LT8253AEUFDM_技术文档

LT8253/LT8253A

40V USB Type-C Power Delivery

Buck-Boost Controller

FEATURES

DESCRIPTION

The LT^®8253/LT8253A are synchronous 4-switch buck-

boost controllers optimized for automotive USB-C power

delivery. The LT8253/53A are fully compliant to the USB

Power Delivery (PD) specification when used in conjunc-

n

Proprietary Low-EMI Buck-Boost Architecture

n

Wide Input Range: 4V to 40V

n

Synchronous Switching: Up to 98% Efficiency

1.5% Output Voltage Regulation

Single Output supports 1 Type-C Port up to 100W

Output Channel Enable Function

Programmable Switching Frequency with External

Synchronization and Spread Spectrum

Over-Current, Over-Voltage, Short-Circuit Protection

Available in 28-Lead Side Solderable QFN Package

AEC-Q100 Qualification in Progress

n

tion with a USB Type-C or PD port controller. The output

voltage slew rate can be controlled through the FB pin.

The LT8253 can deliver up to 100W output power with

98% peak efficiency when running below the AM band.

The LT8253A can deliver up to 60W output power with

95% peak efficiency when running above the AM band.

n

The LT8253/8253A support single buck-boost output for

1 Type-C port with power good flag. Over-current, over-

voltage, and short-circuit protections are also available.

All registered trademarks and trademarks are the property of their respective owners.

APPLICATIONS

n

Automotive USB-C Power Delivery

General Purpose Voltage Regulator

n

TYPICAL APPLICATION

Automotive 60W USB-C Power Delivery Charger (400kHz)

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Rev. 0

1

Document Feedback

For more information www.analog.com

LT8253/LT8253A

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

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V , EN/UVLO............................................................42V

OUT

IN

V

..........................................................................30V

BST1.........................................................................48V

BST2.........................................................................36V

SW1, LSP, LSN.............................................. −6V to 42V

SW2.............................................................. −6V to 30V

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INTV , (BST1-SW1), (BST2-SW2) ............................6V

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CC

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(BST1-LSP), (BST1-LSN) ...........................................6V

FB, VOUTEN, SYNC/SPRD, PGOOD.............................6V

Operating Junction Temperature Range (Notes 2, 3)

LT8253E, LT8253AE .......................... −40°C to 125°C

LT8253J, LT8253AJ........................... −40°C to 150°C

LT8253H, LT8353AH ......................... −40°C to 150°C

Storage Temperature Range .................. −65°C to 150°C

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θ

= 43°C/W, θ = 3.4°C/W

JA

JC

EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

PART

MARKING*

LEAD FREE FINISH

TAPE AND REEL

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT8253EUFDM#PBF

LT8253EUFDM#TRPBF

LT8253JUFDM#TRPBF

LT8253HUFDM#TRPBF

8253

28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 125°C

28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C

28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 125°C

28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C

LT8253JUFDM#PBF

8253

LT8253HUFDM#PBF

LT8253AEUFDM#PBF

LT8253AJUFDM#PBF

LT8253AHUFDM#PBF

AUTOMOTIVE PRODUCTS**

LT8253JUFDM#WPBF

LT8253HUFDM#WPBF

LT8253AJUFDM#WPBF

LT8253AHUFDM#WPBF

8253

LT8253AEUFDM#TRPBF 8253A

LT8253AJUFDM#TRPBF 8253A

LT8253AHUFDM#TRPBF 8253A

LT8253JUFDM#WTRPBF 8253

LT8253HUFDM#WTRPBF 8253

LT8253AJUFDM#WTRPBF 8253A

LT8253AHUFDM#WTRPBF 8253A

28-Lead (4mm x 5mm) Plastic Side Solderable QFN –40°C to 150°C

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by aLabel on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications.

These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact

yourLocal Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for

these models.

Rev. 0

2

For more information www.analog.com

LT8253/LT8253A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, V_EN/UVLO= 1.5V unless otherwise noted.

SYMBOL PARAMETER

Supply

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Operating Voltage Range

Quiescent Current

4

40

V

IN

V

= 0.3V

= 1.5V

1

2.1

2

3

µA

mA

EN/UVLO

V

OUT

Voltage Range

1

25

V

Linear Regulators

INTV Regulation Voltage

I

= 20mA

4.8

5

5.2

V

CC

INTVCC

INTV Current Limit

V

= 4.5V (LT8253)

= 4.5V (LT8253A)

80

110

145

160

190

mA

CC

INTVCC

INTV Undervoltage Lockout Threshold

Falling

3.44

3.54

0.24

2

3.64

V

CC

INTV Undervoltage Lockout Hysteresis

CC

V

REF

V

REF

Regulation Voltage

Current Limit

I

= 100uA

= 1.8V

1.96

2

2.04

3.2

V

VREF

V

REF

2.5

mA

Control Inputs

EN/UVLO Shutdown Threshold

EN/UVLO Enable Threshold

EN/UVLO Enable Hysteresis

EN/UVLO Hysteresis Current

0.3

0.6

1.22

13

1

V

Falling

1.196

1.244

mV

V

= 1.1V

= 1.3V

2

–0.1

2.5

0

3

0.1

µA

EN/UVLO

VOUTEN Threshold

1

1.6

V

Error Amplifier

l

FB Regulation Voltage

0.985

1

1.015

V

FB Voltage Regulation Amplifier g

660

µS

m

Current Comparator

Maximum Current Sense Threshold V

Buck, V = 0.8V

35

50

65

mV

(LSP-LSN)

FB

Boost, V = 0.8V

FB

Fault

FB Short Threshold

FB Short Hysteresis

Falling

0.2

30

8

0.25

50

0.3

70

V

mV

%

Ω

PGOOD Upper Threshold from V

Rising

Falling

10

12

FB

PGOOD Lower Threshold from V

PGOOD Pull-Down Resistance

SS Hard Pull-Down Resistance

SS Pull-Up Current

–12

–10

100

12.5

1.25

1.7

–8

FB

200

V

= 1.1V

Ω

EN/UVLO

= 0.4V, V = 0V

µA

V

FB

SS

SS Pull-Down Current

= 0.1V, V = 2V

SS

SS Fault High Threshold

SS Fault Low Threshold

0.2

V

Oscillator

l

Oscillator Frequency

V

= 0V, RT = 100kΩ (LT8253)

= 0V, RT = 59.0kΩ (LT8253A)

380

1900

400

2000

420

2100

kHz

SYNC/SPRD

SYNC/SPRD Clock SYNC Frequency

(LT8253)

(LT8253A)

150

600

650

2000

kHz

Rev. 0

3

For more information www.analog.com

LT8253/LT8253A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, V_EN/UVLO= 1.5V unless otherwise noted.

SYMBOL PARAMETER

SYNC/SPRD Clock SYNC Threshold

NMOS Drivers

CONDITIONS

MIN

TYP

MAX

UNITS

0.4

1.5

V

TG1, TG2 Gate Driver On-Resistance

V

= 5V

2.6

1.7

Ω

(BST-SW)

Gate Pull-Up

Gate Pull-Down

BG1, BG2 Gate Driver On-Resistance

Gate Pull-Up

= 5V

Ω

INTVCC

3

1.2

Gate Pull-Down

TG Off to BG On Delay Time

BG Off to TG On Delay Time

LT8253

60

25

ns

LT8253A

LT8253

LT8253A

60

25

ns

Note 1. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2. The LT8253E/LT8253AE are guaranteed to meet performance

specifications from 0°C to 125°C operating junction temperature.

Specifications over the −40°C to 125°C operating junction temperature

range are assured by design, characterization and correlation with

statistical process controls. The LT8253J/LT8253AJ and LT8253H/

LT8253AH are guaranteed over the −40°C to 150°C operating junction

temperature range. High junction temperatures degrade operating

lifetimes. Operating lifetime is derated at junction temperatures greater

than 125°C.

Note 3. The LT8253/LT8253A include overtemperature protection that

is intended to protect the device during momentary overload conditions.

Junction temperature will exceed 150°C when overtemperature protection

is active. Continuous operation above the specified absolute maximum

operating junction temperature may impair device reliability.

Rev. 0

4

For more information www.analog.com

LT8253/LT8253A

PIN FUNCTIONS

TG1: Buck Side Top Gate Drive. Drives the gate of buck

side top N-Channel MOSFET with a voltage swing from

SW1 to BST1.

internal 12.5μA pull-up current charging the external SS

capacitor gradually ramps up FB regulation voltage.

FB: Voltage Loop Feedback Input. The FB pin is used for

output voltage regulation and output fault protection.

LSP: Positive Terminal of the Buck Side Inductor Current

Sense Resistor. Ensure accurate current sense with Kelvin

connection.

VC: Error Amplifier Output. The VC pin is used to com-

pensate the control loop with an external RC network.

LSN: Negative Terminal of the Buck Side Inductor Current

Sense Resistor. Ensure accurate current sense with Kelvin

connection.

RT: Switching Frequency Setting. Connect a resistor from

this pin to ground to set the internal oscillator frequency.

SYNC/SPRD: External Clock Frequency Synchronization

or Spread Spectrum. Ground this pin for switching at

internal oscillator frequency. Apply a clock signal for

external frequency synchronization. Tie to INTV_CCfor

spread spectrum frequency modulation.

V : Input Supply. The V pin must be tied to the power

IN

input to determine its operation regions. Locally bypass

this pin to ground with a minimum 0.1μF ceramic

capacitor.

INTV : Internal 5V Linear Regulator Output. The INTV

CC

V_OUT: Output Pin. The V_OUTpin must be tied to the

power output to determine its operation regions. Locally

bypass this pin to ground with a minimum 0.1μF ceramic

capacitor.

linear regulator is supplied from the V_INpin and pow-

ers the internal control circuitry and gate drivers. Locally

bypass this pin to ground with a minimum 4.7µF ceramic

capacitor.

TG2: Boost Side Top Gate Drive. Drives the gate of boost

side top N-Channel MOSFET with a voltage swing from

SW2 to BST2.

EN/UVLO: Enable and Undervoltage Lockout. Force the

pin below 0.3V to shut down the part and force the pin

above 1.23V for normal operation. The 1.22V falling

threshold and 2.5μA pull-down current can be used to

SW2: Boost Side Switch Node.

program V UVLO with hysteresis. If neither function is

IN

BST2: Boost Side Bootstrap Floating Driver Supply. The

used, tie this pin directly to V .

IN

BST2 pin has an integrated bootstrap diode from the

INTV pin and requires an external bootstrap capacitor

TEST: Factory Test. This pin is for factory testing purpose

only and must be directly connected to ground for proper

operation.

CC

to the SW2 pin.

BG2: Boost Side Bottom Gate Drive. Drives the gate of

boost side bottom N-Channel MOSFET with a voltage

VOUTEN: Output Enable. The VOUTEN pin is used to

enable buck-boost switching and deliver output power.

swing from ground to INTV .

CC

BG1: Buck Side Bottom Gate Drive. Drives the gate of

V

: Voltage Reference Output. The V pin provides an

REF

accurate 2V reference capable of supp^Rly^Ei^Fng 1mA current.

Locally bypass this pin to ground with a 0.47μF ceramic

capacitor.

buck side bottom N-Channel MOSFET with a voltage

swing from ground to INTV .

CC

BST1: Buck Side Bootstrap Floating Driver Supply. The

BST1 pin has an integrated bootstrap diode from the

PGOOD: Power Good Open Drain Output. The PGOOD pin

is pulled low when the FB pin is within 10% of its regu-

lation voltage. To function, the pin requires an external

pull-up resistor.

INTV pin and requires an external bootstrap capacitor

CC

to the SW1 pin.

SW1: Buck Side Switch Node.

SS: Soft-Start Timer Setting. The SS pin is used to set

soft-start timer by connecting a capacitor to ground. An

GND (Exposed Pad): Ground. Solder the exposed pad

directly to the ground plane.

Rev. 0

5

For more information www.analog.com

LT8253/LT8253A

BLOCK DIAGRAM

LSN

LSP

V

OUT

IN

INTV

CC

D1

INTV

CC

+

–

5V LDO

2V REF

BST1

TG1

+

–

A1

A3

V

REF

SW1

BUCK

LOGIC

PEAK_BUCK

INTV

CC

RT

BG1

V

OS

OSC

SYNC/SPRD

V

/BST2

OUT

CHARGE

CONTROL

EN/UVLO

V

/BST1

IN

–

+

FB

+

–

FBOV

1.220V

2.5μA

1.1V

BG2

INHIBIT

SWITCH

BOOST

LOGIC

INTV

CC

SW2

TG2

PEAK_BOOST

VOUTEN

+

NC

A4

BST2

V

REF

–

12.5μA

D2

0.25V

FB

+

–

TEST

SHORT

INTV

CC

FAULT

LOGIC

1.1V

FB

+

–

SS

PGOOD

+

–

1.25μA

+

–

FB

EA1

1V

FB

0.9V

V

GND

C

8253A BD

Rev. 0

6

For more information www.analog.com

LT8253/LT8253A

OPERATION

The LT8253/LT8253A are current mode DC/DC controllers

that can regulate output voltage from an input voltage

above, below, or equal to the output voltage. The propri-

etary peak-buck peak-boost current mode control scheme

uses a single current sense resistor and provides smooth

transition between buck region, buck-boost region, and

boost region. Its operation is best understood by referring

to the Block Diagram.

There are total four states: (1) peak-buck current mode

control in buck region, (2) peak-buck current mode con-

trol in buck-boost region, (3) peak-boost current mode

control in buck-boost region, and (4) peak-boost current

mode control in boost region. The following sections

give detailed description for each state with waveforms,

in which the shoot-through protection dead time between

switches A and B, between switches C and D are ignored

for simplification.

Power Switch Control

ꢀ

ꢁꢂꢃ

ꢒꢓ

Figure 1 shows a simplified diagram of how the four

power switches A, B, C, and D are connected to the induc-

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ꢋꢊꢈ

ꢅ

ꢄ

ꢃꢊꢉ

R

ꢑ

ꢆꢔꢓꢆꢔ

ꢆꢇꢈ

ꢆꢇꢉ

tor L, the current sense resistor R

, power input V ,

SENSE

IN

ꢋ

ꢐ

ꢋꢊꢉ

power output V , and ground. The current sense resis-

OUT

tor R

connected to the LSP and LSN pins provides

SENSE

ꢌꢍꢎꢍꢅ ꢏ0ꢈ

inductor current information for both peak current mode

control and reverse current detection in buck region,

buck-boost region, and boost region.

Figure 1. Simplified Diagram of the Power Switches

Rev. 0

7

For more information www.analog.com

LT8253/LT8253A

OPERATION

(1) Peak-Buck in Buck Region (V >> V

)

(2) Peak-Buck in Buck-Boost Region (V ~> V

)

IN

OUT

IN

OUT

When V_INis much higher than V_OUT, the LT8253/LT8253A

use peak-buck current mode control in buck region

(Figure 2). Switch C is always off and switch D is always

on. At the beginning of every cycle, switch A is turned on

and the inductor current ramps up. When the inductor

current hits the peak buck current threshold commanded

by V_Cvoltage at buck current comparator A3 during (A+D)

phase, switch A is turned off and switch B is turned on

for the rest of the cycle. Switches A and B will alternate,

behaving like a typical synchronous buck regulator.

When V_INis slightly higher than V_OUT, the LT8253/

LT8253A use peak-buck current mode control in buck-

boost region (Figure 3). Switch C is always turned on for

the beginning preset cycle and switch D is always turned

on for the remaining cycle. At the beginning of every

cycle, switches A and C are turned on and the inductor

current ramps up. After preset cycle, switch C is turned off

and switch D is turned on, and the inductor keeps ramping

up. When the inductor current hits the peak buck current

threshold commanded by V voltage at buck current com-

C

parator A3 during (A+D) phase, switch A is turned off and

switch B is turned on for the rest of the cycle.

ꢅ

ꢆ

ꢀ

ꢁ

ꢇ

ꢈ

ꢀ00ꢁ ꢂꢃꢃ

ꢀ00ꢁ ꢂꢄ

ꢂ

ꢃ

ꢉ

ꢊ

ꢆꢋꢈ

ꢅꢋꢈ

ꢄ

ꢅ

ꢌꢍꢎꢏꢅ ꢃ0ꢍ

ꢀꢆꢃ

ꢀꢆꢂ

ꢁꢆꢃ

Figure 2. Peak-Buck in Buck Region (V_IN>> V_OUT

)

ꢇꢈꢉꢊꢀ ꢋ0ꢊ

Figure 3. Peak-Buck in Buck-Boost Region (V_IN~> V_OUT

)

Rev. 0

8

For more information www.analog.com

LT8253/LT8253A

OPERATION

(3) Peak-Boost in Buck-Boost Region (V <~ V

)

(4) Peak-Boost in Boost Region (V << V

)

IN

OUT

IN

OUT

When V_INis slightly lower than V_OUT, the LT8253/

LT8253A use peak-boost current mode control in buck-

boost region (Figure 4). Switch A is always turned on

for the beginning preset cycle and switch B is always

turned on for the remaining cycle. At the beginning of

every cycle, switches A and C are turned on and the induc-

tor current ramps up. When the inductor current hits the

When V is much lower than V , the LT8253/LT8253A

IN OUT

use peak-boost current mode control in boost region

(Figure 5). Switch A is always on and switch B is always

off. At the beginning of every cycle, switch C is turned

on and the inductor current ramps up. When the induc-

tor current hits the peak boost current threshold com-

manded by V_Cvoltage at boost current comparator A4

during (A+C) phase, switch C is turned off and switch D

is turned on for the rest of the cycle. Switches C and D

will alternate, behaving like a typical synchronous boost

regulator.

peak boost current threshold commanded by V voltage at

C

boost current comparator A4 during (A+C) phase, switch

C is turned off and switch D is turned on for the rest of the

cycle. After preset cycle, switch A is turned off and switch

B is turned on for the rest of the cycle.

ꢀ

ꢁ

ꢃ00ꢄ ꢅꢆ

ꢃ00ꢄ ꢅꢇꢇ

ꢀ

ꢁ

ꢂ

ꢈ

ꢂ

ꢃ

ꢉ

ꢊ

ꢀꢆꢃ

ꢄ

ꢅ

ꢀꢋꢂ

ꢀꢋꢈ

ꢀꢋꢂ

ꢀꢋꢈ

ꢀꢆꢂ

ꢌꢍꢎꢏꢀ ꢇ0ꢎ

ꢁꢆꢃ

ꢇꢈꢉꢊꢀ ꢋ0ꢌ

Figure 5. Peak-Boost in Boost Region (V_IN<< V_OUT

)

Figure 4. Peak-Boost in Buck-Boost Region (V_IN<~ V_OUT

)

Rev. 0

9

For more information www.analog.com

LT8253/LT8253A

OPERATION

Main Control Loop

Shutdown and Power-On-Reset

The LT8253/LT8253A are fixed frequency current mode

controllers. The inductor current is sensed through the

inductor sense resistor between the LSP and LSN pins.

The current sense voltage is gained up by amplifier A1

and added to a slope compensation ramp signal from the

internal oscillator. The summing signal is then fed into the

positive terminals of the buck current comparator A3 and

boost current comparator A4. The negative terminals of

The LT8253/LT8253A enter shutdown mode and drain

less than 2µA quiescent current when the EN/UVLO pin

is below its shutdown threshold (0.3V minimum). Once

the EN/UVLO pin is above its shutdown threshold (1V

maximum), the LT8253/LT8253A wake up startup cir-

cuitry, generate bandgap reference, and power up the

internal INTV LDO. The INTV LDO supplies the inter-

CC

nal control circuitry and gate drivers. Then the LT8253/

LT8253A enter undervoltage lockout (UVLO) mode with

a hysteresis current (2.5µA typical) pulled into the EN/

UVLO pin. When the INTV_CCpin is charged above its

rising UVLO threshold (3.78V typical), the EN/UVLO pin

passes its rising enable threshold (1.233V typical), and

the junction temperature is less than its thermal shutdown

(165°C typical), the LT8253/LT8253A enter enable mode,

in which the EN/UVLO hysteresis current is turned off

A3 and A4 are controlled by the voltage on the V pin,

C

which is the output of error amplifier EA1.

Depending on the state of the peak-buck peak-boost cur-

rent mode control, either the buck logic or the boost logic

is controlling the four power switches so that the FB volt-

age is regulated to 1V.

Light Load Current Operation

and the voltage reference V is being charged up from

REF

At light load, the LT8253/LT8253A typically run at discon-

tinuous conduction mode, to maintain the regulation and

improve the efficiency.

ground. From the time of entering enable mode to the time

of V passing its rising UVLO threshold (1.89V typical),

REF

the LT8253/LT8253A are going through a power-on-reset

(POR), waking up the entire internal control circuitry and

settling to the right initial conditions. After the POR, the

LT8253/LT8253A start switching.

Rev. 0

10

For more information www.analog.com

LT8253/LT8253A

OPERATION

Start-Up and Fault Protection

During the UP/RUN state, the switching is enabled and

the start-up of the output voltage V

is controlled by

OUT

Figure 6 shows the start-up and fault sequence for the

LT8253/LT8253A. During the POR state, the SS pin is

hard pulled down with a 100Ω to ground. In a pre-biased

condition, the SS pin has to be pulled below 0.2V to enter

the INIT state, where the LT8253/LT8253A wait 10µs so

that the SS pin can be fully discharged to ground. After

the 10µs, the LT8253/LT8253A enter the UP/PRE state

when the VOUTEN signal goes high.

the voltage on the SS pin. When the SS pin voltage is less

than 1V, the LT8253/LT8253A regulate the FB pin voltage

to the SS pin voltage instead of the 1V reference. This

allows the SS pin to program soft-start by connecting an

external capacitor from the SS pin to GND. The internal

12.5µA pull-up current charges up the capacitor, creating

a voltage ramp on the SS pin. As the SS pin voltage rises

linearly from 0.25V to 1V and above, the output voltage

During the UP/PRE state, the SS pin is charged up by a

12.5µA pull-up current while the switching is disabled.

Once the SS pin is charged above 0.25V, the LT8253/

LT8253A enter the UP/TRY state. After 10µs in the UP/

TRY state, the LT8253/LT8253A enter the UP/RUN state.

V

rises smoothly to its final regulation voltage.

OUT

Once the SS pin is charged above 1.75V, the LT8253/

LT8253A enter the OK/RUN state, where the output

short detection is activated. The output short means V

< 0.25V. When the output short happens, the LT825^F3^B/

LT8253A enter the FAULT/RUN state, where a 1.25µA pull-

down current slowly discharges the SS pin with the other

conditions the same as the OK/RUN state. Once the SS pin

is discharged below 1.7V, the LT8253/LT8253A enter the

DOWN/STOP state, where the switching is disabled and

the short detection is deactivated with the previous fault

latched. Once the SS pin is discharged below 0.2V and

the VOUTEN signal is still high, the LT8253/LT8253A go

back to the UP/RUN state.

ꢓꢔR ꢕ ꢖꢗ

POR

INIT

ꢀ ꢁꢁ ꢂꢃꢄꢅ ꢆꢇꢈꢈ ꢅꢉꢊꢋ

ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ

ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ

ꢀ ꢁꢁ ꢂꢃꢄꢅ ꢆꢇꢈꢈ ꢅꢉꢊꢋ

ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ

ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ

ꢁꢁ ꢘ 0.ꢙꢚ

ꢁꢁ ꢣ 0.ꢙꢜꢚ

ꢁꢁ ꢣ ꢛ.ꢤꢜꢚ

ꢁꢁ ꢘ ꢛ.ꢤꢚ

ꢟꢃꢌꢍ ꢛ0ꢝꢐ ꢃꢋꢅ

ꢚꢔꢠꢡꢢꢒ ꢕ ꢖꢗ

UP/TRY

UP/PRE

ꢀ ꢁꢁ ꢛꢙ.ꢜꢝꢞ ꢆꢇꢈꢈ ꢇꢆ

ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ

ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ

ꢀ ꢁꢁ ꢛꢙ.ꢜꢝꢞ ꢆꢇꢈꢈ ꢇꢆ

ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ

ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ

In an output short condition, the LT8253/LT8253A can

be set to hiccup, latch-off, or keep-running fault pro-

tection mode with a resistor between the SS and V

REF

ꢟꢃꢌꢍ ꢛ0ꢝꢐ

pins. Without any resistor, the LT8253/LT8253A will

hiccup between 0.2V and 1.75V and go around the UP/

RUN, OK/RUN, FAULT/RUN, and DOWN/STOP states

until the fault condition is cleared. With a 499kΩ resis-

tor, the LT8253/LT8253A will latch off until the EN/UVLO

is toggled. With a 100kΩ resistor, the LT8253/LT8253A

will keep running regardless of the fault.The front page

shows a typical LT8253/LT8253A application circuit. This

Applications Information section serves as a guideline of

selecting external components for typical applications. The

examples and equations in this section assume continuous

conduction mode unless otherwise specified.

UP/RUN

OK/RUN

ꢀ ꢁꢁ ꢛꢙ.ꢜꢝꢞ ꢆꢇꢈꢈ ꢇꢆ

ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ eꢋꢃꢑꢈeꢅ

ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ

ꢀ ꢁꢁ ꢛꢙ.ꢜꢝꢞ ꢆꢇꢈꢈ ꢇꢆ

ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ eꢋꢃꢑꢈeꢅ

ꢀ ꢁꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ

ꢁꢁ ꢘ 0.ꢙꢚ ꢃꢋꢅ

ꢚꢔꢠꢡꢢꢒ ꢕ ꢖꢗ

ꢁꢖꢔRꢡ

DOWN/STOP

FAULT/RUN

ꢀ ꢁꢁ ꢛ.ꢙꢜꢝꢞ ꢆꢇꢈꢈ ꢅꢉꢊꢋ

ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ

ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ

ꢀ ꢁꢁ ꢛ.ꢙꢜꢝꢞ ꢆꢇꢈꢈ ꢅꢉꢊꢋ

ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ eꢋꢃꢑꢈeꢅ

ꢀ ꢁꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ

ꢥꢙꢜꢦꢞ ꢧ0ꢨ

Figure 6. Start-Up and Fault Sequence

Switching Frequency Selection

The LT8253/LT8253A use a constant frequency control

scheme, 150kHz-650kHz for LT8253 and 600kHz-2MHz

Rev. 0

11

For more information www.analog.com

LT8253/LT8253A

APPLICATIONS INFORMATION

for LT8253A. Selection of the switching frequency is a

tradeoff between efficiency and component size. Low

frequency operation improves efficiency by reducing

MOSFET switching losses, but requires larger inductor

and capacitor values. For high power applications, con-

sider operating at lower frequencies to minimize MOSFET

heating from switching losses. For low power applica-

tions, consider operating at higher frequencies to mini-

mize the total solution size.

Spread Spectrum Frequency Modulation

Switching regulators can be particularly troublesome for

applications where electromagnetic interference (EMI) is

a concern. To improve the EMI performance, the LT8253/

LT8253A implement a triangle spread spectrum frequency

modulation scheme. With the SYNC/SPRD pin tied to

INTV_CC, the LT8253 spreads its switching frequency

15% around and the LT8253A spreads its switching

frequency 25% above the internal oscillator frequency.

In addition, the specific application also plays an impor-

tant role in switching frequency selection. In a noise-sen-

sitive system, the switching frequency is usually selected

to keep the switching noise out of a sensitive frequency

band.

Frequency Synchronization

The LT8253/LT8253A switching frequency can be syn-

chronized to an external clock using the SYNC/SPRD pin.

Driving the SYNC/SPRD with a 50% duty cycle waveform

is always a good choice, otherwise maintain the duty cycle

between 10% and 90%.

Switching Frequency Setting

The switching frequency of the LT8253/LT8253A can be

set by the internal oscillator. With the SYNC/SPRD pin

pulled to ground, the switching frequency is set by a resis-

tor from the RT pin to ground. Table 1 and Table 2 show

Inductor Selection

The switching frequency and inductor selection are inter-

related in that higher switching frequencies allow the use

of smaller inductor and capacitor values. The inductor

value has a direct effect on ripple current. The highest cur-

R resistor values of common switching frequencies for

T

LT8253 and LT8253A, respectively.

rent ripple ∆I % happens in the buck region at V

,

L

IN(MAX)

Table 1. LT8253 Switching Frequency vs R_TValue (1% Resistor)

and the lowest current ripple ∆I % happens in the boost

L

f

(kHz)

R (k)

T

OSC

region at V

. For any given ripple allowance set by

IN(MIN)

150

309

226

140

100

75

customers, the minimum inductance can be calculated as:

200

300

400

500

600

650

V

• V

� V

IN(MAX)

OUT

(

)

OUT

L

>

BUCK

f •I

• � I % • V

L

IN(MAX)

OUT(MAX)

2

59

V

• V

(

� V

IN(MIN)

OUT

)

IN(MIN)

>

51.1

BOOST

2

f •I

• � I % • V

L

OUT

OUT(MAX)

Table 2. LT8253A Switching Frequency vs R_TValue (1%

Resistor)

where:

� I % =

f

(MHz)

R (k)

T

OSC

� I

L

0.6

267

191

147

118

97.6

82.5

66.5

59.0

L

I

L(AVG)

0.8

1.0

1.2

1.4

1.6

1.8

2.0

f is switching frequency

V

is minimum input voltage

is maximum input voltage

IN(MIN)

IN(MAX)

is output voltage

OUT

I

is maximum output current

OUT(MAX)

Rev. 0

12

For more information www.analog.com

LT8253/LT8253A

APPLICATIONS INFORMATION

Slope compensation provides stability in constant fre-

quency current mode control by preventing subharmonic

oscillations at certain duty cycles. The minimum induc-

tance required for stability when duty cycles are larger

than 50% can be calculated as:

The maximum current sense R

in boost region is:

SENSE

2 • 50mV • V

IN(MIN)

R

=

SENSE(BOOST)

2 •I

• V

+ � I

• V

IN(MIN)

L(BOOST)

OUT(MAX)

OUT

10 • V

• R

SENSE

The maximum current sense R

in buck region is

OUT

SENSE

L >

f

2 • 50mV

R

=

SENSE(BUCK)

2 •I

+ � I

For high efficiency, choose an inductor with low core loss,

such as ferrite. Also, the inductor should have low DC

resistance to reduce the I R losses, and must be able to

handle the peak inductor current without saturating. To

minimize radiated noise, use a shielded inductor.

OUT(MAX)

L(BUCK)

2

The final R

SENSE

value should be lower than the calculated

R

in ^Sb^Eo^Nt^Sh^Ebuck and boost regions. A 20% to 30%

margin is usually recommended. Always choose a low

ESL current sense resistor.

R

Selection and Maximum Output Current

SENSE

Power MOSFET Selection

R

is chosen based on the required output current.

SENSE

The LT8253/LT8253A require four external N-channel

power MOSFETs, two for the top switches (switches A

and D shown in Figure 1) and two for the bottom switches

(switches B and C shown in Figure 1). Important param-

eters for the power MOSFETs are the breakdown volt-

The duty cycle independent maximum current sense

thresholds (50mV in peak-buck and 50mV in peak-boost)

set the maximum inductor peak current in buck region,

buck-boost region, and boost region.

In boost region, the lowest maximum average load cur-

age V

, threshold voltage V

, on-resistance

BR(DSS)

GS(TH)

rent happens at V

and can be calculated as:

IN(MIN)

R_DS(ON), reverse transfer capacitance C_RSSand maximum

current I

.

�

DS(MAX)

V

� I

50mV

IN(MIN)

L(BOOST)

I

=

�

•

�

÷

�

OUT(MAX _BOOST)

To achieve 2MHz operation, the power MOSFET selec

-

R

2

V

SENSE

OUT

tion is critical. With typical 25ns shoot-through protection

deadtime, high performance power MOSFETs with low Q

where ∆I

is peak-to-peak inductor ripple current

g

L(BOOST)

and low R

must be used.

in boost region and can be calculated as:

DS(ON)

Since the gate drive voltage is set by the 5V INTV_CCsupply,

logic-level threshold MOSFETs must be used in LT8253/

LT8253A applications. Switching four MOSFETs at higher

frequency like 2MHz, the substantial gate charge current

V

• V

� V

IN(MIN)

OUT

(

)

IN(MIN)

� I

=

L(BOOST)

f • L • V

OUT

In buck region, the lowest maximum average load current

from INTV can be estimated as:

CC

happens at V

and can be calculated as:

IN(MAX)

I

= f • Q + Q + Q + Q

(

)

gA

gB

gD

INTVCC

gC

�

÷

�

� I

50mV

L(BUCK)

I

=

�

OUT(MAX _BUCK)

R

2

where:

SENSE

f is the switching frequency

where ∆I_L(BUCK)is peak-to-peak inductor ripple current in

buck region and can be calculated as:

Q_gA, Q_gB, Q_gC, Q_gDare the total gate charges of

MOSFETs A, B, C, D

V

• V

(

� V

)

IN(MAX)

OUT

� I

=

Make sure the total required INTV_CCcurrent does not

exceed the INTV_CCcurrent limit in the datasheet. Typically,

MOSFETs with less than 10nC Q are recommended.

L(BUCK)

f • L • V

IN(MAX)

g

Rev. 0

13

For more information www.analog.com

LT8253/LT8253A

APPLICATIONS INFORMATION

The LT8253/LT8253A use the V /V

ratio to transition

IN OUT

V

� V • V

(

)

2

IN

OUT

P

=

•I

• �

T

OUT(MAX)

between modes and regions. Bigger IR drop in the power

path caused by improper MOSFET and inductor selection

may prevent the LT8253/LT8253A from smooth transi-

tion. To ensure smooth transitions between buck, buck-

C(BOOST)

2

V

IN

I

OUT(MAX)

3

• R

+ k • V

•

• C

• f

RSS

DS(ON)

OUT

V

IN

boost, and boost modes of operation, choose low R

MOSFETs and low DCR inductor to satisfy:

DS(ON)

2.0

0.025 • V

OUT

1.5

1.0

0.5

I

�

OUT(MAX)

R

+ R + R

+ R

L

SENSE

A,B

C,D

where:

R

is the maximum R

of MOSFETs A or B at 25°C

of MOSFETs C or D at 25°C

A,B

DS(ON)

R

C,D

DS(ON)

0

50

100

–50

150

0

R is the maximum DCR resistor of inductor at 25°C

L

JUNCTION TEMPERATURE (°C)

8253A F07

The R_DS(ON)and DCR increase at higher junction

temperatures and the process variation have been

included in the calculation above.

Figure 7. Normalized R_DS(ON)vs Temperature

where C

is usually specified by the MOSFET manufac-

RSS

In order to select the power MOSFETs, the power dis-

sipated by the device must be known. For switch A, the

maximum power dissipation happens in boost region,

when it remains on all the time. Its maximum power dis-

sipation at maximum output current is given by:

turers. The constant k, which accounts for the loss caused

by reverse recovery current, is inversely proportional to

the gate drive current and has an empirical value of 1.7.

For switch D, the maximum power dissipation happens in

boost region, when its duty cycle is higher than 50%. Its

maximum power dissipation at maximum output current

is given by:

2

�

÷

�

I

• V

OUT

OUT(MAX)

P

=

• � • R

T

DS(ON)

�

A(BOOST)

V

IN

V

2

where ρ_Tis a normalization factor (unity at 25°C) ac-

counting for the significant variation in on-resistance with

temperature, typically 0.4%/°C as shown in Figure 7. For

a maximum junction temperature of 125°C, using a value

OUT

P

=

•I

• � • R

T

OUT(MAX) DS(ON)

D(BOOST)

V

IN

For the same output voltage and current, switch A has the

highest power dissipation and switch B has the lowest

power dissipation unless a short occurs at the output.

of ρ = 1.5 is reasonable.

T

Switch B operates in buck region as the synchronous

rectifier. Its power dissipation at maximum output cur-

rent is given by:

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

V � V

2

IN

OUT

P

=

•I

• � • R

T

OUT(MAX) DS(ON)

B(BUCK)

T = T + P • R

TH(JA)

J

A

V

IN

The junction-to-ambient thermal resistance R_TH(JA)

Switch C operates in boost region as the control switch.

Its power dissipation at maximum current is given by:

includes the junction-to-case thermal resistance R

TH(JC)

and the case-to-ambient thermal resistance R

. This

TH(CA)

value of T can then be compared to the original, assumed

value use^Jd in the iterative calculation process.

Rev. 0

14

For more information www.analog.com

LT8253/LT8253A

APPLICATIONS INFORMATION

C and C

Selection

steady state ripple due to charging and discharging the

bulk capacitance is given by:

IN

OUT

Input and output capacitance is necessary to suppress

voltage ripple caused by discontinuous current moving

in and out the regulator. A parallel combination of capaci-

tors is typically used to achieve high capacitance and low

equivalent series resistance (ESR). Dry tantalum, special

polymer, aluminum electrolytic and ceramic capacitors are

all available in surface mount packages. Capacitors with

low ESR and high ripple current ratings, such as OS-CON

and POSCAP are also available.

I

• V

� V

IN(MIN)

OUT

(

)

OUT(MAX)

� V

=

CAP(BOOST)

C

• V

• f

OUT

�

V

OUT

�

÷

V

• 1�

OUT

V

IN(MAX)

�

� V

=

CAP(BUCK)

2

8 • L • f • C

OUT

The maximum steady ripple due to the voltage drop

across the ESR is given by:

Ceramic capacitors should be placed near the regulator

input and output to suppress high frequency switching

spikes. Ceramic capacitors, of at least 1µF, should also

V

•I

OUT OUT(MAX)

� V

=

• ESR

ESR(BOOST)

be placed from V to GND and V

to GND as close

V

to the LT8253/LT^I8^N253A pins as p^Oo^Us^Tsible. Due to their

excellent low ESR characteristics, ceramic capacitors can

significantly reduce input ripple voltage and help reduce

power loss in the higher ESR bulk capacitors. X5R or X7R

dielectrics are preferred, as these materials retain their

capacitance over wide voltage and temperature ranges.

Many ceramic capacitors, particularly 0805 or 0603 case

sizes, have greatly reduced capacitance at the desired

operating voltage.

IN(MIN)

�

V

OUT

�

÷

V

• 1�

OUT

V

IN(MAX)

�

� V

=

• ESR

ESR(BUCK)

L • f

INTV Regulator

CC

An internal P-channel low dropout regulator produces

5V at the INTV pin from the V supply pin. The INTV

CC

IN

CC

powers internal circuitry and gate drivers in the LT8253/

LT8253A. The INTV_CCregulator must be bypassed to

ground with a minimum of 4.7µF ceramic capacitor. Good

local bypass is necessary to supply the high transient

current required by MOSFET gate drivers.

Input Capacitance C_IN: Discontinuous input current is

highest in the buck region due to the switch A toggling

on and off. Make sure that the C capacitor network has

IN

low enough ESR and is sized to handle the maximum RMS

current. In buck region, the input RMS current is given by:

Higher input voltage applications with large MOSFETs

being driven at higher switching frequencies may cause

the maximum junction temperature rating for the LT8253/

LT8253A to be exceeded. The system supply current is

normally dominated by the gate charge current. Additional

V

IN

OUT

I

� I

•

� 1

RMS

OUT(MAX)

V

OUT

IN

The formula has a maximum at V = 2V , where I

RMS

IN

OUT

= I

/2. This simple worst-case condition is com-

OUT(MAX)

external loading of the INTV also needs to be taken into

CC

monly used for design because even significant deviations

do not offer much relief.

account for the power dissipation calculation. The total

LT8253/LT8253A power dissipation in this case is V

•

IN

I_INTVCC, and overall efficiency is lowered. The junction

Output Capacitance C : Discontinuous current shifts

OUT

temperature can be estimated by using the equation:

from the input to the output in the boost region. Make sure

that the C

capacitor network is capable of reducing the

OUT

T = T + P • θ

JA

J

A

D

output voltage ripple. The effects of ESR and the bulk

capacitance must be considered when choosing the right

capacitor for a given output ripple voltage. The maximum

where θ (in °C/W) is the package thermal resistance.

JA

Rev. 0

15

For more information www.analog.com

LT8253/LT8253A

APPLICATIONS INFORMATION

To prevent maximum junction temperature from being

Programming Output Voltage and Thresholds

exceeded, the input supply current must be checked oper-

The LT8253/LT8253A have a voltage feedback pin FB

that can set the output voltage with R3 and R4 (Figure 9)

according to the following equation:

ating in continuous mode at maximum V .

IN

Top Gate MOSFET Driver Supply (C

, C

BST1 BST2

)

R3+ R4

The top MOSFET drivers, TG1 and TG2, are driven between

their respective SW and BST pin voltages. The boost volt-

ages are biased from floating bootstrap capacitors C

V

= 1V •

OUT

R4

BST1

In addition, the FB pin also sets output overvoltage

threshold, output power good thresholds, and output

short threshold. For an application with small output

capacitors, the output voltage may overshoot a lot during

load transient event. Once the FB pin hits its overvoltage

and C

, which are normally recharged through inter-

BST2

nal bootstrap diodes when the respective top MOSFET

is turned off. Both capacitors are charged to the same

voltage as the INTV voltage. The bootstrap capacitors

CC

C

and C

, need to store about 100 times the gate

BST1

charge requ^Bir^Se^Td²by the top switches A and D. In most

applications, a 0.1µF to 0.47µF, X5R or X7R dielectric

capacitor is adequate.

ꢈ

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ꢌꢎ

Rꢋ

Programming V UVLO

IN

ꢂꢅꢄꢃꢇ ꢌ0ꢍ

A resistor divider from V to the EN/UVLO pin imple-

IN

Figure 9. Feedback Resistor Connection

ments V_INundervoltage lockout (UVLO). The EN/UVLO

enable falling threshold is set at 1.220V with 13mV hyster-

esis. In addition, the EN/UVLO pin sinks 2.5µA when the

voltage on the pin is below 1.220V. This current provides

user programmable hysteresis based on the value of R1.

The programmable UVLO thresholds are:

threshold 1.1V, the LT8253/LT8253A stop switching by

turning off TG1, BG1, TG2, and BG2. The output overvolt-

age threshold can be set as:

R3+ R4

V

= 1.1V •

R1+ R2

OUT(OVP)

R4

V

= 1.233V •

= 1.220V •

+ 2.5µA • R1

IN(UVLO+)

R2

R1+ R2

R2

To provide the output short-circuit detection and protec-

tion, the output short falling threshold can be set as:

V

IN(UVLO� )

R3+ R4

V

= 0.25V •

Figure 8 shows the implementation of external shut-down

control while still using the UVLO function. The NMOS

grounds the EN/UVLO pin when turned on, and puts the

LT8253/LT8253A in shutdown with quiescent current less

than 2µA.

OUT(SHORT)

R4

Power GOOD (PGOOD) Pin

The LT8253/LT8253A provide an open-drain status pin,

ꢈ

ꢉꢊ

PGOOD, which is pulled low when V is within 10% of

FB

the 1.00V regulation voltage. The PGOOD pin is allowed

Rꢋ

to be pulled up by an external resistor to INTV or an

CC

ꢓꢊꢆꢔꢈꢀꢍ

external voltage source of up to 6V.

ꢀꢁꢂꢆꢌꢁꢍꢎ

ꢏꢍꢊꢁRꢍꢀ

ꢐꢍꢎꢁꢉꢍꢊꢇꢀꢑ

ꢀꢁꢂꢃꢄꢅꢆꢀꢁꢂꢃꢄꢅꢇ

Rꢃ

ꢕꢊꢖ

ꢂꢃꢄꢅꢇ ꢒ0ꢂ

Figure 8. V_INUndervoltage Lockout (UVLO)

Rev. 0

16

For more information www.analog.com

LT8253/LT8253A

APPLICATIONS INFORMATION

Soft-Start and Short-Circuit Protection

Loop Compensation

As shown in Figure 6 and explained in the Operation sec-

tion, the SS pin can be used to program the output volt-

age soft-start by connecting an external capacitor from

the SS pin to ground. The internal 12.5µA pull-up current

charges up the capacitor, creating a voltage ramp on the

SS pin. As the SS pin voltage rises linearly from 0.25V

to 1V (and beyond), the output voltage rises smoothly

into its final voltage regulation. The soft-start time can

be calculated as:

The LT8253/LT8253A use an internal transconductance

error amplifier, the output of which, V , compensates the

C

control loop. The external inductor, output capacitor, and

the compensation resistor and capacitor determine the

loop stability.

The inductor and output capacitor are chosen based on

performance, size and cost. The compensation resistor

and capacitor on the V pin are set to optimize control

C

loop response and stability.

C

SS

t

= 1V •

SS

Efficiency Considerations

12.5µA

The power efficiency of a switching regulator is equal

to the output power divided by the input power times

100%. It is often useful to analyze individual losses

to determine what is limiting the efficiency and which

change would produce the most improvement. Although

all dissipative elements in circuits produce losses, four

main sources account for most of the losses in LT8253/

LT8253A circuits:

Make sure the C is at least five to ten times larger than

SS

the compensation capacitor on the V pin for a well-con-

C

trolled output voltage soft-start.

The SS pin is also used as a fault timer. Once an output

short-circuit fault is detected, a 1.25µA pull-down current

source is activated. Using a single resistor from the SS

pin to the V

pin, the LT8253/LT8253A can be set to

REF

three different fault protection modes: hiccup (no resis-

tor), latch-off (499k), and keep-running (100k).

1. DC I²R losses. These arise from the resistances of the

MOSFETs, sensing resistor, inductor and PC board

traces and cause the efficiency to drop at high output

currents.

With a 100k resistor in keep-running mode, the LT8253/

LT8253A continue switching normally and regulates the

current into ground. With a 499k resistor in latch-off

mode, the LT8253/LT8253A stop switching until the EN/

UVLO pin is pulled low and high to restart. With no resis-

tor in hiccup mode, the LT8253/LT8253A enter low duty

cycle auto-retry operation. The 1.25µA pull-down current

discharges the SS pin to 0.2V and then 12.5µA pull-up

current charges the SS pin up. If the output short-circuit

condition has not been removed when the SS pin reaches

1.75V, the 1.25µA pull-down current turns on again, ini-

tiating a new hiccup cycle. This will continue until the

fault is removed. Once the output short-circuit condition

is removed, the output will have a smooth short-circuit

recovery due to soft-start.

2. Transition loss. This loss arises from the brief amount

of time switch A or switch C spends in the saturated

region during switch node transitions. It depends

upon the input voltage, load current, driver strength

and MOSFET capacitance, among other factors.

3. INTV_CCcurrent. This is the sum of the MOSFET driver

and control currents.

4. C and C

loss. The input capacitor has the diffi-

IN

OUT

cult job of filtering the large RMS input current to the

regulator in buck region. The output capacitor has the

difficult job of filtering the large RMS output current in

boost region. Both C and C

are required to have

IN

OUT

2

low ESR to minimize the AC I R loss and sufficient

capacitance to prevent the RMS current from causing

additional upstream losses in fuses or batteries.

Rev. 0

17

For more information www.analog.com

LT8253/LT8253A

APPLICATIONS INFORMATION

n

5. Other losses. Schottky diode D and D are respon-

Place switch A and switch C as close to the controller

as possible, keeping the PGND, BG and SW traces

short.

B

D

sible for conduction losses during dead time and light

load conduction periods. Inductor core loss occurs

predominately at light loads. Switch A causes reverse

recovery current loss in buck region, and switch C

causes reverse recovery current loss in boost region.

Keep the high dV/dT SW1, SW2, BST1, BST2, TG1

and TG2 nodes away from sensitive small-signal

nodes.

When making adjustments to improve efficiency, the

input current is the best indicator of changes in effi-

ciency. If you make a change and the input current

decreases, then the efficiency has increased. If there

is no change in the input current, then there is no

change in efficiency.

The path formed by switch A, switch B, D and the

B

C capacitor should have short leads and PCB trace

IN

lengths. The path formed by switch C, switch D, D

D

and the C

capacitor also should have short leads

OUT

and PCB trace lengths.

n

The output capacitor (–) terminals should be con-

nected as close as possible to the (–) terminals of the

input capacitor.

PC Board Layout Checklist

The basic PC board layout requires a dedicated ground

plane layer. Also, for high current, a multilayer board pro-

vides heat sinking for power components.

Connect the top driver bootstrap capacitor C_BST1

closely to the BST1 and SW1 pins. Connect the top

driver bootstrap capacitor C

and SW2 pins.

closely to the BST2

BST2

n

The ground plane layer should not have any traces

and it should be as close as possible to the layer with

power MOSFETs.

n

Connect the input capacitors C and output capaci-

IN

tors C_OUTclosely to the power MOSFETs. These

n

Place C , switch A, switch B and D in one compact

IN

B

capacitors carry the MOSFET AC current.

area. Place C , switch C, switch D and D in one

OUT

D

compact area.

Route LSP and LSN traces together with minimum

PCB trace spacing. Avoid sense lines pass through

noisy areas, such as switch nodes. The filter capacitor

between LSP and LSN should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

n

Use immediate vias to connect the components to the

ground plane. Use several large vias for each power

component.

n

Use planes for V and V

to maintain good voltage

connections at the R

resistor. Low ESL sense

IN

OUT

SENSE

filtering and to keep power losses low.

resistor is recommended.

Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise

of power components. Connect the copper areas to

n

Connect the V pin compensation network close to

C

the IC, between V_Cand the signal ground. The capaci-

tor helps to filter the effects of PCB noise and output

voltage ripple voltage from the compensation loop.

any DC net (V or GND).

IN

n

Separate the signal and power grounds. All small-

signal components should return to the exposed GND

pad from the bottom, which is then tied to the power

GND close to the sources of switch B and switch C.

n

Connect the INTV bypass capacitor, C

, close

CC

INTVCC

to the IC, between the INTV and the power ground.

CC

This capacitor carries the MOSFET drivers’ current

peaks.

Rev. 0

18

For more information www.analog.com

LT8253/LT8253A

PACKAGE DESCRIPTION

UFDM Package

28-Lead Plastic Side Wettable QFN (4mm × 5mm)

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R ꢤ 0.ꢃ0 ꢌR 0.ꢕꢉ

R ꢤ 0.0ꢉ

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0.ꢃ0ꢕ Rꢇꢊ

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0.ꢉ0 ꢘꢄꢒ

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Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

19

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LT8253/LT8253A

TYPICAL APPLICATION

Automotive 45W USB-C Power Delivery Charger (2MHz)

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Rev. 0

09/20

www.analog.com

 ANALOG DEVICES, INC. 2020

20

For more information www.analog.com


型号：	LT8253AEUFDM
厂家：	ADI
描述：	40V USB Type-C Power Delivery Buck-Boost Controller
文件：	总20页 (文件大小：906K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT8253AEUFDM [ADI]

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