LTC2635HMSE-LZ10#TRPBF

LTC2635

2

Quad 12-/10-/8-Bit I C V

OUT

DACs with 10ppm/°C Reference

FEATURES

DESCRIPTION

The LTC^®2635 is a family of quad 12-, 10-, and 8-bit

voltage-output DACs with an integrated, high-accuracy,

low-drift reference in a 16-pin QFN or a 10-lead MSOP

package. It has rail-to-rail output buffers and is guaran-

teed monotonic. The LTC2635-L has a full-scale output

of 2.5V, and operates from a single 2.7V to 5.5V supply.

The LTC2635-H has a full-scale output of 4.096V, and

operates from a 4.5V to 5.5V supply. Each DAC can also

operate with an external reference, which sets the full-

scale output to the external reference voltage.

n

Integrated Precision Reference

2.5V Full-Scale 10ppm/°C (LTC2635-L)

4.096V Full-Scale 10ppm/°C (LTC2635-H)

n

Maximum INL Error: 2.5 LSꢀ (LTC2635-12)

n

Power-On-Reset to Zero-Scale/Mid-Scale/Hi-Z

n

Low Noise: 0.75mV 0.1Hz to 200kHz

P-P

n

Guaranteed Monotonic Over –40°C to 125°C

Automotive Temperature Range

n

Selectable Internal or External Reference

2.7V to 5.5V Supply Range (LTC2635-L)

Ultralow Crosstalk ꢀetween DACs (3nV•s)

Low Power: 0.6mA at 3V

These DACs communicate via a 2-wire I²C-compatible

serial interface. The LTC2635 operates in both the stan-

dard mode (clock rate of 100kHz) and the fast mode (clock

rate of 400kHz). The LTC2635 incorporates a power-on

reset circuit. Options are available for reset to zero-scale,

reset to mid-scale in internal reference mode, reset to

mid-scale in external reference mode, or reset with all

DAC outputs in a high-impedance state after power-up.

Double-ꢀuffered Data Latches

Small 16-Pin 3mm × 3mm QFN and 10-Lead MSOP

Packages

APPLICATIONS

n

Mobile Communications

Process Control and Industrial Automation

Power Supply Margining

Portable Equipment

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. patents, including 5396245, 5859606, 6891433, 6937178, 7414561.

Automotive

BLOCK DIAGRAM

Integral Nonlinerity

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Rev D

1

Document Feedback

For more information www.analog.com

LTC2635

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Supply Voltage (V ) ................................... –0.3V to 6V

Maximum Junction Temperature ......................... 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

CC

SCL, SDA, REFLO, LDAC .............................. –0.3V to 6V

V

, CA0, CA1, CA2..... –0.3V to Min (V + 0.3V, 6V)

OUTA-D

CC

REF ................................... –0.3V to Min (V + 0.3V, 6V)

MS Package......................................................300°C

CC

Operating Temperature Range

LTC2635C................................................ 0°C to 70°C

LTC2635H (Note 3)............................ –40°C to 125°C

PIN CONFIGURATION

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ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ

ꢅ

ꢇꢈꢉꢊ

ꢇꢈꢉꢋ

ꢆꢊꢌ

ꢍꢆꢎ

ꢀ

ꢁ

ꢂ

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ꢄ

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ꢊ

ꢀ

ꢧ

ꢄ

ꢃ

ꢀꢧ

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LDAC

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Rev D

2

For more information www.analog.com

LTC2635

ORDER INFORMATION ^{http://www.linear.com/product/LTC2635#orderinfo}

LTC2635

C

UD

–L

Z

12

#TR

PBF

LEAD FREE DESIGNATOR

PꢀF = Lead Free

TAPE AND REEL

TR = 2,500-Piece Tape and Reel

RESOLUTION

12 = 12-ꢀit

10 = 10-ꢀit

8 = 8-ꢀit

POWER-0N RESET

MI = Reset to Mid-Scale in Internal Reference Mode

MX = Reset to Mid-Scale in External Reference Mode (LMX Only)

MO = Reset to Mid-Scale in Internal Reference Mode, DAC Outputs Hi-Z (LMO Only)

Z = Reset to Zero-Scale in Internal Reference Mode

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

UD = 16-Pin QFN

MSE = 10-Lead MSOP

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

H = Automotive Temperature Range (–40°C to 125°C)

PRODUCT PART NUMBER

Consult LTC Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPꢀF suffix.

Rev D

3

For more information www.analog.com

LTC2635

PRODUCT SELECTION GUIDE

PART MARKING*

POWER-ON

REFERENCE

MODE

VFS WITH INTERNAL

POWER-ON

RESET TO CODE

MAXIMUM

INL

PART NUMBER

QFN

MSOP

REFERENCE

RESOLUTION

V

CC

LTC2635-LMI12

LTC2635-LMI10

LTC2635-LMI8

LDZꢀ

LDZJ

LDZR

LTDZY

LTFꢀG

LTFꢀP

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

Internal

12-ꢀit

10-ꢀit

8-ꢀit

2.7V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-LMX12

LTC2635-LMX10

LTC2635-LMX8

LDYZ

LDZH

LDZQ

LTDZX

LTFꢀF

LTFꢀN

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

External

12-ꢀit

10-ꢀit

8-ꢀit

2.7V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-LZ12

LTC2635-LZ10

LTC2635-LZ8

LDYY

LDZG

LDZP

LTDZW

LTFꢀD

LTFꢀM

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Zero-Scale

Internal

12-ꢀit

10-ꢀit

8-ꢀit

2.7V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-LMO12**

LTC2635-LMO10**

LTC2635-LMO8**

LFꢀT

LFꢀV

LFꢀW

LTFꢀX

LTFꢀY

LTFꢀZ

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

High Impedance

Internal

12-ꢀit

10-ꢀit

8-ꢀit

2.7V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-HMI12

LTC2635-HMI10

LTC2635-HMI8

LDZF

LDZN

LDZV

LTFꢀC

LTFꢀK

LTFꢀS

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Mid-Scale

Internal

12-ꢀit

10-ꢀit

8-ꢀit

4.5V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

LTC2635-HZ12

LTC2635-HZ10

LTC2635-HZ8

LDZC

LDZK

LDZS

LTDZZ

LTFꢀH

LTFꢀQ

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Zero-Scale

Internal

12-ꢀit

10-ꢀit

8-ꢀit

4.5V to 5.5V

2.5LSꢀ

1LSꢀ

0.5LSꢀ

*Above options are available in a 16-pin QFN package (LTC2635xUD) or 10-lead MSOP package (LTC2635xMSE).

**Contact Linear Technology for other Hi-Z options.

Rev D

4

For more information www.analog.com

LTC2635

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_OUTunloaded unless otherwise specified.

LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (V_FS= 2.5V)

LTC2635-8

LTC2635-10

LTC2635-12

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN

TYP MAX MIN

TYP

MAX

UNITS

l

8

10

12

ꢀits

Monotonicity

V

= 3V, Internal Ref. (Note 4)

= 3V, Internal Ref., Code=0

= 3V, Internal Ref. (Note 5)

= 3V, Internal Ref.

CC

DNL

INL

Differential Nonlinearity

0.5

5

0.5

1

2.5

5

LSꢀ

mV

Integral Nonlinearity

Zero-Scale Error

Offset Error

0.05

0.5

10

0.2

0.5

10

1

0.5

10

ZSE

5

V

5

mV

OS

V

Temperature

OS

µV/°C

OSTC

Coefficient

l

GE

Gain Error

V

= 3V, Internal Ref.

0.2

0.8

0.2

0.8

0.2

0.8

%FSR

CC

Gain Temperature

Coefficient

= 3V, Internal Ref. (Note 10)

C-Grade

H-Grade

TC

CC

10

ppm/°C

10

Load Regulation

Internal Ref., Mid-Scale,

= 3V 10%,

l

0.009 0.016

0.035 0.064

0.14 0.256

LSꢀ/

mA

V

CC

–5mA ≤ I

≤ 5mA

OUT

V

= 5V 10%,

CC

LSꢀ/

mA

–10mA ≤ I

≤ 10mA

OUT

R

DC Output Impedance

Internal Ref., Mid-Scale,

= 3V 10%,

OUT

l

0.09 0.156

Ω

V

CC

–5mA ≤ I

≤ 5mA

OUT

V

= 5V 10%,

CC

–10mA ≤ I

≤ 10mA

OUT

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

OUT

DAC Output Span

External Reference

Internal Reference

0 to V

V

REF

0 to 2.5

PSR

Power Supply Rejection

V

CC

= 3V 10% or 5V 10%

–80

dꢀ

I

Short Circuit Output Current (Note 6)

V

= V = 5.5V

CC

SC

FS

l

Sinking

Zero-Scale; V

Shorted to V

27

–28

48

–48

mA

OUT

CC

Sourcing

Full-Scale; V

Shorted to GND

OUT

DAC I

DAC Output Current in High Impedance Mode MO Options Only

SD

l

Sinking

0.05

–0.001

2

–0.1

µA

Sourcing

Power Supply

l

V

Positive Supply Voltage

Supply Current (Note 7)

For Specified Performance

2.7

5.5

V

CC

l

I

CC

V

= 3V, V = 2.5V, External Reference

0.5

0.6

0.7

0.8

0.9

mA

CC

REF

= 3V, Internal Reference

= 5V V = 2.5V, External Reference

REF

= 5V, Internal Reference

l

I

Supply Current in Power-Down Mode

(Note 7)

V

= 5V, C-Grade

= 5V, H-Grade

1

20

30

µA

SD

CC

Rev D

5

For more information www.analog.com

LTC2635

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_OUTunloaded unless otherwise specified.

LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (V_FS= 2.5V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Input

l

Input Voltage Range

Resistance

1

V

kΩ

pF

CC

120

160

14

200

Capacitance

l

I

Reference Current, Power-Down Mode

DAC Powered Down

0.005

1.5

µA

REF

Reference Output

Output Voltage

1.24

–0.5

1.25

10

1.26

V

ppm/°C

kΩ

Reference Temperature Coefficient

Output Impedance

0.5

10

Capacitive Load Driving

Short Circuit Current

µF

V

CC

= 5.5V, REF Shorted to GND

2.5

mA

Digital I/O

l

V

Low Level Input Voltage

(SDA and SCL)

(Note 14)

0.3V

V

IL

CC

High Level Input Voltage

(SDA and SCL)

(Note 11)

0.7V

CC

IH

Low Level Input Voltage on CAn

(n = 0, 1,2)

See Test Circuit 1

See Test Circuit 2

Sink Current = 3mA

0.15V

V

IL(CAn)

IH(CAn)

CC

High Level Input Voltage on CAn

(n = 0, 1,2)

0.85V

V

CC

R

Resistance from CAn (n = 0, 1,2)

10

kΩ

MΩ

INH

INL

INF

OL

to V to Set CAn = V

CC

Resistance from CAn (n = 0, 1,2)

to GND to Set CAn = GND

Resistance from CAn (n = 0, 1,2)

2

0

to V or GND to Set CAn = Float

CC

l

V

Low Level Output Voltage

Output Fall Time

0.4

V

t

I

V = V

ꢀ

to V = V

,

20 + 0.1C

250

ns

OF

O

IH(MIN)

O

IL(MAX)

ꢀ

C = 10pF to 400pF (Note 12)

l

Pulse Width of Spikes Suppressed

by Input Filter

0

50

ns

SP

IN

l

Input Leakage

0.1V ≤ V ≤ 0.9V

1

µA

pF

CC

IN

CC

C

I/O Pin Capacitance

(Note 8)

10

IN

Capacitive Load for Each ꢀus Line

400

10

ꢀ

External Capacitive Load on Address

Pin CAn (n = 0, 1,2)

CAn

Rev D

6

For more information www.analog.com

LTC2635

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_OUTunloaded unless otherwise specified.

LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (V_FS= 2.5V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

AC Performance

t

Settling Time

V

= 3V (Note 9)

S

CC

0.39% ( 1LSꢀ at 8 ꢀits)

0.098% ( 1LSꢀ at 10 ꢀits)

0.024% ( 1LSꢀ at 12 ꢀits)

3.5

4.1

4.4

µs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

1

V/µs

pF

500

2.1

2.6

320

At Mid-Scale Transition

nV • s

kHz

DAC-to-DAC Crosstalk

Multiplying ꢀandwidth

Output Voltage Noise Density

1 DAC Held at FS, 1 DAC Switched 0 to FS

External Reference

e

n

At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

180

160

200

180

nV/√Hz

Output Voltage Noise

0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference

35

40

680

730

µV

P-P

µV

P-P

µV

P-P

µV

P-P

C

= 0.1µF

REF

TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. V_CC= 2.7V to 5.5V. (See Figure 1) (Note 13)

LTC2635-LMI12/-LMI10/-LMI8/-LMX12/-LMX10/-LMX8/-LZ12/-LZ10/-LZ8/-LMO12/-LMO10/-LM08 (V_FS= 2.5V)

SYMBOL

PARAMETER

CONDITIONS

MIN

0

TYP

MAX

UNITS

kHz

µs

l

f

t

SCL Clock Frequency

400

SCL

Hold Time (Repeated) Start Condition

Low Period of the SCL Clock Pin

High Period of the SCL Clock Pin

Set-Up Time for a Repeated Start Condition

Data Hold Time

0.6

HD(STA)

LOW

1.3

µs

0.6

µs

HIGH

SU(STA)

HD(DAT)

SU(DAT)

r

0.6

µs

0

0.9

µs

Data Set-Up Time

100

ns

Rise Time of ꢀoth SDA and SCL Signals

Fall Time of ꢀoth SDA and SCL Signals

Set-Up Time for Stop Condition

ꢀus Free Time ꢀetween a Stop and Start Condition

(Note 12)

20 + 0.1C

0.6

300

ns

ꢀ

ns

f

ꢀ

µs

SU(STO)

ꢀUF

1.3

µs

th

rd

Falling Edge of 9 Clock of the 3 Input ꢀyte to LDAC

High or Low Transition

400

ns

1

l

t

LDAC Low Pulse Width

20

ns

2

Rev D

7

For more information www.analog.com

LTC2635

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded unless otherwise specified.

LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (V_FS= 4.096V)

LTC2635-8

LTC2635-10

LTC2635-12

SYMBOL PARAMETER

DC Performance

Resolution

CONDITIONS

MIN TYP MAX MIN

TYP MAX MIN

TYP

MAX

UNITS

l

8

10

12

ꢀits

Monotonicity

V

= 5V, Internal Ref. (Note 4)

= 5V, Internal Ref., Code=0

= 5V, Internal Ref. (Note 5)

= 5V, Internal Reference

CC

DNL

INL

Differential Nonlinearity

0.5

5

0.5

1

2.5

5

LSꢀ

mV

Integral Nonlinearity

Zero-Scale Error

Offset Error

0.05

0.5

10

0.2

0.5

10

1

0.5

10

ZSE

5

V

5

mV

OS

V

Temperature

OS

µV/°C

OSTC

Coefficient

l

GE

Gain Error

V

= 5V, Internal Reference

0.2

0.8

0.2

0.8

0.2

0.8

%FSR

CC

Gain Temperature

Coefficient

= 5V, Internal Ref. (Note 10)

C-Grade

H-Grade

TC

CC

10

ppm/°C

10

l

Load Regulation

DC Output

Internal Reference, Mid-Scale,

= 5V 10%,

0.006 0.01

0.022 0.04

0.09 0.16 LSꢀ/mA

V

CC

–10mA ≤ I

≤ 10mA

OUT

R

OUT

Internal Reference, Mid-Scale,

= 5V 10%,

0.09 0.156

Ω

V

CC

–10mA ≤ I

≤ 10mA

OUT

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

0 to V

MAX

UNITS

V

DAC Output Span

External Reference

Internal Reference

V

OUT

REF

0 to 4.096

PSR

Power Supply Rejection

V

= 5V 10%

–80

dꢀ

CC

I

Short Circuit Output Current (Note 6)

Sinking

Sourcing

= V = 5.5V

CC

SC

FS

l

Zero-Scale; V

Shorted to V

27

–28

48

–48

mA

OUT

CC

Full-Scale; V

Shorted to GND

Power Supply

l

V

Positive Supply Voltage

Supply Current (Note 7)

For Specified Performance

4.5

5.5

V

CC

l

I

V

CC

V

CC

= 3V, V = 4.096V, External Reference

0.6

0.7

0.8

0.9

mA

CC

REF

= 3V, Internal Reference

l

I

Supply Current in Power-Down Mode

(Note 7)

V

CC

V

CC

= 5V, C-Grade

= 5V, H-Grade

1

20

30

µA

SD

Rev D

8

For more information www.analog.com

LTC2635

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded unless otherwise specified.

LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (V_FS= 4.096V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Reference Input

l

Input Voltage Range

Resistance

1

V

kΩ

pF

CC

120

160

14

200

Capacitance

l

I

Reference Current, Power-Down Mode

DAC Powered Down

0.005

1.5

µA

REF

Reference Output

Output Voltage

2.032

2.048

10

2.064

V

ppm/°C

kΩ

Reference Temperature Coefficient

Output Impedance

0.5

10

Capacitive Load Driving

Short Circuit Current

µF

V

= 5.5V, REF Shorted to GND

4

mA

CC

Digital I/O

l

V

Low Level Input Voltage

(SDA and SCL)

(Note 14)

–0.5

0.7V

0.3V

V

IL

CC

High Level Input Voltage

(SDA and SCL)

(Note 11)

IH

CC

Low Level Input Voltage on CAn

(n = 0, 1,2)

See Test Circuit 1

See Test Circuit 2

Sink Current = 3mA

0.15V

V

IL(CAn)

IH(CAn)

CC

High Level Input Voltage on CAn

(n = 0, 1,2)

0.85V

V

CC

R

Resistance from CAn (n = 0, 1,2)

10

kΩ

MΩ

INH

INL

INF

OL

to V to Set CAn = V

CC

Resistance from CAn (n = 0, 1,2)

to GND to Set CAn = GND

Resistance from CAn (n = 0, 1,2)

2

0

to V or GND to Set CAn = Float

CC

l

V

Low Level Output Voltage

Output Fall Time

0.4

V

t

I

V = V

to V = V

,

20 + 0.1C

250

ns

OF

O

IH(MIN)

O

IL(MAX)

ꢀ

C = 10pF to 400pF (Note 12)

ꢀ

l

Pulse Width of Spikes Suppressed

by Input Filter

0

50

ns

SP

IN

l

Input Leakage

0.1V ≤ V ≤ 0.9V

1

µA

pF

CC

IN

CC

C

I/O Pin Capacitance

(Note 8)

10

IN

Capacitive Load for Each ꢀus Line

400

10

ꢀ

External Capacitive Load on Address

Pin CAn (n=0, 1,2)

CAn

Rev D

9

For more information www.analog.com

LTC2635

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded unless otherwise specified.

LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (V_FS= 4.096V)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

AC Performance

t

Settling Time

V

= 5V (Note 9)

S

CC

0.39% ( 1LSꢀ at 8 ꢀits)

0.098% ( 1LSꢀ at 10 ꢀits)

0.024% ( 1LSꢀ at 12 ꢀits)

3.9

4.3

5

µs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Impulse

1

500

3

V/µs

pF

At Mid-Scale Transition

nV • s

kHz

DAC-to-DAC Crosstalk

Multiplying ꢀandwidth

Output Voltage Noise Density

1 DAC Held at FS, 1 DAC Switched 0 to FS

External Reference

3

320

e

n

At f = 1kHz, External Reference

At f = 10kHz, External Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

180

160

250

230

nV/√Hz

Output Voltage Noise

0.1Hz to 10Hz, External Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, External Reference

0.1Hz to 200kHz, Internal Reference

35

50

680

750

µV

P-P

µV

P-P

µV

P-P

µV

P-P

C

= 0.1µF

REF

TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. V_CC= 4.5V to 5.5V. (See Figure 1) (Note 13)

LTC2635-HMI12/-HMI10/-HMI8/-HZ12/-HZ10/-HZ8 (V_FS= 4.096V)

SYMBOL

PARAMETER

CONDITIONS

MIN

0

TYP

MAX

UNITS

kHz

µs

l

f

t

SCL Clock Frequency

400

SCL

Hold Time (Repeated) Start Condition

Low Period of the SCL Clock Pin

High Period of the SCL Clock Pin

Set-Up Time for a Repeated Start Condition

Data Hold Time

0.6

HD(STA)

LOW

1.3

µs

0.6

µs

HIGH

SU(STA)

HD(DAT)

SU(DAT)

r

0.6

µs

0

0.9

µs

Data Set-Up Time

100

20+0.1C

0.6

ns

Rise Time of ꢀoth SDA and SCL Signals

Fall Time of ꢀoth SDA and SCL Signals

Set-Up Time for Stop Condition

ꢀus Free Time ꢀetween a Stop and Start Condition

(Note 12)

300

ns

ꢀ

ns

f

µs

SU(STO)

ꢀUF

1.3

µs

th

rd

Falling Edge of 9 Clock of the 3 Input ꢀyte to LDAC

High or Low Transition

400

ns

1

l

t

LDAC Low Pulse Width

20

ns

2

Rev D

10

For more information www.analog.com

LTC2635

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device reliability

and lifetime.

the specified maximum operating junction temperature may impair device

reliability.

Note 7: Digital inputs at 0V or V

.

CC

Note 8: Guaranteed by design and not production tested.

Note 2: All voltages are with respect to GND.

Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and

3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.

Note 3: Operating at temperatures above 90°C and with V > 4V requires

CC

V

slew rates to be no greater than 73mV/us.

Note 10: Temperature coefficient is calculated by dividing the maximum

N

Note 4: Linearity and monotonicity are defined from code k to code 2 – 1,

L

change in output voltage by the specified temperature range.

N

where N is the resolution and k is given by k = 0.016 • (2 / V ),

L

FS

rounded to the nearest whole code. For V = 2.5V and N = 12, k = 26

FS

L

Note 11: Maximum V = V

+ 0.5V.

IH

CC(MAX)

and linearity is defined from code 26 to code 4,095. For V = 4.096V and

FS

Note 12: C = capacitance of one bus line in pF.

ꢀ

N = 12, k = 16 and linearity is defined from code 16 to code 4,095.

L

Note 13: All values refer to V = V

and V = V

levels.

IH

IH(MIN)

IL

IL(MAX)

Note 5: Inferred from measurement at code 16 (LTC2635-12), code 4

(LTC2635-10) or code 1 (LTC2635-8), and at full-scale.

Note 14: Minimum V_ILexceeds the Absolute Maximum rating. This condition

won’t damage the IC, but could degrade performance.

Note 6: This IC includes current limiting that is intended to protect the device

during momentary overload conditions. Junction temperature can exceed

the rated maximum during current limiting. Continuous operation above

Rev D

11

For more information www.analog.com

LTC2635

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

LTC2635-L12 (Internal Reference, V_FS= 2.5V)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

ꢋꢌꢃ

ꢃꢌꢍ

ꢊꢋꢃ

ꢃꢋꢌ

ꢗ

ꢘ ꢑꢗ

ꢖ

ꢗ ꢐꢖ

ꢀꢀ

ꢃ

ꢎꢃꢌꢍ

ꢎꢋꢌꢃ

ꢍꢃꢋꢌ

ꢍꢊꢋꢃ

ꢃ

ꢋꢃꢏꢐ

ꢏꢃꢐꢖ

ꢑꢃꢒꢏ

ꢐꢃꢕꢍ

ꢃ

ꢊꢃꢎꢏ

ꢎꢃꢏꢕ

ꢐꢃꢑꢎ

ꢏꢃꢔꢌ

ꢀꢁDꢂ

ꢏꢓꢑꢍ ꢔꢃꢋ

ꢎꢒꢐꢌ ꢓꢃꢎ

Reference Output Voltage vs

Temperature

INL vs Temperature

DNL vs Temperature

ꢑꢒꢌ

ꢒꢓꢌ

ꢌꢓꢋ

ꢏꢐꢑꢒꢌ

ꢏꢐꢑꢋꢋ

ꢏꢐꢑꢋꢌ

ꢏꢐꢑꢓꢋ

ꢏꢐꢑꢓꢌ

ꢙ

ꢈꢈ

ꢚ ꢖꢙ

ꢙ

ꢚ ꢗꢙ

ꢍ

ꢗ ꢕꢍ

ꢈꢈ

ꢌꢒꢋ

ꢌ

ꢍꢎꢏ ꢆꢃꢛꢐꢉ

Dꢍꢎ ꢆꢃꢛꢏꢉ

Dꢍꢎ ꢆꢍꢁꢗꢉ

ꢌ

ꢊꢌꢒꢋ

ꢊꢌꢓꢋ

ꢍꢎꢏ ꢆꢎꢁꢘꢉ

ꢊꢑꢒꢌ

ꢊꢒꢓꢌ

ꢊꢋꢌ ꢊꢓꢋ

ꢌ

ꢓꢋ ꢋꢌ ꢔꢋ ꢑꢌꢌ ꢑꢓꢋ ꢑꢋꢌ

ꢊꢋꢌ ꢊꢔꢋ

ꢌ

ꢔꢋ ꢋꢌ ꢕꢋ ꢒꢌꢌ ꢒꢔꢋ ꢒꢋꢌ

ꢊꢋꢌ ꢊꢑꢋ

ꢌ

ꢑꢋ ꢋꢌ ꢔꢋ ꢏꢌꢌ ꢏꢑꢋ ꢏꢋꢌ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢓꢕꢖꢋ ꢗꢌꢘ

ꢔꢖꢗꢋ ꢘꢌꢗ

ꢑꢒꢕꢋ ꢖꢌꢋ

Settling to 1 LSB Rising

Settling to 1 LSB Falling

ꢔꢕꢖ ꢍꢊꢆꢍꢗ ꢆꢘ ꢐꢙꢚ

Dꢛꢈꢛ ꢌꢜꢈꢝ

ꢐꢃꢔ ꢋꢍꢕꢊꢖ ꢈꢆ ꢉꢃꢔ ꢋꢍꢕꢊꢖ ꢋꢈꢖꢗ

ꢘ ꢐ ꢙ ꢅ ꢘ ꢀꢛꢎꢅ

ꢋꢍꢊ

ꢎꢅꢃDꢄꢅ

ꢅ

ꢍꢍ

ꢚꢋ

ꢅ

ꢆꢇꢈ

R ꢘ ꢀꢜꢙ ꢍ ꢘ ꢉꢒꢒꢝꢚ

ꢊ

ꢉ ꢊꢋꢌꢃDꢄꢅ

ꢕꢅꢖRꢕꢑꢖ ꢆꢚ ꢀꢎꢏ ꢖꢅꢖꢞꢈꢋ

ꢔꢛꢔꢁꢂ

ꢐꢓꢐꢁꢂ

ꢅ

ꢆꢇꢈ

ꢉꢃꢞ ꢋꢍꢛꢊꢝ ꢈꢆ ꢐꢃꢞ ꢋꢍꢛꢊꢝ ꢋꢈꢝꢟ

ꢠ ꢐ ꢡ ꢅ ꢠ ꢀꢓꢎꢅ

ꢟꢠꢡ ꢍꢊꢆꢍꢢ ꢆꢚ ꢐꢣꢤ

Dꢕꢈꢕ ꢌꢥꢈꢖ

ꢉ ꢊꢋꢌꢃDꢄꢅ

ꢅ

ꢍꢍ

ꢘꢋ

ꢋꢍꢊ

ꢎꢅꢃDꢄꢅ

R ꢠ ꢀꢢꢡ ꢍ ꢠ ꢉꢒꢒꢣꢘ

ꢊ

ꢛꢅꢝRꢛꢑꢝ ꢆꢘ ꢀꢎꢏ ꢝꢅꢝꢤꢈꢋ

ꢀꢏꢐꢎ ꢑꢒꢏ

ꢀꢏꢐꢎ ꢑꢒꢓ

ꢀꢁꢂꢃDꢄꢅ

Rev D

12

For more information www.analog.com

LTC2635

TYPICAL PERFORMANCE CHARACTERISTICS T_A= 25°C, unless otherwise noted.

LTC2635-H12 (Internal Reference, V_FS= 4.096V)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

ꢋꢌꢃ

ꢊꢋꢃ

ꢃꢋꢌ

ꢗ

ꢘ ꢍꢗ

ꢖ

ꢗ ꢌꢖ

ꢀꢀ

ꢃꢌꢍ

ꢃ

ꢎꢃꢌꢍ

ꢎꢋꢌꢃ

ꢍꢃꢋꢌ

ꢍꢊꢋꢃ

ꢃ

ꢋꢃꢏꢐ

ꢏꢃꢐꢕ

ꢑꢃꢒꢏ

ꢐꢃꢖꢍ

ꢃ

ꢊꢃꢎꢏ

ꢎꢃꢏꢕ

ꢐꢃꢑꢎ

ꢏꢃꢔꢌ

ꢀꢁDꢂ

ꢏꢓꢑꢍ ꢔꢃꢕ

ꢎꢒꢐꢌ ꢓꢃꢔ

Reference Output Voltage vs

Temperature

INL vs Temperature

DNL vs Temperature

ꢒꢓꢌ

ꢌꢓꢋ

ꢑꢒꢌ

ꢏꢐꢌꢑꢒ

ꢏꢐꢌꢋꢒ

ꢏꢐꢌꢓꢒ

ꢏꢐꢌꢔꢒ

ꢏꢐꢌꢏꢒ

ꢙ

ꢚ ꢋꢙ

ꢘ

ꢈꢈ

ꢙ ꢋꢘ

ꢈꢈ

ꢍ

ꢘ ꢋꢍ

ꢈꢈ

ꢍꢎꢏ ꢆꢃꢛꢐꢉ

ꢌꢒꢋ

ꢌ

Dꢍꢎ ꢆꢃꢚꢏꢉ

Dꢍꢎ ꢆꢍꢁꢗꢉ

ꢌ

ꢍꢎꢏ ꢆꢎꢁꢘꢉ

ꢊꢌꢓꢋ

ꢊꢌꢒꢋ

ꢊꢒꢓꢌ

ꢊꢑꢒꢌ

ꢊꢋꢌ ꢊꢔꢋ

ꢌ

ꢔꢋ ꢋꢌ ꢕꢋ ꢒꢌꢌ ꢒꢔꢋ ꢒꢋꢌ

ꢊꢋꢌ ꢊꢓꢋ

ꢌ

ꢓꢋ ꢋꢌ ꢔꢋ ꢑꢌꢌ ꢑꢓꢋ ꢑꢋꢌ

ꢊꢋꢌ ꢊꢏꢋ

ꢌ

ꢏꢋ ꢋꢌ ꢖꢋ ꢕꢌꢌ ꢕꢏꢋ ꢕꢋꢌ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢔꢖꢗꢋ ꢘꢒꢌ

ꢓꢕꢖꢋ ꢗꢑꢑ

ꢏꢑꢔꢋ ꢗꢕꢏ

Settling to 1 LSB Rising

Settling to 1 LSB Falling

ꢐꢃꢒ ꢋꢍꢓꢊꢔ ꢈꢆ

ꢛꢟꢠ ꢍꢊꢆꢍꢡ ꢆꢘ ꢐꢢꢣ

Dꢓꢈꢓ ꢌꢤꢈꢔ

ꢉꢃꢒ ꢋꢍꢓꢊꢔ ꢋꢈꢔꢕ

ꢋꢍꢊ

ꢎꢅꢃDꢄꢅ

ꢅ

ꢖ ꢎ ꢗ ꢅ ꢖ ꢒꢙꢚꢛꢎꢅ

ꢍꢍ

ꢘꢋ

ꢅ

R

ꢊ

ꢖ ꢀꢜꢗ ꢍ ꢖ ꢉꢚꢚꢝꢘ

ꢊ

ꢆꢇꢈ

ꢉ ꢊꢋꢌꢃDꢄꢅ

ꢓꢅꢔRꢓꢑꢔ ꢆꢘ ꢀꢎꢏ ꢔꢅꢔꢞꢈꢋ

ꢐꢙꢛꢁꢂ

ꢎꢁꢂ

ꢛꢟꢠ ꢍꢊꢆꢍꢡ ꢆꢘ ꢐꢢꢣ

Dꢓꢈꢓ ꢌꢤꢈꢔ

ꢅ

ꢋꢍꢊ

ꢎꢅꢃDꢄꢅ

ꢆꢇꢈ

ꢉꢃꢒ ꢋꢍꢓꢊꢔ ꢈꢆ ꢐꢃꢒ ꢋꢍꢓꢊꢔ ꢋꢈꢔꢕ

ꢖ ꢎ ꢗ ꢅ ꢖ ꢒꢙꢚꢛꢎꢅ

ꢉ ꢊꢋꢌꢃDꢄꢅ

ꢅ

ꢍꢍ

ꢘꢋ

R ꢖ ꢀꢜꢗ ꢍ ꢖ ꢉꢚꢚꢝꢘ

ꢊ

ꢓꢅꢔRꢓꢑꢔ ꢆꢘ ꢀꢎꢏ ꢔꢅꢔꢞꢈꢋ

ꢀꢏꢐꢎ ꢑꢉꢐ

ꢀꢏꢐꢎ ꢑꢉꢒ

ꢀꢁꢂꢃDꢄꢅ

Rev D

13

For more information www.analog.com

LTC2635

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

LTC2635-10

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

ꢋꢌꢃ

ꢃꢌꢍ

ꢊꢋꢃ

ꢃꢋꢌ

ꢔ

ꢀꢀ

ꢔ

ꢖꢇ

ꢕ ꢒꢔ

ꢕ ꢎꢋꢌꢔ

ꢕ

ꢀꢀ

ꢕ

ꢗꢈ

ꢖ ꢓꢕ

ꢖ ꢏꢌꢍꢕ

ꢗꢄꢘꢂRꢄꢙꢅ Rꢂꢖ

ꢄꢅꢘꢂRꢅꢙꢆ Rꢂꢗ

ꢃ

ꢎꢃꢌꢍ

ꢎꢋꢌꢃ

ꢍꢃꢋꢌ

ꢍꢊꢋꢃ

ꢃ

ꢏꢍꢐ

ꢍꢋꢏ

ꢑꢐꢒ

ꢋꢃꢏꢓ

ꢃ

ꢎꢌꢏ

ꢌꢊꢎ

ꢐꢏꢑ

ꢊꢃꢎꢒ

ꢀꢁDꢂ

ꢏꢐꢓꢍ ꢔꢋꢍ

ꢎꢏꢒꢌ ꢓꢊꢏ

LTC2635-8

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

ꢃꢋꢌꢃ

ꢃꢋꢍꢌ

ꢃ

ꢃꢊꢋꢃ

ꢃꢊꢌꢋ

ꢃ

ꢗ

ꢀꢀ

ꢗ

ꢙꢈ

ꢘ ꢓꢗ

ꢘ ꢍꢋꢌꢗ

ꢕ

ꢀꢀ

ꢕ

ꢗꢇ

ꢖ ꢒꢕ

ꢖ ꢌꢊꢋꢕ

ꢄꢅꢚꢂRꢅꢛꢆ Rꢂꢙ

ꢘꢄꢙꢂRꢄꢚꢅ Rꢂꢗ

ꢎꢃꢋꢍꢌ

ꢎꢃꢋꢌꢃ

ꢍꢃꢊꢌꢋ

ꢍꢃꢊꢋꢃ

ꢃ

ꢏꢐ

ꢑꢍꢖ

ꢑꢒꢍ

ꢍꢌꢌ

ꢃ

ꢎꢏ

ꢐꢌꢔ

ꢐꢑꢌ

ꢌꢋꢋ

ꢀꢁDꢂ

ꢍꢏꢓꢌ ꢔꢑꢕ

ꢌꢎꢒꢋ ꢓꢐꢔ

LTC2635

Load Regulation

Current Limiting

Offset Error vs Temperature

ꢊꢌꢍꢊ

ꢊꢌꢎꢏ

ꢊꢌꢎꢊ

ꢊꢌꢊꢏ

ꢊ

ꢒ

ꢓ

ꢌꢊ

ꢋ

ꢒꢒ

ꢋ

ꢒꢒ

ꢋ

ꢒꢒ

ꢓ ꢏꢋ ꢄꢔꢃꢒꢍꢐꢉꢏꢕꢖꢇ

ꢓ ꢏꢋ ꢄꢔꢃꢒꢍꢐꢉꢏꢕꢔꢇ

ꢓ ꢉꢋ ꢄꢔꢃꢒꢍꢐꢉꢏꢕꢔꢇ

ꢋ

ꢔꢔ

ꢋ

ꢔꢔ

ꢋ

ꢔꢔ

ꢕ ꢑꢋ ꢄꢖꢃꢔꢐꢎꢉꢑꢗꢘꢇ

ꢕ ꢑꢋ ꢄꢖꢃꢔꢐꢎꢉꢑꢗꢖꢇ

ꢕ ꢉꢋ ꢄꢖꢃꢔꢐꢎꢉꢑꢗꢖꢇ

ꢍ

ꢎ

ꢏ

ꢔ

ꢐ

ꢌ

ꢊ

ꢈꢐ

ꢈꢏ

ꢈꢎ

ꢈꢍ

ꢈꢌꢊ

ꢈꢊꢌꢊꢏ

ꢈꢊꢌꢊꢎ

ꢈꢊꢌꢎꢏ

ꢈꢊꢌꢍꢊ

ꢊꢔ

ꢊꢓ

ꢊꢒ

ꢀꢗꢃꢘRꢗꢆꢔ Rꢘꢙꢌ

ꢒꢁDꢘ ꢓ ꢚꢀDꢕꢛꢒꢆꢔꢘ

ꢀꢙꢃꢚRꢙꢆꢖ Rꢚꢛꢜ

ꢔꢁDꢚ ꢕ ꢝꢀDꢗꢞꢔꢆꢖꢚ

ꢈꢉꢊ

ꢈꢍꢊ

ꢈꢎꢊ

ꢊ

ꢎꢊ ꢍꢊ ꢉꢊ

ꢊꢋꢌ ꢊꢓꢋ

ꢌ

ꢓꢋ ꢋꢌ ꢕꢋ ꢔꢌꢌ ꢔꢓꢋ ꢔꢋꢌ

ꢈꢉꢊ

ꢈꢐꢊ

ꢈꢌꢊ

ꢊ

ꢌꢊ ꢐꢊ ꢉꢊ

ꢀ

ꢄꢅꢆꢇ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢀ

ꢄꢅꢆꢇ

ꢁꢂꢃ

ꢍꢐꢉꢏ ꢑꢍꢊ

ꢓꢖꢒꢋ ꢗꢓꢔ

ꢐꢎꢉꢑ ꢒꢌꢓ

Rev D

14

For more information www.analog.com

LTC2635

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

LTC2635

Large-Signal Response

Mid-Scale Glitch Impulse

Power-On Reset Glitch

ꢑꢉꢌꢀꢍꢎꢊꢒꢑ

ꢑꢒꢓ ꢌꢍꢆꢌꢔ ꢆꢕ ꢏꢖꢗ

Dꢘꢈꢘ ꢙꢚꢈꢛ

ꢋꢌꢍ

ꢉꢅꢃDꢄꢅ

ꢆ

ꢌꢌ

ꢀꢆꢄDꢅꢆ

ꢅ

ꢆꢇꢈ

ꢍꢈꢌꢀꢎꢏꢉꢜꢝꢞꢀꢟ ꢅ ꢠ ꢉꢅ

ꢌꢌ

ꢏꢡꢅ ꢢ ꢂ ꢈꢚꢣ

ꢉꢊꢋꢅꢃDꢄꢅ

ꢓꢔRꢇ ꢕꢌꢖꢑꢔ

ꢅ

ꢆ

ꢆꢇꢈ

ꢇꢈꢉ

ꢉꢊꢅꢃDꢄꢅ

ꢊꢋꢆꢄDꢅꢆ

ꢍꢈꢌꢀꢎꢏꢉꢜꢍꢞꢀꢟ ꢅ ꢠ ꢏꢅ

ꢌꢌ

ꢀꢤꢞꢡꢅ ꢢ ꢂ ꢈꢚꢣ

ꢅ

ꢑ ꢅ ꢑ ꢋꢅ

ꢒꢒ

ꢏꢐ

ꢓꢃꢔ ꢐꢒꢕꢖꢗ ꢘꢙ ꢍꢃꢔ ꢐꢒꢕꢖꢗ

ꢀꢎꢏꢉ ꢐꢀꢏ

ꢀꢁꢂꢃDꢄꢅ

ꢀꢁꢁꢂꢃꢄDꢅꢆ

ꢀꢌꢍꢋ ꢎꢀꢀ

ꢀꢍꢎꢊ ꢏꢀꢐ

Headroom at Rails vs

Output Current

Exiting Power-Down to Mid-Scale

Power-On Reset to Mid-Scale

ꢊꢋꢈ

ꢌꢋꢊ

ꢌꢋꢈ

ꢏꢋꢊ

ꢏꢋꢈ

ꢎꢋꢊ

ꢎꢋꢈ

ꢍꢋꢊ

ꢍꢋꢈ

ꢈꢋꢊ

ꢈ

ꢅ

ꢣ ꢀꢅ

ꢌꢌ

ꢊꢉ ꢕꢁꢂRꢖꢀꢗꢔ

ꢄꢟꢈꢜRꢟꢙꢍ

RꢜꢖꢜRꢜꢟꢌꢜ

ꢆ

ꢇꢇ

ꢀꢆꢄDꢅꢆ

ꢋꢌꢍ

ꢀꢅꢃDꢄꢅ

ꢒꢓꢔ ꢌꢍꢆꢌꢕ ꢆꢖ ꢐꢗꢘ

Dꢙꢈꢙ ꢚꢛꢈꢜ

ꢏꢉ ꢄꢘꢃꢖꢎꢓꢏꢊꢙꢘꢇ ꢕꢁꢂRꢖꢀꢗꢔ

ꢑꢊꢇꢀꢍꢎꢌꢒꢓ

Dꢙꢌꢂ ꢙꢝꢌ ꢄꢟ

ꢠꢆꢡꢜRꢝDꢆꢡꢟ

ꢢꢆDꢜ

ꢅ

ꢆꢇꢈ

ꢉꢊꢀꢅꢃDꢄꢅ

ꢊꢉ ꢕꢀꢗꢚꢀꢗꢔ

ꢏꢉ ꢄꢘꢃꢖꢎꢓꢏꢊꢙꢘꢇ ꢕꢀꢗꢚꢀꢗꢔ

ꢑꢊꢇꢀꢍꢎꢌꢒꢑ

ꢆ

ꢈꢉꢊ

ꢁꢋꢌꢆꢄDꢅꢆ

ꢍꢈꢌꢎꢏꢐꢀꢝꢞ

ꢎꢏꢐꢀ ꢑꢎꢏ

ꢀꢁꢂꢃDꢄꢅ

ꢀꢁꢁꢂꢃꢄDꢅꢆ

ꢈ

ꢍ

ꢎ

ꢏ

ꢌ

ꢊ

ꢓ

ꢐ

ꢑ

ꢒ

ꢍꢈ

ꢀꢍꢎꢌ ꢏꢀꢐ

ꢀ

ꢄꢅꢆꢇ

ꢁꢂꢃ

ꢎꢓꢏꢊ ꢔꢎꢊ

Exiting Power-Down for Hi-Z

Option

Supply Current vs Logic Voltage

ꢐꢌꢎ

ꢐꢌꢍ

ꢐꢌꢑ

ꢐꢌꢋ

ꢋꢌꢏ

ꢋꢌꢎ

ꢋꢌꢍ

ꢕꢖꢈꢈꢗ ꢕDꢇꢘ ꢕꢄꢀ

ꢙꢈꢆꢖꢈꢈꢚ

ꢟꢣꢤ ꢈꢆꢎꢈꢥ ꢎꢦ ꢊꢧꢨ

Dꢑꢇꢑ ꢖꢗꢇꢔ

ꢋꢅ ꢇꢚD ꢅ

ꢄꢄ

ꢙꢈꢆ

ꢋꢅꢃDꢄꢅ

Dꢑꢈ ꢎꢒꢇꢓꢒꢇ ꢙꢔꢇ

ꢇꢎ ꢍꢄDꢌꢙꢈꢑꢆꢔ

ꢚꢄꢛꢚꢌꢄꢍꢓꢔDꢑꢕꢈꢔ

ꢠꢓꢎꢡꢔRꢌDꢎꢡꢕꢢ ꢍꢎDꢔ

ꢅ

ꢛ ꢓꢅ

ꢄꢄ

ꢅ

ꢎꢒꢇ

ꢋꢝꢝꢞꢅꢃDꢄꢅ

ꢅ

ꢛ ꢒꢅ

ꢄꢄ

ꢉꢀꢆꢄꢑꢎꢒꢓꢜꢀꢊ

ꢀꢉꢊꢋ ꢛꢀꢟ

ꢀꢁꢂꢃDꢄꢅ

ꢋ

ꢐ

ꢑ

ꢒ

ꢍ

ꢓ

ꢆꢇꢈꢀꢉꢊꢋꢌꢆꢍꢎꢏ ꢅ ꢐ ꢊꢅ

ꢈꢈ

ꢀꢁꢂꢃꢄ ꢅꢁꢀꢆꢇꢂꢈ ꢉꢅꢊ

ꢑꢎꢒꢓ ꢂꢑꢏ

Dꢑꢈ ꢎꢒꢇꢓꢒꢇ DRꢄꢅꢔꢕ ꢖꢗ

ꢘꢅ ꢙꢎꢒRꢈꢔ ꢇꢚRꢎꢒꢛꢚ

ꢘꢋꢜ RꢔꢙꢄꢙꢇꢎR

Rev D

15

For more information www.analog.com

LTC2635

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

LTC2635

Mulitplying Bandwidth

Noise Voltage vs Frequency

Gain Error vs Reference Input

ꢍ

ꢓ

ꢌꢐꢑ

ꢑꢐꢒ

500

400

300

200

100

0

V

= 5V

CC

ꢄ

ꢙ ꢗꢐꢗꢄ

ꢃꢃ

CODE = MID-SCALE

INTERNAL REF

ꢉꢈꢍꢂ ꢀRRꢅR ꢅꢁ ꢔ ꢃꢚꢈꢂꢂꢀꢆꢏ

ꢔꢍ

ꢑꢐꢓ

ꢔꢕ

ꢑꢐꢔ

ꢔꢎ

ꢑꢐꢖ

ꢔꢖ

ꢑ

LTC2635-H

ꢔꢒꢓ

ꢔꢒꢍ

ꢔꢒꢕ

ꢔꢒꢎ

ꢔꢒꢖ

ꢕꢑꢐꢖ

ꢕꢑꢐꢔ

ꢕꢑꢐꢓ

ꢕꢑꢐꢒ

ꢕꢌꢐꢑ

LTC2635-L

ꢙ

ꢚ ꢐꢙ

RꢁꢀꢇDꢅꢊ

Rꢁꢀꢇꢛꢅꢊ

ꢅꢟDꢁ ꢚ ꢀꢃꢠꢠꢞꢡꢅꢛꢠꢁ

ꢅꢅ

ꢚ ꢍꢙ

ꢚ ꢓꢜꢍꢙ

ꢝꢞꢝ

ꢒꢗ

ꢒꢓꢗ

ꢒꢓꢓꢗ

ꢒꢘ

ꢌ

ꢌꢐꢗ

ꢖ

ꢖꢐꢗ

ꢘ

ꢘꢐꢗ

ꢔ

ꢔꢐꢗ

ꢗ

ꢗꢐꢗ

100

1k

10k

100k

1M

ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ

RꢀꢁꢀRꢀꢂꢃꢀ ꢄꢅꢆꢇꢈꢉꢀ ꢊꢄꢋ

FREQUENCY (Hz)

ꢍꢎꢏꢐ ꢑꢏꢒ

ꢖꢓꢘꢗ ꢉꢘꢘ

2634 G32

0.1Hz to 10Hz Voltage Noise

DAC-to-DAC Crosstalk (Dynamic)

Gain Error vs Temperature

ꢔꢕꢌ

ꢌꢕꢋ

ꢄ

ꢎ ꢊ ꢏ ꢄ ꢎ ꢇꢒꢊꢄ

ꢐꢑ

ꢍꢍ

ꢘꢙꢚ ꢈꢓꢐꢈꢛ ꢐꢏ ꢖꢜꢝ

Dꢇꢋꢇ ꢞꢟꢋꢠ

ꢍꢓDꢔ ꢎ ꢕꢃDꢖꢑꢍꢗꢘꢔ

ꢃꢙꢚꢔRꢙꢗꢘ Rꢔꢐ

ꢉꢈꢓ

ꢔꢅꢃDꢄꢅ

ꢆ Dꢇꢈ

ꢉꢊꢄꢋꢈꢌ ꢍꢎꢏꢉ

ꢀꢅꢃDꢄꢅ

ꢀꢅꢆꢄꢂDꢃꢄ

ꢌ

ꢅ

ꢐꢑꢋ

ꢊꢌꢕꢋ

ꢀꢒꢅꢃDꢄꢅ

ꢓꢋꢈꢀꢕꢖꢔꢎꢌꢆꢀꢡ ꢅ ꢢ ꢔꢅ

ꢈꢈ

ꢖꢣꢅ ꢤ ꢂ ꢋꢟꢥꢄꢈꢇꢓ ꢈ ꢢ ꢍꢦꢆꢁꢏ

Rꢠꢏ

ꢊꢔꢕꢌ

ꢀꢕꢖꢔ ꢗꢖꢔ

ꢀꢁꢂꢃDꢄꢅ

ꢀꢁꢂDꢃꢄ

ꢊꢋꢌ ꢊꢖꢋ

ꢌ

ꢖꢋ ꢋꢌ ꢗꢋ ꢔꢌꢌ ꢔꢖꢋ ꢔꢋꢌ

ꢇꢈꢉꢊ ꢋꢉꢌ

ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ

ꢖꢘꢙꢋ ꢍꢙꢘ

Rev D

16

For more information www.analog.com

LTC2635

PIN FUNCTIONS ^(MSOP/QFN)

V

(Pin 1/Pin 16): Supply Voltage Input. 2.7V ≤ V

≤

REF (Pin 7/Pin 10): Reference Voltage Input or Output.

When External Reference mode is selected, REF is an

input (1V ≤ V_REF≤ V_CC) where the voltage supplied

sets the full-scale DAC output voltage. When Internal

Reference is selected, the 10ppm/°C 1.25V (LTC2635-L)

or 2.048V (LTC2635-H) internal reference (half full-scale)

is available at the pin. This output may be bypassed to

GND with up to 10µF, and must be buffered when driving

an external DC load current.

CC

5.5V (LTC2635-L) or 4.5V ≤ V ≤ 5.5V (LTC2635-H).

CC

ꢀypass to GND with a 0.1µF capacitor.

V

to V

(Pins 2, 3, 8, 9/Pins 1, 2, 11, 12): DAC

OUTA

OUTD

Analog Voltage Outputs.

LDAC (Pin 3, QFN Only): Asynchronous DAC Update. A

falling edge on this input after four bytes (slave address

byte plus three data bytes) have been written into the part

immediately updates the DAC registers with the contents

of the input registers (similar to a software update). A

low on this input without a complete 32-bit (four bytes

including the slave address) data write transfer to the part

does not update the DAC output. A low on the LDAC pin

powers up the DACs. A software power down command

is ignored if LDAC is low.

DNC (Pins 6, 15, QFN Only): Do Not Connect These Pins.

CA2 (Pin 7, QFN Only): Chip Address ꢀit 2. Tie this pin to

V_CC, GND or leave it floating to select an I²C slave address

for the part (see Table 1).

CA1 (Pin 9, QFN Only): Chip Address ꢀit 1. Tie this pin to

V_CC, GND or leave it floating to select an I²C slave address

for the part (see Table 1).

CA0 (Pin 4/Pin 4): Chip Address ꢀit 0. Tie this pin to V ,

CC

2

GND or leave it floating to select an I C slave address for

GND (Pin 10, Exposed Pad Pin 11/Pin 14, Exposed Pad

Pin 17): Ground. Must be soldered to PCꢀ ground.

the part (see Tables 1 and 2).

SCL (Pin 5/Pin 5): Serial Clock Input Pin. Data is shifted

into the SDA pin at the rising edges of the clock. This

high-impedance pin requires a pull-up resistor or current

REFLO (Pin 13, QFN Only): Reference Low Pin. The volt-

age at this pin sets the zero-scale voltage of all DACs. This

pin must be tied to GND.

source to V .

CC

SDA (Pin 6/Pin 8): Serial Data ꢀidirectional Pin. Data is

shifted into the SDA pin and acknowledged by the SDA

pin. This pin is high impedance while data is shifted in.

Open drain N-channel output during acknowledgment.

SDA requires a pull-up resistor or current source to V .

CC

Rev D

17

For more information www.analog.com

LTC2635

BLOCK DIAGRAM

Rꢀꢋ

ꢂꢒꢄꢀRꢒꢅꢌ

RꢀꢋꢀRꢀꢒꢆꢀ

ꢁꢒD

ꢃꢗꢂꢄꢆꢘ

ꢇ

Rꢀꢋ

ꢇ

ꢊRꢀꢋꢌꢈꢍ

ꢆꢆ

ꢇ

ꢈꢉꢄꢅ

ꢈꢉꢄD

Dꢅꢆ ꢅ

Dꢅꢆ ꢖ

Dꢅꢆ D

Dꢅꢆ ꢆ

ꢇ

Rꢀꢋ

ꢇ

Rꢀꢋ

ꢇ

ꢈꢉꢄꢆ

ꢈꢉꢄꢖ

ꢊLDACꢍ

DꢀꢆꢈDꢀ

ꢓꢈꢗꢀRꢙꢈꢒ

Rꢀꢃꢀꢄ

ꢆꢅꢎ

ꢐ

ꢂ ꢆ

ꢅDDRꢀꢃꢃ

DꢀꢆꢈDꢀ

ꢊꢆꢅꢏꢍ

ꢊꢆꢅꢐꢍ

ꢃꢆꢌ

ꢃDꢅ

ꢐ

ꢂ ꢆ ꢂꢒꢄꢀRꢋꢅꢆꢀ

ꢐꢚꢛꢜ ꢖD

ꢊ ꢍ ꢑꢋꢒ ꢓꢅꢆꢔꢅꢁꢀ ꢈꢒꢌꢕ

Rev D

18

For more information www.analog.com

LTC2635

TEST CIRCUITS

Test Circuits for I²C Digital I/O (See Electrical Characteristics)

Test Circuit 1

Test Circuit 2

ꢍ

DD

100Ω

/V

CAn

R

ꢊR ꢊR

ꢇꢈꢉ ꢇꢈꢋ ꢇꢈꢌ

ꢅꢏn

V

IH(CAn) IL(CAn)

2635 TC01

ꢀꢁꢂꢃ ꢄꢅꢆꢀ

ꢎꢈD

TIMING DIAGRAMS

SDA

t

SU(DAT)

t

BUF

t

f

t

SP

t

r

t

LOW

t

r

HD(STA)

r

SCL

t

SU(STO)

HD(STA)

SU(STA)

t

S

HIGH

Sr

P

S

t

HD(DAT)

2635 F01

ꢀꢁꢁ ꢂꢃꢁꢄꢀꢅꢆ ꢁꢆꢂꢆꢁꢇ RꢆꢈꢆR ꢄꢃ ꢂ

ꢀꢍD ꢂ

ꢁꢆꢂꢆꢁꢇ

ꢉꢊꢋꢌꢉꢍꢎ

ꢉꢁꢋꢌꢀꢏꢎ

Figure 1. I²C Timing

Rev D

19

For more information www.analog.com

LTC2635

TIMING DIAGRAMS

ꢍꢏꢅꢐꢑ ꢅDDRꢑꢍꢍ

ꢍꢎꢅRꢎ

ꢃꢍꢎ Dꢅꢎꢅ ꢒꢓꢎꢑ

ꢂꢔD Dꢅꢎꢅ ꢒꢓꢎꢑ

ꢁRD Dꢅꢎꢅ ꢒꢓꢎꢑ

ꢍDꢅ

ꢍꢀꢏ

ꢗ

ꢈ

ꢗ

ꢊ

ꢗ

ꢋ

ꢅꢉ ꢅꢈ ꢅꢇ ꢅꢁ ꢅꢂ ꢅꢃ ꢅꢄ

W

ꢅꢀꢆ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢅꢁ ꢅꢂ ꢅꢃ ꢅꢄ ꢅꢀꢆ

ꢅꢀꢆ

ꢌ

ꢅꢀꢆ

ꢌ

ꢃ

ꢂ

ꢁ

ꢇ

ꢈ

ꢉ

ꢊ

ꢋ

ꢌ

ꢃ

ꢂ

ꢁ

ꢇ

ꢈ

ꢉ

ꢊ

ꢋ

ꢌ

ꢃ

ꢂ

ꢁ

ꢇ

ꢈ

ꢉ

ꢊ

ꢋ

ꢃ

ꢂ

ꢁ

ꢇ

ꢉ

t

1

t

2

LDAC

ꢂꢉꢁꢈ ꢕꢄꢂꢖ

Figure 2a. Typical LTC2635 Write Transaction

ꢀꢁꢂ ꢃꢄꢅꢃꢆ

ꢅꢇ ꢈRD

Dꢉꢁꢉ ꢊꢋꢁꢌ

ꢍꢃꢄ

t

1

LDAC

2635 F02b

Figure 2b. LTC2635 LDAC Timing (QFN Package Only)

Rev D

20

For more information www.analog.com

LTC2635

OPERATION

The LTC2635 is a family of quad voltage output DACs in

16-pin QFN and 10-lead MSOP packages. Each DAC can

operate rail-to-rail using an external reference, or with its

full-scale voltage set by an integrated reference. Eighteen

combinations of accuracy (12-, 10-, and 8-bit), power-on

reset value (zero-scale, mid-scale in internal reference

mode, or mid-scale in external reference mode), DAC

power-down output load (high impedance or 200kΩ),

and full-scale voltage (2.5V or 4.096V) are available. The

taken to observe these limits during power supply turn-on

and turn-off sequences, when the voltage at V_CCis in

transition.

Transfer Function

The digital-to-analog transfer function is

⎛

⎞

k

V

=

V

– V

+ V

(

)

⎜

⎟

OUT(IDEAL)

REF

REFLO REFLO

N

⎝

⎠

2

LTC2635 is controlled using a 2-wire I C interface.

where k is the decimal equivalent of the binary DAC

input code, N is the resolution, and V is either 2.5V

Power-On Reset

REF

(LTC2635-LMI/-LMX/-LMO/-LZ) or 4.096V (LTC2635-

HMI/-HZ) when in Internal Reference mode, and the volt-

age at REF when in External Reference mode.

The LTC2635-HZ/-LZ clear the output to zero-scale

when power is first applied, making system initialization

con-sistent and repeatable.

2

I C Serial Interface

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2635

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero-

scale during power on. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

The LTC2635 communicates with a host using the stan-

2

dard 2-wire I C interface. The timing diagrams (Figures

1 and 2) show the timing relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources are required on these lines. The value of

these pull-up resistors is dependent on the power supply

2

and can be obtained from the I C specifications. For an

2

I C bus operating in the fast mode, an active pull-up will

The LTC2635-HMI/-LMI/-LMX provide an alternative

reset, setting the output to mid-scale when power is first

applied. The LTC2635-LMI and LTC2635-HMI power

up in internal reference mode, with the output set to a

mid-scale voltage of 1.25V and 2.048V, respectively. The

LTC2635-LMX power-up in external reference mode, with

the output set to mid-scale of the external reference. The

LTC2635-LMO powers up in internal reference mode with

all the DAC channels placed in the high-impedance state

(powered-down). Input and DAC registers are set to the

mid-scale code, and only the internal reference is powered

up, causing supply current to be typically 100µA upon

power up. Default reference mode selection is described

in the Reference Modes section.

be necessary if the bus capacitance is greater than 200pF.

The LTC2635 is a receive-only (slave) device. The master

can write to the LTC2635. The LTC2635 will not acknowl-

edge (NAK) a read request from the master.

START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition. A

START condition is generated by transitioning SDA from

high to low while SCL is high.

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

Power Supply Sequencing

The voltage at REF (Pin 10 – QFN, Pin 7 – MSOP) must

2

another I C device.

be kept within the range –0.3V ≤ V

≤ V + 0.3V (see

Absolute Maximum Ratings). Parti^Rc^Eu^Flar c^Ca^Cre should be

Rev D

21

For more information www.analog.com

LTC2635

OPERATION

Acknowledge

Table 1. Slave Address Map (QFN Package)

CA2

CA1

CA0

A6

0

1

A5

0

1

0

1

A4

1

0

1

0

1

0

1

A3

0

A2

0

A1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

The Acknowledge (ACK) signal is used for handshaking

between the master and the slave. An ACK (active LOW)

generated by the slave lets the master know that the lat-

est byte of information was properly received. The ACK

related clock pulse is generated by the master. The mas-

ter releases the SDA line (HIGH) during the ACK clock

pulse. The slave-receiver must pull down the SDA bus

line during the ACK clock pulse so that it remains a sta-

ble LOW during the HIGH period of this clock pulse. The

LTC2635 responds to a write by a master in this manner

but does not acknowledge a read operation; in that case,

SDA is retained HIGH during the period of the ACK clock

pulse.

GND

GND FLOAT

GND

V

CC

FLOAT GND

FLOAT FLOAT

FLOAT

V

CC

V

GND

CC

V

FLOAT

CC

V

CC

FLOAT GND

FLOAT GND FLOAT

FLOAT GND

GND

V

CC

FLOAT FLOAT GND

FLOAT FLOAT FLOAT

Chip Address

FLOAT FLOAT

V

CC

The state of pins CA0, CA1 and CA2 (CA1 and CA2 are

only available on the QFN package) determines the slave

address of the part. These pins can be each set to any one

FLOAT

V

GND

CC

FLOAT

of three states: V , GND or float. This results in 27 (QFN

V

CC

Package) or 3 (MSOP Package) selectable addresses for

the part. The slave address assignments are shown in

Tables 1 and 2.

V

GND

GND FLOAT

GND

CC

V

CC

FLOAT GND

FLOAT FLOAT

In addition to the address selected by the address pins,

the part also responds to a global address. This address

allows a common write to all LTC2635 parts to be ac-com-

FLOAT

V

CC

2

V

CC

V

CC

V

CC

GND

plished using one 3-byte write transaction on the I C bus.

FLOAT

The global address, listed at the end of Tables 1 and 2,

is a 7-bit hardwired address not selectable by CA0, CA1

or CA2. If another address is required, please consult the

factory.

V

CC

GLOꢀAL ADDRESS

The maximum capacitive load allowed on the address pins

(CA0, CA1 and CA2) is 10pF, as these pins are driven

during address detection to determine if they are floating.

Table 2. Slave Address Map (MSOP Package)

CA0

GND

A6

0

A5

0

A4

1

A3

0

A2

A1

A0

0

1

FLOAT

0

1

0

1

V

0

1

0

CC

GLOꢀAL ADDRESS

1

0

1

Rev D

22

For more information www.analog.com

LTC2635

OPERATION

Write Word Protocol

DAC if it had been in power-down mode. The data path

and registers are shown in the ꢀlock Diagram.

The master initiates communication with the LTC2635

with a START condition and a 7-bit slave address followed

by the Write bit (W) = 0. The LTC2635 acknowledges by

pulling the SDA pin low at the 9th clock if the 7-bit slave

address matches the address of the part (set by CA0, CA1

or CA2) or the global address. The master then transmits

three bytes of data. The LTC2635 acknowledges each byte

of data by pulling the SDA line low at the 9th clock of each

data byte transmission. After receiving three complete

bytes of data, the LTC2635 executes the command spec-

ified in the 24-bit input word.

Table 3. Command Codes

COMMAND*

C3 C2 C1 C0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to Input Register n

Update (Power Up) DAC Register n

Write to Input Register n, Update (Power Up) All

Write to and Update (Power Up) DAC Register n

Power Down n

Power Down Chip (All DAC’s and Reference)

Select Internal Reference (Power Up Reference)

Select External Reference (Power Down Internal

Reference)

If more than three data bytes are transmitted after a valid

7-bit slave address, the LTC2635 does not acknowledge

(NAK) the extra bytes of data (SDA is high during the 9th

clock).

1

No Operation

*Command codes not shown are reserved and should not be used.

The format of the three data bytes is shown in Figure 3.

The first byte of the input word consists of the 4-bit com-

mand, followed by the 4-bit DAC address. The next two

bytes contain the 16-bit data word, which consists of the

12-, 10- or 8-bit input code, MSꢀ to LSꢀ, followed by 4,

6 or 8 don’t-care bits (LTC2635-12, -10 and -8, respec-

tively). A typical LTC2635 write transaction is shown in

Figure 4.

Table 4. Address Codes

ADDRESS (n)*

A3 A2 A1 A0

0

1

0

1

0

1

0

1

0

1

DAC A

DAC ꢀ

DAC C

DAC D

ALL DACs

The command bit assignments (C3-C0) and address (A3-

A0) assignments are shown in Tables 3 and 4. The first

four commands in the table consist of write and update

operations. A write operation loads a 16-bit data word

from the 32-bit shift register into the input register. In an

update operation, the data word is copied from the input

register to the DAC register. Once copied into the DAC

register, the data word becomes the active 12-, 10-, or

8-bit input code, and is converted to an analog voltage at

the DAC output. Write to and Update combines the first

two commands. The Update operation also powers up the

* Address codes not shown are reserved and should not be used.

Reference Modes

For applications where an accurate external reference is

either not available, or not desirable due to limited space,

the LTC2635 has a user-selectable, integrated reference.

The integrated reference voltage is internally amplified

by 2x to provide the full-scale DAC output voltage range.

The LTC2635-LMI/-LMX/-LMO/-LZ provides a full-scale

output of 2.5V. The LTC2635-HMI/-HZ provides a full-

scale output of 4.096V. The internal reference can be

useful in applications where the supply voltage is poorly

regulated. Internal Reference mode can be selected by

Rev D

23

For more information www.analog.com

LTC2635

OPERATION

Write Word Protocol for LTC2635

ꢃ

W

ꢅꢀꢚ

ꢅꢂ

ꢂꢃꢄ Dꢅꢄꢅ ꢆꢇꢄꢈ

ꢅꢀꢚ

ꢉꢊD Dꢅꢄꢅ ꢆꢇꢄꢈ

ꢓꢊꢔꢕꢄ ꢖꢗRD

ꢅꢀꢚ

Dꢐ

ꢁRD Dꢅꢄꢅ ꢆꢇꢄꢈ

ꢅꢀꢚ

Dꢂ

ꢒ

ꢔ

ꢃꢘꢅꢙꢈ ꢅDDRꢈꢃꢃ

Input Word (LTC2635-12)

ꢀꢁ

ꢅꢁ

ꢅꢉ

ꢅꢋ

Dꢍ

ꢀꢂ

Dꢎ

Dꢏ

Dꢑ

Dꢉ

Dꢑ

Dꢂꢂ Dꢂꢋ Dꢌ

Dꢁ

Dꢂ

ꢒ

Dꢉ

Dꢋ

ꢒ

Dꢋ

ꢒ

ꢀꢉ

ꢀꢋ

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ꢉꢊD Dꢅꢄꢅ ꢆꢇꢄꢈ

ꢁRD Dꢅꢄꢅ ꢆꢇꢄꢈ

Input Word (LTC2635-10)

ꢒ

ꢅꢁ

ꢀꢋ

ꢅꢉ

Dꢏ

ꢀꢁ

ꢀꢉ

ꢅꢂ

Dꢐ

Dꢁ

Dꢂ

Dꢉ

Dꢋ

Dꢌ

Dꢎ

Dꢍ

Dꢏ

Dꢎ

Dꢐ

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ꢉꢊD Dꢅꢄꢅ ꢆꢇꢄꢈ

ꢁRD Dꢅꢄꢅ ꢆꢇꢄꢈ

Input Word (LTC2635-8)

ꢅꢁ

ꢀꢋ

Dꢑ

ꢒ

ꢀꢁ

ꢀꢉ

Dꢁ

ꢂꢃꢄ Dꢅꢄꢅ ꢆꢇꢄꢈ

ꢉꢊD Dꢅꢄꢅ ꢆꢇꢄꢈ

ꢁRD Dꢅꢄꢅ ꢆꢇꢄꢈ

ꢉꢏꢁꢐ ꢛꢋꢁ

Figure 3. Command and Data Input Format

using command 0110b, and is the power-on default for

LTC2635-HZ/-LZ, as well as for LTC2635-HMI/-LMI/-LMO.

by software command after power up. The same is true

for LTC2635-LMX (External Reference power-on default).

The 10ppm/°C, 1.25V (LTC2635-LMI/-LMX/-LMO/-LZ) or

2.048V (LTC2635-HMI/-HZ) internal reference is available

at the REF pin. Adding bypass capacitance to the REF pin

will improve noise performance; and up to 10µF can be

driven without oscillation. This output must be buffered

when driving an external DC load current.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than four DAC outputs are needed. When in power-down,

the buffer amplifiers, bias circuits, and integrated reference

circuits are disabled, and draw essentially zero current.

The DAC amplifier outputs are put into a high-impedance

state, and the output pins are passively pulled to ground

through individual 200k resistors (LTC2635-LMI/-LMX/

-LZ/-HMI/-HZ). For the LTC2635-LMO options, the out-

put pins are not passively pulled to ground, but are also

placed in a high-impedance state (open-circuited state)

during power-down, typically drawing less than 0.1µA.

The LTC2635-LMO options power-up with all DAC outputs

in this high-impedance state. They remain that way until

Alternatively, the DAC can operate in External Reference

mode using command 0111b. In this mode, an input

voltage supplied externally to the REF pin provides the

reference (1V ≤ V

≤ V ) and the supply current is

REF

CC

reduced. The external reference voltage supplied sets the

full-scale DAC output voltage. External Reference mode

is the power-on default for LTC2635-LMX.

The reference mode of LTC2635-HZ/-LZ/-HMI/-LMI/-LMO

(Internal Reference power-on default), can be changed

Rev D

24

For more information www.analog.com

LTC2635

OPERATION

given a software or hardware update command. For all

LTC2635 options, input- and DAC-register contents are

not disturbed during power-down.

Load regulation is a measure of the amplifier’s ability to

maintain the rated voltage accuracy over a wide range of

load current. The measured change in output voltage per

change in forced load current is expressed in LSꢀ/mA.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in com

-

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change

in units from LSꢀ/mA to Ω. The amplifier’s DC output

impedance is 0.1Ω when driving a load well away from

the rails.

bi-nation with the appropriate DAC address, (n). The sup-

ply current is reduced approximately 20% for each DAC

powered down. The integrated reference is automatically

powered down when external reference is selected using

command 0111b. In addition, all the DAC channels and

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by the

50Ω typical channel resistance of the output devices (e.g.,

when sinking 1mA, the minimum output voltage is 50Ω

• 1mA, or 50mV). See the graph Headroom at Rails vs.

Output Current in the Typical Performance Characteristics

section.

the integrated reference together can be put into pow

-

er-down mode using Power Down Chip command 0101b.

When the integrated reference is in power-down mode,

the REF pin becomes high impedance (typically > 1GΩ).

For all power-down commands the 16-bit data word is

ignored.

Normal operation resumes after executing any command

that includes a DAC update, (as shown in Table 1) or pull-

ing the asynchronous LDAC pin low (QFN package only).

The selected DAC is powered up as its voltage output is

updated. When a DAC which is in a powered-down state

is powered up and updated, normal settling is delayed. If

less than four DACs are in a powered-down state prior to

the update command, the power-up delay time is 10µs.

However, if all four DACs and the integrated reference are

powered down, then the main bias generation circuit block

has been automatically shut down in addition to the DAC

amplifiers and reference buffers. In this case, the power

up delay time is 12µs. The power-up of the integrated

reference depends on the command that powered it down.

If the reference is powered down using the Select External

Reference Command (0111b), then it can only be pow-

ered back up using Select Internal Reference Command

(0110b). However, if the reference was powered down

using Power Down Chip Command (0101b), then in addi-

tion to Select Internal Reference Command (0110b), any

command (in software or using the LDAC pin) that powers

up the DACs will also power up the integrated reference.

The amplifier is stable driving capacitive loads of up to

500pF.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is lim-

ited to voltages within the supply range.

Since the analog output of the DAC cannot go below

ground, it may limit for the lowest codes as shown in

Figure 5b. Similarly, limiting can occur near full-scale

when the REF pin is tied to V . If V

= V and the

CC

REF

CC

DAC full-scale error (FSE) is positive, the output for the

highest codes limits at V_CC, as shown in Figure 5c. No

full-scale limiting can occur if V is less than V – FSE.

REF

CC

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.

Board Layout

The PC board should have separate areas for the analog

and digital sections of the circuit. A single, solid ground

plane should be used, with analog and digital signals care-

fully routed over separate areas of the plane. This keeps

digital signals away from sensitive analog signals and

minimizes the interaction between digital ground currents

and the analog section of the ground plane. The resistance

Voltage Output

The LTC2635’s integrated rail-to-rail amplifier has

guar-anteed load regulation when sourcing or sinking up

to 10mA at 5V, and 5mA at 3V.

Rev D

25

For more information www.analog.com

LTC2635

OPERATION

from the LTC2635 GND pin to the ground plane should

be as low as possible. Resistance here will add directly to

the effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2635 is no more susceptible to

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

analog ground, digital ground, and power ground. When

the LTC2635 is sinking large currents, this current flows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

It is sometimes necessary to interrupt the ground plane

to confine digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

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ꢌꢋ Dꢅꢎꢅ

ꢅꢒ ꢅꢓ ꢅꢔ ꢅꢁ ꢅꢂ ꢅꢃ ꢅꢄ

W

ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢅꢁ ꢅꢂ ꢅꢃ ꢅꢄ

Dꢃꢃ Dꢃꢄ Dꢏ Dꢐ Dꢑ Dꢒ Dꢓ Dꢔ

Dꢁ Dꢂ Dꢃ Dꢄ

ꢖ

ꢒ

ꢖ

ꢑ

ꢖ

ꢐ

ꢋꢎꢆꢗ

ꢋꢎꢅRꢎ

ꢋDꢅ

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W

ꢅꢀꢕ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢅꢁ ꢅꢂ ꢅꢃ ꢅꢄ ꢅꢀꢕ

ꢅꢀꢕ

ꢏ

ꢅꢀꢕ

ꢏ

ꢃ

ꢂ

ꢁ

ꢔ

ꢓ

ꢒ

ꢑ

ꢐ

ꢏ

ꢃ

ꢂ

ꢁ

ꢔ

ꢓ

ꢒ

ꢑ

ꢐ

ꢏ

ꢃ

ꢂ

ꢁ

ꢔ

ꢓ

ꢒ

ꢑ

ꢐ

ꢃ

ꢂ

ꢁ

ꢔ

ꢓ

ꢘꢙꢌꢌꢚꢋꢀꢅꢌꢊ

ꢍꢆꢌꢎꢅꢛꢊ

ꢍ

ꢆꢙꢎ

ꢜꢊRꢆꢚꢋꢀꢅꢌꢊ

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ꢖ ꢝ Dꢆꢈꢞꢎ ꢀꢅRꢊ

ꢂꢒꢁꢓ ꢘꢄꢔ

Figure 4. Typical LTC2635 Input Waveform—Programming DAC Output for Full-Scale

Rev D

26

For more information www.analog.com

LTC2635

OPERATION

ꢈꢌꢒꢆꢊꢆꢎꢍ

ꢄꢒꢍ

ꢎ

Rꢍꢄ

ꢗ ꢎ

ꢋꢋ

ꢎ

ꢗ ꢎ

ꢋꢋ

Rꢍꢄ

ꢌꢉꢊꢈꢉꢊ

ꢎꢌꢏꢊꢐꢑꢍ

ꢌꢉꢊꢈꢉꢊ

ꢎꢌꢏꢊꢐꢑꢍ

ꢆꢇꢈꢉꢊ ꢋꢌDꢍ

ꢀꢁꢂꢃ ꢄꢅꢃ

ꢌꢉꢊꢈꢉꢊ

ꢎꢌꢏꢊꢐꢑꢍ

(c)

ꢅꢎ

ꢅ

ꢀꢓꢅꢔꢕ

ꢔꢓꢅꢖꢃ

ꢆꢇꢈꢉꢊ ꢋꢌDꢍ

(a)

ꢅꢎ

ꢇꢍꢑꢐꢊꢆꢎꢍ

ꢌꢄꢄꢒꢍꢊ

ꢆꢇꢈꢉꢊ ꢋꢌDꢍ

(b)

Figure 5. Effects of Rail-to-Rail On a DAC Transfer Curve (Shown for 12 Bits).

(a) Overall Transfer Function

(b) Effect of Negative Offset for Codes Near Zero

(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale

Rev D

27

For more information www.analog.com

LTC2635

APPLICATION INFORMATION

Voltage Margining Application with LTC3850 (1.2V 5%) –LTC2635– LMO Option Only

V

IN

6.5V TO 14V

0.1µF

4.7µF

2.2Ω

100k

0.1µF

INTV

PGOOD

V

CC

IN

I

TG1

LIM

0.1µF

10k

BOOST1

SW1

FREQ

2.2µH

0.008Ω

V

OUT

1.2V 5ꢀ

LTC3850EUF

3.32k

1nF

BG1

PGND

10Ω

I

TH1

+

SENSE

RUN1

1nF

500kHz

MODE/PLLIN

TK/SS1

1nF

100pF

–

SENSE

10k

10nF

V

FB1

SGND

15pF

63.4k

5V

2635 TA02

20k

DAC D

OUTPUT DAC CODE

1

9

7

REF

V

CC

V

OUT

0.1µF

LTC2635CMSE-LMOI2

1.26V

1.2V

1.14V

0.5V

0.8V

1.1V

819

1311

1802

10k

15k

0.22µF

2

3

DAC A

DAC B

DAC D

DAC C

8

10

4

5

6

CAO

SCL

SDA

GND

2

TO I C

BUS

2635 TA02

Rev D

28

For more information www.analog.com

LTC2635

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2635#packaging for the most recent package drawings.

UD Package

16-Lead Plastic QFN (3mm × 3mm)

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ꢃꢁꢅꢓ ±ꢂꢁꢂꢓ

ꢄꢅ ꢆꢇDꢈꢆꢉ

ꢏꢐꢊꢙꢐꢖꢈ ꢋꢚꢑꢎꢇꢍꢈ

ꢂꢁꢜꢓ ±ꢂꢁꢂꢓ

ꢂꢁꢓꢂ ꢟꢆꢊ

RꢈꢊꢋꢌꢌꢈꢍDꢈD ꢆꢋꢎDꢈR ꢏꢐD ꢏꢇꢑꢊꢒ ꢐꢍD Dꢇꢌꢈꢍꢆꢇꢋꢍꢆ

ꢟꢋꢑꢑꢋꢌ ꢝꢇꢈꢕꢤꢈꢞꢏꢋꢆꢈD ꢏꢐD

ꢏꢇꢍ ꢃ ꢍꢋꢑꢊꢒ R ꢦ ꢂꢁꢜꢂ ꢑꢢꢏ

ꢋR ꢂꢁꢜꢓ × ꢅꢓ° ꢊꢒꢐꢌꢗꢈR

R ꢦ ꢂꢁꢃꢃꢓ

ꢑꢢꢏ

ꢂꢁꢥꢓ ±ꢂꢁꢂꢓ

ꢀꢁꢂꢂ ±ꢂꢁꢃꢂ

ꢄꢅ ꢆꢇDꢈꢆꢉ

ꢃꢓ ꢃꢣ

ꢏꢇꢍ ꢃ

ꢑꢋꢏ ꢌꢐRꢙ

ꢄꢍꢋꢑꢈ ꢣꢉ

ꢂꢁꢅꢂ ±ꢂꢁꢃꢂ

ꢃ

ꢜ

ꢃꢁꢅꢓ ± ꢂꢁꢃꢂ

ꢄꢅꢛꢆꢇDꢈꢆꢉ

ꢄꢚDꢃꢣꢉ ꢨꢗꢍ ꢂꢩꢂꢅ

ꢂꢁꢜꢂꢂ Rꢈꢗ

ꢂꢁꢜꢓ ±ꢂꢁꢂꢓ

ꢂꢁꢂꢂ ꢧ ꢂꢁꢂꢓ

ꢂꢁꢓꢂ ꢟꢆꢊ

ꢍꢋꢑꢈꢔ

ꢃꢁ DRꢐꢕꢇꢍꢖ ꢊꢋꢍꢗꢋRꢌꢆ ꢑꢋ ꢘꢈDꢈꢊ ꢏꢐꢊꢙꢐꢖꢈ ꢋꢚꢑꢎꢇꢍꢈ ꢌꢋꢛꢜꢜꢂ ꢝꢐRꢇꢐꢑꢇꢋꢍ ꢄꢕꢈꢈDꢛꢜꢉ

ꢜꢁ DRꢐꢕꢇꢍꢖ ꢍꢋꢑ ꢑꢋ ꢆꢊꢐꢎꢈ

ꢀꢁ ꢐꢎꢎ Dꢇꢌꢈꢍꢆꢇꢋꢍꢆ ꢐRꢈ ꢇꢍ ꢌꢇꢎꢎꢇꢌꢈꢑꢈRꢆ

ꢅꢁ Dꢇꢌꢈꢍꢆꢇꢋꢍꢆ ꢋꢗ ꢈꢞꢏꢋꢆꢈD ꢏꢐD ꢋꢍ ꢟꢋꢑꢑꢋꢌ ꢋꢗ ꢏꢐꢊꢙꢐꢖꢈ Dꢋ ꢍꢋꢑ ꢇꢍꢊꢎꢚDꢈ

ꢌꢋꢎD ꢗꢎꢐꢆꢒꢁ ꢌꢋꢎD ꢗꢎꢐꢆꢒꢠ ꢇꢗ ꢏRꢈꢆꢈꢍꢑꢠ ꢆꢒꢐꢎꢎ ꢍꢋꢑ ꢈꢞꢊꢈꢈD ꢂꢁꢃꢓꢡꢡ ꢋꢍ ꢐꢍꢢ ꢆꢇDꢈ

ꢓꢁ ꢈꢞꢏꢋꢆꢈD ꢏꢐD ꢆꢒꢐꢎꢎ ꢟꢈ ꢆꢋꢎDꢈR ꢏꢎꢐꢑꢈD

ꢣꢁ ꢆꢒꢐDꢈD ꢐRꢈꢐ ꢇꢆ ꢋꢍꢎꢢ ꢐ RꢈꢗꢈRꢈꢍꢊꢈ ꢗꢋR ꢏꢇꢍ ꢃ ꢎꢋꢊꢐꢑꢇꢋꢍ

ꢋꢍ ꢑꢒꢈ ꢑꢋꢏ ꢐꢍD ꢟꢋꢑꢑꢋꢌ ꢋꢗ ꢏꢐꢊꢙꢐꢖꢈ

Rev D

29

For more information www.analog.com

LTC2635

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2635#packaging for the most recent package drawings.

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev I)

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.88

(.074)

1.88 ±0.102

(.074 ±.004)

0.889 ±0.127

(.035 ±.005)

1

0.29

REF

1.68

(.066)

0.05 REF

5.10

(.201)

MIN

1.68 ±0.102

3.20 – 3.45

DETAIL “B”

(.066 ±.004) (.126 – .136)

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

10

NO MEASUREMENT PURPOSE

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ±.0015)

TYP

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

0.497 ±0.076

(.0196 ±.003)

10 9

8

7 6

RECOMMENDED SOLDER PAD LAYOUT

REF

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

4.90 ±0.152

(.193 ±.006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

1

2

3

4 5

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.1016 ±0.0508

(.004 ±.002)

0.50

(.0197)

BSC

MSOP (MSE) 0213 REV I

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

Rev D

30

For more information www.analog.com

LTC2635

REVISION HISTORY

REV

DATE

12/09 Revise QFN pin names.

Minor text edit in Operations section.

DESCRIPTION

PAGE NUMBER

A

2, 17

21, 24

11

ꢀ

06/10 Revised Note 3 in the Electrical Characteristics section.

Added Typical Application drawing and revised Related Parts List.

32

C

D

05/17 Corrected V slew rate requirement when operating above 90°C and with V > 4V.

11

CC

04/18 Edits to Note 3.

11

Rev D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

31

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTC2635

TYPICAL APPLICATION

Voltage Margining Application with LTC3850 (1.2V 5%) –LTC2635– LMO Option Only

V

IN

6.5V TO 14V

0.1µF

4.7µF

2.2Ω

100k

0.1µF

INTV

PGOOD

V

CC

TG1

IN

I

LIM

0.1µF

10k

FREQ

BOOST1

SW1

2.2µH

0.008Ω

V

OUT

1.2V 5ꢀ

3.32k

1nF

BG1

LTC3850EUF

PGND

10Ω

+

SENSE

I

TH1

RUN1

1nF

–

1nF

SENSE

500kHz

MODE/PLLIN

TK/SS1

100pF

V

10k

FB1

SGND

10nF

15pF

63.4k

5V

1

9

7

REF

V

CC

LTC2635CMSE-LMOI2

0.1µF

2635 TA02

20k

10k

15k

0.22µF

DAC D

OUTPUT DAC CODE

2

3

DAC A

DAC B

DAC D

DAC C

V

OUT

1.26V

1.2V

1.14V

0.5V

0.8V

1.1V

819

1311

1802

8

10

4

5

6

CAO

SCL

SDA

GND

2

TO I C

BUS

2635 TA03

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

2

LTC2654/LTC2655 Quad 16-/12 ꢀit, SPI/I C V

Maximum Reference

DACs with 10ppm/°C

4LSꢀ INL Maximum at 16 ꢀits and 2mV Offset Error, Rail-to-Rail Output,

20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages

OUT

2

LTC2609/

LTC2619/ LTC2629

Quad 16-/14-/12-ꢀit V

DACs with I C Interface

250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with

OUT

Separate V Pins for Each DAC

REF

LTC2604/

Quad 16-/14-/12-ꢀit, SPI V

DACs with External

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 16-Lead

SSOP Package

OUT

LTC2614/LTC2624 Reference

LTC2634

Quad 12-/10-/8-ꢀit SPI V

DACs with 10ppm/°C

125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External

REF Mode, Rail-to-Rail Output, 16-Pin 3mm × 3mm QFN and 10-Lead MSOP

Packages

OUT

Reference

2

LTC2656/LTC2657 Octal 16-/12 ꢀit, SPI/I C V

DACs with 10ppm/°C

4LSꢀ INL Maximum at 16 ꢀits and 2mV Offset Error, Rail-to-Rail Output,

20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages

OUT

Maximum Reference

2

LTC2636/LTC2637 Octal 12-/10-/8-ꢀit, SPI/I C V

10ppm/°C Reference

DACs with

125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External

REF Mode, Rail-to-Rail Output, 14-Lead 4mm × 3mm DFN and 16-Lead

MSOP Packages

OUT

2

LTC2630/LTC2631 Single 12-/10-/8-ꢀit, SPI/ I C V

10ppm/°C Reference

DACs with

180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

Rail-to-Rail Output, SC70 (LTC2630)/ThinSOT™ (LTC2631) Packages

OUT

LTC2640

Single 12-/10-/8-ꢀit, SPI V

Reference

DACs with 10ppm/°C 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External

REF Mode, Rail-to-Rail Output, ThinSOT Package

OUT

LTC1664

Quad 10-ꢀit, Serial V

DAC

V

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output, 16-Pin Narrow SSOP

CC

OUT

Rev D

D16867-0-5/18(D)

www.analog.com

32

 ANALOG DEVICES, INC. 2009-2018

For more information www.analog.com


型号：	LTC2635HMSE-LZ10#TRPBF
厂家：	ADI
描述：	Quad 12-/10-/8-Bit I<sup>2</sup>C VOUT DACs with 10ppm/°C Reference 光电二极管转换器
文件：	总32页 (文件大小：728K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2635HMSE-LZ10#TRPBF [ADI]

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