LTC2672CUH-16 [ADI]
Five-Channel, Low Dropout, 300 mA, Current Source Output, 16-Bit SoftSpan DAC;
| 型号： | LTC2672CUH-16 |
| 厂家： | 
ADI |
| 描述： | Five-Channel, Low Dropout, 300 mA, Current Source Output, 16-Bit SoftSpan DAC |
| 文件： | 总26页 (文件大小：541K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Five-Channel, Low Dropout, 300 mA,
Current Source Output, 16-Bit SoftSpan DAC
Data Sheet
LTC2672
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Per channel programmable output current ranges: 300 mA,
200 mA, 100 mA, 50 mA, 25 mA, 12.5 mA, 6.25 mA, and
3.125 mA
Flexible 2.1 V to VCC output supply voltages
Flexible single- or dual-supply operation
0.6 V maximum dropout voltage guaranteed
Separate voltage supply per output channel
Internal switches to optional negative supply
Full 16-bit resolution at all ranges
Guaranteed operation −40°C to 125°C (H-grade)
Precision internal reference (10 ppm/°C maximum VREF
temperature coefficient) or external reference
Analog multiplexer monitors voltages and currents
A/B toggle via SPI or dedicated pin
LTC2672-16
IO
V
DD0
VCC
29
2
25
TGP
SDI
DAC0
OUT0
24
3
SPAN0
–
–
–
–
–
V
V
V
V
V
SDO
SCK
CS/LD
LDAC
CLR
4
SERIAL
INTERFACE
V
DD1
22
23
5
DAC1
6
OUT1
7
SPAN1
31
V
DD2
21
20
1.71 V to VCC digital I/O supply
32-Lead Lead Frame Chip Scale Package [LFCSP]
GND
1, 8, 14, 32
DAC2
OUT2
APPLICATIONS
FAULT
FAULT
DETECT
30
SPAN2
Tunable lasers
Semiconductor optical amplifier biasing
Resistive heaters
V
DD3
18
19
FSADJ
12
9
Current mode biasing
DAC3
FULL SCALE
ADJUST
OUT3
REFLO
REF
SPAN3
10
11
INTERNAL
REFERENCE
REFCOMP
V
DD4
17
16
V
CC
13, 27
DAC4
OUT4
MUX
ANALOG
MUX
28
–
V
SPAN4
15, 26
Figure 1.
GENERAL DESCRIPTION
The LTC2672-16 is a five-channel, 16-bit current source, digital-
to-analog converter (DAC) that provides five high compliance
current source outputs with guaranteed 600 mV dropout at
200 mA. There are eight current ranges that are programmable per
channel with full-scale outputs of up to 300 mA. The channels
can be paralleled to allow either ultrafine adjustments of large
currents or combined outputs of up to 1.5 A. A dedicated
supply pin is provided for each output channel. Each channel
can be operated from 2.1 V to VCC, and internal switches allow
any output to be pulled to the optional negative supply. The
LTC2672-16 includes a precision integrated 1.25 V reference
(10 ppm/°C maximum), with the option to use an external
reference. The serial peripheral interface (SPI) compatible,
3-wire serial interface operates on logic levels as low as 1.71 V
and at clock rates as high as 50 MHz.
Note than throughout this data sheet, multifunction pins, such
as /LD, are referred to by the entire pin name or by a single
CS
function of the pin.
Rev. 0
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice.
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Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
LTC2672
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Die Temperature Measurement Using the Multiplexer....... 19
Monitor Multiplexer Precharge Considerations ................... 19
Toggle Operations...................................................................... 19
Toggle Select Register (TSR) .................................................... 19
Writing to Input Register A and Input Register B ................ 20
Toggling Between Register A and Register B............................. 20
Daisy-Chain Operation............................................................. 22
Echo Readback............................................................................ 22
Fault Register (FR)..................................................................... 22
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings ........................................................... 8
Thermal Resistance...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions ............................ 9
Typical Performance Characteristics........................................... 11
Terminology.................................................................................... 14
Theory of Operation ...................................................................... 15
Load Termination and Combining Channels........................ 15
Power-On Reset.......................................................................... 15
Power Supply Sequencing......................................................... 15
Data Transfer Functions ........................................................... 15
Applications Information.............................................................. 16
Serial Interface ............................................................................ 16
Input and DAC Registers.......................................................... 16
Output Ranges and SoftSpan Operation................................. 17
Monitor Multiplexer.................................................................. 19
Current Measurement Using the Multiplexer ....................... 19
Fault Indicator Pin (
, Pin 30)...................................... 22
FAULT
Fault Conditions and Thermal Overload Protection............ 22
Configuration Command ......................................................... 23
Power-Down Mode ................................................................... 23
Safe Supply Ranges..................................................................... 23
Current Outputs......................................................................... 23
Switch to V− Mode ..................................................................... 24
Gain Adjustment Using the FSADJ Pin.................................. 24
Offset Current and Code Zero ................................................. 24
Reference Modes ........................................................................ 24
Board Layout............................................................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
12/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 26
Data Sheet
LTC2672
SPECIFICATIONS
All specifications apply over the full operating junction temperature range −40°C to +125°C, unless otherwise noted. Typical values are at
TJ = 25°C, VCC = IOVCC = 5 V, V− = –3.3 V, VDDx = 5 V, FSADJ = VCC, and VREF = 1.25 V external, unless otherwise specified.
Table 1.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
DC PERFORMANCE
Resolution
Monotonicity
Differential Nonlinearity
Integral Nonlinearity
Current Offset Error
IOS Temperature Coefficient
Gain Error
16
16
−1
−64
−0.4
Bits
Bits
LSB
LSB
%FSR
ppm/°C
%FSR
%FSR
All ranges1
DNL
INL
IOS
All ranges1
+0.45 +1
All ranges1
All current ranges1
All current ranges
300 mA and 200 mA output current ranges
100 mA, 50 mA, and 25 mA output current
ranges
+12
+0.1
10
+64
+0.4
GE2
−0.9
−1.2
+0.3
+0.4
+0.9
+1.2
12.5 mA, 6.25 mA, and 3.125 mA output
current ranges
−1.5
+0.7
+1.5
%FSR
Gain Temperature Coefficient
Total Unadjusted Error
FSADJ = VCC
300 mA and 200 mA output current ranges
100 mA, 50 mA, and 25 mA output current
ranges
12.5 mA, 6.25 mA, and 3.125 mA output
current ranges
Range = 100 mA, IOUTx = 50 mA
VCC = 4.75 V to 5.25 V
VDDX = 2.85 V to 3.15 V
VDDX = 4.75 V to 5.25 V
V− = −3.25 V to −2.75 V
Result of a 200 mW change in dissipated power
200 mA range; (VDDX − V−) = 4.75 V
200 mA range; (VDDX – V–) = 2.85 V
300 mA range; (VDDX – V–) = 4.75 V
300 mA range; (VDDX – V–) = 2.85 V
800 Ω load to GND
30
+0.4
+0.5
ppm/°C
%FSR
%FSR
TUE2
PSR
−1.4
−1.7
+1.4
+1.7
−2
+0.8
+2
%FSR
Power Supply Rejection
0.5
0.4
0.7
0.6
0.1
0.45
0.5
0.75
0.85
+0.1
8
LSB
LSB
LSB
LSB
%FSR
V
V
V
V
μA
Ω
DC Crosstalk3
Dropout Voltage (VDDX − VOUTX
4
)
VDROPOUT
0.6
0.65
1.15
+1
12
Off Mode Output Leakage Current5
OUTx Switch to V− Resistance
AC PERFORMANCE
−1
RPULLDOWN Span code = 1000b, sinking 80 mA
TA = 25°C for all ac performance specifications
tSET
Settling Time6, 7
Full-Scale Step 3.125 mA Range
0.0015% ( 1 LSB at 16b)
21.1
3.8
μs
μs
μs
0.024% ( 1 LSB at 12b)
0.0015% ( 1 LSB at 16b)
145 mA to 155 mA Step 200 mA
Range
7.2
0.024% ( 1 LSB at 12b)
0.0015% ( 1 LSB at 16b)
0.024% ( 1 LSB at 12b)
At midscale transition, 200 mA range,
resistive load that connects the DAC output
to GND (RLOAD) = 4 Ω
3.6
200
3.5
1.0
μs
μs
μs
nA × s
Full-Scale Step 200 mA Range
Glitch Impulse
DAC to DAC Crosstalk8
100 mA to 200 mA step, RLOAD = 15 Ω
230
pA × s
Rev. 0 | Page 3 of 26
LTC2672
Data Sheet
Parameter
Symbol Test Conditions/Comments
Output current noise density internal reference,
OUTx = 150 mA, RLOAD = 4 Ω, CLOAD = 10 μF
Min
Typ
Max
Unit
iNOISE
I
Frequency (f) = 1 kHz
12
5
0.5
0.05
nA/√Hz
nA/√Hz
nA/√Hz
nA/√Hz
f = 10 kHz
f = 100 kHz
f = 1 MHz
REFERENCE
Reference Output Voltage
VREF Temperature Coefficient9
VREF Line Regulation
VREF Short-Circuit Current
REFCOMP Pin Short-Circuit Current
VREF Load Regulation
VREF
1.248
−10
1.250 1.252
V
+3
50
+10
ppm/°C
μV/V
mA
μA
mV/mA
nV/√Hz
VCC = 5 V 10ꢀ
VCC = 5.5 V, forcing output to GND
VCC = 5.5 V, forcing output to GND
VCC = 5 V, IREF = 100 μA sourcing
REFCOMP pin current (CREFCOMP) = REFCOMP
pin capacitance (CREF) = 0.1 μF, at f = 10 kHz
2.5
65
140
32
VREF Output Voltage Noise Density
External Reference Input Current
External Reference Input Capacitance10
External Reference Input Voltage
External Full-Scale Adjust Resistor
DIGITAL INPUT/OUPUT
0.001
40
1
μA
pF
V
REFCOMP pin is tied to GND
RFSADJ to GND
1.225
19
1.275
41
RFSADJ
20
kΩ
Digital Output High Voltage
VOH
VOL
SDO pin, load current = −100 μA
IOVCC
0.2
−
V
Digital Output Low Voltage
SDO pin, load current = 100 μA
FAULT pin, load current = 100 μA
SDO pin leakage current (CS/LD high)
FAULT pin leakage current (not asserted)
VIN = GND to IOVCC
0.2
0.2
+1
1
V
V
Digital High-Z Output Leakage Current
−1
−1
μA
μA
μA
pF
V
Digital Input Current
Digital Input Capacitance10
High Level Input Voltage
+1
8
CIN
VIH
2.85 ≤ IOVCC ≤ VCC
1.71 ≤ IOVCC ≤ 2.85
0.8 ×
IOVCC
0.8 ×
IOVCC
V
Low Level Input Voltage
VIL
2.85 ≤ IOVCC ≤ VCC
1.71 ≤ IOVCC ≤ 2.85
0.3
0.3
V
V
POWER SUPPLY
Analog Supply Voltage
Digital I/O Supply Voltage
Negative Supply
VCC
IOVCC
V−
2.85
1.71
−5.5
2.1
2.4
2.85
5.5
VCC
0
VCC
VCC
9
V
V
V
V
V
V
mA
μA
mA
mA
mA
mA
ꢁA
ꢁA
mA
ꢁA
Output Supplies
VDDx
200 mA range and below (relative to GND)
300 mA range and below (relative to GND)
Safe operating area (VDDx relative to V−)
All ranges (code = 0, all channels)
All ranges (code = 0, all channels)
All ranges (code = 0, all channels)
All ranges (code = 0, per channel)
25 mA range (code = full-scale, per channel)12
200 mA range (code = full-scale, per channel)12
Output Supplies, Total Voltage11
VCC Supply Current
IOVCC Supply Current
V− Supply Current
4
5.3
1
0.01
7.5
1.5
28
205
50
0.01
0.29
80
11
2.2
32
215
500
1
VDDX Supply Current
VCC Shutdown Current13, 14
IOVCC Shutdown Current13, 14
V− Shutdown Current13, 14
VDDX Shutdown Current13, 14
ISLEEP
1.2
250
Rev. 0 | Page 4 of 26
Data Sheet
LTC2672
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
MONITOR MULTIPLEXER
MUX Pin DC Output Impedance
MUX Pin Leakage Current
15
+0.1
kΩ
μA
Monitor multiplexer disabled (high
impedance)
Monitor multiplexer selected to OUT0 pin
voltage to OUT4 pin voltage
−1
V−
+1
VCC
+1
MUX Pin Output Voltage Range
MUX Pin Continuous Current11
V
TA = 25°C (do not exceed)
−1
mA
1 Offset current is measured at Code 384 for the LTC2672-16. Linearity is defined from Code 384 to Code 65535 for the LTC2672-16.
2 For the full-scale current (IFS) = 300 mA, RLOAD = 10 Ω. For IFS = 200 mA, RLOAD = 15 Ω. For IFS = 100 mA, RLOAD = 30 Ω. For IFS = 50 mA, RLOAD = 50 Ω. For IFS = 25 mA, RLOAD
100 Ω. For IFS = 12.5 mA, RLOAD = 200 Ω. For IFS = 6.25 mA, RLOAD = 400 Ω. For IFS = 3.125 mA, RLOAD = 800 Ω.
3 IFS = 200 mA and RLOAD = 15 Ω. DC crosstalk is measured with a 100 mA to 200 mA current step on all four aggressor channels. Total power dissipation change is 4 × 50 mW =
200 mW. The monitor channel is held at 3/4 × IFS or 150 mA.
=
4 VOUTx is the channel output voltage.
5 The loads attached to the OUTx pins must be terminated to GND.
6 VDDX = 5 V (3.125 mA range), VDDX = 3.6 V (200 mA range), and V− = −3.3 V for all ranges. For large current output steps, internal thermal effects result in a final settling
tail. In most cases, the tail is too small to affect settling to 0.024%, but several milliseconds can be needed for full settling to the 0.0015% level. For optimal results,
always solder the exposed pad (Pin 33) to a solid GND plane and set VDDX as low as practicable for each channel to reduce power dissipation in the device. The listed
results were obtained using the DC2903 evaluation board demo circuit with no additional heatsinks.
7 Internal reference mode. The load is 15 Ω (200 mA range) or 800 Ω (3.125 mA range) terminated to GND.
8 DAC to DAC crosstalk is the glitch that appears at the output of one DAC because of a 100 mA to 200 mA step change in an adjacent DAC channel. The measured DAC
is at midscale (100 mA output current) in the 200 mA span range, with the internal reference, VDDX = 5 V, V− = −3.3 V.
9 The temperature coefficient is calculated by first computing the ratio of the maximum change in the output voltage to the nominal output voltage, and then dividing
the ratio by the specified temperature range.
10 Guaranteed by design and not production tested.
11 Stresses beyond those listed for extended periods can cause permanent damage to the device or affect device reliability and lifetime.
12 Single channel at a specified output.
13
V
= IOVCC = 5 V, VDDx = 5 V, V− = −3.3 V.
CC
14 Digital inputs are at 0 V or IOVCC
.
Rev. 0 | Page 5 of 26
LTC2672
Data Sheet
TIMING CHARACTERISTICS
All specifications apply over the full operating junction temperature range −40°C to +125°C, otherwise specifications are at TJ = 25°C.
Digital input low and high voltages are 0 V and IOVCC, respectively.
Table 2. 2.85 V ≤ VCC ≤ 5.5 V, 2.85 V ≤ IOVCC ≤ VCC
Parameter
Test Conditions/Comments
Min
6
6
9
9
10
19
7
Typ
Max
Unit
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
t8
SDI valid to SCK setup
SDI valid to SCK hold
SCK high time
SCK low time
CS/LD pulse width
ns
LSB SCK high to CS/LD high
ns
CS/LD low to SCK high
ns
SDO propagation delay from SCK falling edge, CLOAD = 10 pF, 4.5 V < IOVCC < VCC
SDO propagation delay from SCK falling edge, CLOAD = 10 pF, 2.85 V < IOVCC < 4.5 V
20
30
ns
ns
t9
CLR pulse width
20
7
ns
t10
t11
t12
fSCK
t13
t14
CS/LD high to SCK positive edge
LDAC pulse width
ns
15
15
ns
CS/LD high to LDAC high or low transition
ns
SCK frequency
50
MHz
μs
μs
TGPx high time1
1
1
TGPx low time1
1 Guaranteed by design and not production tested.
Table 3. 2.85 V ≤ VCC ≤ 5.5 V, 1.71 V ≤ IOVCC ≤2.85 V
Parameter
Test Conditions/Comments
Min
7
7
30
30
15
19
7
Typ
Max
Unit
t1
t2
t3
t4
SDI valid to SCK setup
SDI valid to SCK hold
SCK high time
SCK low time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
μs
μs
t5
CS/LD pulse width
t6
LSB SCK high to CS/LD high
CS/LD low to SCK high
t7
t8
t9
SDO propagation delay from SCK falling edge, CLOAD = 10 pF
CLR pulse width
60
15
30
7
t10
t11
t12
fSCK
t13
t14
CS/LD high to SCK positive edge
LDAC pulse width
15
15
CS/LD high to LDAC high or low transition
SCK frequency (50% duty cycle, excludes SDO operation)
TGPx high time1
1
1
TGPx low time1
1 Guaranteed by design and not production tested.
Rev. 0 | Page 6 of 26
Data Sheet
LTC2672
Timing Diagrams
t1
t2
t3
2
t4
t6
SCK
1
3
23
24
t10
SDI
t5
t7
CS/LD
LDAC
Figure 2. Timing Diagram for Serial Interface,
, and Toggle Pins
CS/LD
SCK
SDI
3
5
6
8
9
15
19
27
1
2
4
7
10
11
12
13
14
16
17
18
20
21
22
23
24
25
26
28
29
30
31
32
X
X
X
X
X
X
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
32-BIT INPUT WORD
SDO
FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0
FAULT REGISTER (FR) BITS
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(HIGH-Z)
(HIGH-Z)
COMMAND WORD
ADDRESS WORD
DATA WORD
PREVIOUS 24-BIT INPUT WORD + 8-BIT FAULT REGISTER
Figure 3. LTC2672-16 32-Bit Load Sequence
CS/LD
SCK
1
3
4
5
6
8
9
15
19
2
7
10
11
12
13
14
16
17
18
20
21
22
23
24
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14 D13 D12
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDI
24-BIT INPUT WORD
SDO
FR7 FR6 FR5
FR4 FR3 FR2 FR1 FR0
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14 D13
D12 D11
D10
D9
D8
(HIGH-Z)
(HIGH-Z)
FAULT REGISTER [FR] BITS
COMMAND WORD
ADDRESS WORD
TRUNCATED DATA WORD
8-BIT FAULT REGISTER + TRUNCATED PREVIOUS 24-BIT INPUT WORD
Figure 4. LTC2672-16 24-Bit Load Sequence
Rev. 0 | Page 7 of 26
LTC2672
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
VCC to GND
IOVCC to GND
V− to GND
VDDx to GND
VDDx to V−
OUTx to GND
MUX
REF, REFCOMP, FSADJ
CS/LD, SCK, SDI, LDAC, CLR,
TGP to GND
−0.3 V to +6 V
−0.3 V to +6 V
−6 V to +0.3 V
−0.3 V to (VCC + 0.3 V)
−0.3 V to +10 V
(V− − 0.3 V) to (VDDX + 0.3 V)
(V− − 0.3 V) to (VCC + 0.3 V)
−0.3 V to minimum (VCC + 0.3 V, 6 V)
−0.3 V to +6 V
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 5. Thermal Resistance
Package Type
θJA
θJC
Unit
UH-321
44
7.3
°C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with no bias. See JEDEC JESD-51.
FAULT to GND
−0.3 V to +6 V
SDO
–0.3 V to minimum (VCC + 0.3 V,
6 V)
ESD CAUTION
Temperature
Operating Range
Storage Range
Junction, TJMAX
−40°C to +125°C
−65°C to +150°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. 0 | Page 8 of 26
Data Sheet
LTC2672
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LTC2672-16
TOP VIEW
(Not to Scale)
32 31 30 29 28 27 26 25
GND
TGP
1
2
3
4
5
6
7
8
24 OUT0
23 OUT1
SDI
V
V
22
21
20
19
18
17
DD1
DD2
SDO
33
GND
SCK
OUT2
OUT3
CS/LD
LDAC
GND
V
V
DD3
DD4
9
10 11 12 13 14 15 16
NOTES
1. T
= 150°C, θ = 44°C/W, θ = 7.3°C/W.
JMAX
JA
JC
2. GROUND. SOLDER THIS PAD DIRECTLY TO
THE ANALOG GROUND PLANE.
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 8, 14, 32 GND
Analog Ground. Tie GND to an analog ground plane.
2
TGP
Asynchronous Toggle Pin. A falling edge on TGP updates the DAC register with data from Input Register A. A rising
edge on TGP updates the DAC register with data from Input Register B. Toggle operations only affect the DAC
channels that have the toggle select bit (Tx) set to 1. Tie TGP to IOVCC if the toggle operations are to be done through
software. Tie TGP to GND if the toggle operations are not used. Logic levels are determined by IOVCC
.
3
4
SDI
Serial Data Input. Data on SDI is clocked into the DAC on the rising edge of SCK. The LTC2672-16 accepts input
word lengths of 24 bits, 32 bits, or multiples of 32 bits. Logic levels are determined by IOVCC.
Serial Data Output. The serial output of the 32-bit shift register appears at SDO. The data transferred to the
device via SDI is delayed 32 SCK rising edges before being output at the next falling edge. SDO can be used for
data echo readback or daisy-chain operation. SDO becomes high impedance when CS/LD is high. Logic levels
SDO
are determined by IOVCC
.
5
6
SCK
CS/LD
Serial Clock Input. Logic levels are determined by IOVCC.
Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting SDI data into the register
and SDO is enabled. When CS/LD is taken high, SDO and SCK are disabled and the specified command (see
Table 7) is executed. Logic levels are determined by IOVCC
.
7
LDAC
Active Low Asynchronous DAC Update Pin. LDAC allows updates independent of SPI timing. If CS/LD is high, a
falling edge on LDAC updates all DAC registers with the contents of the input registers. LDAC is gated by CS/LD and
has no effect if CS/LD is low. Logic levels are determined by IOVCC. If LDAC is not used, tie LDAC to IOVCC
.
9
10
REFLO
REF
Reference Low. REFLO is the signal ground for the reference. Tie REFLO directly to GND.
Reference Input/Output. The voltage at REF proportionally scales the full-scale output current of each DAC
output channel. By default, the internal 1.25 V reference is routed to REF. REF must be buffered when driving
external dc load currents. If the reference is disabled (see the Reference Modes section), the reference output is
disconnected and REF becomes a high impedance input that accepts a precision external reference. For low
noise and reference stability, tie a capacitor from REF to GND. The value must be less than CREFCOMP, where
C
REFCOMP is the capacitance tied to REFCOMP. The allowable external reference input range is 1.225 V to 1.275 V.
11
REFCOMP
Internal Reference Compensation Pin. For low noise and reference stability, tie a 0.1 ꢀF capacitor from REFCOMP
to GND. Tying REFCOMP to GND causes the device to power up with the internal reference disabled and allows
the use of an external reference at start-up.
Rev. 0 | Page 9 of 26
LTC2672
Data Sheet
Pin No.
Mnemonic Description
FSADJ
Full-Scale Current Adjust Pin. FSADJ can be used in one of two ways to produce either nominal, internally
12
calibrated output ranges, or incrementally tunable ranges. In either case, the reference voltage, VREF, is forced
across a resistor, RFSADJ, to define a reference current that scales the outputs for all ranges and channels. Full-
scale currents are proportional to the voltage at REF and are inversely proportional to RFSADJ. If FSADJ is tied to
V
CC, an internal RFSADJ (20 kΩ) is selected, which results in nominal output ranges. An external resistor of 19 kΩ to
41 kΩ can be used instead by connecting the resistor between FSADJ and GND. In this case, the external resistor
controls the scaling of the ranges and the internal resistor is automatically disconnected. See Table 9 for details.
When using an external resistor, FSADJ is sensitive to stray capacitance and must be compensated with a
snubber network that consists of a series combination of 1 kΩ and 1 ꢀF connected in parallel to RFSADJ. With the
recommended compensation, FSADJ is stable while driving stray capacitance up to 50 pF.
13, 27
15, 26
VCC
V−
Analog Supply Voltage. 2.85 V ≤ VCC ≤ 5.5 V. All output supply voltages must be less than or equal to VCC, (VDDx
CC). Bypass VCC to GND with a 1 ꢀF capacitor.
Negative Supply Voltage. −5.5 V ≤ V− ≤ GND. Bypass V− to GND with a 1 ꢀF capacitor unless V− is connected to
GND. See Figure 28 for safe operating voltages.
≤
V
16, 19, 20, OUT4 to
DAC Analog Current Outputs. Each current output pin has a dedicated analog supply pin, VDD0 to VDD4. The load
attached to OUTx must be terminated to GND. For information on combining outputs, see the Load Termination
and Combining Channels section.
23, 24
OUT0
17, 18, 21,
22, 25
VDD4 to VDD0 Output Supplies. VDD0 to VDD4 operate at 2.1 V to VCC with respect to GND, and at 2.85 V to 9 V with respect to V−.
These five positive supply inputs provide independent supplies for each of the five DAC current output pins,
OUT0 to OUT4, respectively. Note that the highest output supply voltage must be less than or equal to VCC (VDDx
≤ VCC). Bypass each supply input to GND separately with a 1 ꢀF capacitor. Unused output supplies must be
connected to a valid VCC or VDDX supply. Do not leave these pins floating. See Figure 28 for safe operating voltages.
28
MUX
Analog Multiplexer Output. Pin voltages and currents can be monitored by measuring the voltage at MUX. When the
multiplexer is disabled, MUX becomes high impedance. The available multiplexer selections are shown in Table 10.
29
30
IOVCC
FAULT
Digital Input/Output Supply Voltage. 1.71 V ≤ IOVCC ≤ VCC + 0.3 V. Bypass IOVCC to GND with a 0.1 ꢀF capacitor.
Active Low Fault Detection Pin. This open-drain, N-channel output pulls low when any valid fault condition is
detected. FAULT is released on the next CS/LD rising edge. A pull-up resistor is required (5 kΩ recommended).
31
33
CLR
Active Low Asynchronous Clear Input. A logic low at this level triggered input clears the device to the default
reset code and output range, which is zero-scale with the outputs off. The control registers are cleared to zero.
Logic levels are determined by IOVCC
.
GND
Ground. Solder this pad directly to the analog ground plane.
Rev. 0 | Page 10 of 26
Data Sheet
LTC2672
TYPICAL PERFORMANCE CHARACTERISTICS
32
1.00
0.75
0.50
0.25
0
25mA RANGE
24
16
8
0
–0.25
–0.50
–0.75
–1.00
–8
–16
3.125mA
25mA
200mA
300mA
–24
–32
0
16384
32768
CODE
49152
65536
0
16384
32768
CODE
49152
65536
Figure 9. DNL
Figure 6. INL
1.0
0.8
25mA
50mA
100mA
200mA
300mA
V
, 1V/DIV
OUT
0.6
SPAN = 3.125mA
LOAD
0.4
R
= 800Ω
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
RESIDUAL 500µV/DIV
OUT
CS/LD
AVERAGE OF 1024 EVENTS
= 3.8µs TO ±0.024%,
5µs/DIV
–40
–20
0
20
40
60
80
100
120
140
t
SETTLE
21.1µs TO ±0.0015%
TEMPERATURE (°C)
Figure 7. Full–Scale Current Error (FSE) vs Temperature
Figure 10. Settling 0 mA to 3.125 mA Step
V
, 2V/DIV
OUTX
V
, 500mV/DIV
OUT
V
= 5V
V
DDX
= 4.5V
= 3.6V
SPAN = 200mA
= 15Ω
DDX
SPAN = 200mA
= 15Ω
R
LOAD
R
LOAD
V
DDX
V
RESIDUAL 100µV/DIV
OUTX
V
RESIDUAL 500µV/DIV
OUT
CS/LD
CS/LD
t
= 3.5µs TO ±0.024%, 2ms/DIV
AVERAGE OF 1024 EVENTS
= 3.6µs TO ±0.024%,
2µs/DIV
SETTLE
200µs TO ±0.0015%
t
SETTLE
7.2µs TO ±0.0015%
AVERAGE OF 1024 EVENTS.
TO MINIMIZE THERMAL SETTLING TAIL
t
MEASURED AT V
= 3.6V
DDX
SETTLE
Figure 8. Settling 145 mA to 155 mA Step
Figure 11. Settling 0 mA to 200 mA Step
Rev. 0 | Page 11 of 26
LTC2672
Data Sheet
0.4
1.254
1.253
1.252
1.251
1.250
1.249
1.248
1.247
1.246
25mA
50mA
100mA
200mA
300mA
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
MEASURED AT 16-BIT CODE 384
–0.4
–40
–40
–20
0
20
40
60
80
100
120
140
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Reference Output (VREF) vs. Temperature
Figure 12. Offset Current Error vs. Temperature
250
225
200
175
150
125
100
75
350
300
250
200
150
100
50
–
CODE 65535
CODE 49152
CODE 32768
CODE 16384
0.463V
300mA
200mA
100mA
50mA
V
– V = 4.75V
DDX
0.709V
0.347V
0.473V
0.440V
0.229V
50
0.114V
25
0.432V
0.50
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0
0.25
0.75
1.00
1.25
1.50
DROPOUT VOLTAGE (V)
DROPOUT VOLTAGE (V)
Figure 13. IOUTX vs. Dropout Voltage for Multiple Current Ranges
Figure 16. IOUTX vs. Dropout Voltage for Multiple Codes (200 mA Span)
0.60
200mA RANGE
OUTX
I
= 200mA
0.55
0.50
0.45
0.40
I
= 100mA
OUTX
SPAN = 200mA
= 4Ω
CODE SEQUENCE =
0x7FFF TO 0x8000
R
LOAD
2µs/DIV
2
3
4
5
6
7
8
9
–
– V (V)
TOTAL SUPPLY V
DDX
Figure 14. VDROPOUT vs. Total Supply VDDx − V−
Figure 17. Midscale Glitch
Rev. 0 | Page 12 of 26
Data Sheet
LTC2672
80
70
60
50
40
30
20
10
0
200mA RANGE; R
= 15Ω
CURRENT NOISE IN R
( = 4Ω)
LOAD
LOAD
I
= 150mA (200mA RANGE)
OUT
C
C
C
= 0
= 1µF
= 10µF
L
L
L
5µs/DIV
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 18. Current Noise Density vs. Frequency,
Grounded Load Capacitor (CL) = 0 μF, 1 μF, and 10 μF
Figure 20. Large Signal Response
CH1: 200mA SPAN, I
CH0: 200mA SPAN, STEP 100mA TO 200mA
[RISING TRANSITION]
= 100mA
OUT1
ALL CHANNELS: R
= 15Ω, C = 0pF
LOAD
LOAD
2µs/DIV
Figure 19. DAC to DAC Crosstalk (Rising)
Rev. 0 | Page 13 of 26
LTC2672
Data Sheet
TERMINOLOGY
Integral Nonlinearity (INL)
Power Supply Rejection (PSR)
INL is a measurement of the maximum deviation, in LSBs,
from a straight line passing through the endpoints of the DAC
transfer function. INL for this DAC is defined from Code 384
to Code 65535.
PSR indicates how the output of the DAC is affected by changes
in the supply voltage. PSR is the change in VOUTX because of a
specified change in VCC, V−, or VDDX for a full-scale output of
the DAC and is expressed in LSB.
Differential Nonlinearity (DNL)
Settling Time
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of 1 LSB maximum ensures monotonicity. This DAC is
guaranteed monotonic by design. Because the output must
have a finite output current, DNL for this DAC is defined from
Code 384 to Code 65,535.
Settling time is the amount of time it takes for the output of a
DAC to settle to a specified error window for a full-scale input
CS
change and is measured from the rising edge of /LD.
Glitch Impulse
Glitch impulse is the impulse injected into the analog output
when the input code in the DAC register changes state. Glitch
impulse is normally specified as the area of the glitch in nA × sec,
and is measured when the digital input code is changed by 1 LSB at
the midscale transition.
Current Offset Error (IOS)
Unipolar offset error is typically measured when zero code is
loaded to the DAC register. Because offset can be either positive
or negative polarity and the output current cannot go below
zero, offset for this DAC is defined at Code 384 and calculated
based on the expected output at that code.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a 100 mA to 200 mA change in the outputs of all
other DAC channels. The monitored channel is maintained at
150 mA (3/4 × IFS). DC crosstalk is expressed in %FSR.
I
OS Temperature Coefficient
The IOS temperature coefficient is a measure of the change in IOS
with a change in temperature, and is expressed in ppm/°C.
DAC to DAC Crosstalk
Gain Error
DAC to DAC crosstalk is the glitch that appears at the output
of one DAC because of a step change from 100 mA to 200 mA
in another DAC channel. The measured DAC is at midscale
(100 mA output current) in the 200 mA range. The energy of
the glitch is expressed in nA × sec.
Gain error is a measure of the span error of the DAC, and is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as a percentage of full-scale range (%FSR).
Gain Error Temperature Coefficient
The gain error temperature coefficient is a measurement of the
change in gain error with changes in temperature, and is
expressed in ppm/°C.
Output Noise Spectral Density
Output noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nA/√Hz) and is measured by loading the DAC
to 150 mA (3/4 × IFS) and measuring noise at the output.
Rev. 0 | Page 14 of 26
Data Sheet
LTC2672
THEORY OF OPERATION
The LTC2672-16 is a five-channel, current source output DAC
with selectable output ranges, precision reference, and a
multiplexer for surveying the channel output voltages and
currents. Each output draws its current from a separate dedicated
positive supply pin that accepts voltages of 2.1 V to VCC to allow
optimization of power dissipation and headroom for a wide
range of loads. Internal 12 Ω switches allow any output pin to
be connected to an optional negative V− supply voltage and
sink up to 80 mA.
POWER-ON RESET
The outputs reset to a current off state (off mode) on power-up,
which makes system initialization consistent and repeatable.
When power-on initialization is complete, select the output
span via the SPI bus using Table 7, Table 8, and Table 9.
POWER SUPPLY SEQUENCING
The supplies (VCC, IOVCC, V−, and VDD0 to VDD4) can be powered
up in any convenient order. If an external reference is used, do
not allow the input voltage at REF to rise above VCC + 0.3 V
during supply turn on and turn off sequences (see the Absolute
Maximum Ratings section). When startup is complete, ensure
that no supply exceeds VCC. DC reference voltages of 1.225 V to
1.275 V are acceptable.
LOAD TERMINATION AND COMBINING
CHANNELS
The load attached to any OUTx pins must be terminated to
ground. OUTx pins that are not used in the system design must
be left open (no connect).
Supply bypassing is critical to achieving the best possible
performance. Use at least 1 μF of low ESR capacitance to
ground on all supply pins and locate the capacitor as close to
Any combination of OUTx pins can be tied together if currents
greater than 300 mA are needed or for finer control of large
currents. The LTC2672-16 offers the following four span
categories:
the device as possible. A 0.1 μF capacitor can be used for IOVCC
.
DATA TRANSFER FUNCTIONS
Eight current ranges
Off mode
The DAC input to output transfer functions for all resolutions
and output ranges ≥25 mA are shown in Figure 22. The input
code is in straight binary format for all ranges.
Switch to V−
Power-down
All channels tied together must be operated in the same span
category.
The device is tolerant of mixing span categories, but avoid
doing so because mixing can increase supply currents and/or
compromise accuracy. When the combined channels are
operated in the current range span category (3.125 mA to
300 mA), the ranges and DAC codes do not need to be the
same for each channel.
Rev. 0 | Page 15 of 26
LTC2672
Data Sheet
APPLICATIONS INFORMATION
SERIAL INTERFACE
Table 8. DAC Address Mapping
When the /LD pin is taken low, the data on the SDI pin is bit
CS
Address
DAC Number
DAC0
DAC1
DAC2
DAC3
A3
0
0
0
0
A2
0
0
0
0
A1
0
0
1
1
A0
0
1
0
1
loaded into the shift register on the rising edge of the clock
(SCK pin). The 4-bit command, C3 to C0, is loaded first,
followed by the 4-bit DAC address, A3 to A0, and then the 16-
bit data word in straight binary format. For the LTC2672-16,
the data word comprises the 16-bit input code ordered MSB to
LSB. Data can only be transferred to the LTC2672-16 when the
DAC4
0
1
0
0
/LD signal is low. The rising edge of /LD ends the data
transfer and causes the device to carry out the action specified
in the 24-bit input word.
CS
CS
Note that any DAC address code used other than the codes
given in Table 8 causes the command to be ignored.
INPUT AND DAC REGISTERS
Even though the minimum input word is 24 bits, it can be
extended to 32 bits. To use the 32-bit word width, transfer eight
don’t care bits to the device first, followed by the 24-bit word.
The 32-bit word is required for echo readback and daisy-chain
operation. The 32-bit word also provides accommodation for
processors that have a minimum word width of 16 bits or more.
The LTC2672-16 has five internal registers for each DAC, in
addition to the main shift register. Each DAC channel has two
sets of double-buffered registers, one set for the code data and
one set for the span (output range) of the DAC. Double
buffering provides the capability to simultaneously update the
span and code, which allows smooth current transitions when
changing output ranges. Double buffering also allows the
simultaneous updating of multiple DACs. Each set of double-
buffered registers comprises an input register and a DAC register.
The complete 24-bit and 32-bit sequences are shown in Figure 4.
Note that the fault register outputs appear on the SDO pin for
either word width.
Table 7. Write Operation for SPI Commands
Regarding the input register, the write operation shifts data
from the SDI pin into a chosen register. The input registers are
holding buffers. Write operations do not affect the DAC
outputs.
Command
Number
0000
1000
0110
1110
0001
1001
0011
Data
Write code to DAC Channel x
Write code to all DAC channels
Write span to DAC Channel x
Write span to all DAC channels
Power up and update DAC Channel x
Power up and update all DAC channels
In the code data path, there are two input registers, Register A
and Register B, for each DAC register. Register B is an alternate
register used only in the toggle operation, and Register A is the
default input register.
Regarding the DAC register, the update operation copies the
contents of an input register to its associated DAC register. The
content of a DAC register directly controls the DAC output
current or range.
Write code to DAC Channel x, power up and
update DAC Channel x
0010
1010
Write code to DAC Channel x, power up,
and update all DAC channels
Power up, write code to and update all DAC
channels
The update operation also powers up the selected DAC if the
DAC had been in power-down mode. Note that updates always
refresh both code and span data, but the values held in the
DAC registers remain unchanged unless the associated input
register values have been changed via a write operation. For
example, if a new code is written and the channel is updated,
the code is updated while the span is refreshed and unchanged.
A channel update can come from a serial update command, an
0100
0101
1011
1100
1101
0111
1111
Power down Channel x
Power down chip
Monitor multiplexer
Toggle select
Global toggle
Configuration command
No operation
negative pulse, or a toggle operation.
LDAC
Rev. 0 | Page 16 of 26
Data Sheet
LTC2672
As shown in Table 9, there are two additional selections (Code
0000 and Code 1000) that place the output(s) in off mode or in
a mode where a low on resistance (≤12 Ω) switch shunts the
DAC output to the negative supply, V−. When the switch is on,
the OUTx pin driver is disabled for that channel(s). Span codes
not listed in Table 9 default to the off mode output range.
OUTPUT RANGES AND SOFTSPAN OPERATION
The LTC2672-16 is a five-channel current DAC with selectable
output ranges. The full set of current output ranges is only
available through SPI programming.
Figure 23 shows a simplified diagram of a single channel of the
LTC2672-16. The full-scale current range of the LTC2672-16 is
selected via four control bits, Bits[S3:S0], on a per channel
basis. The user can also provide an external reference at the
REF pin or use an external resistor at the FSADJ pin to adjust
the full-scale currents as needed.
Table 9. Span Codes
Output Range
S3
0
S2
0
S1
0
S0
0
FSADJ = VCC
External RFSADJ
Off mode
0
0
0
1
3.125 mA
6.25 mA
12.5 mA
25 mA
50 × VREF/RFSADJ
The LTC2672-16 initializes at power-up with all channel
outputs (OUT0 to OUT4) in off mode. The range and code of
each channel are then fully programmable through SoftSpan™,
as shown in Table 9 and Figure 21. Each channel has a set of
double-buffered registers for range information. Program the
span input register using the write span to DAC Channel x or
write span all commands (0110b and 1110b, respectively, see
Table 7). Figure 22 shows the syntax, and Table 9 shows the
span codes and ranges. As with the double-buffered code registers,
update operations copy the span input registers to the associated
span DAC registers.
0
0
1
0
100 × VREF/RFSADJ
200 × VREF/RFSADJ
400 × VREF/RFSADJ
800 × VREF/RFSADJ
1600 × VREF/RFSADJ
3200 × VREF/RFSADJ
4800 × VREF/RFSADJ
0
0
1
1
0
1
0
0
0
1
0
1
50 mA
0
1
1
0
100 mA
200 mA
300 mA
0
1
1
1
1
1
1
1
1
0
0
0
Switch to V−
300
300mA RANGE
200mA RANGE
100mA RANGE
50mA RANGE
250
25mA RANGE
200
150
100
50
0
0
16384
32768
CODE
49152
65536
Figure 21. LTC2672-16 Transfer Function
WRITE SPAN COMMAND
ADDRESS
DON’T CARE
SPAN CODE
0
1
1
0
A3
A2
A1
A0
X
X
X
X
X
X
X
X
X
X
X
X
S3
S2
S1
S0
Figure 22. Write Span Syntax
Rev. 0 | Page 17 of 26
LTC2672
Data Sheet
V
DDX
V
CC
PER CHANNEL (×5)
INTERNAL
REFERENCE
SPAN
REF
FULL
SCALE
ADJUST
CODE
DAC
OUTX
FSADJ
SWITCH
–
TO V
SPAN
R
20kΩ
FSADJ
–
V
GND
REFLO
Figure 23. LTC2672-16 Single-Channel Simplified Diagram
MUX COMMAND
DON’T CARE
MUX CONTROL CODE
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
M4
M3
M2
M1
M0
Figure 24. Multiplexer Command
Table 10. Analog Multiplexer Control Address Bits
M4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
M3
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
M2
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
M1
0
0
1
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
0
1
1
0
M0
0
1
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
Multiplexer Signal Output
Notes1
Disabled (high-Z)
OUT0 current measurement
OUT1 current measurement
OUT2 current measurement
OUT3 current measurement
OUT4 current measurement
VCC
VREF
VREFLO
Die temperature, T
VDD0
VDD1
VDD2
VDD3
VDD4
V–
IOUT0 = full-scale current (IFS) × VMUX/VREF
IOUT1 = IFS × VMUX/VREF
IOUT2 = IFS × VMUX/VREF
IOUT3 = IFS × VMUX/VREF
IOUT4 = IFS × VMUX/VREF
DAC ground (0 V) reference
T = 25°C + (1.4 V − VMUX)/(0.0037 V/°C)
GND
OUT0 pin voltage
OUT1 pin voltage
OUT2 pin voltage
OUT3 pin voltage
OUT4 pin voltage
1 IFS is the full-scale current and VMUX is the output voltage of the multiplexer at the MUX pin.
Rev. 0 | Page 18 of 26
Data Sheet
LTC2672
MONITOR MULTIPLEXER
MONITOR MULTIPLEXER PRECHARGE
CONSIDERATIONS
The LTC2672-16 includes a multiplexer for monitoring both
the voltages and currents at the five current output pins
(OUTx). Additionally, VDDx, the negative V− supply, core supply
(VCC), reference voltage (VREF), and die temperature can all be
monitored.
The analog multiplexer in the LTC2672-16 is unbuffered. This
obviates error terms from amplifier offsets. However, without
buffers, the high impedance current outputs can be disturbed
because of charge transfer at the moment when the MUX pin is
connected. The LTC2672-16 contains circuitry that suppresses
charging glitches on the output pins (OUTx) by precharging
the MUX pin before connecting the MUX pin to the output.
The MUX pin is intended for use with high impedance inputs
only. The impedance at the MUX pin is typically 15 kΩ. The
continuous dc output current at the MUX pin must be limited
to 1 mA to avoid damaging internal circuitry.
Because of the precharge behavior, the multiplexer output becomes
valid approximately 7 μs after the multiplexer command is given
The operating range of the multiplexer extends rail-to-rail from
V− to VCC and its output is disabled (high impedance) at power-up.
(
/LD rising). Residual charging transients can be further
CS
reduced by adding capacitance to the output pins, if needed. Do
not add capacitance to the MUX pin as this action can increase
the disturbance to the outputs during multiplexer switching.
Up to 100 pF on the MUX pin is allowable.
The syntax and codes for the multiplexer command are shown
in Figure 24 and Table 10.
CURRENT MEASUREMENT USING THE
MULTIPLEXER
TOGGLE OPERATIONS
Measure the current of any output pin by using the multiplexer
command (1011b) with one of the multiplexer current
measurement codes from Table 10. The multiplexer responds
by outputting a voltage proportional to the actual output
current. The proportionality factor is given by the following
equation:
Some systems require that the DAC outputs switch repetitively
between two output levels (for example, switching between an
on and off state). The LTC2672-16 toggle function facilitates
these kinds of operations by providing two input registers
(Register A and Register B) per DAC channel.
Toggling between Register A and Register B is controlled by
three signals. The first signal is the toggle select command,
which acts on the data field of 5 bits, each of which controls a
single channel (see Figure 25). The second signal is the global
toggle command, which controls all selected channels using the
global toggle bit, TGB (see Figure 26). Lastly, the TGP pin
allows the use of an external clock or logic signal to toggle the
DAC outputs between Register A and Register B. The signals
from these controls are combined as shown in Figure 27. If the
toggle function is not needed, tie the TGP pin (Pin 2) to ground
and leave the toggle select register in its power-on reset state
(cleared to zero). Input Register A then functions as the sole
input register, and Register B is not used.
I
OUTX = IFS × VMUX/VREF
where:
OUTX is the output current the OUTX pin.
(1)
I
The current measurement function does not sense the current
at the OUTx pins, but instead uses the DAC settings to predict
the output current. Therefore Equation 1 is invalid if the output
pin is open (or dropping out), or if the span is not set to one of
the eight current ranges.
In Equation 1, note that VMUX varies only with the DAC code
(and reference voltage), and is the same for every span setting.
I
FS must be given the value of the active span setting for the
equation to evaluate correctly.
TOGGLE SELECT REGISTER (TSR)
VMUX has the same optimal linearity as the current outputs, but
calibrating for slope error ( 15% FSR) is necessary for accurate
results. 1% FSR accuracy is achievable with a one-point or
two-point calibration.
The toggle select command (1100b) syntax is shown in Figure 25.
Each bit in the 5-bit TSR data field controls the corresponding
DAC channel of the same name (T0 controls Channel 0, T1
controls Channel 1,…, and T4 controls Channel 4).
DIE TEMPERATURE MEASUREMENT USING THE
MULTIPLEXER
The toggle select bits (T0 to T4) have a dual function. First,
each toggle select bit controls which input register (Register A
or Register B) receives data from a write code operation. When
the toggle select bit of a given channel is high, write code
operations are directed to Input Register B of the addressed
channel. When the bit is low, write code operations are directed
to Input Register A. In addition, each toggle select bit enables
the corresponding channel for a toggle operation.
Measure the die temperature by using the multiplexer command
with the multiplexer Control Code 01010b. The voltage at the
MUX pin (VMUX) in this case is linearly related to the die
temperature by a temperature coefficient of −3.7 mV/°C.
The measured junction temperature, TJ, is then
TJ = 25°C + (1.4 V − VMUX)/(3.7 mV/°C)
(2)
If needed, the temperature monitor can be calibrated by measuring
the initial temperature and voltage, and then substituting these
values for 25°C and 1.4 V, respectively, in the equation.
Rev. 0 | Page 19 of 26
LTC2672
Data Sheet
WRITING TO INPUT REGISTER A AND INPUT
REGISTER B
TOGGLING BETWEEN REGISTER A AND REGISTER B
When the input registers have been written to for all desired
channels and the corresponding toggle select bits are set high, as
in the previous example, the channels are ready for toggling.
When channels to toggle are chosen, write the desired codes to
Input Register A for the chosen channels, then set the channel
toggle select bits using the toggle select command and write the
desired codes to Input Register B. When these steps are
complete, the channels are ready to toggle. For example, to set
up Channel 3 to toggle between Code 4096 and Code 4200, take
the following steps:
The LTC2672-16 supports three types of toggle operations: one
in which all selected channels are toggled together using the SPI
port, another in which all selected channels are toggled together
using an external clock or logic signal, and a third in which any
combination of channels can be instructed to update from
either input register.
1. Write Code Channel 3 (code = 4096) to Register A
00000011 00010000 00000000.
2. Toggle select (set Bit T3)
11000000 00000000 00001000.
3. Write Code Channel 3 (code = 4200) to Register B
00000011 00010000 01101000.
The internal toggle update circuit is edge triggered, so only
transitions (of TGB or TGP) trigger an update from the
respective input register.
To toggle all selected channels together using the SPI port,
ensure the TGP pin is high and that the bits in the toggle select
register corresponding to the desired channels are also high.
Use the global toggle command (1101b) to alternate codes and
sequentially change the global toggle bit, TGB (see Figure 26).
Changing TGB from 1 to 0 updates the DAC registers from the
respective Input Register A. Changing TGB from 0 to 1 updates
the DAC registers from the respective Input Register B. Note
that in this way, up to five channels can be toggled with just one
serial command.
The write code of Step 3 is directed to Register B because in
Step 2, Bit T3 was set to 1. Channel 3 now has Input Register A
and Register B holding the two desired codes, and is prepared
for the toggle operation.
Note that after writing to Register B, the code for Register A
can still be changed. The state of the toggle select bit determines
to which register (Register A or Register B) a write is directed.
For example, to change Register A while toggling Register B,
take the following steps:
To toggle all selected channels using an external logic signal,
ensure that the TGB bit in the global toggle register is high and
that in the toggle select register, the bits corresponding to the
desired channels are also high. Apply a clock or logic signal to
the TGP pin to alternate codes. The TGP falling edges update
the DAC registers from the associated Input Register A. The
TGP rising edges update the DAC registers from the associated
Input Register B. Note that after the input registers are set up,
all toggling is triggered by the signal applied to the TGP pin
with no further SPI instructions needed.
1. Reset the toggle select bit, Bit T3, to 0 (11000000 00000000
00000000).
2. Write the new Register A code. If the code used for this
example is 4300, the instruction is 00000011 00010000
11001100
3. Set the toggle select bit, Bit T3, back to 1 (see previous Step 2).
It is not necessary to write to Register B again. Channel 3 is
ready for the toggle operation.
To cause any combination of channels to update from either
Input Register A or Input Register B, ensure that the TGP pin is
high and that the TGB bit in the global toggle register is also
high. Use the toggle select command to set the toggle select bits
as needed to select the input register (Register A or Register B)
with which each channel is to be updated. Then, update all
channels either by using the serial command (1001b) or by
applying a negative pulse to the
pin. Any channels that
LDAC
have toggle select bits that are 0 update from Input Register A,
and channels that have toggle select bits that are 1 update from
Input Register B (see Figure 27). By alternating between toggle
select and update operations, up to five channels can be
simultaneously switched to Register A or Register B as needed.
Rev. 0 | Page 20 of 26
Data Sheet
LTC2672
TOGGLE SELECT BITS
(1-BIT/CHANNEL)
TOGGLE SELECT
DON’T CARE
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
T4
T3
T2
T1
T0
MSB
LSB
Figure 25. Toggle Select Syntax
GLOBAL
TOGGLE
BIT
GLOBAL TOGGLE
COMMAND
DON’T CARE
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TGB
Figure 26. Global Toggle Syntax
CHANNEL 3
LOGIC
INPUT REGISTER A
(16-BIT)
16
16
0
1
WRITE
16
16
A/B
MUX
DAC REGISTER
16-BIT
INPUT REGISTER B
(16-BIT)
LDAC
7
UPDATE
TOGGLE SELECT BIT T3
TOGGLE
SELECT
REGISTER
TGB
LTC2672-16
SDI
GLOBAL TOGGLE
BIT (TGB)
3
32-BIT SHIFT REGISTER
SCK
CS/LD
TGP
5
6
2
Figure 27. Conceptual Block Diagram, Toggle Functionality
Rev. 0 | Page 21 of 26
LTC2672
Data Sheet
DAISY-CHAIN OPERATION
FAULT INDICATOR PIN (
, PIN 30)
FAULT
The serial output of the shift register appears at the SDO pin.
Data transferred to the device from the SDI input is delayed for
32 SCK rising edges before being output at the next SCK falling
edge so that the data can be clocked into the microprocessor on
the next 32 SCK rising edges.
The
pin is an open-drain, N-channel output that pulls
FAULT
low when a fault condition is detected. The
released on the next rising /LD edge and is an open-drain
CS
output suitable for wired-OR connection to an interrupt bus. A
pull-up resistor on the bus is required (5 kΩ is recommended).
pin is
FAULT
The SDO output can be used to facilitate control of multiple serial
Table 11. Fault Register (FR)
Bit Fault Condition
devices from a single 3-wire serial port (SCK, SDI and /LD).
CS
This kind of daisy-chain series is configured by connecting the
SDO of each upstream device to the SDI of the next device in
the chain. The shift registers of the devices are thus connected
in series to effectively form a single input shift register that
extends through the entire chain. Because of this connection,
the devices can be addressed and controlled individually by
concatenating their input words (the first instruction addresses
FR0 Open-circuit condition detected on OUT0
FR1 Open-circuit condition detected on OUT1
FR2 Open-circuit condition detected on OUT2
FR3 Open-circuit condition detected on OUT3
FR4 Open-circuit condition detected on OUT4
FR5 Overtemperature. If die temperature TJ > 175°C, FR5 is set
and thermal protection is activated. Can be disabled using
the configuration command (0111b)
the last device in the chain, and so on). The SCK and /LD
CS
signals are common to all devices in the series.
FR6 Unused
When in use, /LD is first taken low. Then, the concatenated
CS
input data is transferred to the chain using the SDI of the first
device as the data input. When the data transfer is complete,
FR7 Invalid SPI sequence length. Valid sequence lengths are
24, 32 and multiples of 32 bits. For all other lengths, FR7 is
set and the SPI instruction is ignored.
/LD is taken high, which completes the instruction sequence
for all devices simultaneously. A single device can be controlled
by using the no operation command (1111b) for all other
CS
FAULT CONDITIONS AND THERMAL OVERLOAD
PROTECTION
There are three types of fault conditions that cause the
FAULT
devices in the chain. When /LD is taken high, the SDO pin
CS
pin to pull low. First, FR0 to FR4 flag an open-circuit (OC)
condition on any of the output pins (OUT0 to OUT4,
respectively) when an output channel enters dropout because of
insufficient voltage from VDDX to OUTx. An independent open-
circuit detection circuit is provided for each of the five DAC
current output pins.
presents a high impedance output. Therefore, a pull-up resistor
is required at the SDO of each device (except the last) for daisy-
chain operation.
ECHO READBACK
The SDO pin can be used to verify data transfer to the device.
During each 32-bit instruction cycle, the SDO pin outputs the
previous 32-bit instruction for verification. The 8-bit don’t care
prefix is replaced by eight fault register status bits, followed by
the 4-bit command and address words and the full 16-bit data
word (Figure 3 and Figure 4). The SDO sequence for a 24-bit
instruction cycle is the same, except that the data word is
FR5 provides a detection flag which is set when the die
temperature exceeds 175°C. The overtemperature condition
also forces all five DAC channels to power down and the open-
drain
pin to pull low.
FAULT
FR5 remains set and the device stays in shutdown until the die
cools. Below approximately 150°C the DAC channels can be
truncated to 8 bits (see Figure 3). When /LD is high, SDO
CS
returned to normal operation. Note that a /LD rising edge
CS
presents a high impedance output and releases the bus for use
by other SPI devices.
releases the
pin regardless of the die temperature.
FAULT
Because any DAC channel can source up to 300 mA, die heating
potential of the system design must be evaluated carefully.
FAULT REGISTER (FR)
The LTC2672-16 provides notifications of operational fault
conditions. The fault register (FR) status bits comprise the first
data byte (8 bits) of each 24-bit or 32-bit SDO word outputted
to the SDO pin during each SPI transaction. See Figure 3 and
Figure 4 for the sequences.
Finally, FR7 is provided to flag invalid SPI word lengths. Valid
word lengths are 24 bits, 32 bits, and integer multiples of 32
bits. Any other length causes FR7 to set, the
pin to
FAULT
assert, and the instruction itself to be ignored.
FR6 is unused in this device.
An FR bit is set when its trigger condition is detected, and
clocked to SDO during the next SPI transaction. FR
information is updated with each SPI transaction. Note that if a
fault condition is corrected by the action of an SPI instruction,
the cleared FR flag for that condition is observable at SDO on
the next SPI transaction.
Table 11 lists the FR bits and their associated trigger conditions.
Rev. 0 | Page 22 of 26
Data Sheet
LTC2672
Dropout performance is sensitive to the total output supply
CONFIGURATION COMMAND
voltage. VDROPOUT falls to its minimum as (VDDx − V−) rises from
2.85 V to 4.75 V, and then stays essentially constant as the
voltage further increases to 9 V. See the VDROPOUT specifications
in Table 1 and Figure 14.
The configuration command has three arguments, OC, TS, and
RD (see Figure 30).
Setting the OC bit disables open-circuit detection (FR0 to FR4),
while the TS bit disables thermal protection (FR5). Set TS with
caution, as thermal damage can easily occur and is the user
responsibility.
VCC (Pin 13 and Pin 27) must be in the 2.85 V ≤ VCC ≤ 5.5 V
range and be greater than or equal to the VDD0 to VDD4 output
supplies.
The RD bit is used to select external reference operation. The
REFCOMP pin must be grounded for external reference use
whether the RD bit is set or not.
7
6
5
V
CC
V
/V
/V
/V
/V
DD0 DD1 DD2 DD3 DD4
4
SAFE-OPERATING AREA
POWER-DOWN MODE
3
For power constrained applications, power-down mode can be
used to reduce the supply current whenever less than five DAC
outputs are needed. When in power-down, the voltage-to-
current output drivers and reference buffers are disabled. The
current DAC outputs are set to off mode. Register contents are
not disturbed during power-down.
2
1
2.85V MINIMUM
0
9.0V MAXIMUM
–1
–2
–3
–4
–5
–6
–
V
Any channel or combination of channels can be put into
power-down mode by using Command 0100b in combination
with the appropriate DAC address. In addition, all DAC
channels and the integrated reference together can be put into
power-down using the power-down chip command, 0101b.
The 16-bit data word is ignored for all power-down commands.
Figure 28. Output Supply Safe Operating Area
CURRENT OUTPUTS
The LTC2672-16 incorporates a high gain voltage to current
converter at each current output pin. INL and DNL are
guaranteed for all ranges from 3.125 mA to 300 mA if the
minimum dropout voltage (VDDX − VOUTX) is met for all DAC
codes.
Active operation resumes by executing any command that
includes a DAC update, either in software, as shown in Table 6
or by toggling (see the Toggle Operations section). The selected
DAC channel is powered up as it is updated with the new code
value. When updating a powered-down DAC, add wait time to
accommodate the extra power-up delay. If the channels have
been powered down (Command 0100b) prior to the update
command, the power-up delay time is 30 μs. If, alternatively,
the chip has been powered down (Command 0101b), the
power-up delay time is 35 μs.
If sufficient dropout voltage is maintained, the dc output
impedances of the current outputs (OUT0 to OUT4) are high.
Each current output has a dedicated positive supply pin, VDD0 to
VDD4, to allow the tailoring of the current compliance and
power dissipation of each channel.
V
DDX
SAFE SUPPLY RANGES
OFF
The five output supplies (VDD0 to VDD4) can be independently
set between 2.1 V (2.4 V for the 300 mA range) and VCC. And
the negative supply, V−, can be set to any voltage between
−5.5 V and GND. But keep the total output supply voltage
(VDDx with respect to V−) in the 2.85 V to 9.0 V range, as
specified in Table 1 and shown in Figure 28.
80mA
OUTx
R
< 12Ω
ON
–
V
A minimum of 2.85 V is needed to establish drive for the
output P-type metal-oxide semiconductor (PMOS), while the
maximum of 9 V provides a margin of voltage stress tolerance
for the output circuit.
–
Figure 29. Switch to V Mode
CONFIG COMMAND
DON’T CARE
CONFIG BITS
TS
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OC
X
RD
Figure 30. Configuration Command Syntax, Open-Circuit Detection Disable (OC), Thermal Shutdown Disable (TS), and Reference Disable (RD)
Rev. 0 | Page 23 of 26
LTC2672
Data Sheet
SWITCH TO V− MODE
REFERENCE MODES
Span Code 1000b can be used to pull outputs below GND. In
switch to V− mode, the output current is turned off for the
addressed channel(s), and the channel voltage VOUTX pulls to
V−. The pulldown switch can sink up to 80 mA at an effective
resistance of 12 Ω maximum. Note that exceeding 80 mA can
affect reliability and device lifetime. Switch to V− mode can be
invoked with the write span to all channels or write span to
DAC Channel x command and the desired address. Span codes
are shown in Table 9. A diagram of an output in switch to V−
mode is shown in Figure 29, where RON is the resistance when the
NMOS transistor is conducting.
The LTC2672-16 can be used with either an internal or external
reference. As with voltage DACs, the reference voltage scales
the outputs, so that the outputs reflect any errors in the
reference. Full scale output currents are limited to 300 mA
maximum per channel regardless of reference voltage.
The internal 1.25 V reference has a typical temperature drift of
2 ppm/ꢂC and an initial output tolerance of 2 mV maximum.
The reference is trimmed, tested, and characterized
independent of the DACs, and the DACs are tested and
characterized with an ideal external reference.
To use the internal reference, leave the REFCOMP pin floating
with no dc path to GND. In addition, the RD bit in the
configuration register must have a value of 0. This value is reset
to 0 at power-up and can be reset using the configuration
command, 0111b. Figure 30 shows the command syntax.
GAIN ADJUSTMENT USING THE FSADJ PIN
The full-scale output currents are proportional to the reference
voltage, and inversely proportional to the resistance associated
with FSADJ, that is,
For reference stability and low noise, tie a 0.1 ꢃF capacitor
between REFCOMP and GND. In this configuration, the
internal reference can drive up to 0.1 ꢃF with optimal stability.
To ensure stable operation, the capacitive load on the REF pin
must not exceed that on the REFCOMP pin. A buffer is needed
if the internal reference is to drive external circuitry.
I
OUTFS ~ VREF/RFSADJ
If the FSADJ pin is tied to VCC, the LTC2672-16 uses an internal
FSADJ ~ 20 kꢀ, trimmed to ensure optimal full-scale current
(3)
R
error with no user intervention. Optionally, FSADJ can instead
be connected to a grounded external resistor to tune the default
current ranges to the application using an appropriately specified
precision resistor. Values from 19 kꢀ to 41 kꢀ are supported.
The new current ranges can be calculated using the external
To use an external reference, tie the REFCOMP pin to GND,
which disables the output of the internal reference at startup so
that the REF pin becomes a high impedance input. Apply the
reference voltage at the REF pin after powering up. Set the
RD bit to 1 using the configuration command, 0111b. The REF
input voltage range is 1.225 V to 1.275 V.
R
FSADJ column of Table 9. The internal resistor is automatically
disconnected when using an external resistor.
When using an external resistor, the FSADJ pin is sensitive to
stray capacitance. The FSADJ pin must be compensated with a
snubber network consisting of a series combination of 1 kꢀ
and 1 μF connected in parallel to RFSADJ. With the recommended
compensation, the FSADJ pin is stable while driving stray
capacitance of up to 50 pF.
BOARD LAYOUT
The load regulation and dc crosstalk performance of the device
is achieved in the device by minimizing the common-mode
resistance of the signal and power grounds.
OFFSET CURRENT AND CODE ZERO
As with any high resolution converter, clean board grounding
is important. A low impedance analog ground plane is
necessary, as well as star grounding techniques. Keep the board
layer used for star ground continuous to minimize ground
resistances, that is, use the star ground concept without using
separate star traces. Resistance from the REFLO pin to the star
point must be as low as possible. The GND pin (Pin 33) is
recommended as the star ground point.
The offset current error of the LTC2672-16 is guaranteed
0.4 ꢁFSR maximum. If the offset of a given channel is
positive, some nonzero current flows at code zero. If negative,
the current is zero (leakage only) for a range of codes close to
zero. Offset and linearity endpoints are measured at Code 384
(LTC2672-16) guaranteeing that the DAC is operating with a
measurable output current at the point of measurement.
For optimal performance, stitch the ground plane with arrays
of vias on 150 mil to 200 mil centers to connect the plane with
the ground pours from the other board layers, which reduces
the overall ground resistance and minimizes ground loop area.
A channel with a positive offset error may not completely turn off,
even at code zero. To turn an output completely off, set the span to
off (Span Code 0000b from Table 9), and update the channel.
Rev. 0 | Page 24 of 26
Data Sheet
LTC2672
OUTLINE DIMENSIONS
0.70 0.05
5.50 0.05
4.10 0.05
3.45 0.05
3.50 REF
(4 SIDES)
3.45 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 0.05
5.00 0.10
(4 SIDES)
31 32
0.40 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 0.10
3.50 REF
(4-SIDES)
3.45 0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Figure 31. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body
(UH-32)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
0°C to 70°C
0°C to 70°C
−40°C to +85°C
−40°C to +85°C
−40 to +125°C
−40 to +125°C
Package Description
Package Option
UH-32
UH-32
UH-32
UH-32
LTC2672CUH-16#TRPBF
LTC2672CUH-16#PBF
LTC2672IUH-16#TRPBF
LTC2672IUH-16#PBF
LTC2672HUH-16#TRPBF
LTC2672HUH-16#PBF
DC2903A-A
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
UH-32
UH-32
Rev. 0 | Page 25 of 26
LTC2672
NOTES
Data Sheet
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D25700-12/20(0)
Rev. 0 | Page 26 of 26
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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