LTC3310 [ADI]
5V, 12.5A Synchronous Step-Down Silent Switcher in 3mm x 3mm LQFN;
| 型号： | LTC3310 |
| 厂家： | 
ADI |
| 描述： | 5V, 12.5A Synchronous Step-Down Silent Switcher in 3mm x 3mm LQFN |
| 文件： | 总26页 (文件大小：2795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3311
5V, 12.5A Synchronous Step-Down
Silent Switcher in 3mm x 3mm LQFN
FEATURES
DESCRIPTION
The LTC®3311 is a very small, low noise, monolithic
step-down DC/DC converter capable of providing up to
12.5A of output current from a 2.25V to 5.5V input supply.
The device employs Silent Switcher 1 architecture with
internal hot loop bypass capacitors to achieve both low
EMI and high efficiency at switching frequencies as high
as 5MHz. For systems with higher power requirements,
multi-phasing parallel converters is readily implemented.
n
Pin Compatible with LTC3310/LTC3310S and LTC3311S
Silent Switcher® Architecture:
n
n
Ultralow EMI Emissions
n
n
n
n
n
n
n
n
n
n
n
n
n
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High Efficiency—4.5mΩ NMOS and 16mΩ PMOS
Wide Bandwidth, Fast Transient Response
Safely Tolerates Inductor Saturation in Overload
V Range: 2.25V to 5.5V
IN
OUT
OUT
V
V
Range: 0.5V to V
IN
Accuracy: 1% with Remote Sense
The LTC3311 uses a constant frequency, peak current
mode control architecture for fast transient response. A
500mV reference allows for low voltage outputs. 100%
duty cycle operation delivers low drop out.
Peak Current Mode Control
Minimum On-Time: 35ns
Programmable Frequency to 5MHz
Precision 400mV Enable Threshold, 1μA in Shutdown
Output Soft-Start with Voltage Tracking
Power Good Output
Die Temperature Monitor
Configurable for Paralleling Power Stages in Forced
Continuous Mode
Other features include a power good signal when the
output is in regulation, precision enable threshold, output
overvoltage protection, thermal shutdown, a temperature
monitor, clock synchronization, mode selection and
output short circuit protection. The device is available in
a compact 18-lead 3mm x 3mm LQFN package.
n
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Thermally-Enhanced 3mm × 3mm LQFN Package
AEC-Q100 Qualified for Automotive Applications
All registered trademarks and trademarks are the property of their respective owners.
APPLICATIONS
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Automotive/Industrial/Communications
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Servers, Telecom Power Supplies
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Distributed DC Power Systems (POL)
FPGA, ASIC, µP Core Supplies
n
TYPICAL APPLICATION
Efficiency vs Load Current
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ꢀ.ꢁ
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0
1.2V 12.5A Step-Down Converter
ꢀ
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ꢀꢁ
V
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ
IN
3.0V to 5.5V
22µF
22µF
V
IN
EN
MODE/SYNC
100nH
V
OUT
SW
FB
1.2V
12.5A
47µF
140k
100k
6.8pF
LTC3311
PGND
PGOOD
SSTT
×3
ꢀꢁꢂꢃR ꢄꢁꢅꢅ
V
IN
1μF
0.1µF
AGND
RT
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢁ
ITH
ꢀ
ꢀ ꢁ.ꢂꢃ
ꢀꢁꢂ
10k
470pF
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂ
274k
0
ꢀ
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ꢀ
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3311 TA01a
ꢀꢁꢂ
ꢀꢀꢁꢁ ꢂꢃ0ꢁꢄ
Rev. 0
1
Document Feedback
For more information www.analog.com
LTC3311
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ꢀꢁꢂ ꢃꢄꢅꢆ
V
............................................................. –0.3V to 6V
IN
EN, SSTT ............. –0.3V to Lesser of (V + 0.3V) or 6V
IN
IN
IN
IN
MODE/SYNC ........ –0.3V to Lesser of (V + 0.3V) or 6V
ꢇꢕ ꢇꢭ ꢇꢩ ꢇꢪ
RT........................ –0.3V to Lesser of (V + 0.3V) or 6V
ꢅꢊ
ꢇ
ꢢ
ꢙ
ꢡ
ꢪ
ꢇꢡ ꢂꢉꢁꢁꢋ
FB ........................ –0.3V to Lesser of (V + 0.3V) or 6V
ꢌꢉꢊꢋ
ꢇꢙ ꢍꢁꢋꢅꢎꢏꢐꢊꢑ
PGOOD......................................................... –0.3V to 6V
ꢇꢈ
ꢂꢉꢊꢋ
ꢃ
ꢄꢊ
ꢃ
ꢄꢊ
ꢇꢢ
ꢇꢇ
ꢃ
ꢃ
ꢄꢊ
ꢄꢊ
I
......................................................................5mA
PGOOD
Operating Junction Temperature Range (Notes 2, 3)
LTC3311J......................................... –40°C to +150°C
LTC3311H ........................................ –40°C to +150°C
Storage Temperature............................ –65°C to +150°C
Maximum Reflow (Package Body) Temperature ...260°C
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θ
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Ψ
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ꢠ ꢇ.ꢢꢪꢣꢑꢎꢆꢤ θ VALUES DETERMINED PER JESD51-12
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ORDER INFORMATION
LEAD FREE – TRAY/REEL
AUTOMOTIVE PRODUCTS**
PART MARKING PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3311JV#PBF
LTC3311JV#WPBF
LTC3311HV#PBF
LTC3311HV#WPBF
LTC3311JV#TRPBF
LTC3311HV#TRPBF
LTC3311JV#TRMPBF
LTC3311HV#TRMPBF
LTC3311JV#WTRPBF
LTC3311HV#WTRPBF
LTC3311JV#WTRMPBF
LTC3311HV#WTRMPBF
18-Lead (3mm × 3mm) LQFN
LHMN
–40°C to 150°C
(Laminate Package with QFN Footprint)
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. 0
2
For more information www.analog.com
LTC3311
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3) VIN = 3.3V, VEN = VIN, MODE/SYNC = 0V, unless otherwise noted.
PARAMETER
Input Supply
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Operating Supply Voltage (V )
2.25
2.0
5.5
2.2
V
IN
V
V
Undervoltage Lockout
Undervoltage Lockout Hysteresis
V
Rising
IN
2.1
150
V
mV
IN
IN
V
V
Quiescent Current
Quiescent Current in Shutdown
(Note 4)
EN
1.3
1
2.0
2
mA
μA
IN
IN
V
= 0.1V
l
EN Threshold
EN Hysteresis
V
Rising
0.375
495
0.4
60
0.425
V
EN
mV
EN Pin Leakage Current
V
EN
= 0.4V
20
nA
Voltage Regulation
l
Regulated Feedback Voltage (V
)
500
505
0.025
20
mV
%/V
nA
FB
Feedback Voltage Line Regulation
Feedback Pin Input Current
Error Amp Transconductance
Error Amp Sink/Source Current
Top Switch Current Limit
2.5V ≤ V ≤ 5.0V
0.002
IN
V
= 0.5V
FB
1
mS
µA
45
18
14
16
4.5
100
26
35
l
l
15
12
21
16
V
/V ≤ 0.2, Current Out of SW
A
OUT IN
Bottom Switch Current Limit (I
Top Switch ON-Resistance
Bottom Switch ON-Resistance
SW Leakage Current
)
Current Out of SW
A
VALLEYMAX
mΩ
mΩ
nA
V
= 0.1V
EN
V
ITH
to I
Current Gain
A/V
ns
Peak
l
l
Minimum On-Time
60
Maximum Duty cycle
100
%
Power Good/Soft-Start/Temp Monitor
l
l
PGOOD Rising Threshold
PGOOD Hysteresis
As a Percentage of the Regulated V
As a Percentage of the Regulated V
97
98
1
99
%
%
OUT
0.5
1.5
l
l
Overvoltage Rising Threshold
Overvoltage Hysteresis
105
1
110
2.5
115
3.5
%
%
OUT
PGOOD Leakage Current
PGOOD Pull Down Resistance
PGOOD Delay
V
V
= 5.5V
= 0.1V
20
20
nA
Ω
PGOOD
12
PGOOD
125
µs
l
l
PGOOD Input Threshold
PGOOD Input Hysteresis
Multi-Phase Mode, Rising
= 0.5V
390
7
440
130
490
13
mV
mV
Soft-Start Charge Current
Temp Monitor Slope
Oscillator
V
10
4
µA
SSTT
mV/°C
l
l
l
l
Switching Frequency Range
Switching Frequency
Synchronization Frequency Range
Default Frequency
R Programmable
0.5
1.8
0.5
1.8
1.2
5
MHz
MHz
MHz
MHz
T
R = 274k
T
2
2
2.2
2.25
2.2
R = V
T
IN
IN
R = V
T
l
l
SYNC Level High on MODE/SYNC
SYNC Level Low on MODE/SYNC
V
V
0.4
Minimum MODE/SYNC Pulse Width
40
ns
Rev. 0
3
For more information www.analog.com
LTC3311
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3) VIN = 3.3V, VEN = VIN, MODE/SYNC = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
200
20
MAX
UNITS
kΩ
µs
MODE/SYNC Input Resistance
MODE/SYNC No Clock Detect Time
MODE/SYNC Clock Out Rise/Fall Time
MODE/SYNC Clock Low Output Voltage
MODE/SYNC Clock High Output Voltage
MODE/SYNC Clock Out Duty Cycle
C
= 50pF
= 100µA
= 100µA
10
ns
MODE/SYNC
MODE/SYNC
MODE/SYNC
I
I
0.2
V
V
– 0.2
V
IN
50
%
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LTC3311 includes overtemperature protection which protects
the device during momentary overload conditions. Junction temperatures
will exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 2: The LTC3311J/ LTC3311H are guaranteed to meet performance
specifications from –40°C to 150°C junction temperature.
Note 4: Supply current specification does not include switching currents.
Actual supply currents will be higher.
VIN = 3.3V, TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Line Regulation
VOUT = 1.2V
VOUT Load Regulation
VOUT = 1.2V
Efficiency, VOUT = 0.5V
Forced Continuous Operation
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ꢀꢀꢁꢁ ꢂ0ꢃ
ꢀꢀꢁꢁ ꢂ0ꢁ
Efficiency, VOUT = 0.5V
Pulse Skip Mode Operation
Efficiency, VOUT = 1.2V
Forced Continuous Operation
Efficiency, VOUT = 1.2V
Pulse Skip Mode Operation
ꢀ00
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ꢀꢀꢁꢁ ꢂ0ꢃ
ꢀꢀꢁꢁ ꢂ0ꢃ
Rev. 0
4
For more information www.analog.com
LTC3311
VIN = 3.3V, TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency, VOUT = 1.8V
Forced Continuous Operation
Efficiency, VOUT = 1.8V
Pulse Skip Mode Operation
Feedback Reference Voltage
ꢀ00
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ꢀ
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ꢀ ꢁꢂ
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ꢀ ꢁ.ꢁꢂ
ꢀ ꢁꢂ
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0.00ꢀ
0.0ꢀ
0.ꢀ
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ꢀ0 ꢀ0
0.00ꢀ
0.0ꢀ
0.ꢀ
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ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀ
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ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀꢁꢁ ꢂ0ꢃ
ꢀꢀꢁꢁ ꢂ0ꢃ
Switch On Resistance vs VIN
Switch On Resistance
Switch Leakage
24
22
20
18
16
14
12
10
8
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢁ
ꢀꢁ
PMOS
NMOS
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
6
ꢀ
4
0
ꢀꢁ
2
2.0 2.5 3.0 3.5 4.0 4.5
INPUT VOLTAGE (V)
50
5.5
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
3311 G10
Default Switching Frequency
VIN UVLO Threshold
Switching Frequency
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
R
ꢀ
ꢀ ꢁꢂꢃꢄꢅꢆ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
Rev. 0
5
For more information www.analog.com
LTC3311
VIN = 3.3V, TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
EN Pin Thresholds
Soft-Start Current
Soft-Start Tracking
ꢀꢀ.0
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.0
ꢀ.ꢁ
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
00
ꢀꢁ Rꢂꢃꢂꢁꢄ
00
00
00
00
00
0
ꢀꢁ ꢂꢃꢄꢄꢅꢁꢆ
ꢀ.ꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
0
00
00
00
00
00
00
VIN Quiescent Current
VIN Shutdown Current
Switch Current Limit
ꢀ.ꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁ.ꢁꢂꢃ
ꢀ ꢁ.ꢁꢂ
ꢀ ꢁ.ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ ꢄ
ꢀꢁꢂꢁꢃ
ꢀꢁꢂꢁꢃ
ꢀ
ꢀꢁꢂꢃ ꢄ
0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
0
UV PGOOD Threshold
Minimum On-Time
OV PGOOD Threshold
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁ.0
ꢀꢁ.ꢂ
ꢀꢁ.0
ꢀꢁ.ꢂ
ꢀꢁ.0
ꢀꢁ.ꢂ
ꢀꢁ.0
ꢀ0.ꢁ
0
ꢀ0.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢀ
ꢀ.0
ꢀ
ꢀ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀ ꢁ.ꢁꢂ
ꢀ ꢁ.ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀ
ꢀ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀꢁꢁ ꢂꢃꢄ
Rev. 0
6
For more information www.analog.com
LTC3311
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
CISPR25 Conducted EMI Performance (CISPR25
Conducted Emission Test with Class 5 Peak Limits)
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁꢂꢃꢃ ꢄ ꢅꢆꢂꢇ ꢁꢈꢉꢈꢊ
ꢀꢁꢂꢃꢄRꢁꢅ ꢁꢀꢆꢃꢃꢆꢇꢈꢃ
ꢀꢁꢂꢃꢄꢅꢆ ꢅꢇꢃꢈꢄ
ꢀꢁ0
ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00 ꢀꢀ0
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢀꢁꢁ ꢂꢃꢄ
ꢀꢁꢂ0ꢃꢄꢅ ꢀꢆꢇꢈ ꢉꢈꢅRꢀ
ꢀꢁꢂꢃꢄ ꢅꢆꢂ ꢇꢂꢈꢃꢅR ꢂꢉꢊꢃꢋꢈꢈꢅꢌꢍ
ꢀ.ꢀꢁ ꢂꢃꢄꢅꢆ ꢆꢇ ꢈ.ꢉꢁ ꢇꢅꢆꢄꢅꢆ ꢊꢆ ꢈ0ꢊꢋ ꢌ ꢀ ꢁꢂꢃꢄ
ꢀꢁ
Radiated EMI Performance (CISPR25 Radiated
Emissions Test with Class 5 Peak Limits)
Radiated EMI Performance (CISPR25 Radiated
Emissions Test with Class 5 Peak Limits)
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁRꢂꢃꢁꢄꢅꢆꢇ ꢈꢁꢇꢆRꢂꢃꢆꢅꢂꢁꢄ
ꢀꢁRꢂꢃꢄꢅꢆ ꢇꢈꢆꢅRꢃꢉꢅꢂꢃꢈꢊ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
0
ꢀꢁꢂꢃꢃ ꢄ ꢅꢆꢂꢇ ꢁꢈꢉꢈꢊ
ꢀꢁꢂꢃꢃ ꢄ ꢅꢆꢂꢇ ꢁꢈꢉꢈꢊ
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁꢂꢃꢄRꢁꢅ ꢁꢀꢆꢃꢃꢆꢇꢈꢃ
ꢀꢁꢂꢃꢄRꢁꢅ ꢁꢀꢆꢃꢃꢆꢇꢈꢃ
ꢀꢁꢂꢃꢄꢅꢆ ꢅꢇꢃꢈꢄ
ꢀꢁꢂꢃꢄꢅꢆ ꢅꢇꢃꢈꢄ
0
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00 ꢀ000
0
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00 ꢀ000
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢀꢁꢁ ꢂꢃꢄ
ꢀꢀꢁꢁ ꢂꢃꢄ
ꢀꢁꢂ0ꢃꢄꢅ ꢀꢆꢇꢈ ꢉꢈꢅRꢀ
ꢀꢁꢂ0ꢃꢄꢅ ꢀꢆꢇꢈ ꢉꢈꢅRꢀ
ꢀꢁꢂꢃꢄ ꢅꢆꢂ ꢇꢂꢈꢃꢅR ꢂꢉꢊꢃꢋꢈꢈꢅꢌꢍ
ꢀꢁꢂꢃꢄ ꢅꢆꢂ ꢇꢂꢈꢃꢅR ꢂꢉꢊꢃꢋꢈꢈꢅꢌꢍ
ꢀ.ꢀꢁ ꢂꢃꢄꢅꢆ ꢆꢇ ꢈ.ꢉꢁ ꢇꢅꢆꢄꢅꢆ ꢊꢆ ꢈ0ꢊꢋ ꢌ ꢀ ꢁꢂꢃꢄ
ꢀ.ꢀꢁ ꢂꢃꢄꢅꢆ ꢆꢇ ꢈ.ꢉꢁ ꢇꢅꢆꢄꢅꢆ ꢊꢆ ꢈ0ꢊꢋ ꢌ ꢀ ꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁ
Rev. 0
7
For more information www.analog.com
LTC3311
PIN FUNCTIONS
EN (Pin 1): The EN pin has a precision enable threshold
with hysteresis. An external resistor divider, from V or
from another supply, programs the threshold below which
the LTC3311 will shut down. If the precision threshold is
not used, directly connect the pin to VIN. When the EN pin
is low, the LTC3311 enters a low current shutdown mode
where all internal circuitry is disabled.
PGOOD (Pin 14): The PGOOD pin is a power good pin and
is the open drain output of an internal comparator. The
PGOOD output is pulled low when VIN is above 2.25V and
the part is in shutdown. When connecting multiple phases
in parallel, connect the PGOOD pins together.
IN
RT (Pin 15): The RT pin sets the oscillator frequency
with an external resistor to AGND or sets the phasing
for multiphase operation. (see Multiphase Operation in
Applications Information).
AGND (Pin 2): The AGND pin is the output voltage remote
ground sense. Connect the AGND pin directly to the nega-
tive terminal of the output capacitor at the load and to the
feedback divider resistor.
SSTT (Pin 16): Soft-Start, Track, Temperature Monitor.
An internal 10µA current into an external capacitor on the
soft-start pin programs the output voltage ramp rate dur-
ing start-up. During the soft-start cycle, the FB pin voltage
will track the SSTT pin voltage. When the soft-start cycle
is complete, the tracking function is disabled, the internal
reference resumes control of the error amplifier and the
SSTT pin servos to a voltage representative of junction
temperature. For a clean recovery from an output short
circuit condition, the SSTT pin is pulled down to approxi-
VIN (Pins 3, 4, 11, 12): The VIN pins supply current to the
internal circuitry and topside power switch. All of the V
pins must be connected together with short, wide traces
and bypassed to PGND with low ESR capacitors located
as close as possible to the pins.
IN
PGND (Pins 5, 10, 19): The PGND pins are the return
path of the internal bottom side power switch. Connect
the PGND pins together and to the exposed pad. Connect
the negative terminal of the input capacitors as close to
the PGND pins as possible. The PGND node is the main
thermal highway and should be connected to a large PCB
ground plane with many large vias.
mately 140mV above the V voltage and a new soft-start
FB
cycle is initiated. During shutdown and fault conditions,
the SSTT pin is pulled to ground.
ITH (Pin 17): The ITH pin is the compensation node for
the output voltage regulation control loop. Compensation
components connected to this pin are referenced to AGND.
SW (Pins 6–9): The SW pins are the switching outputs of
the internal power switches. Connect these pins together
to the inductor with short, wide traces.
FB (Pin 18): The output voltage feedback pin is externally
connected to the output voltage via a resistive divider and
is internally connected to the inverting input of the error
amplifier. The LTC3311 regulates the FB pin to 500mV. A
MODE/SYNC (Pin 13): The MODE/SYNC pin facilitates
multiphase operation and synchronization to an external
clock. Depending on the mode of operation, the MODE/
SYNC pin either accepts an input clock pulse or outputs
a clock pulse at its operating frequency. (see Multiphase
Operation in Applications Information). The MODE/SYNC
pin also programs the mode of operation: pulse skip or
forced continuous.
phase lead capacitor connected between V and V
is
FB
OUT
used to optimize the transient response.
Rev. 0
8
For more information www.analog.com
LTC3311
BLOCK DIAGRAM
ꢁ
ꢖꢌ
Rꢅ
ꢋꢌ
0.ꢀꢀꢁ
0.ꢀꢁ
0.ꢂꢃꢁ
ꢈ
ꢉ
ꢁ
ꢖꢌ
ꢖꢌꢑꢋRꢌꢎꢐ
RꢋꢍꢋRꢋꢌꢔꢋ
ꢁ
ꢖꢌ
Rꢓ
0.ꢂꢁ
0.ꢅꢒꢍ
ꢗꢓ
ꢔ
ꢖꢌ
Rꢑ
ꢐ
ꢊꢘꢖꢑꢔꢝ ꢐꢕꢚꢖꢔ
ꢊ
R
ꢜ
ꢊꢘ
ꢁ
ꢖꢌ
ꢎꢌꢇ
ꢁ
ꢕꢏꢑ
R
ꢑ
ꢕꢊꢔꢖꢐꢐꢎꢑꢕR
ꢎꢌꢑꢖꢞꢊꢝꢕꢕꢑ ꢑꢝRꢕꢏꢚꢝ
ꢔ
ꢕꢏꢑ
ꢈ
ꢉ
ꢊꢋꢌꢊꢋ
ꢊꢋꢌꢊꢋ
ꢈ
ꢉ
ꢛꢕꢇꢋꢟꢊꢠꢌꢔ
ꢙꢚꢌꢇ
ꢍꢆ
ꢊꢐꢕꢙꢋ ꢔꢕꢛꢙ
ꢖꢑꢝ
R
R
ꢔ
ꢍꢍ
ꢎ
ꢆ
ꢋRRꢕR
ꢎꢛꢙ
ꢉ
ꢈ
ꢈ
0.ꢀꢁ
R
ꢔ
ꢎꢚꢌꢇ
ꢔ
ꢔ
ꢅ0ꢒꢎ
ꢉ
ꢈ
ꢙꢚꢕꢕꢇ
ꢈ ꢁ
ꢉ
ꢊꢊꢑꢑ
ꢑꢋꢛꢙ
0.ꢂꢃꢁ
0.ꢀꢀꢁ
ꢍꢎꢏꢐꢑ
ꢔ
ꢊꢊ
ꢍꢎꢏꢐꢑ
ꢈ
ꢉ
ꢄꢄꢅꢅ ꢆꢇ
Rev. 0
9
For more information www.analog.com
LTC3311
OPERATION
Voltage Regulation
Synchronizing the Oscillator to an External Clock
The LTC3311 is a monolithic, constant frequency, current
mode step-down DC/DC converter. An oscillator turns on
the internal top power switch at the beginning of each
clock cycle. Current in the inductor increases until the
top switch current comparator trips and turns off the top
power switch. The peak inductor current at which the top
switch turns off is controlled by the voltage on the ITH
node. The error amplifier servos the ITH node by com-
paring the voltage on the FB pin with an internal 500mV
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference
leading the error amplifier to raise the ITH voltage until the
average inductor current matches the new load current.
When the top power switch turns off, the synchronous
power switch turns on until the next clock cycle begins
or, in pulse-skipping mode, inductor current falls to zero.
If overload conditions result in excessive current flowing
through the bottom switch, the next clock cycle will be
delayed until switch current returns to a safe level.
The LTC3311’s internal oscillator is synchronized through
an internal PLL circuit to an external frequency by apply-
ing a square wave clock signal to the MODE/SYNC pin.
During synchronization, the top power switch turn-on is
locked to the rising edge of the external frequency source.
While synchronizing, the switcher operates in forced con-
tinuous mode. The slope compensation is automatically
adapted to the external clock frequency.
After detecting an external clock on the first rising edge
of the MODE/SYNC pin, the internal PLL gradually adjusts
its operating frequency to match the frequency and phase
of the signal on the MODE/SYNC pin. When the external
clock is removed, the LTC3311 detects the absence of
the external clock within approximately 20µs. During this
time, the PLL will continue to provide clock cycles. Once
the external clock removal has been detected, the oscilla-
tor gradually adjusts its operating frequency back to the
default frequency.
The output voltage is resistively divided externally to cre-
ate a feedback voltage for the regulator. In high current
operation, a ground offset may be present between the
LTC3311 local ground and ground at the load. To over-
come this offset, AGND should have a Kelvin connec-
tion to the load ground, and the lowest potential node of
the resistor divider should be connected to AGND. The
internal error amplifier senses the difference between
this feedback voltage and a 0.5V AGND referenced volt-
age. This scheme overcomes any ground offsets between
local ground and remote output ground, resulting in a
more accurate output voltage. The LTC3311 allows for
remote output ground deviations as much as 100mV
with respect to local ground.
Mode Selection
The MODE/SYNC pin either synchronizes the switch-
ing frequency to an external clock, is a clock output, or
sets the PWM mode. The PWM modes of operation are
either pulse skip or forced continuous. See Table 6 in
the Applications Information section. In pulse skip mode,
switching cycles are skipped at light loads to regulate the
output voltage. During forced continuous mode, the top
switch turns on every cycle and light load regulation is
achieved by allowing negative inductor current.
Output Power Good
Comparators monitoring the FB pin voltage pull the
PGOOD pin low if the output voltage varies from the
nominal set point or if a fault condition is present. The
comparator includes voltage hysteresis. A time delay to
report PGOOD is used to filter short duration output volt-
age transients.
If the EN pin is low, the LTC3311 is shut down and in a
low quiescent current state. When the EN pin is above its
threshold, the switching regulator will be enabled.
Rev. 0
10
For more information www.analog.com
LTC3311
OPERATION
Soft-Start/Tracking/Temperature Monitor
Output Short-Circuit Protection and Recovery
The soft-start tracking function facilitates supply sequenc-
The peak inductor current level, at which the current com-
parator shuts off the top power switch, is controlled by the
voltage on the ITH pin. If the output current increases, the
error amplifier raises the ITH pin voltage until the average
inductor current matches the load current. The LTC3311
clamps the maximum ITH pin voltage, thereby limiting the
peak inductor current.
ing, limits V inrush current and reduces start-up output
IN
overshoot. When soft-starting is completed, the SSTT pin
parks itself at a voltage representative of the LTC3311
die junction temperature. The SSTT capacitor is reset
during shutdown, V UVLO and thermal shutdown. See
IN
Application section.
When the output is shorted to ground, the inductor cur-
rent decays very slowly during a single switching cycle
because the voltage across the inductor is low. To keep
the inductor current in control, a secondary limit is
imposed on the valley of the inductor current. If the induc-
tor current measured through the bottom power switch
Dropout Operation
As the input supply voltage approaches the output volt-
age, the duty cycle increases. Further reduction of the
supply voltage forces the main switch to remain on for
more than one cycle, eventually reaching 100% duty
cycle. The output voltage will then be determined by the
input voltage minus the DC voltage drop across the inter-
nal main P-channel MOSFET and the inductor.
is greater than the I
the top power switch will
VALLEY(MAX)
be held off. Subsequent switching cycles will be skipped
until the inductor current is reduced below I
.
VALLEY(MAX)
In many designs when the input voltage approaches the
output voltage, the amplitude of the output ripple volt-
age increases from its normally low value. To avoid any
increase in output ripple voltage under these conditions,
it is recommended to utilize a resistor divider on the EN
Recovery from an output short circuit goes through a
soft-start cycle. When V
goes below regulation, as
defined by the PGOOD tOhUreTshold, the SSTT voltage is
pulled to a voltage just above the FB voltage. Because
the SSTT pin is pulled low, a soft-start cycle is initiated
once the output short is removed.
input and limit the V turn-on and turn-off thresholds to
IN
where the output ripple voltage is acceptable for the given
application (typically 500mV above V ).
OUT
Low Supply Operation
The LTC3311 is designed to operate down to an input
supply voltage of 2.25V. An important thermal design
consideration is that the R
of the power switches
DS(ON)
increase at low VIN. Calculate the worst case LTC3311
power dissipation and die junction temperature at the low-
est input voltages.
Rev. 0
11
For more information www.analog.com
LTC3311
APPLICATIONS INFORMATION
Refer to the Block Diagram for reference.
switching frequency (fSW(MAX)) for a given application
can be calculated using Equation 2.
FB Resistor Network
V
OUT + VSW BOT
( )
(2)
fSW MAX
=
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistor
values according to Equation 1.
(
)
tON MIN
V
) – VSW TOP + VSW BOT
IN MAX
( ) ( )
(
)
(
where VIN(MAX) is the maximum input voltage, VOUT is the
output voltage, VSW(TOP) and VSW(BOT) are the internal
⎛
⎜
⎝
⎞
VOUT
500mV
(1)
RA =RB
– 1
⎟
⎠
switch drops and t
is the minimum top switch on-
ON(MIN)
time. Equation 2 shows that a slower switching frequency
is necessary to accommodate a high V /V ratio.
as shown in Figure 1:
IN OUT
ꢆ
ꢁꢂꢃ
The LTC3311 is capable of a maximum duty cycle of
100%, therefore, the V -to-V dropout is limited by
DS(ON)
load current.
ꢖ
R
R
ꢀ
ꢄꢄ
ꢀ
ꢁꢂꢃ
ꢅ
IN
OUT
ꢇꢂꢀꢊ
ꢋꢌꢍꢃꢀꢎꢍꢏꢐ
RꢑꢐꢂꢒꢅꢃꢁR
ꢄꢇ
the R
of the top switch, the inductor DCR and the
ꢓꢁꢔꢃꢍꢁꢏꢅꢒꢕ
ꢇ
ꢈꢈꢉꢉ ꢄ0ꢉ
Setting the Switching Frequency
Figure 1. Feedback Resistor Network
The LTC3311 uses a constant frequency PWM architec-
ture. There are three methods to set the switching fre-
Reference designators refer to the Block Diagram. 1%
resistors are recommended to maintain output voltage
accuracy. When optimizing the control loop for high band-
width and optimal transient response add a phase-lead
quency. The first method is with a resistor (R ) tied from
T
the RT pin to ground. The frequency can be programmed
to switch from 500kHz to 5MHz. Table 1 shows the neces-
sary R value for a desired switching frequency.
T
capacitor connected from V
to FB.
OUT
The R resistor required for a desired switching frequency
T
Operating Frequency Selection and Trade-Offs
is calculated using Equation 3.
Selection of the operating frequency is a trade-off between
efficiency, component size, transient response and input
voltage range.
(3)
(–1.08)
RT = 568 • fSW
where R is in kΩ and f is the desired switching fre-
T
SW
The advantage of high frequency operation is that smaller
inductor and capacitor values may be used. Higher
switching frequencies allow for higher control loop
bandwidth and, therefore, faster transient response. The
disadvantages of higher switching frequencies are lower
efficiency, because of increased switching losses, and a
smaller input voltage range, because of minimum switch
on-time limitations.
quency in MHz.
Table 1. SW Frequency vs RT Value
f
SW
(MHz)
R (kΩ)
T
0.5
1
1210
549
274
243
178
130
100
2
2.2
3
Although the maximum programmable switching fre-
quency is 5MHz, the minimum on-time of the LTC3311
imposes a minimum operating duty cycle. The highest
4
5
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12
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APPLICATIONS INFORMATION
The second method to set the LTC3311 switching fre-
quency is by synchronizing the internal PLL circuit to an
external frequency applied to the MODE/SYNC pin. The
synchronization frequency range is 0.5MHz to 2.25MHz.
where I
is the maximum output load current for
a givenLaOpApDl(iMcaAtXio) n and ΔI is the inductor ripple current
L
calculated using Equation 7.
⎛
⎞
VOUT
L • fSW
VOUT
VIN(MAX)
⎜
⎟
∆IL =
• 1–
(7)
The internal PLL starts up at the 2MHz default frequency.
After detecting an external clock on the first rising edge
of the MODE/SYNC pin, the internal PLL gradually adjusts
its operating frequency to match the frequency and phase
of the MODE/SYNC signal.
⎜
⎝
⎟
⎠
where V
is the maximum application input voltage.
IN(MAX)
To keep the efficiency high, choose an inductor with the
lowest series resistance (DCR). The core material should
be intended for high frequency applications.
The LTC3311 detects when the external clock is removed
and will gradually adjust its operating frequency to the
2MHz default frequency. The LTC3311 operates in forced
continuous mode when synchronized to an external clock.
The LTC3311 limits the peak switch current in order to
protect the switches and the system from overload faults.
The inductor value must then be sufficiently large to sup-
ply the desired maximum output current, IOUT(MAX), which
is a function of the switch current limit, ILIM, and the ripple
current (Equation 8).
The third method of setting the LTC3311 switching fre-
quency is to use the internal nominal 2MHz default clock.
See Table 4 for pin configuration.
Inductor Selection and Maximum Output Current
IOUT MAX = ILIM – ∆IL
(8)
(
)
Considerations in choosing an inductor are inductance,
RMS current rating, saturation current rating, DCR and
core loss.
Therefore, the maximum output current that the LTC3311
will deliver depends on the switch current limit, the induc-
tor value, and the input and output voltages. The inductor
value may have to be increased if the inductor ripple cur-
rent does not allow sufficient maximum output current
inOpUuTt(vMoAlXta)ge used in the desired application.
Table 2. Inductor Manufacturers
A good first choice for the inductor value is given by
Equation 4 and Equation 5.
(I
) given the switching frequency, and maximum
⎛
⎞
VOUT
4A• fSW
VOUT
VOUT
V
IN(MAX)
L ≈
L ≈
• 1−
for
≤ 0.5
⎜
⎟
(4)
(5)
V
⎝
⎠
IN(MAX)
VENDOR
Coilcraft
Sumida
URL
0.25• V
VOUT
V
IN(MAX)
IN(MAX)
for
> 0.5
www.coilcraft.com
www.sumida.com
www.toko.com
www.we-online.com
www.vishay.com
www.xfmrs.com
4A• fSW
Toko
where f is the switching frequency in MHz, V is the
SW
IN
Wurth Elektronik
Vishay
input voltage and L is the inductor value in μH.
To avoid overheating of the inductor, choose an inductor with
an RMS current rating that is greater than the maximum
expected output load of the application. Overload and short
circuit conditions may need to be taken into consideration.
XFMRS
Input Capacitors
Bypass the input of the LTC3311 with at least two bulk
storage ceramic capacitors close to the part, one on each
In addition, the saturation current (ISAT) rating of the
inductor must be higher than the load current plus 1/2 of
the inductor ripple current (Equation 6).
side from V to PGND. These capacitors should be 0603
IN
or 0805 in size. See layout section for more detail. X7R or
1
I
SAT ≥ILOAD MAX) + ∆IL
(6)
(
2
Rev. 0
13
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X5R capacitors are recommended for best performance
across temperature and input voltage variations. Note that
larger input capacitance is required when a lower switch-
ing frequency is used. For high frequency applications,
adding two small capacitors close to the part is recom-
mended. If the input power source has high impedance, or
there is significant inductance due to long wires or cables,
additional bulk capacitance may be necessary. This can
be provided with a low performance electrolytic capacitor.
X5R or X7R type capacitors will provide low output ripple
and good transient response. Transient performance is
improved with a higher value output capacitor and the
addition of a feedforward capacitor placed between
V
and FB. Increasing the output capacitance will also
OUT
decrease the output voltage ripple. A lower value of output
capacitor saves space and cost but transient performance
will suffer and may cause loop instability. See the Typical
Applications for suggested capacitor values.
A ceramic input capacitor combined with trace or cable
inductance forms a high quality (under damped) tank
circuit. If the LTC3311 circuit is plugged into a live sup-
ply, the input voltage can ring to twice its nominal value,
possibly exceeding the LTC3311’s voltage rating. This
situation is easily avoided (see Analog Devices Application
Note 88).
Multiphase Operation
The LTC3311 is easily configurable for multiphase opera-
tion. See Table 4.
Connecting the RT pin, of the master phase, to a resis-
tor to AGND programs the frequency and configures the
MODE/SYNC pin to become clock output used to drive
the MODE/SYNC pin of the slave phase(s).
Table 3. Ceramic Capacitor Manufacturers
VENDOR
AVX
URL
Connecting the RT pin of the master phase to V con-
IN
www.avxcorp.com
www.murata.com
www.tdk.com
figures the MODE/SYNC pin to become an input capable
of accepting an external clock. The switching frequency
defaults to the nominal 2MHz internal frequency when
the external clock is unavailable, such as during start-up.
Murata
TDK
Taiyo Yuden
Samsung
www.t-yuden.com
www.samsungsem.com
Connecting the FB pin to VIN configures a phase as a
slave. The MODE/SYNC becomes an input and the voltage
control loop is disabled. The slave phase current control
loop is still active and the peak current is controlled via the
shared ITH node. Careful consideration should be taken
when routing the ITH node between phases. Routing the
ITH and AGND nodes together is recommended to create
a low inductance path. See the Multi-Phase Demo Board
PCB layout as an example.
Output Capacitor and Output Ripple
The output capacitor has two essential functions. Along
with the inductor, it filters the square wave, generated
by the LTC3311, to produce the DC output. In this role
it determines the output ripple, thus, low impedance at
the switching frequency is important. The second func-
tion is to store energy in order to satisfy transient loads
and stabilize the LTC3311’s control loop. Ceramic capaci-
tors have very low equivalent series resistance (ESR) and
provide the best ripple performance. For good starting
values, see the Typical Applications section.
Connecting the PGOOD pins together and adding an exter-
nal pull-up resistor allows the master phase to commu-
nicate with the slave phases on when start-up has been
completed.
Table 4. LTC3311 Multiphase Configuration
Master/Slave
Master
RT Pin
FB Pin
MODE/SYNC Pin
Clock Input
Switching Frequency (f
)
SW
V
IN
V
V
Divider
External Clock/2MHz Default
RT programmed
OUT
OUT
Master
Resistor to AGND
Divider
Divider
Clock Output
Clock Input
Slave
V
V
IN
External Clock
IN
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Table 6. LTC3311 Single Phase Configuration
The phasing of a slave phase relative to the master phase
is programmed with a resistor divider on the RT pin. Use
of 1% resistors is recommended. See Table 5 for more
information.
RT Pin
Connection
MODE/SYNC
Pin Connection
MODE of
Operation
Switching
Frequency
VIN
VIN
VIN
Clock Input
AGND
Forced
External Clock
Continuous
Table 5. LTC3311 Programming Slave Phase Angle
SYNC
Forced
Continuous
2MHz Default
Phase
Angle
R3
Ratio
R4
Ratio
R3
Example
R4
VIN
Pulse Skip
2MHz Default
Example
Resistor to AGND Clock Output
Forced
Continuous
RT Programmed
0°
0Ω
3 • R
7 • R
NA
NA
R
0Ω
301k
243k
NA
NA
90°
100k
174k
0Ω
120°
180°
240°
270°
5 • R
0Ω
Synchronization
To synchronize the LTC3311 oscillator to an external fre-
quency, configure the MODE/SYNC pin as an input by
5 • R
R
7 • R
3 • R
174k
100k
243k
300k
connecting the RT pin to V . Drive the MODE/SYNC pin
IN
with a square wave in the frequency range of 500 kHz to
2.25MHz range, an amplitude greater than 1.2V and less
than 0.4V with a pulse width greater than 40ns.
When configured for master/slave operation, the slave
phases operate in forced continuous modes.
ꢅ
ꢆꢇ
The LTC3311 phase locked loop (PLL) will synchronize
the internal oscillator to the clock applied to the MODE/
SYNC pin. At start up, before the LTC3311 recognizes
the external clock applied to MODE/SYNC, the LTC3311
will switch at its default frequency of 2MHz. Once the
externally applied clock is recognized, the switching
frequency will gradually transition from the default fre-
quency to the applied frequency. If the external clock is
removed, the LTC3311 will slowly transition back to the
default frequency.
ꢈꢉ
Rꢃ
Rꢋ
ꢀꢁꢂꢃꢃꢄꢄ
Rꢁ
ꢃꢃꢄꢄ ꢈ0ꢊ
ꢌꢍꢇꢎ
Figure 2. Phase Programming
MODE of Operation
For most configurations, the LTC3311 operates in forced
continuous mode. While in forced continuous mode, reg-
ulation at low currents is achieved by allowing negative
inductor current. Switching cycles are not skipped.
The LTC3311 operates in forced continuous mode during
synchronization. An internal 200kΩ resistor on MODE/SYNC
pin to AGND allows the MODE/SYNC pin to be left floating.
Transient Response and Loop Compensation
The LTC3311 operates in pulse skip mode when both R
T
and MODE/SYNC pins are connected to V . In this mode,
the switching frequency is set with theINnominal 2MHz
internal clock. While in pulse skip mode negative current
is disallowed and regulation at low currents is achieved
by skipping switching cycles.
When determining the compensation components, C ,
FF
R , and C , control loop stability and transient response
C
C
are the two main considerations.
The LTC3311 has been designed to operate at a high band-
width for fast transient response capability. Operating at
a high loop bandwidth reduces the output capacitance
required to meet transient response requirements.
Applying a load transient and monitoring the response of
the system or using a network analyzer to measure the
actual loop response are two ways to verify and optimize
Rev. 0
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APPLICATIONS INFORMATION
the control loop stability. LTpowerCAD® is a useful tool to
help optimize the compensation components.
Output Voltage Sensing
The LTC3311 AGND pin is the ground reference for the
internal analog circuitry, including the bandgap voltage
reference. To achieve good load regulation, connect the
AGND pin to the negative terminal of the output capaci-
When using the load transient response method to sta-
bilize the control loop, apply an output current pulse of
20% to 100% of full load current having a rise time of
1µs. This will produce a transient on the output voltage
and ITH pin waveforms.
tor (C ) at the load. A drop in the high current power
OUT
ground return path will be compensated. All of the signal
components, such as the FB resistor dividers and soft-
start capacitor, should be referenced to the AGND node.
The AGND node carries very little current and, therefore,
can be a minimal size trace. See the example PCB Layout
for more information.
Switching regulators take multiple cycles to respond to
a step in load current. When a load step occurs, V
is
OUT
immediately perturbed, generating a feedback error signal
used by the regulator to return V
value.
to its steady-state
OUT
During this recovery time, monitor VOUT for overshoot
or ringing that would indicate a stability problem. The
initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with the R and the
bandwidth of the loop increases with decreasingCCC. If RC
Enable Threshold Programming
The LTC3311 has a precision threshold enable pin
to enable or disable switching. When forced low, the
LTC3311 enters a low current shutdown mode.
The rising threshold of the EN comparator is 400mV, with
60mV of hysteresis. Connect the EN pin to V if the shut-
IN
down feature is not used. Adding a resistor divider from
is increased by the same factor that C is decreased, the
C
V
to EN programs the LTC3311 to regulate the output
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, adding a feed forward capaci-
tor, CFF, improves the high frequency response. Capacitor
CFF provides phase lead by creating a high frequency zero
IN
only when V is above a desired voltage (see the Block
IN
Diagram). Typically, this threshold, V
, is used in situ-
IN(EN)
ations where the input supply is current limited or has a
relatively high source resistance. A switching regulator
draws constant power from the source, so source current
increases as source voltage drops. This looks like a nega-
tive resistance load to the source and can cause the source
to current limit or latch low under low source voltage con-
with R to improve the phase margin. The compensation
A
components of the typical application circuits are a good
starting point for component values.
The output voltage settling behavior is related to the sta-
bility of the closed-loop system. For a detailed explanation
of optimizing the compensation components, including
a review of control loop theory, refer to Analog Devices
Application Note 76.
ditions. The V
threshold prevents the regulator from
IN(EN)
operating at source voltages where problems may occur.
This threshold can be adjusted by setting the values R1
and R2 such that they satisfy Equation 9.
⎛
⎜
⎝
⎞
R1
R2
V
=
+1 • 400mV
(9)
⎟
IN EN
(
)
Output Overvoltage Protection
⎠
During an output overvoltage event, when the FB pin volt-
age is greater than 110% of nominal, the LTC3311 top
power switch will be turned off. If the output remains out
of regulation for more than 100µs, the PGOOD pin will
be pulled low.
where the LTC3311 will remain off until VIN is above
VIN(EN). Due to the comparator’s hysteresis, switching
will not stop until the input falls slightly below V
.
IN(EN)
Alternatively, a resistor divider from an output of another
regulator to the enable pin of the LTC3311 provides event-
based power-up sequencing, enabling the LTC3311 when
An output overvoltage event should not happen under
normal operating conditions.
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the output of the other regulator reaches a predetermined
level.
The following procedure is used for a more accurate mea-
surement of the junction temperature:
1. Measure the ambient temperature T .
A
Output Voltage Tracking and Soft-Start
2. Measure the SSTT voltage while in pulse skip mode
with the VOUT pulled up slightly higher than the
The LTC3311 allows the user to program its output volt-
age ramp rate by means of the SSTT pin.
regulated V
.
OUT
An internal 10μA pulls up the SSTT pin. Putting an external
capacitor on SSTT enables soft-starting the output to pre-
vent current surge on the input supply and output voltage
overshoot. During the soft-start ramp, the output volt-
age will proportionally track the SSTT pin voltage. When
the soft-start is complete, the pin will servo to a voltage
proportional to the LTC3311 junction temperature. See
Figure 3 showing the SSTT pin operating range.
3. Calculate the slope of the temperature sensing circuit
with Equation 12.
VSSTT
TA +273
Slope (mV /°C)=
(12)
4. Calculate the junction temperature with the new cali-
brated slope.
When the output voltage goes out of regulation and the
power good pin is pulled low, the soft-start pin no longer
reports the temperature.
The soft-start time is calculated using Equation 10.
500mV
t
SS = CSS •
(10)
10µA
ꢍꢎ0
ꢍꢏꢎ
For output tracking applications, SSTT can be externally
driven by another voltage source. From 0V to 0.5V, the
SSTT voltage will override the internal 0.5V reference
input to the error amplifier, thus regulating the FB pin
voltage to that of SSTT pin. When SSTT is above 0.5V,
tracking is disabled and the feedback voltage will regulate
to the internal reference voltage
ꢍ00
ꢐꢎ
ꢔꢔꢃꢃ ꢅꢁꢖ ꢌꢕꢚꢃꢛꢜꢂ
ꢕꢅꢂRꢛꢃꢁꢖꢜ Rꢛꢖꢜꢂ
ꢀꢁꢂ ꢃꢂꢄꢅ
ꢆꢇꢈꢉ
ꢃꢂꢄꢅ
ꢄꢕꢖꢁꢃꢕR
ꢗꢓꢘꢌꢙꢇꢈ
ꢎ0
ꢏꢎ
0.ꢑ
0.ꢎ
0.ꢓ
0.ꢒ
0.ꢏ
0.ꢍ
0
An active pull-down circuit is connected to the SSTT pin
to discharge the external soft-start capacitor in the case
of fault conditions. The ramp will restart when the fault is
cleared. Fault conditions that clear the soft-start capacitor
are the EN/UV pin transitioning low, VIN voltage falling too
low or thermal shutdown.
ꢊꢋ
ꢆꢌꢉ
ꢔꢕꢊꢃꢝꢔꢃꢛRꢃ
ꢛꢖꢀ ꢃRꢛꢈꢞꢁꢖꢜ
0
0.ꢍ 0.ꢏ 0.ꢒ 0.ꢓ 0.ꢎ 0.ꢑ ꢍ.ꢏ ꢍ.ꢒ ꢍ.ꢓ ꢍ.ꢎ ꢍ.ꢑ ꢍ.ꢐ ꢔꢔꢃꢃ ꢆꢌ
ꢒꢒꢍꢍ ꢊ0ꢒ
Figure 3. Soft-Start and Temperature Monitor Operation
Temperature Monitor
Output Power Good
Once the soft-start cycle has completed and the output
power good flag thrown, the SSTT pin reports the die
junction temperature. The LTC3311 regulates the SSTT
pin to a voltage proportional to the junction temperature.
While reporting the temperature, the SSTT voltage is not
valid below 1V. The junction temperature is calculated
with Equation 11.
When the LTC3311’s output voltage is within the –2/+10%
window of the nominal regulation voltage the output is
considered good and the open-drain PGOOD pin goes
high impedance and is typically pulled high with an exter-
nal resistor. Otherwise, the internal pull-down device will
pull the PGOOD pin low. To prevent glitching both the
upper and lower thresholds, include 1% of hysteresis as
well as a built in time delay, typically 100µs. The PGOOD
VSSTT
4mV
(11)
TJ (°C)=
–273
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pin is also actively pulled low during fault conditions: EN
The LTC3311 does not have any internal bypass capacitors
and hence requires three additional 0201 external capaci-
pin is low, V is too low or in thermal shutdown.
IN
tors (C , C , and C ), as shown in Figure 4. Place
IN5 IN6
IN7
For multiphase applications the PGOOD pin is used for
communication between the master and slave phases.
these capacitors as close as possible to the IC.
Connect the PGOOD pins together and pull-up to V or
To avoid noise coupling into FB, the resistor divider
should be placed near the FB and AGND pins and physi-
cally close to the LTC3311. The remote output and ground
traces should be routed together as a differential pair to
the remote output. These traces should be terminated as
close as physically possible to the remote output point
that is to be accurately regulated through remote differ-
ential sensing.
IN
V
with an external resistor.
OUT
Output Short Circuit Protection and Recovery
The peak inductor current at which the current compara-
tor shuts off the top power switch is controlled by the
voltage on the ITH pin. If the output current increases,
the error amplifier raises the ITH pin voltage until the
average inductor current matches the new load current.
In normal operation, the LTC3311 clamps the maximum
ITH pin voltage.
See Figure 4 for a recommended PCB layout.
ꢏRꢁꢂꢈꢐ ꢒꢆꢊꢈꢓ ꢁꢈ ꢆꢊꢔꢓR ꢅ
ꢑ
ꢇꢈ
When the output is shorted to ground, the inductor cur-
rent decays very slowly during the switch off time because
of the low voltage across the inductor. To keep the current
in control, a secondary limit is also imposed on the valley
inductor current. If the inductor current measured through
ꢀ
ꢀꢄ
ꢀ
R
ꢕꢕ
ꢃ
ꢀ
ꢋꢋ
R
ꢊ
ꢉ
the bottom power switch increases beyond I
,
VALLEY(MAX)
the top power switch will be held off and switching cycles
will be skipped until the inductor current is reduced.
ꢀ
R
ꢀ
ꢀꢅ
R
ꢄ
ꢍ
ꢄꢗ
ꢄ0
ꢀ
ꢇꢈꢎ
Recovery from a short circuit can be abrupt and because
the output is shorted and below regulation the regulator
is requesting the maximum current to charge the output.
When the short circuit condition is removed, the induc-
tor current could cause an extreme voltage overshoot in
the output. The LTC3311 addresses this potential issue
by regulating the SSTT voltage just above the FB volt-
age anytime the output is out of regulation. Therefore,
a recovery from an output short circuit goes through a
soft-start cycle. The output ramp is controlled and the
overshoot is minimized.
ꢄꢘ
ꢌ
ꢄꢍ
ꢙ
ꢀ
ꢇꢈꢌ
ꢄꢙ
ꢀ
ꢀ
ꢇꢈꢅ
ꢇꢈꢄ
ꢀ
ꢇꢈꢍ
ꢏꢈꢐ
ꢏꢈꢐ
ꢀ
ꢆ
ꢀ
ꢁꢂꢃꢅ
ꢁꢂꢃꢄ
ꢃꢁ ꢑ
ꢚ ꢏꢈꢐ
ꢁꢂꢃ
Rꢓꢛꢁꢃꢓ ꢕꢓꢈꢕꢓ
ꢑ
ꢁꢂꢃ
ꢖꢖꢄ0 ꢋ0ꢗ
Low EMI PCB Layout
The LTC3311 is specifically designed to minimize EMI/
EMC emissions and also to maximize efficiency when
switching at high frequencies. For optimal performance,
the LTC3311 requires the use of multiple VIN bypass
capacitors.
Figure 4. Recommended PCB Layout for the LTC3311
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Large, switched currents flow in the LTC3311 VIN, SW and
PGND pins and the input capacitors. The loops formed
by the input capacitors should be as small as possible by
placing the capacitors adjacent to the VIN and PGND pins.
Place the input capacitors, inductor and output capaci-
tors on the same layer of the circuit board. Place a local,
unbroken ground plane under the application circuit on
the layer closest to the surface layer.
High Temperature Considerations
For higher ambient temperatures, care should be taken
in the layout of the PCB to ensure good heat sinking of
the LTC3311. The PGND pins and the exposed pad on the
bottom of the package should be soldered to a ground
plane. This ground should be tied to large copper layers
below with many thermal vias; these layers will spread
heat dissipated by the LTC3311. Placing additional vias
can reduce thermal resistance further. The maximum load
current should be derated as the ambient temperature
approaches the maximum junction rating. Power dissi-
pation within the LTC3311 can be estimated by calculat-
ing the total power loss from an efficiency measurement
and subtracting the inductor loss. The die temperature is
monitored with the SSTT pin.
The SW node should be as short as possible. Finally,
keep the FB and RT nodes small and away from the noisy
SW node.
TYPICAL APPLICATIONS
Dual Phase 5V to 3.3V, 25A, Forced Continuous Mode
ꢇ
ꢗꢓ
ꢜ.ꢊꢇ ꢁꢈ ꢊ.ꢊꢇ
ꢄꢙꢐ
ꢆꢆꢙꢐ
0.0ꢄꢙꢐ
ꢒꢓ
0.0ꢄꢙꢐ
ꢆꢆꢙꢐ
ꢄꢔ
ꢋꢌꢈꢈꢍ
ꢄ00ꢡ
ꢇ
ꢗꢓ
ꢋꢌꢈꢈꢍ
ꢎꢏ
ꢇ
ꢃ.ꢃꢇ
ꢆꢊꢅ
ꢆ00ꢟꢘ
ꢈꢉꢁ
ꢄ00ꢡ
ꢆꢝꢜꢡ
ꢜ.ꢝꢞꢐ
ꢀꢁꢂꢃꢃꢄꢄ
ꢔꢈꢍꢒꢕꢎꢖꢓꢂ
ꢗꢁꢘ
ꢆꢆꢙꢐ
ꢛꢃ
ꢐꢑ
Rꢁ
ꢜꢢ.ꢝꢡ
ꢎꢎꢁꢁ
ꢅꢌꢓꢍ ꢋꢌꢓꢍ
ꢆꢝꢜꢡ
ꢜ.ꢠꢠꢡ
0.ꢄꢙꢐ
ꢜꢝ0ꢞꢐ
ꢇ
ꢗꢓ
ꢆꢆꢙꢐ
ꢄꢙꢐ
ꢆꢆꢙꢐ
0.0ꢄꢙꢐ
0.0ꢄꢙꢐ
ꢆ00ꢟꢘ
ꢇ
ꢗꢓ
ꢋꢌꢈꢈꢍ
ꢒꢓ
ꢋꢌꢈꢈꢍ
ꢎꢏ
ꢔꢈꢍꢒꢕꢎꢖꢓꢂ
ꢆꢆꢙꢐ
ꢚꢆ
ꢓꢂ
ꢎꢎꢁꢗ
ꢗꢁꢘ
ꢀꢁꢂꢃꢃꢄꢄ
ꢐꢑ
ꢇ
ꢗꢓ
ꢄꢢ0ꢣ
ꢅꢌꢓꢍ ꢋꢌꢓꢍ Rꢁ
ꢃꢃꢄꢄ ꢁꢅ0ꢆ
ꢀ ꢤ ꢂꢈꢗꢀꢂRꢅꢐꢁꢥ ꢦꢒꢀꢜ0ꢃ0ꢧꢆ0ꢄꢔꢒ
Rev. 0
19
For more information www.analog.com
LTC3311
TYPICAL APPLICATIONS
Three Phase, 0.6V, 37.5A, Forced Continuous Mode
ꢆ
ꢚꢖ
ꢃ.0ꢆ ꢁꢇ ꢜ.ꢋꢆ
0.0ꢄꢍꢎ
ꢄ0ꢞꢎ
ꢄꢍꢎ
ꢌꢌꢍꢎ
0.0ꢄꢍꢎ
ꢌꢌꢍꢎ
ꢄ00ꢠ
ꢏꢐꢇꢇꢑ
ꢆ
ꢚꢖ
ꢕꢖ
ꢗꢇꢑꢕꢘꢒꢙꢖꢂ
ꢀꢁꢂꢃꢃꢄꢄ
ꢏꢐꢇꢇꢑ
ꢆ
ꢊ0ꢟꢛ
ꢇꢈꢁ
0.ꢉꢆ
ꢒꢓ
ꢃꢊ.ꢋꢅ
ꢢꢉ.ꢉꢠ
ꢜꢃꢌꢠ
ꢜꢊꢍꢎ
ꢝꢃ
ꢚꢁꢛ
ꢎꢔ
Rꢁ
ꢋ.ꢜꢡꢠ
ꢒꢒꢁꢁ
ꢅꢐꢖꢑ ꢏꢐꢖꢑ
ꢌꢊꢜꢣ
ꢄꢋ00ꢞꢎ
0.ꢄꢍꢎ
ꢆ
ꢚꢖ
ꢌꢌꢍꢎ
ꢄꢍꢎ
ꢌꢌꢍꢎ
0.0ꢄꢍꢎ
ꢖꢂ
0.0ꢄꢍꢎ
ꢆ
ꢚꢖ
ꢏꢐꢇꢇꢑ
ꢊ0ꢟꢛ
ꢕꢖ
ꢏꢐꢇꢇꢑ
ꢒꢓ
ꢗꢇꢑꢕꢘꢒꢙꢖꢂ
ꢆ
ꢚꢖ
ꢜꢊꢍꢎ
ꢝꢌ
ꢒꢒꢁꢁ
ꢚꢁꢛ
ꢀꢁꢂꢃꢃꢄꢄ
ꢎꢔ
ꢌꢜꢃꢠ
ꢄꢊꢜꢠ
ꢄꢌ0ꢤ
ꢅꢐꢖꢑ ꢏꢐꢖꢑ Rꢁ
ꢆ
ꢆ
ꢚꢖ
ꢌꢌꢍꢎ
ꢄꢍꢎ
ꢌꢌꢍꢎ
0.0ꢄꢍꢎ
ꢖꢂ
0.0ꢄꢍꢎ
ꢚꢖ
ꢏꢐꢇꢇꢑ
ꢊ0ꢟꢛ
ꢕꢖ
ꢏꢐꢇꢇꢑ
ꢒꢓ
ꢗꢇꢑꢕꢘꢒꢙꢖꢂ
ꢆ
ꢚꢖ
ꢜꢊꢍꢎ
ꢝꢌ
ꢒꢒꢁꢁ
ꢚꢁꢛ
ꢀꢁꢂꢃꢃꢄꢄ
ꢎꢔ
ꢄꢊꢜꢠ
ꢌꢜꢃꢠ
ꢌꢜ0ꢤ
ꢅꢐꢖꢑ ꢏꢐꢖꢑ Rꢁ
ꢃꢃꢄꢄ ꢁꢅ0ꢃ
ꢀ ꢥ ꢂꢇꢚꢀꢂRꢅꢎꢁ ꢦꢕꢀꢃꢋꢌ0ꢧꢊ00ꢗꢕꢔ
Rev. 0
20
For more information www.analog.com
LTC3311
TYPICAL APPLICATIONS
Four Phase, 2MHz, 1.2V, 50A, Forced Continuous Mode
ꢇ
ꢘꢔ
ꢃ.0ꢇ ꢁꢈ ꢋ.ꢋꢇ
ꢄꢚꢑ
ꢊꢊꢚꢑ
0.0ꢄꢚꢑ
0.0ꢄꢚꢑ
ꢊꢊꢚꢑ
ꢄ00ꢝ
ꢌꢍꢈꢈꢎ
ꢇ
ꢘꢔ
ꢓꢔ
ꢕꢈꢎꢓꢖꢏꢗꢔꢂ
ꢀꢁꢂꢃꢃꢄꢄ
ꢌꢍꢈꢈꢎ
ꢇ
ꢄ.ꢊꢇ
ꢋ0ꢅ
ꢄ00ꢜꢙ
ꢈꢉꢁ
ꢏꢐ
ꢣ.ꢠꢟꢑ
ꢄꢆ0ꢝ
ꢊꢊꢚꢑ
ꢛꢃ
ꢘꢁꢙ
ꢑꢒ
Rꢁ
ꢄ00ꢝ
ꢃ.ꢃꢊꢝ
ꢏꢏꢁꢁ
ꢅꢍꢔꢎ ꢌꢍꢔꢎ
ꢊꢞꢆꢝ
ꢆꢞ0ꢟꢑ
0.ꢄꢚꢑ
ꢇ
ꢘꢔ
ꢄꢚꢑ
ꢄꢚꢑ
ꢄꢚꢑ
ꢊꢊꢚꢑ
ꢊꢊꢚꢑ
ꢊꢊꢚꢑ
0.0ꢄꢚꢑ
0.0ꢄꢚꢑ
ꢊꢊꢚꢑ
ꢇ
ꢘꢔ
ꢌꢍꢈꢈꢎ
ꢄ00ꢜꢙ
ꢓꢔ
ꢌꢍꢈꢈꢎ
ꢏꢐ
ꢕꢈꢎꢓꢖꢏꢗꢔꢂ
ꢇ
ꢘꢔ
ꢊꢊꢚꢑ
ꢛꢊ
ꢔꢂ
ꢏꢏꢁꢁ
ꢘꢁꢙ
ꢀꢁꢂꢃꢃꢄꢄ
ꢑꢒ
ꢃ0ꢄꢝ
ꢄ00ꢝ
ꢢ0ꢡ
ꢅꢍꢔꢎ ꢌꢍꢔꢎ Rꢁ
ꢇ
ꢇ
ꢘꢔ
ꢊꢊꢚꢑ
0.0ꢄꢚꢑ
0.0ꢄꢚꢑ
ꢘꢔ
ꢌꢍꢈꢈꢎ
ꢄ00ꢜꢙ
ꢓꢔ
ꢌꢍꢈꢈꢎ
ꢏꢐ
ꢕꢈꢎꢓꢖꢏꢗꢔꢂ
ꢊꢊꢚꢑ
ꢛꢊ
ꢔꢂ
ꢏꢏꢁꢁ
ꢘꢁꢙ
ꢀꢁꢂꢃꢃꢄꢄ
ꢇ
ꢘꢔ
ꢑꢒ
ꢄꢠ0ꢡ
ꢅꢍꢔꢎ ꢌꢍꢔꢎ Rꢁ
ꢇ
ꢇ
ꢘꢔ
ꢊꢊꢚꢑ
0.0ꢄꢚꢑ
0.0ꢄꢚꢑ
ꢘꢔ
ꢌꢍꢈꢈꢎ
ꢄ00ꢜꢙ
ꢓꢔ
ꢌꢍꢈꢈꢎ
ꢏꢐ
ꢕꢈꢎꢓꢖꢏꢗꢔꢂ
ꢇ
ꢘꢔ
ꢔꢂ
ꢊꢊꢚꢑ
ꢛꢊ
ꢏꢏꢁꢁ
ꢘꢁꢙ
ꢀꢁꢂꢃꢃꢄꢄ
ꢑꢒ
ꢄ00ꢝ
ꢃ0ꢄꢝ
ꢊꢞ0ꢡ
ꢅꢍꢔꢎ ꢌꢍꢔꢎ Rꢁ
ꢃꢃꢄꢄ ꢁꢅ0ꢆ
ꢀ ꢤ ꢂꢈꢘꢀꢂRꢅꢑꢁꢥ ꢦꢓꢀꢆ0ꢃ0ꢧꢄ0ꢄꢕꢓ
Rev. 0
21
For more information www.analog.com
LTC3311
TYPICAL APPLICATIONS
Four Phase, 2MHz, 1.2V, 50A Driven with External Clock, Forced Continuous Mode
ꢌ
ꢙꢃ
ꢉ.0ꢌ ꢂꢇ ꢋ.ꢋꢌ
ꢊꢛꢔ
ꢎꢎꢛꢔ
0.0ꢊꢛꢔ
0.0ꢊꢛꢔ
ꢎꢎꢛꢔ
ꢌ
ꢙꢃ
ꢏꢐꢇꢇꢑ
ꢊ00ꢝꢚ
ꢀꢃ
ꢖꢇꢑꢀꢗꢒꢘꢃꢆ
ꢅꢂꢆꢉꢉꢊꢊ
ꢏꢐꢇꢇꢑ
ꢌ
ꢊ.ꢎꢌ
ꢋ0ꢄ
ꢇꢍꢂ
ꢒꢓ
ꢀꢁꢂꢀRꢃꢄꢅ
ꢆꢅꢇꢆꢈ
ꢥ.ꢢꢡꢔ
ꢊꢟ0ꢞ
ꢎꢎꢛꢔ
ꢜꢉ
ꢙꢂꢚ
ꢔꢕ
Rꢂ
ꢌ
ꢙꢃ
ꢊ00ꢞ
ꢉ.ꢉꢎꢞ
ꢒꢒꢂꢂ
ꢄꢐꢃꢑ ꢏꢐꢃꢑ
ꢟꢠ0ꢡꢔ
0.ꢊꢛꢔ
ꢌ
ꢙꢃ
ꢊꢛꢔ
ꢊꢛꢔ
ꢊꢛꢔ
ꢎꢎꢛꢔ
ꢎꢎꢛꢔ
ꢎꢎꢛꢔ
0.0ꢊꢛꢔ
0.0ꢊꢛꢔ
ꢎꢎꢛꢔ
ꢌ
ꢙꢃ
ꢏꢐꢇꢇꢑ
ꢊ00ꢝꢚ
ꢀꢃ
ꢏꢐꢇꢇꢑ
ꢒꢓ
ꢖꢇꢑꢀꢗꢒꢘꢃꢆ
ꢌ
ꢙꢃ
ꢃꢆ
ꢎꢎꢛꢔ
ꢜꢎ
ꢒꢒꢂꢂ
ꢙꢂꢚ
ꢅꢂꢆꢉꢉꢊꢊ
ꢔꢕ
ꢉ0ꢊꢞ
ꢊ00ꢞ
ꢤ0ꢣ
ꢄꢐꢃꢑ ꢏꢐꢃꢑ Rꢂ
ꢌ
ꢌ
ꢙꢃ
ꢎꢎꢛꢔ
0.0ꢊꢛꢔ
0.0ꢊꢛꢔ
ꢙꢃ
ꢏꢐꢇꢇꢑ
ꢊ00ꢝꢚ
ꢀꢃ
ꢏꢐꢇꢇꢑ
ꢒꢓ
ꢖꢇꢑꢀꢗꢒꢘꢃꢆ
ꢃꢆ
ꢒꢒꢂꢂ
ꢙꢂꢚ
ꢎꢎꢛꢔ
ꢜꢎ
ꢅꢂꢆꢉꢉꢊꢊ
ꢌ
ꢙꢃ
ꢔꢕ
ꢊꢢ0ꢣ
ꢄꢐꢃꢑ ꢏꢐꢃꢑ Rꢂ
ꢌ
ꢌ
ꢙꢃ
ꢎꢎꢛꢔ
0.0ꢊꢛꢔ
0.0ꢊꢛꢔ
ꢙꢃ
ꢏꢐꢇꢇꢑ
ꢊ00ꢝꢚ
ꢀꢃ
ꢏꢐꢇꢇꢑ
ꢒꢓ
ꢖꢇꢑꢀꢗꢒꢘꢃꢆ
ꢌ
ꢙꢃ
ꢃꢆ
ꢎꢎꢛꢔ
ꢜꢎ
ꢒꢒꢂꢂ
ꢙꢂꢚ
ꢅꢂꢆꢉꢉꢊꢊ
ꢔꢕ
ꢊ00ꢞ
ꢉ0ꢊꢞ
ꢎꢠ0ꢣ
ꢄꢐꢃꢑ ꢏꢐꢃꢑ Rꢂ
ꢉꢉꢊꢊ ꢂꢄ0ꢋ
ꢅ ꢦ ꢆꢇꢙꢅꢆRꢄꢔꢂꢧ ꢁꢀꢅꢟ0ꢉ0ꢨꢊ0ꢊꢖꢀ
Rev. 0
22
For more information www.analog.com
LTC3311
TYPICAL APPLICATIONS
5MHz, 1V, 12.5A, Forced Continuous Mode
V
IN
3.0V TO 3.6V
22µF
0.1µF
0.1µF
22µF
649k
100k
V
IN
EN
PGOOD
SW
55nH
V
OUT
1V
12.5A
MODE/SYNC
SSTT
10pF 100k
100k
22µF
×3
FB
LTC3311
PGND
V
1μF
IN
0.1µF
AGND
RT
ITH
4.12k
680pF
100k
WURTH 744340300055
3311 TA06
2MHz, 3.3V, 12.5A, Pulse Skip Mode
V
IN
4.5V TO 5.5V
22µF
0.1µF
0.1µF
100k
22µF
1M
V
IN
V
EN
PGOOD
OUT
PGOOD
100k
200nH
V
OUT
V
MODE/SYNC
SSTT
IN
3.3V
SW
FB
12.5A
LTC3311
PGND
10pF 562k
100k
22µF
x2
0.1µF
V
1μF
IN
ITH
AGND
RT
1k
1500pF
V
IN
3311 TA07
L = COILCRAFT, XEL4030-201ME
High Efficiency, 2MHz, 0.5V, 12.5A, Forced Continuous Mode, Low Part Count
V
IN
3.0V TO 4.3V
22µF
0.1µF
0.1µF
22µF
V
IN
EN
PGOOD
SW
55nH
V
OUT
MODE/SYNC
0.5V
SSTT
ITH
12.5A
0.1µF
47µF
×4
FB
1MΩ
LTC3311
PGND
V
1μF
IN
AGND
RT
6.81k
680pF
V
IN
3311 TA08
WURTH 744340300055
Rev. 0
23
For more information www.analog.com
LTC3311
TYPICAL APPLICATIONS
2MHz, 1.0V, Forced Continuous
1.5A DC to 7.5A Step Load 6A/µs Transient, 1.8% VOUT Deviation
V
IN
3.3V 10ꢀ
22µF
0.1µF
0.1µF
22µF
1M
100k
V
IN
V
EN
PGOOD
OUT
PGOOD
249k
100nH
V
OUT
MODE/SYNC
SSTT
1V
SW
FB
12.5A
LTC3311
PGND
100pF 124k
113k
47µF
x7
0.1µF
V
IN
1μF
ITH
AGND
RT
3.3pF
20k
270pF
V
IN
3311 TA09a
1.69M
L = COILCRAFT, XEL4030-101ME
ꢆ
ꢇꢈꢉ
ꢀ0ꢊꢆꢃꢄꢅꢆ
ꢅ
ꢇꢈꢉ
ꢋ.ꢌꢍ
ꢎ.ꢌꢍ
ꢒꢓꢔꢕ Rꢍꢉꢔ ꢖ ꢗꢍꢃꢁꢂ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢏꢏꢎꢎ ꢉꢍ0ꢐꢑ
Rev. 0
24
For more information www.analog.com
LTC3311
PACKAGE DESCRIPTION
ꢜ
ꢛ
ꢞ
ꢠ ꢄ ꢄ ꢄ
ꢯ ꢯ ꢯ
ꢞ
ꢞ
× ꢏ ꢎ
ꢞ
ꢦ ꢦ ꢤ ꢤ ꢤ
ꢞ
0 . ꢨ ꢌ 0 0
0 . ꢟ ꢌ 0 0
0 . 0 0 0 0
0 . ꢟ ꢌ 0 0
0 . ꢨ ꢌ 0 0
ꢝ ꢝ ꢝ
ꢞ
× ꢟ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
25
LTC3311
TYPICAL APPLICATION
3MHz, 1.0V, 12.5A , Forced Continuous Mode
V
IN
3.0V TO 5.5V
22µF
0.1µF
0.1µF
22µF
V
IN
EN
PGOOD
SW
72nH
V
OUT
MODE/SYNC
1.0V
SSTT
ITH
12.5A
10pF 100k
100k
0.1µF
22µF
×3
FB
LTC3311
PGND
V
IN
1μF
AGND
4.75k
470pF
RT
178k
3311 TA10a
L = COILCRAFT, XEL3515-720MEB
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
Switching Frequencies Up to 5MHz. Silent Switcher Architecture 2 for Ultralow EMI
LTC3311S
5V, 12.5A Synchronous Step-Down
Silent Switcher 2 in 3mm × 3mm LQFN
Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to V Output Voltage Range with 1%
IN
Accuracy. PGOOD Indication, R Programming, SYNC Input. Configurable for Paralleling
T
Power Stages. Pin Compatible with LTC3310/LTC3310S. 3mm × 3mm LQFN-18 Package.
LTC3310/
LTC3310S
5V, 10A Synchronous Step-Down
Silent Switcher/Silent Switcher 2 in
3mm × 3mm LQFN
Switching Frequencies Up to 5MHz. Silent Switcher/Silent Switcher 2 Architecture for
Ultralow EMI Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to V Output
IN
Voltage Range with 1% Accuracy. PGOOD Indication, R Programming, SYNC Input.
T
Configurable for Paralleling Power Stages. 150°C Operation (LTC3310). Pin Compatible
with LTC3311/LTC3311S. 3mm × 3mm LQFN-18 Package.
LTC3315A/
LTC3315B
Dual 5V, 2A Synchronous Step-Down DC/DCs in Dual Monolithic Synchronous Step-Down Voltage Regulators each Capable of Supplying
2mm × 2mm LQFN
2A at Switching Frequencies up to 3MHz(A) and 10MHz(B). 2.25V to 5.5V Input
Operating Range. 0.5V to V Output Voltage Range with 1% Accuracy.
IN
PGOOD Indication, SYNC Input. 2mm × 2mm LQFN-12.
LTC3636/
LTC3636-1
Dual Channel 6A, 20V Monolithic Synchronous 95% Efficiency, V : 3.1V to 20V, V
= 0.6V (LTC3636), 1.8V (LTC3636-1),
OUT(MIN)
IN
Step-Down Regulator
I = 1.3mA, I < 13µA, 4mm × 5mm QFN-28
Q SD
LTC3615/
Dual Channel 5.5V, 3A (I ), 4MHz, Synchronous 94% Efficiency, V : 2.25V to 5.5V, V
= 0.6V, I = 130µA, I < 1µA,
Q SD
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
LTC3615-1
Step-Down DC/DC Converter
4mm × 4mm QFN-24 Package
LTC3614/
LTC3616
5.5V, 4A/6A (I ), 4MHz, Synchronous Step-
95% Efficiency, V : 2.25V to 5.5V, V
= 0.6V, I = 75µA, I < 1µA,
Q SD
OUT
IN
Down DC/DC Converter with Tracking and DDR 3mm × 5mm QFN-24 Package
LTC3612
LTC7150S
LT8642S
LT8640S
LT8650S
LTC7151S
5.5V, 3A (I ), 4MHz, Synchronous Step-
95% Efficiency, V : 2.25V to 5.5V, V
= 0.8V, I = 60µA, I < 1µA,
Q SD
OUT
IN
Down DC/DC Converter
TSSOP-16E and 4mm × 4mm QFN-16 Packages
20V, 20A Synchronous Step-Down
Silent Switcher 2 Regulator
92% Efficiency, V : 3.1V to 20V, V = 0.6V, I = 2mA, I ≤ 40µA,
IN
OUT(MIN)
Q
SD
Differential Remote Sense, 6mm × 5mm BGA
18V, 10A Synchronous Step-Down
Silent Switcher 2 Regulator
96% Efficiency, V : 2.8V to 18V, V
= 0.6V, I = 240µA, I < 1µA,
Q SD
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
4mm × 4mm LQFN-24
42V, 6A Synchronous Step-Down Silent Switcher 2
with 2.5μA Quiescent Current
96% Efficiency, V : 3.4V to 42V, V
= 1.0V, I = 230µA, I < 1µA,
Q SD
IN
4mm × 4mm LQFN-24
Dual Channel 4A, 42V, Synchronous Step-Down 94.5% Efficiency, V : 3V to 42V, V
Silent Switcher 2 with 6.2µA Quiescent Current 4mm × 6mm LQFN-32
= 0.8V, I = 5mA, I < 2µA,
Q SD
IN
20V, 15A Synchronous Step-Down
Silent Switcher 2 Regulator
92.5% Efficiency, V : 3.1V to 20V, V
= 0.5V, I = 2mA, I < 20µA,
IN
OUT(MIN) Q SD
4mm × 5mm LQFN-28
LTC3307A/B, 3A, 4A and 6A 5V Synchronous Step-Down
Monolithic Synchronous Step-Down DC/DC Capable of Supplying up to 6A at Switching
LTC3308A/B, Silent Switcher DC/DC in 2mm × 2mm LQFN-12 Frequencies Up to 3MHz(A) and 10MHz(B). Silent Switcher Architecture for Ultralow EMI
LTC3309A/B
Emissions. 2.25V to 5.5V Input Operating Range. 0.5V to V Output Voltage Range with
IN
1% Accuracy. PGOOD Indication, RT Programming, SYNC Input. 2mm × 2mm LQFN-12
Rev. 0
01/21
www.analog.com
26
ANALOG DEVICES, INC. 2021
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