LTC4283 [ADI]
High Voltage High Current Hot Swap Controller;
| 型号： | LTC4283 |
| 厂家： | 
ADI |
| 描述： | High Voltage High Current Hot Swap Controller |
| 文件： | 总32页 (文件大小：1451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4238
High Voltage High Current
Hot Swap Controller
FEATURES
DESCRIPTION
The LTC®4238 is a high voltage high current Hot Swap
controller that allows a board to be safely inserted and
removed from a live backplane. Dual 12V gate drive is
well suited for high power applications to either share
safe operating area across parallel MOSFETs or support
a 2-stage start-up that first charges the load capacitance
followed by enabling a low on-resistance path to the load.
n
Allows Safe Board Insertion into Live Backplane
n
Wide Operating Voltage Range: 6.5V to 80V
n
Drives Two Gates for High Power Applications
n
Configurable Parallel, Staged Start or
Single MOSFET Modes
n
Adjustable Precision Current Limit: 6mV to 20mV
n
Current Foldback Limits MOSFET Power
n
SOA Timer Optimizes MOSFET Capability
The device features active current limiting (ACL) with two
foldback options as V increases. The constant power
profile limits the power dissipation to be no higher than
a fixed value, while the high power profile allows the part
to ride through large input steps during operation.
n
Monitors V and V for MOSFET Health
GS
DS
DS
n
n
n
12V Gate Drive for Lower MOSFET R
DS(ON)
Parallelable Controllers for Very High Current Levels
Available in 24-Lead Narrow SSOP and 24-Pin
4mm × 5mm QFN Packages
The LTC4238 notifies when output power is good. In
addition, it has protection features that respond to input
undervoltage, overvoltage; and generate a fault when
there is an overcurrent or FET bad condition.
APPLICATIONS
n
Live Board Insertion in 12V, 24V and 48V Systems
n
Industrial High Side Switch/Circuit Breaker
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 9634480, 9634481, 9671465B2, 10003190B2. More patents pending.
n
Computers, Servers
Vehicle Electrical Systems
n
TYPICAL APPLICATION
48V, 63A Hot Swap Controller in Low Stress Staged Start Mode
4mΩ
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Start-Up Behavior
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Rev. 0
1
Document Feedback
For more information www.analog.com
LTC4238
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
(Notes 1 and 2)
Output Voltages
V
...................................................... –0.3V to 100V
CC
GATE, PG, FLT#.................................... –0.3V to 100V
COMM .................................................. –0.3V to 5.5V
Output Currents
DD
INTV .................................................. –0.3V to 5.5V
Input Voltages
GATE – SOURCE (Note 3) ...................... –0.3V to 10V
INTV ...............................................................10mA
Operating Junction Temperature Range
CC
+
–
+
SENSE1 , SENSE1 , SENSE2 ,
–
SENSE2 ............................. V – 4.5V to V + 0.3V
LTC4238C................................................ 0°C to 70°C
LTC4238I .............................................–40°C to 85°C
LTC4238H.......................................... –40°C to 125°C
Storage Temperature Range
GN Package ....................................... –65°C to 150°C
UFD Package ..................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)...................300°C
DD
DD
SOURCE, FB, OV, UV, .......................... –0.3V to 100V
........................................... –0.3V to V +0.3V
V
DSFB
DD
TMR, TMRFET, ISET, CONFIG1,
CONFIG2 ...............................–0.3V to INTV + 0.3V
CC
PIN CONFIGURATION
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ꢞ ꢀꢄ0ꢟꢓꢠ θ ꢞ ꢇꢄꢟꢓꢡꢏ
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ꢞ ꢟꢖ0ꢠꢍꢡ θ ꢞ ꢑꢢꢠꢍꢣꢈ
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ORDER INFORMATION
TUBE
TAPE AND REEL
PART MARKING*
4238
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4238CUFD#PBF
LTC4238IUFD#PBF
LTC4238HUFD#PBF
LTC4238CGN#PBF
LTC4238IGN#PBF
LTC4238HGN#PBF
LTC4238CUFD#TRPBF
LTC4238IUFD#TRPBF
LTC4238HUFD#TRPBF
LTC4238CGN#TRPBF
LTC4238IGN#TRPBF
LTC4238HGN#TRPBF
24-Lead (4mm × 5mm) Plastic QFN
24-Lead (4mm × 5mm) Plastic QFN
24-Lead (4mm × 5mm) Plastic QFN
24-Lead Plastic SSOP
4238
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
4238
LTC4238GN
LTC4238GN
LTC4238GN
24-Lead Plastic SSOP
–40°C to 85°C
–40°C to 125°C
24-Lead Plastic SSOP
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
2
For more information www.analog.com
LTC4238
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 48V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
l
l
l
l
l
l
l
V
Input Supply Range
6.5
80
5
V
mA
V
DD
I
Input Supply Current
3
6
DD
V
V
Input Supply Undervoltage Lockout
Input Supply Undervoltage Lockout Hysteresis
Internal 5V Supply Voltage
V
Rising
5.8
6.2
DD(UVLO)
DD(HYST)
DD
500
5.0
4
mV
V
INTV
INTV
INTV
I
= 0mA to 10mA
4.5
5.5
CC
LOAD
INTV Undervoltage Lockout Threshold
INTV Rising
3.75
4.25
V
CC(UVLO)
CC(HYST)
CC
CC
INTV Undervoltage Lockout Hysteresis
110
mV
CC
Current Limit
l
l
ΔV
Current Limit Sense Voltage Threshold
ISET= 0V
ISET = INTV
5.8
19.5
6
20
6.2
20.5
mV
mV
SNS(TH)
+
–
(SENSE – SENSE )
CC
l
l
10% Current Limit Foldback, Start-Up Only
ISET = 0V
ISET = INTV
0.18
1.6
0.6
2
0.9
2.4
mV
mV
CC
30% Current Limit Foldback, Normal
V
– V
=12V
DSFB
DD
l
l
ISET = 0V
1.5
5.6
1.8
6
2.1
6.4
mV
mV
ISET = INTV
CC
l
l
l
l
l
l
Current Limit Threshold DAC INL
0
0
3
60
300
4
µV
µV
ΔV
– ΔV
Current Limit Channel Voltage Mismatch
V
V
+, V
+ = 48V
SENSE2
SNS1
SNS2
SENSE1
α
Ratio of Fast Current Limit to Nominal ΔV
2
0
3
ILIM(FAST)
SNS(TH)
+
I
I
+
–
SENSE1 Input Current
+ = 48V, V
SENSE1
≤ 20mV
150
7
µA
µA
µA
SENSE1
SENSE1
SNS1
–
SENSE1 Input Current,
HSSS Mode with CH2 Off
5
0
V
– = V
SENSE1
– = 48V
SENSE2
Parallel, LSSS Mode, HSSS Mode with
CH2 On
1
+
l
l
I
I
+
–
SENSE2 Input Current
V
V
+ = 48V
0
70
1
µA
µA
SENSE2
SENSE2
–
SENSE2 Input Current
+ = V
– = 48V
0
SENSE2
SENSE2
SENSE2
Gate Drive
l
l
l
ΔV
ΔV
External N-Channel Gate Drive (V
–V
)
V
= 6.5V to 80V, I = –5μA (Note 3)
GATE
10
6
12
8
14
10
V
V
GATE
GATE
SOURCE
DD
Gate Threshold for FET-Bad and Power Good
GATE1, GATE2 Pull-Up Current
GATE(TH)
GATE(UP)
GATE(DN)
I
I
Gate On, GATE = 0V
ΔV = 100mV, ΔVGATE = 6V
–35
–50
0.8
10
1.5
0.5
1
–70
µA
A
GATE1, GATE2 Fast Pull-Down Current
Gate Off Pull-Down Current to SOURCE
Gate Off Pull-Down Current to Ground
SNS
l
l
l
l
l
ΔVGATE = 6V
ΔVGATE = 6V
6
16
2.5
1
mA
mA
µs
µs
µs
0.5
t
t
t
ΔV
SNS
High to GATE Low Propagation Delay
ΔV
= 0mV to 100mV Step, C = 10nF
SNS
PHL(SENSE)
PHL(GATE)
UV, OV Turn Off Propagation Delay
GATE < 6V, Gate Open
Gate Open
0.3
3
Propagation Delay to Turn Off Low Stress
MOSFET in HSSS Mode
6
13
PHL(STRESS)
Comparator Inputs
l
l
l
l
l
l
l
V
UV, OV, FB Threshold Voltage
UV Hysteresis
Rising
2.5
280
25
2.56
360
46
2.62
440
85
V
mV
mV
mV
V
TH
ΔV
ΔV
ΔV
UV(HYST)
OV(HYST)
FB(HYST)
OV Hysteresis
FB Power Good Hysteresis
UV Reset Threshold Voltage
UV Reset Threshold Hysteresis
UV, OV, FB Input Current
60
80
100
1.05
150
1
V
Falling
0.95
50
1.00
100
0
TH
ΔV
mV
μA
UVR(HYST)
I
V = 2.56V
INPUT
Rev. 0
3
For more information www.analog.com
LTC4238
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 48V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
80
TYP
100
2
MAX
120
2.4
300
50
UNITS
mV
V
l
l
l
l
l
l
l
V
V
V
V
– SOURCE FET-Bad Threshold
FETBAD(TH)
STRESS(TH)
SOURCE
DL(UV)
DD
DD
– SOURCE Low Stress Threshold
1.6
10
I
t
t
t
SOURCE Input Current
V
= 48V
40
40
25
1
µA
ms
µs
SOURCE
Debounce Turn-On Propagation Delay
Turn-On Propagation Delay
Power Good Delay
UV Turn-On
OV Turn-On
30
50
DL(OV)
3
µs
DL(PG)
V
Input High Threshold
INTV
INTV
INTV
CC
V
CONFIG1/2
CC
CC
– 0.8
– 0.5
– 0.2
0.8
20
l
l
l
l
Input Low Threshold
0.2
0.5
V
µA
I
CONFIG Sink or Source Current
ISET Threshold Error
ISET Input Current
CONFIG = 0 to INTV
(Note 4)
CONFIG
CC
V
150
1
mV
µA
ISET(TH)
I
V = 0, 5V
0
ISET
Other Pin and Functions
l
l
l
l
l
l
l
l
l
V
PG, FLT# Output Low Voltage
PG, FLT# Leakage Current
I = 2mA
V = 80V
Gate On
Gate Off
0.3
0
0.4
1
V
µA
kΩ
µA
µA
mA
V
OL
OH
I
R
Resistance Between V and V Pins
DSFB
90
120
0
150
1
VDSFB
VDSFB
COMM
DD
I
I
V
Input Current
DSFB
COMM Source Current
COMM Sink Current
COMM Servo Voltage
V = 2.5V, Gate On and in Current Limit
V = 2.5V, Gate Off
–3.5
3
–5
–6.5
V
V
LSSS Start-Up
0.35
2.3
0.8
2.5
0.9
2.7
COMM(SERVO)
COMM(TH)
Gate Fully On, Not in Current Limit
In Current Limit
V
COMM High Threshold
INTV
– 2
INTV
INTV
CC
V
CC
CC
– 1.5
– 0.85
1.9
0.3
2.62
0.24
–22
1
l
l
l
l
l
l
l
l
l
l
l
l
COMM Low Threshold
Gates On, Not in LSSS
Gate On, in LSSS
Rising (Note 5)
0.9
1.4
V
V
COMM LSSS Threshold
0.1
0.2
V
V
TMR, TMRFET High Threshold
TMR, TMRFET Low Threshold
2.50
0.16
–16.5
2.56
0.2
V
TMR(H)
TMR(L)
Falling (Note 5)
V
I
TMR (ILIM), TMRFET Pull Up Current
TMR (SOA) Pull Up Current
V
TIMER
= 0V
–20
µA
µA
µA
µA
µA
mA
%
TMR(UP)
ΔV
SNS
ΔV
SNS
ΔV
SNS
= 0V and V – V
= 0V
VDSFB
DD
= 10mV and V – V
= 6V
–90
–2.5
3
–100
–1.4
5
–110
1
DD
VDSFB
VDSFB
= 20mV and V – V
= 50mV
DD
I
I
TMR(ILIM) Pull Down Current
TMRFET Pull Down Current
V = 2.56V
TMR
V
TMRFET
7
TMR(DN)
= 2.56V
0.2
0.04
0.8
0.5
0.8
0.12
2.4
TMRFET(DN)
D
D
Overcurrent Auto-Retry Duty Cycle
FETBAD Auto-Retry Duty Cycle
0.08
1.6
OC
%
FETBAD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Internal clamps limit the GATE pin to a minimum of 10V above or
0.3V below SOURCE. Driving this pin to voltages beyond the clamp may
damage the device.
Note 4: See Table 1 for more details.
Note 2: All currents into pins are positive. All voltages are referenced to
GND unless otherwise specified.
Rev. 0
4
For more information www.analog.com
LTC4238
TA = 25°C, VDD = 48V unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Current Limit Threshold vs
Temperature
Supply Current vs Voltage
INTVCC Load Regulation
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀꢀ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀ
ꢁꢁ
ꢀ
ꢁꢁ
ꢀ
ꢁꢁ
ꢂ ꢃ.ꢄꢀ
ꢂ ꢅꢆꢀ
ꢂ ꢇꢈꢀ
ꢀ
ꢀ ꢁꢂ ꢄ ꢅꢆꢃ
ꢀꢀ
ꢀ
ꢀ ꢁ.ꢂꢃ
ꢀꢀ
0
ꢀ0
ꢀ0
ꢀꢁꢂ
ꢀ0
ꢀ0
0
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ0
ꢀꢁ0
0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢀ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢁ
ꢀꢁꢂꢃ ꢄ0ꢂ
Current Limit Foldback Profiles
MOSFET Power Limit
MOSFET Gate Drive vs VDD
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ
ꢀ ꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ ꢃꢄꢅꢆR
ꢀꢁꢂꢀ ꢃꢄꢅꢆR
ꢀꢁꢂꢃꢄꢅꢂꢄ ꢆꢁꢇꢈR
ꢀꢁꢂꢃꢄꢅꢂꢄ ꢆꢁꢇꢈR
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢀ
ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢆꢄ ꢈ ꢉ0ꢊ
0
0
ꢀ
ꢀ
ꢀ
ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀꢁ
0
ꢀ0
ꢀ0
ꢀ
ꢀꢀ
ꢀ0
ꢀꢁꢂ
ꢀ0
ꢀ00
ꢀ
ꢀ ꢁ
ꢀꢁꢂ
ꢀ
ꢀ ꢁ
ꢀꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄ0ꢀ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢅ
MOSFET Gate Drive vs Gate
Leakage Current
MOSFET Gate Drive Pull-Up
Current vs Temperature
Gate Pull-Down Current vs Sense
Input Voltage
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ
ꢀ0
ꢀꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ0
ꢀ
ꢀ
∆V
ꢀ ꢁꢂ
ꢀꢁꢂꢃ
ꢀ ꢁ0ꢂꢃ
ꢀꢁꢀꢂꢃꢄꢅ
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉꢊꢋ
0.ꢀ
ꢀ
ꢀ
0.0ꢀ
0.00ꢀ
ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢆꢄ
ꢀ
0
0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁ0
0
ꢀ0
ꢀ00
ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀ
ꢀꢁꢂꢃꢄꢃꢅꢂꢆ ꢀꢇꢃꢆ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
∆V
ꢀꢁꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢃ
ꢀꢁꢂꢃ ꢄ0ꢅ
Rev. 0
5
For more information www.analog.com
LTC4238
TA = 25°C, VDD = 48V unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
SOA Timer Pull-Up Current
Current Limit Propagation Delay
vs Overdrive
Source Pin Current vs
Source Voltage
vs ΔVSENSE1
ꢀꢁ
ꢀ00
ꢀ0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ00
∆V
ꢀ ꢁ0ꢂꢃ
ꢀꢁꢂꢃ ꢄꢀ ꢅ ꢆ ꢀ ꢁ0ꢂ
∆V
DSFB
∆V
DSFB
∆V
DSFB
∆V
DSFB
= 12V
= 6V
ꢀꢁꢀꢂꢃꢄꢅ
ꢀꢀ
= 3V
= 0.5V
ꢀ00
ꢀ00
ꢀ00
0
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉꢊꢋ
ꢀ
0.ꢀ
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
∆V
– ∆V
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ
∆V
ꢀꢁꢂ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢀ
ꢀꢁꢀꢂꢃꢄꢅ
ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢃ ꢄꢅ0
ꢀꢁꢂꢃ ꢄ0ꢅꢅ
ꢀꢁꢂꢃ ꢄꢅꢁ
SOA Timer Pull-Up Current vs
PG and FLT# Output Low Voltage
vs Load Current
VDD – VDSFB
ꢀ00
ꢀ.ꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ0ꢃꢄ
ꢀ ꢁ0ꢂꢃ
ꢀ ꢁꢂꢃꢄ
ꢀ ꢁꢂꢃꢄꢅ
∆V
= 20mV
= 10mV
= 6mV
= 1.8mV
= 0.6mV
ꢀ
ꢀ
ꢀ
ꢀ
SENSE1
SENSE1
SENSE1
SENSE1
∆V
∆V
ꢀ.ꢁ
0.ꢀ
0.ꢀ
0.ꢀ
0
∆V
ꢀ00
ꢀ00
ꢀ00
0
∆V
SENSE1
0
ꢀ
ꢀ
ꢀ
ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀ
ꢀ ꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀ ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ ꢄꢅꢂ
ꢀꢁꢂꢃ ꢄꢅꢀ
Rev. 0
6
For more information www.analog.com
LTC4238
PIN FUNCTIONS
COMM: Communication Input/Output. Coordinates turn
on, turn off, and overcurrent faults between parts. Directly
connect the COMM pins of a group of parts to operate
them together. COMM may also be used as an ON status
or current limit status indicator. May be pulled to ground
with an open drain output to turn off the part. Leave open
if unused.
pin can be driven by an external supply that can only
source, but not sink current.
ISET: Current Limit Adjustment Input. The ISET voltage
is compared with seven threshold voltages generated by
a resistive voltage divider from INTV . The result sets
CC
the current limit voltage to be one of eight discrete values
from 6mV to 20mV in 2mV increments. When ISET is
connected to ground, the current limit threshold is set
CONFIG1, CONFIG2: Three State Configuration Inputs.
Decoded to select one of nine possible configurations.
These include single FET, High Stress Staged Start (HSSS),
Parallel or Low Stress Staged Start (LSSS) modes, cur-
rent limit profile and timer type for TMR pin (see Table 3).
to 6mV. When ISET is connected to INTV , current limit
CC
threshold is set to 20mV (see Table 1).
NC: No Connection. Not Internally connected.
OV: Overvoltage Comparator Input. Connect OV to an
FB: Power Good Comparator Input. Connect this pin to
an external resistive divider from SOURCE to GND. If the
FB voltage falls below 2.48V, the PG pin will pull low to
indicate the power is bad.
external resistive voltage divider from V to GND. An
DD
overvoltage fault is detected if this pin rises above the
2.56V threshold. When the OV pin voltage falls back below
the 2.51V falling threshold, the GATE pins will turn on
again immediately. Tie to GND if unused.
FLT#: Over Current or FET Bad Fault Output. An open drain
output that pulls low when the FET bad timer or current
limit/SOA timer expires. Tie FLT# and UV together through
a resistor to INTV to enable auto-retry (see Applications
Information for dCeCtails).
PG: Power Good Output. An open drain output that
pulls low when the FB pin drops below 2.48V indicat-
ing the power is bad. If the FB pin rises above 2.56V,
V
– V
is lower than 2V, and the GATEs are fully
DD
SOURCE
GATE1, GATE2: Gate Drives for External N-Channel
MOSFETs. Internal 50µA current sources charge the gates
of the MOSFETs. No compensation capacitors are required
on the GATE pins, but a resistor-capacitor (RC) network
from these pins to ground may be used to set the turn-on
output voltage slew rate. During turn-off there is a 10mA
pull-down current to SOURCE and a 1mA pull-down cur-
rent to GND. During a short-circuit or undervoltage lock-
enhanced, the open-drain pull-down releases the PG to
go high.
+
+
SENSE1 , SENSE2 : Positive Kelvin Current Sense Input.
Connect these pins to the V side of the current sense
resistor(s).
DD
–
–
SENSE1 , SENSE2 : Negative Kelvin Current Sense Input.
Connect this pin to the MOSFET side of the current sense
resistor(s). The current limit circuit controls the GATE
out (V or INTV ), a 0.8A pull-down between GATE1/
DD
CC
+
pin to limit the sense voltage between the SENSE and
GATE2 and SOURCE is activated. If only one MOSFET is
–
+
SENSE pins to the value selected by the ISET pin or less;
used, leave the GATE2 pin open and connect SENSE2
–
–
depending on the voltage at the V
DD
pin. Tie SENSE2 to
and SENSE2 to V .
DSFB
DD
V
when unused.
GND: Device Ground.
SOURCE: N-Channel MOSFET Source Connection.
Connect this pin to the source of the external N-channel
MOSFET switch. This pin provides a return for the gate
pull-down circuit and is used as an input to the 100mV
and 2V VDS comparators which are used for FET-BAD
faults and staged start timing, respectively.
INTVCC: Internal Supply Decoupling Output. Connect a
capacitor no smaller than 0.1µF from this pin to ground.
Up to 10mA may be drawn from this pin to power appli-
cation circuitry. This pin is current limited and will drop
to GND to reduce heating in an overcurrent condition.
Overloading this pin can disrupt internal operation. This
Rev. 0
7
For more information www.analog.com
LTC4238
PIN FUNCTIONS
TMR: Current Limit Timer or SOA Timer Output. The mode
of operation is set by the state of CONFIG pins. In current
limit timer mode, connect a capacitor between this pin
and ground to set a 128ms/µF duration for current limit
before the switch is turned off. If the UV pin is toggled
low while the MOSFET switch is off, the switch will turn
on again following a cool-down time of 150s/µF, result-
ing in a 0.08% duty cycle. In SOA timer mode, connect
a RC network between this pin and ground. The current
charging the RC network is proportional to the power
UV: Undervoltage Comparator Input. Connect this pin
to an external resistive divider from V to GND. If the
DD
UV pin falls below 2.2V, an undervoltage is detected and
the switch turns off. Pulling this pin below 1V resets the
overcurrent and FET-bad faults and allows the switch to
turn back on (see Applications Information for details). If
overcurrent auto-retry is desired, then tie this pin to the
FLT# pin. Tie to INTV if unused.
CC
V : Supply Voltage Input. This pin has an undervoltage
DD
lockout threshold of 6V. V is an input for the FET-bad
DD
dissipation in the powerpath, which is equal to ΔV
SENSE1
DD
comparator with a 100mV threshold. It is also an input
multiplied by the voltage difference between the V and
for the stress comparator with a 2V threshold.
SOURCE pins as measured at the V
pin.
DSFB
VDSFB: VDS Foldback Sense Input. This pin is used to
monitor the drain to source voltage of the external
MOSFETs, which is used by the SOA timer to monitor
MOSFET power, as well as set the foldback current limit.
TMRFET: FET-Bad Timer Input. Connect a capacitor
between this pin and ground to set a 128ms/µF duration
for a FET-bad condition before the switch is turned off
due to a FET-bad fault. If the UV pin is toggled low while
the MOSFET switch is off, the switch will turn on again
following a cool down time of 8s/µF, resulting in a 1.6%
duty cycle. Tie to GND if unused.
12V systems may connect V
directly to the SOURCE
DSFB
pin. 48V systems will require an additional RVDSFB resistor
of 10kΩ/V for input voltage over 12V to set the proper
gain of the SOA timer and foldback circuits.
Rev. 0
8
For more information www.analog.com
LTC4238
BLOCK DIAGRAM
GATE1
SOURCE
14V
GATE2
14V
–
+
+
+
8V
SENSE1
SENSE2
+
–
+
–
FAST CL
ACL
FAST CL
CHARGE
CHARGE
+
+
+
–
–
PUMP AND
PUMP AND
–
–
+
+
GATE DRIVER
GATE DRIVER
18mV TO
60mV
18mV TO
60mV
+
–
+
–
ACL
–
–
SENSE1
SENSE2
+
–
–
0.6mV TO
20mV
0.6mV TO
20mV
SOA MULT
+
–
+
–
ISET
CONFIG1
CONFIG2
ILIM
100%
30%
10%
10k
PG
110k
V
DSFB
FLT#
FB
PG
+
–
2.56V
LOGIC
V
DS2
+
–
COMM
SOURCE
SOURCE
+
+
–
COMM
2V
V
DS100
+
–
UVL02
+
–
4V
INTV
CC
–
100mV
UVL01
+
–
6.0V
5V
LDO
V
DO
V
DD
INTV
UVRESET
UV
CC
1.0V
+
–
20μA
TMR
MUX
+
–
2.56V
2.56V
+ 0.2V
–
5μA
UV
OV
OV
+
–
+
2.56V
–
INTV
CC
0.2V
+
–
OSC
20μA
TMRFET
+
0.5mA
2.56V
–
4238 BD
Rev. 0
9
For more information www.analog.com
LTC4238
OPERATION
The LTC4238 is designed to turn a board’s supply volt-
age on and off in a controlled manner, allowing the board
to be safely inserted or removed from a live backplane.
The device features four distinct operation modes: single
driver mode, parallel mode, high stress staged start mode
(HSSS), and low stress staged start mode (LSSS). Each of
these modes addresses specific application requirements
limit to 30% of nominal based on foldback. In the event of
a catastrophic output short, fast current limit comparators
immediately pull the GATE pins down with 0.8A when the
sensed current is three times the nominal current limit.
The LTC4238 provides two ways of limiting the time the
system is exposed to overstress conditions: a MOSFET
SOA timer or a current limit timer. The timer selection is
made via the CONFIG pins. If the MOSFET SOA timer is
chosen, the TMR pin is pulled up by a current that is pro-
portional to the power dissipation in the MOSFET driven
by GATE1. With an RC network representing the thermal
behavior of this MOSFET, the TMR voltage is proportional
to the MOSFET temperature rise. When the TMR voltage
reaches its threshold of 2.56V (representing TJ(MAX) of the
MOSFET), the overcurrent fault is triggered. Both GATEs
turn off to protect the MOSFETs based on their SOA. If
the current limit timer is chosen, the TMR pin is config-
ured to drive a single capacitor and ramps up with 20µA
when active current limiting is engaged. If the TMR pin
reaches its 2.56V threshold, the LTC4238 turns off both
GATEs and FLT# pin pulls low to indicate a fault. Then the
TMR pin ramps down using a 5μA current source until
the voltage drops below 0.2V. After that, the TMR pin will
ramp up and down 256 times with 20µA/5µA to allow the
pass transistor to cool down. If overcurrent auto-retry is
enabled by tying the FLT# pin to the UV pin, the LTC4238
will turn on again at the end of 256 timer cycles.
for Safe Operating Area (SOA), R
, and cost.
DS(ON)
The Block Diagram shows the monitoring blocks of the
LTC4238. First, two undervoltage lockout circuits, UVLO1
and UVLO2, validate the input supply and the internally
generated 5V supply, INTVCC. UVLO2 also generates the
power-up initialization to the logic. The undervoltage (UV),
and overvoltage (OV) comparators determine if the exter-
nal conditions are valid prior to turning on the GATEs.
In normal operation, the LTC4238 turns on the external
N-channel MOSFETs after a startup debounce delay, pass-
ing power to the load. A precise current limit value can
be set from 6mV to 20mV in 2mV steps using the ISET
+
voltage. During startup, the voltage between SENSE and
–
SENSE may be controlled to be no higher than 10% of
the current limit threshold or to the current limit threshold
with foldback. The startup current may be set to even
lower values with an external gate RC network.
An overcurrent fault at the output may result in exces-
sive MOSFET power dissipation during Active Current
Limiting (ACL). To limit this power in each channel, the
The output voltage is monitored using the FB pin and the
Power Good (PG) comparator to determine if the power is
ready for the load. The power good condition is signaled
by the PG pin using an open-drain pull-down transistor.
+
ACL amplifiers regulate the voltage between SENSE1 ,
–
+
–
SENSE1 and SENSE2 , SENSE2 pins by reducing the
GATE-to-SOURCE voltages in an active control loop when
the sense voltages exceed the current limit value. When
the MOSFET’s drain to source voltage is high, power dis-
sipation is further reduced by folding back the current
Rev. 0
10
For more information www.analog.com
LTC4238
APPLICATIONS INFORMATION
A typical LTC4238 application is a high availability system
in which a positive voltage supply is distributed to power
individual hot-swapped cards.
component selection is discussed in detail in the Design
Examples section.
Turn-On Sequence
In the following sections, the parallel mode is first cho-
sen to demonstrate common functions and basic hot-
swap applications. The unique features and applications
of each operation mode are then described separately. A
basic 48V, 40A LTC4238 application circuit is shown in
Figure 1. The power supply on a board is controlled by
using two pairs of N-channel pass transistors, M1A-B
Several conditions must be met before the external
MOSFETs turn on. First the external supply, VDD, must
exceed its 6.0V undervoltage lockout level. Next, the inter-
nally generated supply, INTV , must cross its 4V under-
CC
voltage threshold. This generates a power-on-reset pulse.
After a power-on-reset pulse, the UV and OV pins verify
that input power is within the acceptable range. The state
of the UV comparator must be stable for at least 40ms to
qualify for turn-on. The MOSFETs are then turned on by
charging up the GATE pins with 50μA current sources.
When the GATE voltage reaches the MOSFET threshold
voltage, the MOSFET begins to turn on and the SOURCE
voltage then follows the GATE voltages as it increases.
and M2A-B, placed in the power path. Resistors R and
S1
R
sense current through M1A-B and M2A-B. Resistors
S2
R1, R2 and R3 define undervoltage and overvoltage lev-
els. R prevent high frequency self-oscillations in the
G1-4
MOSFETs. R7 and R8 set the power good threshold, and
R6 scales current limit foldback to the intended operating
voltage.
The following sections cover turn-on, turn-off and various
faults that the LTC4238 detects and acts upon. External
While the MOSFETs are turning on, the power dissipa-
tion in current limit for each MOSFET is limited to the
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀꢁꢂ
R
ꢀꢁ
0.5mΩ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
R
R
ꢀꢁ
R
ꢀ0ꢁ
ꢀꢁ
10Ω 10Ω
ꢀꢁ
ꢂꢃꢄꢅꢆꢇ0ꢈ
ꢉꢊ
ꢀꢁ
0.5mΩ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀꢁꢂ
ꢀ
ꢁ
Rꢀ
ꢀꢁ0ꢂ
ꢀꢁ
R
R
ꢀꢁ
ꢀꢁ
10Ω
10Ω
Rꢀ
ꢀꢁ.ꢂꢃ
Rꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ ꢀꢁꢂRꢃꢄ
ꢀ
ꢀ
ꢁꢂꢃꢄ
ꢁꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢁ
0.ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
Rꢀ
ꢀ.0ꢁꢂ
ꢀꢁ
Rꢀ
ꢀ.ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢂ
ꢀꢁR
ꢀꢁꢂꢃꢄꢅꢆ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁRꢂꢃꢀ
ꢀꢁꢂ
ꢄꢄ
Rꢀ
ꢀ.ꢁꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃ ꢄ0ꢅ
R
R
ꢀꢁ
ꢀꢁ
ꢀ.ꢁꢂꢃꢄ ꢀꢅ ꢀꢀ.ꢁꢂꢃ ꢄꢅ
R
ꢀꢁꢂ
ꢀꢁ.ꢂꢃ
ꢀ
ꢀꢁ
0.ꢀꢁꢂ
ꢁꢂꢃ
ꢀꢁ
R
ꢀꢁ
ꢀꢁꢂꢃ
ꢀ
ꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢁꢂ
ꢀꢁ0ꢂꢃ
ꢁꢂ
ꢀ.ꢁꢂꢃ
R
ꢀꢁ0ꢂ
ꢀꢁꢂꢂꢁꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢁꢆꢇ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂRꢃ
Figure 1. 48V, 40A Hot Swap Controller with SOA Timer in Parallel Mode
Rev. 0
11
For more information www.analog.com
LTC4238
APPLICATIONS INFORMATION
foldback profile as shown in Figure 2. As the SOURCE
The MOSFETs are turned off with 10mA from GATE to
SOURCE and with 1mA currents pulling the GATE pins to
ground. With the MOSFET turned off, the SOURCE and FB
voltages drop as the load capacitance discharges. When
the FB voltage crosses below its threshold, PG pulls low
to indicate that the output power is no longer good. If
voltage rises, the V
and FB pins follow as set by R6,
DSFB
R7 and R8. Once the MOSFET drain to source voltage is
lower than its 2V threshold, both GATE pins are higher
than their 8V thresholds, and the FB pin has exceeded its
ꢀ
ꢚ ꢔꢘꢀ
ꢀ
ꢁꢕꢈꢉ
ꢊꢊ
the V pin falls below 5.5V or INTV drops below the
DD
CC
ꢀ
ꢊꢊ
ꢚ ꢄꢀ
undervoltage lockout falling threshold of 3.89V, a fast
shut down of the MOSFET is initiated. The GATE pins are
then pulled down with 0.8A currents to the SOURCE pin.
ꢀ
ꢊꢊ
ꢛ ꢀ
ꢌꢏꢈ
ꢋꢌꢍꢉR ꢁꢌꢌꢊ
Overcurrent Protection
The LTC4238 features two levels of protection from short-
circuit and overcurrent conditions. Load current is moni-
ꢀ
ꢃ ꢄꢀ
ꢁꢂ
ꢀ
ꢂꢉꢐꢂꢉ
ꢔ00ꢓ
+
–
tored by the SENSE and SENSE pins across the current
sense resistors. There are two distinct thresholds for the
current sense voltages, an active current limit threshold
and a fast current limit comparator threshold. The fast
current limit comparator threshold is always three times
the nominal current limit threshold. If the sense volt-
age of a channel reaches the current limit threshold, the
corresponding GATE is pulled down until the associated
active current limit loop is engaged. In the event of a cata-
strophic short-circuit or a sudden input step, where the
sense voltage of a channel reaches the fast current limit
comparator threshold, the corresponding GATE is imme-
diately pulled to SOURCE to limit peak current through
the MOSFET. When the sense voltage drops to the current
limit threshold, the active current limit loop is engaged.
ꢒ0ꢓ
ꢆ
ꢖ R
ꢂ
ꢅꢌꢕꢊ
ꢎꢏRRꢉꢐꢈ
ꢅꢆꢇꢆꢈꢉꢊ
ꢇꢌꢂꢑꢉꢈ ꢋꢌꢍꢉR
ꢑꢙ
ꢗꢘꢒꢄ ꢑ0ꢘ
ꢅꢆꢇꢆꢈꢉꢊ ꢋꢌꢍꢉR
Figure 2. Power-Up Waveforms
2.56V threshold, then the PG pin releases high to indicate
power is good and the load may be activated.
Current Limit Foldback
In normal operation, the minimum GATE-to-SOURCE
(ΔVGATE) drive voltage is 10V. The ΔVGATE voltage is
clamped below 14V to protect the gates of 20V N-channel
The LTC4238 features an adjustable current limit with
foldback that protects the MOSFETs from excessive power
dissipation. During active current limiting, the available
current is reduced as a function of the voltage across
MOSFETs. A curve of ΔV
drive versus V is shown
GATE
DD
in the typical performance characteristics.
MOSFET sensed by V and V
pins. The higher the
DD
DSFB
voltage across MOSFET, the lower the current limit thresh-
old will be. The lowest foldback value after start-up is 30%
of the nominal voltage.
Turn-Off Sequence
A normal turn-off sequence is initiated by card removal
when the backplane connector short pin opens, caus-
ing the UV or OV comparator output to change state.
Additionally, several fault conditions can turn off the
GATEs. These include an input overvoltage, input under-
voltage, overcurrent or FET-bad fault.
The nominal voltage of the LTC4238 current limit thresh-
old is set between 6mV and 20mV in 2mV steps via the
ISET pin (Table 1). This can be used to achieve a given
current limit with the limited selection of standard sense
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LTC4238
APPLICATIONS INFORMATION
resistor values available around 1mΩ. Threshold values
as low as 6mV reduce power dissipation in sense resis-
tors for high current applications.
Configurations using the 10% current limit for start-up
all use the SOA timer. This timer provides the flexibility
to allow a long current limit timeout at low power levels
during start-up, and a short current limit timeout during
a fault after start-up.
Two current limit foldback profiles are available to meet
different application needs, constant power and high
power. Refer to Table 3 for foldback configurations. The
constant power profile is shaped such that the power in
the MOSFET is constant while current limiting, regardless
Constant Current Start-Up Using GATE RC Networks
An optional series RC network from GATE to GND (RG
and C in Figure 5) provides an inrush current less than
of V . This simplifies the SOA design of the application
G
DS
the current limit by limiting the slew rate of the GATE
pin. The current limit timer will not run since the current
limit is not engaged during start-up. Thus, a small timer
capacitor may be used which allows the use of MOSFETs
with smaller SOA. Power good will signal when the FB
and makes the safe dissipation time a constant for various
voltage and current conditions. This works well with the
current limit timer on the TMR pin. However, the constant
power foldback profile starts to fold back at small V ,
DS
which could occur during an input step. For that reason
pin crosses its 2.56V threshold and the ΔV
voltages
the high power profile is also available. It doesn’t start to
GATE
cross their 8V thresholds. When both those conditions are
met and the impedance back to the supply through the
MOSFET is low, the output voltage is suitable for the load
to be turned on. PG voltage goes high to indicate power
fold back until the V is around 50% of the nominal input
DS
voltage. This prevents the current limit from folding back
after an input step and collapsing the output because it is
less than the load current. Since the power dissipation in
the MOSFET is not constant for the high power profile, the
worst-case power dissipation usually occurs when half of
the nominal supply voltage is across the MOSFET. Graphs
in the Typical Performance Characteristics show the cur-
rent limit and power versus voltage across the MOSFETs.
is good. R should be chosen such that I
• R is less
G
GATE
G
than the threshold voltage of the MOSFET to avoid an ini-
tial inrush current spike. But increasing R improves the
G
stability of the current limit servo loop (see Applications
Information on current limit stability). If the voltage of the
50µA I
current across R is higher than MOSFET's
GATE
G
Additionally, to ease start-up, the LTC4238 features a
configurable option for a start-up current at 10% of the
full current limit. The LTC4238 stays at 10% until the
conditions for power good are met, at which point it will
switch to the normal foldback profile and current limit. In
many cases this will eliminate the need for an RC network
on the GATEs of the MOSFETs to limit the inrush current.
threshold, a diode may be added in parallel with the large
RG to limit its voltage while charging up CG (see Figure 5).
For the staged-start architectures, an RC network may be
used on a trickle MOSFET or stress MOSFET. In the paral-
lel architecture, identical RC networks may be used on
both MOSFETs. Bypass MOSFETs don’t need the current
Table 1. ISET Pin Voltage* vs Current Limit Thresholds and Suggested 1% Resistor Values
Thresholds Compared with
I
SET
ΔV
(mV)
V
(V)
Lower (V)
Upper (V)
0.357
1.071
1.786
2.5
R
(kΩ)
R
(kΩ)
R
/(R
+ R
)
SNS(TH)
ISET
TOP
BOTTOM
BOTTOM
TOP
BOTTOM
6
0
Open
Short
14.7
29.4
44.2
59.0
73.2
88.7
Open
0.000
0.143
0.286
0.429
0.571
0.714
0.857
1.000
8
0.714
1.429
2.143
2.857
3.571
4.286
5
0.357
1.071
1.786
2.5
88.7
73.2
59.0
44.2
29.4
14.7
Short
10
12
14
16
18
20
3.214
3.929
4.643
3.214
3.929
4.643
*INTV = 5V is used for this table.
CC
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LTC4238
APPLICATIONS INFORMATION
limiting function of an RC network, but an RC network
may be used in low stress staged start to improve the
undershoot recovery time of the bypass MOSFET(s).
wiring inductance. To prevent this second type of oscilla-
tion, load the source with more than 10μF and bypass the
input supply with a series 10Ω, 100nF snubber to ground.
Current Limit Stability
Overcurrent Fault with a Basic Current Limit Timer
For many applications the LTC4238 current limit loop is
stable without additional components. However, there are
certain conditions where additional components may be
needed to improve stability. The dominant pole of the
current limit circuit is set by the capacitance at the gate of
the external MOSFET, and larger gate capacitance makes
the current limit loop more stable. Usually a total of 10nF
GATE-to-SOURCE capacitance is sufficient for stability
During active current limit, the power dissipation in the
MOSFET is large. If this power dissipation persists, the
MOSFET can reach temperatures that cause damage. A
basic current limit timer has a single capacitor connected
between TMR pin and GND and sets a maximum time for
the MOSFET to operate in a current limit mode. When
this timer expires, an over current fault is generated and
the MOSFET is turned off to protect it from overheating.
and is provided by inherent MOSFET C . The stability of
GS
Current limiting begins when the current sense voltage
between the SENSE+ and SENSE– pins reaches the current
limit threshold level (which depends on foldback and the
voltage of the ISET pin). The corresponding GATE pin is
then pulled down and regulated to limit the current sense
voltage to the current limit value. In parallel mode, if either
GATE is in current limit during start-up then the current
limit timer starts to run. The external timer capacitor at
the TMR pin will be charged with a 20µA pull-up current.
After start-up, only when both GATE pins are regulated in
current limit will the current limit timer start to run. If at
least one of the GATE pins stops limiting current before
the TMR pin reaches the 2.56V threshold, then the TMR
pin will discharge with 5μA. For HSSS, LSSS or Single
Driver Modes, if the current sense voltage between the
SENSE1+ and SENSE1– pins reaches the current limit
threshold level, then the current limit timer will start to
the loop is degraded by reducing the size of the resistor
on a gate RC network if one is used, which may neces-
sitate additional GATE-to-SOURCE capacitance. The worst
case for current limit stability occurs when the output is
shorted to ground after a normal start-up. Board level
short-circuit testing is highly recommended as board lay-
out can also affect transient performance.
Parasitic MOSFET Oscillations
Not all circuit oscillations can be ascribed to the cur-
rent limit loop. Some higher frequency oscillations can
arise from the MOSFETs themselves. (See Rarely Asked
Questions 151, High-Side Current Sensing). There are two
possible parasitic oscillation mechanisms. The first type
of oscillation occurs at high frequencies, typically above
1MHz. This high frequency oscillation is easily damped
with gate resistors RG1 – RG4 as shown in Figure 1. In
some applications, one may find that these resistors
help in short-circuit transient recovery as well. However,
too large of a resistor will slow down the turn-off time.
The recommended RG1 – RG4 range is between 5Ω and
500Ω. 10Ω provides stability without affecting turn-off
time. These resistors must be located next to the MOSFET
gate pin with no other connections between them.
run. For a given current limit time delay, t , use Equation
ACL
1 for setting the timing capacitor’s value:
C
TMR
= t
• 8[nF/ms]
(1)
ACL
When the TMR pin reaches its 2.56V threshold, the
LTC4238 turns off both GATEs and generates an over-
current fault. The MOSFETs are turned off with a 10mA
current from GATE to SOURCE and a 1mA current from
GATE to ground. Open-drain output FLT# also pulls low.
After the fault, the TMR pin begins discharging with a 5μA
pull-down current. When the TMR pin reaches its 200mV
low threshold, it will cycle up with 20μA and down with
5μA 256 times to give the MOSFETs time to cool.
A second type of parasitic oscillation occurs at frequen-
cies between 200kHz and 800kHz when the MOSFET
source is loaded with less than 10μF, and the drain is
fed with an inductive impedance such as contributed by
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An overcurrent fault may be cleared by pulling the UV pin
below its 1V UV reset threshold, which happens automati-
cally if FLT# is tied to the UV pin. Once the TMR completes
the cool down delay, the MOSFETs turn on if the fault has
been cleared. The cool down time is 150s/µF, resulting in
a 0.08% duty cycle.
The SOA timer requires an RC network representing
the MOSFET thermal model to be connected to TMR
(Figure 1). At least two resistors and two capacitors are
required for minimum accuracy of the thermal behavior.
More RC elements provide better accuracy. Thus, the cost
and board area are larger than the single-capacitor timer.
The SOA timer voltage represents the real time rise in the
junction temperature of the channel 1 MOSFET and its trip
threshold 2.56V represents the maximum allowable peak
temperature of the MOSFET. With the SOA timer, the selec-
tion of MOSFETs is much simpler: they just need to meet
the worst-case operation requirements. In fault conditions
such as output short, the SOA timer automatically pro-
tects the MOSFETs by turning them off once the maximum
allowable peak temperature is reached (TMR tripped).
With the single capacitor timer, the minimum capacitor
must first be selected to keep the MOSFETs on during
worst-case operating conditions, then the MOSFETs must
be selected to withstand the worst-case SOA conditions
during normal operating and fault conditions. The cost
of MOSFETs selected based on the single capacitor timer
for parallel mode or high stress staged start mode may
be substantially higher than that using the SOA timer. It
is recommended to use the SOA timer for high power
applications using parallel mode or high stress staged
start mode, especially for those with large input steps.
MOSFET manufacturers specify the safe limits on operat-
ing voltage, current and time as a set of curves referred
to as the Safe Operating Area (SOA). The proper timer
capacitance must be set to allow the worst-case operating
condition to stay within the SOA limits. The worst-case
operating condition could be completely charging a large
bypass capacitor at the output during start-up, or riding
through a large input step. With a basic current limit timer,
once a timer capacitance is set, the MOSFET must be
selected to withstand the worst-case SOA condition that
occurs during any possible normal operating condition
or fault condition.
The waveform in Figure 3 shows how the output turns off
following a short circuit.
ꢀꢁꢂRꢃꢄ
ꢅ0ꢆꢇꢈꢉꢆ
∆V
GATE
10V/DIV
ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢆꢄ
ꢀꢁRRꢂꢃꢄ
ꢅ0ꢆꢇꢈꢉꢊ
ꢀꢁꢁꢂ ꢃꢁꢄꢅ
During all modes of operation an internal multiplier drives
TMR with a current proportional to V
multiplied by
SENSE1
ꢀꢁR
ꢂꢃꢄꢅꢆꢃ
the voltage difference between V and SOURCE pin as
DD
ꢀꢁꢂꢃ ꢄ0ꢂ
ꢀꢁꢂꢃꢄꢅꢆ
measured the V
pin (Equation 2).
DSFB
Figure 3. GATE1, SOURCE, TMR Current vs Time
400µA • V
• V – V
(
)
DD
SENSE1
DSFB
(2)
I
=
TMR
20mV •12V
Overcurrent Fault with the SOA Timer
The LTC4238 features another mode for the TMR pin,
SOA Timer, which better protects the MOSFET(s) when
the power dissipated in the MOSFET varies widely. Instead
of a constant 20µA current, the TMR outputs a current pro-
portional to the power dissipation in the MOSFET driven
by GATE1 and the 5µA internal TMR pull-down current is
disabled. The assumption is made that in parallel mode
the MOSFETs of both channels see the similar stresses. In
other modes, the MOSFET at channel 1 sees more stress.
The mode of TMR pin is configured using the CONFIG pins.
For example, it produces 100µA when V
= 10mV
SENSE1
and V – V
= 6V. When the TMR voltage crosses its
DD
DSFB
2.56V threshold, the MOSFETs are shut off and an overcur-
rent fault is detected. When the multiplier output current is
low, the TMR voltage drops as the RC network discharges.
When it drops below 0.2V, Overcurrent Fault is cleared and
MOSFETs can turn on if FLT# is connected to UV.
In order for the SOA timer to work properly, 12V is
expected between VDD and VDSFB when VDD is at its nomi-
nal and SOURCE is at ground. There is 120k of resistance
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APPLICATIONS INFORMATION
internally from V to V
. For 12V systems, V
• I
= The TMR pull-up current correspond-
DD
DSFB
DSFB
TIMER(UP),MAX
ing to the maximum power dissipation.
should be simply connected to SOURCE. For input volt-
ages larger than 12V, add a resistance of 10kΩ/V between
P
= V
• I
MAX
DS,MAX D,MAX
the V
and SOURCE pins. For example, for 48V sys-
tems,DaSF3B60k resistor is required to be added between
the two pins.
• V
= TMR rising threshold (2.56V).
TMR(TH)
• ΔT
= The Maximum allowable temperature rise of
MAX
the MOSFET.
Note that the SOA timer is independent of the current limit
set via the ISET pin. The current limit may be adjusted with
the ISET pin without the need to modify the thermal RC
network. However, if the sense resistor value is changed,
a modified thermal RC network will be required. Using a
large current limit threshold, such as 20mV, achieves the
greatest accuracy and dynamic range from the SOA timer.
Refer to Typical Performance Characteristics for the SOA
For example, if V
= 400μA and ΔTDS,MA=X110°C (175°C T
k = 1.4 • 10 [V /°C]. A thermal RC network consisting of
three resistors and capacitors that represent the thermal
behavior of PSMN3R7-100BSE is shown in Figure 1.
= 58V, I
= 40A, I
JMAX
D,MAX TMR(UP),MAX
– 65°C T ),
MAX
A
5
2
FET-Bad Fault and Auto-Retry
TMR pull-up currents at different ΔV
and different
SENSE1
A damaged MOSFET may have leakage from gate to
drain or have degraded RDS(ON). Debris on the board
may also produce leakage or a short from the GATE pin
to the SOURCE pin, the MOSFET drain, or to ground. In
these conditions the LTC4238 may not be able to pull the
GATE pin high enough to fully enhance the MOSFET, or
the MOSFET may not reach the intended RDS(ON) when the
GATE pin is fully enhanced. This can put the MOSFET in a
condition where the power in the MOSFET is higher than
its continuous power handling capability, even though the
current is below the current limit.
V
– V
voltages.
DD
DSFB
The configuration of the thermal RC network for a particu-
lar MOSFET starts with the selection of a desired num-
ber of resistive and capacitive elements. Their values are
decided based on the thermal impedance plot provided
by the MOSFET manufacturer. Three resistors and three
capacitors are usually enough to fit the plot fairly well
from 10μs to 100ms (Figure 1), which covers the timing
range of typical operating and fault conditions. If better
fitting accuracy or wider fitting range is desired, more
elements may be used. After the thermal RC network is
configured, the thermal quantities are then converted to
electric quantities according to Equation 3.
The LTC4238 monitors the integrity of the MOSFETs in
two ways, and acts on both of them in the same manner.
First, the LTC4238 monitors the voltage between the V
DD
RE = k •Rθ
and SOURCE pins. A comparator detects a high DRAIN-
(3)
to-SOURCE voltage (V ) whenever V to SOURCE volt-
Cθ
CE =
k
DD
age is greater than 10D0SmV. Second, the LTC4238 moni-
tors the GATE voltage. The GATE voltage may not fully
enhance with a damaged MOSFET. A gate low condition is
detected if Gate-to-Source voltage is lower than 8V, and
that channel is not in active current limit.
where R and C are electric resistance and capacitance,
E
E
respectively and R and C are thermal resistance and
θ
θ
capacitance, respectively. The conversion constant k is
given by Equation 4.
When either a high DRAIN-to-SOURCE voltage or a gate
low condition is present for either or both MOSFETs while
they are commanded on, the FET-bad timer starts to run.
The logic determining FET-bad condition is in Figure 4.
The external timer capacitor on the TMRFET pin is charged
with a 20μA pull-up current. When the timer reaches the
2.56V rising threshold, a FET-bad fault condition is set, the
VTIMER(TH)
ΔTMAX
VDS,MAX •ID,MAX
ITIMER(UP),MAX
(4)
k =
•
• V
= The Maximum drain-to-source voltage that
DS,MAX
results in V
at 12V below V .
DSFB
DD
• I
= 20mV/R
.
D,MAX
SENSE1
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ꢏ
ꢒ ꢓꢋꢈꢇ ꢑꢆ ꢈꢔRꢇꢕꢔꢑꢖꢌ
ꢐꢑꢎꢎ
If the UV voltage subsequently rises back above the
threshold for 40ms, the GATEs can turn on again. If the
OV voltage subsequently falls back below the threshold,
the GATEs can turn on again immediately. The UV and OV
signals may be filtered by placing a capacitor, CF, between
the UV pin and GND.
ꢏ
ꢗ ꢕꢑꢅRꢐꢇ ꢒ ꢘ00ꢙꢏ
ꢐꢐ
Rꢅꢆ
ꢄꢇꢈꢉꢊꢋꢌ
ꢈꢍꢎꢇR
ꢓꢋꢈꢇꢘ ꢚ ꢃꢏ
ꢓꢋꢈꢇꢘ ꢆꢑꢈ ꢍꢆ ꢋꢐꢖ
ꢓꢋꢈꢇꢁ ꢚ ꢃꢏ
ꢓꢋꢈꢇꢁ ꢇꢆꢋꢊꢖꢇꢌ ꢑR ꢆꢑꢈ ꢍꢆ ꢋꢐꢖ
ꢛꢌꢇꢜꢇꢆꢌꢍꢆꢓ ꢑꢆ ꢈꢔꢇ ꢎꢑꢌꢇꢝ
ꢀꢁꢂꢃ ꢄ0ꢀ
Figure 4. LOGIC Diagram for FET-Bad Timer
Dual Gate Operation Modes
part turns off, and the GATE pins are pulled low with 10mA
to SOURCE and 1mA to ground. If the DRAIN-to-SOURCE
voltage falls below 100mV and the GATE low conditions
are cleared before the TMRFET reaches 2.56V threshold,
the TMRFET pin will discharge with 500μA. For a given
FET-bad time delay, tFET-BAD, use Equation 5 for setting
the timing capacitor’s value:
The LTC4238 features dual gate drivers that are config-
ured by the CONFIG1 and CONFIG2 pins into four dis-
tinct operation modes: single driver, parallel, high stress
staged start (HSSS), and low stress staged start (LSSS).
As shown in Table 2, each mode features specific SOA or
RDS(ON) benefits, GATE(s) on/off behavior, power good
signaling and fault detection logic.
C
= t
• 8[nF/ms]
FET-BAD
(5)
TMRFET
All modes except LSSS support starting up with a resis-
tive load such as a heating element or incandescent lamp.
The modes of the dual gate drivers are selected together
with the foldback profile and TMR behavior by the status
of CONFIG1 and CONFIG2 pins as shown in Table 3.
Note that during start-up, the VDS high condition is present
because the voltage from drain-to-source is greater than
100mV. To avoid undesired turn-off, the FET-bad timer
duration must be long enough for the largest allowable
load to start up. FET-bad faults are disabled by grounding
the TMRFET pin.
Parallel
High current applications often demand several power
The LTC4238 treats a FET-bad fault similar to an overcur-
rent fault. If a FET-bad fault is detected, the MOSFETs are
turned off and the TMRFET pin begins discharging with a
500μA pull-down current. When the TMRFET pin reaches
its 0.2V threshold, it will cycle up with 20μA and down
with 500μA 64 times to allow the MOSFET time to cool
down. When automatically retrying with FLT# pin tied to
UV pin, the resulting FET-bad duty cycle is 1.6%. After
the final time the TMRFET pin falls below its 0.2V low
threshold the MOSFETs are allowed to turn on again.
MOSFETs in parallel to reach a target R
under 1mΩ
that is unavailable in a single MOSFET.DISn(OaNd)dition, divid-
ing the load current amongst multiple devices alleviates
the PCB current crowding problem with the use of a single
MOSFET.
Parallel MOSFETs share current well when their GATE-
to-SOURCE voltages are fully enhanced. However, when
the MOSFETs are limiting current, the mismatch between
gate thresholds will cause the MOSFET with the lowest
threshold to carry more current than the others. Since
threshold voltage has a negative temperature coefficient,
as this MOSFET heats it may carry even more current.
Eventually all the load current may be carried by a single
MOSFET. For this reason, when a group of MOSFETs are
operated in parallel only the SOA (Safe Operating Area)
of a single MOSFET is guaranteed.
Undervoltage and Overvoltage Faults
The UV pin can be used to monitor a supply undervoltage
condition using an external resistive voltage divider. An
undervoltage fault occurs when the UV voltage falls below
its 2.2V falling threshold. An overvoltage fault occurs
when the OV voltage goes above its rising threshold of
2.56V. When either an undervoltage or overvoltage fault
occurs, the LTC4238 shuts off the GATE pins with a 10mA
current to SOURCE and a 1mA current to ground.
The LTC4238 resolves this problem by offering two gate
drivers, each with an independent current limit circuit and
associated current sense pins. For configuration 4, 7, 8,
and 9 as shown in Table 3, these two gate drivers operate
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APPLICATIONS INFORMATION
Table 2. LTC4238 Dual-Gate Operation Modes
MODE
SINGLE DRIVER
PARALLEL
HIGH STRESS STAGED START LOW STRESS STAGED START
FEATURE
Simple
SOA Doubled, R
Halved
GATE1 Drives High SOA
MOSFET.
GATE1 Drives Low R
Small SOA MOSFET.
,
DS(ON)
DS(ON)
GATE2 Drives Low R
MOSFET
GATE2 Drives Small SOA
MOSFET
DS(ON)
TURN-ON
SEQUENCE
GATE1 and GATE2 Turn on at
the Same Time
GATE1 Turns on First.
GATE 2 Turns on First.
GATE2 Turns on after GATE1
Turns High and
GATE1 Turns on if V > 2.56V
FB
Once GATE2 Turns High
V
– V
< 2V and
DD
SOURCE
Channel 1 Is Not in ACL
POWER SET
GOOD
V
DD
– SOURCE < 2V, and V > 2.56V, and ΔV
> 10V, and (ΔV
> 10V or Disabled)
GATE2
FB
GATE1
RESET
FB Drops Below 2.48V
FB Drops Below 2.48V or V
Drops Below 0.2V
COMM
LATCH
GATE1 TURN-OFF
V
< 1.4V
V
V
< 0.2V or V < 2.56V
COMM
COMM
COMM
FB
GATE2 TURN-OFF ΔV
< 8V or
V
< 1.4V
ΔV < 8V or
GATE1
< 0.2V
GATE1
DD
COMM
V
– SOURCE > 2V or
V
– SOURCE > 2V or
DD
Channel 1 is in ACL
Channel is 1 in ACL
CURRENT LIMIT Runs if V
> 3.5V or
Runs if V
> 3.5V or
Runs if V > 3.5V or
Runs if V > 3.5V or
COMM
Channel 1 is in ACL
COMM
COMM
COMM
TIMER
Channel 1 is in ACL
During Start-Up:
Channel 1 is in ACL
Either Channel Is in ACL
After Start-Up:
Both Channels are in ACL
FET BAD TIMER Runs if V
> 1.4V and
Runs if V
> 1.4V and
Runs if V
> 1.4V and
Runs if V
> 0.2V and
COMM
COMM
COMM
COMM
[(V – SOURCE > 100mV) or
[(V – SOURCE > 100mV) or
[(V – SOURCE > 100mV) or
[(V – SOURCE > 100mV) or
DD
DD
DD
DD
GATE1
GATE2
(ΔV
(ΔV
< 8V and Not in ACL) or (ΔV
< 8V and Enabled)]
< 8V and Not in ACL) or (ΔV
< 8V and Not in ACL)] (ΔV
< 8V and Not in ACL) or (ΔV
< 8V and Enabled)]
< 8V and Not in ACL) or
< 8V and Not in ACL)]
GATE1
GATE2
GATE1
GATE2
GATE1
GATE2
(ΔV
(ΔV
Table 3. LTC4238 Configurations
10% FOLDBACK DURING
START-UP
CONFIGURATION
CONFIG2
Ground
Ground
Ground
Open
CONFIG1
Ground
Open
DUAL-GATE MODE FOLDBACK PROFILE
TMR PIN TYPE
1
2
3
4
5
6
7
8
9
HSSS/Single
HSSS/Single
HSSS/Single
Parallel
High Power
Constant Power
High Power
Current Limit Timer
SOA Timer
No
Yes
No
No
No
No
Yes
No
No
INTV
SOA Timer
CC
Ground
Open
High Power
SOA Timer
Open
LSSS
Constant Power
Constant Power
Constant Power
Constant Power
High Power
SOA Timer
Open
INTV
LSSS
Current Limit Timer
SOA Timer
CC
INTV
INTV
INTV
Ground
Open
Parallel
CC
CC
CC
Parallel
SOA Timer
INTV
Parallel
Current Limit Timer
CC
in parallel mode, in which GATE1 and GATE2 are turned on
or off simultaneously. In this mode, the LTC4238 allows
a group of parallel MOSFETs to be divided into two chan-
nels. During current limiting in an overcurrent event such
as output short or input step, the independent gate control
of the two channels divides the current evenly between
them, resulting in twice the SOA performance of a Hot
Swap controller with a single current limit circuit. This
allows the use of smaller, less expensive MOSFETs, can
start up a load twice as big, or increase SOA margins. In
addition, multiple LTC4238s can be connected in parallel
using the COMM pin to coordinate turn on, turn off, and
fault behavior to further improve SOA.
Rev. 0
18
For more information www.analog.com
LTC4238
APPLICATIONS INFORMATION
Figure 1 shows an application example providing 48V,
40A operating in the parallel mode. Two MOSFETs in
each channel are used so that the power dissipation in
each MOSFET is less than 1W when fully enhanced. After
start-up, when the voltage across the MOSFETs drain and
source is lower than 2V, the gate-to-source voltages for
both MOSFETs are higher than 8V, and the FB voltage is
higher than 2.56V, power is considered good. Open-drain
output PG is then released to go high. After that, if the FB
falls below 2.48V, PG will be reset to low.
than SOURCE pin, the open drain output PG pin is latched
high given FB pin is higher than 2.56V. Most of the load
current is delivered by M2A and M2B, which usually have
much lower R
than M1.
DS(ON)
In this mode the current sense resistor is connected
between SENSE1+ and SENSE1–, while SENSE2+ and
SENSE2– are connected to VDD to disable the current limit
circuit of GATE2. During overcurrent events such as an
output short or an input step, the LTC4238 immediately
switches off GATE2 to protect M2A and M2B from over-
stress, leaving the current limit of GATE1 to regulate the
load current through M1. In this condition the TMR pull-
up current is turned on. When the TMR voltage reaches
2.56V, GATE1 is turned off and an overcurrent fault is
logged.
If the current limit timer is selected with parallel mode
(configuration 9), it will run if either channel is in current
limit during start-up. Once start-up is finished and PG has
been released, the current limit timer will run only if both
channels are in current limit. If the SOA timer is selected,
the RC network should represent the thermal behavior of
a single MOSFET, since the TMR pull-up current is only
related to the power dissipation in the channel 1 MOSFET.
When TMR reaches 2.56V (representing the maximum
allowable temperature rise in the MOSFET), both GATE1
and GATE2 are turned off and the overcurrent fault status
will pull the FLT# pin low.
The high stress staged start mode decouples the SOA
requirement from the R
requirement. The MOSFET
DS(ON)
driven by GATE1 (M1) is selected so that its SOA is large
enough to withstand stresses in all operating conditions.
The R
of M1 is not a major concern but needs to
DS(ON)
keep the MOSFET drain to source voltage lower than 2V
when GATE2 is off, otherwise GATE2 will not be turned
on. The MOSFETs driven by GATE2 (M2A and M2B) are
High Stress Stage Start
2
selected so that their R
minimizes the I R power
DS(ON)
The two GATE drivers of the LTC4238 can also be con-
figured to operate in high stress staged start mode by
grounding the CONFIG2 pin (Table 3). In this mode
GATE1 drives a high SOA MOSFET (M1) for start-up and
to withstand overstresses; GATE2 drives less expensive
dissipation, typically below or close to 1W. The SOA of
M2A and M2B does not need to be large because GATE2 is
switched off when either GATE1 is in current limit, GATE1
is low (GATE1 is less than 8V above SOURCE pin), or the
MOSFET drain to source is higher than 2V. In this way
the selection of MOSFET(s) for each channel is easier
and the overall cost of MOSFETs may be lower than the
parallel mode.
bypass MOSFETs (M2A and M2B) with low R
and
DS(ON)
relaxed SOA requirements to carry the load, as shown in
Figure 5a. The high stress staged start mode works well
for systems where large input steps or supply surges may
occur. M1 must be selected with large enough SOA to
withstand these conditions, in which M1 not only carries
the full load current, but also needs to deliver the current
to charge up the load capacitor.
In the high stress staged start mode, the FET-bad timer
starts to run when either GATE1 is low but channel 1
is not in active current limit, GATE2 is enabled but low,
or the MOSFET drain to source voltage is higher than
100mV. When TMRFET rises above 2.56V, a FET-bad fault
is triggered.
At power up, GATE1 is turned on first to charge the load
and GATE2 is held off. As illustrated in Figure 5b, GATE2
is turned on when GATE1 is fully enhanced (GATE1 is
more than 8V higher than SOURCE pin), the MOSFET
drain to source voltage is lower than 2V and channel 1 is
not in current limit. After GATE2 is more than 8V higher
Low Stress Stage Start
The low stress staged start mode is well suited for
applications with a tightly regulated supply voltage. In
Rev. 0
19
For more information www.analog.com
LTC4238
APPLICATIONS INFORMATION
such a system without significant input voltage steps,
the worst-case operating condition for the MOSFET SOA
occurs when charging the load capacitance during start-
up. By limiting the start-up inrush current to a very low
level, the SOA demand for the start-up MOSFET is greatly
alleviated. Additionally, the bypass path which turns on
after start-up only needs inexpensive, switching regulator
class MOSFETs. Therefore, this architecture minimizes
ꢀꢁꢂ0ꢃꢄꢅꢃ0ꢅꢄ
ꢀꢁꢂ
ꢀꢁꢂ0ꢃꢄꢅꢃ0ꢅꢄ
R
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
0.2mΩ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢁ
ꢀ0ꢁ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅ0ꢆ
ꢇꢈ
ꢂꢃꢄꢅꢆꢃꢇꢈꢉꢊ
R
R
ꢀꢁ
10Ω
ꢀꢁ
Rꢀ
ꢀꢁ.ꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢁꢂꢃꢄ
ꢀꢀꢁꢂ
ꢀ
ꢁ
R
R
ꢀꢁ
10Ω
Rꢀ
ꢀꢁ0ꢂ
ꢀꢁ
ꢀꢁ
10Ω
ꢀ
ꢁ
0.ꢀꢁꢂ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂRꢃꢄ
ꢁꢂꢃꢄ
ꢁꢁ
Rꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
Rꢀ
ꢀ.0ꢁꢂ
ꢀꢁ
Rꢀ
ꢀ.ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢂ
Rꢀ
ꢀ.ꢁꢁꢂ
ꢀꢁ
ꢀꢁR
ꢀꢁꢂꢃꢄꢅꢆ ꢀꢁꢂꢃ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ
ꢀꢁRꢂꢃꢀ
ꢀꢁꢂ
ꢄꢄ
ꢀꢁꢂꢃ ꢄ0ꢅꢆ
R
R
ꢀꢁ
ꢀꢁ
R
ꢀ.ꢁꢂꢃꢄ ꢅꢆ
ꢀ0ꢁꢂ ꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
0.ꢀꢁꢂ
ꢀꢁ
ꢁꢂꢃ
R
ꢀꢁ
0.ꢀꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢁꢂ
ꢀꢁ0ꢂꢃ
ꢁꢂ
ꢀ.ꢁꢂꢃ
ꢁꢂ
R
ꢀꢁꢂꢂꢁꢃ
ꢀ.ꢀꢁꢂ
ꢀꢁ
ꢀꢀꢁꢂ
ꢀꢀ.ꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢁꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂRꢃ
(a) 48V,60A Application Circuit with TA = 65°C
∆V
GATE1
∆V
GATE1
10V/DIV
10V/DIV
∆V
GATE2
∆V
GATE2
10V/DIV
10V/DIV
ꢀꢁR
ꢂꢃꢄꢅꢆꢃ
ꢀꢁ
ꢂꢃꢄꢅꢆꢃ
ꢀ
ꢀ
ꢁꢂꢃRꢂꢄꢅ
ꢆ0ꢃꢇꢈꢀꢉ
ꢀꢁRꢂꢃꢄ
ꢅꢆꢇꢈꢀꢉ
ꢀꢁꢂꢃ ꢄ0ꢅꢆ
ꢀꢁꢂꢃ ꢄ0ꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
(b) Normal Start-Up Waveform
(c) Start-Up into Short-Circuit
Figure 5. High Stress Staged Start Application
Rev. 0
20
For more information www.analog.com
LTC4238
APPLICATIONS INFORMATION
the cost of MOSFETs to achieve a given load current and
Figure 6a shows an application circuit for a 48V, 63A
system operating in the low stress staged start mode.
This mode is enabled by using configuration 5 or 6 in
Table 3. In this mode GATE2 drives a compact, inexpen-
sive MOSFET (M2) with small SOA as a trickle charging
R . However, LSSS mode has limited capability to
DS(ON)
ride through an input step or a sustained load surge in
current limit. Due to the low start-up current it also cannot
start up a large resistive load such as a heating element
or incandescent lamp.
device for start-up. GATE1 drives parallel, low RDS(ON)
,
R
ꢀꢁ
4mΩ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ0ꢃꢄꢅꢃ0ꢅꢄ
ꢁꢂꢃ
ꢀꢁꢂ
R
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ0ꢆ
ꢇꢈ
0.2mΩ
ꢀꢁꢂ0ꢃꢄꢅꢃ0ꢅꢄ
ꢀꢁꢂ
ꢀ
ꢁ
R
R
ꢀꢁ
R
ꢀꢁ
ꢀꢁ
Rꢀ
10Ω
10Ω
10Ω
ꢀꢁ.ꢂꢃ
ꢀꢁ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢁꢁ
ꢀꢁꢂRꢃꢄ
ꢀ
ꢀꢁ
ꢁ
Rꢀ
ꢀꢁ0ꢂ
ꢀꢁ
Rꢀ
0.ꢀꢁꢂ
ꢀꢁꢂ
Rꢀ
ꢀ.0ꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀ
ꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁ
ꢀꢁ
Rꢀ
ꢀ.ꢁꢁꢂ
ꢀꢁ
ꢀꢁꢂꢂ
Rꢀ
ꢀ.ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢀꢁꢂꢃ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁRꢂꢃꢀ
ꢀꢁꢂ
ꢀꢁR
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ ꢄ0ꢅꢆ
R
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁ
0.ꢀꢁꢂ
ꢀꢁ
ꢁꢂꢃ
ꢁꢂR
ꢀ.ꢁꢂꢃ
ꢀꢁ0ꢂꢃ
R
ꢀꢁꢂꢂꢁꢃꢄ
ꢀꢀ.ꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢁꢆꢇ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂRꢃ
(a) 48V, 63A Application Circuit
∆V
GATE2
∆V
GATE1
10V/DIV
10V/DIV
∆V
ꢀꢁꢂꢃꢄꢅꢆ ꢂꢇꢈꢁR ꢁꢉꢊꢇRꢁꢋ
GATE1
∆V
GATE2
10V/DIV
10V/DIV
ꢀꢁRꢂꢃꢀ
ꢄꢅꢆꢇꢈꢅ
ꢀ
ꢁꢂꢃ
ꢄ0ꢀꢅꢆꢇꢀ
ꢀꢁRRꢂꢃꢄ
ꢅ0ꢆꢇꢈꢉꢊ
ꢀꢁꢂꢂ
ꢃꢄꢅꢆꢇꢄ
ꢀꢁꢂꢃ ꢄ0ꢅꢆ
ꢀꢁꢂꢃ ꢄ0ꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
(b) Normal Start-Up Waveform
(c) Start-Up into Short-Circuit
Figure 6. Low Stress Staged Start Application
Rev. 0
21
For more information www.analog.com
LTC4238
APPLICATIONS INFORMATION
low SOA MOSFETs (M1A and M1B) with a high current
limit to deliver the full load current. The turn-on sequence
is the opposite of that in the high stress staged start mode
as illustrated in Figure 5b: M2 turns on first and deliv-
ers a low inrush current due to the large sense resistor
RS2. Once the load is fully charged (FB pin is higher than
2.56V) and the start-up MOSFET is fully enhanced (V
> 8V) and not in active current limit, GATE1 turnGsAoTEn2.
When the MOSFETs of both channels are fully enhanced,
the drain-to-source voltage is lower than 2V and FB pin
voltage is higher than 2.56V, power-good is asserted.
must be programmed long enough to avoid turning off
M2 too early.
If the current limit timer is chosen, the TMR capacitor
will be charged only when channel 1 is in current limit.
A single, small TMR capacitor as shown in Figure 6a can
be used to configure a brief delay, which should be within
the worst SOA of M1A/M1B and M2. If the SOA timer is
chosen, an RC network that represents the electric model
for the thermal behavior of M1A or M1B should be con-
nected to TMR. Note that during startup when M1A and
M1B are turned off, the TMR pull-up current still relates
to the power dissipation in M1A and M1B, which is zero.
M2 should be selected so that its SOA allows it to be in
current limit longer than M1A or M1B. In this way M2 is
automatically protected when M1A and M1B turn off in
an overcurrent condition.
The current sense pins for both current limit circuits on
GATE1 and GATE2 must be connected to their corre-
sponding sense resistors. If an overcurrent event occurs,
both GATE1 and GATE2 stay in current limit to share the
stress. GATE1 turns off if the FB pin drops below 2.48V
or GATE2 turns off due to a fault, which is different from
the high stress staged start mode where GATE2 turns off
if GATE1 is in current limit.
Single Driver Mode
Figure 7 shows a single MOSFET application. Configured
in high stress staged start mode, this implementation
behaves as other single Hot Swap controllers like the
LT4256 when the bypass MOSFETs are not stuffed and
the GATE2 pin is open.
The condition to start the FET-bad fault timer in this mode
is the same as in the parallel mode (see Table 2). Since
the FET-bad fault timer is running during the trickle start-
up while the load is slowly charged, the timer duration
R
ꢀ
0.5mΩ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀ
ꢀꢁꢂ
ꢀ
ꢁꢂꢃ
ꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ
ꢁ
ꢁ
R
ꢀ
Rꢀ
ꢀꢁ0ꢂ
ꢀꢁ
Rꢀ
ꢀꢁ.ꢂꢃ
ꢀꢁ
10Ω
ꢄ
ꢄ
ꢄ
ꢄ
Rꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂRꢃꢄ
ꢁꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢁꢂꢃꢄ
ꢀꢁ
ꢀ
ꢁ
ꢀꢁ
Rꢀ
ꢀ.0ꢁꢂ
ꢀꢁ
Rꢀ
ꢀ.ꢁꢂꢃ
ꢀꢁ
0.ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢂ
Rꢀ
ꢀ.ꢁꢁꢂ
ꢀꢁ
ꢀꢁR
ꢀꢁꢂꢃꢄꢅꢆ ꢀꢁꢂꢃꢄꢅꢆ ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁRꢂꢃꢀ
ꢀꢁꢂ
ꢄꢄ
ꢀꢁꢂꢃ ꢄ0ꢅ
R
ꢃꢃ.ꢄꢅ
ꢆꢇ
ꢀꢁꢂ
ꢀ
ꢀ
ꢁ
ꢀꢁꢂꢃ
ꢀꢁ
0.ꢀꢁꢂ
ꢁꢂꢃ
0.ꢀꢁꢂꢃ
R
ꢄꢅ.ꢆꢇ
ꢄꢈ
ꢀꢁꢂꢂꢁꢃ
ꢀꢁꢂꢃꢄꢅꢁꢆꢇ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂRꢃ
Figure 7. 48V, 16A A Single MOSFET Implementation with HSSS Mode
Rev. 0
22
For more information www.analog.com
LTC4238
APPLICATIONS INFORMATION
On-Off Control
ꢀꢁꢂ
The LTC4238 can be configured to turn on automatically
on insertion by connecting the UV/OV resistive voltage
divider through a short pin on the connector. For an active
high turn-on, the top of the divider is connected to the
supply through the short pin as in Figure 8a; for active low
turn-on, the bottom of the divider is connected to ground
through the short pin as in Figure 8b. Both the UV and
OV pins are rated to 100V so no additional protection is
needed when pulled up to the supply.
Rꢀ
ꢀꢁ
Rꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂ
ꢃꢂ
ꢀꢁ
Rꢀ
(a) Short Pin to Supply
An open-drain pull-down, or logic level NMOS may be
connected to the UV pin to allow a logic signal to turn the
LTC4238 on and off as shown in Figure 8c.
ꢀꢁꢂ
In addition the COMM pin may be used to turn off the
LTC4238 by pulling it to GND with an open-drain pull-
down. When COMM is released, the LTC4238 will turn on
immediately provided no faults are present.
Rꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
Rꢀ
ꢀꢁꢂ
ꢃ00ꢂ
ꢀꢁ
Parallel Controllers Using the COMM Pin
Rꢀ
The LTC4238 has a COMM pin that communicates its sta-
tus so that multiple LTC4238s can operate in parallel. Tie
the COMM pins of a group of parts together to allow them
to operate in tandem. A small capacitor may be connected
to COMM node to improve noise immunity if necessary.
(b) Short Pin to Ground
ꢀꢁꢂ
The COMM pin has 4 states.
Rꢀ
• Zero Volts mean none of the parts can turn on. Any
part with a fault present will pull the pin to 0V to turn
off the entire bank.
ꢀꢁ
Rꢀ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁꢁ
• 0.8V indicates only the start-up channel of the parts
configured with LSSS mode are allowed to turn on.
Those parts will regulate the COMM at 0.8V voltage
with a 5µA pull-up current until the start-up MOSFET
is fully enhanced.
Rꢀ
ꢀꢁꢂꢃ ꢄ0ꢃ
(c) On/Off Control by Logic Signal
• 2.5V at the COMM indicates that all the parts can turn
on. The parts that have no faults present regulate at
2.5V with a 5µA pull-up current. The parts that are
on and in current limit will disable the 2.5V regulator,
allowing the COMM voltage to rise.
Figure 8. On/Off Control with UV/OV Pins
When configured as a current limit timer, only one
LTC4238 needs to have capacitor connected to the TMR
pin. When the COMM voltage is within 1.5V of INTV ,
CC
the current limit TMR integrates. The remaining LTC4238s
• 5V means all the parts are in current limit.
may have their TMR pins grounded to disable overcurrent
Rev. 0
23
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LTC4238
APPLICATIONS INFORMATION
faults. When using thermal networks, each individual part
has its own thermal network and may generate a thermal
fault regardless of the state of the COMM pin.
current limit comparator engages at 3× the current limit
threshold and has a propagation delay of 500ns. If the
supply inductance is less than 2000nH in a 48V applica-
tion, it is unlikely that the VDD UVLO threshold will be
breached and the fast di/dt rate allows the current to rise
to the 3× level long before the UV pin responds.
When multiple LTC4238s work together by having COMM
pins connected, care must be taken to make sure all the
LTC4238s see the same solid ground potential. Ground
bounce could corrupt COMM function or possibly damage
the LTC4238 if the absolute maximum rating is violated.
Putting a current limiting resistor in series with the COMM
pins, or putting a Schottky or capacitor between COMM
and ground next to LTC4238 may mitigate ground noise.
Once the fast current limit comparator begins to arrest
the short circuit current, the input voltage rapidly recovers
and even overshoots its DC value. The LTC4238 is safe
from damage up to 100V. In card-resident applications
clamp the V pin with a surge suppressor Z1, as shown
in Figure 1.DDTo minimize spikes in backplane resident
applications, bypass the LTC4238 input supply with an
The COMM pin may also be used as a current limit or
processor hot (PROCHOTB) indicator for a single or mul-
tiple LTC4238s, if the group is in current limit, the pin is
electrolytic capacitor between V and GND.
DD
pulled to INTV . A PNP and resistor circuit can convert
In the worst case, Z1 has to absorb the high current that
triggers the fast current limit comparator. Several surge
suppressors may be required to clamp this current for
high power applications. In applications where a solid
ground is not available to connect the surge suppressor,
it may be connected from input to output, allowing the
output capacitance to absorb spikes. In 12V applications,
many 20V to 30V MOSFETs enter avalanche breakdown
before 50V. In such a case, the MOSFET can also act as
a surge suppressor and protect the Hot Swap controller
from inductive input voltage surges.
CC
this signal to a logic signal, as shown in Figure 9.
R
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁ
ꢀꢁꢂꢂ
ꢀRꢁꢂꢃꢁꢄꢅ
ꢀ0ꢁ
ꢀꢁꢂꢃ ꢄ0ꢅ
Design Examples
The design flow starts with specifying the maximum load
power and the operating voltage limits. If redundant sup-
plies are used, the system usually has wide supply range
and can experience large input steps when switching. An
operation mode is then selected based on the approximate
guideline in Table 4.
Figure 9. Current Limit/PROCHOT Indication Using the COMM Pin
Supply Transients
In card-resident applications, output short circuits work-
ing against the inductive nature of the supply can easily
cause the input voltage to dip below the UV threshold.
Table 4. The Guideline for Mode Selection
In severe cases where the supply inductance is 500nH or
more, the input can dip below the VDD undervoltage lock-
out threshold of 5.5V. It is possible for the UV comparator
or, the VDD UVLO circuit to respond before the current
reaches the current limit threshold. Adding a 100nF filter
capacitor to the UV pin ensures that the UV compara-
tor responds after current limiting commences. The fast
Mode
Power Level
<800W
Supply Range
Narrow or Wide
Narrow or Wide
Wide
Single Driver
Parallel
HSSS
<1500W
>1500W
>1500W
LSSS
Narrow
Two or More LTC4238 >3000W
Using the COMM Pin
Rev. 0
24
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LTC4238
APPLICATIONS INFORMATION
Example 1: Parallel Mode with Current Limit Start-Up
and SOA Timer
ꢄ
ꢀ
ꢀ
ꢁꢁ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢁꢁ
R
ꢀ ꢁ R
ꢂ
R
R
ꢀꢁꢂꢀꢁꢃꢄ
ꢀꢁꢂꢀꢁꢃꢄ
As a design example, take the following specifications:
R
ꢅ ꢆ R
R
ꢀ ꢁ R
ꢀ
ꢀ
ꢀ
ꢂ
V
= 48V 20%, the maximum load power of 1.4kW,
IN
ꢄ
start into active current limit and C = 1500μF. The par-
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ ꢄꢅ0
L
allel mode is chosen based on the guideline above. In
the parallel mode, GATE1 and GATE2 drive two parallel
channels of MOSFETs to charge the load capacitor simul-
taneously at startup, share the load current after startup,
and turn off simultaneously upon a fault condition such
as output overload or short-circuit. Since the input volt-
age varies between 38V and 58V, the high power profile
is selected for foldback to better cope with input varia-
tions without folding back the current limit threshold. In
addition, SOA Timer is picked for the TMR pin to protect
the MOSFETs more effectively. This completed design is
shown in Figure 1.
Figure 10. Weighted Averaging Sense Voltages
Step 2. Select the MOSFETs. The MOSFET should be
sized to handle the power dissipation during the inrush
charging of the load capacitor C . In addition, the R
L
DS(ON)
must be low enough to carry maximum load current. The
method used to determine the power is the principle:
E = Energy in C = Energy in M1+ Energy in M2 (7)
C
L
Thus:
1
1
2
2
(8)
E = CV = (1500µF) • (58V) ≈ 2.5J
C
2
2
The maximum load current is calculated by:
During start-up, current limit foldback will limit the power
dissipation in MOSFET of each channel to:
P
1400W
38V
L(MAX)
I
=
=
≈ 37A
(6)
L(MAX)
V
UV(ON)
10mV • 30% • 58V
(9)
P
=
≈ 348W
DISS,START-UP
0.5mΩ
Calculate the time it takes to charge up C .
Since there are two channels, the maximum current each
channel carries is 18.5A.
L
Step 1. Configure current limit and select current sense
resistors.
E
C
t
=
CHARGEUP
P
•2MOSFETs
DISS,START-UP
(10)
A 10mV sense voltage with a 0.5mΩ sense resistance is
picked to provide 20A for each channel. When a specific
design is actually built, there can be small inaccuracies
in the current sensing owing to contact and copper trace
resistances. An immediate remedy without changing
sense resistors is to readjust the sense voltage in 2mV
steps. For instance, moving sense voltage from 10mV to
12mV gives a 20% increase in current.
2.5J
=
≈ 3.6ms
348W •2
The SOA curves of candidate MOSFETs must be evalu-
ated to ensure that heat capacity of the package can
tolerate this power for 3.6ms. The SOA curve of the
NXP PSMN3R7-100BSE shows it can sustain 9A with
60V across it for 10ms, satisfying this requirement.
Additional MOSFETs in parallel may be required to
keep power dissipation within limits at maximum load
current, or to reduce the worst case MOSFET drain
to source voltage. In this design a pair of PSMN3R7-
100BSE is required for both channels. The worst-case
MOSFET drain to SOURCE voltage with full load is:
Some designers may use parallel sense resistors to
achieve a specific resistance, in which case the averag-
ing resistors, R , should be selected with the same ratio,
A
k, as the sense resistors they connect to. See Figure 10.
This allows the current limit circuit to measure the correct
sense voltage for this effective sense resistor. The small-
est averaging resistor should not exceed 1Ω.
Rev. 0
25
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LTC4238
APPLICATIONS INFORMATION
thermal resistance of the board is added to the termi-
nation resistance (the largest one). Assuming a 5°C/W
board thermal resistance in this application, it is con-
ICH(MAX) •RDS(ON),MAX
VDS,MAX
=
2
(11)
5
verted to 5 • 1.4 • 10 = 700k. If the computed resistance
20A •3.7mΩ
=
= 37mV
for the board thermal resistance is over 1M, choose 1M.
This avoids accuracy degradation due to board leakage
currents. The resulting electrical capacitors and resis-
2
There is enough margin with the full current load for
V
– SOURCE before reaching FET bad threshold of
DD
100mV.
tors are CE1 = 6.8nF, RE1 = 1.82k, CE2 = 56nF, RE2
=
22.6k, CE3 = 680nF, RE3 = 750k, as shown in Figure 1 and
Figure 3. After the SOA timer is configured, run simula-
tions in LTspice to ensure TMR does not reach its 2.56V
trip point in any operating conditions including start-up
and input step. When it trips in fault conditions such as
output overload or short-circuit, verify the peak tempera-
ture of the MOSFET matches the proposed maximum
temperature. Iterations of the above procedure may be
needed before the RC network is finalized.
Since PSMN3R7-100BSE has about 10nF of gate
capacitance it is likely to be stable, but the short-circuit
stability of the current limit loop should be checked and
improved by adding capacitors from GATE to SOURCE
if needed.
Step 3. Select the RC network for the SOA timer following
the procedure as shown in the SOA Timer section. Three
thermal capacitors and three thermal resistors provide
fairly good curve fitting for the thermal impedance plot
of the chosen MOSFET, PSMN3R7-100BSE in the range
between 100μs and 100ms (wide enough for typical oper-
Step 4. Design the FET-bad timer. During start-up the FET-
Bad Timer is running. The load capacitor must be fully
charged before this timer expires, or the gate outputs will
be turned off once a FET-bad fault is triggered. For a start-
up time of 3.6ms and taking into account the tolerance of
components, we choose having a 2× safety margin.
ating conditions of this application): C = 0.001J/°C,
θ1
Rθ1 = 0.013°C/W, Cθ2 = 0.008J/°C, R = 0.16°C/W,
θ2
C
= 0.1J/°C, R = 0.27°C/W. The conversion constant
θ3
θ3
is given by:
T
3.6ms
START-UP
C
= 2 •
= 2 •
≈ 56nF
(13)
FET
128ms /µF
128ms /µF
VTMR(TH)
VDS,MAX •ID,MAX
ITMR(UP),MAX
k =
•
∆TMAX
The closest larger available capacitance 62nF is picked.
Step 5. VUV(ON) = 36V, VUV(OFF) = 60V, VPWRGD(UP)
33V. Select resistive dividers for UV/OV and Power Good
inputs. The UV and OV resistor string values can be solved
in the following method. To keep the error due to 1μA of
leakage to less than 1% choose a divider current of at
least 200μA. R1 < 2.56V/200μA = 12.8kΩ. Then calculate:
=
58V •20mV
400µA •0.5mΩ 175°C–65°C
2.56V
=
•
(12)
2
⎡
⎢
⎣
⎤
V
=1.4•105
⎥
°C
⎢
⎥
⎦
V
UV
TH(RISING)
where ΔTMAX is the maximum allowable temperature
rise and chosen to be 110°C, which corresponds to a
maximum MOSFET temperature of 175°C at an operat-
ing temperature of 65°C. The thermal R and C values are
then converted to electric R and C values as shown in
the SOA timer section. After the electrical R and C val-
ues are computed, choose the closest next-larger avail-
able resistor value and the closest next-smaller available
capacitor value. Then the resistance corresponding to the
OV(OFF)
R2 =
•R1•
–R1
(14)
V
OV
TH(FALLING)
UV(ON)
V
•(R1+ R2)
UV(ON)
R3 =
–R1–R2
(15)
UV
TH(RISING)
In our case we choose R1 to be 4.22k to give a resis-
tor string current greater than 200μA. Then, solving the
equations results in R2 = 3.01k and R3 = 93.1k. A 0.1μF
Rev. 0
26
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LTC4238
APPLICATIONS INFORMATION
capacitor, C , is placed on the UV pin to prevent supply
The maximum load current is calculated by Equation 17.
F
glitches from turning off the GATE via UV or OV.
I
= P
/V
= 2500W/43V ≈ 58A (17)
L(MAX)
L(MAX) S(MIN)
The FB divider is solved by picking R8 and solving for R7,
choosing 5.23k for R8.
With the two channels decoupled (channel 2 dedicated to
start-up and channel 1 dedicated to passing the load cur-
rent), the overall design flow and design considerations in
some individual steps of the low stress staged start mode
are different from the parallel mode.
V
PWRGD(UP)
R7 =
•R8 –R8
(16)
FB
TH(RISING)
resulting in R7 = 62k.
Step 1. Select sufficient bypass MOSFETs to carry the
maximum load current. For the maximum channel current
of 58A, two IPT015N10N5 (RDS(ON) < 1.5mΩ) devices
result in 1.26W per package, an acceptable dissipation
with airflow.
Since the fast-current limit comparator is engaged at
120A, the input TVS needs to be capable of clamping a
120A surge at a voltage above the OV threshold but below
the 100V absolute maximum rating of the LTC4238 for
about 1μs. The SMC5K60A clamps 51.7A at 96.8V for
1ms and can dissipate 23kW for 10μs. Three of them are
required to sink 120A current.
With full load, the worst-case voltage across the MOSFET
is about 58A • (1.5/2)mΩ = 43.5mV. The threshold for
starting the FET-bad timer is 100mV. There is sufficient
margin to account for inaccuracies before enabling the
TMRFET pull-up current. See detailed design consider-
ations in Example 1, Step 2.
In addition, a 0.1µF ceramic bypass capacitor is placed
on the INTVCC pin. No bypass capacitor is required on
the V pin.
DD
Step 2. Configure the current limit and select the current
sense resistors. The current limit in this example should
cover the maximum load current, with enough margin to
account for device tolerances. Pick the minimum resis-
tance available for a single sense resistor, 200µΩ, which is
a metal element resistor. Select the current limit threshold
voltage by first assuming channel 1 carries the maximum
load current, then add a small current carried by the start-
up channel for the margin.
Example 2: Low Stress Staged Start Mode with Basic
Timer
The second example has a line regulated 48V supply with
the voltage variation of 10%. The output is a 2.5kW con-
stant power load. V
= 36V and V
= 60V as
UV(ON)
OV(OFF)
shown in Figure 6. The load capacitance is specified as CL
= 2500μF. The low stress staged start mode is chosen for
this example since the power exceeds 1500W and there
is no concern of large input steps. In LSSS, the FET bad
timer will run if GATE1 is low and not in ACL (Table 2),
which could happen when the power good voltage hasn’t
been reached. Therefore, the power good voltage is rec-
ommended to be lower than the input UV voltage. In this
ΔVSENSE(MIN) = RS1 • IL(MAX) = 200µΩ • 58A ≈ 12mV (18)
The resistor power dissipation of channel 1 is given by
Equation 21.
PS1 = ΔVSENSE(MIN) • IL(MAX) = 12mV • 58A = 696mW (19)
example, V
is set to 33V. The current in chan-
PWRGD(UP)
Which is well within the power limit of several Watts for
a metal element sense resistor.
nel 2 is usually only a small fraction of the maximum load
current, such as 10% or less. For this reason, its cur-
rent contribution during normal operation can be ignored
for the first phase of the design. Later channel 2 can be
accounted for or sized to make up for any shortfall in the
high current (channel 1) path, so that full power (2500W)
can be supplied at minimum input voltage (43V).
As a last step, a 4mΩ sense resistor is chosen for a chan-
nel 2 current:
∆VSENSE 12mV
ILIM1
=
=
= 3A
(20)
RS2
4mΩ
Rev. 0
27
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LTC4238
APPLICATIONS INFORMATION
so that the total current limit is calculated by Equation 21.
12mV
The FET bad timer must be set longer than the startup
time for the load capacitor to be fully charged. Meanwhile,
FET-bad timer should be short enough that the FET picked
for channel 2 can handle the start-up current with the full
drain to source voltage for this duration. With a 2× safety
margin, we choose:
ILIM =ILIM1+ILIM2
=
+3A = 63A
(21)
200µΩ
Taking all tolerances into account, this provides sufficient
margin for the maximum load current of 58A.
2 • t
•I
TMRFET(UP)
START-UP
Step 3. Design the TMR behavior. Since there is no con-
cern about a large input step, a short timer delay is chosen
for overcurrent turn-off. In the low stress staged start
mode the TMR function is a filtered circuit breaker and
a single timer capacitor on TMR works for this purpose.
Channel 1 dictates the timer capacitor selection since it
carries most of the load current. All of the channel 1 cur-
rent could be concentrated into a single MOSFET. The
current limit of channel 1 is 60A in this example, and
the MOSFET (IPT015N10N5) can handle 50V and 60A
for 80μs. It has been found that 20μs of circuit breaker
filtering is sufficient to reject noise encountered in most
systems, so the chosen MOSFET is up to the task. The
TMR pull-up current is 20μA, with a voltage threshold of
2.56V. Compute the timer capacitance for 20μs filter delay
using Equation 22.
C
=
=
FET
2.56V
(24)
2 •74ms •20µA
2.56V
= 1.2µF
The next larger available capacitance, 1.5µF, is used.
Since the start-up current is relatively low, a small, low
cost device may be used. PSMN7R6-100B, which can
stand the 30% foldback of 3A at 48V as a DC condition is
selected for this trickle channel. Its R
is no higher
DS(ON)
than 7.6mΩ. After startup, the worst-case power dissipa-
tion in this channel is (3A)2 • 7.6mΩ = 68mW, well within
the MOSFET capability.
Step 5. Run simulations to verify temperature rises in
both the channel 1 and channel 2 MOSFETs under all oper-
ating and fault conditions. This is a necessary step when
using a single capacitor current limit timer as selected
in Step 3.
I
• t
TMR(UP),MAX FILTER
C
=
TMR
V
TMR(TH)
(22)
First, check the temperature rise in the channel 2 MOSFET
(M2) during startup. The conditions include normal startup
into current limit to fully charge the 2500μF load capacitor
at the maximum input voltage. If the temperature rise is
too high in normal startup condition, a larger MOSFET
can be selected for channel 2. For the fault condition, the
worst-case power dissipated in MOSFET is same as the
max voltage (53V) across the MOSFET with 30% of full
current limit since the constant power profile is selected
for foldback. If the temperature rise is too high, the startup
current limit may be reduced by selecting a larger sense
resistor R . Using the conditions of this example, it is
found theSw2 orst-case temperature rise in M2 either in
normal startup condition or with fault resistors is lower
than 50°C. This verifies the selected channel 2 MOSFET,
PSMN7R6-100B, has more than enough SOA to handle
the worst-case dissipation.
20µA •20µs
2.56V
=
= 156pF
Select the next-larger available capacitance: CTMR
180pF.
=
Step 4. Design the start-up channel (channel 2) and FET-
bad timer. At start-up in low stress staged start mode,
channel 2 charges the load capacitance with a small trickle
current. The necessary start-up time for a 2500μF load
capacitor is:
1
2
2
C • V
L
t
=
=
CHAREGUP
P
DISS,START-UP
(23)
1
2
•2500µF •(53V)
3A •30% •53V
2
= 74ms
Rev. 0
28
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LTC4238
APPLICATIONS INFORMATION
Second, check the temperature rise in channel 1 after
startup when TMR times out under different overload
conditions. In this example, IPT015N10N5 can take 60A
with 40V across it for 100µs. The temperature rise in 20µs
is insignificant under overload conditions. If the worst-
case temperature rise in channel 1 is too high, better SOA
MOSFET(s) must be selected for it.
to put the INTV bypass capacitor as close as possible
CC
between the INTV and GND pins. A 0.1μF capacitor,
CC
C , from the UV pin (and OV pin through resistor R2)
F
to GND also helps reject supply noise. Figure 11 shows
a layout that addresses these issues. Note that a surge
suppressor, Z1, is placed between supply and ground
using wide traces.
It is advised to avoid placing the ground plane under the
power MOSFETs. If the MOSFETs overheat, the insulation
could fail between the input voltage at their drains and an
underlying ground plane. This could create a catastrophic
short across the supply.
Layout Considerations
For high current applications, PCB layout plays a critical
role in minimizing current congestion as well as partition-
ing the current between two channels. In parallel mode,
to achieve the even split of current flow between the two
channels, the two high current paths should have very
ꢋ
ꢈꢉꢊꢈꢉ RꢉꢈꢋꢈꢌꢍR R
ꢎꢍꢏꢐ
ꢈ
similar layouts for the R
and MOSFET placements.
ꢒ
ꢋꢊ
SENSE
To achieve accurate current sensing, Kelvin connec-
+
–
tions are also required. The SENSE and SENSE lines
should be laid out as differential signal pair. Their trace
lengths to LTC4238 pins should be as short as possible.
The minimum trace width for 1oz copper foil is 0.02" per
amp to make sure the trace stays at a reasonable tem-
perature. Using 0.03" per amp or wider is recommended.
Note that 1oz copper exhibits a sheet resistance of about
530μΩ/. Small resistances add up quickly in high cur-
rent applications.
ꢆꢅ
Rꢂ
Rꢁ
Rꢅ
ꢓꢒ
ꢍꢒ
ꢄꢖ
ꢇ
ꢄ
Rꢃ
ꢋ
ꢎꢍꢏꢐ
To improve noise immunity, place the resistive voltage
dividers for the UV, OV and FB pins close to the device and
ꢑꢊꢐ
ꢀꢁꢂꢃ ꢄꢅꢅ
Figure 11. Recommended PCB Layout
keep traces to V and GND short. It is also important
DD
Rev. 0
29
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LTC4238
PACKAGE DESCRIPTION
UFD Package
24-Lead Plastic QFN (4mm × 5mm)
ꢂReꢨeꢩeꢪꢫe ꢘꢌꢕ ꢆꢏꢐ ꢬ 0ꢉꢙ0ꢭꢙꢁꢢꢮꢢ Rev ꢎꢈ
0.ꢤ0 0.0ꢉ
ꢀ.ꢉ0 0.0ꢉ
ꢜ.ꢁ0 0.0ꢉ
ꢃ.ꢢꢉ 0.0ꢉ
ꢃ.00 Rꢇꢝ
ꢜ.ꢢꢉ 0.0ꢉ
ꢑꢎꢕꢖꢎꢐꢇ ꢋꢗꢌꢘꢅꢊꢇ
0.ꢃꢉ 0.0ꢉ
0.ꢉ0 ꢒꢄꢕ
ꢜ.00 Rꢇꢝ
ꢀ.ꢁ0 0.0ꢉ
ꢉ.ꢉ0 0.0ꢉ
Rꢇꢕꢋꢓꢓꢇꢊꢆꢇꢆ ꢄꢋꢘꢆꢇR ꢑꢎꢆ ꢑꢅꢌꢕꢞ ꢎꢊꢆ ꢆꢅꢓꢇꢊꢄꢅꢋꢊꢄ
ꢎꢑꢑꢘꢡ ꢄꢋꢘꢆꢇR ꢓꢎꢄꢖ ꢌꢋ ꢎRꢇꢎꢄ ꢌꢞꢎꢌ ꢎRꢇ ꢊꢋꢌ ꢄꢋꢘꢆꢇRꢇꢆ
R ꢥ 0.0ꢉ ꢌꢡꢑ
ꢑꢅꢊ ꢁ ꢊꢋꢌꢕꢞ
ꢃ.00 Rꢇꢝ
R ꢥ 0.ꢃ0 ꢋR ꢕ ꢥ 0.ꢜꢉ
R ꢥ 0.ꢁꢁꢉ
ꢌꢡꢑ
0.ꢤꢉ 0.0ꢉ
ꢀ.00 0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢃꢜ
ꢃꢀ
0.ꢀ0 0.ꢁ0
ꢑꢅꢊ ꢁ
ꢌꢋꢑ ꢓꢎRꢖ
ꢂꢊꢋꢌꢇ ꢢꢈ
ꢁ
ꢃ
ꢉ.00 0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢜ.00 Rꢇꢝ
ꢜ.ꢢꢉ 0.ꢁ0
ꢃ.ꢢꢉ 0.ꢁ0
ꢂꢗꢝꢆꢃꢀꢈ ꢧꢝꢊ 0ꢉ0ꢢ Rꢇꢚ ꢎ
0.ꢃꢉ 0.0ꢉ
0.ꢃ00 Rꢇꢝ
0.ꢉ0 ꢒꢄꢕ
0.00 ꢦ 0.0ꢉ
ꢒꢋꢌꢌꢋꢓ ꢚꢅꢇꢏꢣꢇꢛꢑꢋꢄꢇꢆ ꢑꢎꢆ
ꢊꢋꢌꢇꢍ
ꢁ. ꢆRꢎꢏꢅꢊꢐ ꢑRꢋꢑꢋꢄꢇꢆ ꢌꢋ ꢒꢇ ꢓꢎꢆꢇ ꢎ ꢔꢇꢆꢇꢕ ꢑꢎꢕꢖꢎꢐꢇ ꢋꢗꢌꢘꢅꢊꢇ ꢓꢋꢙꢃꢃ0 ꢚꢎRꢅꢎꢌꢅꢋꢊ ꢂꢏꢛꢛꢛꢙꢛꢈ.
ꢃ. ꢆRꢎꢏꢅꢊꢐ ꢊꢋꢌ ꢌꢋ ꢄꢕꢎꢘꢇ
ꢜ. ꢎꢘꢘ ꢆꢅꢓꢇꢊꢄꢅꢋꢊꢄ ꢎRꢇ ꢅꢊ ꢓꢅꢘꢘꢅꢓꢇꢌꢇRꢄ
ꢀ. ꢆꢅꢓꢇꢊꢄꢅꢋꢊꢄ ꢋꢝ ꢇꢛꢑꢋꢄꢇꢆ ꢑꢎꢆ ꢋꢊ ꢒꢋꢌꢌꢋꢓ ꢋꢝ ꢑꢎꢕꢖꢎꢐꢇ ꢆꢋ ꢊꢋꢌ ꢅꢊꢕꢘꢗꢆꢇ
ꢓꢋꢘꢆ ꢝꢘꢎꢄꢞ. ꢓꢋꢘꢆ ꢝꢘꢎꢄꢞꢟ ꢅꢝ ꢑRꢇꢄꢇꢊꢌꢟ ꢄꢞꢎꢘꢘ ꢊꢋꢌ ꢇꢛꢕꢇꢇꢆ 0.ꢁꢉꢠꢠ ꢋꢊ ꢎꢊꢡ ꢄꢅꢆꢇ
ꢉ. ꢇꢛꢑꢋꢄꢇꢆ ꢑꢎꢆ ꢄꢞꢎꢘꢘ ꢒꢇ ꢄꢋꢘꢆꢇR ꢑꢘꢎꢌꢇꢆ
ꢢ. ꢄꢞꢎꢆꢇꢆ ꢎRꢇꢎ ꢅꢄ ꢋꢊꢘꢡ ꢎ RꢇꢝꢇRꢇꢊꢕꢇ ꢝꢋR ꢑꢅꢊ ꢁ ꢘꢋꢕꢎꢌꢅꢋꢊ
ꢋꢊ ꢌꢞꢇ ꢌꢋꢑ ꢎꢊꢆ ꢒꢋꢌꢌꢋꢓ ꢋꢝ ꢑꢎꢕꢖꢎꢐꢇ
Rev. 0
30
For more information www.analog.com
LTC4238
PACKAGE DESCRIPTION
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 1413
.045 .005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 .004
(0.38 0.10)
.0532 – .0688
(1.35 – 1.75)
× 45°
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN24 REV B 0212
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
31
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC4238
TYPICAL APPLICATION
48V, 150A Hot Swap Controllers Using the COMM Pin
ꢀꢁ ꢂꢃꢄꢅꢆꢀꢇ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀꢁꢂ
Rꢀꢁ
0.8mΩ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀ
ꢀꢁꢂ
ꢀꢁ0ꢂ
ꢁꢂꢃ
ꢀꢁꢂ
Rꢀꢁ
ꢀꢁꢂꢃꢄꢅ0ꢆ
ꢇꢈ
0.8mΩ
ꢀꢁꢂꢃꢄRꢅꢆꢇ00ꢈꢁꢉ
ꢀꢁꢂ
ꢀ
ꢁ
Rꢀ
360kΩ
Rꢀꢁ
Rꢀꢁ
10Ω
Rꢀꢁ
Rꢀꢁ
10Ω
ꢀꢁ
10Ω
10Ω
Rꢀ
ꢀꢁꢂ
ꢀꢁ
0.0ꢀꢁꢂꢃ
0.0ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
Rꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂRꢃꢄ
ꢀ
ꢀ
ꢁꢂꢃꢄ
ꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
FLT
ꢀꢁ
Rꢀ
ꢀ.ꢁꢂꢃ
ꢀꢁ
0.ꢀꢁꢂ
Rꢀ
ꢀ.0ꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢂ
Rꢀ
ꢀ.ꢁꢁꢂ
ꢀꢁ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆ ꢀꢁꢂꢃꢄꢅꢆ ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁRꢂꢃꢀ
ꢀꢁꢂ
ꢀꢁR
ꢀꢁꢂ
ꢀꢁ
0.ꢀꢁꢂ
ꢀꢁꢂꢃ
0.ꢀꢀꢁꢂ
ꢀ
ꢃ
ꢁꢂR
ꢀꢁ00ꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢁꢆꢇ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂRꢃ
ꢀꢁꢂꢃ ꢄꢅ0ꢁ
ꢀꢁꢂꢃꢄ ꢁꢂꢅ ꢁꢆ ꢇꢃꢃ ꢈꢉꢅ ꢃꢈꢊꢋꢌꢍꢎꢏ ꢂꢅꢅꢐꢑ ꢈꢁ ꢉꢇꢒꢅ ꢇ ꢊꢇꢓꢇꢊꢔꢈꢁR ꢊꢁꢂꢂꢅꢊꢈꢅꢐ ꢈꢁ ꢈꢉꢅ ꢈꢕR ꢓꢔꢂ.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
Active Current Limiting, Supplies from 9V to 80V
LT®1641-1/
Positive High Voltage Hot Swap Controllers
LT1641-2
LT4256-1/
LT4256-2
Positive 48V Hot Swap Controller with Open-Circuit Detect Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output, Up to
80V Supply
2
LTC4281
LTC4282
LTC4283
LTC4284
LTC4237
Positive Voltage Hot Swap Controller with I C Compatible 12-/16-Bit ADC Monitors Current, Voltage, Power and Energy, Internal
2
Monitoring
EEPROM, I C, Supplies from 2.9V to 33V
2
High Current Positive Voltage Hot Swap Controller with I C Dual Gate Drive, 12-/16-Bit ADC Monitors Current, Voltage, Power and
2
Compatible Monitoring
Energy, Internal EEPROM, I C, Supplies from 2.9V to 33V
–48V Hot Swap Controller with Energy Monitor
SOA Timer, 8-Bit to 16-Bit ADC Monitors Current, Voltage, Power and
2
Energy, Internal EEPROM, I C or Single-Wire Broadcast
–48V High Current Hot Swap Controller with Energy
Monitor
Dual Gate Drive, SOA Timer, 8-Bit to 16-Bit ADC Monitors Current, Voltage,
2
Power and Energy, Internal EEPROM, I C or Single-Wire Broadcast
Positive High Voltage Hot Swap Controllers
Active Current Limiting, Foldback Current Limiting, SOA Timer, FET Health
Monitor, Supplies from 6.5V to 80V
Rev. 0
07/20
www.analog.com
32
ANALOG DEVICES, INC. 2020
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