LTC4290 [ADI]
4-Port IEEE 802.3bt PoE PSE Controller;
| 型号： | LTC4290 |
| 厂家： | 
ADI |
| 描述： | 4-Port IEEE 802.3bt PoE PSE Controller |
| 文件： | 总50页 (文件大小：3420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC9101-1/
LTC9102/LTC9103
48-Port IEEE 802.3bt PoE PSE Controller
DESCRIPTION
FEATURES
n
Fully Compliant IEEE 802.3bt Type 3 and 4 PSE
Fully Compliant IEEE 802.3at Type 2 PSE
The LTC®9101-1/LTC9102/LTC9103 chipset is a 48-port
power sourcing equipment (PSE) controller designed for use
in IEEE 802.3at Type 2, 802.3bt Type 3 and 4 compliant Power
over Ethernet (PoE) systems. The LTC9101-1/LTC9102/
LTC9103 is designed to power compliant 802.3af, 802.3at,
and 802.3bt PDs. The LTC9101-1/LTC9102/LTC9103 chip-
set delivers lowest-in-industry heat dissipation by utilizing
low-RDS(ON) external MOSFETs and 0.1Ω sense resistance
per power channel. A transformer-isolated communication
protocol replaces expensive opto-couplers and complex iso-
lated 3.3V supply, resulting in significant BOM cost savings.
n
n
n
n
n
n
Software-Compatible with LTC4291-1/LTC4292
Up to 48 PSE Ports with One Power Channel per Port
Up to 24 PSE Ports with Two Power Channels per Port
ECC-Protected eFlash and Data RAMs
Low Power Path Dissipation per Channel
n
100mΩ Sense Resistance
30mΩ or Lower MOSFET R
n
DS(ON)
n
n
Chipset Provides Electrical Isolation
n
Eliminates Optos and Isolated 3.3V Supply
Very High Reliability Multipoint PD Detection
Advanced power management features include per-port
14-bit current/power monitoring, programmable current/
power limits, and versatile fast shut-down of preselected
ports. An advanced power management host software
layer is available. PD detection uses a proprietary multi-
point detection mechanism ensuring excellent immunity
from false PD identification. Autoclass and 5-event physi-
cal classification are supported. The LTC9101-1/LTC9102/
LTC9103 includes an I2C serial interface operable up to
n
Connection Check Distinguishes Single-
Signature and Dual-Signature PDs
n
n
n
n
Continuous Per-Port Power and Current Monitoring
2
2
1MHz I C Compatible Serial Control Interface
Pin or I C Programmable PD Power
Available in 24-Lead 4mm × 4mm (LTC9101-1) and
a 64-Lead 7mm × 11mm (LTC9102/LTC9103) QFN
Packages
2
1MHz. The LTC9101-1/LTC9102/LTC9103 is pin or I C pro-
grammable to negotiate PD delivered power up to 71.3W.
APPLICATIONS
n
PoE PSE Switches/Routers and Midspans
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
>47µF
ID:11b
ID:10b
ID:01b
0.1µF
3.3V
V
EE
ID:00b
1
1µF
V
100V
DD
CFG2
TX1
V
EE
0.1µF
100V
CFG1
CFG0
S1B
AGND
2
OUT1
ISOLATION
AUTO
3
RESET
MSD
CPD
CPA
GATE1
TX2
•
•
SENSE1
4PVALID
6
2
LTC9102/LTC9103
(NO I C
0.1Ω
4
ISOLATION
CND
CNA
LTC9101-1
VSSK1
REQUIRED)
TX3
V
EE
FLASH
0.1µF
100V
INT
5
S1B
OUT2
DPD
DPA
SCL
•
•
SDAIN
7
GATE2
SDAOUT
TX4
SENSE2
DND
DNA
8
AD2
AD3
0.1Ω
4
1000pF
2kV
1000BASE-T
RJ45
VSSK2
3
V
EE
DGND
2
V
EE ONE 4-PAIR PORT SHOWN
1
V
EE
9101123 TA01a
V
EE
Rev. 0
1
Document Feedback
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
ABSOLUTE MAXIMUM RATINGS
(Note 1)
(Notes 1, 4)
LTC9101-1
LTC9102/LTC9103
Supply Voltages (with respect to DGND)
Supply Voltages (with respect to V )
EE
V
...................................................... –0.3V to 3.6V
AGND ................................................... –0.3V to 80V
PWRIN ................................................. –0.3V to 80V
CAP3, CAP4 ........................................... –0.3V to 5V
VSSKn ................................................ –0.3V to 0.3V
Analog Pins
SENSEn, OUTn ...................................... –20V to 80V
GATEn, IDn, PWRMD ........................... –0.3V to 80V
CPA, CNA, DPA, DNA ...............–0.3V to CAP3 + 0.3V
EXT3...................................................... –0.3V to 30V
Operating Ambient Temperature ..............–40°C to 85°C
Operating Junction Temperature (Note 2)...–40°C to 125°C
Storage Temperature ............................. –65°C to 150°C
DD
CAP1, CAP2.........................................–0.3V to 1.32V
Digital Pins
ADn, AUTO, CFGn, MSD, SDAIN, SDAOUT,
SCL, RESET, INT, 4PVALID ........ –0.3V to V + 0.3V
DD
Analog Pins
CPD, CND, DPD, DND ............... –0.3V to V + 0.3V
DD
Operating Ambient Temperature ............. –40°C to 85°C
Operating Junction Temperature (Note 2).. –40°C to 125°C
Storage Temperature ............................ –65°C to 150°C
Rev. 0
2
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
PIN CONFIGURATION
LTC9101-1
TOP VIEW
24 23 22 21 20 19
CFG0
CFG1
CFG2
DNC
AD2
1
2
3
4
5
6
18 SCL
17
16
SDAIN
SDAOUT
25
DGND
15 INT
14
RESET
AD3
13 4PVALID
7
8
9 10 11 12
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
= 4°C/W, θ = 47°C/W
θ
JC
JA
EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB
LTC9102
LTC9103
TOP VIEW
TOP VIEW
CAP3 1
EXT3 2
GATE1 3
OUT1 4
SENSE1 5
VSSK1 6
VSSK2 7
SENSE2 8
OUT2 9
GATE2 10
GATE3 11
OUT3 12
SENSE3 13
VSSK3 14
VSSK4 15
SENSE4 16
OUT4 17
GATE4 18
GATE5 19
OUT5 20
52 ID1
51 ID0
CAP3 1
EXT3 2
52 ID1
51 ID0
50 GATE12
GATE1 3
49 OUT12
OUT1 4
50 GATE8
49 OUT8
48 SENSE8
47 VSSK8
46 VSSK7
45 SENSE7
44 OUT7
43 GATE7
42 GATE6
41 OUT6
40 SENSE6
39 VSSK6
38 VSSK5
37 SENSE5
36 OUT5
35 GATE5
34 NC
48 SENSE12
SENSE1 5
47 VSSK12
VSSK1 6
46 VSSK11
VSSK2 7
45 SENSE11
SENSE2 8
44 OUT11
OUT2 9
65
EE
43 GATE11
GATE2 10
42 GATE10
GATE3 11
41 OUT10
OUT3 12
65
EE
V
V
40 SENSE10
SENSE3 13
39 VSSK10
VSSK3 14
38 VSSK9
VSSK4 15
37 SENSE9
SENSE4 16
36 OUT9
OUT4 17
35 GATE9
GATE4 18
34 GATE8
NC 19
33 OUT8
NC 20
33 NC
UKJ PACKAGE
UKJ PACKAGE
64-LEAD (7mm × 11mm) PLASTIC QFN
64-LEAD (7mm × 11mm) PLASTIC QFN
θ
= 1°C/W, θ = 22°C/W
JA
JC
θ
= 1°C/W, θ = 22°C/W
JA
JC
EXPOSED PAD (PIN 65) IS V , MUST BE SOLDERED TO PCB
EE
EXPOSED PAD (PIN 65) IS V , MUST BE SOLDERED TO PCB
EE
ORDER INFORMATION
LEAD FREE FINISH
LTC9101AUF-1#PBF
LTC9102AUKJ#PBF
LTC9103AUKJ#PBF
TAPE AND REEL
PART MARKING PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC9101AUF-1#TRPBF
LTC9102AUKJ#TRPBF
LTC9103AUKJ#TRPBF
91011
24-Lead (4mm × 4mm) Plastic QFN
64-Lead (7mm × 11mm) Plastic QFN
64-Lead (7mm × 11mm) Plastic QFN
LTC9102
LTC9103
–40°C to 85°C
–40°C to 85°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
3
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
AGND – V
MIN
TYP
MAX
UNITS
Main PoE Supply Voltage
EE
l
l
Type 2 or 3 Compliant Output
Type 4 Compliant Output
51
53
57
57
V
V
l
l
LTC9102/LTC9103 Undervoltage Lock-Out
AGND – V
8.2
3.3
2.8
9
V
EE
V
V
Supply Voltage
V – DGND
DD
3
3.6
V
DD
DD
Undervoltage Lock-Out
Slew Rate, Falling
V
mV/μs
V
V
DD
2.4 ≤ V – DGND ≤ 3.0 (Note 7)
20
DD
V
V
, V
Internal Regulator Supply Voltage
Internal 3.3V Regulator Supply Voltage
CAP3 External Supply Rise Time
V
– DGND, V – DGND (Note 13)
CAP2
1.2
3.3
CAP1 CAP2
CAP1
l
l
CAP3 – V (Note 13)
3
3.6
1
V
CAP3
EE
t
0.5V < CAP3 < CAP3(Min), EXT3 Tied to CAP3
(Note 7)
ms
CAP3EXT
l
V
Internal 4.3V Regulator Supply Voltage
CAP4 – V (Note 13)
4.3
11
V
CAP4
EE
I
V
Supply Current
EE
PWRIN Pin Connected to AGND, EXT3 LOW, All
Gates Fully Enhanced.
7.7
4.2
14
mA
EE
3.3V Rail Supply Current
Supply Current
From CAP3 = 3.3V (EXT3 HIGH)
5.4
40
6.6
60
mA
mA
l
I
V
(V – DGND) = 3.3V
DD
DD
DD
Detection/Connection Check
l
l
Forced Current
Load Resistance 15.5k to 32k
Load Resistance 18.5k to 27.5k
220
143
240
160
260
180
µA
µA
l
l
Forced Voltage
7
3
8
4
9
5
V
V
l
l
l
Detection/Connection Check Current
AGND – OUTn = 0V
0.8
0.9
12
mA
V
Compliance
V
Detection/Connection Check Voltage
Compliance
AGND – OUTn, Open Port
10.4
OC
Detection/Connection Check Voltage Slew
Rate
AGND – OUTn, C
= 150nF (Note 7)
0.01
V/µs
PORT
l
l
Min. Valid Signature Resistance
Max. Valid Signature Resistance
15.5
27.5
17
18.5
32
kΩ
kΩ
29.7
Classification
l
l
V
Classification Voltage
AGND – OUTn, SENSEn – VSSKn < 5mV
SENSEn – VSSKn, OUTn = AGND (Note 15)
16
7
20.5
9
V
CLASS
Classification Current Compliance
Classification Threshold
8
mV
SENSEn – VSSKn (Note 15)
Class Signature 0 – 1
l
l
l
l
l
0.5
1.3
2.1
3.1
4.5
0.65
1.45
2.3
3.3
4.8
0.8
1.6
2.5
3.5
5.1
mV
mV
mV
mV
mV
Class Signature 1 – 2
Class Signature 2 – 3
Class Signature 3 – 4
Class Signature 4 – Overcurrent
l
l
V
Classification Mark State Voltage
Mark State Current Compliance
AGND – OUTn, SENSEn – VSSKn < 5mV
OUTn = AGND
7.5
7
9
8
10
9
V
MARK
mV
Gate Driver
GATE Pin Pull-Down Current
GATE Pin Fast Pull-Down Current
GATE Pin On Voltage
Port Off, GATEn = V + 5V
1
mA
mA
V
EE
GATEn = V + 5V
65
EE
l
GATEn – V , I
= 1µA
11
14
EE GATEn
Rev. 0
4
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Sense
l
l
V
Power Good Threshold Voltage
OUTn – V
2
2.4
2.8
V
PG
EE
OUT Pin Pull-Up Resistance to AGND
Port On
Port Off
2500
500
kΩ
kΩ
300
700
Current Sense
V
Active Current Limit,
Single-Signature PD
OUTn – V < 10V
LIM-2P
EE
Class 1 – Class 3
Class 4 – Class 6
Class 7
40
80
100
110
42.5
85
106
117
45
90
112
124
mV
mV
mV
mV
l
l
l
l
Class 8
Active Current Limit,
Dual-Signature PD
OUTn – V < 10V
EE
Class 1 – Class 3
Class 4
40
80
110
42.5
85
117
45
90
124
mV
mV
mV
l
l
l
Class 5
l
l
V
V
Active Current Limit, Inrush
DC Disconnect Sense Voltage
OUTn – VEE < 30V (Note 16)
Single-Signature, Class 1–4, 4-Pair Power
All Others
INRUSH-2P
HOLD-2P
20
40
21.3
42.5
22.5
45
mV
mV
SENSEn – VSSKn
Single-Signature Class 1–4, 4-Pair Power
Single-Signature Class 1–4, 2-Pair Power
Single-Signature Class 5–8, 4-Pair Power
Dual Signature, 2-Pair or 4-Pair Power
200
500
200
200
350
700
350
350
500
900
700
700
µV
µV
µV
µV
l
l
l
l
V
Short-Circuit Sense
SENSEn – VSSKn – V
60
mV
SC
LIM-2P
Port Current Readback (See Typical Performance Characteristics, Note 17)
Full-Scale Range
LSB Weight
(Notes 7, 15)
|SENSEn – VSSKn|, VSSKn = V (Note 15)
204.6
24.98
1.967
mV
μV/LSB
ms
EE
Conversion Period
V
EE
Readback (See Typical Performance Characteristics, Note 17)
Full-Scale Range
LSB Weight
(Note 7)
|AGND – V
82
V
mV/LSB
ms
|
EE
10.01
1.967
Conversion Period
Digital Interface
l
l
l
V
Digital Input Low Voltage
ADn, RESET, MSD, CFGn, AUTO, 4PVALID (Note 6)
SCL, SDAIN (Note 6)
0.8
1
V
V
V
ILD
2
I C Input Low Voltage
V
IHD
Digital Input High Voltage
Digital Output Low Voltage
(Note 6)
2.2
l
l
I
I
= 3mA, I = 3mA
0.4
0.7
V
V
SDAOUT
SDAOUT
INT
= 5mA, I = 5mA
INT
Internal Pull-Up to V
ADn, RESET, MSD, CFG2
AUTO, 4PVALID, CFG0
50
50
50
5
kΩ
kΩ
kΩ
μA
DD
Internal Pull-Down to DGND
EXT3 Pull-Down to V
EE
IDn Internal Pull-Up to CAP4
IDn = 0V
Rev. 0
5
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
380
15
MAX
UNITS
PSE Timing Characteristics (Note 7)
l
l
l
l
l
l
l
t
t
t
t
t
t
t
Detection Time
Beginning to End of Detection
500
ms
ms
ms
ms
ms
ms
ms
DET
Classification Reset Duration
Class Event Duration
15
6
CLASS_RESET
CEV
20
0.1
105
Class Event Turn On Duration
Long Class Event Duration
C
= 0.6µF
PORT
CEVON
LCE
88
6
Class Event I
Measurement Timing
CLASS
CLASS
Long Class Event I
Timing
Measurement
CLASS
6
75
CLASS_LCE
l
l
t
t
Autoclass I
Measurement Timing
88
6
105
12
ms
ms
CLASS_ACS
CLASS
Mark Event Duration (Except Last Mark
Event)
(Note 11)
(Note 11)
9.6
20
ME1
l
l
t
t
Last Mark Event Duration
6
ms
ms
ME2
PON
Power On Delay, Auto Mode
From End of Valid Detect to End of Valid Inrush
(Note 14)
400
1.6
3.5
l
l
t
Autoclass Power Measurement Start
Autoclass Power Measurement End
From End of Inrush to Beginning of Autoclass
Power Measurement
1.4
3.1
s
s
AUTO_PSE1
AUTO_PSE2
t
From End of Inrush to End of Autoclass Power
Measurement
l
l
l
t
t
t
Autoclass Average Power Sliding Window
Fault Delay
0.15
1.0
50
0.23
1.3
60
0.3
1.8
75
s
s
AUTO_WINDOW
From Power On Fault to Next Detect
ED
Maximum Current Limit Duration During
Inrush
ms
START
l
l
t
t
Maximum Overcurrent Duration After Inrush
Maximum Overcurrent Duty Cycle
50
65
75
ms
%
CUT
LIM
5.8
6.3
6.7
Maximum Current Limit Duration After
Inrush
(Note 12)
l
l
Type 3, t
Type 4, t
= 0x8
= 0x5
10
6
15
11
22
17
ms
ms
LIMn
LIMn
l
t
t
t
Maintain Power Signature (MPS) Pulse
Width Sensitivity
Current Pulse Width to Reset Disconnect Timer
(Note 8)
6
ms
MPS
l
Maintain Power Signature (MPS) Dropout
Time
(Note 5)
320
370
2
400
ms
DIS
Masked Shut Down Delay
6.5
3
µs
s
MSD
2
l
l
I C Watchdog Timer Duration
1.5
3
Minimum Pulse Width for Masked Shut
Down
µs
l
Minimum Pulse Width for RESET
4.5
µs
Rev. 0
6
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted.
(Notes 3 and 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C Timing (Note 7)
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
Clock Frequency
1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
SCLK
Bus Free Time
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
Figure 5 (Note 9)
(Notes 9, 10)
480
240
480
240
60
1
2
3
4
5
Start Hold Time
SCL Low Time
SCL High Time
SDAIN Data Hold Time
Data Clock to SDAOUT Valid
Data Set-Up Time
250
t
t
t
t
t
80
6
7
8
r
Start Set-Up Time
240
240
Stop Set-Up Time
SCL, SDAIN Rise Time
SCL, SDAIN Fall Time
Fault Present to INT Pin Low
Stop Condition to INT Pin Low
ARA to INT Pin High Time
SCL Fall to ACK Low
120
60
f
150
1.5
1.5
250
(Notes 9, 10)
(Note 9)
(Note 9)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifespan.
Note 9: Values Measured at V
Note 10: If a fault condition occurs during an I C transaction, the INT pin
will not be pulled down until a stop condition is present on the I C bus.
Note 11: Load characteristics of the LTC9102/LTC9103 during Mark: 7V <
.
IHD
2
2
Note 2: This chipset includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC9102/LTC9103 operates with a negative supply voltage
(with respect to AGND). To avoid confusion, voltages in this data sheet are
referred to in terms of absolute magnitude.
(AGND – V
) < 10V.
OUTn
Note 12: See the LTC9101-1 Software Programming documentation
for information on serial bus usage and device configuration and
status registers.
Note 13: Do not source or sink current from CAP1, CAP2, CAP3 and CAP4.
Note 14: For single-signature PDs, t
detect on either power channel. For dual-signature PDs, t
from the end of valid detect on the same power channel.
Note 15: Port current and port power measurements depend on sense
resistor value (0.1Ω typical). See External Component Selection for details.
Note 16: See Inrush Control for details on inrush threshold selection.
Note 17: ADC characteristics and typical performance are described in
terms of LTC9102/LTC9103 hardware capability. Measurements from
LTC9102/LTC9103 are processed and synthesized by LTC9101-1 to
maintain backwards compatibility with LTC4291 software interface. See
LTC9101-1 Software Interface for register descriptions and LSB weights
is measured from end of valid
PON
is measured
PON
Note 5: t is the same as t
defined by IEEE 802.3.
DIS
MPDO
Note 6: The LTC9101-1 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3 defines MPS as the set of minimum PSE and PD
input current requirements to maintain power. An LTC9101-1/LTC9102/
LTC9103 port resets its MPS timer when V
– VSSKn ≥ V
for
SENSEn
HOLD-2P
(port current, port power, V voltage, and system temperature).
EE
t
and removes port power when V
– VSSKn ≥ V
for a
MPS
SENSEn
HOLD-2P
period longer than t . See Disconnect section.
DIS
Rev. 0
7
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
TYPICAL PERFORMANCE CHARACTERISTICS (RSENSE = 0.1Ω unless otherwise specified.)
802.3bt Single-Signature
Classification and Power-On, 4-Pair
802.3bt Single-Signature
Power-On Sequence, 4-Pair
802.3bt Single-Signature
Power-On Sequence, 2-Pair
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
CLASS8
DETECTION
DETECTION/
CONNECTION
CHECK
CLASSIFICATION
CLASSIFICATION
CLASSIFICATION
OUT1A
OUT1B
OUT1A
OUT1B
POWER
POWER
ON
POWER
ON
ON
V
EE
V
V
EE
EE
9101123 G01
9101123 G02
9101123 G03
200ms/DIV
50ms/DIV
100ms/DIV
802.3bt Dual-Signature
Power-On Sequence
802.3bt Single-Signature Class
Probe and Demotion
Open Circuit Detection
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
CLASS5
CLASS8
AGND
OUT1B
5V/DIV
DETECTION/
CONNECTION
CHECK
AGND
OUT1A
5V/DIV
CLASS3
DEMOTION
PROBE
CLASS 8
CLASSIFICATION
CLASS
BACKOFF
RESET
OUT1A
OUT1B
OUT1A
OUT1B
POWER
ON
POWER
ON
9101123 G06
50ms/DIV
V
EE
V
EE
9101123 G04
9101123 G05
200ms/DIV
50ms/DIV
Power-On Current Limits
Single-Signature
Inrush Current Limit (Note 16)
120
100
80
60
40
20
0
1200
120
100
80
60
40
20
0
1200
1000
800
600
400
200
0
LIMn = 80h
LIMn = 08h
CLASS 1–3
CLASS 4–6
CLASS 7
1000
800
600
400
200
0
AGND – V = 55V
EE
CLASS 8
AGND – V = 55V
EE
0
11
22
33
44
55
0
11
22
33
44
55
OUTn – V (V)
OUTn – V (V)
EE
EE
9101123 G07
9101123 G08
Rev. 0
8
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
TYPICAL PERFORMANCE CHARACTERISTICS (RSENSE = 0.1Ω unless otherwise specified.)
Power-On Current Limits
Dual-Signature
ILIM-2P vs Temperature
120
100
80
60
40
20
0
1200
1000
800
600
400
200
0
45
44
43
42
41
40
450
440
430
420
410
400
LIMn = 80h
CLASS 1–3
CLASS 4
CLASS 5
OUTn = V
EE
AGND – V = 55V
EE
0
11
22
33
44
55
–40 –20
0
20
40
60
80 100
OUTn – V (V)
T
(°C)
EE
A
9101123 G09
9101123 G10
Port Current Readback
Classification Current Compliance
700
600
500
400
300
200
100
0
0
–4
SENSEn – VSSKn = 89.6mV
N = 4488
µ = 89.610
σ = 0.252
24.98µV/LSB
–8
–12
–16
–20
88.1 88.6 89.1 89.6 90.1 90.6 91.1
0
0
20
40
60
80
100(mA)
10(mV)
2
4
6
8
READBACK (mV)
9101123 G12
CLASSIFICATION CURRENT (mA)
SENSEn – VSSKn (mV)
9101123 G11
Port Current Readback vs
Temperature
Port Current Readback Offset
Port Current Readback LSB
2500
2000
1500
1000
500
500
400
300
200
100
0
100.8
100.6
100.4
100.2
100.0
99.8
N = 4476
µ = 10.931
σ = 14.363
SENSEn – VSSKn = 0
SENSEn – VSSKn = 100mV
N = 4488
µ = 24.980
σ = 0.070
24.98µV/LSB
24.98µV/LSB
0
99.6
–100 –75 –50 –25
0
25 50 75 100
24.6 24.7 24.8 24.9 25.0 25.1 25.2 25.3 25.4
–40 –20
0
20
40
60
80 100
READBACK (µV)
(µV/LSB)
T
(°C)
A
9101123 G13
9101123 G14
9101123 G15
Rev. 0
9
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
TYPICAL PERFORMANCE CHARACTERISTICS (RSENSE = 0.1Ω unless otherwise specified.)
VEE Supply Current vs Voltage and
Temperature
VEE Readback
VEE Readback vs Temperature
30
25
20
15
10
5
55.2
55.1
55.0
54.9
54.8
54.7
54.6
54.5
16
15
14
13
12
11
10
ALL PORTS ON
CLASS 8 LIMITS
EXT3 TIED TO V
N = 364
µ = 54.998
σ = 0.058
AGND – V = 55V
AGND – V = 55V
EE
EE
10.01mV/LSB
10.01mV/LSB
EE
PWRIN FLOATED
85°C
25°C
–40°C
0
54.7 54.8 54.9 55.0 55.1 55.2 55.3
–40 –20
0
20
40
60
80 100
30
35
40
45
50
55
60
READBACK (V)
T (°C)
A
AGND – V (V)
EE
9101123 G16
9101123 G17
9101123 G18
Port Power Readback vs
Temperature
Powering Up into 180μF
Short Circuit Recovery
55.5
AGND – V = 55V
EE
V
= –55V
EE
55.4
55.3
55.2
55.1
55.0
54.9
54.8
54.7
54.6
54.5
SENSEn – VSSKn = 100mV
OUT
CURRENT
5A/DIV
LIMn = E9h
OUT1A
POWERn = 55W
20V/DIV
V
EE
FAST PULL-DOWN
LOAD FULLY CHARGED
FOLDBACK
CHANNEL
CURRENT
200mA/DIV
GATE
10V/DIV
QUICK CURRENT LIMIT RECOVERY
FAULT
CURRENT
LIMIT
OUT
50V/DIV
REMOVED
GATE1A
10V/DIV
MOSFET ON
5ms/DIV
9101123 G20
9101123 G21
SHORT-CIRCUIT
50µs/DIV
FAULT APPLIED
–40 –20
0
20
40
(°C)
60
80 100
T
A
9101123 G19
LTC9102/LTC9103 CP/CN and
DP/DN Common Mode
Correction Current
CLOCK and DATA WRITE
EYE DIAGRAM
CLOCK and DATA READ
EYE DIAGRAM
4
3
N = 337
N = 570
2
CP – CN
CP – CN
1
200mV/
DIV
200mV/
DIV
0
–1
–2
–3
–4
DP – DN
DP – DN
9101123 G22
9101123 G23
10ns/DIV
10ns/DIV
0
0.5
1
1.5
2
2.5
3
3.5
V
(V)
CM
9101123 G24
Rev. 0
10
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
TYPICAL PERFORMANCE CHARACTERISTICS (RSENSE = 0.1Ω unless otherwise specified.)
LTC9101-1 VDD Supply Current vs
Voltage and Temperature
EXT3 Pin Current vs Voltage
IDn Pin Current vs Voltage
80
70
60
50
40
30
20
10
0
2
0
40.0
37.5
35.0
32.5
30.0
27.5
25.0
22.5
20.0
85°C
25°C
–40°C
–2
–4
–6
–8
–10
0
1
2
3
4
5
0
1
2
3
4
5
2.9
3
3.1 3.2 3.3 3.4 3.5 3.6
(V)
EXT3 – V (V)
IDn – V (V)
V
DD
EE
EE
9101123 G25
9101123 G26
9101123 G27
TEST TIMING DIAGRAMS
DETECTION
CONNECTION
CHECK
CLASSIFICATION
TURN ON
t
DET
FORCED-
VOLTAGE
FORCED-CURRENT
0V
2.8V
t
ME1
t
ME2
t
ME1
V
OUTn
V
OC
V
MARK
15.5V
20.5V
V
CLASS
t
t
LCE
LCE
t
CEV
t
CEV
PD
CONNECTED
t
CEVON
t
CLASS_RESET
V
EE
t
START
t
PON
INT
9101123 F01
Figure 1. Detect, Class and Turn-On Timing, 4-Pair Port, Primary Alternative, Auto or Semi-Auto Mode
Rev. 0
11
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
TEST TIMING DIAGRAMS
V
LIM-2P
I
V
CUT-2P
CUT-2P
V
TO VSSKn
0V
SENSEn
0
t
t
, t
CUT
START LIM
INT
INT
9101123 F02b
9101123 F02a
(a) Current Limit Timing
(b) Current Cutoff Timing
Figure 2. Current Timings
V
SENSEn
V
HOLD-2P
TO VSSKn
INT
t
t
DIS
MPS
9101123 F03
Figure 3. DC Disconnect Timing, 2-Pair System
80%
V
GATEn
V
EE
t
MSD
MSD
9101123 F04
Figure 4. Shut Down Delay Timing
t
t
r
3
t
t
f
4
SCL
SDA
t
t
6
t
7
t
8
t
5
2
9101123 F05
t
1
Figure 5. I2C Interface Timing
Rev. 0
12
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
I2C TIMING DIAGRAMS
SCL
SDA
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
0
1
0
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
ACK BY
SLAVE
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
9101123 F06
Figure 6. Writing to a Register
SCL
SDA
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
0
AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
0
1
0
1
0
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
REPEATED
START BY MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
9101123 F07
Figure 7. Reading from a Register
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W
FRAME 1
ACK
D7 D6 D5 D4 D3 D2 D1 D0
ACK
STOP BY
MASTER
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 2
DATA BYTE
SERIAL BUS ADDRESS BYTE
9101123 F08
Figure 8. Reading the Interrupt Register (Short Form)
SCL
SDA
0
0
0
1
1
0
0
R/W
ACK
0
1
0
AD3 AD2 AD1 AD0
1
ACK
STOP BY
MASTER
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
ALERT RESPONSE ADDRESS BYTE
FRAME 2
SERIAL BUS ADDRESS BYTE
9101123 F09
Figure 9. Reading from Alert Response Address
Rev. 0
13
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
PIN FUNCTIONS
LTC9101-1
RESET (Pin 14): Reset Input, Active Low. When RESET
is low, the LTC9101-1/LTC9102/LTC9103 is held inactive
with all ports off and all internal registers reset. When
RESET is pulled high, the LTC9101-1/LTC9102/LTC9103
begins normal operation. RESET can be connected to an
external capacitor or RC network to provide a power turn-
on delay. Internal filtering of RESET prevents glitches less
than 1µs wide from resetting the LTC9101-1/LTC9102/
LTC9103. Internally pulled up to VDD.
CFG[2:0] (Pins 3, 2, 1 Respectively): Device Configuration
Inputs. Tie the configuration pins high or low to set num-
ber of ports, channels per port, and number of connected
LTC9102/LTC9103s. See Device Configuration for details.
CFG[0] is ignored when a custom configuration package is
present. See Stored Configurations for details.
2
AD[3:2] (Pins 6, 5 Respectively): I C Address Bits 3 to
2
2. Tie the address pins high or low to set the base I C
INT (Pin 15): Interrupt Output, Open Drain. INT will
pull low when any one of several events occur in the
LTC9101-1. It will return to a high impedance state when
bits 6 or 7 are set in the Reset PB register (0x1A). The
INT signal can be used to generate an interrupt to the
host processor, eliminating the need for continuous soft-
ware polling. Individual INT events can be disabled using
the Int Mask register (0x01). See LTC9101-1 Software
Programming documentation for more information. INT
serial address. The base address will be (010A3A200)b.
Internally pulled up to V . See Bus Addressing for details.
DD
CAP[2:1] (Pins 7, 23 Respectively): Core Power Supply
Bypass Capacitors. Connect each pin to a 1μF capacitance
to DGND for the internal 1.2V regulator bypass. Do not
use other capacitor values. Do not source or sink current
from this pin.
CPD (Pin 8): Clock Transceiver Positive Input Output
(Digital). Connect to CPA through a data transformer.
2
is only updated between I C transactions.
SDAOUT (Pin 16): Serial Data Output, Open Drain Data
CND (Pin 9): Clock Transceiver Negative Input Output
2
Output for the I C Serial Interface Bus. The LTC9101-1
(Digital). Connect to CNA through a data transformer.
uses two pins to implement the bidirectional SDA func-
2
DPD (Pin 10): Data Transceiver Positive Input Output
(Digital). Connect to DPA through a data transformer.
tion to simplify opto isolation of the I C bus. To imple-
ment a standard bidirectional SDA pin, tie SDAOUT and
SDAIN together. See Applications Information for more
information.
DND (Pin 11): Data Transceiver Negative Input Output
(Digital). Connect to DNA through a data transformer.
SDAIN (Pin 17): Serial Data Input. High impedance data
VDD (Pins 12, 19, 24): VDD IO Power Supply. Connect
2
input for the I C serial interface bus. The LTC9101-1 uses
to a 3.3V power supply relative to DGND. Each V pin
DD
two pins to implement the bidirectional SDA function to
must be locally bypassed with at least a 0.1µF capacitor.
2
simplify opto isolation of the I C bus. To implement a stan-
A 10µF bulk capacitor must be connected across V for
DD
dard bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
increased surge immunity.
4PVALID (Pin 13): 4-Pair Valid Input, Active Low. When
low, the LTC9101-1/LTC9102/LTC9103 will not apply
power to a port unless both pairsets present a valid signa-
ture. When high, the LTC9101-1/LTC9102/LTC9103 will
power any pairset presenting a valid signature, regard-
less of the other pairset. Ports in 2-pair or AT mode are
unaffected by 4-Pair Valid setting. Internally pulled down
to DGND. 4PVALID pin is ignored when a custom con-
figuration package is present. See Stored Configurations
for details.
SCL (Pin 18): Serial Clock Input. High impedance clock
2
input for the I C serial interface bus. The SCL pin should
2
be connected directly to the I C SCL bus line. SCL must
2
be tied high if the I C serial interface bus is not used.
Rev. 0
14
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
PIN FUNCTIONS
AUTO (Pin 20): Auto Mode Input, Active High. Auto mode
allows the LTC9101-1 to detect, classify, and power up
valid PDs without host interaction. AUTO determines the
state of the internal registers when the LTC9101-1 is
reset or comes out of UVLO (see LTC9101-1 Software
Programming documentation). See Auto Mode Maximum
PSE Power for details. The state of these register bits can
PWRIN (Pin 55): Startup Regulator Bypass and External
Low Voltage Supply Input. Power for the internal 4.3V
and 3.3V internal supplies. An internal regulator maintains
the voltage of this pin above 6V. An external resistor or
supply may be connected to this node to improve the
power efficiency of the LTC9102/LTC9103. Connect a 1µF
capacitor between this pin and V .
EE
2
subsequently be changed via the I C interface. Internally
AGND (Pin 56): Analog Ground.
pulled down to DGND. The AUTO pin is ignored when
a custom configuration package is present. See Stored
Configurations for details.
PWRMD[1:0] (Pins 57, 58 Respectively): Maximum
Power Mode Input. Connect PWRMD0 of the LTC9102/
LTC9103 with ID[1:0] = 00b to VEE with configuration
MSD (Pin 21): Maskable Shutdown Input, Active Low.
When pulled low, all ports that have their corresponding
mask bit set in the mconf register (0x17) will be reset.
Internal filtering of MSD prevents glitches less than 1µs
wide from resetting ports. The MSD Pin Mode register
resistor R
. When the LTC9101-1 is reset with AUTO
PWRMD
PWRMD
pin high, R
selects initial maximum power alloca-
tion values for every port in the chipset; the system power
supply must be sized to support all ports outputting up to
R . When auto mode is enabled, the chipset runs
PWRMD
can configure MSD polarity. Internally pulled up to V .
DD
independently as a PoE PSE. The chipset will detect and
class all ports and grant power to each port up to R
DGND (Pins 22, 25): Digital Ground. DGND should be
connected to the return from the V supply.
PWRMD
DD
setting. The PWRMD0 pin of LTC9102/LTC9103s with ID
pins set to 01b, 10b, and 11b must be left floating. The
PWRMD1 pin of all LTC9102/LTC9103s must be left float-
LTC9102/LTC9103 COMMON
ing. See Auto Mode Maximum PSE Power for R
PWRMD
CAP3 (Pin 1): Analog Internal 3.3V Power Supply Bypass
Capacitor. Connect a 1μF ceramic cap to VEE. A 3.3V power
supply may be connected to this pin to improve power
supply efficiency. The EXT3 pin must be pulled to CAP3
to shut off the internal 3.3V regulator if power is supplied
externally. Do not source or sink current from this pin. Do
not connect to CAP3 except as explicitly instructed in ADI
documentation (e.g., strapping LTC9102/LTC9103 pins
and terminating the serial interface).
options and details. The PWRMD pins are ignored when
a custom configuration package is present. See Stored
Configurations for details.
CAP4 (Pin 59): Analog Internal 4.3V Power Supply
Bypass Capacitor. Connect a 1μF ceramic cap to V . Do
EE
not source or sink current from this pin.
V
(Pins 60, 65): Main PoE Supply Input. Connect to a
EE
–51V to –57V supply, relative to AGND. Voltage depends
EXT3 (Pin 2): External 3.3V Enable. Connect the EXT3
on PSE Type (Type 3 or 4).
pin to CAP3 to shut off the internal 3.3V regulator when
DNA (Pin 61): Data Transceiver Negative Input Output
(Analog). Connect to DND through a data transformer.
power is supplied externally. Float or connect to V for
EE
internal regulator operation.
DPA (Pin 62): Data Transceiver Positive Input Output
ID[1:0] (Pins 52, 51 respectively): Transceiver ID. Sets
the address of the LTC9102/LTC9103 on the multidrop
high-speed data interface. ID numbering must start at
00b. Tie high by connecting to CAP3. Tie low by connect-
(Analog). Connect to DPD through a data transformer.
CNA (Pin 63): Clock Transceiver Negative Input Output
(Analog). Connect to CND through a data transformer.
ing to V . See Device Configuration section for details.
EE
CPA (Pin 64): Clock Transceiver Positive Input Output
(Analog). Connect to CPD through a data transformer.
Rev. 0
15
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
PIN FUNCTIONS
LTC9102 EXCLUSIVE
GATE[12:1] (Pins 50, 43, 42, 35, 34, 27, 26, 19, 18,
11, 10, 3 Respectively): Gate Drive, channel n. Connect
GATEn to the gate of the external MOSFET for channel n.
When the MOSFET is turned on, the gate voltage is driven
VSSK[12:1] (Pins 47, 46, 39, 38, 31, 30, 23, 22, 15,
14, 7, 6 Respectively): Kelvin Sense to V . Connect to
EE
V
side of sense resistor for channel n through a 0.1Ω
EE
to 12V (typ) above V . During a current limit condition,
EE
resistor. Do not connect directly to V plane. See Kelvin
EE
the voltage at GATEn will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATEn is pulled down, turning the MOSFET off
and raising a port fault event. If the channel is unused,
the GATEn pin must float.
Sense layout requirements.
SENSE[12:1] (Pins 48, 45, 40, 37, 32, 29, 24, 21, 16,
13, 8, 5 Respectively): Current Sense Input, channel n.
SENSEn monitors the external MOSFET current via a 0.1Ω
sense resistor between SENSEn and VSSKn. If the voltage
across the sense resistor reaches the current limit thresh-
LTC9103 EXCLUSIVE
old I
, the GATEn pin voltage is lowered to maintain
LIM-2P
VSSK[8:1](Pins47, 46, 39, 38, 15, 14, 7, 6Respectively):
See LTC9102 VSSK[12:1].
constant current in the external MOSFET. See Applications
Information for further details. If the channel is unused,
tie SENSEn to V .
EE
SENSE[8:1] (Pins 48, 45, 40, 37, 16, 13, 8, 5
Respectively): See LTC9102 SENSE[12:1].
OUT[12:1] (Pins 49, 44, 41, 36, 33, 28, 25, 20, 17,
12, 9, 4 Respectively): Output Voltage Monitor, channel
n. Connect OUTn to the output channel. A current limit
foldback circuit limits the power dissipation in the external
MOSFET by reducing the current limit threshold when the
drain-to-source voltage exceeds 10V. A port power good
OUT[8:1] (Pins 49, 44, 41, 36, 17, 12, 9, 4 Respectively):
See LTC9102 OUT[12:1].
GATE[8:1] (Pins 50, 43, 42, 35, 18, 11, 10, 3
Respectively): See LTC9102 GATE[12:1].
event is raised when the voltage from OUTn to V drops
EE
below 2.4V (typ). A 500k resistor is connected internally
from OUTn to AGND when the channel is idle. If the chan-
nel is unused, the OUTn pin must float.
COMMON PINS
NC, DNC (LTC9101-1 Pin 4; LTC9102 Pins 53, 54;
LTC9103 Pins 19–34, 53, 54): All pins identified with
“NC” or “DNC” must be left unconnected.
Rev. 0
16
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
OVERVIEW
The LTC9101-1/LTC9102/LTC9103 delivers power over
one or two power channels when configured in 2-pair or
4-pair mode, respectively. Each pairset is driven by a dedi-
cated power channel. In this data sheet, the term “chan-
nel” refers to the PSE circuitry assigned to a correspond-
ing pairset. For the purposes of this document, the terms
channel and pairset may be considered interchangeable.
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE standard, known as 802.3af, allowed for 48V
DC power at up to 13W. 802.3af was widely popular, but
13W was not adequate for some applications. In 2009,
the IEEE released a new standard, known as 802.3at or
In addition, IEEE 802.3bt enables substantially lower
Maintain Power Signature (MPS) currents, resulting in
significantly lower standby power consumption. This
allows new and emerging government or industry standby
regulations to be met using standard PoE components.
+
PoE , increasing the voltage and current requirements
to provide 25.5W of delivered power. IEEE 802.3af and
802.3at are commonly known as PoE 1. In 2018, the IEEE
released the latest PoE standard, known as 802.3bt or
PoE 2. 802.3bt maximizes PD delivered power at 71.3W.
LTC9101-1/LTC9102/LTC9103 Product Overview
The LTC9101-1/LTC9102/LTC9103 is a sixth generation
PSE controller that implements up to 24 (71.3W) 4-pair
or 48 (25.5W) 2-pair PSE ports in either an endpoint or
midspan application. Virtually all necessary circuitry is
included to implement an IEEE 802.3bt compliant PSE
design, requiring a pair of external power MOSFETs and
sense resistors per port; these minimize power loss com-
pared to alternative designs with onboard MOSFETs, and
increase system reliability.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE,
or power sourcing equipment, while a device that draws
power from the network is known as a PD, or powered
device. PSEs come in two types: endpoints (typically net-
work switches or routers), which provide data and power;
and midspans, which provide power but pass through
data. Midspans are typically used to add PoE capabil-
ity to existing non-PoE networks. PDs are typically IP
phones, wireless access points, security cameras, and
similar devices.
The LTC9101-1/LTC9102/LTC9103 chipset implements
a proprietary isolation scheme for inter-chip commu-
nication. This architecture substantially reduces BOM
cost by replacing expensive opto-isolators and isolated
power supplies with a single low-cost transformer. A
single LTC9101-1 is capable of controlling a bus of up
to 4 LTC9102s/LTC9103s over this transformer-isolated
interface. Direct connection of the LTC9101-1 and the
associated LTC9102s/LTC9103s is also possible.
++
PoE Evolution
Even during the development of the IEEE 802.3at (PoE 1)
25.5W standard, it became clear there was a significant
and increasing need for more than 25.5W of delivered
power. In 2013, the 802.3bt task force was formed to
develop a standard capable of increasing delivered
PD power.
The LTC9101-1/LTC9102/LTC9103 offers configurable
interrupt signal triggered by per-port events, per-channel
power on control and fault telemetry, per-port current
The primary objective of the task force is to use all four
pairs of the Ethernet cable as opposed to the two pair
power utilized by 802.3at. Using all four pairs allows for
at least twice the delivered power over existing Ethernet
cables. Further, the amount of current per two pairs
(known as a pairset) has been increased while maintain-
ing the Ethernet data signal integrity. 802.3bt increases
PD delivered power from 25.5W to 71.3W, enabling IEEE-
compliant high power PD applications.
monitoring, V monitoring, and one second rolling cur-
EE
rent, voltage and port power averaging.
The LTC9101-1/LTC9102/LTC9103 also offers advanced
sixth-generation PSE features including internal eFlash for
storage of firmware updates and custom user configura-
tion packages, 2-pair operation in 802.3at-compliant or
2
802.3bt-compliant mode, I C quad virtualization for full
Rev. 0
17
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
backwards-compatibility with LTC4291 drivers, ultralow
100mΩ sense resistors, +80V/–20V tolerant port-facing
pins, and improvements to cable surge ride through.
In LTC9101-1 2-pair mode, exactly one LTC9102/LTC9103
channel is associated with each port in a quad. As such it
is required that the LTC9102/LTC9103 power channel is
connected to either Alternative A or Alternative B of the
associated RJ45 connector. (See Figure 10)
Each LTC9102/LTC9103 power channel is implemented
with dedicated detection and classification hardware. This
allows all ports and channels to detect, classify and power
on simultaneously, drastically reducing power on latency
across a switch. Other less advanced PSEs are subject to
visible delays as PDs, e.g. LED lights, power on a port-
by-port basis.
In 2-pair mode the IEEE 802.3bt standard limits delivered
power to 25.5W and supports PD Classes 0 to 4.
In LTC9101-1 4-pair mode, two LTC9102/LTC9103 chan-
nels are associated with each port. As such it is required
that power channels are connected to Alternative A and
Alternative B, respectively (see Figure 11). In 4-pair mode
the host is responsible for deciding if both power channels
will be utilized to power a given PD. Thus 2-pair powering
in 4-pair mode can be used to power single-signature
Class 0 to 4 PDs. For higher power Class 5 to 8 PDs and
for all dual-signature PDs, both power channels must be
utilized, also referred to as 4-pair power (see Figure 12).
VEE and port current measurements are performed simul-
taneously, enabling coherent and precise per-port power
monitoring.
2-PAIR VS 4-PAIR MODE
The LTC9101-1 includes up to 12 groups of four identical
ports. Each group of four ports is referred to as a quad. In
the LTC9101-1 architecture, each quad contains register
configuration and status for exactly four ports, regardless
of whether the ports are in 2-pair mode or 4-pair mode.
In 4-pair mode the IEEE 802.3bt standard supports delivered
power to 71.3W, supporting all existing single-signature PD
Classes 0 to 8 and dual-signature PD Classes 1 to 5.
Mixes of 2-pair and 4-pair quads are available using a con-
figuration package. See Stored Configurations for details.
1
1
TX1
TX1
AGND
2
2
DATA PAIRS
3
3
GATEn
2
TX2
–55V
TX2
I C
+
OUT
–
6
6
V
PD
4
4
LTC9101-1/
LTC9102/LTC9103
TX3
TX3
5
5
DATA PAIRS
7
7
TX4
TX4
8
8
V
EE
1000BASE-T
1000BASE-T
RJ45
RJ45
9101123 F10
–55V
Figure 10. 2-Pair, Alternative A (Endpoint), Power over Ethernet Single-Signature PD System Diagram
Rev. 0
18
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
802.3at Mode
PoE BASICS
The LTC9101-1/LTC9102/LTC9103 may be configured as
a 2-pair (802.3at or 802.3bt) or 4-pair 802.3bt PSE. All
802.3bt-compliant PSEs are fully backwards compatible
with existing 802.3at Type 1 and Type 2 PDs as shown
in Table 1. In addition to full compatibility, 802.3bt PSEs
extend support for lower standby power, enhanced cur-
rent limit timing, and dynamic power management to all
PD Types (as supported by the PD application).
Common Ethernet data connections consist of two or
four twisted pairs of copper wire (commonly known
as Ethernet cable), transformer-coupled at each end to
avoid ground loops. PoE systems take advantage of this
coupling arrangement by applying voltage between the
center-taps of the data transformers to transmit power
from the PSE to the PD without affecting data transmis-
sion. Figure 11 and Figure 12 show high level PoE system
schematics.
Table 1. PSE Maximum Delivered Power, Per-Port
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE standard defines a
protocol that determines when the PSE may apply and
remove power. Valid PDs are required to have a specific
25k common-mode resistance at their input. When such
a PD is connected to the cable, the PSE detects this sig-
nature resistance and applies power. When the PD is
later disconnected, the PSE senses the open circuit and
removes power. The PSE also removes power in the event
of a current fault or short circuit.
DEVICE
PSE
STANDARD
802.3at
802.3bt
TYPE
1
2
3
4
1
2
3
4
13W
13W
13W
13W
802.3at
802.3bt
13W*
25.5W 25.5W
51W
13W* 25.5W* 51W*
25.5W
51W
PD
13W* 25.5W*
71.3W
*Indicates PD allocated less power than requested.
The LTC9101-1 supports operation as an 802.3at com-
pliant PSE. This feature is available in both 2-pair and
4-pair modes.
When a PD is detected, the PSE looks for a classification
signature that tells the PSE the maximum power the PD
will draw. The PSE can use this information to allocate
power among several ports, to police the current con-
sumption of the PD, or to reject a PD that will draw more
power than the PSE has available.
Note that an 802.3at PSE will not pass an 802.3bt PSE
compliance test, and an 802.3bt PSE will not pass an
802.3at PSE compliance test. This is by design of the
respective standards. 802.3at and 802.3bt devices are
designed to be interoperable.
New in 802.3bt
Table 2. 802.3at vs 802.3bt Features
The 802.3bt specification introduces several new features:
FEATURE
802.3at
802.3bt
Long
Yes
n
Type 3 and Type 4 PSEs may provide power over all
First Class Event
Short
four pairs (both pairsets), depending on connected PD
characteristics.
First Mark Event (15W Mode) No
Limit Timer
No (Uses Cutoff Timer) Yes
n
Connection Check
Active Alternative(s)
No
A
Yes
Type 3 and Type 4 PDs are required to be capable of
2-Pair: A
4-Pair: A and B
receiving power over all four pairs (both pairsets).
n
Type 3 and 4 PDs can be formed as either a single-
Maximum Class Events
2
5
signature PD or dual-signature PD. A single-signature
PD presents the same valid signature resistor to both
pairsets simultaneously (see Figure 11). A dual-signa-
ture PD presents two fully independent valid detection
signatures, one to each pairset (see Figure 12).
Maximum Available Power
Class 4
2-Pair: Class 4
4-Pair: Class 8
Short MPS
Autoclass
No
No
Yes
Yes
Rev. 0
19
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
1
1
TX1
TX1
AGND
2
2
DATA PAIRS
3
3
GATEn
2
TX2
TX2
I C
–55V
+
OUT
–
6
6
V
PD
4
4
LTC9101-1/
LTC9102/LTC9103
TX3
TX3
5
5
DATA PAIRS
7
7
GATEn+1
TX4
TX4
–55V
8
8
V
EE
1000BASE-T
1000BASE-T
RJ45
RJ45
9101123 F11
–55V
Figure 11. 4-Pair Power over Ethernet Single-Signature PD System Diagram
1
1
+
TX1
TX1
AGND
V
OUT
PD1
2
2
–
DATA PAIRS
3
3
GATEn
2
TX2
TX2
I C
–55V
6
6
4
4
LTC9101-1/
LTC9102/LTC9103
TX3
TX3
+
OUT
–
V
PD2
5
5
DATA PAIRS
7
7
GATEn+1
TX4
TX4
–55V
8
8
V
EE
1000BASE-T
1000BASE-T
RJ45
RJ45
9101123 F12
–55V
Figure 12. 4-Pair Power over Ethernet Dual-Signature PD System Diagram
Rev. 0
20
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
n
Type 3 single-signature PDs request exactly one of six
Table 3. IEEE-Specified Power Allocations, Single-Signature PD
possible power levels: 3.84W, 6.49W, 13W, 25.5W,
40W, or 51W.
PSE OUTPUT
POWER
ALLOCATED
PD INPUT
POWER
PD CLASS
CABLING LOSS
1
2
3
4
5
6
7
8
4W
6.7W
14W
30W
45W
60W
75W
90W
0.16W
0.21W
1W
3.84W
6.49W
13W
n
Type 3 dual-signature PDs request exactly one of four
possible power levels on each pairset: 3.84W, 6.49W,
13W, or 25.5W. The total PD requested power is the
sum of the requested power on both pairsets.
4.5W
5W
25.5W
40W
n
Type 3 PD Classes overlap with Type 1 and 2 Classes in
order to provide additional Type 3 feature sets at lower
power levels.
9W
51W
13W
18.7W
62W
71.3W
n
Type 4 single-signature PDs request exactly one of two
possible power levels: 62W or 71.3W.
REGISTER MAP BACKWARD COMPATIBILITY
n
Type 4 dual-signature PDs request exactly 35.6W on at
Software register map compatibility with LTC4266,
LTC4271 and LTC4291-based PSEs has been maintained
to the extent possible. LTC4291-based PSEs utilize two
channels to control a single PSE port. LTC9101-based
PSEs can be configured to utilize either a single power
channel, delivering up to 25.5W, or as two channels,
delivering up to 71.3W.
least one pairset and one of five possible power levels
on the other pairset: 3.84W, 6.49W, 13W, 25.5W, or
35.6W. The total PD requested power is the sum of the
requested power on both pairsets.
n
Classification is extended to a possible maximum of
five class events. The additional events allow for unique
identification of existing and new PD Classes.
For register map details please contact Analog Devices
to request the LTC9101-1 Software Programming
documentation.
n
Type 3 and 4 PSEs issue a long first class event to
advertise Type 3 and 4 feature support to attached PDs.
n
Lower standby power is enabled by shortening the
Special Compatibility Mode Notes
length of the maintain power signature pulse (short
MPS). The PD duty cycle drops from ~23% to ~2%. A
PD is allowed to present short MPS if the PSE issues
a long first class event.
2
n
As with prior generations, each I C address provides
status and control for four PoE ports.
n
In 4-pair mode, each port register slice provides port
control and status as well as channel A vs B control
and status.
n
Power management is augmented by Autoclass, an
optional feature for 802.3bt PSEs and PDs. In an
Autoclass system the maximum PD power is mea-
sured and reported to the PSE host, enabling the PSE
to reclaim output power not used by the PD appli-
cation and losses in the Ethernet cabling (Table 3).
See Autoclass section and LTC9101-1 Software
Programming documentation for details.
n
In 2-pair mode, each port register slice provides port
control and status via channel A control and status.
In this mode channel B control and status fields
are ignored.
n
Certain status registers, e.g. Port Status and Power
Status, relate to a channel state, as opposed to port
state and are split into three copies; a generalized port
state, channel A state and channel B state.
n
Certain command registers, e.g., Power-on pushbutton,
likewise are bifurcated to allow per-channel control.
Rev. 0
21
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
DEVICE CONFIGURATION
combination of 2-pair or 4-pair quads by storing a cus-
tom configuration package. See Stored Configurations
for details.
An LTC9101-1 can control between one and four
LTC9102/LTC9103. Each LTC9102 controls 12 power
channels while each LTC9103 controls 8 channels. Thus,
each LTC9101-1 can control up to 48 power channels
configured in either 2-pair or 4-pair mode.
As described later in Bus Addressing, each group of four
2
ports occupies a single I C address, regardless of 2-pair
(2P) or 4-pair (4P) configuration. Using the CFG pins and
a default configuration package, a LTC9101-1 can control
either all 2-pair ports or can control all 4-pair ports (see
Table 4).
Large port count switch implementation may require a mix
of 2-pair (25.5W) ports and 4-pair (up to 71.3W) ports.
LTC9101-1 channels may be configured in an arbitrary
Table 4. Device Configuration Options
2
DEVICE COUNT
NUMBER OF PORTS
I C ADDRESS OFFSET
CFG [2:0] LTC9102 LTC9103 4P
2P
12
8
TOTAL
12
8
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
0
1
2
2
2
3
3
4
4
4
4
5
5
6
6
6
6
6
7
7
7
000
000
001
010
010
010
011
011
100
100
100
100
101
101
110
110
110
110
110
111
111
111
1
0
0
2
1
0
2
0
3
2
1
0
2
0
4
3
2
1
0
4
2
0
0
1
1
0
1
2
0
2
0
1
2
3
1
3
0
1
2
3
4
0
2
4
0
0
2P 2P 2P
2P 2P
4
0
4
4P
0
24
20
16
0
24
20
16
12
8
2P 2P 2P
2P 2P 2P
2P 2P 2P
4P 4P 4P
4P 4P
2P 2P 2P
2P 2P
2P
0
0
12
8
0
0
36
32
28
24
0
36
32
28
24
16
12
48
44
40
36
32
24
20
16
2P 2P 2P
2P 2P 2P
2P 2P 2P
2P 2P 2P
4P 4P 4P
4P 4P 4P
2P 2P 2P
2P 2P 2P
2P 2P 2P
2P 2P 2P
2P 2P 2P
4P 4P 4P
4P 4P 4P
4P 4P 4P
2P 2P 2P
2P 2P 2P
2P 2P 2P
2P 2P 2P
4P
2P 2P 2P
2P 2P
2P
0
0
0
16
12
0
0
48
44
40
36
32
0
2P 2P 2P
2P 2P 2P
2P 2P 2P
2P 2P 2P
2P 2P 2P
4P 4P 4P
4P 4P
2P 2P 2P
2P 2P 2P
2P 2P 2P
2P 2P 2P
2P 2P
2P 2P 2P
2P 2P
2P
0
0
0
0
24
20
16
0
0
4P
Rev. 0
22
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
OPERATING MODES
In shutdown mode the port is disabled and will not detect
or power a PD.
The LTC9101-1/LTC9102/LTC9103 includes up to 48
independent ports, each of which can operate in one of
three modes: manual, semi-auto, or auto. A fourth mode,
shutdown, disables the port (see Table 5).
Regardless of which mode it is in, the LTC9101-1/
LTC9102/LTC9103 will remove power automatically from
any port or channel, as appropriate, that generates a fault.
It will also automatically remove power from any port/
channel that generates a disconnect event if disconnect
detection is enabled. The host controller may also com-
mand the port to remove power at any time.
Table 5. Operating Modes
AUTOMATIC
AUTO
OPMD
DETECT/
THRESHOLD
POWER-UP ASSIGNMENT
MODE
PIN REGISTER CLASS
Enabled
1
0
0
11b
11b
10b
Automatically
Automatically
Yes
Yes
No
at Reset
Reset and the AUTO Pin
Auto
Host
Enabled
The initial LTC9101-1/LTC9102/LTC9103 configuration
depends on the state of AUTO during reset. Reset occurs
at power-up, whenever RESET is pulled low, or when the
global Reset All bit is set. Changing the state of AUTO
after power-up will not change the port behavior of the
LTC9101-1/LTC9102/LTC9103 until a reset occurs.
Host
Enabled
Upon
Request
Semi-Auto
Once
Upon
Upon
Manual
0
0
01b
00b
No
No
Request
Request
Shutdown
Disabled
Disabled
With AUTO high, each port will detect and classify repeat-
edly until a PD is discovered, set ICUT-2P, ILIM-2P, and
PCUT-4P according to the PSE assigned Class, apply
power to valid PDs, and remove power when a PD is
disconnected.
In manual mode, the port waits for instructions from the
host system before taking any action. It runs a single
detection, or detection and classification cycle when com-
manded to by the host, and reports the result in its Port
Status register. The host system can command the port
to apply or remove power at any time.
Table 6 and Table 7 show the I
, I
, and P
CUT-2P LIM-2P CUT-4P
values that will be automatically set in auto mode, based
on the PSE assigned Class.
In semi-auto mode, the port repeatedly attempts to detect
and classify any PD attached to it. It reports the status of
these attempts back to the host, and waits for a command
from the host before applying power to the port. The host
must enable detection and classification.
Table 6. Typical Auto Mode Power On Thresholds,
Single-Signature PD**
PER-CHANNEL
PER-PORT
PSE ASSIGNED
CLASS
I
I
P
CUT-4P
CUT-2P
LIM-2P
Auto mode operates the same as semi-auto mode except
it will automatically apply power to the port if detection
and classification are successful. Auto mode will autono-
1
2
3
4
5
6
7
8
94mA
150mA
338mA
638mA
581mA
731mA
825mA
975mA
425mA
425mA
425mA
850mA
850mA
850mA
1063mA
1167mA
4.86W
7.56W
16.2W
32.4W
48.1W
64.3W
80.5W
96.1W
mously set the I
, I
, and P
values based
CUT-2P LIM-2P
CUT-4P
on the Class result. This operational mode may be entered
by setting AUTO high at reset or by changing the OPMD
state to Auto (11b). See AUTO pin description and the
Auto Mode Maximum PSE Power section.
Rev. 0
23
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
Table 7. Typical Auto Mode Power On Thresholds,
Dual-Signature PD**
for the connected device to be categorized as a single-
signature PD, a dual-signature PD, or an invalid result.
PER-CHANNEL
PSE ASSIGNED
An invalid connection check result is reported when a
device is added or removed during connection check.
CLASS
I
I
P
*
CUT-2P
CUT-2P
LIM-2P
1
94mA
150mA
338mA
638mA
975mA
425mA
425mA
425mA
850mA
1167mA
4.86W
7.56W
16.2W
32.4W
48.1W
Connection check only affects operation in 4-pair mode.
In 4-pair mode a detection cycle always includes a con-
nection check unless the port is in AT mode. See Figure 1.
2
3
4
5
In 2-pair mode connection check is not enabled (intrinsi-
cally a 4-pair only operation) and all PDs are reported
as single-signature regardless of the PD’s actual
signature configuration.
*A per-port P
threshold holds the sum of P
for each
CUT-4P
CUT-2P
powered channel.
**R = 0.1Ω.
SENSE
CONNECTION CHECK
DETECTION
Connection Check Overview
Detection Overview
IEEE 802.3bt introduces a new detection subroutine known
as connection check. A connection check is required to
determine whether the attached PD is a single-signature
PD, a dual-signature PD or an invalid result.
To avoid damaging network devices that were not designed
to tolerate DC voltage, a PSE must determine whether the
connected device is a valid PD before applying power.
The IEEE 802.3 specification requires that a valid PD has
a common-mode resistance of 25k 5% at any channel
voltage below 10V. The PSE must accept resistances that
fall between 19k and 26.5k, and it must reject resistances
above 33k or below 15k (shaded regions in Figure 13).
The PSE may choose to accept or reject resistances in
the undefined areas between the must-accept and must-
reject ranges. In particular, the PSE must reject standard
computer Network Interface Cards (NICs), many of which
have 150Ω common-mode termination resistors that will
be damaged if power is applied to them (the black region
at the left of Figure 13).
In 802.3at, only one PD configuration was described;
this is known as a single-signature PD and is shown in
Figure 11. A single-signature PD presents the same 25k
detection resistor to both the pairsets in parallel.
New in 802.3bt is the dual-signature PD as shown
in Figure 12. A dual-signature PD presents two fully
independent 25k detection signature resistors, one to
each pairset.
The PD configuration (single or dual) determines how
the PD is managed during subsequent detection, classi-
fication and power on procedures. Throughout this data
sheet attention will be called to the different treatment of
single-signature and dual-signature PDs.
RESISTANCE 0Ω
10k
20k
30k
150Ω (NIC)
23.75k
26.25k
26.5k
PD
PSE
15k 19k
33k
429291 F13
Connection check is performed with two current measure-
ments, at the same forced voltage, on the first channel.
The second channel is tested for aggressor behavior by
introducing a forced current on the second channel during
the second measurement. Comparison of the two result-
ing current measurements on the first channel allows
Figure 13. IEEE 802.3 Signature Resistance Ranges
Rev. 0
24
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LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
Multipoint Detection
Table 8. Port Detection Status
MEASURED PD SIGNATURE
(TYPICAL)
The LTC9101-1/LTC9102/LTC9103 uses a multipoint
method to detect PDs. False-positive detections are min-
imized by checking for signature resistance with both
forced current and forced voltage measurements.
PORT DETECTION RESULT
Detect Status Unknown
Short Circuit
Incomplete or Not Yet Tested
V
< 1V
PD
R
PD
< 17k
R
SIG
Too Low
Initially, two test currents are forced onto the channel (via
the OUTn pin) and the resulting voltages are measured.
The detection circuitry subtracts the two V-I points to
determine the resistive slope while removing offset caused
by series diodes or leakage at the port (see Figure 14). If
the forced current detection yields a valid signature resis-
tance, two test voltages are then forced onto the channel
and the resulting currents are measured and subtracted.
Both methods must report valid resistances to report a
valid detection. PD signature resistances between 17k
and 29k (typically) are detected as valid and reported as
Detect Good in the corresponding Port Status register or
Channel Status register, as appropriate. Values outside
this range, including open and short circuits, are also
reported. If the channel measures less than 1V during
any forced current test, the detection cycle will abort and
Short Circuit will be reported. Table 8 and Table 9 show
the possible detection results.
17k < R < 29k
Detect Good, Single-Signature PD
Too High
PD
R
R
> 29k
> 50k
> 10V
R
SIG
PD
PD
PD
Open Circuit
V
Port Voltage Outside Detect Range
Connection Check Invalid
Refer to Channel Detect Results
Connection Check = INVALID
Connection Check = DUAL or
Channel Detection Results Differ
Table 9. Channel Detection Status
MEASURED PD SIGNATURE
(TYPICAL)
CHANNEL DETECTION RESULT
Incomplete or Not Yet Tested
Detect Status Unknown
Short Circuit
V
C
< 1V
PD
PD
> 2.7μF
< 17k
C
Too High
Too Low
PD
R
R
SIG
PD
17k < R < 29k
Detect Good, Dual-Signature PD
Too High
PD
R
R
> 29k
> 50k
> 10V
R
SIG
PD
PD
PD
Open Circuit
V
Channel Voltage Outside Detect Range
Connection Check Invalid
Refer to Port Detect Result
Detection is enabled in both 2-pair and 4-pair modes.
Detection is always performed on a per-channel basis.
Connection Check = INVALID
Connection Check = SINGLE or
Channel Detection Results Match
More on Operating Modes
240
FIRST
The port’s operating mode determines when the
LTC9101-1/LTC9102/LTC9103 runs a detection cycle. In
manual mode, the port will idle until the host orders a
detect cycle. It will then run detection, report the result,
and return to idle to wait for another command.
DETECTION
POINT
25kΩ SLOPE
160
SECOND
DETECTION
POINT
VALID PD
In semi-auto mode the LTC9101-1/LTC9102/LTC9103
autonomously polls a port for PDs, but it will not apply
power until commanded to do so by the host. The
Detection/Classification Status registers are updated at
the end of each detection/classification cycle.
0V–2V
OFFSET
VOLTAGE
9101123 F14
Figure 14. PD Detection
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In semi-auto mode, if a valid signature resistance is
detected and classification is enabled, the port will clas-
sify the PD and report that result as well. The port will then
wait for at least 100ms, and will repeat the detection cycle
to refresh the data in the Port Status registers.
CLASSIFICATION
802.3af Classification
A PD may optionally present a classification signature
to the PSE to indicate the maximum power it will draw
while operating. The IEEE specification defines this sig-
nature as a constant current draw when the PSE port
The port will not turn on in response to a power-on com-
mand unless the current detect result is Detect Valid. Any
other detect result will generate a tSTART fault if a power-on
command is received.
voltage is in the V
range (between 15.5V and 20.5V)
as shown in FiguCreLA1S6S, with the current level indicating
one of five possible PD signatures. Figure 15 shows a
typical PD load line, starting with the slope of the 25k
signature resistor below 10V, then transitioning to the
classification signature current (in this case, Class 3)
Behavior in Auto mode is similar to semi-auto; however,
after Detect Valid is reported and the port is classified, it
is automatically powered on without host intervention. In
auto mode the ICUT-2P, ILIM-2P, and PCUT-4P thresholds are
automatically set; see the Reset and the AUTO Pin section
for more information.
in the V
range. Table 10 shows the possible clas-
CLASS
sification values.
80
Detection is disabled for a port when the LTC9101-1/
LTC9102/LTC9103 is initially powered up with AUTO low,
when the port is in shutdown mode, or when the corre-
sponding Detect Enable bit is cleared.
PSE LOAD LINE
48mA
≈
≈
OVER
CURRENT
50
40
30
20
10
CLASS 4
CLASS 3
33mA
23mA
Detection of Legacy PDs
CLASS 2
Proprietary PDs that predate the original IEEE 802.3af stan-
dard are commonly referred to today as legacy PDs. One
type of legacy PD uses a large common-mode capacitance
(>10μF) as the detection signature. Note that PDs in this range
of capacitance are defined as invalid, so a PSE that pow-
ers legacy PDs is noncompliant with the IEEE standard. The
LTC9101-1/LTC9102/LTC9103 can be configured to detect
this type of legacy PD. Legacy detection is disabled by default,
but can be manually enabled on a per-port basis. When
enabled, the port will report Detect Good when it detects either
a valid IEEE PD or a high-capacitance legacy PD. With legacy
mode disabled, only valid IEEE PDs will be recognized.
TYPICAL
CLASS 3
PD LOAD
LINE
14.5mA
6.5mA
CLASS 1
CLASS 0
0
0
5
10
15
20
25
VOLTAGE (V
)
CLASS
9101123 F15
Figure 15. PD Classification
POWER ON
CLASS
V
V
CLASSMIN
If a nonstandard PD presents an invalid detection signa-
ture not included by legacy detection, the LTC9101-1/
LTC9102/LTC9103 may be configured to perform classi-
fication and/or apply power regardless of detection result.
To accomplish this, the LTC9101-1/LTC9102/LTC9103
introduces per-port Force Power and Class Event over-
rides. These overrides intentionally defeat compliance
MARKMAX
DETECT
V
RESET
V
SIGMIN
9101123 F16
Figure 16. Type 1 or 2 PSE, 1-Event Class Sequence
checks. See the LTC9101-1 Software Programming docu
-
mentation for details.
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Table 10. Type 1 and Type 2 PD Classification Values
A Type 2 PD requesting 25.5W presents class signature 4
during all class events. If a Type 2 PSE with 25.5W of
available power measures class signature 4 during the
CLASS
Class 0
Class 1
Class 2
Class 3
Class 4
RESULT
No Class Signature Present; Treat Like Class 3
3.84W
first class event, it forces the PD to V
(9V typical),
MARK
pauses briefly, and issues a second class event as shown
in Figure 17. The second class event informs the PD that
the PSE has allocated 25.5W.
6.49W
13W
25.5W (Type 2)
POWER ON
If classification is enabled, the PSE will classify the PD
immediately after a successful detection cycle. The PSE
measures the PD classification signature by applying
1ST
2ND
CLASS
CLASS
V
V
CLASSMIN
MARKMAX
V
to the port via OUTn and measuring the result-
CLASS
ing current; it then reports the discovered class in the
Port Status or Channel Status register, as appropriate. If
the LTC9101-1/LTC9102/LTC9103 is in auto mode, it will
DETECT
1ST
MARK
2ND
MARK
V
RESET
additionally use the classification result to set the I
,
CUT-2P
V
SIGMIN
I
, and P
thresholds.
LIM-2P
CUT-4P
9101123 F17
Classification is disabled for a port when the LTC9101-1/
LTC9102/LTC9103 is initially powered up with the AUTO
pin low, when the port is in shutdown mode, or when the
corresponding Class Enable bit is cleared.
Figure 17. Type 2 PSE, 2-Event Class Sequence
Note that the second classification event only runs if
required by the IEEE classification procedure. For exam-
ple, a single-signature Class 0 to 3 PD will only be issued
a single class event as shown in Figure 16.
LLDP Classification
Introduced in 802.3at and extended by 802.3bt, the PoE
specification defines a Link Layer Discovery Protocol
(LLDP) method of classification. The LLDP method adds
extra fields to the Ethernet LLDP data protocol.
The concept of demotion is introduced in 802.3at. A
Type 2 PD may be connected to a PSE only capable of
delivering 13W, perhaps due to power management limi-
tations. In this case, the PSE will perform a single classi-
fication event as shown in Figure 16, and note that 25.5W
is requested. Due to the limited power availability, the
PSE will not issue a second event and proceeds directly
to power on the PD. The presence of a single class event
informs the Type 2 PD it has been demoted to 13W. If
demoted, the PD is subject to power limitations and may
operate in a reduced power mode.
Although the LTC9101-1/LTC9102/LTC9103 is compat-
ible with this classification method, it cannot perform
LLDP classification directly since it does not have access
to the data path. LLDP classification allows the host to
perform LLDP communication with the PD and update the
PD’s power allocation. The LTC9101-1/LTC9102/LTC9103
supports changing the I
, I
, and P
levels
LIM-2P CUT-2P
dynamically, enabling system-level LLDP support.
CUT-4P
802.3bt Multi-Event Classification
The LTC9101-1/LTC9102/LTC9103 implements Type 3
and Type 4 classification as required by 802.3bt. Type 3
and Type 4 classification are backwards-compatible with
Type 1 and Type 2 PDs.
802.3at 2-Event Classification
In 802.3at, 802.3af classification is named Type 1 clas-
sification. The 802.3at standard introduces an extension
of Type 1 classification: Type 2 (2-event) classification.
Type 2 PSEs are required to perform classification.
While Type 2 (802.3at) classification extends Type 1
(802.3af) classification, Type 3 and Type 4 (802.3bt)
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classification supersede Type 1 and Type 2 classifica-
tion. Type 1 and Type 2 classification are described in
the preceding sections as a historical reference and to
define common terminology such as power demotion,
class events, mark events, and electrical parameters.
from a higher Class SS PD. Power limited IEEE 802.3bt
PSEs may issue three classification events to Class 5 and
higher SS PDs in order to demote those PDs to 25.5W.
Type 3 and 4 PSEs present four classification events (see
Figure 20) to Class 5 and 6 SS PDs if sufficient power is
available. Class 5 and 6 SS PDs present class signature
4 on the first two events. Class 5 and 6 SS PDs present
class signature 0 or 1, respectively, on the subsequent
events. Power limited PSEs may issue four events to
Class 7 and 8 SS PDs in order to demote those PDs to
51W.
IEEE 802.3bt defines eight PD Classes for single-signature
PDs and five PD Classes for dual-signature PDs, as shown
in Table 11.
Classification treatment of single-signature and dual-
signature PDs differs. The following sections explain the
Physical Layer classification of each PD configuration
separately.
Type 4 PSEs present five classification events (see
Figure 21) to Class 7 and 8 SS PDs if sufficient power is
available. Class 7 and 8 PDs present class signature 4 on
the first two events. Class 7 and 8 SS PDs present class
signature 2 or 3, respectively, on the subsequent events.
Table 11. Type 3 and Type 4 PD Classifications by
PD Configuration
SINGLE-SIGNATURE PDs
DUAL-SIGNATURE PDs
PD AVAILABLE
CHANNEL AVAILABLE
*
CLASS
POWER
3.84W
6.49W
13W
CLASS
POWER
3.84W
6.49W
13W
802.3bt Classification of Dual-Signature PDs
Class 1
Class 2
Class 3
Class 4
Class 5
Class 6
Class 7
Class 8
Class 1
Class 2
Class 3
Class 4
Class 5
Classification and power allocations to each pairset of a
dual-signature (DS) PD are fully independent. For exam-
ple, a DS PD may request Class 1 (3.84W) on one pairset
and a Class 4 (25.5W) on the second pairset for a total
PD requested power of 29.3W. As such, all classification
is performed to the pairset entity as opposed to the PD.
The terms should be considered interchangeable for the
remainder of this section.
25.5W
40W
25.5W
35.6W
51W
62W
71.3W
*Dual-signature PD total available power is the sum of both channels
available power. Class signatures may differ between channels of a port,
e.g., Class 3 + Class 4 = 13W + 25.5W = 38.5W.
Type 3 and Type 4 PSEs issue three classification events
(see Figure 19) to all Class 1 through 4 DS PDs.
Power limited Type 3 and Type 4 PSEs may issue a class
reset to Class 4 and 5 DS PDs in order to demote those
PDs to 13W (see Understanding 4PID section).
802.3bt Classification of Single-Signature PDs
Type 3 and Type 4 PSEs issue a single classification event
(see Figure 18) to Class 0 through 3 single-signature (SS)
PDs. A Class 0 through 3 SS PD presents its class signa-
ture to the PSE and is then powered on if sufficient power
is available. Power limited 802.3bt PSEs may also issue a
single classification event to Class 4 and higher SS PDs in
order to demote those PDs to 13W. See Figure 18.
Power limited Type 3 and Type 4 PSEs may issue only
three events to Class 5 DS PDs in order to demote those
PDs to 25.5W.
Type 4 PSEs present four classification events (see
Figure 20) to Class 5 DS PDs if sufficient power is avail-
able. Class 5 DS PDs present class signature 4 on the first
two events and class signature 3 on subsequent events.
Type 3 and 4 PSEs present three classification events
to Class 4 SS PDs (see Figure 19) if sufficient power is
available. Class 4 SS PDs present class signature 4 on
all events. The third event differentiates a Class 4 SS PD
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APPLICATIONS INFORMATION
POWER ON
POWER ON
1ST
CLASS
1ST
2ND
3RD
CLASS
4TH
CLASS
CLASS CLASS
V
V
V
V
CLASSMIN
MARKMAX
CLASSMIN
MARKMAX
DETECT
DETECT
1ST
MARK
2ND
MARK
3RD
MARK
4TH
MARK
1ST
MARK
V
V
RESET
RESET
V
V
SIGMIN
SIGMIN
9101123 F18
9101123 F20
Figure 20. Type 3 or 4 PSE, 4-Event Class Sequence
Figure 18. Type 3 or 4 PSE, 1-Event Class Sequence
POWER ON
POWER ON
1ST
CLASS
2ND
CLASS
3RD
CLASS
1ST
CLASS
2ND
CLASS
3RD
CLASS
4TH
5TH
CLASS CLASS
V
V
CLASSMIN
MARKMAX
V
V
CLASSMIN
MARKMAX
DETECT
DETECT
1ST
MARK
2ND
MARK
3RD
MARK
V
RESET
1ST
MARK
2ND
MARK
3RD
MARK
4TH
MARK
5TH
MARK
V
RESET
V
SIGMIN
9101123 F19
V
SIGMIN
9101123 F21
Figure 21. Type 4 PSE, 5-Event Class Sequence
Figure 19. Type 3 or 4 PSE, 3-Event Class Sequence
Understanding 4PID
identify such a PD as single-signature or dual-signature.
Single-signature PDs may receive 4-pair power regardless
of PD Type. Certain pre-802.3bt “dual-signature” PDs may
be damaged by 4-pair power.
4-pair identification (4PID) refers to a set of conditions for
determining whether a PD is capable of receiving power
over both pairsets simultaneously.
Type 3 and Type 4 dual-signature PDs are required to
present a unique classification response from pre-802.3bt
dual-signature PDs of the same Class. For dual-signature
PDs, the LTC9101-1/LTC9102/LTC9103 determines and
reports both PD Class and PD Type during classification.
The PSE may apply 4-pair power if the PD presents a valid
detection signature on both pairsets and one or more of
the following conditions are met:
• The port is in 4-pair mode.
• The PD is single-signature configuration.
• The PD is Type 3 or Type 4.
Type 3, Type 4, and pre-802.3bt Class 1 through Class 4
dual-signature PDs present class signature 1 through 4,
respectively, during the first and second class events.
Type 3 and Type 4 dual-signature PDs present class sig-
nature 0 for all subsequent class events. Thus, a PSE can
conclusively determine PD Type by the third class event
for all dual-signature PDs.
• The PD presents a valid detection signature on an
unpowered pairset when power is applied over the
other pairset.
Although PD signature configuration is not defined for
Type 1 and Type 2 PDs, a Type 3 or Type 4 PSE may
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Class Reset
Any individual class signature that exceeds the class cur-
rent limit is flagged as an invalid classification result. Any
sequence of class signatures that does not represent a
legal sequence based on PD configuration will likewise
be flagged as an invalid classification result.
An issue arises when a Class 4 or Class 5 dual-signature
PD is connected. In order to determine PD Type, three
class events are issued. Based on the class event count,
the PD has been allocated 25.5W. If the PSE desires to
both determine PD Type (3 events) and demote to 13W
(1 event), a class reset event must be issued as shown
in Figure 22.
Auto Mode Maximum PSE Power
In auto mode the LTC9101-1/LTC9102/LTC9103 auto-
matically detects, classifies and powers all connected
valid PDs. In order to do this, each port must be config-
ured for its maximum power allocation. Select the resistor
RPWRMD from Table 12 that reflects each port’s maximum
power delivery capability.
POWER ON
1ST
2ND
3RD
1ST
CLASS CLASS
CLASS CLASS
V
V
CLASSMIN
MARKMAX
Connect the PWRMD0 pin of the LTC9102/LTC9103 at ID
address 00b to V through R
. The PWRMD0 pin
PWRMD
EE
DETECT
of the LTC9102/LTC9103 at ID address 01b, 10b, and 11b
must be left floating. The PWRMD1 pin of each LTC9102/
LTC9103 must be left floating. The PWRMD resistor is
measured at reset.
1ST
MARK
2ND
MARK
1ST
V
RESET
MARK
CLASS
RESET
9101123 F22
Figure 22. Class Reset Event Between Class Sequences
The maximum power allocation is a reflection of the power
supply and power path capability. The PWRMD resistor
setting is applied to every port in this chipset, across all
quads and ICs. Accordingly, the PWRMD resistor must be
set with consideration for each port’s power path capabil-
ity and for the system’s power supply capability.
A class reset event is issued by maintaining the channel
voltage below 2.8V for at least t
. The subse-
CLASS_RESET
quent single event classification is used to demote the
PD to 13W.
In auto mode the 4PID information and the state of
4PVALID are used to automatically determine the number
of powered channels.
When AUTO is low the PWRMD0 pin setting is ignored.
Table 12. Auto Mode Maximum Delivered Power Capabilities
2-PAIR MODE
4-PAIR MODE
MAX PORT POWER MAX PORT POWER
SINGLE-SIGNATURE PD DUAL-SIGNATURE PD
LLDP signaling may, at some time later, determine the
pre-bt PD is actually four pair capable and the LTC9101-1/
LTC9102/LTC9103 may be instructed to deliver 4-pair
power.
MAX PORT
POWER
*
RPWRMD
Open
Class 3: 13.0W
Class 3: 13.0W
Class 3: 13.0W
24.3k
18.7k
14.3k
Class 4: 25.5W
Class 4: 25.5W
Invalid Multi-Event Classification Combinations
Class 5: 40.0W
Class 6: 51.0W
Class 7: 62.0W
Class 8: 71.3W
Class 3: 13.0W
Class 4: 25.5W
Class 4: 25.5W
Class 5: 40.0W
The 802.3bt specification defines a set of valid class sig-
nature combinations. All PDs return the same classifica-
tion signature on the first two class events. Type 3 and 4
PDs modify the classification signature on all subsequent
class events. For example, a single-signature Class 5 PD
will respond to the class events 1, 2, 3, and 4 with a class
signature of 4, 4, 0, and 0, respectively.
11.0k Class 4: 25.5W
8.45k
6.49k
*In auto mode, total port power allocation is double this value, reflecting
the two halves of a dual-signature PD.
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POWER CONTROL
below IINRUSH-2P, as appropriate per the PD configuration
and Class.
The primary function of the LTC9101-1/LTC9102/LTC9103
is to control power delivery to the PSE port. With the
LTC9101-1/LTC9102/LTC9103, a PSE port is composed
of either one or two power channels; each power channel
controls power delivery over a pairset. Within this section,
operation of 4-pair configured ports is defined per chan-
nel. When configured for 2-pair operation, only a single
power channel is present per port.
If inrush is not successful, power is removed and the
corresponding t
faults are set. Otherwise, the port
START
or channel, as appropriate, advances to power on and
the programmed current limiting thresholds are used as
described in the Current Cutoff and Limit section.
Port Power Policing
The power policing threshold (P
) is monitored on a
The LTC9101-1/LTC9102/LTC9103 delivers power by
controlling the gate drive voltage of an external power
MOSFET while monitoring the current (through an exter-
nal sense resistor) and the output voltage (across the
OUT pin).
CUT-4P
per-port basis, up to 128W in 0.5W increments (typical).
When the total output power over a one second mov-
ing average exceeds the specified threshold, power is
removed from the port and the corresponding t
are set.
faults
CUT
The LTC9101-1/LTC9102/LTC9103 connects the VEE
power supply to the PSE port in a controlled manner,
meeting the power demands of the PD while minimizing
power dissipation in the external MOSFET and distur-
In particular, the port policing feature may be used to
ensure delivery of PD Class power while staying below
100W Limited Power Source (LPS) requirements.
bances to the V backplane.
EE
Current Cutoff and Limit
Inrush Control
Each LTC9101-1/LTC9102/LTC9103 port includes two
current limiting thresholds (ICUT-2P and ILIM-2P), each with
When commanded to apply power to a port, the
LTC9101-1/LTC9102/LTC9103 ramps up the GATE pin
of one or both channels (as commanded), raising the
external MOSFET gate voltage in a controlled manner.
a corresponding timer (t
and t ). Setting the I
CUT
LIM CUT-2P
and ILIM-2P thresholds depends on several factors: the PD
assigned Class, the main supply voltage (V ), the PSE
EE
Type (Type 3 or 4), and the MOSFET SOA.
During a typical inrush, the MOSFET gate voltage will rise
until the external MOSFET is fully enhanced or the channel
A single set of programmable port ICUT-2P and ILIM-2P
thresholds is shared by both channels. The thresholds
should be set based on the classification result as shown
in Table 6 and Table 7. For a dual-signature PD assigned
unequal Classes, the highest Class is used to set the
thresholds. For example, a dual-signature PD assigned
reaches the inrush current limit (I
). I
is
set automatically by the PSE. When the PSEINisRUapSHp-l2yPing
INRUSH-2P
4-pair power to a single-signature PD assigned Class 0
to Class 4, I
Otherwise, I
is 212.5mA (typical) per channel.
is 425mA (typical) per channel.
INRUSH-2P
INRUSH-2P
Class 1 and Class 5 would enforce I
based on Class 5.
and I
CUT-2P
LIM-2P
The GATE pin will be servoed if channel current exceeds
I , actively limiting current to I
INRUSH-2P
. When
INRUSH-2P
Per the IEEE specification, the LTC9101-1/LTC9102/
the GATE pin is not being servoed, the final V is 12V
GS
LTC9103 will allow the channel current to exceed I
(typical).
CUT-2P
for a limited period of time before removing power from
the port, or channel, as appropriate whereas it will actively
control the MOSFET gate drive to keep the channel cur-
During inrush, each powered channel runs a timer (tSTART).
Each powered channel stays in inrush until t
expires.
When t
expires, the PSE inspects chSaTnAnReTl voltage
START
rent below I
. The channel does not take any action
to limit the LcIMur-r2ePnt when only the ICUT-2P threshold is
exceeded, but does start the tCUT timer. If the current
and current. When the PSE is applying power to a PD,
inrush is successful if the channel(s) are drawing current
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drops below the ICUT-2P threshold before its timer expires,
dissipation at safe levels. Current limit and foldback
behavior are programmable on a per-port basis.
the t
timer counts back down, but at 1/16 the rate that
it coCuUnTts up. If the tCUT timer reaches 65ms (typical),
the port or channel, as appropriate, is turned off and the
corresponding tCUT faults are set. This allows the channel
to tolerate intermittent overload signals with duty cycles
below about 6%; longer duty cycle overloads will remove
power from the port or channel, as appropriate.
The LTC9101-1/LTC9102/LTC9103 supports current
levels well beyond the maximum values in the 802.3bt
specification. Large values of I
may require larger
LIM-2P
external MOSFETs, additional heat sinking, and setting the
Timer Configuration field to a lower value.
t
LIM
MOSFET Fault Detection
The I
current limiting circuit is always enabled and
LIM-2P
actively limiting channel current. The tLIM timer is enabled
only when the t Timer Configuration field is set to a
non-zero value. This allows tLIM to be set to a shorter value
than tCUT to provide more aggressive MOSFET protection
and turn off a port before MOSFET damage can occur. The
LTC9101-1/LTC9102/LTC9103 PSE ports are designed to
tolerate significant levels of abuse, but in extreme cases
it is possible for an external MOSFET to be damaged.
A failed MOSFET may short source to drain, which will
make the port appear to be on when it should be off; this
condition may also cause the sense resistor to fuse open,
turning off the port but causing SENSE to rise to an abnor-
mally high voltage. A failed MOSFET may also short from
gate to drain, causing GATE to rise to an abnormally high
voltage. OUT, SENSE and GATE are designed to tolerate
up to 80V faults without damage.
LIM
t
timer starts when the I
threshold is exceeded.
LIM
When the tLIM timer reachLeIsM1-2.P9ms (typical) times the
value in the t
Timer Configuration field, the port or
LIM
channel, as appropriate, is turned off and the appropriate
tLIM faults are set. When the tLIM Timer Configuration
field is set to 0, t
behaviors are tracked by the t
LIM
CUT
and I
CUT-2P
timer, which counts up during both I
LIM-2P
If the LTC9101-1/LTC9102/LTC9103 detects any of these
conditions for more than 3.8ms, it disables all port func-
tionality, reduces the gate drive pull-down current for
the port and reports a FET Bad fault. This is typically a
permanent fault, but the host can attempt to recover by
resetting the port, or by resetting the entire chip if a port
reset fails to clear the fault. If the MOSFET is in fact bad,
the fault will quickly return, and the port will disable itself
again. The remaining ports of the LTC9101-1/LTC9102/
LTC9103 are unaffected.
events. To maintain IEEE compliance, the programmed
Timer Configuration field should be set as shown in
t
LIM
the LTC9101-1 Software Programming documentation.
ICUT-2P is typically set to a lower value than ILIM-2P
,
allowing the port to tolerate minor faults without current
limiting.
To maintain IEEE compliance, I
should be set as
LIM-2P
shown in Table 6 and Table 7. The programmed I
LIM-2P
setting is automatically applied following the completion
of inrush.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a tSTART fault if the LTC9101-1/
LTC9102/LTC9103 attempts to turn on the port.
The t
and t timers are maintained on a per channel
LIM
CUT
basis. When a t
or t fault occurs a determination is
CUT
LIM
made to turn off one or both channels. See the Port Fault
vs Channel Fault section for details.
Disconnect
The LTC9101-1/LTC9102/LTC9103 monitors powered
channels to ensure the PD continues to draw the mini-
I
Foldback
LIM-2P
mum specified current. The I
threshold, monitored
The LTC9101-1/LTC9102/LTC9103 I
threshold is
threshold acHroOsLDs-t2hPe 0.1Ω sense resistor,
LIM-2P
as the V
implemented as a two-stage foldback circuit that reduces
the channel current if the channel voltage falls below the
normal operating voltage. This keeps MOSFET power
is used HtoOLdDe-t2ePrmine if a PD has been disconnected.
Rev. 0
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LTC9102/LTC9103
APPLICATIONS INFORMATION
The I
threshold is set automatically in auto mode
As the surge dissipates, the LTC9102/LTC9103 quickly
turns the MOSFET back on in a safe, current limited
manner while minimizing power disruption to the PD.
The LTC9102/LTC9103 fast MOSFET turn off and power
recovery better support both IEEE compliant PDs and PDs
with lower bulk capacitance in high reliability applications.
HOLD-2P
and is set by the user in semi-auto and manual modes.
When powering a single-signature PD assigned Class 0 to
Class 4 over a single channel, set the I
threshold
HOLD-2P
to 7.5mA (typ) via the Disconnect Configuration bit. In all
other cases, set the I threshold to 3.5mA (typ).
HOLD-2P
A disconnect timer (t ) counts up whenever channel
DIS
Port Fault vs Channel Fault
current is below the I
threshold, indicating that the
PD has been disconnHeOctLeDd-2.PIf the appropriate tDIS timer(s)
expire, the port or channel (Table 13) will be turned off
The t , t
and t timers are maintained on a per-
DIS
CUT LIM
channel basis. When any channel timer expires, a deter-
mination is made to remove power from both, one, or
neither channel of the port.
and the corresponding t faults are set. If the current
DIS
increases above I
before the t timer expires, the
HOLD-2P
DIS
timer(s) reset. As long as the PD exceeds the minimum
Optional behavior is allowed by the 802.3bt standard
when faults occur on single-signature PDs. This option
allows a single-signature PD to remain powered on pair-
set X, even if a fault occurs on pairset Y. The fault2Pn bit,
when set, enables this optional behavior. This behavior is
not recommended for normal operation, as a fault in the
PD or cabling is indicative of imminent PD or cable failure.
current level before t expires, it will remain powered.
DIS
Although not recommended, the DC disconnect fea-
ture can be disabled by clearing the corresponding DC
Disconnect Enable bits. Disabling the DC disconnect
feature forces the LTC9101-1/LTC9102/LTC9103 out of
compliance with the IEEE standard. A powered port will
stay powered after the PD is removed; the still-powered
port may be subsequently connected to a non-PoE data
device, potentially causing damage.
In 2-pair mode fault2Pn has no effect.
Table 13. Channel Fault Effect on Port/Channel State
FAULT RESULT:
The LTC9101-1/LTC9102/LTC9103 does not include AC
disconnect circuitry. AC disconnect is not a supported
feature of 802.3bt.
TURN OFF PORT OR CHANNEL
PD CON-
FIGURATION
fault2Pn
BIT
t
**
t
t
DIS
CUT
LIM
0
1
x
Port
Port
Single
Dual
Port*
Channel
Channel
Channel
Channel
Fast Surge Recovery
Channel
High reliability systems demand excellent surge recov-
ery. It is increasingly important for a PSE to minimize
power disruption to the PDs during extreme power tran-
sients. Furthermore, PDs that do not meet minimum bulk
capacitance requirements are particularly vulnerable to
power brownouts with traditional PSE solutions. The
LTC9101-1/LTC9102/LTC9103 provides an improved
hot swap responsiveness with excellent recovery from
surge events.
*If t Expires on Both Channels
DIS
**Port power policing (P
) raises a t
event. When enabled, port
CUT-4P
CUT
power policing removes power from the port regardless of fault2Pn
configuration.
Fault Telemetry
As discussed in the preceding sections, faults may occur
on one or both channels, resulting in power removal on
one or both channels. The fault event registers have tra-
ditionally been implemented at the port level. In order
to trace faults to the offending channel, a second layer
of fault registers have been added to the LTC9101-1/
During a surge event, the LTC9102/LTC9103 GATE pin
quickly turns off the external MOSFET current flow to
protect the PSE, the MOSFET, and downstream circuitry.
Rev. 0
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LTC9102/LTC9103: the Fault Telemetry registers. See
the LTC9101-1 Software Programming documentation
for additional information.
If an additional 13W PD is plugged into the fourth PSE
port, only 10W is available and the PD cannot be powered.
Figure 24 shows a 100W four port PSE servicing three
25.5W PDs over 10m cables. Such a system requires the
PSE to allocate 25.5W per PD and a further ~0.5W for
each 10m cable’s IR drop.
Autoclass
IEEE 802.3bt introduces a new optional feature, Autoclass.
Autoclass enables the PSE to reclaim power budget from
single-signature PDs requesting more power than needed
under worst-case operating conditions. 802.3bt does not
specify Autoclass for dual-signature PDs. The LTC9101-1/
LTC9102/LTC9103 fully supports Autoclass.
Without Autoclass, the total power allocation is:
3 ports • (4.5W + 25.5W) = 90W
13W PD
Prior versions of the 802.3 PoE standard specify mini-
mum PSE output power for worst-case IR drop across
the Ethernet cable and minimum PSE output voltage.
However, a method for the PSE to reclaim over-allocated
power is not specified. When a shorter Ethernet cable is
used, or when the guaranteed PSE output voltage is above
the specified minimum, the specified minimum PSE out-
put power substantially over-allocates power to the PD.
10m CABLE
~0.5W IR DROP
25.5W PD
100W PSE
10m CABLE
~0.5W IR DROP
25.5W PD
10m CABLE
~0.5W IR DROP
25.5W PD
9101123 F24
Figure 24. 100W PoE System with 10m Cables
An example PoE system is shown in two versions.
Figure 23 shows a 100W four port PSE servicing three
25.5W PDs over 100meter cables. Such a system requires
the PSE to allocate 25.5W per PD and a further 4.5W for
each 100m cable’s IR drop.
If an additional 13W PD is plugged into the fourth PSE
port, only 10W is available and the PD cannot be powered
even though the IR drop is much less than in the prior
example.
The total power allocation is:
Assuming the system in Figure 24 is Autoclass-enabled,
the recovered power budget can be used to power addi-
tional ports. During classification, the PSE observes the
PD’s Autoclass request. After power on is completed, the
PD draws its maximum power while the PSE performs
an Autoclass measurement, as specified by 802.3bt. The
PSE in Figure 24 will measure and report 26W of power
consumption for each of the three 25.5W PDs. This result
allows the host to revise the PSE available power budget.
3 Ports • (4.5W + 25.5W) = 90W
13W PD
100m CABLE
4.5W IR DROP
25.5W PD
100W PSE
100m CABLE
4.5W IR DROP
25.5W PD
100m CABLE
4.5W IR DROP
With Autoclass, the total power allocation for Figure 24 is:
3 Ports • 26W (Measured) = 78W
25.5W PD
9101123 F23
If an additional 13W PD is plugged into the fourth PSE
port, a full 22W is now available and the PD can be suc-
cessfully powered.
Figure 23. 100W PoE System with 100m Cables
Rev. 0
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LTC9102/LTC9103
APPLICATIONS INFORMATION
Autoclass Negotiation Procedure
7. The PSE measures the Autoclass response of the PD.
If class signature 0 is measured, the PD is requesting
Autoclass. When the measurement is complete the first
class event is ended.
A PSE may receive an Autoclass request from the PD by
Physical Layer classification or LLDP (by way of the PSE
host). For Physical Layer requests, the Autoclass negotia-
tion procedure listed below is shown in Figure 25.
8. The PD continues holding the class signature selected
in step 6 until the end of the first class event.
t
V
LCE_MAX
OUTn
t
LCE_MIN
Following the Autoclass negotiation procedure, PSE and
PD continue Physical Layer classification and power up
as normal. Regardless of Autoclass, the PD is required
to operate below the negotiated power allocation corre-
sponding to PD assigned Class.
V
CLASS
1
3
5
7
V
MARK
t
CLASS_MIN
t
t
t
CLASS_LCE_MAX
Autoclass Measurement Procedure
CLASS_ACS_MIN
Autoclass measurements may be requested by the PD
through Physical Layer classification or, following power
on, through LLDP. Although the LTC9101-1/LTC9102/
LTC9103 is compatible with LLDP-based Autoclass
requests, it cannot receive LLDP Autoclass requests
directly since it does not have access to the data path.
I
OUTn
t
CLASS_PD_MAX (5ms)
CLASS_SIG_4
2
4
6
8
CLASS_SIG_0
t
t
(75.5ms)
(87.5ms)
ACS_MIN
9101123 F25
If the PSE is commanded to perform an Autoclass mea-
surement following a Physical Layer request, the mea-
t
ACS_MAX
surement typically begins t
(1.5s typical) after
port inrush is successfullyAcUoTmO_pPlSeEte1d. For LLDP-based
Autoclass requests, the measurement begins immediately.
Figure 25. Autoclass Negotiation, Voltage and Current
1. PSE begins issuing the long first class event. The PD
class signature is allowed to settle during this time.
The Autoclass measurement period is tAUTO_PSE2
tAUTO_PSE1 (1.8s typical) using a sliding window of tAUTO_
(0.23s typical). During the Autoclass measure-
–
2. The PD responds with a class signature corresponding
to its Class. The class signature during this time period
is unrelated to the Autoclass negotiation.
WINDOW
ment period, the PSE continuously monitors I
and
PORT
V , calculating maximum average power. Following the
EE
3. The PSE measures the PD class signature during this
time and uses the result for the normal Multi-event
Classification.
Autoclass measurement period, the Autoclass measure-
ments are reported in the Port Parametric registers.
See the LTC9101-1 Software Programming documen-
tation for details on enabling Autoclass, the status of
the Autoclass negotiation, reading Autoclass measure-
ment results and dynamically requesting an Autoclass
measurement.
4. The PD continues presenting its class signature.
5. The PSE continues the long class event and does not
measure the class signature current at this time.
6. The PD, if requesting Autoclass, transitions to class
signature 0. If the PD is not requesting Autoclass it
continues presenting its class signature.
Rev. 0
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LTC9102/LTC9103
APPLICATIONS INFORMATION
Port Current Readback
may be characterized and extrapolated from the VEE mea-
surement in a user-defined manner.
The LTC9101-1/LTC9102/LTC9103 measures the current
at each power channel with per-channel A/D converters.
Channel current is only valid when at least one power
channel of a port is on and reads zero at all other times.
The converter has two modes:
Masked Shutdown
The LTC9101-1/LTC9102/LTC9103 provides a low latency
port shedding feature to quickly reduce the system load
when required. By allowing a pre-determined set of ports
to be turned off, the current on an overloaded main power
supply can be reduced rapidly while keeping high pri-
ority devices powered. Each port can be configured to
high or low priority; all low-priority ports will shut down
within 6.5μs after MSD is pulled low, high priority ports
will remain powered. If a port is turned off via MSD, the
corresponding Detection and Classification Enable bits are
cleared, so the port will remain off until the host explicitly
re-enables detection.
• 100ms mode: Samples are taken continuously and the
measured value is updated every 100ms
• 1s mode: Samples are taken continuously; a moving
1 second average is updated every 100ms
V
Readback
EE
The LTC9101-1/LTC9102/LTC9103 continuously mea-
sures the VEE voltage with a dedicated A/D converter.
This global V measurement is fully synchronized to all
EE
port current measurements and can monitor down to the
LTC9102/LTC9103 UVLO threshold.
In the LTC9101-1/LTC9102/LTC9103 chipset, the active
level of MSD is register configurable as active high or low.
The default behavior is active low.
Temperature Readback
4-Pair Valid
In addition to the over temperature fault in the supply
event register, the LTC9101-1 also reports die temperature
of each corresponding LTC9102/LTC9103.
The IEEE 802.3bt standard leaves room for interpretation
in the single-signature and dual-signature PD definitions.
Strictly speaking the 802.3bt standard defines only single-
signature and dual-signature PDs.
Overtemperature Protection
Overtemperature protection automatically removes power
from affected ports when LTC9102/LTC9103 temperature
exceeds a preset threshold (150°C, typ). Ports are pre-
vented from resuming operation until the die temperature
drops below a preset recovery threshold (125°C, typ). See
LTC9101-1 Software Interface guide for details.
A strict interpretation limits valid PDs to single-and dual-
signature PDs which are connected to both PSE pair-
sets. PDs which do not have valid detection signatures
on both pairsets are treated as invalid PDs. To enable
a port’s 4-Pair Valid mode, set 4PVALID low or set the
port’s 4-Pair Valid configuration register. With 4-Pair Valid
mode enabled, a port will only apply power if there is a
valid detection signature on both pairsets. See Table 14.
Port Power Readback
The LTC9101-1/LTC9102/LTC9103 provides fully con-
tinuous and synchronized port power measurements. The
LTC9101-1/LTC9102/LTC9103 calculates the port power
Table 14. 4-Pair Valid Enabled
PAIRSET
DETECTION
SIGNATURE
ALTERNATIVE A
INVALID
ALTERNATIVE A
VALID
by multiplying the port current and V measurements.
EE
ALTERNATIVE B
INVALID
Port Unpowered
Port Unpowered
Port Unpowered
Power A and B
P
PORT
= I • V
PORT EE
ALTERNATIVE B
VALID
The Port Power measurements replace the Port Voltage
measurements provided in prior ADI PSEs. Port voltage
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APPLICATIONS INFORMATION
A second interpretation is more liberal and allows PDs
which only present valid detection signatures on one pair-
set to be powered on the corresponding pairset, regard-
less of the detection result on the other pairset. To disable
a port’s 4-Pair Valid mode, set 4PVALID high or clear the
port’s 4-Pair Valid configuration register. With 4-Pair Valid
mode disabled, a port will power a pairset with a valid
signature regardless of the valid or invalid signature on
the other pairset. See Table 15.
initial values are as specified in the LTC9101-1 Software
Interface. These initial values are subject to the state of
pins, such as the AUTO and 4PVALID pins. Register map
default configurations may be stored during manufactur-
ing bring up or field-updated via configuration package
download and will be auto-loaded at boot.
In addition to configuring register map initial values, con-
figuration packages enable port definition as either 2-pair
or 4-pair ports. Ports are configured as 2-pair or 4-pair at
the quad level (groups of 4 ports).
Table 15. 4-Pair Valid Disabled
PAIRSET
Contact ADI applications support for assistance in gener-
ating custom configuration packages. Configuration pack-
ages are downloaded using normal code download mech-
anisms. Package headers ensure configuration packages
are identified and stored in the appropriate flash partition.
DETECTION
SIGNATURE
ALTERNATIVE A
INVALID
ALTERNATIVE A
VALID
ALTERNATIVE B
INVALID
Port Unpowered
Power B
Power A
ALTERNATIVE B
VALID
Power A and B
If a stored configuration is utilized, the state of the AUTO,
CFG[0], PWRMD[1:0] and 4PVALID pins can be overwrit-
ten by a configuration package. CFG[2:1] are still required
to inform the LTC9101-1 how many LTC9102/LTC9103
are attached. AD[3:2] are still required to inform the
Any PD powered with a valid detection signature on one
pairset is treated as a dual-signature PD with one pairset
unpowered.
2
LTC9101-1 of the base I C chip address.
Code Download
Two identical copies of the configuration image are main-
tained under separate ECC and CRC protection for maxi-
mum data protection.
LTC9101-1 firmware is field-upgradable by downloading
and executing firmware images.
Contact Analog Devices for code download procedures
and firmware images.
SERIAL DIGITAL INTERFACE
Firmware images are stored in a dedicated flash partition.
A fully-compliant IEEE 802.3at/bt firmware image is pre-
configured on the LTC9101-1. The firmware image may
be overwritten by the user.
Overview
The LTC9101-1 communicates with the host using a
standard SMBus/I C 2-wire interface. The LTC9101-1 is a
2
slave-only device, and communicates with the host master
using standard SMBus protocols. Interrupts are signaled
to the host via INT. The timing diagrams (Figure 5 through
Figure 9) show typical communication waveforms and
their timing relationships. More information about the
SMBus data protocols can be found at www.smbus.org.
Two complete copies of firmware images are maintained
under separate ECC and CRC protection for maximum
data protection.
Stored Configurations
2
Custom I C register map initial values may optionally be
The LTC9101-1 requires both the V and V supply rails
stored in a dedicated flash partition (configuration pack-
age). When shipped from the factory, the LTC9101-1 con-
tains a default configuration package where register map
DD
EE
to be present for the serial interface to function.
Rev. 0
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LTC9102/LTC9103
APPLICATIONS INFORMATION
Bus Addressing
ISOLATION REQUIREMENTS
The LTC9101-1’s primary 7-bit serial bus address is
010A3A200b, with bits 3:2 set by AD3:AD2 respectively. In
Figure 6 through Figure 9, AD3:AD2 are set by LTC9101-1
pins and AD1:AD0 are inferred by device configuration.
See Table 4 for device configuration options. Depending on
device configuration, up to 12 I2C addresses will be popu-
lated from the I2C base address upwards. All LTC9101-1s
also respond to the broadcast address 0110000b, allow-
ing the host to write the same command (typically con-
figuration commands) to multiple LTC9101-1s in a single
transaction. If the LTC9101-1 is asserting INT, it will also
respond to the alert response address (0001100b) per the
SMBus specification.
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be iso-
lated from each other, provided that the segments are
connected to devices residing within a single building on
a single power distribution system.
If the PSE is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to pro-
tective ground for some other reason, the PoE subsystem
must be electrically isolated from the rest of the system.
The LTC9101-1/LTC9102/LTC9103 chipset simplifies PSE
isolation by allowing the LTC9101-1 chip to reside on the
non-isolated side. There it can receive power from the
Each LTC9101-1/LTC9102/LTC9103 is logically com-
posed of multiple four port groups, known as quads, each
packed into a single I2C address. See Device Configuration
section for details. For example, if CFG[2:0] is set to 000,
an LTC9101-1 is configured as an 8-port or 12-port device
when attached to an LTC9102 or an LTC9103, respectively
(see Table 4). This configuration requires two or three
2
main logic supply and connect directly to the I C/SMBus
bus. In this case, the SDAIN and SDAOUT pins can be tied
2
together and will act as a standard I C/SMBus SDA pin.
Isolation between the LTC9101-1 and LTC9102/LTC9103
is implemented using a proprietary transformer-based
communication protocol. Additional details are provided
in the High-Speed Data Isolation section of this data sheet.
2
consecutive I C addresses, with quad offset 0 starting at
2
the I C base address.
For simple devices, such as unmanaged PoE switches,
the isolation requirement can be met by using an isolated
main power supply for the entire device. This strategy can
be used if the device has no electrically conducting ports
other than twisted-pair Ethernet. The LTC9101-1 may
directly connect to the LTC9102s/LTC9103s in the above
circumstances, or if the system already provides isolation.
2
Note that any individual quad I C address greater than or
equal to 0x30 (the broadcast address) will be automati-
cally disabled.
Interrupts and SMBAlert
Most port events can be configured to trigger an inter-
rupt, asserting INT and alerting the host to the event. This
removes the need for the host to poll the LTC9101-1,
minimizing serial bus traffic and conserving host CPU
cycles. Multiple LTC9101-1s can share a common INT
line, with the host using the SMBAlert protocol (ARA) to
determine which LTC9101-1 caused an interrupt.
EXTERNAL COMPONENT SELECTION
Power Supplies
The LTC9101-1/LTC9102/LTC9103 requires two supply
voltages to operate. VDD requires 3.3V (nominally) relative
to DGND. VEE requires a negative voltage of between –51V
to –57V for Type 2 and 3 PSEs, or –53V to –57V for Type
4 PSEs, relative to AGND.
Register Description
For information on serial bus usage and device configura-
tion and status, refer to the LTC9101-1 Software Interface
guide. Contact Analog Devices to request this document.
Rev. 0
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APPLICATIONS INFORMATION
Digital Power Supply
capacitor of at least 47μF, 100V and a bulk TVS are also
recommended per system.
VDD provides digital power for the LTC9101-1 proces-
sor. A ceramic decoupling cap of at least 0.1μF should
LTC9102/LTC9103 Low Voltage Power Supplies
be placed from each V to DGND, as close as practical
DD
The LTC9102/LTC9103 includes internal voltage regula-
tors that generate low voltage supplies directly from the
main PoE power supply. At startup, an internal regula-
tor generates 6V at PWRIN, drawing power from AGND.
Internal 4.3V and 3.3V rails are sub-regulated from
PWRIN. The PWRIN pin requires a local 1μF, 100V bypass
capacitor.
to each LTC9101-1. In addition, each LTC9101-1 must
include a bulk cap of 10µF for robust surge immunity.
A 1.2V core voltage supply is generated internally and
requires a 1µF ceramic decoupling cap between the CAP1
pin and DGND and between CAP2 and DGND.
In systems using ADI’s proprietary isolation, V should
be delivered by the host controller’s non-isolDatDed 3.3V
supply. To maintain required isolation, LTC9102/LTC9103
AGND and LTC9101-1 DGND must not be connected.
If using the direct connection scheme, the LTC9101-1
Pull-up resistors can be connected from PWRIN to AGND
to dissipate heat outside the LTC9102/LTC9103 package.
Optionally, an external power supply can be connected
to PWRIN to override the startup regulator and reduce
power dissipation.
DGND must be connected to LTC9102/LTC9103 V .
EE
Main PoE Power Supply
Figure 26 shows a pull-up resistor configuration with the
internal 3.3V regulator. Bypass resistors R1, R2, R3, and
R4 draw heat away from the LTC9102s/LTC9103s. Note
that the voltage of the PWRIN pin changes based on the
LTC9102/LTC9103 operating mode and its correspond-
ing current consumption. If more current is consumed
than the bypass resistors provide, the startup regulator
maintains the voltage at 6V typical. The LTC9102 can
operate without the pull-up resistors in space-constrained
applications.
V
is the main isolated PoE supply that provides power
EE
to the PDs. Because it supplies a relatively large amount
of power and is subject to significant current transients,
it requires more design care than a simple logic supply.
For minimum IR loss and best system efficiency, set V
EE
near maximum amplitude (57V), leaving enough margin
to account for transient over or undershoot, temperature
drift, and the line regulation specifications of the particular
power supply used.
Abypasscapacitorandatransientvoltagesuppressor(TVS)
In applications with an external PWRIN supply, a 6.5V reg-
ulator provides an optimum voltage to override the inter-
nal 6V start-up regulator, while minimizing the LTC9102
device heating. The external supply may be shared across
multiple LTC9102s/LTC9103s.
between each LTC9102/LTC9103 AGND and V are very
EE
important for reliable operation. If a short circuit occurs
at one of the output ports it can take as long as 1μs for
the LTC9102/LTC9103 to begin regulating the current.
During this time the current is limited only by the small
impedances in the circuit; a high current spike typically
A 3.3V power supply can be connected directly to the
CAP3 pin, as shown in Figure 27. This provides the most
power efficient sleep mode. When supplying external 3.3V
power, tie the EXT3 pin to CAP3. This will disable the
internal 3.3V regulator and prevent power back-feed. The
3.3V regulator must power up within tCAP3EXT specified in
the electrical characteristics table.
occurs, causing a voltage transient on the V supply and
EE
possibly causing the LTC9101-1/LTC9102/LTC9103 to
reset due to a UVLO fault. A 1μF, 100V X7R capacitor
and a SMAJ58A near each LTC9102/LTC9103 are recom-
mended to minimize spurious resets. An electrolytic bulk
Rev. 0
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LTC9102/LTC9103
APPLICATIONS INFORMATION
1µF
100V
1µF
100V
+
47µF
100V
AGND
AGND
R1
R3
R2
R4
10k
10k
10k
10k
V
V
EE
EE
1/2W 1/2W
1/2W 1/2W
LTC9102/LTC9103
LTC9102/LTC9103
PWRIN
CAP4
CAP3
EXT3
CAP3
EXT3
PWRIN
CAP4
V
V
EE
EE
C1
C1
1µF
100V
1µF
100V
1µF
1µF
V
V
EE
EE
1µF
1µF
V
EE
9101123 F26
Figure 26. Power Supply Configuration with Internal 3.3V Supply
1µF
100V
1µF
100V
R2
10k
1/2W
+
47µF
100V
AGND
AGND
LTC9102/LTC9103
R1
10k
1/2W
V
V
EE
EE
3.3V
LTC9102/LTC9103
3.3V
3.3V
REGULATOR
PWRIN
CAP4
CAP3
EXT3
CAP3
EXT3
PWRIN
CAP4
C2
C1
1µF
1µF
1µF
1µF
1µF
1µF
V
V
EE
EE
100V
100V
V
EE
9101123 F27
Figure 27. Power Supply Configuration with External 3.3V Regulators
If using the direct connection scheme, the 3.3V regu-
lator that supplies the LTC9101-1 can also supply the
LTC9102s/LTC9103s. This is the preferred option when
the LTC9101-1 and LTC9102/LTC9103 are on the same
side of the system isolation barrier.
In the direct connection scheme, the LTC9101-1/LTC9102/
LTC9103 chipset relies on pre-existing system isolation.
In this scheme, the LTC9101-1 connects directly to one
or more LTC9102s/LTC9103s using a proprietary com-
munication protocol (see Figure 29).
High-Speed Data Isolation
External MOSFET
The LTC9101-1/LTC9102/LTC9103 chipset can either pro-
vide proprietary isolation or rely on existing system isola-
tion. Significant BOM cost reductions can be achieved
using the proprietary isolation scheme.
Careful selection of the power MOSFET is critical to sys-
tem reliability. Choosing a MOSFET requires extensive
analysis and testing of the MOSFET SOA curve against the
various PSE current limit conditions. ADI recommends
the PSMN075-100MSE for PSEs configured to deliver
up to 51W maximum port power (single-signature) or
25.5W maximum pairset power (dual-signature). For
PSEs configured to power up to 71.3W maximum port
power (single-signature) or 35.6W maximum pairset
power (dual-signature), ADI recommends the PSMN040-
100MSE. These MOSFETs are selected for their proven
reliability in PoE applications. Contact ADI Applications
before using a MOSFET other than one of these recom-
mended parts.
In the proprietary isolation scheme, the LTC9101-1/
LTC9102/LTC9103 chipset uses transformers to isolate
the LTC9101-1 from one to four LTC9102s/LTC9103s
(see Figure 28). In this case, the SDAIN and SDAOUT
pins can be shorted to each other and tied directly to the
2
I C/SMBus bus. The transformers should be 10BASE-T
or 10/100BASE-T with a 1:1 turns ratio. Optimally, the
selected transformers do not have common-mode chokes.
These transformers typically provide 1500V of isolation
between the LTC9101-1 and the LTC9102s/LTC9103s. For
proper operation, strict layout guidelines must be met.
Rev. 0
40
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
Sense Resistors
Surge Protection
The LTC9101-1/LTC9102/LTC9103 is designed for a low
0.1Ω current sense resistance per channel, laid out as
shown in the Layout Requirements section, Figure 31. In
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect
the application against damage, protection components,
as shown in Figure 30, are required at the main supply,
at the LTC9102/LTC9103 supply pins, and at each port.
order to meet the I
, I
, and I
accuracy
HOLD-2P CUT-2P
LIM-2P
required by the IEEE specification, the sense resistors
should have 1% tolerance or better, and no more than
200ppm/°C temperature coefficient.
Bulk transient voltage suppression (TVS
) and bulk
capacitance (CBULK) are required acrossBUthLeK main PoE
supply and should be sized to accommodate system level
surge requirements.
Port Output Cap
Each port requires a 0.1μF cap across OUTn to AGND (see
Figure 30) to keep the LTC9102/LTC9103 stable while in
current limit during startup or overload. Common ceramic
capacitors often have significant voltage coefficients; this
means the capacitance is reduced as the applied voltage
increases. To minimize this problem, X7R ceramic capaci-
tors rated for at least 100V are recommended and must
be located close to the LTC9102/LTC9103.
Across each LTC9102/LTC9103 AGND pin and V pin is a
EE
SMAJ58A 58V TVS (D1) and a 1µF, 100V bypass capaci-
tor (C1). These components must be placed close to the
LTC9102/LTC9103 pins.
Each port requires an S1B clamp diode from OUTn to
supply AGND. This diode steers harmful surges into the
supply rails where they are absorbed by the surge sup-
pressors and the V bypass capacitance. The layout of
EE
these paths must be low impedance.
Rev. 0
41
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
3.3V
V
DD
CPD
0.01µF
49.9Ω
49.9Ω
0.01µF
0.01µF
•
•
•
V
V
EE
LTC9101-1
CND
2
(NO I C
ISOLATION
REQUIRED)
CPA
CNA
DPA
DNA
AGND
DPD
LTC9102/
LTC9103
INT
0.01µF
49.9Ω
49.9Ω
•
CAP3-1
SCL
SDAIN
SDAOUT
EE
CAP3
1µF
DND
V
EE
DGND
V
EE
1000pF
2kV
CPA
CNA
DPA
DNA
AGND
V
EE
LTC9102/
LTC9103
CAP3-2
CAP3
1µF
V
EE
V
EE
CPA
CNA
DPA
DNA
AGND
NOTES:
1. MULTIPLE LTC9102/LTC9103 DEVICES ON THE HIGH-SPEED DATA INTERFACE ARE DAISY CHAINED.
2. THE HIGH-SPEED DATA INTERFACE IS TERMINATED AT BOTH ENDS.
3. THE 100k RESISTORS AT THE END OF THE HIGH-SPEED DATA INTERFACE CONNECT TO THE
LAST LTC9102/LTC9103 CAP3.
4. THE MAXIMUM LENGTH OF THE HIGH-SPEED DATA INTERFACE IS 16 INCHES.
5. THE HIGH-SPEED DATA INTERFACE DIFFERENTIAL IMPEDANCE IS 100Ω.
LTC9102/
LTC9103
CAP3-3
CAP3
1µF
V
EE
V
EE
CPA
CNA
DPA
DNA
AGND
LTC9102/
LTC9103
CAP3-4
1µF
CAP3
V
EE
V
EE
49.9Ω
100k
100k
100k
49.9Ω
49.9Ω
100k
49.9Ω
0.01µF
0.01µF
V
V
EE
EE
V
V
9101123 F28
EE
EE
Figure 28. LTC9101-1/LTC9102/LTC9103 Proprietary Isolation Scheme
Rev. 0
42
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
3.3V
V
DD
CPD
OPTION 1:
AUTO SET HIGH
TO ENABLE
49.9Ω 0.01µF
AUTO
AUTONOMOUS
OPERATION
LTC9101-1
CND
V
EE
49.9Ω
OR
CPA
CNA
DPA
DNA
AGND
DPD
LTC9102/
LTC9103
OPTION 2:
INT
SCL
SDAIN
SDAOUT
49.9Ω 0.01µF
3.3V
PSE MANAGED
BY SYSTEM
HOST VIA
CAP3
V
EE
ISOLATED
49.9Ω
1µF
2
I C INTERFACE
DND
V
EE
V
EE
DGND
CPA
CNA
DPA
DNA
AGND
V
EE
LTC9102/
LTC9103
3.3V
CAP3
1µF
V
EE
V
EE
CPA
CNA
DPA
DNA
AGND
NOTES:
LTC9102/
LTC9103
1. MULTIPLE LTC9102/LTC9103 DEVICES ON THE HIGH-SPEED DATA
INTERFACE ARE DAISY CHAINED.
2. THE HIGH-SPEED DATA INTERFACE IS TERMINATED AT BOTH ENDS.
3. THE MAXIMUM LENGTH OF THE HIGH-SPEED DATA INTERFACE IS
16 INCHES.
3.3V
CAP3
1µF
4. THE HIGH-SPEED DATA INTERFACE DIFFERENTIAL IMPEDANCE IS 100Ω.
V
EE
V
EE
CPA
CNA
DPA
DNA
AGND
LTC9102/
LTC9103
3.3V
CAP3
1µF
V
EE
V
EE
9101123 F29
49.9Ω
(4 PLACES)
0.01µF
0.01µF
V
V
EE
EE
Figure 29. LTC9101-1/LTC9102/LTC9103 Proprietary Direct Connection Scheme
Rev. 0
43
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
APPLICATIONS INFORMATION
AGND
C1
1µF
D1
SMAJ58A
LTC9102/LTC9103
GATEn OUTn
100V
V
+
EE
C
BULK
VSSKn SENSEn
Cn
TVS
BULK
0.1µF
X7R
100V
S1B
OUTn
TO
PORT
AGND
V
EE
Qn
RSENSEn
9101123 F30
Figure 30. LTC9102/LTC9103 Surge Protection
Table 16. Component Selection for PSE Maximum Class
PSE CLASS
Class 3
SENSE RESISTOR
HOT SWAP MOSFET
PSMN075-100MSE
PSMN075-100MSE
PSMN040-100MSE
PSMN040-100MSE
FUSE
ETHERNET TRANSFORMER
7490220120
100mΩ, 1%, 50mW
100mΩ, 1%, 100mW
100mΩ, 1%, 100mW
100mΩ, 1%, 200mW
SF-0603HI075F-2
SF-0603HI100F-2
SF-0603HI100F-2
SF-0603HI150F-2
Class 4
7490220121
Class 6
7490220121
Class 8
7490220122
LAYOUT REQUIREMENTS
TO FET(Qn)
RSENSEn
Strict adherence to board layout, parts placement and
routing requirements is critical for IEEE compliance, para-
metric measurement accuracy, system robustness and
thermal dissipation. Refer to the DC3160A-KIT demo kit
for example layout references.
SENSEn
VSSKn
Kelvin Sense
V
EE
9101123 F31
Proper connection of the port current Kelvin sense lines is
important for current threshold accuracy and IEEE compli-
ance. Refer to Figure 31 for an example layout of these Kelvin
sense lines. The LTC9102/LTC9103 VSSKn pin is Kelvin con-
Figure 31. RSENSE Kelvin Connections
The data-lines require impedance matched traces to each
LTC9102/LTC9103. The data bus termination resistors must
be located at the LTC9102/LTC9103 farthest away from the
isolation transformers. For isolated applications, the DC
biasing resistors must connect to the LTC9102/LTC9103
CAP3 pin, farthest away from the isolation transformers. As
shown in Figure 28 and Figure 29, design the interface with
100Ω differential transmission lines, and terminate 100Ωs
differentially. Limit the high-speed data interface line length
to 16 inches. Minimize the transmission stubs between the
LTC9102s/LTC9103s and the high-speed data interface.
nected to the sense resistor (V side) pad and is not other-
EE
wise connected to V copper areas. Similarly, the LTC9102/
EE
LTC9103 SENSEn pin is Kelvin connected to the sense resis-
tor (SENSEn side) pad and is not otherwise connected in the
power path. Figure 31 shows the two Kelvin traces from the
LTC9102/LTC9103 to the sense resistor (R
).
SENSEn
High-Speed Data Interface
The LTC9101-1/LTC9102/LTC9103 chipset communi-
cates across a proprietary high-speed, multi-drop data
interface. This allows for a single LTC9101-1 to control
up to four LTC9102s/LTC9103s.
Rev. 0
44
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
TYPICAL APPLICATIONS
S1B
0.1μF
100V
AGND
T1
OUT1
75Ω
GATE1
Q1
CT1
SENSE1
RS1
PORT 1
0.1Ω
1/4W
DATA AND
CPA
4-PAIR POWER OUT
VSSK1
75Ω
75Ω
75Ω
CT2
CT3
CT4
CNA
DPA
DNA
V
EE
1
2
3
4
RJ45
5
0.1μF
100V
6
7
8
OUT2
GATE2
Q2
SENSE2
1000pF
2kV
RS2
0.1Ω
1/4W
VSSK2
S1B
V
EE
LTC9102
REPEAT CONFIGURATION AND CONNECTIONS FOR ALL 4-PAIR PORTS
S1B
0.1μF
100V
T6
OUT11
GATE11
75Ω
Q11
CT21
SENSE11
RS11
0.1Ω
1/4W
PORT 6
DATA AND
4-PAIR POWER OUT
75Ω
75Ω
75Ω
VSSK11
CT22
CT23
CT24
V
EE
1
2
3
4
RJ45
0.1μF
100V
5
6
7
8
OUT12
GATE12
Q12
SENSE12
RS12
0.1Ω
1/4W
1000pF
2kV
VSSK12
V
V
EE
EE
S1B
T1, T6: WURTH 7490220122
COILCRAFT ETH1-460L
CT1 TO CT24: 0.01μF, 200V
Q1 TO Q12: NXP PSMN040-100MSE
9101123 F32
V
EE
Figure 32. Alternative A (MDI-X) and B (S), 4-Pair, 1000BASE-T, IEEE 802.3bt, Type 3 or Type 4 PSE, Ports 1 and 6 Shown
Rev. 0
45
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
TYPICAL APPLICATIONS
S1B
0.1μF
100V
AGND
T1
OUT1
75Ω
GATE1
Q1
CT1
CT2
CT3
CT4
SENSE1
RS1
0.1Ω
1/10W
PORT 1
DATA AND
2-PAIR POWER OUT
CPA
VSSK1
75Ω
75Ω
75Ω
CNA
DPA
DNA
V
EE
1
2
3
4
RJ45
5
6
7
8
1000pF
2kV
REPEAT CONFIGURATION AND CONNECTIONS FOR ALL 2-PAIR PORTS
LTC9102
S1B
0.1μF
100V
T12
OUT12
GATE12
75Ω
Q12
CT45
SENSE12
RS12
0.1Ω
1/10W
PORT 12
DATA AND
2-PAIR POWER OUT
75Ω
75Ω
75Ω
VSSK12
CT46
CT47
CT48
V
EE
1
2
3
4
RJ45
5
6
7
8
1000pF
2kV
V
EE
T1, T12: WURTH 7490220121
9101123 F33
COILCRAFT ETH1-460L
V
EE
CT1 TO CT48: 0.01μF, 200V
Q1 TO Q12: NXP PSMN075-100MSE
Figure 33. Alternative A (MDI-X), 2-Pair, 1000BASE-T, IEEE 802.3bt or IEEE 802.3at PSE, Ports 1 and 12 Shown
Rev. 0
46
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
TYPICAL APPLICATIONS
D1: SMCJ58A
D2: SMAJ58A
3.3V
1µF
100V
1
3.3V REGULATOR
D1
D2
>47µF
TX1
0.1µF
100V
V
EE
S1B
AGND
OUT1
2
ID0
0.1µF
3.3V
ID1
3
PWRMD
V
EE
PSMN040-100MSE
GATE1
TX2
V
DD
SENSE1
6
LTC9102/LTC9103
0.1Ω
LTC9101-1
4
VSSK1
CPD
CND
DPD
DND
CPA
TX3
V
EE
0.1µF
RESET
CNA
DPA
DNA
5
S1B
100V
OUT2
3.3V
7
AUTO
CFG0
CFG1
CFG2
PSMN040-100MSE
GATE2
3.3V
TX4
CAP3
EXT3
SENSE2
8
0.1Ω
1µF
RJ45
1000BASE-T
VSSK2
V
EE
DGND
V
EE
9101123 F34
PORT 1
V
EE
Figure 34. Autonomous IEEE 802.3bt 4-Pair PSE, Type 3 or Type 4, Alternative A (MDI-X) and B(S), 1000BASE-T, 1 Port Shown
Rev. 0
47
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-ꢀ697 Rev B)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.ꢀꢀ5
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
TYP
23 24
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
2.45 0.ꢀ0
(4-SIDES)
(UF24) QFN 0ꢀ05 REV B
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev. 0
48
For more information www.analog.com
LTC9101-1/
LTC9102/LTC9103
PACKAGE DESCRIPTION
UKJ Package
64-Lead Plastic QFN (7mm × 11mm)
(Reference LTC DWG # 05-08-1780 Rev 0)
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
0.75 ±0.05
5.50 REF
63 64
7.00 ±0.10
0.00 – 0.05
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
8.80 ±0.10
0.55 REF
11.00 ±0.10
9.50 REF
4.40
±0.10
4.80 ±0.10
R = 0.125
TYP
(UKJ64) QFN 0119 REV Ø
R = 0.10
TYP
0.200 REF
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.70 ±0.05
7.50 ±0.05
6.10 ±0.05
5.50 REF
8.80 ±0.05
4.80 ±0.05
4.40 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
9.50 REF
10.10 ±0.05
11.50 ±0.05
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
49
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC9101-1/
LTC9102/LTC9103
TYPICAL APPLICATION
IEEE 802.3bt Type 3 or Type 4 PSE, Alternative A (MDI-X) and B (S), 1000BASE-T, 1 Port Shown
D1: SMCJ58A
D2: SMAJ58A
0.1µF
3.3V
1µF
100V
1
D1
D2
>47µF
TX1
0.1µF
100V
V
EE
S1B
V
DD
AGND
OUT1
2
CFG2
ID0
CFG1
CFG0
ISOLATION
ID1
3
PSMN040-100MSE
CPD
CPA
GATE1
RESET
TX2
MSD
2
SENSE1
(NO I C
6
HIGH-
SPEED
DATA
ISOLATION
REQUIRED)
LTC9101-1
LTC9102/LTC9103
0.1Ω
4
CND
CNA
VSSK1
INTERFACE
DPD
DPA
TX3
V
EE
INT
0.1µF
100V
SCL
5
S1B
OUT2
SDAIN
SDAOUT
7
PSMN040-100MSE
GATE2
DND
DNA
TX4
SENSE2
AD2
AD3
8
0.1Ω
RJ45
1000BASE-T
1000pF
2kV
VSSK2
V
EE
DGND
V
EE
9101123 TA02
PORT 1
V
EE
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC4292/
LTC4291-1
4-Port IEEE 802.3bt PoE PSE Controller
Transformer Isolation, 14-bit Current Monitoring per Port with Programmable Current
Limit, Supports Type 1-4 PDs
++
++
LT4293
LTPoE /IEEE 802.3bt PD Interface
External Switch, LTPoE and IEEE 802.3bt Support, Configurable Class and AUX Support
Controller
LT4294
LT4295
IEEE 802.3bt PD Controller
External Switch, IEEE 802.3bt Support, Configurable Class and AUX Support
IEEE 802.3bt PD with Forward/Flyback
Switching Regulator Controller
External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback
Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including
Housekeeping Buck, Slope Compensation
++
+
++
LTC4290/
LTC4271
8-Port PoE/PoE /LTPoE PSE Controller
Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE PDs
LTC4257-1
LTC4263
LTC4265
LTC4266
LTC4267
IEEE 802.3af PD Interface Controller
Single IEEE 802.3af PSE Controller
IEEE 802.3at PD Interface Controller
Quad IEEE 802.3at PoE PSE Controller
Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class
Internal FET Switch
Internal 100V, 1A Switch, 2-Event Classification Recognition
With Programmable I /I , 2-Event Classification, and Port Current and Voltage Monitoring
CUT LIM
IEEE 802.3af PD Interface with Integrated
Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class
12-Port PoE/PoE /LTPoE ® PSE Controller Transformer Isolation, Supports Type 1, Type 2 and LTPoE PDs
+ ++ ++
Switching Regulator
LTC4270/
LTC4271
LTC4278
IEEE 802.3at PD Interface with Integrated
Flyback Switching Regulator
2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,
50kHz to 250kHz, 12V Aux Support
++
+
++
LTC4279
Single PoE/PoE /LTPoE PSE Controller
Supports IEEE 802.3af, IEEE 802.3at, LTPoE and Proprietary PDs
Rev. 0
11/21
www.analog.com
ANALOG DEVICES, INC. 2021
50
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Linear
LTC4300-1CMS8#TRPBF
LTC4300-1/LTC4300-2 - Hot Swappable 2-Wire Bus Buffers; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C
Linear
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