LTC4361 [ADI]
100V UV/OV and Reverse Protection Controller with Bidirectional Circuit Breaker;
| 型号： | LTC4361 |
| 厂家： | 
ADI |
| 描述： | 100V UV/OV and Reverse Protection Controller with Bidirectional Circuit Breaker |
| 文件： | 总22页 (文件大小：1378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4368
100V UV/OV and Reverse Protection
Controller with Bidirectional Circuit Breaker
FEATURES
DESCRIPTION
The LTC®4368 protects applications from power supply
voltages that may be too high, too low, or even negative
and from overcurrent faults in both forward and reverse
directions. The LTC4368 controls the gate voltage of a pair
of external N-channel MOSFETs to ensure that the load
is connected to the input supply only when there are no
voltage or current faults.
n
Wide Operating Voltage Range: 2.5V to 60V
n
Overvoltage Protection to 100V
n
Reverse Supply Protection to –40V
n
Bidirectional Electronic Circuit Breaker:
n
+50mV Forward Sense Threshold
n
–50mV Reverse (LTC4368-1)
n
–3mV Reverse (LTC4368-2)
n
Adjustable 1.5% Undervoltage and Overvoltage
Two comparator inputs allow configuration of the over-
voltage (OV) and undervoltage (UV) set points using an
external resistive divider. A current sense resistor sets the
forward and reverse circuit breaker current thresholds.
After a forward current fault, the LTC4368 will either latch-
off power, or retry after a user adjustable delay. After a
reverse current fault, the LTC4368 waits for the output to
fall 100mV below the input to reconnect power to the load.
Thresholds
n
Low Operating Current: 80µA
n
Low Shutdown Current: 5µA
n
Controls Back-to-Back N-Channel MOSFETs
n
Blocks 50Hz and 60Hz AC Power
Hot Swappable Supply Input
n
n
Pin-Selectable Overcurrent Auto-Retry Timer or Latchoff
n
10-Pin MSOP and 3mm × 3mm DFN Packages
The LTC4368 has a 32ms turn-on delay that debounces
live supply input connections and blocks 50Hz and 60Hz
AC power. UV/OV faults also trigger the 32ms recovery
delay before the external MOSFETs are turned back on.
All registered trademarks and trademarks are the property of their respective owners.
n
AEC-Q100 Qualified for Automotive Applications
APPLICATIONS
n
Reverse Battery Protection
n
Portable Instrumentation
n
Automotive and Industrial Surge Protection
Energy Storage Systems
n
TYPICAL APPLICATION
Load Protected from Reverse and Overvoltage at VIN
24V Application with 10A Circuit Breaker
+50mV
V
OUT
–40V TO 100V
0.005Ω
–3mV
7V TO 36V
ꢀꢁ ꢂ ꢃꢄꢁ
ꢅꢁ ꢂ ꢆꢁ
SiR870
SiR870
V
I
IN
OUT
ꢀꢁꢂꢃ
ꢄꢂꢃꢅꢆꢇꢃ
24V
–0.6A TO 10A
+
INRUSH
CONTROL
ꢀ
ꢀꢁ
100µF
22k
ꢀꢁꢂꢃꢄ ꢅꢃꢆꢄꢇꢅ
3.3nF
SENSE
V
OUT
GATE
V
ꢀꢁꢂ
IN
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
464k
1500k
121k
FAULT
SHDN
UV
ꢀꢁꢂꢃ
ꢄꢂꢃꢅꢆꢇꢃ
LTC4368-2
GND
ꢀ
ꢀꢁ
1200ms COOLDOWN
AFTER FORWARD
OC FAULT
OV = 36V
UV = 7V
OV
RETRY
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
29.4k
0.22µF
4368 TA01a
Rev. B
1
Document Feedback
For more information www.analog.com
LTC4368
ABSOLUTE MAXIMUM RATINGS
(Note 1, Note 2)
Supply Voltage
Output Voltages
V ........................................................ –40V to 100V
FAULT (Note 3)....................................... –0.3V to 80V
IN
Input Voltages
GATE.............................................. –40V to V + 14V
Input Currents
RETRY, UV, OV ,SHDN, FAULT ...........................–1mA
Operating Ambient Temperature Range
IN
UV, SHDN (Note 3) ........................…….–0.3V to 80V
OV (Note 3)............................................ –0.3V to 20V
RETRY (Note 3) ....................................... –0.3V to 5V
V
V
IN
, SENSE............................................–10V to 80V
to SENSE.........................................–10V to 10V
LTC4368C............................................... 0°C to 70°C
LTC4368I............................................ –40°C to 85°C
LTC4368H........................................ . –40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
OUT
OUT
V to V
........................................... –60V to 100V
OUT
MSOP Package .................................................300°C
PIN CONFIGURATION
ꢀꢁꢂ ꢃꢄꢅꢆ
ꢃ
ꢌ
ꢝ
ꢑ
ꢛ
ꢜ
ꢌꢍ ꢋꢈꢀꢅ
ꢋꢉꢖ ꢅꢆꢊꢗ
ꢄꢖ
ꢞꢃ
ꢁꢃ
ꢗ
ꢚ
ꢙ
ꢘ
ꢔꢅꢖꢔꢅ
ꢅ
ꢈꢅ
ꢉꢅ
RꢊꢋRꢌ
ꢍꢇꢎ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀꢏ ꢍꢔꢋꢊ
ꢆꢇ
ꢐ
ꢑ
ꢒ
ꢓ
ꢕꢊꢇꢕꢊ
ꢃ
ꢁꢞꢀ
ꢅ
ꢉꢈꢋ
FAULT
SHDN
RꢅꢀRꢟ
ꢋꢖꢇ
FAULT
SHDN
ꢘꢕꢀꢏ ꢖꢔꢙꢚꢔꢍꢊ
ꢀꢏꢛꢜꢊꢔꢎ ꢖꢜꢔꢕꢋꢆꢙ ꢘꢕꢉꢖ
ꢇꢇ ꢂꢈꢉꢊꢈꢋꢅ
ꢌꢍꢎꢏꢅꢈꢇ ꢐꢑꢒꢒ × ꢑꢒꢒꢓ ꢂꢏꢈꢔꢀꢄꢉ ꢇꢕꢖ
T
= 150°C, θ = 160°C/W
JA
JMAX
EXPOSED PAD (PIN 11) PCB GROUND CONNECTION OPTIONAL
T
= 150°C, θ = 43°C/W
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC4368CDD-1#PBF
LTC4368CDD-2#PBF
LTC4368IDD-1#PBF
LTC4368IDD-2#PBF
LTC4368HDD-1#PBF
LTC4368HDD-2#PBF
LTC4368CMS-1#PBF
LTC4368CMS-2#PBF
LTC4368IMS-1#PBF
LTC4368IMS-2#PBF
LTC4368HMS-1#PBF
LTC4368HMS-2#PBF
TAPE AND REEL
PART MARKING*
LGTH
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4368CDD-1#TRPBF
LTC4368CDD-2#TRPBF
LTC4368IDD-1#TRPBF
LTC4368IDD-2#TRPBF
LTC4368HDD-1#TRPBF
LTC4368HDD-2#TRPBF
LTC4368CMS-1#TRPBF
LTC4368CMS-2#TRPBF
LTC4368IMS-1#TRPBF
LTC4368IMS-2#TRPBF
LTC4368HMS-1#TRPBF
LTC4368HMS-2#TRPBF
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LGTK
0°C to 70°C
LGTH
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
0°C to 70°C
LGTK
LGTH
LGTK
LTGTG
LTGTJ
10-Lead Plastic MSOP
0°C to 70°C
LTGTG
LTGTJ
10-Lead Plastic MSOP
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
10-Lead Plastic MSOP
LTGTG
LTGTJ
10-Lead Plastic MSOP
10-Lead Plastic MSOP
Rev. B
2
For more information www.analog.com
LTC4368
ORDER INFORMATION
AUTOMOTIVE PRODUCTS**
LTC4368IMS-1#WPBF
LTC4368IMS-2#WPBF
LTC4368HMS-1#WPBF
LTC4368HMS-2#WPBF
LTC4368IMS-1#WTRPBF
LTC4368IMS-2#WTRPBF
LTC4368HMS-1#WTRPBF
LTC4368HMS-2#WTRPBF
LTGTG
LTGTJ
LTGTG
LTGTJ
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
–40°C to 85°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
*Temperature grades are identified by a label on the shipping container. Consult ADI Marketing for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 2.5V to 60V, unless otherwise noted (Note 2). UV = 2.5V, OV = 0V,
SHDN = 2.5V, SENSE = VOUT = VIN unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V , V , SENSE
IN OUT
l
l
V
V
Input Voltage: Operating Range
Protection Range
2.5
60
V
V
IN
–40
100
l
Input Supply Undervoltage Lockout
V
Rising
1.8
2.2
2.4
V
IN(UVLO)
VIN
IN
l
l
I
Input Supply Current: On
Off
SHDN = 2.5V, SENSE = V
SHDN = 0V, SENSE = V
= V
30
5
100
25
µA
µA
OUT
OUT
IN
= V
IN
l
I
Reverse Input Supply Current
V
V
V
= –40V, SENSE = V = 0V
OUT
–1.5
2.2
–2.5
2.4
mA
V
VIN(R)
IN
l
l
V
V
OUT
V
OUT
V
OUT
Undervoltage Lockout
Rising, V
– SENSE = 100mV, V = 12V
1.8
40
OUT(UVLO)
VOUT(UVLO)
VOUT
OUT
OUT
IN
t
I
Undervoltage Lockout Delay
= 12V, V :0V→12V, V – SENSE = 100mV
OUT
120
280
µs
IN
OUT
l
l
l
Input Current: On
SHDN = 2.5V, SENSE = V
= V
50
3
20
125
20
50
µA
µA
µA
OUT
OUT
OUT
IN
Off
SHDN = 0V, SENSE = V
= V
IN
Reverse
V
= –40V, SENSE = V
= 0V
IN
Current Sense
l
l
l
I
SENSE Input Current: On
Off
SHDN = 2.5V, SENSE = V
= V
1.2
0.1
1
2
2
10
µA
µA
µA
SENSE
OUT
IN
SHDN = 0V, SENSE = V
= V
IN
OUT
OUT
Reverse
V
= –40V, SENSE = V
= 0V
IN
l
l
l
ΔV
Overcurrent Fault Threshold, Forward
(SENSE – V
V
V
V
= V
IN
40
40
30
50
50
50
60
60
70
mV
mV
mV
SENSE,F
OUT
)
= 12V, V
= 12V, V
= 0.5V
= 0V
OUT
IN
IN
OUT
OUT
l
l
ΔV
ΔV
Overcurrent Fault Threshold, Reverse
(SENSE – V
LTC4368-1
LTC4368-2
V
V
= V
= V
–42
–1
–50
–3
–58
–5
mV
mV
SENSE,R
RR
OUT
OUT
IN
IN
)
OUT
l
l
Reverse Overcurrent Re-Enable
Turn-On Threshold (V – V
V
IN
V
IN
= SENSE = 6V to 60V
= SENSE = 2.5V to <6V
75
20
100
50
125
125
mV
mV
)
OUT
IN
GATE
ΔV
l
l
l
Gate Drive (GATE – V
)
V
V
V
= 2.5V, I = 0µA, –1µA
GATE
3
7.2
10
4
8.7
11
5.5
10.8
13.1
V
V
V
GATE
OUT
IN
IN
IN
= 5V, I
= 0µA, –1µA
GATE
= 12V to 60V, I
= 0µA, –1µA
GATE
Rev. B
3
For more information www.analog.com
LTC4368
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 2.5V to 60V, unless otherwise noted (Note 2). UV = 2.5V, OV = 0V,
SHDN = 2.5V, SENSE = VOUT = VIN unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
GATE = 15V, V = 12V
MIN
–20
40
TYP
–35
90
60
2
MAX
–60
160
90
UNITS
µA
l
l
l
I
Gate Pull Up Current
GATE(UP)
IN
IGATE(SLOW) Gate Slow Pull Down Current
GATE = 20V, V = 12V
µA
IN
I
t
t
t
t
Gate Fast Pull Down Current
Gate Fast Turn Off Delay
GATE = 20V, SENSE = V = 12V
30
mA
µs
GATE(FAST)
D(FAST)
D(SLOW)
D(ON)
IN
l
l
C
C
V
C
= 2.2nF: UV, OV Fault
6
GATE
GATE
Gate Slow Turn Off Delay
= 2.2nF, SHDN Falling, V = 12V
150
22
3
275
32
8
575
45
µs
IN
l
l
Gate Turn-On Delay Time
= 12V, Power Good to ΔV
> 0V
ms
µs
IN
GATE
Overcurrent Fault Propagation Delay
= 2.2nF, Overcurrent Fault to ΔV = 0V
GATE
18
p(GATE)
GATE
SENSE – V : 0 to +100mV, or
OUT
SENSE – V : 0 to –100mV (LTC4368-1)
OUT
SENSE – V : 0 to –10mV (LTC4368-2)
OUT
UV, OV
l
l
l
l
l
l
V
V
V
V
UV Input Threshold Voltage
OV Input Threshold Voltage
UV Input Hysteresis
UV Falling
OV Rising
492.5
492.5
20
500
500
25
507.5
507.5
32
mV
mV
mV
mV
nA
UV
OV
UVHYST
OVHYST
LEAK
OV Input Hysteresis
20
25
32
I
t
UV, OV Leakage Current
UV, OV Fault Propagation Delay
V = 0.5V, V = 60V
10
IN
Overdrive = 50mV, V = 12V
1
2
µs
FAULT
IN
SHDN
l
l
l
l
l
V
SHDN Input Threshold
SHDN Falling
0.4
400
20
0.75
1.2
15
V
nA
µs
SHDN
I
t
t
t
SHDN Input Current
SHDN = 10V, V = 60V
IN
SHDN
Delay Coming Out of Shutdown Mode
SHDN To FAULT Asserted
SHDN Rising to FAULT, V = 12V
800
1.5
32
1400
3
START
IN
V
IN
V
IN
= 12V
= 12V
µs
SHDN(F)
LOWPWR
Delay From Turn Off to Low Power
Operation
48
ms
FAULT
l
l
V
FAULT Output Voltage Low
FAULT Leakage Current
I
= 500µA, V = 12V
0.15
1
0.4
20
V
OL
FAULT
IN
I
FAULT = 5V, V = 60V
nA
FAULT
IN
RETRY
l
V
Configuration Threshold for GATE
Latch-Off
RETRY Falling to ΔI
V
> 2µA
0.5
1.5
V
RETRY
RETRY
CLEAR
RETRY
RETRY
= 12V
IN
l
l
I
t
t
Output Current for RETRY Timer
RETRY = 2V, V = 12V
RETRY = 0V, V = 12V
2.5
–10
3.5
–17
4.5
–25
µA
µA
IN
IN
l
Minimum SHDN Pulse to Clear Forward
Overcurrent RETRY Latch
RETRY = 0V, V = 12V
15
80
µs
IN
l
Forward Overcurrent Cool-Down Delay
FAULT Asserted to FAULT Released, C
SENSE = V
= 22nF
120
150
ms
RETRY
= V = 12V
IN
OUT
Note 1. Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All currents into pins are positive; all voltages are referenced to
GND unless otherwise noted.
Note 3. These pins can be tied to voltages below –0.3V through a resistor
that limits the current below 1mA.
Rev. B
4
For more information www.analog.com
LTC4368
TYPICAL PERFORMANCE CHARACTERISTICS
VIN Operating Current vs
VIN Supply Current vs Voltage
Temperature
VIN Shutdown Current vs Voltage
(–40V to 100V)
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢁ
ꢀ
SHDN ꢀ ꢁ.ꢂꢃ
SHDN
SHDN
ꢀ
ꢀꢁ
ꢀ ꢁ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢂ
ꢀꢁꢂꢂꢂ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢂꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁ.ꢂꢃ
ꢀꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢁ
VOUT Operating Current vs
Temperature
VOUT Shutdown Current vs
Temperature
VOUT Current vs Reverse VIN
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
SHDN ꢀ ꢁ.ꢂꢃ
ꢀꢁ
SHDN
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀ ꢁ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ ꢁ.ꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂ
ꢀ ꢁ.ꢂꢃ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅꢀ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢂ
GATE Drive vs GATE Current
GATE Drive vs VIN Supply Voltage
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ ꢁ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ ꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀ
ꢅꢉꢂꢈ
ꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢃ
Rev. B
5
For more information www.analog.com
LTC4368
TYPICAL PERFORMANCE CHARACTERISTICS
UV, OV Thresholds vs
∆VRR Threshold vs VOUT
FAULT Leakage vs Temperature
Temperature
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ ꢁ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄ
FAULT
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀ
ꢀꢁ
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ꢀ
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ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢅ
UV/OV Propagation Delay vs
Overdrive
FAULT Output Current vs Voltage
GATE Turn-On Delay Time vs VIN
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ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄ
SHDN
ꢀ
ꢂ ꢃꢄꢅꢆꢇ
ꢀ
ꢂ ꢃꢄꢅꢆꢇ
ꢁ
ꢁ
ꢀꢁꢂꢃ
ꢀ
ꢂ ꢃꢄꢅꢆ
ꢁ
ꢀꢁꢂꢃꢄ
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ꢀꢁꢂ
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ꢀꢁ
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ꢀ
ꢀꢁꢂ
ꢀꢁꢂRꢃRꢄꢁꢂ ꢅꢆꢁꢇ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢁ
ꢀꢁꢂꢃ ꢄꢅꢀ
AC Blocking
Turn-On Timing
Turn-Off Timing
ꢀ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂ
DUAL Si7942 MOSFET
100µF, 12Ω LOAD
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
V
= 12V
IN
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
V
= 12V
ꢀꢁꢂ
IN
DUAL Si7942 MOSFET
100µF, 12Ω LOAD
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉ
ꢊꢋꢌ ꢊꢍꢎꢏ ꢃꢐꢂꢀ ꢐꢑ ꢒ
ꢐꢁꢓ
SHDN
ꢀꢁꢂꢃꢄꢁ
SHDN
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢂ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆ
Rev. B
6
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LTC4368
PIN FUNCTIONS
Exposed Pad: The exposed pad may be left open or con-
nected to device ground.
current sink pulls down on the GATE output, thus quickly
disconnecting the load from the input. After a reverse cur-
rent fault, when V
falls 100mV below V , the LTC4368
OUT
IN
FAULT: Fault Indication Output. Connect to a pull-up resis-
tor. This high voltage open drain output is pulled low if
there is a voltage or current fault, if SHDN is low, or if
automatically turns on the external MOSFETs. A forward
overcurrent fault uses the RETRY pin to set the conditions
for reconnecting power to the load. Connect to VOUT if
unused.
V has not risen above V
. Leave unconnected if
IN
IN(UVLO)
unused.
SHDN: Shutdown Control Input. Assuming no voltage or
current faults, SHDN high enables the GATE charge pump
which in turn enhances the gate of the external N-channel
MOSFETs. A low on SHDN generates a pull down on the
GATE output with a 90µA current sink and places the
LTC4368 in low current mode (5µA). If a forward overcur-
rent condition latches off the external MOSFETs (RETRY
grounded), the SHDN pin must be toggled low then high
to re-enable the charge pump that enhances the external
GATE: Gate Drive Output for External N-channel MOSFETs.
An internal charge pump provides 35µA of pull-up current
and up to 13.1V of enhancement to the gate of an external
MOSFET. When turned off, GATE is pulled just below the
lower of V or V . When V goes negative, GATE is
IN
OUT
IN
automatically connected to V .
IN
GND: Device Ground.
OV: Overvoltage Comparator Input. Connect this pin to an
MOSFETs. If V goes above 80V, the SHDN pin voltage
IN
external resistive divider to set the desired V overvolt-
IN
must be kept below 80V.
age fault threshold. This input connects an accurate, fast
(1µs) comparator with a 0.5V rising threshold and 25mV
of hysteresis. When OV rises above its threshold, a 60mA
current sink pulls down on the GATE output. When OV
falls back below 0.475V, and after a 32ms GATE turn-on
delay waiting period, the GATE charge pump is enabled.
The low leakage current on this input allows the use of
large valued resistors for the external resistive divider.
Connect to GND if unused.
UV: Undervoltage Comparator Input. Connect this pin to
an external resistive divider to set the desired V under-
IN
voltage fault threshold. This input connects to an accu-
rate, fast (1µs) comparator with a 0.5V falling threshold
and 25mV of hysteresis. When UV falls below its thresh-
old, a 60mA current sink pulls down on the GATE output.
When UV rises back above 0.525V, and after a 32ms GATE
turn-on delay waiting period, the GATE charge pump is
enabled. The low leakage current on this input allows the
use of large valued resistors for the external resistive
RETRY: Retry or Latch-Off Selection Input. Connect to
ground to latch off the MOSFETs after a forward over-
current fault. To turn the external MOSFETs back on, the
SHDN pin must be toggled low then high. Connect RETRY
to an external capacitor to configure a 5.5ms/nF delay
before the MOSFETs automatically turn on again. Leave
unconnected if unused.
divider. If unused and V is less than 80V, connect to
IN
V with a 510k resistor.
IN
VIN: Power Supply Input. Maximum protection range:
–40V to 100V. Operating range: 2.5V to 60V. This pin
can be hot swapped and has a 2.2V UVLO.
SENSE: Overcurrent Sense Input. Connect a current
sense resistor between SENSE and VOUT. This input
detects overcurrent faults in both directions: forward
VOUT: Output Voltage Sense Input. Connect a current
sense resistor between VOUT and SENSE. The GATE
charge pump voltage is referenced to V . It is used as
OUT
at ΔV
= 50mV, and reverse at ΔV
= –50mV
the charge pump input when V
is greater than approxi-
SENSE
SENSE
mately 5V. The reverse currenOt UfaTult comparators require
(LTC4368-1 option) or ΔVSENSE = –3mV (LTC4368-2
option). When an overcurrent fault is detected, a 60mA
that V
rise above its 2.2V UVLO. V
cannot be hot
OUT
OUT
swapped with supplies above 24V. Place at least 1µF from
to GND.
V
OUT
Rev. B
7
For more information www.analog.com
LTC4368
BLOCK DIAGRAM
ꢅ
ꢖꢗꢒꢓ
ꢑꢓꢇꢑꢓ
ꢅ
ꢋꢉꢒ
ꢆꢇ
ꢔꢀꢌꢅ ꢒꢋ ꢕꢌꢌꢅ
ꢍꢌꢎꢅ
ꢤ
RꢓꢅꢓRꢑꢓ
ꢙRꢋꢒꢓꢚꢒꢆꢋꢇ
ꢔ
ꢤ
ꢔ
ꢤ
ꢔ
ꢋꢚꢢRꢓꢅ
ꢋꢚꢢꢡꢛꢄ
ꢤ
ꢔ
–
+
ꢍꢌꢎꢅ ꢥꢀꢁꢂꢃꢦꢕꢧ
ꢁꢎꢅ ꢥꢀꢁꢂꢃꢦꢈꢧ
ꢋꢅꢓRꢚꢉRRꢓꢇꢒ
ꢚꢋꢜꢙꢗRꢗꢒꢋRꢑ
ꢚꢊꢋꢑꢓꢑ ꢑꢛꢆꢒꢚꢏ
ꢛꢏꢓꢇ ꢅ ꢆꢑ ꢇꢓꢖꢗꢒꢆꢅꢓ
ꢅ
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ꢔ
ꢤ
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ꢆꢇ
RꢓꢅꢢRꢓꢑꢓꢒ
ꢆꢇ
ꢤ
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ꢔ
ꢊꢄꢋ
ꢆ
ꢖꢗꢒꢓ
ꢍꢅ
ꢅ
ꢁꢍꢘꢗ
ꢖꢗꢒꢓ
ꢚꢏꢗRꢖꢓ
ꢙꢉꢜꢙ
ꢋꢉꢒ
ꢓꢇꢗBꢊꢓ
ꢝ ꢞ ꢀꢌꢌꢟꢏꢠ
ꢕꢨꢘꢗ
ꢑꢒꢗRꢒ ꢒꢆꢜꢓR
ꢁꢕ ꢚꢐꢚꢊꢓꢑ
ꢑꢊꢋꢛ
ꢋꢡꢡ
ꢡꢗꢑꢒ
ꢋꢡꢡ
ꢡꢛꢄꢢRꢓꢑꢓꢒ
RꢓꢒRꢐ
ꢁ.ꢍꢘꢗ
ꢣꢌꢘꢗ
ꢂꢌꢎꢗ
ꢖꢗꢒꢓ ꢙꢉꢊꢊꢄꢋꢛꢇ
ꢊꢋꢖꢆꢚ
ꢡꢋRꢛꢗRꢄ ꢋꢅꢓRꢚꢉRRꢓꢇꢒ
ꢒꢆꢜꢓR
SHDN
ꢅ
ꢆꢇ
ꢄꢓꢊꢗꢐ ꢒꢆꢜꢓRꢑ
ꢊꢋꢖꢆꢚ
ꢈ.ꢈꢅ
ꢉꢅꢊꢋ
ꢉꢅ
–
FAULT
+
ꢌ.ꢍꢅ
ꢋꢅ
ꢈꢍꢎꢅ
ꢏꢐꢑꢒꢓRꢓꢑꢆꢑ
+
–
ꢌ.ꢍꢅ
ꢖꢇꢄ
ꢀꢁꢂꢃ Bꢄ
Rev. B
8
For more information www.analog.com
LTC4368
OPERATION
Many of today’s electronic systems get their power from
external sources such as wall adapters, batteries and cus-
tom power supplies. Figure 1 shows a supply arrange-
ment using a DC barrel connector. Power is supplied by
an AC adapter or, if the plug is withdrawn, by a removable
battery. Note that the polarity of the AC adapter and barrel
connector varies by manufacturer. Trouble arises when
any of the following occurs:
of a single catastrophic event, or over time as devices
degrade from repeated overstress.
The LTC4368 limits these errant overvoltage and overcur-
rent conditions and helps extend the life of the electronic
systems it protects. When the part detects an overcurrent
or overvoltage fault, it isolates the input supply from the
load by turning off the external back-to-back MOSFETs.
The LTC4368 provides accurate overvoltage and under-
voltage comparators to ensure that power is applied to
the load only if the input supply meets the user selectable
voltage window. Additionally, two accurate overcurrent
comparators disconnect the load from the supply when
excessive current flows in either the forward (+50mV/
•
•
•
•
•
•
The battery is installed backwards
A wall adapter of opposite polarity is attached
A wall adapter of excessive voltage is attached
A wall adapter with an AC output is attached
The battery is discharged below a safe level
R
) or reverse (–50mV or –3mV/R
) direction.
SENSE
SENSE
Reverse supply voltage protection circuits automatically
isolate the load from negative input voltages. During nor-
mal operation, a high voltage charge pump enhances the
gate of dual external N-channel power MOSFETs, thus
providing a low loss path for qualified power. Power con-
sumption is 5µA during shutdown and 80µA while operat-
ing. The LTC4368 integrates all these functions in small
10-lead 3mm × 3mm DFN and MSOP packages.
The load or the input is shorted to ground or to
another supply
•
Excessive current flows from the supply to the load
or from the load to the supply
These conditions, if unchecked, can damage electronic
systems and their connectors. Damage can take the form
BꢐꢝꢓꢐRꢉꢏꢈꢐꢌꢑꢇꢘ
ꢌꢄꢉRꢏꢔRRꢉꢑꢈ ꢎRꢌꢈꢉꢏꢈꢐꢌꢑ
ꢀꢁꢂꢃꢄ
ꢅꢋꢂꢄ ꢈꢌ ꢍꢂꢂꢄ ꢎRꢌꢈꢉꢏꢈꢐꢌꢑ Rꢇꢑꢒꢉ
ꢞꢍ
ꢞꢚ
+
ꢚ.ꢁꢄ ꢈꢌ ꢛꢂꢄ
ꢐꢑRꢔꢗꢖ
ꢌꢎꢉRꢇꢈꢐꢑꢒ Rꢇꢑꢒꢉ ꢏꢌꢑꢈRꢌꢘ
ꢅꢆꢃꢄ
ꢘꢌꢇꢓ
ꢏꢐRꢏꢔꢐꢈ
ꢇꢏ
ꢇꢓꢇꢎꢈꢉR
ꢐꢑꢎꢔꢈ
R
BꢇꢈꢈꢉRꢊ
ꢒꢇꢈꢉ
ꢏ
ꢒꢇꢈꢉ
–
ꢒꢇꢈꢉ
ꢗꢉꢑꢗꢉ
ꢄ
ꢌꢔꢈ
ꢄ
ꢐꢑ
Rꢋ
Rꢆ
Rꢚ
SHDN
ꢔꢄ
ꢌꢄꢕ ꢔꢄ ꢎRꢌꢈꢉꢏꢈꢐꢌꢑ
ꢈꢖRꢉꢗꢖꢌꢘꢓꢗ ꢗꢉꢈ ꢈꢌ
ꢗꢇꢈꢐꢗꢙꢊ ꢘꢌꢇꢓ ꢏꢐRꢏꢔꢐꢈ
ꢘꢈꢏꢋꢆꢛꢜꢝꢚ
FAULT
ꢌꢄ
RꢉꢈRꢊ
ꢏ
Rꢍ
ꢒꢑꢓ
RꢉꢈRꢊ
ꢋꢆꢛꢜ ꢙꢂꢍ
Figure 1. Polarity Protection for DC Barrel Connectors
Rev. B
9
For more information www.analog.com
LTC4368
APPLICATIONS INFORMATION
+50mV
0.004Ω
M1
M2
V
PSMN4R8-100BSE SiR662
OUT
V
IN
7V TO 36V
24V
INRUSH
CONTROL
–0.75A TO 12.5A
–3mV
22k
2.2nF
GATE
SENSE
V
OUT
V
IN
R4
464k
SHDN
UV
R3
1500k
OV = 36V
UV = 7V
LTC4368-2
FAULT
1200ms COOLDOWN
AFTER FORWARD
OC FAULT
R2
121k
OV
RETRY
R1
29.4k
0.22µF
GND
4368 F02
Figure 2. LTC4368-2 Protects Load from Voltage (–40V to 100V) and Current (–0.75A to 12.5A) Faults
The LTC4368 is an N-channel MOSFET controller that pro-
GATE Drive
tects a load from overvoltage faults (both positive and
negative) and from overcurrent faults (both forward and
reverse). A typical application circuit using the LTC4368-2
is shown in Figure 2. The circuit provides a low loss con-
The LTC4368 turns on the external N-channel MOSFETs
by driving the GATE pin above V . The voltage differ-
OUT
ence between the GATE and V
pins (gate drive) is a
OUT
function of V and V
.
IN
OUT
nection from V to V
as long as there are no voltage
IN
OUT
Figure 3 highlights the dependence of the gate drive on
VIN and VOUT. When system power is first turned on
or current faults.
Voltages at VIN outside of the 7V to 36V range are
prevented from getting to the load and can be as high as
100V and as negative as –40V. Load currents (including
(SHDN low to high, SENSE = V
= 0V), gate drive is
at a maximum for all values of OVUT. This helps prevent
IN
startup problems into heavy loads by ensuring that there
is enough gate drive to support the load.
inrush currents) above 12.5A (forward from V to V
)
IN
OUT
and below –0.75A (reverse from VOUT to VIN) will cause the
14
load to be disconnected from V . The circuit of Figure 2
IN
T
GATE
= 25°C
= –1µA
A
I
protects against negative voltages at V as shown. Note
IN
12
10
8
V
= 12V, 60V
IN
that the SOA and voltage requirements are not the same
for the two external MOSFETs. During power-up, the input
MOSFET (M1) will stand off more voltage (up to V ) than
IN
V
IN
= 5V
the output MOSFET (M2). The body diode of M2 will limit
its drain to source voltage. This allows the use of smaller
MOSFETs at the output.
6
V
= 3.3V
IN
4
V
= 2.5V
IN
2
During normal operation, the LTC4368 provides up to
13.1V of gate enhancement to the external back-to-back
N-channel MOSFETs. This turns on the MOSFETs, thus
0
15
0
5
10
V
(V)
OUT
4365 F03
connecting the load at V
to the supply at V .
OUT
IN
Figure 3. Gate Drive (GATE – VOUT) vs VOUT
Rev. B
10
For more information www.analog.com
LTC4368
APPLICATIONS INFORMATION
As VOUT ramps up from 0V, the absolute value of the GATE
The external resistive divider allows the user to select
an input supply range that is compatible with the load
voltage remains fixed until V
is greater than the lower
crosses this threshold,
OUT
OUT
at V . Furthermore, the UV and OV inputs have very
of (V – 1V) or 5V. Once V
OUT
IN
low leakage currents (typically < 1nA at 100°C), allow-
ing for large values in the external resistive divider. In
the application of Figure 4, the load is connected to the
gate drive begins to increase up to a maximum of 13.1V.
The curves of Figure 3 were taken with a GATE load of
–1µA. If there were no DC load on GATE, the gate drive
supply only if V lies between 3.5V and 18V. In the event
for each V would be slightly higher.
IN
IN
that V goes above 18V or below 3.5V, the gate of the
IN
Note that when V is at the lower end of the operating
IN
external N-channel MOSFET is immediately discharged
with a 60mA current sink, thus isolating the load from
the supply.
range, the external N-channel MOSFET must be selected
with a correspondingly lower threshold voltage.
Overvoltage and Undervoltage Protection
Figure 5 shows the timing associated with the UV pin.
Once a UV fault propagates through the UV comparator
(tFAULT), the FAULT output is asserted low and a 60mA
The LTC4368 provides two accurate comparators to moni-
tor for overvoltage (OV) and undervoltage (UV) conditions
at V . If the input supply rises above the user adjust-
ableINOV threshold, the gates of the external MOSFETs
are quickly turned off, thus disconnecting the load from
the input. Similarly, if the input supply falls below the
user adjustable UV threshold, the gates of the external
MOSFETs are quickly turned off. Figure 4 shows a UV/OV
application for an input supply of 12V.
current sink discharges the GATE pin. As V
falls, the
OUT
GATE pin tracks V
.
OUT
ꢒ
ꢒ
ꢓ ꢒ
ꢌꢒ ꢌꢒꢔꢕꢐꢉ
ꢌꢒ
ꢌꢒ
ꢋ
ꢄꢈꢌꢍꢉ
FAULT
ꢋ
ꢋ
ꢎꢏꢄꢈꢐꢉꢑ
ꢎꢏꢖꢗꢑ
ꢚꢆꢓꢍꢉꢎꢌ
ꢊꢘꢉꢊRꢗꢈꢍ ꢗꢙꢚꢔꢈꢗꢗꢊꢍ ꢛꢖꢐꢄꢊꢉꢐ
ꢉꢌRꢗ ꢖꢄꢄ
ꢃꢄꢀ
ꢀ
ꢁꢂ
ꢇꢈꢉꢊ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢅꢀ
Rꢉ
ꢃꢌꢄꢐꢝ
ꢓꢋꢛꢜꢔRꢔꢆꢋR
–
ꢅꢀ
Figure 5. UV Timing (OV < (VOV – VOVHYST), SHDN > 1.2V)
ꢅꢀ ꢈ ꢉ.ꢊꢀ
ꢆꢇ
ꢄꢊꢘꢀ
ꢋꢀ
+
Figure 6 shows the timing associated with the OV pin.
Once an OV fault propagates through the OV comparator
(tFAULT), the FAULT output is asserted low and a 60mA
Rꢄ
ꢐ.ꢊꢀ
ꢑꢁꢒꢓꢇꢔRꢕꢖ ꢕꢔꢆꢖ
ꢗꢁꢆꢇ ꢎꢐꢘꢔ ꢒꢁꢂꢙ
ꢄꢍꢉꢝ
ꢓꢋꢛꢜꢔRꢔꢆꢋR
ꢋꢀ
ꢋꢀ ꢈ ꢃꢌꢀ
ꢆꢇ
+
current sink discharges the GATE pin. As V
falls, the
OUT
ꢄꢊꢘꢀ
GATE pin tracks V
.
Rꢃ
ꢊꢞꢝ
OUT
ꢐ.ꢊꢀ
–
ꢏ
ꢐꢏ
ꢐꢏ
ꢏ
ꢑ ꢏ
ꢐꢏꢒꢓꢍꢊ
ꢐꢏ
ꢍꢉꢎꢌ ꢏꢐꢍ
ꢆ
ꢄꢇꢈꢉꢊ
Figure 4. UV, OV Comparators Monitor 12V Supply
FAULT
ꢆ
ꢆ
ꢋꢌꢐꢔꢎ
ꢋꢌꢄꢇꢍꢊꢎ
ꢕꢖꢊꢕRꢔꢇꢉ ꢔꢗꢘꢒꢇꢔꢔꢕꢉ ꢙꢐꢍꢄꢕꢊ
ꢊꢈRꢔꢍ ꢐꢄꢄ
ꢚꢇꢊꢕ
ꢀꢁꢂꢃ ꢄꢅꢂ
Figure 6. OV Timing (UV > (VUV + VUVHYST), SHDN > 1.2V)
Rev. B
11
For more information www.analog.com
LTC4368
APPLICATIONS INFORMATION
When both the UV and OV faults are removed, the exter-
nal MOSFETs are not immediately turned on. The input
supply must remain within the user selected power good
window for typically 32ms (tD(ON)) before the load is again
connected to the supply. This recovery timeout period
filters noise (including line noise) at the input supply and
prevents chattering of power at the load.
The example of Figure 4 uses standard 1% resistor values.
The following parameters were selected:
V
I
= 3mV
OS(UV)
= 10nA
UV
UV = 3.5V
TH
OV = 18V
TH
Procedure for Selecting UV/OV External Resistor Values
The resistor values can then be solved:
3mV
The following 3-step procedure helps select the resistor
values for the resistive divider of Figure 4. This procedure
minimizes UV and OV offset errors caused by leakage
currents at the respective pins.
1. R1+ R2 =
= 300k
10nA
3mV
2. R3 = 2 •
• (3.5V – 0.5V) = 1.8M
10nA
1. Choose maximum tolerable offset at the UV pin,
V
. Divide by the worst case leakage current at
OS(UV)
The closest 1% value: R3 = 1.82M
the UV pin, I (10nA). Set the sum of R1 + R2 equal
UV
300k + 1.82M
to V
divided by 10nA. Note that due to the pres-
OS(UV)
3. R1 =
= 58.9k
ence of R3, the actual offset at UV will be slightly
2 • 18V
lower.
The closest 1% value: R1 = 59K
R2 = 300K – 59K = 241K
V
OS(UV)
R1+ R2 =
I
UV
The closest 1% value: R2 = 243K
Therefore: OV = 17.93V, UV = 3.51V.
2. Select the desired V UV trip threshold, UV . Find
IN
TH
the value of R3:
Limiting Inrush Current During Turn On
⎛
⎜
⎝
⎞
V
UV – 0.5V
OS(UV)
TH
R3 =
•
⎟
Charging large capacitors on V
can lead to excessive
OUT
I
0.5V
⎠
UV
inrush currents when LTC4368 turns on the external
N-channel MOSFET. The maximum slew rate at the GATE
pin can be reduced by adding a capacitor on the GATE pin:
3. Select the desired V OV trip threshold, OV . Find
IN
TH
the values of R1 and R2:
I
GATE(UP)
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
V
Slew Rate =
OS(UV)
+R3
C
GATE
I
UV
R1 =
R2 =
• 0.5V
OV
TH
V
OS(UV)
– R1
I
UV
Rev. B
12
For more information www.analog.com
LTC4368
APPLICATIONS INFORMATION
Since the MOSFET acts like a source follower, the slew
Forward Overcurrent Fault
Forward overcurrent protection prevents large currents
from flowing from V to V . This threshold current is
rate at V
equals the slew rate at GATE. Therefore, the
OUT
inrush current due to the capacitance on VOUT is given by:
IN
OUT
determined by the external sense resistor (R
) and an
C
SENSE
OUT
I
=
•I
GATE(UP)
INRUSH
internal comparator (Figure 7, U1) with a 50mV threshold:
C
GATE
50mV
I
=
For example, a 1A inrush current into a 100µF output
capacitance requires a GATE capacitance of (using
GATE(UP)
OC,FWD
R
SENSE
I
= 35µA):
For the example of Figure 7, if 2.5A flows to the output
across the 20mΩ sense resistor, the external MOSFETs
(M1, M2) are immediately (8µs) turned off. This discon-
nects the load from the input supply.
35µA • C
OUT
C
C
=
=
GATE
I
INRUSH
35µA • 100µF
1A
Note that during initial startup, the output capacitance
(COUT) charges from ground to VIN. To prevent this
capacitive inrush current (I
ing the forward overcurrent comparator, place an inrush
limiting capacitor (C ) on the GATE pin (see Limiting
Inrush Current During Turn On). This inrush current plus
the output current must be less than the desired forward
overcurrent threshold:
= 3.5nF
GATE
) from falsely trigger-
INRUSH
The 3.3nF CGATE capacitor in the application circuit of
Figure 7 limits the inrush current to just over 1A. R
GATE
GATE
prevents C
from slowing down the reverse polarity
protection GcAirTcEuits. It also stabilizes the fast pull-down
circuits and prevents chatter during fault conditions. Set
R
GATE
to 22k for most applications.
2.5A
I
> I
+ I
OC,FWD
INRUSH OUT
FDS3992
R
SENSE
100V DUAL
I
< 2.5A
I
OUT
0.02Ω
For the example of Figure 7, the 3.3nF GATE capacitor
and the 100µF output capacitor limit the inrush current
(IINRUSH) to approximately 1A. This means that the output
M1
M2
V
IN
24V
R
GATE
22k
+
–0.15A
C
OUT
100µF
OUT
INRUSH
CONTROL:
~1A
C
3.3nF
GATE
current (I ) must be less than 1.5A during turn on in
OUT
order to avoid a forward overcurrent fault during turn on.
V
IN
GATE
SENSE
V
OUT
Once V
has ramped to its final value, the output cur-
OUT
50mV
rent is limited to 2.5A.
TURN OFF
MOSFETS
–
+
–
+
+
–
U2
U1
Once a forward overcurrent fault is triggered, there are
two application choices for turning the external MOSFETs
back on:
+
3mV
–
TURN MOSFETS
BACK ON
–
+
V
V
OUT
U3
LTC4368-2
+
100mV
–
IN
1. Automatically restart by placing an external capaci-
tor on the RETRY pin. An internal cool-down timer
will charge/discharge this capacitor 31 times with
a 5.5ms/nF total delay. At the end of this delay, the
external MOSFETs are turned back on, thus reconnect-
ing the load to the input supply. The 0.22µF capaci-
tor (CRETRY) in the application of Figure 7 yields a
1200ms cool-down timer delay. Note that the adjust-
able cool-down period provides the user with a means
of keeping the external MOSFETs within the rated SOA
START
TIMER
TURN MOSFETS
BACK ON AFTER
31 CYCLES
31 CYCLES
SHDN
RETRY
RESET FORWARD
OC LATCH
C
RETRY
0.22µF
OC FORWARD TIMER/LATCH
4368 F07
Figure 7. Overcurrent Comparators Monitor 2.5A/–0.15A
Current Faults
(safe operating area). See Figure 8 timing diagram.
Rev. B
13
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LTC4368
APPLICATIONS INFORMATION
2. Latch off the MOSFETs by grounding the RETRY pin
(no external RETRY capacitor needed). This latches
the forward overcurrent fault. The external MOSFETs
are kept in the off condition until the SHDN input pin is
toggled low then high (tCLEAR pulse width < tLOWPWR).
See Figure 9 timing diagram.
ꢜꢔꢕꢄ
ꢛ
ꢀꢁꢂꢀꢁ ꢃ ꢄ
ꢅꢆꢇ
ꢛꢂRꢆꢀꢞ
ꢒꢛꢟꢛꢇꢁꢘ
ꢔꢕꢄ
ꢀꢇꢁꢍꢘꢈ ꢀꢇꢍꢇꢁ ꢒꢅꢍꢘ
ꢀꢇꢁꢍꢘꢈ ꢀꢇꢍꢇꢁ ꢒꢅꢍꢘ
ꢉ
ꢊꢋꢌꢍꢇꢁꢎ
ꢁꢝꢇꢁRꢂꢍꢒ ꢂꢗꢑꢞꢍꢂꢂꢁꢒ
ꢟꢅꢀꢠꢁꢇꢖ ꢇꢆRꢂ ꢅꢠꢠ
ꢌꢍꢇꢁ
RꢁꢇRꢈ
FAULT
ꢁꢝꢇꢁRꢂꢍꢒ ꢂꢗꢑꢞꢍꢂꢂꢁꢒ
ꢟꢅꢀꢠꢁꢇꢖ ꢇꢆRꢂ Bꢍꢑꢡ ꢅꢂ
ꢏꢐ ꢑꢈꢑꢒꢁꢀ
ꢋꢐꢓꢔꢔꢕꢖ ꢑꢅꢅꢒꢗꢘꢅꢙꢂ ꢚꢁRꢛꢅꢘꢎ
Reverse Overcurrent Protection
ꢉ
RꢁꢇRꢈ
Reverse overcurrent protection prevents large currents
from flowing from V
to V . There are two options for
OUT
IN
reverse overcurrent protection thresholds. The LTC4368-1
(–50mV) bidirectional circuit breaker allows load current
ꢢꢏꢣꢤ ꢠꢔꢤ
Figure 8. Forward Overcurrent Fault with 0.22µF RETRY Capacitor
to flow in either direction: from V to V
or from V
to VIN. The LTC4368-2 providesINdiodeO-lUikTe behaviorObUyT
making the reverse overcurrent threshold (–3mV) sig-
nificantly smaller than the forward overcurrent thresh-
old (+50mV). The reverse overcurrent fault threshold is
ꢖꢅꢗꢊ
ꢞ
ꢆꢇꢈꢆꢇ ꢉ ꢊ
ꢋꢌꢍ
ꢞꢈRꢌꢆꢚ
ꢐꢞꢛꢞꢍꢇꢟ
ꢅꢗꢊ
ꢆꢍꢇꢑꢟꢠ ꢆꢍꢑꢍꢇ ꢐꢋꢑꢟ
ꢆꢍꢇꢑꢟꢠ ꢆꢍꢑꢍꢇ ꢐꢋꢑꢟ
ꢎ
ꢡꢢꢕꢑꢍꢇꢣ
determined by the external sense resistor (R
) and
SENSE
ꢇꢘꢍꢇRꢈꢑꢐ ꢈꢙꢏꢚꢑꢈꢈꢇꢐ
ꢛꢋꢆꢄꢇꢍꢜ ꢍꢌRꢈ ꢋꢄꢄ
ꢕꢑꢍꢇ
SHDN
FAULT
ꢇꢘꢍꢇRꢈꢑꢐ ꢈꢙꢏꢚꢑꢈꢈꢇꢐ
ꢛꢋꢆꢄꢇꢍꢜ ꢍꢌRꢈ Bꢑꢏꢝ ꢋꢈ
an internal comparator (Figure 7, U2). For the LTC4368-2
application of Figure 7:
–3mV
–3mV
I
=
=
= –0.15A
OC,REV
R
20mΩ
SENSE
ꢎ
ꢎ
ꢒ ꢎ ꢒ ꢎ
ꢏꢐꢇꢑR ꢐꢋꢓꢔꢓR
If –0.15A flows from the output across the 20mΩ sense
resistor, the external MOSFETs (M1,M2) are immediately
(8µs) turned off.
ꢀꢁꢂꢃ ꢄꢅꢃ
To turn the MOSFETs back on, an internal comparator
Figure 9. Forward Overcurrent Fault with RETRY Pin Grounded
(Figure 7, U3) detects when V
drops 100mV below
OUT
V :
IN
ꢄꢓꢍꢗꢎ
ꢇꢎꢈꢓꢟꢠ ꢇꢎꢓꢎꢈ ꢗꢌꢓꢟ
ꢆꢕꢋ
ꢊꢁꢕꢋ
V
OUT
< V – 100mV
IN
ꢞ
ꢞꢉRꢍꢇꢚ
ꢗꢞꢛꢞꢎꢈꢟ
ꢇꢈꢉꢇꢈ ꢊ ꢋ
ꢌꢍꢎ
Once this condition is met, the gates of the external
MOSFETs are turned on again to reconnect the input sup-
ply to the load. See timing diagrams of Figure 10. Note
that if the LTC4368-1 option is used, the reverse current
threshold becomes:
ꢏ
ꢐꢑꢒꢓꢎꢈꢔ
ꢅꢅꢋ
ꢒꢓꢎꢈ ꢊ ꢋ
ꢌꢍꢎ
ꢆꢋ
ꢈꢖꢎꢈRꢉꢓꢗ ꢉꢘꢙꢚꢓꢉꢉꢈꢗ
ꢛꢌꢇꢄꢈꢎꢜ ꢎꢍRꢉ Bꢓꢙꢝ ꢌꢉ
ꢋ
ꢊ ꢅꢆꢆꢕꢋ
ꢞꢉ
ꢋ
ꢌꢍꢎ
–50mV
I
=
OC,REV
R
SENSE
FAULT
ꢀꢁꢂꢃ ꢄꢅꢆ
Figure 10. Reverse Overcurrent Fault: SENSE – VOUT < –3mV
(LTC4368-2)
Rev. B
14
For more information www.analog.com
LTC4368
APPLICATIONS INFORMATION
Reverse V Protection
parasitic inductance of the V and GATE connections, the
IN
voltage at the V and GATEIpNins ring significantly below
IN
The LTC4368’s rugged and hot swappable V helps pro-
IN
–20V. Therefore, hot swapping a negative input voltage
more negative than –20V should not be performed with-
out additional overshoot mitigation techniques in place.
The front page application was used to generate the wave-
forms of Figure 12.
tect the more sensitive circuits at the output load. If the
input supply is plugged in backwards, or a negative sup-
ply is inadvertently connected, the LTC4368 prevents this
negative voltage from passing to the output load.
As shown in Figure 11, external back-to-back N-channel
MOSFETs are required for reverse supply protection. When
V goes negative, the reverse V comparator closes the
ꢀ
ꢀꢁꢂ
IN
IN
internal switch, which in turn connects the gates of the
external MOSFETs to the negative V voltage. The body
ꢀꢁꢂꢃꢄꢁ
IN
ꢀꢁꢂꢃ
diode (D1) of M1 turns on, but the body diode (D2) of M2
remains in reverse blocking mode. This means that the
common source connection of M1 and M2 remains about
ꢀꢁꢂꢃ
ꢀ
ꢀꢁ
a diode drop higher than V . Since the gate voltage of
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢈꢉ
IN
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
M2 is shorted to V , M2 will be turned off and no current
IN
Figure 12. Hot Swapping VIN to –20V
can flow from V
to V . Note that the voltage rating of
OUT
IN
M2 must withstand the reverse voltage excursion at V .
IN
The speed of the LTC4368 reverse protection circuits is
ꢋꢌꢍꢎꢄꢏ ꢐꢅꢅꢀ ꢊꢑꢉꢈ
ꢊꢐ
ꢊꢏ
evident by how closely the GATE pin follows V during
IN
the negative transients. The two waveforms are almost
ꢛꢐ
ꢛꢏ
ꢀ
ꢆꢇ
ꢁꢂ
indistinguishable on the scale shown.
ꢃꢄꢅꢀ
ꢈꢇꢉꢊ
ꢁꢂRꢑꢋꢙ
+
ꢒ
ꢒꢇꢂꢆRꢇꢈ
ꢇꢑꢆ
ꢒ
ꢙꢇꢆꢋꢜꢉꢝ
ꢞꢇꢝꢆꢁꢇꢂꢉꢈ
ꢄ.ꢄꢘꢔꢟ
The trace at V , on the other hand, does not respond
ꢐꢅꢅꢓꢔ
OUT
R
ꢏꢏꢚ
ꢖꢉꢆꢕ
to the negative voltage at V , demonstrating the desired
reverse supply protection. ITNhe waveforms of Figure 12
were captured using a 40V dual N-channel MOSFET, a
10µF ceramic output capacitor and no load current on
ꢒ
ꢖꢉꢆꢕ
ꢗ.ꢗꢘꢔ
ꢀ
ꢖꢉꢆꢕ
ꢋꢕꢂꢋꢕ
ꢀ
ꢇꢑꢆ
ꢁꢂ
V
.
OUT
RꢕꢀꢕRꢋꢕ ꢀ
ꢁꢂ
LTC4368
ꢒꢇꢛꢝꢉRꢉꢆꢇR
Hot Swap V Protection
ꢃ
IN
ꢠ
The V input of the LTC4368 can be live inserted or hot
ꢒꢈꢇꢋꢕꢋ ꢋꢜꢁꢆꢒꢙ
IN
ꢜꢙꢕꢂ ꢀ ꢁꢋ ꢂꢕꢖꢉꢆꢁꢀꢕ
ꢖꢂꢊ
ꢁꢂ
swapped into a backplane with minor disturbance to the
ꢄꢗꢡꢢ ꢔꢐꢐ
V supply. The idea is to keep the parasitic capacitances
IN
Figure 11. Reverse VIN Protection Circuits
of the external MOSFETs (C ) from coupling onto the
GATE pin and enhancing tGhDe MOSFETs. To improve
positive VIN hot swap capability (without jeopardizing
To avoid large currents when the reverse voltage is hot
plugged, set RGATE to 22k. To further improve reverse
hot swap performance, place the optional C
4.4nF capacitor across the gate and source terminals of
the external MOSFETs.
reverse polarity protection), place C
across the
HOTSWAP
≥
HOTSWAP
gate and source terminals of the back-to-back MOSFETs.
Figure 13 illustrates the waveforms that result when
the V of the front page application is hot plugged to
IN
Figure 12 illustrates the waveforms that result when V
+48V. The top trace is V . The bottom two traces are the
IN
IN
is hot plugged to –20V. V , GATE and V
start out at
MOSFETs gate and source terminals. Note that the bottom
two traces ring together and thus keep the MOSFETs off
IN
OUT
ground just before the connection is made. Due to the
Rev. B
15
For more information www.analog.com
LTC4368
APPLICATIONS INFORMATION
Slow Shutdown
ꢀ
ꢀꢁ
The SHDN input turns off the external MOSFETs in a
slow, controlled manner. When SHDN is asserted low, a
90µA current sink slowly begins to turn off the external
MOSFETs.
ꢀꢁꢂꢃꢄꢅꢂ
ꢀRꢁꢁꢂ ꢃꢄꢅꢆꢇꢈ ꢉꢅꢊꢋꢁꢄ ꢀꢌꢄꢁ
Bꢀꢁꢂ ꢃBꢄꢅꢅꢄꢆꢇꢈ ꢆꢄꢉꢊꢂꢅ ꢉꢄꢁRꢋꢂ
Once the voltage at the GATE pin falls below the voltage
at the V
pin, the current sink is throttled back and a
OUT
ꢀꢁꢂꢃ ꢄꢅꢁ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
feedback loop takes over. This loop forces the GATE volt-
age to track V , thus keeping the external MOSFETs off
OUT
Figure 13. Hot Swapping VIN to +48V
as V
decays. Note that when V
pin is pulled all the way to ground.
< 2.5V, the GATE
OUT
OUT
during the fast transients. To further improve positive
hot swap, place the optional C = 6.8nF capacitor
Slow gate turn off reduces load current slew rates and
mitigates voltage spikes due to parasitic inductances. To
further decrease GATE pin slew rate, place a capacitor
HOTSWAP
across the gate/source of the external MOSFETs. For even
more hot swap protection, add a diode (MBR0540) across
(C
, see Figure 11) across the gate and source
HOTSWAP
R
GATE
(connect cathode to C
). Make sure this diode
GATE
terminals of the external MOSFETs. The waveforms of
Figure 15 were captured using the Si7942 Dual N-channel
MOSFETs, and a 2A load with 100µF output capacitor.
has a reverse breakdown of at least 40V.
Recovery Delay Timer
The LTC4368 has a recovery delay timer that filters noise
at V and helps prevent chatter at V . After either an OV
100µF, 6Ω LOAD ON V
OUT
ꢀꢁꢂꢃ
DUAL Si7942 MOSFET
ꢀ ꢁꢂꢃ
IN
OUT
ꢀ
ꢀꢁ
or UV fault has occurred, the input supply must return to
the desired operating voltage window for typically 32ms
ꢀ
ꢀꢁꢂ
(t ) in order to turn the external MOSFET back on, as
D(ON)
ꢀꢁꢂꢃꢄꢁ
illustrated in Figure 5 and Figure 6. Going out of and then
back into fault in fewer than 32ms will keep the MOSFET
off continuously. Similarly, coming out of shutdown (SHDN
SHDN
ꢀꢁꢂ
low to high) triggers an 800µs startup delay timer (t
see Figure 16).
,
START
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
The recovery delay timer is also active while the LTC4368
is powering up. The 32ms timer starts once VIN rises
Figure 15. Slow Shutdown: GATE Tracks VOUT as VOUT Decays
above V
and V lies within the user selectable
IN(UVLO)
IN
UV/OV power good window. See Figure 14.
SHDN
ꢇ
ꢇ
ꢊꢂꢁRꢂ
ꢈꢉꢊꢋꢅꢌꢍ
ꢎ
ꢑꢎ
ꢎ
ꢏꢍ
ꢎ
ꢏꢍꢐꢑꢎꢒꢋꢓ
ꢀꢁꢂꢃ
Δꢄ
ꢀꢁꢂꢃ
ꢔ
ꢕꢐꢋꢍꢓ
ꢀꢁꢂꢃ ꢎ ꢄ
ꢅꢆꢂ
ꢆꢇꢈꢉ
ꢊꢋꢌꢄꢉꢈ ꢋꢄꢄ
ꢊꢋꢌꢄꢉꢈ ꢋꢍ
ꢄ
ꢅꢆꢂ
ꢀꢁꢂꢃ ꢄꢅꢀ
ꢇ
ꢊꢏꢈꢐꢉꢑꢍ
Figure 14. Recovery Timing During Power-On
OV = GND, UV = SHDN = VIN
FAULT
ꢒꢓꢔꢕ ꢑꢖꢔ
Figure 16. Slow Shutdown Timing
Rev. B
16
For more information www.analog.com
LTC4368
APPLICATIONS INFORMATION
FAULT Status
By driving the SHDN pins separately, this potential back-
flow can be avoided. VOUT can then be selected from either
V1 or V2, irrespective of which supply voltage is higher or
lower. While in shutdown, the LTC4368-2 drives the GATE
The FAULT high voltage open drain output is driven low
if SHDN is asserted low, if V is outside the desired UV/
IN
OV voltage window, if there is an overcurrent fault, or if
pin just below the lower of V and V , thus allowing
IN
OUT
V has not risen above V
. Figures 5, 6, 8, 9, 10
IN
IN(UVLO)
V
to be larger than V while in the off condition.
OUT
IN
and 16 show the FAULT output timing.
Single MOSFET Higher Power Application
Ideal Diode Alternative
When reverse V protection is not needed, only a single
IN
Figure 17 shows two LTC4368-2 connected in parallel.
With both devices turned on, the output will be the higher
of V1 or V2. Unlike ideal diode controllers, the LTC4368
always fully enhances the MOSFETs, even at light loads.
Note, however, that if the voltage difference between V1
and V2 is less than 3mV, the reverse overcurrent com-
parators will not detect a fault and up to 150mA can flow
from the higher to the lower supply. Similarly, disconnect-
ing the higher supply may not generate sufficient reverse
current to turn off the MOSFETs. A subsequent reconnec-
tion may result in an inrush current that temporarily trips
the circuit breakers.
external N-channel MOSFET is necessary. This provides
the user with a larger selection of MOSFETs (not just dual
packages), especially for higher power applications. Note
that care must be taken to stay within the SOA of the
external MOSFET. The RETRY pin of the LTC4368 can be
used to help keep the MOSFET within its SOA. The user
can ground the RETRY pin to latch off the MOSFET after a
forward current fault. For automatic retry after a forward
current fault, C
must be large enough to maintain a
RETRY
low on duty cycle for the MOSFET. See Figure 18.
+50mV
V
I
OUT
OUT
PSMN4R8-100BSE 0.003Ω 3.5V TO 18V –1A TO 16.67A
V
IN
MOSFETs TURN OFF WHEN REVERSE CURRENT EXCEEDS –150mA
12V
R
INRUSH
CONTROL
SENSE
+
–3mV
0.02Ω
22k
100µF
V1
2.2nF
–3mV
SENSE
GATE
SENSE
V
OUT
V
IN
GATE
V
OUT
V
IN
453k
1330k
243k
SHDN
UV
SEL V1
SHDN
V
OUT
LTC4368-2
FAULT
LTC4368-2
1200ms COOLDOWN
AFTER FORWARD
OC FAULT
MOSFETs TURN OFF WHEN REVERSE CURRENT EXCEEDS –150mA
OV
RETRY
R
SENSE
0.22µF
59k
GND
0.02Ω
V2
4368 F18
–3mV
Figure 18. Single MOSFET High Power Application
GATE
SENSE
V
OUT
V
IN
SEL V2
SHDN
LTC4368-2
4368 F17
Figure 17. Alternative to Ideal Diode
Rev. B
17
For more information www.analog.com
LTC4368
APPLICATIONS INFORMATION
300nH
(12 INCH WIRE LENGTH)
FDS3992
100V DUAL
R
SENSE
0.02Ω
V
IN
48V
INRUSH
+
C
CONTROL: ~1A
OUT
48Ω
ꢀꢁꢂꢃ
100µF
R
GATE
22k
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢂ
C
GATE
3.3nF
D1
ꢀ
ꢀꢁ
GATE
SENSE
V
OUT
ꢀꢁꢂꢃꢄꢅꢂ
V
IN
R4
100k
SHDN
UV
FAULT
LTC4368-2
1200ms COOLDOWN
AFTER FORWARD
OC FAULT
R2
2430k
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅ
ꢁꢃ
OV = 60V
OV
RETRY
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
C
R1
20.5k
RETRY
GND
0.22µF
4368 F19
Figure 20. Transients During 0V Fault when
No TransZorb (TVS) Is Used
Figure 19. OV Fault with Large VIN Inductance
Transients During OV Fault
Layout Considerations
The circuit of Figure 19 is used to illustrate transients The trace length between the V pin and the drain of the
IN
commonly encountered during an overvoltage condition. external MOSFET should be minimized, as well as the
The nominal input supply is 48V and it has an overvoltage trace length between the GATE pin of the LTC4368 and
threshold of 60V. The parasitic inductance is that of a 1 the gates of the external MOSFETs. The SENSE and V
OUT
foot wire (roughly 300nH). Figure 20 shows the wave- pins must be connected with traces that tie directly and
forms during on overvoltage condition at VIN. These tran- solely to the sense resistor.
sients depend on the parasitic inductance and resistance
Place the bypass capacitors at V
as close as possible
OUT
of the wire along with the capacitance at the VIN node.
D1 is an optional power clamp (TVS, TransZorb) recom-
mended for applications where the DC input voltage can
to the external MOSFET. Use high frequency ceramic
capacitors in addition to bulk capacitors to mitigate hot
swap ringing. Place the high frequency capacitors closest
to the MOSFET. Note that bulk capacitors mitigate ringing
by virtue of their ESR. Ceramic capacitors have low ESR
and can thus ring near their resonant frequency. The trace
length of the GATE pin should be kept as small as pos-
sible, and the number of components connected to the
GATE pin should also be minimized.
exceed 24V and with large V parasitic inductance. No
IN
clamp was used to capture the waveforms of Figure 20. In
order to maintain reverse supply protection, D1 must be
a bidirectional clamp with appropriate voltage and power
ratings.
The SOA of the external MOSFET might require the board
to have a minimum total area as well as a minimum amount
of trace volume connected to the drain and source pins.
Rev. B
18
For more information www.analog.com
LTC4368
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1ꢀꢀ1 Rev F)
0.889 0.127
(.035 .005)
5.10
(.201)
MIN
3.20 – 3.45
(.12ꢀ – .13ꢀ)
3.00 0.102
(.118 .004)
(NOTE 3)
(.0197)
0.497 0.07ꢀ
(.019ꢀ .003)
REF
0.50
5
0
0.038
.0015)
10 9
8
7 ꢀ
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .00ꢀ)
DETAIL “A”
0.254
(.010)
0° – ꢀ° TYP
GAUGE PLANE
1
2
3
4 5
0.53 0.152
(.021 .00ꢀ)
0.8ꢀ
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.101ꢀ 0.0508
(.004 .002)
0.50
(.0197)
BSC
MSOP (MS) 0213 REV F
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Rev. B
19
For more information www.analog.com
LTC4368
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
ꢃReꢩeꢪeꢫꢬe ꢗꢌꢓ ꢇꢏꢐ ꢭ ꢁꢠꢘꢁꢧꢘꢂꢣꢚꢚ Rev ꢓꢉ
ꢁ.ꢥꢁ ±ꢁ.ꢁꢠ
±ꢁ.ꢁꢠ
ꢙ.ꢂꢠ ±ꢁ.ꢁꢠ ꢃꢙ ꢅꢆꢇꢈꢅꢉ
ꢂ.ꢣꢠ ±ꢁ.ꢁꢠ
ꢔꢎꢓꢕꢎꢐꢈ
ꢋꢖꢌꢗꢆꢊꢈ
ꢁ.ꢙꢠ ±ꢁ.ꢁꢠ
ꢁ.ꢠꢁ
Bꢅꢓ
ꢙ.ꢀꢧ ±ꢁ.ꢁꢠ
ꢃꢙ ꢅꢆꢇꢈꢅꢉ
RECOMMENDED ꢅꢋꢗꢇꢈR ꢔꢎꢇ ꢔꢆꢌꢓꢝ ꢎꢊꢇ ꢇꢆꢑꢈꢊꢅꢆꢋꢊꢅ
R ꢦ ꢁ.ꢂꢙꢠ
ꢁ.ꢄꢁ ±ꢁ.ꢂꢁ
ꢌꢢꢔ
ꢣ
ꢂꢁ
ꢀ.ꢁꢁ ±ꢁ.ꢂꢁ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢂ.ꢣꢠ ±ꢁ.ꢂꢁ
ꢃꢙ ꢅꢆꢇꢈꢅꢉ
ꢔꢆꢊ ꢂ ꢊꢋꢌꢓꢝ
R ꢦ ꢁ.ꢙꢁ ꢋR
ꢔꢆꢊ ꢂ
ꢌꢋꢔ ꢑꢎRꢕ
ꢃꢅꢈꢈ ꢊꢋꢌꢈ ꢣꢉ
ꢁ.ꢀꢠ × ꢄꢠ°
ꢓꢝꢎꢑꢜꢈR
ꢃꢇꢇꢉ ꢇꢜꢊ Rꢈꢛ ꢓ ꢁꢀꢂꢁ
ꢠ
ꢂ
ꢁ.ꢙꢠ ±ꢁ.ꢁꢠ
ꢁ.ꢠꢁ Bꢅꢓ
ꢁ.ꢥꢠ ±ꢁ.ꢁꢠ
ꢁ.ꢙꢁꢁ Rꢈꢜ
ꢙ.ꢀꢧ ±ꢁ.ꢂꢁ
ꢃꢙ ꢅꢆꢇꢈꢅꢉ
ꢁ.ꢁꢁ ꢨ ꢁ.ꢁꢠ
Bꢋꢌꢌꢋꢑ ꢛꢆꢈꢏꢤꢈꢞꢔꢋꢅꢈꢇ ꢔꢎꢇ
ꢊꢋꢌꢈꢍ
ꢂ. ꢇRꢎꢏꢆꢊꢐ ꢌꢋ Bꢈ ꢑꢎꢇꢈ ꢎ ꢒꢈꢇꢈꢓ ꢔꢎꢓꢕꢎꢐꢈ ꢋꢖꢌꢗꢆꢊꢈ ꢑꢁꢘꢙꢙꢚ ꢛꢎRꢆꢎꢌꢆꢋꢊ ꢋꢜ ꢃꢏꢈꢈꢇꢘꢙꢉ.
ꢓꢝꢈꢓꢕ ꢌꢝꢈ ꢗꢌꢓ ꢏꢈBꢅꢆꢌꢈ ꢇꢎꢌꢎ ꢅꢝꢈꢈꢌ ꢜꢋR ꢓꢖRRꢈꢊꢌ ꢅꢌꢎꢌꢖꢅ ꢋꢜ ꢛꢎRꢆꢎꢌꢆꢋꢊ ꢎꢅꢅꢆꢐꢊꢑꢈꢊꢌ
ꢙ. ꢇRꢎꢏꢆꢊꢐ ꢊꢋꢌ ꢌꢋ ꢅꢓꢎꢗꢈ
ꢀ. ꢎꢗꢗ ꢇꢆꢑꢈꢊꢅꢆꢋꢊꢅ ꢎRꢈ ꢆꢊ ꢑꢆꢗꢗꢆꢑꢈꢌꢈRꢅ
ꢄ. ꢇꢆꢑꢈꢊꢅꢆꢋꢊꢅ ꢋꢜ ꢈꢞꢔꢋꢅꢈꢇ ꢔꢎꢇ ꢋꢊ Bꢋꢌꢌꢋꢑ ꢋꢜ ꢔꢎꢓꢕꢎꢐꢈ ꢇꢋ ꢊꢋꢌ ꢆꢊꢓꢗꢖꢇꢈ
ꢑꢋꢗꢇ ꢜꢗꢎꢅꢝ. ꢑꢋꢗꢇ ꢜꢗꢎꢅꢝꢟ ꢆꢜ ꢔRꢈꢅꢈꢊꢌꢟ ꢅꢝꢎꢗꢗ ꢊꢋꢌ ꢈꢞꢓꢈꢈꢇ ꢁ.ꢂꢠꢡꢡ ꢋꢊ ꢎꢊꢢ ꢅꢆꢇꢈ
ꢠ. ꢈꢞꢔꢋꢅꢈꢇ ꢔꢎꢇ ꢅꢝꢎꢗꢗ Bꢈ ꢅꢋꢗꢇꢈR ꢔꢗꢎꢌꢈꢇ
ꢣ. ꢅꢝꢎꢇꢈꢇ ꢎRꢈꢎ ꢆꢅ ꢋꢊꢗꢢ ꢎ RꢈꢜꢈRꢈꢊꢓꢈ ꢜꢋR ꢔꢆꢊ ꢂ ꢗꢋꢓꢎꢌꢆꢋꢊ ꢋꢊ ꢌꢝꢈ
ꢌꢋꢔ ꢎꢊꢇ Bꢋꢌꢌꢋꢑ ꢋꢜ ꢔꢎꢓꢕꢎꢐꢈ
Rev. B
20
For more information www.analog.com
LTC4368
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
06/18 Attached Note 3 to OV and FAULT Absolute Maximum Ratings
2
B
06/19 Added AEC-Q100 qualification and “W” part numbers
1,3
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
21
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC4368
TYPICAL APPLICATION
LTC2966 Extends UV/OV Hysteresis Window
Si7942DP
0.02Ω
V
IN
V
OUT
12V
+
1.96k
100µF
3.3nF
22k
100k
V
INA
V
INB
RS1A
REF
100k
GATE
SENSE
V
OUT
1nF
RS2A
RS1B
RS2B
200k
301k
698k
V
IN
510k
100k
INHA
SHDN
UV
FAULT
LTC2966
U1
LTC4368-2
U2
INLA
INHB
OUTA
PSA
RETRY
301k
0.22µF
150k
750k
OUTB
PSB
OV
GND
INLB
UV: OFF AT 7V
ON AT 10V
4368 TA02
GND
OV: OFF AT 18V
ON AT 15V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC4365
Overvoltage, Undervoltage and Reverse Supply
Protection Controller
Wide Operating Range: 2.5V to 34V, Protection Range: –40V to 60V,
No TVS Required for Most Applications
LTC4367
LT4363
100V Overvoltage, Undervoltage and Reverse Supply Wide Operating Range: 2.5V to 60V, Protection Range: –40V to 100V,
Protection Controller
No TVS Required for Most Applications
High Voltage Surge Stopper with Current Limit
Wide Operating Range: 4V to 80V, Reverse Protection to –60V, Adjustable
Output Clamp Voltage
LTC4380
8µA I Surge Stopper
4V to 72V Operation, Pin Selectable Clamp Voltage
Q
LTC4364
Surge Stopper with Ideal Diode
High Voltage Surge Stopper
4V to 80V Operation, –40V Reverse Input, –20V Reverse Output
9V to >500V Operation, 8-Pin TSOT and 3mm × 2mm DFN Packages
5.8V Overvoltage Threshold, 85V Absolute Maximum
Pin Selectable Input Polarity Allows Negative and OV Monitoring
Adjustable UV and OV Trip Values, 1.5% Threshold Accuracy
For Positive and Negative Supplies
LTC4366
LTC4361
Overvoltage/Overcurrent Protection Controllers
Triple/Dual Inputs UV/OV Negative Monitor
Single/Dual UV/OV Voltage Monitor
Quad UV/OV Monitor
LTC2909
LTC2912/LTC2913
LTC2914
LTC2955
Pushbutton On/Off Controller
Automatic Turn-On, 1.5V to 36V Input, 36V PB Input
LT4256
Positive 48V Hot Swap Controller with
Open-Circuit Detect
Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output,
Up to 80V Supply
LTC4260
Positive High Voltage Hot Swap Controller with
Wide Operating Range 8.5V to 80V
2
ADC and I C
LTC4352
LTC4371
LTC4355
LT1913
Ideal Diode Controller
External N-Channel MOSFETs Replace ORing Diodes, 0V to 18V Operation
External N-Channel MOSFETs, –4.5V to > –100V Operation
External N-Channel MOSFETs, 0.4µs Turn-Off, 80V Operation
3.6V to 25V Input, 3.5A Maximum Current, 200kHz to 2.4MHz
Dual Negative Voltage Ideal Diode-OR Controller
Dual Positive Voltage Ideal Diode-OR Controller
Step-Down Switching Regulator
Rev. B
D17021-0-6/18(B)
www.analog.com
22
ANALOG DEVICES, INC. 2017-2019
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