LTC6806_技术文档

LTC6810-1/LTC6810-2

6 Channel Battery Stack Monitors

FEATURES

DESCRIPTION

The LTC^®6810 is a multicell battery stack monitor. The

LTC6810 measures up to 6 series-connected battery cells

with a total measurement error of less than 1.8mV. The

cell measurement range of 0V to 5V makes the LTC6810

suitable for most battery chemistries. All 6 cells can be

measured in 290µs, and lower data acquisition rates can

be selected for high noise reduction.

n

AEC-Q100 Qualified for Automotive Applications

Measures Up to 6 Battery Cells in Series

1.8mV Maximum Total Measurement Error

Stackable Architecture for High Voltage Systems

290µs to Measure All Cells in a System.

Built-in isoSPI™ Interface

n

1Mb Isolated Serial Communications

n

Uses Single Twisted Pair, Up to 100 Meters

Multiple LTC6810-1 devices can be connected in series,

permitting simultaneous cell monitoring of long, high

voltage battery strings. Each LTC6810 has an isoSPI

interface for high speed, RF-immune, long distance com-

munications. Using the LTC6810-1, multiple devices are

connected in a daisy chain with one host processor con-

nection for all devices. The LTC6810-1 supports bidi-

rectional operation, allowing communication even with

a broken wire. Using the LTC6810-2, multiple devices

are connected in parallel to the host processor, with each

device individually addressed.

n

Low EMI Susceptibility and Emissions

n

Bidirectional for Broken Wire Protection

n

Guaranteed Performance Down to 5V

Performs Redundant Cell Measurements.

Engineered for ISO 26262 Compliant Systems

Passive Cell Balancing with Programmable PWM

4 General Purpose Digital I/O or Analog Inputs

n

Temperature or Other Sensor Inputs

Configurable as an I C or SPI master

2

n

4μA Sleep Mode Supply Current

44-Lead SSOP Package

The LTC6810 can be powered directly from the battery

stack or from an isolated supply. The LTC6810 includes

passive balancing for each cell, with PWM duty cycle

control for each cell and the ability to perform redundant

cell measurements. Other features include an onboard 5V

regulator, 4 general purpose I/O lines and a sleep mode in

which current consumption is reduced to 4µA.

APPLICATIONS

n

Electric and Hybrid Electric Vehicles

n

Backup Battery Systems

Grid Energy Storage

n

High Power Portable Equipment

All registered trademarks and trademarks are the property of their respective owners.

TYPICAL APPLICATION

REVERSIBLE

LTC6810

Measurement Error vs V⁺

+

SERIAL

PORT B

ꢀ.ꢁ

isoSPI

16-BIT ∆ċ WITH

PROGRAMMABLE

NOISE FILTER

ꢀꢁAꢂꢃRꢁꢀꢁꢄꢅ ꢁRRꢆR ꢆꢇ

ꢈꢁꢉꢉꢊ ꢋꢌꢅꢍ ꢎ.ꢎꢏ ꢌꢄꢐꢃ ꢑ

LOGIC

ꢏ

ꢌꢄꢅꢁRꢄAꢉꢉꢓ ꢒꢁꢄꢁRAꢅꢁꢔꢑ

Rꢁꢒ

SERIAL

PORT A

ꢀ.ꢁ

ꢇꢌꢒꢃRꢁ ꢕ

4-WIRE

SPI

ꢀ.ꢁ

UNIQUE ID

DIE TEMP

ꢀ

MUX

OPTIONAL

EEPROM

ꢀꢁ.ꢂ

CURRENT

SENSOR

MUX

ꢀꢁꢂꢃꢄ

ꢁꢂꢃꢄ

ꢅꢆꢇꢃꢄ

4 GENERAL PURPOSE

ANALOG IN AND

DIGITAL IN/OUT

SECOND

REFERENCE

ꢀ

ꢀꢁ

10k

NTC

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄAꢃꢂꢅ

FIRST

REFERENCE

–

68101 TA01a

Rev. A

1

Document Feedback

For more information www.analog.com

LTC6810-1/LTC6810-2

TABLE OF CONTENTS

Features............................................................................................................................ 1

Applications ....................................................................................................................... 1

Typical Application ............................................................................................................... 1

Description......................................................................................................................... 1

Absolute Maximum Ratings..................................................................................................... 3

Pin Configuration ................................................................................................................. 3

Order Information................................................................................................................. 4

Electrical Characteristics........................................................................................................ 4

Typical Performance Characteristics .........................................................................................10

Pin Functions.....................................................................................................................17

Block Diagram....................................................................................................................18

Operation..........................................................................................................................20

State Diagram....................................................................................................................................................... 20

Core LTC6810 State Descriptions......................................................................................................................... 20

isoSPI State Descriptions ..................................................................................................................................... 21

Power Consumption ............................................................................................................................................. 22

V

REG

Configurations ............................................................................................................................................. 23

ADC Operation...................................................................................................................................................... 24

Data Acquisition System Diagnostics ................................................................................................................... 29

Watchdog and Discharge Timer............................................................................................................................ 37

Reset Behaviors.................................................................................................................................................... 39

S Pin Pulse Width Modulation for Cell Balancing.................................................................................................. 40

Discharge Timer Monitor...................................................................................................................................... 40

2

I C/SPI Master on LTC6810 Using GPIOs............................................................................................................. 40

S Pin Muting......................................................................................................................................................... 44

Serial ID and Authentication ................................................................................................................................. 45

Serial Interface Overview...................................................................................................................................... 45

4-Wire Serial Peripheral Interface (SPI) Physical Layer........................................................................................ 45

Data Link Layer..................................................................................................................................................... 55

Network Layer....................................................................................................................................................... 55

Applications Information .......................................................................................................70

Providing DC Power.............................................................................................................................................. 70

Internal Protection and Filtering............................................................................................................................ 71

Cell Balancing ....................................................................................................................................................... 72

Discharge Control During Cell Measurements ...................................................................................................... 74

Digital Communications........................................................................................................................................ 76

Enhanced Applications.......................................................................................................................................... 86

Reading External Temperature Probes.................................................................................................................. 86

Package Description ............................................................................................................88

Revision History .................................................................................................................89

Typical Application ..............................................................................................................90

Related Parts.....................................................................................................................90

Rev. A

2

For more information www.analog.com

LTC6810-1/LTC6810-2

ABSOLUTE MAXIMUM RATINGS

(Note 1)

+

–

Total Supply Voltage, V to V ................................ 37.5V

S6 to S4................................................. –0.3V to 21V

S4 to S2................................................. –0.3V to 21V

S2 to S0................................................. –0.3V to 21V

S6 to C3................................................. –0.3V to 21V

Current In/Out of Pins

–

Input Voltage (Relative to V )

C0............................................................ –0.3V to 5V

S0.......................................................... –0.3V to 21V

C(n), S(n) n = 1 TO 3.............................. –0.3V to 21V

C(n), S(n) n = 4 TO 5............................–0.3V to 37.5V

C(6), S(6) ...................–0.3V to min(V+ + 5.5V, 37.5V)

All Pins Except V , IPA, IMA, IPB, IMB, S(n)..10mA

REG

IPA, IMA, IPB, IMB.............................................30mA

IPA, IMA, IPB, IMB............ –0.3V to V

+ 0.3V, ≤6V

Operating Temperature Range

REG

DRIVE ...................................................... –0.3V to 7V

All Other Pins........................................... –0.3V to 6V

Voltage Between Inputs

LTC6810I .............................................–40°C to 85°C

LTC6810H.......................................... –40°C to 125°C

Specified Temperature Range

LTC6810I .............................................–40°C to 85°C

LTC6810H.......................................... –40°C to 125°C

Junction Temperature ........................................... 150°C

Storage Temperature Range .................. –65°C to 150°C

C(n) to C(n – 1) ...................................... –0.3V to 21V

S(n) to C(n – 1) ...................................... –0.3V to 21V

C6 to C3................................................. –0.3V to 21V

C3 to C0................................................. –0.3V to 21V

PIN CONFIGURATION

LTC6810-1

LTC6810-2

TOP VIEW

–

1

2

V *

1

2

V *

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

V *

–

V *

NC

+

3

WDT

3

WDT

V

4

SDI (NC)**

SDO (NC)**

IPB

4

SDI (ICMP)**

C6

S6

C6

S6

5

SDO (IBIAS)**

6

A3

C5

7

IMB

7

A2

S5

8

SCK (IPA)**

CSB (IMA)**

ICMP

8

SCK (IPA)**

CSB (IMA)**

A1

C4

9

S4

10

11

12

13

14

15

16

17

18

19

20

21

22

10

11

12

13

14

15

16

17

18

19

20

21

22

C3

IBIAS

A0

S3

DRIVE

C2

V

S2

REG

V

REF2

C1

REF2

V

REF1

S1

REF1

–

V

C0

–

V

S0

ISOMD

DTEN

ISOMD

DTEN

GPIO1

GPIO2

GPIO3

GPIO1

GPIO2

GPIO3

GPIO4

–

V *

–

V *

G PACKAGE

44-LEAD PLASTIC SSOP

= 150°C, θ = 50°C/W

G PACKAGE

44-LEAD PLASTIC SSOP

T = 150°C, θ = 50°C/W

JMAX

T

JMAX

JA

**PINS 1, 21–24, 43 AND 44 ARE FUSED TO THE LEADFRAME.

–

THEY SHOULD BE CONNECTED TO V PIN 29

**THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD

–

ISOMD TIED TO V : CSB, SCK, SDI, SDO

ISOMD TIED TO V : IMA, IPA, NC, NC

ISOMD TIED TO V : IMA, IPA, ICMP, IBIAS

REG

Rev. A

3

For more information www.analog.com

LTC6810-1/LTC6810-2

ORDER INFORMATION

AUTOMOTIVE PRODUCTS**

SPECIFIED

TEMPERATURE RANGE

TUBE (37PC)

TAPE AND REEL (2000PC)

PART MARKING

PACKAGE DESCRIPTION

MSL RATING

LTC6810IG-1#3ZZPBF

LTC6810HG-1#3ZZPBF

LTC6810IG-2#3ZZPBF

LTC6810HG-2#3ZZPBF

LTC6810IG-1#3ZZTRPBF

LTC6810HG-1#3ZZTRPBF

LTC6810IG-2#3ZZTRPBF

LTC6810HG-2#3ZZTRPBF

LTC6810G-1

LTC6810G-2

44-Lead Plastic SSOP

1

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These

models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your

local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for

these models.

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. The test conditions are V⁺= 19.8V, V_REG= 5.0V unless otherwise noted.

The ISOMD pin is tied to the V^–pin, unless otherwise noted.

SYMBOL PARAMETER

ADC DC Specifications

CONDITIONS

MIN

TYP

MAX

UNITS

Measurement Resolution

0.1

mV/bit

mV

ADC Offset Voltage

ADC Gain Error

(Note 2)

0.03

0.06

%

l

–

Total Measurement Error (TME) in

Normal Mode (Note 3)

C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V = 0

0.2

0.1

mV

–

C(n) to C(n–1) = 2.0, GPIO(n) to V = 2.0

1.2

1.7

mV

S(n) to S(n–1) = 2.0

–

l

C(n) to C(n–1), GPIO(n) to V = 2.0

1.6

2.2

mV

S(n) to S(n–1) = 2.0

–

C(n) to C(n–1), GPIO(n) to V = 3.3

0.2

0.3

1.8

2.5

mV

S(n) to S(n–1) = 3.3

–

l

C(n) to C(n–1), GPIO(n) to V = 3.3

2.4

3.2

mV

S(n) to S(n–1) = 3.3

C(n) to C(n–1) = 4.2

S(n) to S(n–1) = 4.2

2.3

3.2

mV

–

l

C(n) to C(n–1), GPIO(n) to V = 4.2

3.1

4.1

mV

S(n) to S(n–1) = 4.2

–

C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V = 5.0

1

0.1

5

mV

%

l

Sum of Cells

0.6

Internal Temperature, T = Maximum Specified

Temperature

°C

l

V

0.1

0.02

0.1

0.25

0.1

1

%

REG

REF2

Digital Supply Voltage, V

REGD

Rev. A

4

For more information www.analog.com

LTC6810-1/LTC6810-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. The test conditions are V⁺= 19.8V, V_REG= 5.0V unless otherwise noted.

The ISOMD pin is tied to the V^–pin, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

0.1

MAX

UNITS

–

Total Measurement Error (TME) in

Filtered Mode (Note 3)

C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V = 0

mV

–

C(n) to C(n–1) = 2.0, GPIO(n) to V = 2.0

S(n) to S(n–1) = 2.0

1.2

1.7

mV

–

l

C(n) to C(n–1), GPIO(n) to V = 2.0

1.6

2.2

mV

S(n) to S(n–1) = 2.0

C(n) to C(n–1) = 3.3

S(n) to S(n–1) = 3.3

0.2

0.3

1.8

2.5

mV

–

l

C(n) to C(n–1), GPIO(n) to V = 3.3

S(n) to S(n–1) = 3.3

2.4

3.2

mV

C(n) to C(n–1) = 4.2

S(n) to S(n–1) = 4.2

2.3

3.2

mV

–

l

C(n) to C(n–1), GPIO(n) to V = 4.2

3.1

4.1

mV

S(n) to S(n–1) = 4.2

–

C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V = 5.0

1

0.1

5

mV

%

l

Sum of Cells

0.6

Internal Temperature, T = Maximum Specified

Temperature

°C

l

V

0.1

0.02

0.1

2

0.25

0.1

1

%

REG

REF2

Digital Supply Voltage, V

%

REGD

–

Total Measurement Error (TME) in

Fast Mode (Note 3)

C(n) to C(n–1), S(n) to S(n–1), GPIO(n) to V = 0

mV

–

l

C(n) to C(n–1), GPIO(n) to V = 2.0

4

5

mV

S(n) to S(n–1) = 2.0

–

l

C(n) to C(n–1), GPIO(n) to V = 3.3

5.5

6.5

mV

S(n) to S(n–1) = 3.3

–

l

C(n) to C(n–1), GPIO(n) to V = 4.2

8

9

mV

S(n) to S(n–1) = 4.2

–

C(n) to C(n–1), GPIO(n) to V = 5.0, S(n) to S(n–1) = 5.0

10

0.15

5

mV

%

l

Sum of Cells

1

Internal Temperature, T = Maximum Specified

Temperature

°C

l

V

0.3

0.1

0.2

1

%

V

REG

0.25

REF2

Digital Supply Voltage, V

C(n) n = 1 to 6

S(n) n = 1 to 6

C0/S0

2

REGD

Input Range

C(n–1)

C(n–1) + 5

C(n–1)

C(n+1)

V

0

5

V

GPIO(n) n = 1 to 4

V

l

I

L

Input Leakage Current When Inputs

Are Not Being Measured (State:

Core = STANDBY)

C(n), S(n), n = 0 to 6

GPIO(n) n = 1 to 4

10

250

nA

Input Current When Inputs Are Being C(n)/S(n) n = 0 to 6

1

µA

Measured

GPIO(n) n = 1 to 4

l

Input Current During Open Wire

Detection

70

110

140

µA

Rev. A

5

For more information www.analog.com

LTC6810-1/LTC6810-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. The test conditions are V⁺= 19.8V, V_REG= 5.0V unless otherwise noted.

The ISOMD pin is tied to the V^–pin, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Voltage Reference Specifications

l

V

1st Reference Voltage

V

REF1

V

REF1

V

REF1

V

REF1

V

REF2

V

REF2

V

REF2

V

REF2

V

REF2

Pin, No Load

Pin, 5k Load to V

Pin, No Load

3.1

3.2

3

3.3

V

ppm/°C

ppm

REF1

1st Reference Voltage TC

1st Reference Voltage Hysteresis

1st Reference V. Long Term Drift

2nd Reference Voltage

20

25

3

ppm/√khr

V

l

V

2.995

2.994

3.005

3.006

REF2

–

3

V

2nd Reference Voltage TC

10

100

60

ppm/°C

ppm

2nd Reference Voltage Hysteresis

2nd Reference V. Long Term Drift

ppm/√khr

General DC Specifications

+

I

V Supply Current

(See Figure 1: Operation State

Diagram)

State: Core = SLEEP, isoSPI = IDLE

V

= 0V

= 5V

5.7

3.5

22

10

15

5.5

9

µA

VP

REG

l

State: Core = STANDBY

Internal REG Disabled

14

10

35

45

µA

State: Core = REFUP

25

20

35

50

60

µA

State: Core = MEASURE

30

25

50

70

80

µA

+

I

Total V Current when Internal REG

Enabled = I +I

State: Core = STANDBY

Internal REG Enabled

70

60

130

175

200

µA

VP_INTREG

VP REG

V

Supply Current

State: Core = SLEEP, isoSPI = IDLE

V

= 5V

3.5

48

6.5

9

µA

REG(CORE)

REG

(See Figure 1: Operation State

Diagram)

l

REG

State: Core = STANDBY

State: Core = REFUP

20

18

75

85

µA

1.2

1.1

1.7

2.2

2.3

mA

State: Core = MEASURE

LTC6810-2: ISOMD = 1,

5.7

5.5

6.2

6.6

6.8

mA

l

I

Additional V

Supply Current

READY

ACTIVE

READY

ACTIVE

READY

ACTIVE

READY

ACTIVE

READY

ACTIVE

READY

ACTIVE

3.6

4.6

3.6

5.6

4.0

7.0

1.0

1.2

1.0

1.3

1.6

1.8

4.5

5.8

4.5

6.8

5.2

8.5

1.8

2.2

1.8

2.3

2.5

3.1

5.4

7.0

5.2

8.1

6.5

10.5

2.6

3.2

2.6

3.3

3.5

4.8

mA

REG(isoSPI)

REG

If isoSPI in READY/ACTIVE States

Note: ACTIVE State Current

R

+ R = 2k

B1 B2

LTC6810-1: ISOMD = 0,

+ R = 2k

Assumes t

= 1µs, (Note 3)

CLK

R

B1

B2

LTC6810-1: ISOMD = 1,

+ R = 2k

R

B1

B2

LTC6810-2: ISOMD = 1,

+ R = 20k

R

B1

B2

LTC6810-1: ISOMD = 0,

+ R = 20k

R

B1

B2

LTC6810-1: ISOMD = 1,

R

B1

+ R = 20k

B2

mA

Rev. A

6

For more information www.analog.com

LTC6810-1/LTC6810-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. The test conditions are V⁺= 19.8V, V_REG= 5.0V unless otherwise noted.

The ISOMD pin is tied to the V^–pin, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

5.0

TYP

MAX

UNITS

+

l

V Supply Voltage

TME Specifications Met

TME Supply Rejection < 1mV/V

DRIVE Pin Current > 25µA

20

27.5

V

+

V to C6 Voltage

Supply Voltage

–0.3

4.5

V

REG

V

5

4.6

5

5.5

4.8

5.3

REG

Internal Regulator Voltage

4.5

Allowed V

Driven

Range When Externally DRIVE Pin Is High Z

4.7

REG

+

l

V

DRIVE

DRIVE Output Voltage

V > 12V, Sourcing 1µA

5.5

5.3

25

5.7

5.5

6.2

6

V

+

V > 12V, Sourcing 1mA

Drive Pin Current to Enable Internal

µA

V

REGA

l

Maximum DRIVE Pin Current that

1

µA

Does Not Power Up Internal V

REGA

l

V

Digital Supply Voltage

2.7

3

5

3.6

10

V

Ω

°C

V

REGD

Discharge Switch ON Resistance

Thermal Shutdown Temperature

V

CELL

= 3.3V

150

l

V

Watch Dog Timer (WDT) Pin Voltage WDT Pin Sinking 4mA

General Purpose I/O Pin Low GPIO Pin Sinking 4mA (Used as Digital Output)

0.4

OL(WDT)

V

OL(GPIO)

ADC Timing Specifications

l

t

Measurement + Calibration Cycle Time Measure 6 Cells

1098

381

1411

172

31

1165

404

1497

183

34

1281

444

1647

201

37

µs

CYCLE

(Figure 6) When Starting from the REFUP State in

Normal Mode, SCONV = 0, MCAL = 0

Measure 1 Cells

Measure 6 Cells and 2 GPIO Inputs

µs

Measurement + Calibration Cycle Time Measure 6 Cells

ms

µs

When Starting from the REFUP State in

Filtered Mode, SCONV = 0, MCAL = 0

Measure 1 Cells

Measure 6 Cells and 2 GPIO Inputs

228

495

189

643

242

524

200

682

267

577

220

750

Measurement + Calibration Cycle Time Measure 6 Cells

When Starting from the REFUP State

in Fast Mode, SCONV = 0, MCAL = 0

Measure 1 Cells

µs

Measure 6 Cells and 2 GPIO Inputs

Fast Mode

µs

l

t

Skew Time. The Time Difference

182

511

194

543

214

598

µs

SKEW1

(Figure 9) Between C6 and GPIO1 Measurements,

Command = ADCVAX

Normal Mode

l

t

Skew Time. The Time Difference

Fast Mode

220

631

233

670

257

737

µs

SKEW2

(Figure 6) Between C6 and C1 Measurements,

Command = ADCV

Normal Mode

l

t

Drive Start-Up Time (Note 5)

Internal Regulator Start-Up Time

Watchdog or Discharge Timer

V

Generated from Drive Pin, See Figure 3

Generated Internally, See Figure 2

150

200

2

300

400

2.2

32

µs

WAKE

REG

t

DTEN Pin = 0 or DCTO[3:0] = 0000

DTEN Pin = 1 and DCTO[3:0] = 0001

DTEN Pin = 1 and DCTO[3:0] = 1111

1.8

28

sec

min

ms

SLEEP

(Figure 17)

30

112

2.7

120

3.5

128

4.4

l

t

Reference Wake-up Time. Added to

t

Is Independent of the Number of Channels

REFUP

(Figure 6,

t

Time When Starting from the

Measured and the ADC Mode

CYCLE

Figure 30) STANDBY State. t

= 0 When

REFUP

Starting from Other States.

f

S

ADC Clock Frequency

3.0

3.3

3.5

MHz

Rev. A

7

For more information www.analog.com

LTC6810-1/LTC6810-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. The test conditions are V⁺= 19.8V, V_REG= 5.0V unless otherwise noted.

The ISOMD pin is tied to the V^–pin, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SPI Interface DC Specifications

l

V

SPI Pin Digital Input Voltage High

SPI Pin Digital Input Voltage Low

Pins CSB, SCK, SDI

2.3

V

IH(SPI)

0.8

IL(SPI)

Address Pin Digital Input Voltage High Pins ISOMD, DTEN, GPIO1 to GPIO4, A0–A3

Address Pin Digital Input Voltage Low Pins ISOMD, DTEN, GPIO1 to GPIO4, A0–A3

2.7

V

IH(ADDR)

IL(ADDR)

LEAK(DIG)

1.2

1

V

I

Digital Input Current

Digital Output Low

Pins CSB, SCK, SDI, ISOMD, DTEN, A0 to A3

Pins SDO sinking 1mA

µA

V

0.3

OL(SDO)

isoSPI DC Specifications (see Figure 23)

l

V

BIAS

Voltage on IBIAS Pin

READY/ACTIVE State

IDLE State

1.9

2

0

2.1

V

l

I

Isolated Interface Bias Current

Isolated Interface Current Gain

I = V

/(R + R )

B2

0.1

18

1

mA

mA/mA

V

B

BIAS

B1

A

V ≤ 1.6V

A

I = 1mA

20

22

23

1.6

1.5

IB

B

I = 0.1mA

B

V

Transmitter Pulse Amplitude

V = |V – V

A

|

IM

A

IP

Threshold-Setting Voltage on

ICMP Pin

V

= A

• V

ICMP

0.2

V

ICMP

TCMP

l

I

Input Leakage Current on ICMP Pin

Leakage Current on IP and IM Pins

1

µA

LEAK(ICMP)

IDLE State, V or V , 0V to V

LEAK(IP/IM)

IP

IM

REG

A

Receiver Comparator Threshold

Voltage Gain

V

= 2.5V to V – 0.2

REG

0.4

0.5

0.6

V/V

TCMP

CM

V

Receiver Common-Mode Bias

Receiver Input Resistance

IP/IM Not Driving

Single-Ended to IPA, IMA, IPB, IMB

(V

REG

– V

/3 – 167mV)

V

ICMP

l

R

26

35

45

kΩ

IN

isoSPI Idle/Wake-up Specifications (see Figure 30)

l

V

Differential Wake-up Voltage

V

= |V – V |

IMA

250

240

mV

ns

WAKE

IPA

t

Dwell Time at V Before Wake

WAKE

DWELL

Detection

l

t

Start-Up Time After Wake Detection

Idle Timeout Duration

10

µs

READY

4.3

5.5

6.7

ms

IDLE

isoSPI Pulse Timing Specifications (see Figure 28)

l

t

Chip-Select Half-Pulse Width

Chip-Select Signal Filter

Chip-Select Pulse Inversion Delay

Chip-Select Valid Pulse Window

Data Half-Pulse Width

Transmitter

Receiver

120

70

150

90

180

110

190

330

60

ns

½PW(CS)

FILT(CS)

INV(CS)

WNDW(CS)

½PW(D)

FILT(D)

Transmitter

Receiver

120

220

40

155

270

50

Transmitter

Receiver

Data Signal Filter

10

25

35

Data Pulse Inversion Delay

Data Valid Pulse Window

Transmitter

Receiver

40

55

65

INV(D)

70

90

110

WNDW(D)

Rev. A

8

For more information www.analog.com

LTC6810-1/LTC6810-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. The test conditions are V⁺= 19.8V, V_REG= 5.0V unless otherwise noted.

The ISOMD pin is tied to the V^–pin, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SPI Timing Requirements (see Figure 22 and Figure 29)

l

t

SCK Period

(Note 6)

1

µs

ns

CLK

SDI Setup Time Before SCK Rising

Edge

25

1

l

t

2

t

3

t

4

t

5

t

6

t

7

SDI Hold Time After SCK Rising Edge

SCK Low

25

200

0.6

0.8

1

ns

µs

t

= t + t ³ 1µs

3 4

CLK

SCK High

= t + t ³ 1µs

3

4

CS Rising Edge to CS Falling Edge

SCK Rising Edge to CS Rising Edge

CS Falling Edge to SCK Rising Edge

(Note 6)

isoSPI Timing Specifications (see Figure 29)

l

t

SCK Falling Edge to SDO Valid

SCK Rising Edge to Short 1 Transmit

CS Transition to Long 1 Transmit

CS Rising Edge to SDO Rising

Data Return Delay

(Note 7)

60

50

ns

µs

8

9

60

10

200

425

180

300

70

11

325

375

120

250

55

RTN

DSY(CS)

DSY(D)

LAG

5(GOV)

Chip-Select Daisy-Chain Delay

Data Daisy-Chain Delay

200

0

Data Daisy-Chain Lag (vs. Chip-Select) = [t

+ t

] – [t

+ t

½PW(CS)

]

DSY(D)

½PW(D)

DSY(CS)

Chip-Select High-to-Low Pulse

Governor

0.6

0.82

l

t

Data to Chip-Select Pulse Governor

isoSPI Port Reversal Blocking Window

0.8

2

1.05

10

µs

6(GOV)

BLOCK

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The ADC specifications are guaranteed by the Total Measurement

Error specification.

Note 3: S pin TME may differ from C pin TME by several bits due to the

quantization noise of the ADC and the different external filtering on the

C and S pins.

Note 5: V

transistor, see Figure 3.

Note 6: These timing specifications are dependent on the delay through

the cable, and include allowances for 50ns of delay each direction. 50ns

corresponds to 10m of CAT-5 cable (which has a velocity of propagation of

66% the speed of light). Use of longer cables would require derating these

specs by the amount of additional delay.

is generated from the Drive pin and an external NPN

REG

Note 7: These specifications do not include rise or fall time of SDO. While

fall time (typically 5ns due to the internal pull-down transistor) is not a

concern, rising-edge transition time t

resistance and load capacitance on the SDO pin. The time constant must

be chosen such that SDO meets the setup time requirements of the MCU.

is dependent on the pull-up

RISE

Note 4: The ACTIVE state current is calculated from DC measurements.

The ACTIVE state current is the additional average supply current into

V

when there is continuous 1MHz communications on the isoSPI ports

REG

with 50% data 1s and 50% data 0s. Slower clock rates reduce the supply

current. See Applications Information section for additional details.

Rev. A

9

For more information www.analog.com

LTC6810-1/LTC6810-2

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Measurement Error vs

Temperature

Measurement Error Due to IR

Reflow

Measurement Error Long Term

Drift

ꢀ.ꢁ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂꢂ ꢃꢄꢂꢅAꢆꢁ ꢇ ꢈ.ꢈꢃ

ꢀ ꢁꢂꢃꢄꢅAꢆ ꢇꢈꢄꢁꢉ

ꢀꢁ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ.ꢂ

ꢀ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢂꢂ

ꢀꢁꢁꢁ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁAꢂꢃꢄ ꢅꢂ ꢃAꢅꢂ ꢄRRꢆR ꢇꢈꢈꢉꢊ

ꢀꢁꢂꢃ ꢄꢅꢆꢇRꢈꢉ

ꢀꢁꢂꢃ ꢄꢃꢂ

ꢀꢁꢂꢃ ꢄꢃꢅ

Measurement Error vs Input

Normal Mode

Measurement Error vs Input

Filtered Mode

Measurement Error vs Input

Fast Mode

ꢀ.ꢁ

ꢀꢁ.ꢁ

ꢀ.ꢁ

ꢀꢁ Aꢂꢃ ꢄꢅAꢆꢇRꢅꢄꢅꢈꢉꢆ

AꢀꢁRAꢂꢁꢃ Aꢄ ꢁAꢅꢆ ꢇꢈꢉꢊꢄ

ꢀꢁ Aꢂꢃ ꢄꢅAꢆꢇRꢅꢄꢅꢈꢉꢆ

AꢀꢁRAꢂꢁꢃ Aꢄ ꢁAꢅꢆ ꢇꢈꢉꢊꢄ

ꢀꢁ Aꢂꢃ ꢄꢅAꢆꢇRꢅꢄꢅꢈꢉꢆ

AꢀꢁRAꢂꢁꢃ Aꢄ ꢁAꢅꢆ ꢇꢈꢉꢊꢄ

ꢀ.ꢁ

ꢀ

ꢀꢁ.ꢂ

ꢀꢁꢂ.ꢂ

ꢀꢁ.ꢂ

ꢀ

ꢀꢁꢂꢃꢄ ꢅꢆꢇ

ꢀꢁꢂꢃ ꢄꢃꢅ

ꢀꢁꢂꢃ ꢄꢃꢀ

Measurement Noise vs Input

Normal Mode

Measurement Noise vs Input

Filtered Mode

Measurement Noise vs Input

Fast Mode

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀꢁ.ꢁ

ꢀ.ꢁ

ꢀ

ꢀꢁꢂꢃꢄ ꢅꢆꢇ

ꢀꢁꢂꢃ ꢄꢃꢅ

ꢀꢁꢂꢃ ꢄꢃꢁ

ꢀꢁꢂꢃ ꢄꢃꢅ

Rev. A

10

For more information www.analog.com

LTC6810-1/LTC6810-2

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Measurement Gain Error

Hysteresis, Hot

Measurement Gain Error

Hysteresis, Cold

Noise Filter Response

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃꢄ ꢅꢆ ꢇꢈꢉꢃꢄ

ꢀ

ꢀ ꢁꢂꢃꢄ ꢅꢆ ꢇꢂꢃꢄ

A

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ

ꢀꢁꢂꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁꢂ

ꢀꢁ

ꢀꢁAꢂꢃꢄ ꢅꢂ ꢃAꢅꢂ ꢄRRꢆR ꢇꢈꢈꢉꢊ

ꢀꢁꢂꢃꢄ ꢅRꢆꢇꢃꢆꢁꢈꢉ ꢊꢋꢌꢍ

ꢀꢁꢂꢃ ꢄꢂꢃ

ꢀꢁꢂꢃ ꢄꢂꢂ

ꢀꢁꢂꢃ ꢄꢂꢅ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ

Measurement Error vs V_REG

Measurement Error vs V⁺

Top Cell Measurement Error vs V⁺

ꢀ.ꢁ

ꢀꢁ ꢂ ꢀꢃ ꢄ ꢅ.ꢅꢆ

ꢀꢁ ꢄ ꢇꢈ.ꢉꢆ

ꢀꢁAꢂꢃRꢁꢀꢁꢄꢅ ꢁRRꢆR ꢆꢇ

ꢈꢁꢉꢉꢊ ꢋꢌꢅꢍ ꢎ.ꢎꢏ ꢌꢄꢐꢃ ꢑ

ꢏ

ꢌꢄꢅꢁRꢄAꢉꢉꢓ ꢒꢁꢄꢁRAꢅꢁꢔꢑ

Rꢁꢒ

ꢀ.ꢁ

ꢇꢌꢒꢃRꢁ ꢕ

ꢀ.ꢁ

ꢀ

ꢀꢁ.ꢂ

ꢀ

ꢃ ꢄꢀ

ꢁꢂ

ꢃ ꢄ.ꢄꢀ

ꢃ ꢄ.ꢅꢀ

ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢀ

ꢀ

ꢀꢁ

ꢀꢀ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢂꢅ

Measurement Error vs Common

Mode Voltage

Measurement Error Due to a V_REG

AC Disturbance

Measurement Error Due to a V⁺

AC Disturbance

ꢀ.ꢁ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

.

A

ꢀ.ꢁ

RA

R

ꢀ.ꢁ

ꢀ

ꢀꢁ.ꢂ

ꢀ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ ꢂꢃꢄꢅAꢆꢇ ꢈꢂꢉ

ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ

ꢀꢁꢂꢃ ꢄꢂꢀ

ꢀꢁꢂꢃ ꢄꢂꢅ

ꢀꢁꢂꢃ ꢄꢂꢁ

Rev. A

11

For more information www.analog.com

LTC6810-1/LTC6810-2

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Measurement Error CMRR vs

Frequency

Cell Measurement Error vs Input

GPIO Measurement Error vs Input

RC Values

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀ

ꢇ ꢈꢀ

ꢉꢊꢉ

ꢀꢁꢂꢃ ꢄꢃꢀꢅꢃꢃꢆ ꢂꢃAꢇꢈRꢃꢂꢃꢆꢀꢇ ꢉ ꢊRꢋ

ꢁꢂꢃꢄꢅꢆ

ꢅꢋRꢂAꢌ ꢂꢋꢍꢎ ꢁꢋꢅꢀꢎRꢏꢄꢋꢅꢏ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀ

ꢀꢁꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

INPUT RESISTANCE (Ω)

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢂ

ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ

INPUT RESISTANCE (Ω)

ꢀꢁꢂꢃ ꢄꢂꢅ

ꢀꢁꢂꢃ ꢄꢅꢃ

ꢀꢁꢂꢃ ꢄꢅꢂ

Measurement Time vs

Temperature

Standby Supply Current vs V⁺

Internal REG Enabled

Sleep Mode Supply Current vs V⁺

ꢀ.ꢁꢀꢂ

ꢀ.ꢁꢂꢃ

ꢀ.ꢁꢂꢂ

ꢀ.ꢀꢁꢂ

ꢀꢁ.ꢁꢁ

ꢀ.ꢁꢁ

ꢀ

ꢀꢁꢂ

ꢀꢀꢁ

ꢀꢁꢁ

ꢀ

ꢀ ꢁ

ꢀꢁ Rꢀꢁ

ꢀ

ꢀꢁꢂꢃꢄꢅRꢆꢇ

ꢀ

ꢃ ꢄ.ꢅꢀ

Rꢁꢂ

ꢃ ꢄꢀ

ꢃ ꢄ.ꢄꢀ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ ꢄꢅꢅ

ꢀꢁꢂꢃ ꢄꢅꢆ

Standby Supply Current vs V⁺

Internal REG Disabled

REFUP Supply Current vs V⁺

Internal REG Disabled

Measure Supply Current vs V⁺

Internal REG Disabled

ꢀꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢀ

ꢀ

ꢀ ꢁ

ꢀꢁ Rꢀꢁ

ꢀ

ꢀ ꢁ

ꢀꢁ Rꢀꢁ

ꢀ

ꢀ ꢁ

ꢀꢁ Rꢀꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢀ

ꢀꢁꢂꢃ ꢄꢅꢆ

Rev. A

12

For more information www.analog.com

LTC6810-1/LTC6810-2

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

V_REF1vs Temperature

V_REF2vs Temperature

V_REF2V_REGLine Regulation

ꢀ.ꢁꢂꢃ

ꢀ.ꢁꢂꢂ

ꢀ.ꢁꢂꢃ

ꢀ.ꢁꢀꢂ

ꢀ.ꢁꢁꢂ

ꢀ.ꢁꢁꢀ

ꢀ.ꢁꢁꢂ

ꢀ.ꢁꢁꢁ

ꢀ.ꢁꢁꢂ

ꢀꢁꢁ

ꢀ ꢁꢂꢃꢄꢅAꢆ ꢇꢈꢄꢁꢉ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢂ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀ

Rꢀꢁ

ꢀꢁꢂꢃ ꢄꢅꢁ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢃ

V

_REF2V⁺Line Regulation

V_REF2Load Regulation

V_REF2Long-Term Drift

ꢀꢁꢁ

ꢀꢁ

ꢀꢁꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁ

.

ꢀ ꢁꢂꢃꢄꢅAꢆ ꢇꢈꢄꢁꢉ

R

ꢀꢁ

ꢀꢁꢂꢂ

ꢀꢁꢂꢂꢂ

ꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀ.ꢁ ꢀ.ꢁ ꢀꢁ.ꢂ ꢀꢁ.ꢂ ꢀꢀ.ꢁ ꢀꢁ.ꢂ ꢀꢁ.ꢂ ꢀꢁ.ꢂ

ꢀ.ꢀꢁ

ꢀ.ꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢂꢂ

ꢀꢁꢁꢁ

ꢀꢁꢂꢂ

ꢀ

ꢀꢁAꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢆꢇRꢈꢉ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢂ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢅ

Measurement Gain Error

Hysteresis, Hot

Measurement Gain Error

Hysteresis, Cold

V_REF2Change Due to IR Reflow

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃꢄ ꢅꢆ ꢇꢂꢃꢄ

ꢀ ꢀ ꢁꢂꢃꢄ ꢅꢆ ꢇꢈꢉꢃꢄ

A

ꢀ

ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀꢁꢂꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ

ꢀꢁꢂꢂ ꢀꢁꢂꢂ ꢀꢁꢂꢂ

ꢀ

ꢀꢁꢁ

ꢀꢁAꢂꢃꢄ ꢅꢂ ꢃAꢅꢂ ꢄRRꢆR ꢇꢈꢈꢉꢊ

ꢀꢁAꢂꢃꢄ ꢅꢂ ꢆ

ꢀꢁꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢀ

Rev. A

13

For more information www.analog.com

LTC6810-1/LTC6810-2

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

V_DRIVEvs Temperature

V_DRIVEV⁺Line Regulation

V_DRIVELoad Regulation

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢀꢁ

ꢀꢁ

ꢀ

ꢀ ꢁARꢂꢃ ꢄꢅ ꢆꢅAꢇꢈ ꢉꢊA ꢆꢅAꢇ

ꢀꢁꢂ

ꢀꢁꢂꢂ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀ.ꢀꢁ

ꢀ.ꢁ

ꢀ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅ ꢀꢁ

ꢀ

ꢀRꢁꢂꢃ ꢄꢁꢅ ꢆꢇAꢀ ꢈꢉRRꢃꢅꢊ ꢋꢌAꢍ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢁ

ꢀꢁꢂꢃ ꢄꢅꢆ

V_REGPin Voltage vs

Internal V_REGLoad Regulation

V⁺Pin Voltage

ꢀ

ꢀꢁꢂꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢀꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀꢁꢀ ꢂꢃꢄꢅꢆꢀꢀꢇꢅꢈꢇꢂ ꢉRꢆꢊ ꢋ

Rꢇꢌ

ꢀꢁꢀ ꢂꢃꢀꢀꢄꢂꢅꢄꢆ ꢅꢃ ꢇ

Rꢄꢈ

ꢍꢆAꢂ ꢅꢎRRꢇꢀꢈ ꢃꢀꢅꢍꢎꢂꢇꢄ ꢃ

ꢆꢉ ꢈꢏꢇ ꢅꢏꢃꢁ

ꢇ

ꢉꢃAꢆ ꢂꢊRRꢄꢀꢅ ꢋ ꢌꢍꢎA ꢏꢐꢀꢂꢉꢊꢆꢄꢑ ꢐ

ꢒ

ꢋRꢇꢌ

ꢇRꢄꢈ

ꢀ

ꢀeꢁꢂꢃ ꢄꢅꢆ

ꢀ

ꢀ ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂve ꢃꢄꢅ

ꢀRAꢁꢂꢃꢀꢃꢄꢁ ꢅꢆꢀꢇꢆꢆꢁ ꢃꢁꢀꢆRꢁAꢈ ꢈꢉꢄ

Aꢁꢉ ꢆꢊꢀꢆRꢁAꢈ ꢁꢋꢁ ꢋꢄꢇꢆRꢆꢉ ꢌ

Rꢆꢍ

R A

R

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁAꢂ

ꢀ

ꢀꢁAꢂ ꢃꢄRRꢅꢆꢇ ꢈꢉAꢊ

Rꢀꢁ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ ꢃꢄꢅꢆAꢇꢈ ꢉꢃꢊ

ꢀꢁꢂꢃ ꢄꢅꢃ

ꢀꢁꢂꢃ ꢄꢅꢂ

ꢀꢁꢂꢃ ꢄꢅꢆ

Internal Die Temperature

Discharge Switch On-Resistance

vs Cell Voltage

Internal Die Temperature

Measurement Error vs Temperature

Increase vs Discharge Current

ꢀꢁ.ꢁ

ꢀ.ꢁ

ꢀꢁ

ꢀ

ꢀꢁ

ꢀ

ꢀ ꢁꢂꢃꢄꢅAꢆ ꢇꢈꢄꢁꢉ

ꢀꢁꢂRꢃꢄꢅꢄꢆAꢁꢇꢃ ꢀꢈ ꢅꢁꢆꢃRꢁAꢉ

ꢊꢅꢄꢇꢋARꢌꢃ ꢄꢍꢅꢆꢇꢋ ꢎꢃAꢄꢏRꢃꢊ

ꢐꢃꢆꢍꢃꢃꢁ ꢄꢑꢒꢓ Aꢁꢊ ꢄꢑꢒꢂꢔꢓ

ꢀ ꢁꢂꢃꢃ ꢄ ꢀꢅꢅꢆ

ꢀ ꢁꢂꢃꢃꢄ ꢅꢆꢆꢇ

ꢀ ꢁꢂꢃꢃꢄ ꢅꢆꢇ

ꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀꢁ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀꢁꢂꢂ ꢃꢄꢂꢅAꢆꢁ ꢇꢃꢈ

ꢀꢁꢂꢃRꢁAꢄ ꢅꢀꢆꢇꢈARꢉꢃ ꢇꢊRRꢃꢁꢂ ꢋꢌAꢍꢇꢃꢄꢄꢎ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢅ

ꢀꢁꢂꢃ ꢄꢅꢀ

Rev. A

14

For more information www.analog.com

LTC6810-1/LTC6810-2

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

isoSPI Current (READY) vs

V_REF1and V_REF2Power-Up

V_REGand V_DRIVEPower-Up

Temperature

ꢀ.ꢁ

ꢀ

ꢀ ꢁꢂA

ꢀ

Rꢀꢁꢂ

ꢀ

ꢀRꢁꢂꢃ

ꢀ

ꢀ.ꢀ

ꢀ.ꢁ

ꢀRꢁꢂꢃ

ꢀAꢁꢂꢃꢄ

ꢀ

Rꢀꢁꢂ

ꢀ

Rꢀꢁꢂ

ꢀ

Rꢀꢁ

ꢀꢁꢂꢃꢄꢁ

ꢀ

Rꢀꢁ

ꢀ

Rꢀꢁꢂ

ꢀꢁꢂꢃꢄꢁ

ꢀAꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂꢃꢄꢁ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃ ꢄꢅꢀ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢇ

ꢀꢁꢂꢃꢄꢅꢆꢇꢅꢈ ꢉꢊꢋꢌꢍ ꢎ ꢏ

ꢀ

ꢂꢁꢃꢁRAꢄꢁꢅ ꢆRꢇꢈ ꢅRꢉꢀꢁ ꢊꢉꢃ

R

ꢀꢁꢂꢃꢄꢅꢆꢇꢅꢈ ꢉꢊꢋꢌꢍ ꢎ ꢏ

Rꢁꢂ

Rꢐꢑ

R

ꢋ ꢌ ꢎ ꢏꢐꢆ

ꢍ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁꢂꢃ ꢄꢅꢁ

isoSPI Current (ACTIVE) vs

isoSPI Clock Frequency

IBIAS Voltage vs Temperature

IBIAS Voltage Load Regulation

ꢀꢁ

ꢀ

ꢀ.ꢁꢀ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢂꢁ

ꢀ.ꢁꢁꢂ

ꢀ.ꢁꢁꢁ

ꢀ.ꢁꢁꢂ

ꢀ

ꢀ ꢁꢂA

ꢀꢁꢂꢃꢄ ꢅ ꢆ

ꢀ

Rꢀꢁ

ꢀ ꢁARꢂꢃ

ꢀ

ꢀ ꢁꢂA

ꢀ

R

R A

R

ꢀ

R A

ꢀ

ꢀꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀ

ꢀꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢂꢁꢃꢀ ꢄꢅꢂꢄꢆ ꢇRꢈꢉꢊꢈꢋꢄꢌ ꢍꢎꢏꢐꢑ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀꢁꢀAꢂ ꢃꢄRRꢅꢆ ꢈ ꢀ ꢀꢁAꢂ

ꢀ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢃ

ꢀꢁꢂꢃ ꢄꢅꢂ

isoSPI Driver Current Gain

(Port A/Port B) vs IBIAS Current

isoSPI Driver Current Gain

(Port A/Port B) vs Temperature

ꢀꢁ

ꢀꢀ

ꢀꢁ

ꢀꢀ

ꢀꢁ

.

A

ꢀ

ꢀꢁꢁ

ꢀꢁꢁꢁ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀꢁꢀAꢂ ꢃꢄRRꢅꢆ ꢈ ꢀ ꢀꢁAꢂ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀ

ꢀꢁꢂꢃ ꢄꢅꢆ

Rev. A

15

For more information www.analog.com

LTC6810-1/LTC6810-2

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

isoSPI Driver Common Mode

Voltage (Port A/Port B) vs Pulse

Amplitude

isoSPI Comparator Threshold

Gain (Port A/Port B) vs ICMP

Voltage

Gain (Port A/Port B) vs Receiver

Common Mode

ꢀ.ꢀ

ꢀ.ꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢀ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ.ꢁꢂ

ꢀ.ꢁꢀ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀ ꢁARꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆ.ꢇꢀ

ꢀꢁꢂꢃꢄꢅꢆꢀ

ꢀꢁꢂꢃꢄꢄꢅA

ꢀꢁꢂꢃꢄA

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢀ

ꢀ

ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ

ꢀ

ꢀ.ꢁ ꢀ.ꢁ ꢀ.ꢁ

ꢀꢁꢂꢃꢄ Aꢅꢀꢂꢆꢇꢁꢈꢄꢉ ꢊ ꢀꢁꢂ

RꢀꢁꢀꢂꢃꢀR ꢁꢄꢅꢅꢄꢆ ꢅꢄꢇꢀꢈ ꢃ ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢆꢇAꢈꢉ ꢊꢄꢋ

A

ꢀꢁ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢅ

ꢀꢁꢂꢃ ꢄꢅꢀ

isoSPI Comparator Threshold Gain

(Port A/Port B) vs Temperature

Typical Wake-Up Pulse Amplitude

(Port A/Port B) vs Dwell Time

ꢀ.ꢁꢂ

ꢀ.ꢁꢀ

ꢀ.ꢁꢂ

ꢀ.ꢁꢁ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁ

ꢀꢁARAꢂꢃꢄꢄꢅ

ꢀAꢁꢂꢃꢄꢅ Rꢂꢆꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅꢆꢀ

ꢀꢁꢂꢃꢄꢅꢆ.ꢇꢀ

ꢀ

ꢀꢁꢂ ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ

ꢀ

ꢀꢁꢁ

ꢀꢁꢂꢃ

ꢀꢁꢁ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢀAꢁꢂꢃꢄꢅ ꢆꢀꢂꢇꢇ ꢈꢉꢊꢂꢋ ꢈ

ꢀꢁꢂꢃꢃ

ꢀꢁꢂꢃ ꢄꢅꢆ

ꢀꢁꢂꢃ ꢄꢅꢁ

Rev. A

16

For more information www.analog.com

LTC6810-1/LTC6810-2

PIN FUNCTIONS

C0 – C6: Cell Inputs.

Serial Port Pins

LTC6810-1

LTC6810-2

S0 – S6: Balance Inputs/Outputs Redundant Cell

Measurement. 6 NMOSFETs are connected between S(n)

and S(n–1) for discharging cells. Additionally S pins can

be used for redundant cell measurement.

(DAISY-CHAINABLE)

(ADDRESSABLE)

–

ISOMD = V

ISOMD = V ISOMD = V

ISOMD = V

A3

REG

PORT B

IPB

IMB

IPB

IMB

A3

A2

(Pins 39,

38, 35

and 34)

A2

+

V : Positive Supply Pin.

ICMP

IBIAS

(NC)

IPA

ICMP

IBIAS

SDO

SDI

A1

–

A0

V : Negative Supply Pins. The V pins must be shorted

PORT A

(Pins 40,

41, 37

IBIAS

ICMP

IPA

SDO

SDI

together, external to the IC.

V^–*: These pins are fused to the leadframe, connect to V^–.

SCK

CSB

SCK

CSB

and 36)

V

: Buffered 2nd reference voltage for driving thermis-

IMA

REF2

tors. Bypass with an external 1µF capacitor.

CSB, SCK, SDI, SDO: 4-Wire Serial Peripheral Interface

(SPI). Active low chip select (CSB), serial clock (SCK),

serial data in (SDI), are digital inputs. Serial data out

(SDO) is an open drain NMOS output. SDO requires a 5K

pull-up resistor

V

: ADC Reference Voltage. Bypass with an external

REF1

1µF capacitor. No DC loads allowed.

GPIO[1:4]: General Purpose I/O. Can be used as digital

inputs or digital outputs, or as analog inputs with a mea-

–

surement range from V to 5V. GPIO[2:4] can be used as

A0–A3: Address Pins. These digital inputs are connected

to V_REGor V^–to set the chip address for addressable

serial commands.

2

an I C or SPI port.

DTEN: Discharge Timer Enable. Connect this pin to V

to enable the Discharge Timer.

REG

IPA, IMA: Isolated 2-Wire Serial Interface Port A. IPA

(plus) and IMA (minus) are a differential input/output pair.

DRIVE: Connect the base of an NPN to this pin. Connect

+

the collector to V and the emitter to V

.

IPB, IMB: Isolated 2-Wire Serial Interface Port B. IPB

(plus) and IMB (minus) are a differential input/output pair.

REG

V_REG: 5V Regulator Input. Bypass with an external 1μF

capacitor.

–

IBIAS: Isolated Interface Current Bias. Tie IBIAS to V

through a resistor divider to set the interface output cur-

rent level. When the isoSPI interface is enabled, the IBIAS

pin voltage is 2V. The IPA/IMA or IPB/IMB output current

ISOMD: Serial Interface Mode. Connecting ISOMD to

V_REGconfigures the LTC6810 for 2-wire isolated interface

–

(isoSPI) mode. Connecting ISOMD to V configures the

drive is set to 20 times the current, I , sourced from the

B

LTC6810 for 4-wire SPI mode.

IBIAS pin.

WDT: Watchdog Timer Output Pin. This is an open drain

ICMP: Isolated Interface Comparator Voltage Threshold

NMOS digital output. It can be left unconnected, or con-

Set. Tie this pin to the resistor divider between IBIAS

nected with a 1M resistor to V . If the LTC6810 does

REG

–

and V to set the voltage threshold of the isoSPI receiver

not receive a valid command within 2 seconds, the watch-

dog timer circuit will reset the LTC6810 and the WDT pin

will go high impedance.

comparators. The comparator thresholds are set to ½ the

voltage on the ICMP pin.

Rev. A

17

For more information www.analog.com

LTC6810-1/LTC6810-2

BLOCK DIAGRAM

LTC6810-1

ꢒ

ꢁ

ꢍ

ꢋꢋ

ꢋꢀ

ꢋꢌ

ꢋꢍ

ꢋꢎ

ꢀꢡ

ꢀꢇ

ꢀꢈ

ꢀꢉ

ꢀꢊ

ꢀꢋ

ꢀꢀ

ꢀꢌ

ꢀꢍ

ꢀꢎ

ꢌꢡ

ꢌꢇ

ꢌꢈ

ꢌꢉ

ꢌꢊ

ꢌꢋ

ꢌꢀ

ꢁ

ꢌ

ꢀ

ꢋ

ꢊ

ꢉ

ꢈ

ꢇ

ꢡ

ꢗꢏ

ꢉ ꢐAꢠAꢗꢏꢄ ꢛꢄꢔꢦ

ꢕꢖꢧꢘ

ꢜ

ꢁ

ꢓꢑꢔ

ꢕꢑꢆꢖꢗꢏꢘ

ꢏꢉ

ꢕꢉ

ꢏꢊ

ꢕꢊ

ꢏꢋ

ꢕꢋ

ꢕꢖꢧꢒꢍꢘ

ꢑꢆꢅꢆꢔAꢠ

ꢛꢆꢠꢔꢄR

ꢕꢑꢃꢖꢗꢏꢘ

ꢆꢂꢐ

ꢠꢃꢅꢆꢏ

Aꢗꢑ

ꢕꢄRꢆAꢠ ꢆꢣꢃ

ꢙꢄꢙꢃRꢢ

ꢏꢉ

ꢏꢊ

ꢏꢋ

ꢏꢀ

ꢏꢌ

ꢏꢍ

ꢏꢎ

ꢆꢙꢐ

ꢂ

ꢜ

ꢒ

ꢑꢆꢅꢆꢔAꢠ

ꢛꢆꢠꢔꢄR

ꢏ ꢂꢆꢗ

ꢙꢤꢥ

Aꢑꢏ

ꢕꢏꢚꢖꢆꢂAꢘ

ꢏꢕꢐꢖꢆꢙAꢘ

ꢆꢏꢙꢂ

ꢙ

ꢕꢄRꢆAꢠꢝꢍꢞꢡꢟ

ꢕꢉ

ꢕꢊ

ꢕꢋ

ꢕꢀ

ꢕꢌ

ꢕꢍ

ꢕꢎ

ꢍꢎ ꢏꢀ

ꢍꢍ ꢕꢀ

ꢍꢌ ꢏꢌ

ꢍꢀ ꢕꢌ

ꢍꢋ ꢏꢍ

ꢍꢊ ꢕꢍ

ꢍꢉ ꢏꢎ

ꢍꢈ ꢕꢎ

ꢂ

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ꢆꢐꢆAꢕ

ꢙ

ꢜ

ꢍꢕꢔ

RꢄꢛꢄRꢄꢗꢏꢄ

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ꢑRꢆꢁꢄ

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ꢠꢑꢃ ꢖꢁ

ꢑꢆꢄ

ꢘ

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ꢂꢃR

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Rꢄꢛꢍ

ꢌꢗꢑ

RꢄꢛꢄRꢄꢗꢏꢄ

ꢒ

ꢜ

ꢆꢇ

ꢆꢈ

ꢆꢉ

ꢆꢊ

ꢆꢋ

ꢆꢀ

ꢆꢌ

ꢆꢍ

ꢆꢎ

ꢁ

ꢀꢁ

Rꢄꢅ

ꢒ

ꢁ

ꢂ

Aꢤꢥ

ꢙꢤꢥ

ꢕꢏ

ꢆꢕꢃꢙꢑ

ꢑꢔꢄꢗ

ꢅꢂꢆꢃꢍ

ꢙ

ꢍꢇ

ꢍꢡ

ꢌꢎ

ꢌꢍ

ꢌꢌ

ꢒ

ꢁ

ꢅꢂꢆꢃꢌ

ꢅꢂꢆꢃꢀ

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ꢔꢆꢙꢄR

ꢅꢂꢆꢃꢋ

ꢅꢂꢆꢃꢝꢋꢞꢍꢟ

ꢒ

ꢁ

ꢒ

ꢁ

ꢉꢇꢍꢎꢍ ꢐꢑꢍ

Rev. A

18

For more information www.analog.com

LTC6810-1/LTC6810-2

BLOCK DIAGRAM

LTC6810-2

ꢒ

ꢁ

ꢍ

ꢋꢋ

ꢒ

ꢁ

ꢌ

ꢀ

ꢋ

ꢊ

ꢉ

ꢈ

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ꢡ

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ꢜ

ꢁ

ꢋꢌ

ꢋꢍ

ꢋꢎ

ꢀꢡ

ꢀꢇ

ꢀꢈ

ꢀꢉ

ꢀꢊ

ꢀꢋ

ꢀꢀ

ꢀꢌ

ꢀꢍ

ꢀꢎ

ꢌꢡ

ꢌꢇ

ꢌꢈ

ꢌꢉ

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ꢌꢋ

ꢌꢀ

ꢓꢑꢔ

ꢕꢑꢆꢖꢆꢐꢆAꢕꢗ

ꢏꢉ

ꢕꢉ

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ꢏꢋ

ꢕꢋ

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ꢕꢑꢃꢖꢆꢏꢘꢂꢗ

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ꢕꢉ

ꢕꢊ

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ꢕꢀ

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ꢕꢍ

ꢕꢎ

ꢍꢎ ꢏꢀ

ꢍꢍ ꢕꢀ

ꢍꢌ ꢏꢌ

ꢍꢀ ꢕꢌ

ꢍꢋ ꢏꢍ

ꢍꢊ ꢕꢍ

ꢍꢉ ꢏꢎ

ꢍꢈ ꢕꢎ

ꢂ

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ꢘꢣꢤ

Aꢎ

ꢘ

ꢜ

ꢍꢕꢔ

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ꢀꢁ

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Rꢄꢚꢍ

ꢌꢛꢑ

RꢄꢚꢄRꢄꢛꢏꢄ

ꢒ

ꢜ

ꢆꢇ

ꢆꢈ

ꢆꢉ

ꢆꢊ

ꢆꢋ

ꢆꢀ

ꢆꢌ

ꢆꢍ

ꢆꢎ

ꢁ

ꢀꢁ

Rꢄꢅ

ꢒ

ꢁ

ꢂ

Aꢣꢤ

ꢘꢣꢤ

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ꢆꢕꢃꢘꢑ

ꢑꢔꢄꢛ

ꢅꢂꢆꢃꢍ

ꢘ

ꢍꢇ

ꢍꢡ

ꢌꢎ

ꢌꢍ

ꢌꢌ

ꢒ

ꢁ

ꢅꢂꢆꢃꢌ

ꢅꢂꢆꢃꢀ

ꢑꢆꢕꢏꢧARꢅꢄ

ꢔꢆꢘꢄR

ꢅꢂꢆꢃꢋ

ꢅꢂꢆꢃꢝꢋꢞꢍꢟ

ꢒ

ꢁ

ꢒ

ꢁ

ꢉꢇꢍꢎꢍ ꢐꢑꢌ

Rev. A

19

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

STATE DIAGRAM

this case, the internal regulator must be disabled to avoid

contention by floating the DRIVE pin. For more details see

REG

The operation of the LTC6810 is divided into two separate

sections: the Core circuit and the isoSPI circuit. Both sec-

tions have an independent set of operating states, as well

as a shutdown timeout.

V

Configurations.

When a valid ADC command is received or the REFON

bit is set to 1 in the Configuration Register Group, the

IC pauses for t

to allow for the references to power

REFUP

up and then enters either the REFUP or MEASURE state.

Otherwise, if no valid commands are received for t

the IC returns to the SLEEP state if DTEN = 0 or enters

the EXTENDED BALANCING state if DTEN = 1.

CORE LTC6810 STATE DESCRIPTIONS

SLEEP State

,

SLEEP

The references and ADC modulator are powered down.

The watchdog timer (see Watchdog and Discharge Timer)

has timed out. The discharge timer is either disabled or

timed out. The supply currents are reduced to minimum

levels. The isoSPI ports will be in the IDLE state. The Drive

pin is 0V. All state machines are reset to their default state

REFUP State

To reach this state the REFON bit in the Configuration

Register Group must be set to 1 (using the WRCFG com-

mand, see Table 40). The ADCs are off. The references

are powered up so that the LTC6810 can initiate ADC

conversions more quickly than from the STANDBY state.

If a WAKEUP signal is received (see Waking Up the Serial

Interface), the LTC6810 will enter the STANDBY state.

When a valid ADC command is received, the IC goes to

the MEASURE state to begin the conversion. Otherwise,

the LTC6810 will return to the STANDBY state when the

REFON bit is set to 0, (using WRCFGA command). If no

STANDBY State

The references and the ADC are off. The watchdog timer

and/or the discharge timer is running. V

pin is pow-

REG

valid commands are received for t

, the IC returns

SLEEP

ered to 5.2V through an external transistor controlled by

to the SLEEP state if DTEN = 0 or enters the EXTENDED

+

the DRIVE pin. Alternatively, when V is less than 12V,

BALANCING state if DTEN = 1

V

can be powered through the internal LDO to 4.7V.

can also be powered through an external source. In

REG

CORE LTC6810

isoSPI PORT

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ꢕꢉꢗꢊ ꢙꢕꢎꢊꢆꢒꢙ

ꢋꢘ

ꢋꢅꢆRꢊ ꢌ ꢔꢗꢊꢊꢓꢍ

ꢋꢘ

ꢍ

ꢋꢅꢆRꢊ ꢌ ꢔꢙAꢇꢉꢚꢛꢍ

ꢋꢘ

ꢍ

ꢔꢗꢊꢊꢓ

ꢏAꢐꢊ

ꢍ

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ꢍ

ꢕꢉꢗꢊ

ꢏAꢐꢊ

ꢉꢅꢙꢆ RꢊAꢅꢢꢊꢔ ꢃ

ꢍ

ꢏꢉ ꢙꢕꢎꢊꢆꢒꢙ

Aꢇꢉ ꢉꢙꢊꢇ ꢌ ꢂ

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Rꢊꢄꢆꢇ ꢌ ꢃ

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Rꢊꢄꢆꢇ ꢌ ꢂ

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Rꢊꢄꢒꢓ Aꢉꢅ

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Aꢇꢉ ꢉꢙꢊꢇ ꢌ ꢂ

ꢉꢙꢎ

ꢎꢊAꢔꢒRꢊ

Figure 1. LTC6810 Operation State Diagram

Rev. A

20

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

MEASURE State

isoSPI STATE DESCRIPTIONS

The LTC6810 performs ADC conversions in this state. The

references and ADCs are powered up.

Note: The LTC6810-1 has two isoSPI ports (A and B), for

daisy-chain communication. The LTC6810-2 has only one

isoSPI port (A), for parallel-addressable communication.

After ADC conversions are complete the LTC6810 will

transition to either the REFUP or STANDBY states,

depending on the REFON bit. Additional ADC conversions

can be initiated more quickly by setting REFON = 1 to take

advantage of the REFUP state.

IDLE State

The isoSPI ports are powered down.

When isoSPI port A or port B (LTC6810-1 only) receives a

WAKEUP signal (see Waking up the Serial Interface), the

isoSPI enters the READY state. This transition happens

quickly (within t_READY) if the Core is in the STANDBY state.

If the Core is in the SLEEP state when the isoSPI receives

a WAKEUP signal, the it transitions to the READY state

Note: Non-ADC commands do not cause a Core state tran-

sition. Only an ADC Conversion or DIAGN command will

place the Core in the MEASURE state.

EXTENDED BALANCING State

within t

.

WAKE

The watchdog timer has timed out, but the discharge timer

has not yet timed out (DTEN = 1). Discharge by PWM may

be in progress. If the Discharge Timer Monitor is enabled

then the LTC6810 will transition to the DTM MEASURE

state every 30 seconds to measure the cell voltages. If a

WAKEUP signal is received, the LTC6810 will transition

from EXTENDED BALANCING state to STANDBY state.

READY State

The isoSPI port(s) are ready for communication. Port

B is enabled only for LTC6810-1, and is not present on

the LTC6810-2. The serial interface current in this state

depends on if the part is LTC6810-1 or LTC6810-2, the

status of the ISOMD pin, and R_BIAS= R_B1+ R_B2(the

Discharge Timer Monitor MEASURE State

external resistors tied to the I

pin).

BIAS

The watchdog timer has timed out but background moni-

toring has been enabled (DTMEN = 1 in the Configuration

Register). The LTC6810 enters this state from the

EXTENDED BALANCING state once every 30 seconds to

measure the cell voltages. The LTC6810 is in the highest

core power state and an A/D conversion is in progress. If

a WAKEUP signal is received, the LTC6810 will transition

from DTM MEASURE state to STANDBY state.

If there is no activity (i.e. no WAKEUP signal) for greater

than t = 5.5ms, the LTC6810 goes to the IDLE state.

IDLE

When the serial interface is transmitting or receiving data

the LTC6810 goes to the ACTIVE state.

ACTIVE State

The LTC6810 is transmitting/receiving data using one

or both of the isoSPI ports. The serial interface con-

sumes maximum power in this state. The supply current

increases with clock frequency as the density of isoSPI

pulses increases.

Rev. A

21

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

POWER CONSUMPTION

Table 1 provides typical values for I and I

sup-

VP

REG(Core)

ply currents in each of the Core states. Table 2 provides

+

The LTC6810 is powered via two pins: V and V . The

REG

equations to approximate I

supply pin currents

+

REG(isoSPI)

in each of the isoSPI states.

V input requires voltage greater than or equal to the top

cell voltage minus 0.3V, and it provides power to the high

voltage elements of the core circuitry. The V_REGinput

requires 5V and provides power to the remaining core

circuitry and the isoSPI circuitry.

Table 1. Core Supply Current

STATE

I

REG(CORE)

VP

V

= 0V

= 5V

5.7µA

3.5µA

75µA

20µA

30µA

50µA

0µA

REG

SLEEP

The power consumption varies according to the opera-

3.3µA

55µA

tional states. The V

input can be powered through an

REG

STANDBY, Int Regulator Enabled

STANDBY, Int Regulator Disabled

REFUP

external transistor that is driven by the regulated DRIVE

output pin, through the internal LDO, or through an exter-

55µA

1.7mA

6.1mA

+

nal supply. The internal LDO is powered from V , so in

MEASURE

this configuration V

current also comes from V . Total

REG

+

V current when using the internal LDO to power V

is

REG

Table 2. isoSPI Supply Current Equations

given by,

isoSPI

STATE

ISOMD

CONNECTION

I

REG(isoSPI)

I

= I + I

VP REG

VP_INTREG

IDLE

N/A

0mA

I

current depends only on the Core state. However, I

REG

VP

READY

V

2.2mA + 3 • I

1.5mA + 3 • I

REG

–

B

current depends on both the Core state and isoSPI state,

V

and can therefore be divided into two components. The

isoSPI interface draws current only from the V

ACTIVE

V

REG

⎛

⎞

⎟

⎠

100ns

pin.

Write: 2.5mA + 3+ 20 •

•I

B

⎜

REG

t

⎝

CLK

I

= I

+ I

REG(Core) REG(isoSPI)

REG

⎛

⎞

⎟

⎠

100ns • 1.5

Read: 2.5mA + 3+ 20 •

•I

B

⎜

t

⎝

CLK

–

V

⎛

⎞

⎟

⎠

100ns

1.8mA + 3+ 20 •

•I

B

⎜

t

⎝

CLK

Rev. A

22

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

V

CONFIGURATIONS

Figure 3 shows a typical configuration for LTC6810 that

REG

uses an external transistor to power V . Note that this

REG

This section describes the different configurations that

can be used to power V

pin voltage is less than 12V, the DRIVE pin voltage drops

below its nominal value as the regulator on the DRIVE pin

does not have sufficient headroom. Under these condi-

+

configuration can still be used if V drops below 12V,

+

on the LTC6810. When V

REG

but when V

pin voltage set by the external transistor

REG

drops below the internal LDO level, the internal LDO will

take over and power V

.

REG

tions V

pin cannot be powered through an external

transist^Ro^Er.^GTo overcome this problem, LTC6810 has an

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ꢇ.ꢉꢈ

ꢒꢓꢔꢃꢄꢀꢅ

ꢌ

ꢈ

internal LDO that powers the V

pin to 4.7V typically.

REG

ꢍRꢎꢈꢏ

+

The internal LDO can operate for V pin voltage as low as

5V. The internal LDO is enabled by applying a load current

greater than 15µA on the DRIVE pin. Figure 2 shows a

typical configuration for LTC6810 using the internal LDO

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Rꢏꢐ

ꢀꢁꢂ

ꢑ

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ꢃꢄꢀꢅꢀ ꢂꢅꢆ

Figure 3. V_REGPowered by External Transistor

+

when V is less than 12V. The suggested 100K resistor on

the DRIVE pin draws a minimum of 30µA from the DRIVE

pin. This keeps the internal regulator enabled.

Alternatively, V

pin can also be powered from an exter-

nal source. In t^Rh^Eis^Gconfiguration, it is important to ensure

that the internal LDO is always shutdown so there is no

contention problem. This can be achieved by floating the

DRIVE pin. Figure 4 shows a typical configuration for

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ꢈ

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LTC6810 when V

is powered from an external source.

REG

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Figure 2. V_REGPowered by Internal LDO

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The power dissipation across the pass transistor in the

internal LDO is (V⁺– V_REG) • I_REG. To limit the power

ꢍ

ꢇ

ꢀꢁꢂꢃꢂ ꢄꢃꢅ

dissipation inside the part it is recommended to power

Figure 4. V_REGPowered by an Independent Supply

+

V

using an external transistor when V pin voltage is

REG

greater than 12V. The external transistor is driven by the

regulated DRIVE pin voltage that sets V pin voltage to

REG

5.2V typically. The internal LDO is designed to only source

current, so when V pin is driven to 5.2V by the external

REG

transistor the internal regulator is gracefully shutdown.

Rev. A

23

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

ADC OPERATION

in STANDBY state, an additional t

time is required to

REFUP

power up the reference before beginning the ADC conver-

sions. The reference can remain powered up between ADC

conversions if the REFON bit in Configuration Register

Group is set to 1 so the Core is in REFUP state after a

There is one ADC inside the LTC6810. The ADC is used to

measure the cell voltages via the C or S pins and general

purpose inputs.

delay t

. If REFON is set to 1 the Core will go from

REFUP

ADC Modes

STANDBY to the REFUP state after a delay t

. Then,

REFUP

The ADCOPT bit (CFGR0[0]) in the Configuration Register

Group and the mode selection bits MD[1:0] in the conver-

sion command together provide eight modes of operation

for the ADC which correspond to different oversampling

ratios (OSR). The accuracy and timing of these modes

are summarized in Table 3. In each mode, the ADC first

measures the inputs, and then performs a calibration. The

names of the modes are based on the –3dB bandwidth of

the ADC measurement.

the subsequent ADC commands will not have the t

delay before beginning ADC conversions.

REFUP

ADC Range and Resolution

The cell inputs and GPIO inputs have the same range and

resolution. The ADC inside the LTC6810 has an approxi-

mate range from –0.82V to +5.73V. Negative readings are

rounded to 0V. The format of the data is a 16-bit unsigned

integer where the LSB represents 100µV. Therefore, a

reading of 0x80E8 (33,000 decimal) indicates a measure-

ment of 3.3V.

Mode 7kHz (Normal Mode): In this mode, the ADC has

high resolution and low TME (total measurement error).

This is considered the normal operating mode because of

the optimum combination of speed and accuracy.

ꢒ

ꢃꢈRꢜAꢉ ꢜꢈꢀꢋ

ꢛꢂꢉꢆꢋRꢋꢀ ꢜꢈꢀꢋ

ꢎ.ꢓ

Mode 27kHz (Fast Mode): In this mode, the ADC has

maximum throughput but has some increase in TME (total

measurement error). So this mode is also referred to as

the fast mode. The increase in speed comes from a reduc-

tion in the oversampling ratio. This results in an increase

in noise and average measurement error.

ꢎ.ꢗ

ꢎ.ꢔ

ꢎ.ꢘ

ꢎ.ꢕ

ꢎ.ꢙ

ꢎ.ꢖ

ꢎ.ꢚ

ꢎ.ꢒ

ꢎ

Mode 26Hz (Filtered Mode): In this mode, the ADC digital

filter –3dB frequency is lowered to 26Hz by increasing the

OSR. This mode is also referred to as the filtered mode

due to its low –3dB frequency. The accuracy is similar to

the 7kHz (normal) mode with lower noise.

ꢎ

ꢎ.ꢕ

ꢒ

ꢒ.ꢕ

ꢚ

ꢚ.ꢕ

ꢖ

ꢖ.ꢕ

ꢙ

ꢙ.ꢕ

ꢕ

Aꢀꢁ ꢂꢃꢄꢅꢆ ꢇꢈꢉꢆAꢊꢋ ꢌꢇꢍ

ꢘꢗꢒꢎꢒ ꢛꢎꢕ

Figure 5.

Modes 14kHz, 3kHz, 2kHz, 1kHz and 422Hz: Modes

14kHz, 3kHz, 2kHz, 1kHz and 422Hz provide additional

options to set the ADC digital filter –3dB at 13.5kHz,

3.4kHz, 1.7kHz, 845Hz and 422Hz respectively. The accu-

racy of the 14kHz mode is similar to the 27kHz (fast)

mode. The accuracy of 3kHz, 2kHz, 1kHz and 422Hz

modes is similar to the 7kHz (normal) mode.

Delta-Sigma ADCs have quantization noise which depends

on the input voltage, especially at low Over Sampling

Ratios (OSR), such as in fast mode. In some of the ADC

modes, the quantization noise increases as the input volt-

age approaches the upper and lower limits of the ADC

range. For example, the total measurement noise versus

input voltage in normal and filtered modes is shown in

Figure 5.

The filter bandwidths and the conversion times for these

modes are provided in Table 3 and Table 5. If the Core is

Rev. A

24

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Table 3. ADC Filter Bandwidth, Accuracy and Speed

MODE

27kHz (Fast Mode)

14kHz

–3dB FILTER BW

27kHz

–40dB FILTER BW

84kHz

TME SPEC AT 3.3V, 25°C

TME SPEC AT 3.3V, –40°C, 125°C

5.5mV

1.8mV

5.5mV

2.4mV

13.5kHz

6.8kHz

42kHz

7kHz (Normal Mode)

3kHz

21kHz

3.4kHz

10.5kHz

5.3kHz

2kHz

1.7kHz

1kHz

845Hz

2.6kHz

422Hz

1.3kHz

26Hz (Filtered Mode)

26Hz

82Hz

Note: TME is the total measurement error.

Table 4. ADC Range and Resolution

SPECIFIED

RANGE

PRECISION

NOISE FREE

1

2

3

MODE

27kHz (fast)

14kHz

FULL RANGE

RANGE

LSB

FORMAT

MAX NOISE

RESOLUTION

4mV

1mV

10 Bits

P-P

12 Bits

7kHz (normal)

3kHz

250µV

150µV

100µV

14 Bits

P-P

14 Bits

–0.8192V to

5.7344V

0V to 5V

0.5V to 4.5V

100µV

Unsigned 16 Bits

2kHz

15 Bits

1kHz

15 Bits

422Hz

15 Bits

26Hz (filtered)

50µV

16 Bits

1. Negative readings are rounded to 0V.

2. PRECISION RANGE is the range over which the noise is less than MAX NOISE.

3. NOISE FREE RESOLUTION is a measure of the noise level within the PRECISION RANGE.

The specified range of the ADC is 0V to 5V. In Table 4, the

precision range of the ADC is arbitrarily defined as 0.5V

to 4.5V. This is the range where the quantization noise is

relatively constant even in the lower OSR modes (see

Figure 5). Table 4 summarizes the total noise in this range

for all eight ADC operating modes. Also shown is the

noise free resolution. For example, 14-bit noise free reso-

lution in normal mode implies that the top 14 bits will be

noise free with a DC input, but that the 15th and 16th least

significant bits (LSB) will flicker.

Rev. A

25

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

ꢈ

ꢇꢉꢇꢃꢁ

ꢈ

Rꢁꢆꢒꢐ

ꢈ

ꢀꢊꢁꢋꢌ

ꢀꢁRꢂAꢃ

ꢂꢄꢅꢁRꢆAꢇꢁ

Aꢍꢇꢎ ꢏ ꢐꢁꢇ

ꢑꢁAꢀꢒRꢁ

ꢇꢘ ꢅꢔ ꢇꢙ

ꢑꢁAꢀꢒRꢁ

ꢇꢌ ꢅꢔ ꢇꢘ

ꢑꢁAꢀꢒRꢁ

ꢇꢗ ꢅꢔ ꢇꢌ

ꢑꢁAꢀꢒRꢁ

ꢇꢕ ꢅꢔ ꢇꢗ

ꢑꢁAꢀꢒRꢁ

ꢇꢓ ꢅꢔ ꢇꢕ

ꢑꢁAꢀꢒRꢁ

ꢇꢖ ꢅꢔ ꢇꢓ

Aꢍꢇꢘ

ꢇAꢃꢂꢚRAꢅꢁ

ꢈ

ꢙ

ꢈ

ꢕꢑ

ꢈ

ꢓꢑ

ꢈ

ꢖꢑ

ꢈ

ꢇ

ꢖꢛꢘꢙꢘ ꢆꢙꢖ

ꢘꢑ

ꢌꢑ

ꢗꢑ

Figure 6. Timing for ADCV Command Measuring All 6 Cells, SCONV = 0

Table 5. Conversion and Synchronization Times for ADCV Command Measuring All Six Cells, SCONV = 0

CONVERSION TIMES (in µs)

SYNCHRONIZATION TIME

(IN µs)

MODE

27kHz

14kHz

7kHz

t

SKEW2

0

1M

2M

5M

6M

C,MCAL = 0

C,MCAL = 1

0

57

87

104

162

244

390

291

465

524

1,106

233

699

1,165

1,281

2,328

379

670

145

279

681

815

3kHz

261

511

1,262

2,426

4,753

9,408

149,044

1,513

2,909

5,702

11,287

178,851

1,863

3,026

1,252

2,415

2kHz

494

977

3,259

4,423

1kHz

959

1,908

3,770

59,624

6,052

7,215

4,742

422Hz

26Hz

1,890

29,818

11,637

182,692

12,801

201,310

9,397

149,033

Table 5 shows the conversion times for the ADCV com-

mand measuring all six cells. The total conversion time is

Table 6 shows the conversion time for ADCV command

measuring only 1 cell. t indicates the total conversion

C

given by t which indicates the end of the calibration step.

time for this command.

C

Table 6. Conversion Times for ADCV Command Measuring Only

One Cell, SCONV = 0

Figure 7 illustrates the timing of the ADCV command that

measures only one cell.

CONVERSION TIMES (in μs)

MODE

27kHz

t

C

0

1M

ꢒ

Rꢁꢆꢎꢋ

ꢇꢗꢇꢃꢁ

0

57

87

200

229

ꢀꢁRꢂAꢃ

Aꢈꢇꢉ ꢊ ꢋꢁꢇ

14kHz

7kHz

3kHz

2kHz

1kHz

422Hz

26Hz

ꢂꢄꢅꢁRꢆAꢇꢁ

145

404

ꢍꢁAꢀꢎRꢁ

ꢇꢏ ꢅꢐ ꢇꢑ

Aꢈꢇꢑ

ꢇAꢃꢂꢌRAꢅꢁ

261

520

494

753

ꢒ

ꢓ

ꢒ

ꢇ

ꢑꢍ

ꢔꢕꢑꢓꢑ ꢆꢓꢖ

959

1,218

2,149

33,567

1,890

29,817

Figure 7. Timing for ADCV command measuring 1 cell,

SCONV = 0

Rev. A

26

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Under/Over Voltage Monitoring

the GPIOs and the 2nd reference separately or to mea-

sure S0, all four GPIOs and the 2nd reference in a single

command. See the section on Commands for the ADAX

command format. All auxiliary measurements are relative

Whenever the C inputs are measured, the results are

compared to under voltage and over voltage thresholds

stored in memory. If the reading of a cell is above the over

voltage limit, a bit in memory is set as a flag. Similarly,

measurement results below the under voltage limit cause

a flag to be set. The over voltage and under voltage thresh-

olds are stored in the Configuration Register Group. The

flags are stored in Status Register Group B.

–

to the V pin voltage. This command can be used to read

external temperature by connecting the temperature sen-

sors to the GPIOs. These sensors can be powered from

the 2nd reference which is also measured by the ADAX

command, resulting in precise ratiometric measurements.

Figure 8 illustrates the timing of the ADAX command mea-

suring S0, all GPIOs and the 2nd reference. The 2nd refer-

ence is measured after GPIO4.

Auxiliary (GPIO) Measurements (ADAX Command)

The ADAX command initiates the measurement of the

GPIO inputs. This command has options to select which

GPIO input to measure (GPIO1–4) and which ADC mode

to use. The ADAX command also measures the S0 pin and

Table 7 shows the conversion time for the ADAX com-

mand measuring S0, all the GPIOs and the 2nd reference.

t indicates the total conversion time.

C

–

the 2nd reference relative to the V pin voltage. There are

The timing for ADAX measuring a single auxiliary is the

same as ADCV measuring a single cell.

options in the ADAX command to measure subsets of S0,

ꢈ

ꢇꢉꢇꢃꢁ

ꢈ

Rꢁꢆꢑꢏ

ꢈ

ꢀꢊꢁꢋ

ꢀꢁRꢂAꢃ

ꢂꢄꢅꢁRꢆAꢇꢁ

Aꢌꢇꢍ ꢎ ꢏꢁꢇ

ꢐꢁAꢀꢑRꢁ

ꢀꢘ

ꢐꢁAꢀꢑRꢁ

ꢒꢏꢂꢓꢗ

ꢐꢁAꢀꢑRꢁ

ꢒꢏꢂꢓꢕ

ꢐꢁAꢀꢑRꢁ

ꢒꢏꢂꢓꢖ

ꢐꢁAꢀꢑRꢁ

ꢒꢏꢂꢓꢔ

ꢐꢁAꢀꢑRꢁ

ꢕꢄꢌ Rꢁꢆ

Aꢌꢇꢗ

ꢇAꢃꢂꢛRAꢅꢁ

ꢈ

ꢙꢐ

ꢈ

ꢇ

ꢚꢜꢗꢘꢗ ꢆꢘꢜ

ꢘ

ꢗꢐ

ꢕꢐ

ꢖꢐ

ꢔꢐ

ꢚꢐ

Figure 8. Timing for ADAX Command Measuring All GPIOs and 2nd Reference

Table 7. Conversion and Synchronization Times for ADAX Command Measuring S0, All GPIOs and 2nd Reference

CONVERSION TIMES (in µs)

MODE

27kHz

14kHz

7kHz

t

C,MCAL = 1

0

1M

2M

3M

4M

5M

6M

C,MCAL = 0

0

57

87

104

162

151

238

197

314

244

390

291

465

521

695

1,103

1,277

2,324

145

279

413

547

681

815

1,161

1,859

3,255

6,048

11,634

182,688

3kHz

261

511

762

1,012

1,943

3,805

7,529

119,238

1,262

2,426

4,753

9,408

149,044

1,513

2,909

5,702

11,287

178,851

3,023

2kHz

494

977

1,460

2,856

5,649

89,431

4,419

1kHz

959

1,908

3,770

59,624

7,212

422Hz

26Hz

1,890

29,818

12,797

201,306

Rev. A

27

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Auxiliary (GPIO) Measurements with Digital

Redundancy (ADAXD Command)

simplifies the synchronization of battery cell voltage and

current measurements when a current sensor is con-

nected to the GPIO1 input. Figure 9 illustrates the timing

of ADCVAX command with SCONV set to 0. See the sec-

tion on Commands for the ADCVAX command format. The

time values in Figure 9 assume the ADC is operating in

the 27kHz (fast) mode. The synchronization of the current

and voltage measurements, t_SKEW1, in fast mode is

within 196µs.

The ADAXD command operates similarly to the ADAX

command except that an additional diagnostic is per-

formed using digital redundancy. See A/D Conversion

with Digital Redundancy.

The execution time of ADAX and ADAXD is the same.

Measuring Cell Voltages and GPIOs (ADCVAX

Command)

Table 8 shows the conversion and synchronization

time for the ADCVAX command in different modes with

SCONV = 0. The total conversion time for the command

The ADCVAX command combines six cell measurements

with measurements of S0 and GPIO1. This command

is given by t .

C

ꢈ

ꢇꢉꢇꢃꢁ

ꢈ

Rꢁꢆꢓꢐ

ꢈ

ꢀꢊꢁꢋꢌ

ꢀꢁRꢂAꢃ

ꢂꢄꢅꢁRꢆAꢇꢁ

Aꢍꢇꢎ ꢏ ꢐꢁꢇ

ꢒꢁAꢀꢓRꢁ

ꢇꢌ ꢅꢕ ꢇꢚ

ꢒꢁAꢀꢓRꢁ

ꢇꢛ ꢅꢕ ꢇꢌ

ꢒꢁAꢀꢓRꢁ

ꢇꢘ ꢅꢕ ꢇꢛ

ꢒꢁAꢀꢓRꢁ

ꢀꢚ

ꢒꢁAꢀꢓRꢁ

ꢙꢐꢂꢕꢌ

ꢒꢁAꢀꢓRꢁ

ꢇꢗ ꢅꢕ ꢇꢘ

ꢒꢁAꢀꢓRꢁ

ꢇꢖ ꢅꢕ ꢇꢗ

ꢒꢁAꢀꢓRꢁ

ꢇꢔ ꢅꢕ ꢇꢖ

Aꢍꢇ

ꢇAꢃꢂꢑRAꢅꢁ

ꢈ

ꢚ

ꢈ

ꢗꢒ

ꢈ

ꢖꢒ

ꢈ

ꢔꢒ

ꢈ

ꢇ

ꢔꢝꢌꢚꢌ ꢆꢚꢞ

ꢌꢒ

ꢛꢒ

ꢘꢒ

ꢜꢒ

ꢝꢒ

Figure 9. Timing of ADCVAX command, SCONV = 0

Table 8. Conversion and Synchronization Times for ADCVAX Command, SCONV = 0

SYNCHRONIZATION

TIME (IN µs)

CONVERSION TIMES (in µs)

MODE

27kHz

14kHz

7kHz

t

SKEW1

0

1M

2M

3M

4M

5M

6M

7M

8M

C,MCAL = 0 C,MCAL = 1

0

57

87

104

162

151

238

205

321

251

397

305

480

352

556

399

631

682

915

1,497

1,730

194

310

543

145

261

494

959

1,890

279

413

554

688

829

963

1,097

2,028

3,890

7,613

1,497

2,427

4,289

8,013

15,460

3,126

3kHz

511

762

1,019

1,950

3,812

7,536

1,270

2,433

4,760

9,415

1,527

2,923

5,716

1,777

3,407

6,665

4,057

1,008

1,939

2kHz

977

1,460

2,856

5,649

5,918

1kHz

1,908

3,770

9,642

3,801

422Hz

26Hz

11,302 13,181 15,060

17,089

268,435

7,525

29,817 59,624 89,431 119,245 149,051 178,865 208,672 238,479 242,369

119,234

Rev. A

28

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

DATA ACQUISITION SYSTEM DIAGNOSTICS

the total conversion time for the ADSTAT command. When

ADSTAT is performed measuring all 4 internal parameters,

the LTC6810 will always perform four calibration cycles,

regardless of MCAL.

The battery monitoring data acquisition system is com-

prised of a multiplexer, an ADC, 1st reference, digital

filters, and memory. To ensure long term reliable perfor-

mance there are several diagnostic commands which can

be used to verify the proper operation of these circuits.

The timing for ADSTAT measuring a single status param-

eter is the same as ADCV measuring a single cell.

Sum of All Cells Measurement: The Sum of All Cells mea-

Measuring Internal Device Parameters (ADSTAT

Command)

+

–

surement is the voltage between V and V with a 10:1

+

–

attenuation. The V to V voltage is the same as the total

battery voltage when the IC is powered by the battery cells.

The 16-bit ADC value of Sum of All Cells measurement (SC)

is stored in Status Register Group A. From the SC value, the

sum of all cell voltage measurements is given by,

The ADSTAT command is a diagnostic command that

measures the following internal device parameters: Sum

of All Cells (SC), Internal Die Temperature (ITMP), Analog

Power Supply (VA) and Digital Power Supply (VD). These

parameters are described in the section below. All the 8

ADC modes described earlier are available for these con-

versions. See the section on Commands for the ADSTAT

command format.

Sum of All Cells = SC • 10 • 100µV

Internal Die Temperature: The ADSTAT command can

measure the internal die temperature. The 16 bit ADC

value of the die temperature measurement (ITMP) is

stored in Status Register Group A. From ITMP, the actual

die temperature is calculated using the expression,

Figure 10 illustrates the timing of the ADSTAT command

measuring all the 4 internal device parameters.

Table 9 shows the conversion time of the ADSTAT com-

mand measuring all the 4 internal parameters. t_Cindicates

100µV

Internal Die Temperature (°C) =

ITMP •

°C – 273°C

7.5mV

ꢈ

ꢇꢉꢇꢃꢁ

ꢈ

Rꢁꢆꢑꢏ

ꢀꢊꢁꢋ

ꢀꢁRꢂAꢃ

ꢂꢄꢅꢁRꢆAꢇꢁ

Aꢌꢇꢍ ꢎ ꢏꢁꢇ

ꢐꢁAꢀꢑRꢁ

ꢀꢇ

ꢐꢁAꢀꢑRꢁ

ꢂꢅꢐꢏ

ꢐꢁAꢀꢑRꢁ

ꢍA

ꢐꢁAꢀꢑRꢁ

ꢍꢌ

Aꢌꢇ

ꢇAꢃꢂꢒRAꢅꢁ

ꢈ

ꢕꢐ

ꢈ

ꢇ

ꢘꢙꢔꢓꢔ ꢆꢔꢓ

ꢓ

ꢔꢐ

ꢗꢐ

ꢖꢐ

Figure 10. Timing for ADSTAT command measuring SC, ITMP, VA, VD

Table 9. Conversion and Synchronization Times for ADSTAT Command Measuring SC, ITMP, VA, VD

SYNCHRONIZATION TIME

(in µs)

CONVERSION TIMES (in µs)

MODE

27kHz

14kHz

7kHz

t

SKEW

0

1M

2M

3M

4M

C,MCAL = 1 OR 0

0

57

87

104

162

151

238

197

314

741

858

0

140

227

402

751

145

279

413

547

1,556

2,021

2,952

4,814

8,538

134,210

3kHz

261

511

762

1,012

1,943

3,805

7,528

119,237

2kHz

494

977

1,460

2,856

5,649

89,431

1,449

2,845

5,638

89,420

1kHz

959

1,908

3,770

59,624

422Hz

26Hz

1,890

29,817

Rev. A

29

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Power Supply Measurements: The ADSTAT command is

using digital redundancy. See the A/D Conversion with

Digital Redundancy section.

also used to measure the Analog Power Supply (V

and Digital Power Supply (V

)

REG

).

REGD

The execution time of ADSTAT and ADSTATD is the same.

The 16 bit ADC value of the analog power supply measure-

ment (VA) is stored in Status Register Group A. The 16 bit

ADC value of the digital power supply measurement (VD)

is stored in Status Register Group B. From VA and VD, the

power supply measurements are given by:

+

–

Measuring Cell Voltages and V to V (ADCVSC

Command)

The ADCVSC command combines six cell measurements

and the measurement of Sum of All Cells. This command

simplifies the synchronization of the individual battery

cell voltage and the total Sum of All Cells measurement.

Figure 11 illustrates the timing of ADCVSC command.

See the section on Commands for the ADCVSC com-

mand format. The synchronization of the cell voltage and

Analog Power Supply Measurement (V_REG) = VA • 100µV

Digital Power Supply Measurement (V_REGD) =VD •100µV

The value of V

REG

is determined by external components.

V

should b^Re^Eb^Getween 4.5V and 5.5V to maintain accu-

racy. The value of V_REGDis determined by internal compo-

nents. The normal range of V is 2.7V to 3.6V.

Sum of All Cells measurements, t

, in fast mode is

SKEW

within 147µs.

REGD

Table 10 shows the conversion and synchronization time

for the ADCVSC command in different modes (with

SCONV = 0). The total conversion time for the command

Measuring Internal Device Parameters with Digital

Redundancy (ADSTATD Command)

The ADSTATD command operates similarly to the ADSTAT

command except that an additional diagnostic is performed

is given by t . When ADCVSC is performed, the LTC6810

C

will always perform seven calibration cycles, regardless

of MCAL.

ꢈ

ꢇꢉꢇꢃꢁ

ꢈ

Rꢁꢆꢒꢏ

ꢈ

ꢀꢊꢁꢋ

ꢀꢁRꢂAꢃ

ꢂꢄꢅꢁRꢆAꢇꢁ

Aꢌꢇꢍ ꢎ ꢏꢁꢇ

ꢑꢁAꢀꢒRꢁ

ꢇꢙ ꢅꢔ ꢇꢚ

ꢑꢁAꢀꢒRꢁ

ꢇꢘ ꢅꢔ ꢇꢙ

ꢑꢁAꢀꢒRꢁ

ꢇꢗ ꢅꢔ ꢇꢘ

ꢑꢁAꢀꢒRꢁ

ꢀꢇ

ꢑꢁAꢀꢒRꢁ

ꢇꢖ ꢅꢔ ꢇꢗ

ꢑꢁAꢀꢒRꢁ

ꢇꢕ ꢅꢔ ꢇꢖ

ꢑꢁAꢀꢒRꢁ

ꢇꢓ ꢅꢔ ꢇꢕ

Aꢌꢇ

ꢇAꢃꢂꢐRAꢅꢁ

ꢈ

ꢚ

ꢈ

ꢖꢑ

ꢈ

ꢛꢑ

ꢈ

ꢇ

ꢓꢜꢙꢚꢙ ꢆꢙꢙ

ꢙꢑ

ꢘꢑ

ꢗꢑ

ꢕꢑ

ꢓꢑ

Figure 11. Timing for ADCVSC Command, SCONV = 0

Table 10. Conversion and Synchronization Times for ADCVSC Command, SCONV = 0

SYNCHRONIZATION TIME

(in µs)

CONVERSION TIMES (in µs)

MODE

27kHz

14kHz

7kHz

t

SKEW

0

1M

2M

3M

4M

5M

6M

7M

C,MCAL = 1 OR 0

0

57

87

104

162

151

238

205

321

259

404

305

480

352

556

1,316

147

1,520

2,742

235

409

758

145

279

413

554

695

829

963

3kHz

261

511

762

1,019

1,950

3,812

7,536

1,277

2,440

4,768

9,422

1,527

2,923

5,716

11,302

1,777

3,407

6,665

13,181

3,556

2kHz

494

977

1,460

2,856

5,649

89,431

5,185

1,456

2,853

5,645

89,427

1kHz

959

1,908

3,770

59,624

8,443

422Hz

26Hz

1,890

29,817

14,960

234,887

119,245 149,059 178,865 208,672

Rev. A

30

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

A/D Conversion with Digital Redundancy

DIS_RED bit in the Configuration Register Group is writ-

ten to 1 it will disable the digital redundancy comparison

and subsequent ADC commands will store the normal

ADC result.

The internal ADC contains its own digital filter. The

LTC6810 also contains a second digital filter that is used

for redundancy and error checking.

All of the ADC and self test commands except ADAX and

ADSTAT can operate with digital redundancy. This includes

ADCV, ADOW, CVST, ADAXD, AXOW, AXST, ADSTATD,

STATST, ADCVAX and ADCVSC. DIS_RED and SCONV

must be set to 0 to enable digital redundancy during cell

measurements (see Redundant Cell Measurement Using

the S pins). When performing an ADC conversion with

redundancy, the analog modulator sends its bit stream

to both the primary digital filter and the redundant digital

filter. At the end of the conversion the results from the

two filters are compared. If any result bit mismatch is

detected then a digital redundancy fault code is stored

in place of the ADC result. The digital redundancy fault

code is a value of 0xFF0X. This is detectable because it

falls outside the normal result range of 0x0000 to 0xDFFF.

The last 4 bits are used to indicate which nibble(s) of the

result values did not match.

Redundant Cell Measurement Using the S pins

The LTC6810 has the ability to perform redundant mea-

surements of the cells by measuring across the S pins.

Redundant measurements using an independent pair of

pins can be used to detect if leakage is present at the

pins of the IC, in the external filter components or in the

internal MUX. The Block Diagram (LTC6810-1) shows that

both the C pins and the S pins can be connected to the

ADC. If a cell is measured twice using two different mea-

surement paths and the measurements agree, than the

two paths can be considered to be functioning correctly.

The host can enable this feature by writing the SCONV

bit in the Configuration Register Group to 1. Then any

subsequent ADC command that measures a cell voltage

will measure first using the C pins and then measure again

using the S pins. The results of the C pin measurements

are stored in the C voltage register groups. The results

from the S pin measurements are stored in S voltage

register groups (Redundant S Voltage Register Group A,

Redundant S Voltage Register Group B). It is up to the

host controller to compare the 2 measurements. The mea-

surements may differ by several LSBs due to the quanti-

zation noise of the ADC and different external filtering on

the C pins and S pins.

Indication of Digital Redundancy Fault Codes

DIGITAL REDUNDANCY FAULT

CODE 4 LSBs

Indication

0b0XXX

0b1XXX

0bX0XX

0bX1XX

0bXX0X

0bXX1X

0bXXX0

0bXXX1

0b0000

No fault detected in bits 15–12.

Fault detected in bits 15–12.

No fault detected in bits 11–8.

Fault detected in bits 11–8.

No fault detected in bits 7–4.

Fault detected in bits 7–4.

No fault detected in bits 3–0.

Fault detected in bits 3–0.

S pin measurements utilize the redundant digital filter to

provide additional redundancy and error checking. So the

digital redundancy feature is not available when perform-

ing cell measurements with S pins.

The digital redundancy feature will

not write this value of all zeros in

the last 4 bits.

Figure 12 shows the ADCV sequence measuring 6 cells

with redundant measurements enabled.

Table 11 shows the conversion times for the ADCV com-

mand measuring all six cells with redundant measure-

When the FDRF bit in the Configuration Register Group is

written to 1 it will force the digital redundancy compari-

son to fail during subsequent A/D conversions. When the

ments enabled. The total conversion time is given by t

which indicates the end of the calibration step.

C

Rev. A

31

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

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Figure 12. Timing for ADCV Command Measuring All 6 Cells, SCONV = 1

Table 11. Conversion Times for ADCV Command Measuring All Six Cells, SCONV = 1

CONVERSION TIMES (in µs)

MODE

27kHz

14kHz

7kHz

t

t t

C,MCAL = 0 C,MCAL = 1

0

1M

2M

3M

4M

5M

6M

7M

8M

9M

10M

11M

12M

0

57

104

163

279

511

977

151

238

413

762

197

314

244

390

291

466

337

541

384

431

477

769

524

844

571

920

913

2,194

2,543

87

617

693

1,263

2,077

3,473

6,266

11,852

23,023

145

261

494

959

547

680

814

948

1,082

2,013

3,875

7,599

1,216

2,263

4,358

8,547

1,350

2,514

4,841

1,484

2,764

5,324

1,618

3,014

5,807

4,637

3kHz

1,012

1,262

2,426

4,753

1,513

2,909

5,702

1,763

3,392

6,650

6,033

2kHz

1,460 1,943

8,827

1kHz

1,908 2,856 3,805

9,496 10,444 11,393

14,412

25,583

402,601

422Hz

26Hz

1,890 3,770 5,649 7,528

9,408 11,287 13,167 15,046 16,925 18,805 20,684 22,563

29,818 59,624 89,431 119,238 149,044 178,851 208,658 238,464 268,271 298,078 327,884 357,691 361,641

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Figure 13 illustrates the timing of the ADCV command that

measures one cell with redundant measurement.

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Table 12 shows the conversion time for ADCV command

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measuring only 1 cell. t indicates the total conversion

C

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time for this command.

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Figure 14 illustrates the timing of the ADCVAX command

with SCONV set to 1.

Figure 13. Timing for ADCV Command Measuring

One Cell, SCONV = 1

Table 13 shows the conversion and synchronization time

for the ADCVAX command in different modes with SCONV

set to 1. The total conversion time for the command is

Table 12. Conversion Times for ADCV Command Measuring Only

One Cell, SCONV = 1

CONVERSION TIMES (in µs)

given by t .

C

MODE

27kHz

14kHz

7kHz

t

t t

C,MCAL = 0 C,MCAL = 1

0

1M

2M

Figure 15 illustrates the timing of the ADCVSC command

with SCONV set to 1.

0

57

87

104

162

265

323

381

440

Table 14 shows the conversion and synchronization time

for the ADCVSC command in different modes with SCONV

set to 1. The total conversion time for the command is

145

279

556

789

3kHz

261

512

789

1,021

1,487

2,418

4,280

67,116

2kHz

494

977

1,254

2,185

4,047

63,392

given by t .

C

1kHz

959

1,908

3,770

59,624

422Hz

26Hz

1,890

29,817

Rev. A

32

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Rev. A

33

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Rev. A

34

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LTC6810-1/LTC6810-2

OPERATION

Accuracy Check

Digital Filter Check

Measuring an independent voltage reference is the best

means to verify the accuracy of a data acquisition system.

The LTC6810 contains a 2nd reference for this purpose.

The ADAX command will initiate the measurement of the

2nd reference. The results are placed in Auxiliary Register

Group B. The range of the result depends on the accuracy

of the 2nd reference, including thermal hysteresis and

long term drift. Readings outside the range 2.99V to 3.01V

(final data sheet limits plus 2mV for Hys and 3mV for LTD)

indicate the system is out of its specified tolerance.

The delta-sigma ADC is composed of a 1-bit pulse den-

sity modulator followed by a digital filter. A pulse density

modulated bit stream has a higher percentage of 1s for

higher analog input voltages. The digital filter converts

this high frequency 1-bit stream into a single 16-bit word.

This is why a delta-sigma ADC is often referred to as an

over-sampling converter.

The self test commands verify the operation of the digital

filters and memory. Figure 16 illustrates the operation

of the ADC during self test. The output of the 1-bit pulse

density modulator is replaced by a 1-bit test signal. The

test signal passes through the digital filter and is con-

verted to a 16-bit value. The 1-bit test signal undergoes

the same digital conversion as the regular 1-bit pulse

from the modulator, so the conversion time for any self

test command is exactly the same as the corresponding

regular ADC conversion command. The 16-bit ADC value

is stored in the same register groups as the regular ADC

conversion command. The total conversion time for the

self test commands is the same as the regular ADC con-

version commands. The test signals are designed to place

alternating one-zero patterns in the registers.

MUX Decoder Check

The diagnostic command DIAGN ensures the proper oper-

ation of each multiplexer channel. The command cycles

through all channels and sets the MUXFAIL bit to 1 in

Status Register Group B if any channel decoder fails. The

MUXFAIL bit is set to 0 if the channel decoder passes the

test. The MUXFAIL bit is also set to 1 on power-up (POR)

or after a CLRSTAT command.

The DIAGN command takes about 300µs to complete if

the Core is in REFUP state and about 3.8ms to complete

if the Core is in STANDBY state. The polling methods

described in the section Polling Methods can be used to

determine the completion of the DIAGN command.

Table 15 provides a list of the self test commands. If the

digital filters and memory are working properly, then the

registers will contain the values shown in Table 15. For

more details see the Commands section.

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Figure 16. Operation of LT6810 ADC Self Test

Rev. A

35

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Table 15. Self Test Command Summary

OUTPUT PATTERN IN DIFFERENT ADC MODES

7kHz, 3kHz, 2kHz,

RESULTS REGISTER

GROUPS

COMMAND

SELF TEST OPTION

ST[1:0] = 01

ST[1:0] = 10

ST[1:0] = 01

ST[1:0] = 10

ST[1:0] = 01

ST[1:0] = 10

27kHz

0x9565

0x6A9A

0x9565

0x6A9A

0x9565

0x6A9A

14kHz

0x9553

0x6AAC

0x9553

0x6AAC

0x9553

0x6AAC

1kHz, 422Hz, 26Hz

CVST

0x9555

C1V to C18V

(CVA, CVB, CVC, CVD)

0x6AAA

AXST

0x9555

S0, G1V to G4V, REF

(AUXA, AUXB)

0x6AAA

STATST

0x9555

SC, ITMP, VA, VD

(STATA, STATB)

0x6AAA

ADC Clear Commands

The following simple algorithm can be used to check for

an open wire on any of the 7 C pins:

LTC6810 has 3 clear ADC commands: CLRCELL, CLRAUX

and CLRSTAT. These commands clear the registers that

store all ADC conversion results.

1. Run the 6-cell command ADOW with PUP = 1 at least

twice. Read the cell voltages for cells 1 through 6

once at the end and store them in array CELLPU(n).

The CLRCELL command clears Cell Voltage Register

Group A, B, C and D. All bytes in these registers are set

to 0xFF by CLRCELL command.

2. Run the 6-cell command ADOW with PUP = 0 at least

twice. Read the cell voltages for cells 1 through 6

once at the end and store them in array CELLPD(n).

The CLRAUX command clears Auxiliary Register Group

A and B. All bytes in these registers are set to 0xFF by

CLRAUX command.

3. Take the difference between the pull-up and pull-down

measurements made in above steps for cells 2 to 6:

CELL∆(n) = CELLPU(n) – CELLPD(n).

The CLRSTAT command clears Status Register Group

A and B except the REVCODE and RSVD bits in Status

Register Group B. A read back of REVCODE will return the

revision code of the part. RSVD bits always read back 0s.

All OV and UV flags, MUXFAIL bit, and THSD bit in Status

Register Group B are set to 1 by CLRSTAT command.

The THSD bit is set to 0 after RDSTATB command. The

registers storing SC, ITMP, VA and VD are all set to 0xFF

by CLRSTAT command.

4. For all values of n from 1 to 5: If CELL∆(n+1) <

–400mV, then C(n) is open. If CELLPU(1) = 0.0000,

then C(0) is open. If CELLPD(6) = 0.0000, then C(6)

is open.

The above algorithm detects open wires using normal

mode conversions with as much as 10nF of capacitance

on the LTC6810 side of the open wire. However, if more

external capacitance is on the open C pin, then the length

of time that the open wire conversions are run in steps 1

and 2 must be increased to give the 100µA current sources

time to create a large enough difference for the algorithm

to detect an open connection. This can be accomplished

by running more than two ADOW commands in steps 1

and 2, or by using filtered mode conversions instead of

normal mode conversions. Use Table 16 to determine how

many conversions are necessary.

Open Wire Check (ADOW Command)

The ADOW command is used to check for any open wires

between the ADCs of the LTC6810 and the external cells.

This command performs ADC conversions on the C pin

inputs identically to the ADCV command, except two inter-

nal current sources sink or source current into the two C

pins while they are being measured. The pull-up (PUP) bit

of the ADOW command determines whether the current

sources are sinking or sourcing 100µA.

Rev. A

36

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Table 16.

Revision Code and Reserved Bits

NUMBER OF ADOW COMMANDS REQUIRED IN

STEPS 1 AND 2

The Status Register Group B contains a 4-bit revision

code. If software detection of device revision is neces-

sary, then contact the factory for details. Otherwise the

code can be ignored. In all cases, however, the values of

all bits must be used when calculating the Packet Error

Code (PEC) on data reads.

EXTERNAL C PIN

CAPACITANCE

NORMAL MODE

FILTERED MODE

≤10nF

100nF

1µF

2

10

100

C

1 + ROUNDUP(C/10nF)

WATCHDOG AND DISCHARGE TIMER

Thermal Shutdown

When there is no valid command for more than 2 seconds,

the watchdog timer expires. This resets Configuration

Register bytes CFGR0, CFGR1-3 (if DTMEN=0). CFGR4,

CFGR5, and the PWM configuration bits in the PWM

Register Group are reset by the watchdog timer when the

Discharge Timer is disabled. The WDT pin is pulled high

by the external pull-up when the watchdog time elapses.

The watchdog timer is always enabled and it resets after

every valid command with matching command PEC.

To protect the LTC6810 from over-heating, there is a ther-

mal shutdown circuit included inside the IC. If the tem-

perature detected on the die goes above approximately

150°C, the thermal shutdown circuit trips and resets the

Configuration Register Group and PWM Register Group

to their default state. This turns off all discharge switches.

When a thermal shutdown event has occurred, the THSD

bit in Status Register Group B will go high. The CLRSTAT

command can also set the THSD bit high for diagnostic

purposes. This bit is cleared when a read operation is

performed on the Status Register Group B (RDSTATB

command).

The discharge timer is used to enable cell discharge using

pulse width modulation, for programmable time duration

after the watchdog time elapses. To enable the Discharge

Timer, tie the DTEN pin high to V

(Figure 17) and

REGA

write the DCTO value in the Configuration Register Group

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Figure 17. Watchdog and Discharge Timer

Rev. A

37

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Table 17. DCTO Settings

DCTO

0

1

0.5

2

1

3

2

4

3

5

4

6

5

7

8

9

A

B

C

D

E

F

Time (min)

Disabled

10 15 20 30 40 60 75 90 120

to a non-zero value. Once the watchdog time elapses,

the discharge switches are now allowed to discharge at

a duty cycle specified by the PWM configuration bits in

the PWM Register Group for a time duration that is deter-

mined by the DCTO value. Table 17 shows the various

time settings and the corresponding DCTO value. Table

18 summarizes the status of the Configuration Register

Group after a watchdog timer or discharge timer event.

Table 18

WATCHDOG TIMER

DISCHARGE TIMER

DTEN = 0,

DCTO = XXXX bits when it fires.

Resets CFGR0-5 and PWM Disabled

DTEN = 1,

DCTO = 0000 bits when it fires.

Resets CFGR0-5 and PWM Disabled

DTEN = 1,

Resets CFGR0, CFGR1-3 (if Resets CFGR1-3 (if DTMEN

DCTO != 0000 DTMEN=0) when it fires.

=1), and PWM bits when

it fires.

The status of the discharge timer can be determined by

reading the configuration register using the RDCFG com-

mand. The DCTO value indicates the time left before the

Discharge Timer expires as shown in Table 19.

Table 19.

DCTO (READ VALUE)

TIME LEFT (MIN)

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Disabled (or) Discharge Timer Has Timed Out

0 < Timer ≤ 0.5

Unlike the watchdog timer, the discharge timer does not

reset when there is a valid command. The discharge timer

is only reset after a valid WRCFG (Write Configuration

Register Group) command. There is a possibility that

the Discharge Timer will expire in the middle of some

commands.

0.5 < Timer ≤ 1

1 < Timer ≤ 2

2 < Timer ≤ 3

3 < Timer ≤ 4

4 < Timer ≤ 5

5 < Timer ≤ 10

10 < Timer ≤ 15

15 < Timer ≤ 20

20 < Timer ≤ 30

30 < Timer ≤ 40

40 < Timer ≤ 60

60 < Timer ≤ 75

75 < Timer ≤ 90

90 < Timer ≤ 120

If Discharge Timer expires in the middle of WRCFG

command, the Configuration Register Group and PWM

Register Group reset as per Table 18. However, at the end

of the valid WRCFG command, the new data is copied to

the configuration register. The new data is not lost when

the Discharge Timer fired.

If Discharge Timer fires in the middle of RDCFG com-

mand, the Configuration Register Group resets as per

Table 18. As a result, the read back data from bytes CRFG4

and CRFG5 could be corrupted. If Discharge Timer fires in

the middle of WRPWM or RDPWM command, the PWM

Register Group resets as per Table 18. As a result, the

data could be corrupted.

Rev. A

38

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LTC6810-1/LTC6810-2

OPERATION

RESET BEHAVIORS

Power cycling, thermal shutdown, watchdog timeout

and discharge timeout can cause various registers and

circuitry to reset when they occur. The following sum-

marizes the behaviors when these events occur:

RESET EVENT

DEVICE BEHAVIOR

Power Cycle

Transition to STANDBY state.

All registers and state machines are reset to default values.

Cell discharge is disabled.

+

(V and V

both

REG

power cycled)

Thermal Shutdown

Cell discharge is disabled.

All of Configuration Register Group is reset.

The COMM Register Group is reset.

Watchdog Timeout

Transition to EXTENDED BALANCING state.

(while Discharge Timer CFGR0 of Configuration Register is reset.

is Running)

If DTMEN (in Configuration Register Group) = 0

then CFGR1, CFGR2 and CFGR3 of Configuration Register Group are reset.

The COMM Register Group is reset.

Watchdog Timeout

(no Discharge Timer

Running)

Transition to SLEEP state.

Cell discharge is disabled.

All state machines are reset.

All of Configuration Register Group is reset.

The PWM Register Group is reset.

The COMM Register Group is reset.

Discharge Timeout

(while Watchdog

Timeout has Elapsed)

Transition to SLEEP state.

Same behavior as the previous case above.

Discharge Timeout

(while Watchdog

Cell discharge is disabled.

The PWM Register Group is reset.

Timeout is not Elapsed) If DTMEN (in Configuration Register) = 1

then CFGAR1, CFGAR2 and CFGAR3 of Configuration Register Group are reset.

CFGAR4 and CFGAR5 of Configuration Register Group are reset.

Rev. A

39

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

S PIN PULSE WIDTH MODULATION FOR CELL

BALANCING

at the same time. The switching interval between chan-

nels is 62.5ms, and 375ms are required for all 6 pins to

switch (6 • 62.5ms).

While the watchdog timer is not expired, the DCC bits

in the Configuration Register Group control the S pins

directly. After the watchdog timer expires, PWM operation

begins and continues for the remainder of the selected

software discharge time or until a wake-up event occurs

(and the watchdog timer is reset).

The default value of the PWMC settings in the PWM

Register Group is all 0s. Upon entry to sleep mode, the

PWMC settings will be reset to their default value.

DISCHARGE TIMER MONITOR

Once PWM operation begins, the configurations in the

PWM Register Group control the S pins to achieve the

desired duty cycle as shown in Table 20. Each PWM signal

operates on a 30 second period. For each cell, the duty-

cycle can be programmed from 0% to 50% duty cycle in

increments of 1/30 = 3.33% (1 second). S pins for adja-

cent cells are never activated at the same time, hence the

maximum 50% duty cycle. There is a non-overlap of at

least 1ms between activation of any two adjacent S pins.

The LTC6810 has the ability to periodically monitor cell

voltages while the discharge timer is active. The host

should write the DTMEN bit in the Configuration Register

Group to 1 to enable this feature.

When the discharge timer monitor is enabled and the

watchdog timer has expired, the LTC6810 will perform

a conversion of all cell voltages in 7kHz (Normal) Mode

every 30 seconds. The overvoltage and undervoltage

comparisons will be performed and flags will be set if

cells have crossed a threshold. For any undervoltage cells

the discharge timer monitor will automatically clear the

associated PWMC bits in the PWM Register Group so

that the cell will no longer be discharged. Clearing the

Discharge Control bit will also disable PWM discharge.

With this feature, the host can write the undervoltage

threshold to the desired discharge level and use the dis-

charge timer monitor to discharge all, or selected, cells

down to that level.

Table 20. PWM Configurations

DTEN

SETTING

PWMC

ON TIME

OFF TIME

[SECONDS]

DUTY CYCLE

[%]

SETTING [SECONDS]

1’b0

1’b1

4’bXXXX

4’b1111

4’b1110

4’b1101

4’b1100

4’b1011

4’b1010

4’b1001

4’b1000

4’b0111

4’b0110

4’b0101

4’b0100

4’b0011

4’b0010

4’b0001

4’b0000

0

15

14

13

12

11

10

9

Continuously Off

0

15

50

16

46.7

43.3

40

17

18

19

36.7

33.3

30

20

During discharge timer monitoring, digital redundancy

checking will be performed on the cell voltage measure-

ments. If a digital redundancy failure occurs, all PWMC

bits will be cleared and discharge will be terminated.

21

8

22

26.7

23.3

20

7

23

6

24

5

25

16.7

13.3

10

2

I C/SPI MASTER ON LTC6810 USING GPIOS

4

26

3

27

The I/O ports GPIO2, GPIO3 and GPIO4 on LTC6810 can

2

28

29

6.7

3.3

0

be used as an I C or SPI master port to communicate

2

1

to an I C or SPI slave. In case of I C master, GPIO3 and

2

0

Continuously Off

GPIO4 form the SDA and SCL ports of the I C interface

respectively. In case of SPI master, GPIO2, GPIO3 and

GPIO4 become the CSB, SDIO and SCK ports of the SPI

interface respectively. The SPI master on LTC6810 sup-

ports SPI mode 3 (CHPA = 1, CPOL = 1).

The PWM turn on/off times for the S pins are sequenced

at different intervals so that no two pins switch on or off

Rev. A

40

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

The GPIOs are open drain outputs, so an external pull

If the bit ICOMn[3] in the COMM register is set to 1 the

part becomes an SPI master and if the bit is set to 0 the

2

up is required on these ports to operate as an I C or SPI

2

master. It is also important to write the GPIO bits to 1 in

the CFG register group so these ports are not pulled low

internally by the device.

part becomes a I C master.

Table 22 describes the valid write codes for ICOMn[3:0]

and FCOMn[3:0] and their behavior when using the part

2

as an I C master.

COMM Register

Table 23 describes the valid codes for ICOMn[3:0] and

FCOMn[3:0] and their behavior when using the part as

an SPI master.

LTC6810 has a 6 byte COMM register as shown in Table

21. This register stores all data and control bits required

2

for I C or SPI communication to a slave. The COMM reg-

ister contains 3 bytes of data Dn[7:0] to be transmitted

to or received from the slave device. ICOMn[3:0] specify

control actions before transmitting/receiving the data

byte. FCOMn[3:0] specify control actions after transmit-

ting/receiving the data byte.

Note that only the codes listed in Table 22 and Table 23

are valid for ICOMn[3:0] and FCOMn[3:0]. Writing any

other code that is not listed above to ICOMn[3:0] and

FCOMn[3:0] may result in unexpected behavior on the

2

I C and SPI ports.

Table 21. COMM Register Memory Map

REGISTER

COMM0

COMM1

COMM2

COMM3

COMM4

COMM5

RD/WR

BIT 7

ICOM0[3]

D0[3]

BIT 6

ICOM0[2]

D0[2]

BIT 5

ICOM0[1]

D0[1]

BIT 4

ICOM0[0]

D0[0]

BIT 3

D0[7]

BIT 2

D0[6]

BIT 1

D0[5]

BIT 0

D0[4]

RD/WR

FCOM0[3]

D1[7]

FCOM0[2]

D1[6]

FCOM0[1]

D1[5]

FCOM0[0]

D1[4]

ICOM1[3]

D1[3]

ICOM1[2]

D1[2]

ICOM1[1]

D1[1]

ICOM1[0]

D1[0]

FCOM1[3]

D2[7]

FCOM1[2]

D2[6]

FCOM1[1]

D2[5]

FCOM1[0]

D2[4]

ICOM2[3]

D2[3]

ICOM2[2]

D2[2]

ICOM2[1]

D2[1]

ICOM2[0]

D2[0]

FCOM2[3]

FCOM2[2]

FCOM2[1]

FCOM2[0]

Table 22. Write Codes for ICOMn[3:0] and FCOMn[3:0] on I²C Master

CONTROL BITS

CODE ACTION

DESCRIPTION

2

ICOMn[3:0]

0110

0001

0000

0111

0000

1000

1001

START

Generate a START signal on I C port followed by data transmission.

2

STOP

Generate a STOP signal on I C port.

2

BLANK

Proceed directly to data transmission on I C port.

No Transmit

Master ACK

Master NACK

Master NACK + STOP

Release SDA and SCL and ignore the rest of the data.

Master generates an ACK signal on ninth clock cycle.

Master generates a NACK signal on ninth clock cycle.

Master generates a NACK signal followed by STOP signal.

FCOMn[3:0]

Table 23. Write Codes for ICOMn[3:0] and FCOMn[3:0] on SPI Master

CONTROL BITS

CODE ACTION

DESCRIPTION

ICOMn[3:0]

1000

1010

1001

1111

CSBM low

Generates a CSBM low signal on SPI port (GPIO3).

Drives CSBM (GPIO3) high, then low.

CSBM falling edge

CSBM high

Generates a CSBM high signal on SPI port (GPIO3).

Releases the SPI port and ignores the rest of the data.

Holds CSBM low at the end of byte transmission.

Transitions CSBM high at the end of byte transmission.

No Transmit

FCOMn[3:0]

X000 CSBM low

1001 CSBM high

Rev. A

41

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

COMM Commands

Table 24. Read Codes for ICOMn[3:0] and FCOMn[3:0] on I²C Master

2

CONTROL BITS

CODE DESCRIPTION

Three commands help accomplish I C or SPI communica-

ICOMn[3:0]

0110 Master generated a START signal.

0001 Master generated a STOP signal.

0000 Blank, SDA was held low between bytes.

0111 Blank, SDA was held high between bytes.

0000 Master generated an ACK signal.

0111 Slave generated an ACK signal.

1111 Slave generated a NACK signal.

tion to the slave device: WRCOMM, STCOMM, RDCOMM

WRCOMM Command: This command is used to write

data to the COMM register. This command writes 6 bytes

of data to the COMM register. The PEC needs to be written

at the end of the data. If the PEC does not match, all data

in the COMM register is cleared to 1s when CSB goes

high. See the Bus Protocols section for more details on a

write command format.

FCOMn[3:0]

0001 Slave generated an ACK signal, master

generated a STOP signal.

STCOMM Command: This command initiates I²C/SPI

communication on the GPIO ports. The COMM register

contains 3 bytes of data to be transmitted to the slave.

During this command, the data bytes stored in the COMM

register are transmitted to the slave I²C or SPI device and

1001 Slave generated a NACK signal, master

generated a STOP signal.

2

Figure 18 illustrates the operation of LTC6810 as an I C

or SPI master using the GPIOs.

2

the data received from the I C or SPI device is stored in

the COMM register. This command uses GPIO3 (SDA)

and GPIO4 (SCL) for I²C communication or GPIO2

(CSBM), GPIO3 (SDIOM) and GPIO4 (SCKM) for SPI

communication.

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The STCOMM command is to be followed by 24 clock

cycles for each byte of data to be transmitted to the slave

device while holding CSB low. For example, to transmit 3

bytes of data to the slave, send STCOMM command and

its PEC followed by 72 clock cycles. Pull CSB high at the

end of the 72 clock cycles of STCOMM command.

ꢀꢁꢂꢃꢂ ꢄꢂꢁ

Figure 18. LTC6810 I²C/SPI Master using GPIOs

Any number of bytes can be transmitted to the slave in

groups of 3 bytes using these commands. The GPIO

ports will not get reset between different STCOMM com-

mands. However, if the wait time between the commands

is greater than 2s, the watchdog will time out and reset

the ports to their default values.

2

During I C or SPI communication, the data received from

the slave device is updated in the COMM register.

RDCOMM Command: The data received from the slave

device can be read back from the COMM register using the

RDCOMM command. The command reads back 6 bytes of

data followed by the PEC. See the Bus Protocols section

for more details on a read command format.

2

To transmit several bytes of data using an I C master,

a START signal is only required at the beginning of the

entire data stream. A STOP signal is only required at the

end of the data stream. All intermediate data groups can

use a BLANK code before the data byte and an ACK/NACK

signal as appropriate after the data byte. SDA and SCL

will not get reset between different STCOMM commands.

Table 24 describes the possible read back codes for

ICOMn[3:0] and FCOMn[3:0] when using the part as an

2

I C master. Dn[3:0] contains the data byte transmitted by

2

the I C slave.

To transmit several bytes of data using SPI master, a

CSBM low signal is sent at the beginning of the 1st data

byte. CSBM can be held low or taken high for intermediate

data groups using the appropriate code on FCOMn[3:0].

In case of the SPI master, the read back codes for

ICOMn[3:0] and FCOMn[3:0] are always 0111 and 1111

respectively. Dn[3:0] contains the data byte transmitted

by the SPI slave.

Rev. A

42

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

A CSB high signal is sent at the end of the last byte of

data. CSBM, SDIOM and SCKM will not get reset between

different STCOMM commands.

Figure 19 shows the 24 clock cycles following STCOMM

2

command for an I C master in different cases. Note that

if ICOMn[3:0] specified a STOP condition, after the STOP

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Figure 19. STCOMM Timing Diagram for an I²C Master

t

4

t

3

CLK

(SCK)

CSBM HIGH ≥ LOW

CSBM LOW

CSBM (GPIO2)

SCKM (GPIO4)

SDIOM (GPIO3)

CSBM LOW

CSBM LOW ≥ HIGH

CSBM (GPIO2)

SCKM (GPIO4)

SDIOM (GPIO3)

CSBM HIGH/NO TRANSMIT

CSBM (GPIO2)

SCKM (GPIO4)

SDIOM (GPIO3)

68111 F14

Figure 20. STCOMM Timing Diagram for a SPI Master

Rev. A

43

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

signal is sent, the SDA and SCL lines are held high and

all data in the rest of the word is ignored. If ICOMn[3:0]

is a NO TRANSMIT, both SDA and SCL lines are released,

and rest of the data in the word is ignored. This is used

when a particular device in the stack does not have to

communicate to a slave.

Table 26. SPI Master Timing

SPI MASTER PARAMETER

TIMING RELATIONSHIP

TO PRIMARY SPI

INTERFACE

TIMING

SPECIFICATIONS

AT t

= 1μs

CLK

SDIOM Valid to SCKM Rising

Setup

t

3

Min 200ns

SDIO Valid from SCKM Rising

Hold

t

+ t *

CLK 4

Min 1.03μs

Figure 20 shows the 24 clock cycles following STCOMM

2

SCKM Low

SCKM High

t

Min 1μs

Min 2μs

CLK

command for a SPI master. Similar to the I C master, if

ICOMn[3:0] specified a CSBM HIGH or a NO TRANSMIT

condition, the CSBM, SCKM and SDIOM lines of the SPI

master are released and the rest of the data in the word

is ignored.

SCKM Period (SCKM_Low +

SCKM_High)

2 • t

CLK

CSBM Pulse Width

3 • t

Min 3μs

Min 5.03μs

Min 200ns

Min 1.2μs

CLK

SCKM Rising to CSBM Rising

CSBM Falling to SCKM Falling

CSBM Falling to SCKM Rising

5 • t

+ t *

CLK 4

2

t

3

Timing Specifications of I C and SPI master

t

+ t

3

CLK

The timing of the LTC6810 I²C or SPI master will be

controlled by the timing of the communication at the

LTC6810’s primary SPI interface. Table 25 shows the

SCKM Falling to SDIOM Valid Master requires < t

CLK

*Note: When using isoSPI, t is generated internally and is a minimum of

4

30ns. Also, t = t

– t . When using SPI, t and t are the low and high

4 3 4

3

CLK

2

I C master timing relationship to the primary SPI clock.

times of the SCK input, each with a specified minimum of 200ns.

Table 26 shows the SPI master timing specifications.

Table 25. I²C MASTER TIMING

S PIN MUTING

TIMING RELATIONSHIP

TO PRIMARY SPI

INTERFACE

TIMING

2

I C MASTER

SPECIFICATIONS AT

The S pins may be disabled by sending the MUTE com-

mand and re-enabled by sending the UNMUTE command.

The MUTE and UNMUTE commands do not require any

subsequent data and thus the commands will propagate

quickly through a stack of LTC6810-1 devices. Likewise,

they can be sent as broadcast commands to a network of

LTC6810-2 devices. This allows the host to quickly dis-

able and re-enable discharging without disturbing register

contents. This can be useful, for instance, to allow specific

settling time before taking cell measurements. The mute

status is reported in the read-only MUTE bit in Status

Register Group B.

PARAMETER

t

= 1μs

CLK

SCL Clock Frequency

1/(2 • t

)

Max 500kHz

Min 200ns

Min 1μs

CLK

t ;STA

HD

t

3

t

LOW

HIGH

CLK

t

Min 1μs

t

;STA

;DAT

;STO

t

+ t *

Min 1.03μs

Min 30ns

Min 200ns

Min 1.03μs

Min 3μs

SU

HD

CLK

4

t

t *

4

t

3

SU

t

+ t *

4

CLK

t

3 • t

CLK

BUF

*Note: When using isoSPI, t is generated internally and is a minimum of

4

30ns. Also, t = t

– t . When using SPI, t and t are the low and high

3

CLK

4 3 4

times of the SCK input, each with a specified minimum of 200ns.

Rev. A

44

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

SERIAL ID AND AUTHENTICATION

There are two versions of the IC: the LTC6810-1 and the

LTC6810-2. The LTC6810-1 is used in a daisy chain con-

figuration and the LTC6810-2 is used in an addressable

bus configuration. The LTC6810-1 provides a second iso-

SPI interface using pins 34, 35, 38, and 39. LTC6810-2

Each LTC6810 is programmed at the factory with a unique

48-bit serial identification code (SID) which is stored in

the Serial ID Register Group. The host can read the unique

SID code for each device using the RDSID command.

uses pins 34, 35, 38 and 39 to set the address of the

–

The LTC6810 also contains a feature that can be used to

authenticate devices. Contact the factory for details about

the authentication feature.

device, by tying these pins to V or V

.

REG

4-WIRE SERIAL PERIPHERAL INTERFACE (SPI)

PHYSICAL LAYER

SERIAL INTERFACE OVERVIEW

External Connections

There are two types of serial ports on the LTC6810: a stan-

dard 4-wire serial peripheral interface (SPI) and a 2-wire

isolated interface (isoSPI). The state of the ISOMD pin

determines whether pins 36, 37, 40 and 41 are a 2-wire

or 4-wire serial port.

Connecting ISOMD to V^–configures serial port A for

4-wire SPI. The SDO pin is an open drain output which

requires a pull-up resistor tied to the appropriate supply

voltage (Figure 21).

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Figure 21. 4-Wire SPI Configuration

Rev. A

45

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Timing

2-Wire Isolated Interface (isoSPI) Physical Layer

The 4-wire serial port is configured to operate in a SPI

system using CPHA = 1 and CPOL = 1. Consequently, data

on SDI must be stable during the rising edge of SCK. The

timing is depicted in Figure 22. The maximum data rate

is 1Mbps.

The 2-wire interface provides a means to interconnect

LTC6810 devices using simple twisted pair cabling. The

interface is designed for low packet error rates when the

cabling is subjected to high RF fields. Isolation is achieved

through an external transformer.

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ꢅꢂ

ꢅꢋ

ꢅꢌꢍꢅꢎ

ꢅꢉ

ꢗ

ꢘ

ꢇꢄꢙ

ꢄꢅꢓ

ꢗ

ꢁ

ꢅꢎ

ꢅꢉ

ꢅꢊ

ꢅꢂ

ꢅꢋ

ꢅꢌꢍꢅꢎ

ꢅꢉ

ꢀꢁꢂꢂꢂ ꢃꢂꢀ

ꢕRꢐꢖꢆꢓꢏꢄ ꢇꢓꢔꢔAꢑꢅ

ꢇꢏRRꢐꢑꢒ ꢇꢓꢔꢔAꢑꢅ

Figure 22. Timing Diagram of 4-Wire Serial Peripheral Interface

ꢎꢕꢊꢀꢁꢂꢃ

ꢞAꢝꢓꢛꢋ

ꢊꢆRꢊꢛꢆꢕ

ꢕꢖ ꢙ ꢌꢃ ꢙ ꢆ

ꢆꢋ

ꢈ

ꢕꢖ ꢗ ꢘꢂ

ꢕꢖ ꢗ ꢃ

ꢙ

ꢉꢒꢏ

ꢉꢒꢆ

R

ꢎꢏꢐꢆꢊ

Aꢑꢒ

ꢇꢓꢇꢏRꢔ

ꢇ

ꢆꢇ

ꢙ

ꢕꢖ ꢗ ꢚꢂ

ꢋꢛꢎꢉꢓ

ꢓꢑꢊꢏꢒꢓRꢜ

ꢒꢓꢊꢏꢒꢓR

ꢉꢊꢝ

ꢊꢉꢈ

Rꢖ ꢗ ꢘꢂ

Rꢖ ꢗ ꢃ

ꢘ

ꢚ

ꢆ

ꢆꢈꢆAꢉ

ꢆꢊꢇꢋ

Rꢖ ꢗ ꢚꢂ

ꢈ

ꢘ

ꢌꢍ

ꢚ

R

ꢈꢂ

ꢈꢌ

ꢂꢍ ꢙ R

ꢈꢌ

ꢊꢏꢇꢋARAꢕꢏR ꢕꢟRꢓꢉꢟꢏꢎꢒ ꢗ

R

ꢈꢂ

ꢘ R

ꢈꢌ

ꢃ.ꢠꢡ

ꢀꢁꢂꢃꢂ ꢄꢂꢅ

Figure 23. isoSPI Interface

Rev. A

46

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

ꢄꢇꢈ

ꢄꢆꢈ

ꢄꢇA

Standard SPI signals are encoded into differential pulses.

The strength of the transmission pulse and the threshold

level of the receiver are set by 2 external resistors. The

values of the resistors allow the user to trade off power

dissipation for noise immunity.

ꢄꢆA

ꢃ

ꢀ

ꢍꢎꢅꢏꢐꢑꢒꢓꢑ

ꢋAꢄꢉꢔꢓꢅꢕAꢄꢌ

ꢆꢊꢋꢁ

ꢃ

ꢂꢌꢋꢋ

ꢂꢌꢋꢅ

ꢂꢌꢋꢈ

ꢄꢅꢆꢇ

ꢄꢈꢄAꢉ

ꢄꢉꢊꢆꢋ

ꢌꢅ

Figure 23 illustrates how the isoSPI circuit operates. A 2V

reference drives the IBIAS pin. External resistors RB1 and

RB2 create the reference current IB. This current sets the

drive strength of the transmitter. RB1 and RB2 also form

a voltage divider to supply a fraction of the 2V reference

for the ICMP pin, which sets the threshold voltage of the

receiver circuit.

ꢌꢅ

ꢋꢁꢀ ꢋ

ꢀ

Rꢁꢂ

ꢄꢇꢈ

ꢄꢆꢈ

ꢄꢇA

ꢄꢆA

External Connections

ꢃ

ꢀ

ꢂꢌꢋꢅ

ꢍꢎꢅꢏꢐꢑꢒꢓꢑ

ꢋAꢄꢉꢔꢓꢅꢕAꢄꢌ

ꢆꢊꢋꢁ

ꢃ

The LTC6810-1 has 2 serial ports which are called Port

B and Port A. Port B is always configured as a 2-wire

interface. Port A is either a 2-wire or 4-wire interface,

depending on the connection of the ISOMD pin.

ꢂꢌꢋꢅ

ꢄꢅꢆꢇ

ꢄꢈꢄAꢉ

ꢄꢉꢊꢆꢋ

ꢌꢅ

ꢋꢁꢀ ꢅ

When Port A is configured as a 4-wire interface, Port A

is always the slave port and Port B is the master port.

Communication is always initiated on Port A of the first

device in the daisy chain configuration. The final device

in the daisy chain does not use Port B, and it should

be terminated into RM. Figure 24 shows the simplest

port connections possible when the microprocessor

and the LTC6810s are located on the same PCB. In this

figure capacitors are used to couple signals between the

LTC6810s.

ꢀ

Rꢁꢂ

ꢄꢇꢈ

ꢄꢆꢈ

ꢄꢇA

ꢄꢆA

ꢃ

ꢀ

ꢂꢌꢋꢈ

ꢍꢎꢅꢏꢐꢑꢒꢓꢑ

ꢋAꢄꢉꢔꢓꢅꢕAꢄꢌ

ꢆꢊꢋꢁ

ꢃ

ꢂꢌꢋꢈ

ꢄꢅꢆꢇ

ꢄꢈꢄAꢉ

ꢄꢉꢊꢆꢋ

ꢌꢅ

When Port A is configured as a 2-wire interface, com

-

ꢌꢅ

ꢋꢁꢀ ꢈ

ꢀ

Rꢁꢂ

ꢄꢇꢈ

munication can be initiated on either Port A or Port B. If

communication is initiated on Port A, LTC6810 configures

Port A as slave and Port B as master. Likewise, if com-

munication is initiated on Port B, LTC6810 configures

Port B as slave and Port A as master. See the Reversible

isoSPI for LTC6810-1 section for a detailed description

of reversible isoSPI.

ꢂꢌꢋA

ꢄꢆꢈ

ꢍꢎꢅꢏꢐꢑꢒꢓꢑ

ꢋAꢄꢉꢔꢓꢅꢕAꢄꢌ

ꢆꢊꢋꢁ

ꢀ

ꢋꢋA

ꢉꢅꢚ

ꢅꢉꢈ

ꢅꢍꢚ

ꢅꢉ

ꢀ

ꢋꢋ

ꢃ

ꢀ

ꢃ

ꢛꢜ

ꢄꢅꢆꢇ

ꢄꢈꢄAꢉ

ꢆꢇꢖ

ꢄꢉꢊꢆꢋ

ꢂꢌꢋA

ꢉꢋꢊ

ꢉꢋꢄ

ꢆꢄꢉꢊ

ꢆꢊꢉꢄ

ꢋꢁꢀ A

ꢏꢐꢑꢒꢑ ꢗꢘꢙ

Figure 24. Capacitive-Coupled Daisy-Chain Configuration

Using LT6810-1

Rev. A

47

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Figure 25 is an example of a robust interconnection of

multiple identical PCBs, each containing 1 LTC6810-1.

The microprocessor is located on a separate PCB. To

achieve 2-wire isolation between the microprocessor PCB

and the 1st LTC6810 PCB, use the LTC6820 support IC.

The LTC6820 is functionally equivalent to the diagram in

Figure 16. In this example, communication is initiated on

Port A. So the LTC6810 configures Port A as slave and

Port B as master.

Reversible isoSPI for LTC6810-1

Figure 26 illustrates a daisy-chained configuration of

LTC6810-1s using reversible isoSPI. LTC6820s are con-

nected on either side of the daisy-chain. Both LTC6820s

are configured as Master and share the same SPI interface

to connect to the MPU. The MPU uses two CS signals to

talk to one of the two LTC6820s.

ꢍꢈꢎ

ꢍꢇꢎ

ꢀꢁꢂꢃꢄꢓꢆꢖꢓ

ꢌAꢍꢑꢗꢖꢂꢘAꢍꢋ ꢍꢈA

ꢇꢒꢌꢐ

ꢍꢇA

ꢙ

ꢏ

ꢙ

ꢏ

ꢊꢋꢌꢌ

ꢍꢂꢇꢈ

ꢍꢎꢍAꢑ

ꢍꢑꢒꢇꢌ

ꢌꢐꢏ ꢂ

ꢏ

Rꢐꢊ

ꢊꢋꢌꢌ

ꢍꢈꢎ

ꢍꢇꢎ

ꢍꢈA

ꢀꢁꢂꢃꢄꢓꢆꢖꢓ

ꢌAꢍꢑꢗꢖꢂꢘAꢍꢋ

ꢇꢒꢌꢐ

ꢍꢇA

ꢙ

ꢏ

ꢙ

ꢏ

ꢊꢋꢌꢂ

ꢍꢂꢇꢈ

ꢍꢎꢍAꢑ

ꢍꢑꢒꢇꢌ

ꢌꢐꢏ ꢎ

ꢏ

Rꢐꢊ

ꢊꢋꢌꢂ

ꢏ

ꢌꢌA

ꢇꢑꢁR

ꢍꢎꢍAꢑ

ꢍꢂꢇꢈ

ꢈꢒꢀ

ꢈꢘA

ꢍꢈ

ꢇꢒꢑꢍ

ꢇꢍꢑꢒ

ꢑꢂꢚ

ꢇꢒꢑꢍ

ꢇꢍꢑꢒ

ꢂꢀꢚ

ꢍꢈꢎ

ꢍꢇꢎ

ꢇꢈꢉ

ꢊꢋꢌA

ꢀꢁꢂꢃꢄꢅꢆ

ꢂꢑꢎ

ꢑꢂ

ꢏ

ꢌꢌ

ꢏ

ꢂꢂꢆ

ꢐꢋ

ꢍꢈA

ꢀꢁꢂꢃꢄꢓꢆꢖꢓ

ꢌAꢍꢑꢗꢖꢂꢘAꢍꢋ

ꢇꢒꢌꢐ

ꢍꢇA

ꢑꢀꢒꢛ

ꢏ

ꢍꢇ

ꢙ

ꢏ

ꢂꢂ

ꢙ

ꢏ

ꢊꢋꢌꢎ

ꢍꢂꢇꢈ

ꢍꢎꢍAꢑ

ꢍꢑꢒꢇꢌ

ꢃꢄꢓꢆꢓ ꢔꢅꢕ

ꢌꢐꢏ A

ꢏ

Rꢐꢊ

Figure 25. Transformer-Coupled Daisy-Chain Configuration Using LT6810-1

Rev. A

48

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

For example, in Figure 26, if the bottom LTC6820 is

addressed, then LTC6810 DEV A becomes the first device

in the stack followed by DEV B and DEV C. Port A of

each LTC6810 is configured as the slave and Port B is

configured as the Master. On the other hand, if the top

LTC6820 is addressed, then LTC6810 DEV C becomes

the first device in the stack followed by DEV B and DEV

A. Port B of each LTC6810 is configured as slave and Port

A is configured as Master.

The reversible isoSPI provides a redundant communica-

tion path in the event of a single point failure in the 2-wire

interface.

ꢍꢋꢎ

ꢍꢊꢎ

ꢃꢄꢅꢆꢇꢓꢉꢕꢓ

ꢂAꢍꢑꢖꢕꢅꢗAꢍꢁ ꢍꢋA

ꢊꢒꢂꢐ

ꢍꢊA

ꢘ

ꢏ

ꢘ

ꢏ

ꢀꢁꢂꢂ

ꢍꢅꢊꢋ

ꢍꢎꢍAꢑ

ꢍꢑꢒꢊꢂ

ꢂꢐꢏ ꢅ

ꢏ

Rꢐꢀ

ꢀꢁꢂꢂ

ꢍꢋꢎ

ꢍꢊꢎ

ꢍꢋA

ꢃꢄꢅꢆꢇꢓꢉꢕꢓ

ꢂAꢍꢑꢖꢕꢅꢗAꢍꢁ

ꢊꢒꢂꢐ

ꢍꢊA

ꢘ

ꢏ

ꢊꢑꢄR

ꢍꢎꢍAꢑ

ꢍꢅꢊꢋ

ꢋꢒꢃ

ꢋꢗA

ꢍꢋ

ꢊꢒꢑꢍ

ꢊꢍꢑꢒ

ꢑꢅꢙ

ꢘ

ꢏ

ꢀꢁꢂꢅ

ꢍꢅꢊꢋ

ꢍꢎꢍAꢑ

ꢀꢁꢂA

ꢃꢄꢅꢆꢇꢈꢉ

ꢅꢑꢈ

ꢅꢑꢎ

ꢍꢑꢒꢊꢂ

ꢏ

ꢅꢅꢉ

ꢐꢁ

ꢊꢋꢌ

ꢂꢐꢏ ꢎ

ꢍꢊ

ꢑꢃꢒꢚ

ꢏ

Rꢐꢀ

ꢀꢁꢂꢅ

ꢅꢅ

ꢊꢒꢑꢍ

ꢊꢍꢑꢒ

ꢅꢃꢙ

ꢊꢑꢄR

ꢍꢎꢍAꢑ

ꢍꢅꢊꢋ

ꢋꢒꢃ

ꢋꢗA

ꢍꢋ

ꢊꢒꢑꢍ

ꢊꢍꢑꢒ

ꢑꢅꢙ

ꢍꢋꢎ

ꢍꢊꢎ

ꢀꢁꢂA

ꢃꢄꢅꢆꢇꢈꢉ

ꢅꢑꢓ

ꢅꢑꢎ

ꢏ

ꢂꢂ

ꢏ

ꢅꢅꢉ

ꢐꢁ

ꢏ

ꢂꢂA

ꢍꢋA

ꢃꢄꢅꢆꢇꢓꢉꢕꢓ

ꢂAꢍꢑꢖꢕꢅꢗAꢍꢁ

ꢊꢒꢂꢐ

ꢍꢊA

ꢑꢃꢒꢚ

ꢏ

ꢍꢊ

ꢘ

ꢏ

ꢅꢅ

ꢘ

ꢏ

ꢀꢁꢂꢎ

ꢍꢅꢊꢋ

ꢍꢎꢍAꢑ

ꢍꢑꢒꢊꢂ

ꢆꢇꢓꢉꢓ ꢔꢈꢆ

ꢂꢐꢏ A

ꢏ

Rꢐꢀ

Figure 26. Reversible isoSPI Daisy Chain using the LTC6810-1

Rev. A

49

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

The LTC6810-2 has a single serial port (Port A) which can

be 2-wire or 4-wire, depending on the state of the ISOMD

pin. When configured for 2-wire communications, several

devices can be connected in a multi-drop configuration,

as shown in Figure 27. The LTC6820 IC is used to inter-

face the MPU (master) to the LTC6810-2s (slaves).

Aꢍ

Aꢅ

ꢎꢈA

ꢎꢇA

ꢘ

ꢀꢁꢂꢃꢄꢑꢆꢗꢅ

ꢈARAꢀꢀꢐꢀ

ꢇꢓꢌꢐ

ꢏ

ꢘ

ꢊꢋꢌꢌ

Aꢑ

Aꢆ

ꢎꢒꢓꢇꢌ

ꢎꢂꢇꢈ

ꢎꢔꢎAꢒ

ꢌꢐꢏ ꢂ

ꢏ

Rꢐꢊ

ꢊꢋꢌꢌ

Aꢍ

Aꢅ

ꢎꢈA

ꢎꢇA

ꢘ

ꢏ

ꢘ

ꢏ

ꢊꢋꢌꢂ

ꢀꢁꢂꢃꢄꢑꢆꢗꢅ

ꢈARAꢀꢀꢐꢀ

ꢇꢓꢌꢐ

Aꢑ

Aꢆ

ꢎꢒꢓꢇꢌ

ꢎꢂꢇꢈ

ꢎꢔꢎAꢒ

ꢌꢐꢏ ꢔ

ꢏ

Rꢐꢊ

ꢊꢋꢌꢂ

Aꢍ

Aꢅ

ꢎꢈA

ꢎꢇA

ꢘ

ꢏ

ꢘ

ꢏ

ꢀꢁꢂꢃꢄꢑꢆꢗꢅ

ꢈARAꢀꢀꢐꢀ

ꢇꢓꢌꢐ

ꢊꢋꢌꢔ

ꢏ

ꢌꢌA

Aꢑ

Aꢆ

ꢎꢒꢓꢇꢌ

ꢎꢂꢇꢈ

ꢎꢔꢎAꢒ

ꢇꢓꢒꢎ

ꢇꢎꢒꢓ

ꢒꢂꢚ

ꢇꢓꢒꢎ

ꢇꢎꢒꢓ

ꢂꢀꢚ

ꢇꢒꢁR

ꢎꢔꢎAꢒ

ꢎꢂꢇꢈ

ꢈꢓꢀ

ꢈꢙA

ꢎꢈ

ꢇꢈꢉ

ꢀꢁꢂꢃꢄꢅꢆ

ꢂꢒꢔ

ꢒꢂ

ꢏ

ꢌꢌ

ꢊꢋꢌA

ꢏ

ꢂꢂꢆ

ꢐꢋ

ꢌꢐꢏ A

ꢒꢀꢓꢛ

ꢏ

ꢎꢇ

Rꢐꢊ

ꢊꢋꢌꢔ

ꢂꢂ

ꢏ

Rꢐꢊ

ꢃꢄꢑꢆꢑ ꢕꢅꢖ

Figure 27. Transformer-Coupled Multi-Drop Configuration Using LT6810-2

Rev. A

50

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Selecting Bias Resistors

isoSPI Pulse Detail

The isoSPI transmitter drive current and comparator volt-

age threshold are set by a resistor divider (RBIAS = RB1 +

Two LTC6810 devices can communicate by transmitting

andreceivingdifferentialpulsesbackandforththroughan

isolation barrier. The transmitter can output three voltage

levels: +VA, 0V, and –VA. A positive output results from

IP sourcing current and IM sinking current across load

resistor RM. A negative voltage is developed by IP sink-

ing and IM sourcing. When both outputs are off, the load

resistance forces the differential output to 0V.

–

RB2) between the IBIAS and V pins. The divided voltage

is connected to the ICMP pin, which sets the comparator

threshold to ½ of this voltage (V

). When either isoSPI

ICMP

interface is enabled (not IDLE) IBIAS is held at 2V, causing

a current IB to flow out of the IBIAS pin. The IP and IM

pin drive currents are 20 • I .

B

As an example, if divider resistor RB1 is 1.78kΩ and resis-

tor RB2 is 200Ω (so that RBIAS = 2kΩ), then:

To eliminate the DC signal component and enhance reli-

ability,isoSPIpulsesaredefinedassymmetricpulsepairs.

A +1 pulse will be transmitted as a positive pulse followed

by a negative pulse. A –1 pulse will be transmitted as a

negative pulse followed by a positive pulse. The duration

2V

I =

= 1mA

B

R +R

B1

B2

of each pulse is defined as t

, since each is half of the

½PW

I

= I = I = 20 • I = 20mA

IP IM B

DRV

required symmetric pair (the total isoSPI pulse duration

).

R

is 2 • t

½PW

B2

V

= 2V •

= I • R = 422mV

B B2

ICMP

R +R

B1

B2

Table 27. isoSPI Pulse Types

FIRST LEVEL

SECOND LEVEL

(t

V

TCMP

= 0.5 • V

= 211mV

ICMP

PULSE TYPE

(t

)

½PW

ENDING LEVEL

½PW

Long +1

+V (150ns)

–V (150ns)

0V

Inthisexample,thepulsedrivecurrentIDRVwillbe20mA,

andthereceivercomparatorswilldetectpulseswithIP–IM

amplitudes greater than 211mV.

A

Long –1

–V (150ns)

A

+V (150ns)

A

Short +1

Short –1

+V (50ns)

A

–V (50ns)

A

–V (50ns)

A

+V (50ns)

A

If the isolation barrier uses 1:1 transformers connected

by a twisted pair and terminated with 100Ω resistors on

eachend,thenthetransmitteddifferentialsignalamplitude

( ) will be:

A host microcontroller does not have to generate isoSPI

pulses to use this 2-wire interface. The first LTC6810 in

the system can communicate to the microcontroller using

the 4-wire SPI interface on its Port A, then daisy-chain to

other LTC6810s using the 2-wire isoSPI interface on its

Port B. Alternatively, the LTC6820 can be used to translate

the SPI signals into isoSPI pulses.

R

M

V = I

•

= 1V

A

DRV

2

(This result ignores transformer and cable losses, which

may reduce the amplitude.)

Theadjustablesignalamplitudeallowsthesystemtotrade

power consumption for communication robustness, and

the adjustable comparator threshold allows the system to

account for signal losses.

Operation with Port A Configured for SPI

When the LTC6810-1 is operation with Port A as a SPI

–

(ISOMD = V ), the SPI detects one of four communication

events: CSB falling, CSB rising, SCK rising with SDI = 0,

and SCK rising with SDI = 1. Each event is converted

into one of four pulse types for transmission to another

daisy-chained LTC6810. Long pulses are used to transmit

CSB changes and short pulses transmit data as explained

in Table 28.

Rev. A

51

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Table 28. Port B (Master) isoSPI Port Function

Table 29. Port A (Slave) isoSPI Port Function

COMMUNICATION EVENT

(Port A SPI)

TRANSMITTED PULSE

RECEIVED PULSE INTERNAL SPI PORT

RETURN PULSE

(Port B isoSPI)

(Port A isoSPI)

ACTION

CS Rising

Long +1

Drive CS High

Drive CS Low

None

CS Falling

Long –1

Short –1 Pulse if Reading a

0 bit

SCK Rising Edge, SDI = 1

SCK Rising Edge, SDI = 0

Short +1

1. Set SDI = 1

2. Pulse SCK

(No Return Pulse if Not in READ

Mode or if Reading a 1 bit)

Short –1

1. Set SDI = 0

2. Pulse SCK

Operation with Port A Configured for isoSPI

The slave isoSPI port (slave) never transmits long (CSB)

pulses. Furthermore, a slave isoSPI port will only trans-

mit short –1 pulses, never a +1 pulse. The master port

recognizes a null response as a logic 1. This allows for

multiple slave devices on a single cable without risk of

collisions (Multi-drop).

On the other side of the isolation barrier (i.e. at the other

endofthecable),the2ndLTC6810willhaveISOMD=V

Its Port A operates as a slave isoSPI interface. It receives

each transmitted pulse and reconstructs the SPI signals

internally,asshowninTable29.Inaddition,duringaREAD

command this port may transmit return data pulses.

.

REG

+1 PULSE

ꢀꢁ

A

ꢇ

ꢀꢁ

ꢊꢋꢌꢆꢍ

ꢃꢄꢅꢆ

V

– V

IP

IM

ꢇ

ꢂꢁ

ꢈꢉꢁ

ꢊꢋꢌꢆꢍ

ꢃꢄꢅꢆ

ꢂꢁ

A

–1 PULSE

ꢀꢁ

A

ꢇ

ꢀꢁ

ꢈꢉꢁ

ꢊꢋꢌꢆꢍ

ꢃꢄꢅꢆ

V

– V

IP

IM

ꢇ

ꢂꢁ

ꢊꢋꢌꢆꢍ

ꢃꢄꢅꢆ

ꢂꢁ

A

ꢎꢏꢊꢐꢊ ꢑꢌꢏ

Figure 28. isoSPI Pulse Detail

Rev. A

52

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Timing Diagrams

Bits WN–W0 refers to the 16 bit command code and the

16 bit PEC of a READ command. At the end of bit W0 the

3 parts decode the READ command and begin shifting out

datawhichisvalidonthenextrisingedgeofclockSCK.Bits

XN–X0 refer to the data shifted out by Part 1. Bits YN–Y0

refer to the data shifted out by Part 2 and bits ZN–Z0 refer

to the data shifted out by Part 3. All this data is read back

from the SDO port on Part 1 in a daisy-chained fashion.

Figure 29 shows the isoSPI timing diagram for a READ

command to daisy chained LTC6810-1 parts. The ISOMD

–

pin is tied to V on the bottom part so its Port A is config-

ured as a SPI port (CSB, SCK, SDI and SDO). The isoSPI

signals of three stacked devices are shown labeled with

the port (A or B) and part number. Note that ISO B1 and

ISO A2 is actually the same signal, but shown on each

end of the transmission cable that connects Parts 1 and 2.

Likewise, ISO B2 and ISO A3 is the same signal, but with

the cable delay shown between Parts 2 and 3.

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ꢇꢈꢉ

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ꢓ

ꢖ

ꢀ

ꢕ

ꢂ

ꢕ

ꢅ

ꢕ

ꢊꢗꢋ

ꢕ

ꢎ

ꢇꢊꢋ

ꢔ

ꢕ

ꢁ

ꢕ

ꢂꢂ

ꢕ

Rꢉꢇꢏ

ꢇꢈꢌ

ꢟ

ꢛ

ꢃ

ꢜ

ꢜꢝꢂ

ꢕ

ꢆ

ꢂꢃ

ꢞ

ꢘ

ꢜ

ꢘ

ꢜꢝꢂ

ꢜ

ꢃ

ꢜ

ꢉꢇꢌ ꢍꢂ

ꢉꢇꢌ Aꢅ

ꢉꢇꢌ ꢍꢅ

ꢉꢇꢌ Aꢎ

ꢞ

ꢘ

ꢜꢝꢂ

ꢜ

ꢃ

ꢕ

Rꢐꢒ

ꢕ

ꢈꢇꢘꢙꢊꢇꢚ

ꢕ

ꢈꢇꢘꢙꢈꢚ

ꢞ

ꢛ

ꢜ

ꢛ

ꢜꢝꢂ

ꢜ

ꢃ

ꢜ

ꢞ

ꢛ

ꢜꢝꢂ

ꢜ

ꢃ

ꢀꢁꢂꢃꢂ ꢄꢅꢆ

ꢃ

ꢂꢃꢃꢃ

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ꢎꢃꢃꢃ

ꢔꢃꢃꢃ

ꢓꢃꢃꢃ

ꢀꢃꢃꢃ

Figure 29. isoSPI Timing Diagram

Rev. A

53

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Waking up the Serial Interface

Waking a Daisy Chain — Method 1

The serial ports (SPI or isoSPI) will enter the low power

IDLE state if there is no activity on Port A or Port B for

The LTC6810-1 sends a long +1 pulse on Port B after it is

ready to communicate. In a daisy-chained configuration,

this pulse wakes up the next device in the stack which will,

in turn, wake up the next device. If there are ‘N’ devices in

the stack, all the devices are powered up within the time

a time of t

. The WAKEUP circuit monitors activity on

IDLE

pins 36 and 37, which are CSB and SCK if ISOMD is low,

or IPA and IMA if ISOMD is high, and activity on pins 38

and 39, which are IMB and IPB for LTC6810-1 and A2 and

A3 for LTC6810-2.

N • t

or N • t

, depending on the Core state. For

WAKE

READY

large stacks, the time N • t

may be equal to or larger

WAKE

than t

. In this case, after waiting longer than the time

, the host may send another dummy byte and

–

IDLE

If ISOMD = V , Port A is in SPI mode. Activity on the CSB

of N • t

WAKE

orSCKpinwillwakeuptheSPIinterface. IfISOMD=V

,

REG

wait for the time N • t

devices are in the READY state.

, in order to ensure that all

READY

PortAisinisoSPImode.DifferentialactivityonIPA–IMAor

IPB–IMB wakes up the isoSPI interface. The LTC6810 will

be ready to communicate when the isoSPI state changes

Method 1 can be used when all devices on the daisy chain

are in the IDLE state. This guarantees that they propagate

the wake-up signal up the daisy chain. However, this

method will fail to wake up all devices when a device in

the middle of the chain is in the READY state instead of

IDLE. When this happens, the device in READY state will

not propagate the wake-up pulse, so the devices above it

will remain IDLE. This situation can occur when attempt-

to READY within t

or t

, depending on the Core

WAKE

READY

state (see Figure 1 and state descriptions for details).

Figure 30 illustrates the timing and the functionally

equivalent circuit. The wake-up circuit responds to the

difference between SCK(IPA) and CS(IMA). Common

mode signals will not wake up the serial interface. The

interface is designed to wake up after receiving a large

signal single-ended pulse, or a low-amplitude symmetric

pulse. The differential signal | SCK(IPA) – CS(IMA)|, must

ing to wake up the daisy chain after only t

of idle time

IDLE

(some devices may be IDLE, some may not).

be at least V

DWELL

= 200mV for a minimum duration of

WAKE

t

= 240ns to qualify as a wake up signal that powers

up the serial interface.

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ꢇꢆꢌ ꢉR ꢊꢍA

ꢤ

ꢚ ꢡꢜꢃꢝꢤ

ꢒAꢌꢓ

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ꢛ

ꢚ ꢡꢢꢃꢣꢞ

ꢘꢒꢓꢙꢙ

ꢒAꢌꢓꢑꢔꢍ

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ꢙꢉꢒ ꢍꢉꢒꢓR ꢋꢉꢘꢓ

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ꢙꢉꢒ ꢍꢉꢒꢓR ꢋꢉꢘꢓ

ꢚ ꢛ

RꢓAꢘꢟ

ꢏꢂꢃꢠꢞꢐ

ꢚ ꢛ

ꢊꢘꢙꢓ

ꢏꢜ.ꢜꢝꢞꢐ

RꢓꢕRꢊꢥꢥꢓRAꢈꢙꢓ

ꢦ ꢜ.ꢜꢝꢞ

ꢆꢇꢈ

ꢇꢆꢌ

ꢒAꢌꢓꢑꢔꢍ

ꢡꢃꢃꢣꢞ

ꢘꢓꢙAꢟ

ꢛ

ꢊꢘꢙꢓ

ꢉꢗꢓꢑꢇꢧꢉꢕ

ꢀꢁꢂꢃꢂ ꢄꢅꢃ

Figure 30. Wake-up Detection and IDLE Timer

Rev. A

54

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Waking a Daisy Chain — Method 2

To calculate the 15-bit PEC value, a simple procedure can

be established:

Amorerobustwake-upmethoddoesnotrelyonthebuilt-in

wake-uppulse,butmanuallysendsisoSPItrafficforenough

time to wake the entire daisy chain. At minimum, a pair of

long isoSPI pulses (–1 and +1) is needed for each device,

separated by more than t

is STANDBY or SLEEP, respectively), but less than t

This allows each device to wake up and propagate the next

pulse to the following device. This method works even if

some devices in the chain are not in the IDLE state. In

practice,implementingmethod2requirestogglingtheCSB

pin (of the LTC6820, or bottom LTC6810 with ISOMD = 0)

to generate the long isoSPI pulses. Alternatively, dummy

commands (such as RDCFG) can be executed to generate

the long isoSPI pulses.

1. Initialize the PEC to 000000000010000 (PEC is a 15 bit

register group)

2. For each bit DIN coming into the PEC register group,

set

or t

(if the Core state

READY

WAKE

.

IDLE

IN0 = DIN XOR PEC [14]

IN3 = IN0 XOR PEC [2]

IN4 = IN0 XOR PEC [3]

IN7 = IN0 XOR PEC [6]

IN8 = IN0 XOR PEC [7]

IN10 = IN0 XOR PEC [9]

IN14 = IN0 XOR PEC [13]

3. Update the 15-bit PEC as follows

PEC [14] = IN14,

PEC [13] = PEC [12],

PEC [12] = PEC [11],

PEC [11] = PEC [10],

PEC [10] = IN10,

PEC [9] = PEC [8],

PEC [8] = IN8,

DATA LINK LAYER

All Data transfers on LTC6810 occur in byte groups.

Every byte consists of 8 bits. Bytes are transferred with

the most significant bit (MSB) first. CSB must remain low

for the entire duration of a command sequence, including

between a command byte and subsequent data. On a write

command, data is latched in on the rising edge of CSB.

PEC [7] = IN7,

PEC [6] = PEC [5],

PEC [5] = PEC [4],

PEC [4] = IN4,

NETWORK LAYER

Packet Error Code

PEC [3] = IN3,

PEC [2] = PEC [1],

PEC [1] = PEC [0],

PEC [0] = IN0

The packet error code (PEC) is a 15-bit cyclic redundancy

check (CRC) value calculated for all of the bits in a register

group in the order they are passed, using the initial PEC

value of 000000000010000 and the following character-

4. Go back to step 2 until all the data is shifted. The final

PEC (16 bits) is the 15 bit value in the PEC register with

a 0 bit appended to its LSB

15

14

10

8

7

4

3

istic polynomial: x + x + x + x + x + x + x + 1.

ꢋꢉꢊ

ꢇꢉꢊ ꢒꢋR ꢎAꢐꢌ

ꢇꢉꢊ

ꢒ

ꢊꢌꢍ RꢌꢎꢇꢏꢐꢌR ꢑꢇꢐ ꢒ

ꢆꢇꢈ

ꢂꢔ

ꢂꢅ ꢂꢓ ꢂꢂ ꢂꢃ

ꢗ

ꢁ

ꢖ

ꢀ

ꢕ

ꢔ

ꢅ

ꢓ

ꢂ

ꢃ

ꢀꢁꢂꢃꢂ ꢄꢅꢂ

Figure 31.

Rev. A

55

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Figure 31 illustrates the algorithm described above. An

example to calculate the PEC for a 16 bit word (0x0001)

is listed in Table 30. The PEC for 0x0001 is computed as

0x3D6E after stuffing a 0 bit at the LSB. For longer data

streams, the PEC is valid at the end of the last bit of data

sent to the PEC register.

LTC6810calculatesPECforanycommandordatareceived

and compares it with the PEC following the command or

data. The command or data is regarded as valid only if

the PEC matches. LTC6810 also attaches the calculated

PEC at the end of the data it shifts out. Table 31 shows the

format of PEC while writing to or reading from LTC6810.

Table 30. PEC Calculation for 0x0001

PEC[14]

PEC[13]

PEC[12]

PEC[11]

PEC[10]

PEC[9]

PEC[8]

PEC[7]

PEC[6]

PEC[5]

PEC[4]

PEC[3]

PEC[2]

PEC[1]

PEC[0]

IN14

0

1

0

1

0

1

0

1

0

1

0

2

0

1

0

1

0

3

0

1

0

4

0

1

0

1

0

5

0

1

0

6

0

1

0

7

0

1

0

8

0

1

0

1

0

9

1

0

1

0

10

1

0

1

0

1

0

1

0

1

0

1

0

1

0

11

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

12

1

0

1

0

1

0

1

0

1

0

13

1

0

1

0

1

0

1

0

1

0

14

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

IN10

PEC word

IN8

IN7

IN4

IN3

IN0

DIN

Clock Cycle

16

Table 31. Write/Read PEC format

Name

PEC0

PEC1

RD/WR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PEC[7]

0

PEC[14]

PEC[6]

PEC[13]

PEC[5]

PEC[12]

PEC[4]

PEC[11]

PEC[3]

PEC[10]

PEC[2]

PEC[9]

PEC[1]

PEC[8]

PEC[0]

Rev. A

56

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

While writing any command to LTC6810, the command

bytes CMD0 and CMD1 (see Table 38 and Table 39) and

the PEC bytes PEC0 and PEC1 are sent on Port A in the

following order:

In parallel (LTC6810-2) configurations, broadcast com-

mands are useful for initiating ADC conversions or for

sending write commands when all parts are being written

with the same data. The polling function (automatic at the

end of ADC commands, or manual using the PLADC com-

mand) can also be used with broadcast commands, but

not with parallel isoSPI devices. Likewise, broadcast read

commandsshouldnotbeusedintheparallelconfiguration

(either SPI or isoSPI).

CMD0, CMD1, PEC0, PEC1

After a broadcast write command to daisy chained

LTC6810-1 devices, data is sent to each device followed

by the PEC. For example, when writing the Configuration

Register Group to two daisy-chained devices (primary

device P, stacked device S), the data will be sent to the

primary device on its slave port in the following order:

Daisy-chained(LTC6810-1)configurationssupportbroad-

cast commands only, because they have no addressing.

All devices in the chain receive the command bytes simul-

taneously. For example, to initiate ADC conversions in a

stack of devices, a single ADCV command is sent, and all

devices will start conversions at the same time. For read

and write commands, a single command is sent, and then

the stacked devices effectively turn into a cascaded shift

register, in which data is shifted through each device to the

nexthigher(onawrite)orthenextlower(onaread)device

in the stack. See the Serial Interface Overview section.

CFGR0(S), …, CFGR5(S), PEC0(S), PEC1(S),

CFGR0(P), …, CFGR5(P), PEC0(P), PEC1(P)

After a read command for daisy chained devices, each

device shifts out its data and the PEC that it computed for

its data on its slave port followed by the data received on

itsmasterport.Forexample,whenreadingStatusRegister

Group B from two daisy-chained devices (primary device

P, stacked device S), the primary device sends out data on

its slave port in the following order:

Polling Methods

STBR0(P), …, STBR5(P), PEC0(P), PEC1(P),

STBR0(S), …, STBR5(S), PEC0(S), PEC1(S)

The simplest method to determine ADC completion is

for the controller to start an ADC conversion and wait for

the specified conversion time to pass before reading the

results.BothLTC6810-1andLTC6810-2alsoallowpolling

to determine ADC completion.

Address Commands (LTC6810-2 Only)

An address command is one in which only the addressed

device on the bus responds. Address commands are used

only with LTC6810-2 parts. All commands are compatible

withaddressing.SeetheBusProtocolssectionforAddress

command format.

In parallel configurations that communicate in SPI mode

(ISOMD pin tied low), there are two methods of polling.

The first method is to hold CSBI low after an ADC con-

version command is sent. After entering a conversion

command, the SDO line is driven low when the device is

busy performing conversions. SDO is pulled high when

the device completes conversions. However, the SDO

will also go back high when CSBI goes high even if the

device has not completed the conversion (Figure 32). An

addressed device drives the SDO line based on its status

alone. A problem with this method is that the controller

is not free to do other serial communication while waiting

for ADC conversions to complete.

Broadcast Commands (LTC6810-1 or LTC6810-2)

A broadcast command is one to which all devices on

the bus will respond, regardless of device address. This

command can be used with LTC6810-1 and LTC6810-2

parts. See the Bus Protocols section for Broadcast com-

mand format. With broadcast commands all devices can

be sent commands simultaneously.

Rev. A

57

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

The next method overcomes this limitation. The controller

cansendanADCstartcommand,performothertasks,and

then send a poll ADC converter status (PLADC) command

todeterminethestatusoftheADCconversions(Figure33).

After entering the PLADC command, SDO will go low if

the device is busy performing conversions. SDO is pulled

high at the end of conversions. However, the SDO will also

go high when CSBI goes high even if the device has not

completed the conversion.

InparallelconfigurationsthatcommunicateinisoSPImode,

the low side port transmits a data pulse only in response

to a master isoSPI pulse received by it. So, after enter-

ing the command in either method of polling described

above, isoSPI data pulses are sent to the part to update

the conversion status. These pulses can be sent using

LTC6820 by simply clocking its SCK pin. In response to

this pulse, the device sends back a low isoSPI pulse if it

is still busy performing conversions or a high data pulse

if it has completed the conversions. If a CSB high isoSPI

pulse is sent to the device, it exits the polling command.

ꢌ

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ꢇꢊꢋ

ꢇꢈꢉ

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ꢑꢉꢖ ꢂꢗꢓꢊꢒꢈꢔ

ꢎꢇꢑꢓꢕꢏꢊꢔ

ꢇꢈꢐ

ꢀꢁꢂꢃꢂ ꢄꢅꢆ

Figure 32. SDO Polling After an ADC Conversion Command (Parallel Configuration)

ꢉꢆꢌ

ꢆꢉꢊ

ꢆꢇꢈ

ꢍꢆꢌꢎꢉꢍꢇꢏ

ꢌꢈꢕ ꢂꢖꢎꢉꢍꢇꢏ

ꢐꢆꢌꢎꢑꢒꢉꢏ

ꢆꢇꢋ

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ꢀꢁꢂꢃꢂ ꢄꢅꢅ

Figure 33. SDO Polling Using PLADC Command (Parallel Configuration)

Rev. A

58

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

In a daisy-chained configuration of N stacked devices,

the same two polling methods can be used. If the bottom

device communicates in SPI mode, the SDO of the bot-

tom device indicates the conversion status of the entire

stack (i.e. SDO will remain low until all the devices in the

stack have completed conversions). In the first method of

polling, after an ADC conversion command is sent, clock

pulses are sent on SCK while keeping CSB low. The SDO

status becomes valid only at the end of N clock pulses on

SCK and gets updated for every clock pulse that follows

(Figure 34). In the second method, the PLADC command

is sent followed by clock pulses on SCK while keeping

CSBI low. Similar to the first method, the SDO status is

valid only after N clock cycles on SCKI and gets updated

after every clock cycle that follows (Figure 35).

IfthebottomdevicecommunicatesinisoSPImode,isoSPI

data pulsesare sent to the device to update the conversion

status. Using LTC6820, this can be achieved by just clock-

ing its SCK pin. The conversion status is valid only after

the bottom LTC6810 device receives N isoSPI data pulses

and the status gets updated for every isoSPI data pulse

that follows. The device returns a low data pulse if any of

the devices in the stack is busy performing conversions

and returns a high data pulse if all the devices are free.

ꢌ

ꢐAꢎꢎ ꢈꢏꢑꢉꢊꢏꢇꢒ

ꢊꢍꢊꢎꢏ

ꢊꢇꢔ

ꢂ

ꢗ

ꢘ

ꢇꢊꢋ

ꢇꢈꢉ

ꢕꢇꢔꢐꢊꢕꢈꢒ

ꢎꢇꢔꢐꢖꢏꢊꢒ

ꢇꢈꢓ

ꢀꢁꢂꢃꢂ ꢄꢅꢆ

Figure 34.

ꢊꢇꢍ

ꢂ

ꢔ

ꢕ

ꢇꢊꢋ

ꢇꢈꢉ

ꢎꢇꢍꢏꢊꢎꢈꢐ

ꢑꢇꢍꢏꢒꢓꢊꢐ

ꢇꢈꢌ

ꢀꢁꢂꢃꢂ ꢄꢅꢆ

ꢊꢌꢕꢖꢓRꢇꢉꢌꢕ ꢈꢌꢕꢓ

Figure 35.

Rev. A

59

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Bus Protocols

Command Format: The formats for the broadcast and

address commands are shown in Table 38 and Table 39

respectively. The 11 bit command code CC[10:0] is the

same for a broadcast or an address command. A list of

all the command codes is shown in Table 40. A broadcast

command has a value 0 for CMD0[7] through CMD0[3].

An address command has a value 1 for CMD0[7] fol-

lowed by the 4 bit address of the device (a3, a2, a1, a0)

in bits CMD0[6:3]. An addressed device will respond

to an address command only if the physical address of

the device on pins A3 to A0 match the address specified

in the address command. The PEC for broadcast and

address commands must be computed on the entire 16

bit command (CMD0 and CMD1).

Protocol Format: The protocol formats for both broadcast

and address commands are depicted in Table 33 through

Table 37. Table 32 is the key for reading the protocol diagrams.

Table 32. Protocol Key

CMD0

CMD1

PEC0

PEC1

N

Command Byte 0 (See Table 38 and Table 39)

Command Byte 1 (See Table 38 and Table 39)

Packet Error Code Byte 0 (See Table 31)

Packet Error Code Byte 1 (See Table 31)

Number of Bytes

…

Continuation of Protocol

Master to Slave

Slave to Master

Table 33. Broadcast/Address Poll Command

8

CMD0

CMD1

PEC0

PEC1

Poll Data

Table 34. Broadcast Write Command

8

CMD0

CMD1

PEC0

PEC1

Data Byte Low

…

Data Byte High

PEC0

PEC1

Shift Byte 1

…

Shift Byte n

Table 35. Address Write Command

8

CMD0

CMD1

PEC0

PEC1

Data Byte Low

Data Byte High

PEC0

PEC1

Table 36. Broadcast Read Command

8

CMD0

CMD1

PEC0

PEC1

Data Byte Low

Data Byte High

PEC0

PEC1

Shift Byte 1

…

Shift Byte n

Table 37. Address Read Command

8

CMD0

CMD1

PEC0

PEC1

Data Byte Low

Data Byte High

PEC0

PEC1

Table 38. Broadcast Command Format

NAME

CMD0

CMD1

RD/WR

WR

BIT 7

0

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

BIT 2

BIT 1

BIT 0

CC[8]

CC[0]

0

CC[10]

CC[2]

CC[9]

CC[1]

WR

CC[7]

CC[6]

CC[5]

CC[4]

CC[3]

Table 39. Address Command Format

NAME

CMD0

RD/WR

WR

BIT 7

1

BIT 6

a3*

BIT 5

a2*

BIT 4

a1*

BIT 3

a0*

BIT 2

CC[10]

CC[2]

BIT 1

CC[9]

CC[1]

BIT 0

CC[8]

CC[0]

CMD1

WR

CC[7]

CC[6]

CC[5]

CC[4]

CC[3]

*ax is Address Bit x

Rev. A

60

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Commands

Table 40 lists all the commands and its options for both

LTC6810-1 and LTC6810-2.

Table 40. Command Codes

COMMAND DESCRIPTION

NAME

CC[10:0] — COMMAND CODE

10

9

8

7

6

5

4

3

2

1

0

Write Configuration

Register Group

WRCFG

RDCFG

0

1

Read Configuration

Register Group

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Write Control Register Group WRSCTRL*

(PWM and S)

0

1

0

Read Control Register Group RDSCTRL*

(PWM and S)

0

1

0

Write PWM Register Group

(PWM and S)

WRPWM*

RDPWM*

RDCVA

RDCVB

RDSA

0

1

0

Read PWM Register Group

(PWM and S)

0

1

0

1

0

Read Cell Voltage

Register Group A

0

1

0

Read Cell Voltage

Register Group B

0

1

0

Read S Voltage

Register Group A

0

Read S Voltage

Register Group B

RDSB

0

1

0

Read Auxiliary

Register Group A

RDAUXA

RDAUXB

RDSTATA

RDSTATB

RDSID

0

1

0

Read Auxiliary

Register Group B

0

1

0

Read Status

Register Group A

0

1

0

Read Status

Register Group B

0

1

0

1

0

Read Serial ID

Register Group

1

0

Start Cell Voltage ADC

Conversion and Poll Status

ADCV

MD[1] MD[0]

1

DCP

0

CH[2]

1

CH[1]

1

CH[0]

1

Start Open Wire ADC

Conversion and Poll Status

ADOW

PUP

ST[1]

1

ST[0]

1

Start Self-Test Cell Voltage

Conversion and Poll Status

CVST

Start GPIOs/Cell 0/REF2 ADC

Conversion and Poll Status

ADAX

0

CHG[2] CHG[1] CHG[0]

Start GPIOs/Cell 0/REF2

ADC Conversion with Digital

Redundancy and Poll Status

ADAXD

0

Rev. A

61

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

COMMAND DESCRIPTION

NAME

CC[10:0] — COMMAND CODE

10

9

8

7

6

5

4

3

2

1

0

Start GPIOs/Cell 0/REF2 ADC

Open Wire Conversion

AXOW

AXST

1

0

MD[1] MD[0]

PUP

0

1

0

CHG[2] CHG[1] CHG[0]

Start Self-Test GPIOs/Cell 0/

REF2 Conversion and Poll

Status

1

0

MD[1] MD[0]

ST[1]

ST[0]

0

1

Start Status Group ADC

ADSTAT

1

0

MD[1] MD[0]

1

0

1

0

1

CHST[2] CHST[1] CHST[0]

Conversion and Poll Status

Start Status Group ADC

Conversion with Digital

Redundancy and Poll Status

ADSTATD

Start Self-Test Status Group

Conversion and Poll Status

STATST

ADCVAX

1

0

MD[1] MD[0]

ST[1]

1

ST[0]

1

0

1

Start Combined Cell Voltage

and Cell 0, GPIO1 Conversion

and Poll Status

DCP

Start Combined Cell Voltage

and SC Conversion and Poll

Status

ADCVSC

1

0

MD[1] MD[0]

1

DCP

0

1

Clear Cell Voltage

Register Group

CLRCELL

CLRAUX

1

0

1

0

1

0

Clear Auxiliary

Register Group

Clear Status Register Group

Poll ADC Conversion Status

CLRSTAT

PLADC

1

0

1

0

1

0

1

0

1

Diagnose MUX and Poll

Status

DIAGN

Write COMM

WRCOMM

RDCOMM

1

0

1

0

1

0

Register Group

Read COMM

Register Group

2

Start I C/SPI Communication STCOMM

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Mute Discharge

MUTE

Unmute Discharge

UNMUTE

*The WRSCTRL and WRPWM and RDSCTRL and RDPWM commands all access the same PWM Register Group. The WRSCTRL and RDSCTRL

commands are provided for compatibility with other LTC681x devices in a daisy-chain.

Table 41. Command Bit Descriptions

NAME

DESCRIPTION

VALUES

MD ADCOPT(CFGR0[0]) = 0

ADCOPT (CFGR0[0]) = 1

1kHz Mode

00

01

10

11

422Hz Mode

MD[1:0] ADC Mode

27 kHz Mode (Fast)

7 kHz Mode (Normal)

26 Hz Mode (Filtered)

14 kHz Mode

3 kHz Mode

2 kHz Mode

Rev. A

62

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

NAME

DESCRIPTION

VALUES

DCP

0

DCP

Discharge Permitted

Discharge Not Permitted

Discharge Permitted

1

Total Conversion Time in 8 ADC Modes

CH

000

001

010

011

100

101

110

PUP

0

27kHz

14kHz

699µs

7kHz

3kHz

2kHz

1kHz

422Hz

12ms

26Hz

All Cells

Cell 1

Cell 2

Cell 3

Cell 4

Cell 5

Cell 6

524µs

1.2ms

1.9ms

3.3ms

6.1ms

201ms

Cell Selection for ADC

Conversion

CH[2:0]

200µs

229µs

404µs

520µs

753µs

1.2ms

2.1ms

34ms

Pull-Up/Pull-Down Current

for Open Wire Conversions

PUP

Pull-Down Current

Pull-Up Current

1

Self Test Conversion Result

7kHz 3kHz 2kHz 1kHz

ST

01

10

27kHz

14kHz

422Hz

26Hz

ST[1:0] Self Test Mode Selection

Self Test 1

Self test 2

0x9565 0x9553 0x9555 0x9555 0x9555 0x9555 0x9555 0x9555

0x6A9A 0x6AAC 0x6AAA 0x6AAA 0x6AAA 0x6AAA 0x6AAA 0x6AAA

Total Conversion Time in the 8 ADC Modes

CHG

000

27kHz

14kHz

7kHz

3kHz

2kHz

1kHz

422Hz

26Hz

S0, GPIO 1–4,

2nd Reference

521µs

695µs

1.2ms

1.9ms

3.3ms

6.0ms

12ms

183ms

001 S0

GPIO Selection for ADC

CHG[2:0]

Conversion

010 GPIO 1

011 GPIO 2

100 GPIO 3

101 GPIO 4

110 2nd Reference

200µs

229µs

403µs

520µs

752µs

1.2ms

2.1ms

34ms

Total Conversion Time in 8 ADC Modes

CHST

27kHz

741µs

14kHz

858µs

7kHz

3kHz

2kHz

1kHz

422Hz

8.5ms

26Hz

SOC, ITMP,

VA, VD

000

1.6ms

2.0ms

3.0ms

4.8ms

134ms

CHST[2:0]* Status Group Selection

001 SC

010 ITMP

011 VA

100 VD

200µs

229µs

403µs

520µs

752µs

1.2ms

2.1ms

34ms

*Note: Valid options for CHST in ADSTAT command are 0–4. If CHST is set to 5/6 in ADSTAT command, the LTC6810 treats it like ADAX command with

CHG =5/6.

Rev. A

63

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Memory Map

Table 42. Configuration Register Group

REGISTER

CFGR0

CFGR1

CFGR2

CFGR3

CFGR4

CFGR5

RD/WR

BIT 7

RSVD

BIT 6

GPIO4

BIT 5

GPIO3

VUV[5]

VOV[1]

VOV[9]

DCC6

BIT 4

GPIO2

VUV[4]

VOV[0]

VOV[8]

DCC5

BIT 3

GPIO1

VUV[3]

VUV[11]

VOV[7]

DCC4

BIT 2

REFON

VUV[2]

VUV[10]

VOV[6]

DCC3

BIT 1

DTEN

BIT 0

ADCOPT

VUV[0]

VUV[8]

VOV[4]

DCC1

VUV[7]

VOV[3]

VOV[11]

DCC0

VUV[6]

VOV[2]

VOV[10]

MCAL

VUV[1]

VUV[9]

VOV[5]

DCC2

DCTO[3]

DCTO[2]

DCTO[1]

DCTO[0]

SCONV

FDRF

DIS_RED

DTMEN

Table 43. Cell Voltage Register Group A

REGISTER

CVAR0

CVAR1

CVAR2

CVAR3

CVAR4

CVAR5

RD/WR

RD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

C1V[7]

C1V[15]

C2V[7]

C2V[15]

C3V[7]

C3V[15]

C1V[6]

C1V[14]

C2V[6]

C2V[14]

C3V[6]

C3V[14]

C1V[5]

C1V[13]

C2V[5]

C2V[13]

C3V[5]

C3V[13]

C1V[4]

C1V[12]

C2V[4]

C2V[12]

C3V[4]

C3V[12]

C1V[3]

C1V[11]

C2V[3]

C2V[11]

C3V[3]

C3V[11]

C1V[2]

C1V[10]

C2V[2]

C2V[10]

C3V[2]

C3V[10]

C1V[1]

C1V[9]

C2V[1]

C2V[9]

C3V[1]

C3V[9]

C1V[0]

C1V[8]

C2V[0]

C2V[8]

C3V[0]

C3V[8]

RD

Table 44. Cell Voltage Register Group B

REGISTER

CVBR0

CVBR1

CVBR2

CVBR3

CVBR4

CVBR5

RD/WR

RD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

C4V[7]

C4V[15]

C5V[7]

C5V[15]

C6V[7]

C6V[15]

C4V[6]

C4V[14]

C5V[6]

C5V[14]

C6V[6]

C6V[14]

C4V[5]

C4V[13]

C5V[5]

C5V[13]

C6V[5]

C6V[13]

C4V[4]

C4V[12]

C5V[4]

C5V[12]

C6V[4]

C6V[12]

C4V[3]

C4V[11]

C5V[3]

C5V[11]

C6V[3]

C6V[11]

C4V[2]

C4V[10]

C5V[2]

C5V[10]

C6V[2]

C6V[10]

C4V[1]

C4V[9]

C5V[1]

C5V[9]

C6V[1]

C6V[9]

C4V[0]

C4V[8]

C5V[0]

C5V[8]

C6V[0]

C6V[8]

RD

Table 45. Auxiliary Register Group A

REGISTER

AVAR0

AVAR1

AVAR2

AVAR3

AVAR4

AVAR5

RD/WR

RD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

S0V[7]

S0V[15]

G1V[7]

G1V[15]

G2V[7]

G2V[15]

S0V[6]

S0V[14]

G1V[6]

G1V[14]

G2V[6]

G2V[14]

S0V[5]

S0V[13]

G1V[5]

G1V[13]

G2V[5]

G2V[13]

S0V[4]

S0V[12]

G1V[4]

G1V[12]

G2V[4]

G2V[12]

S0V[3]

S0V[11]

G1V[3]

G1V[11]

G2V[3]

G2V[11]

S0V[2]

S0V[10]

G1V[2]

G1V[10]

G2V[2]

G2V[10]

S0V[1]

S0V[9]

G1V[1]

G1V[9]

G2V[1]

G2V[9]

S0V[0]

S0V[8]

G1V[0]

G1V[8]

G2V[0]

G2V[8]

RD

Rev. A

64

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Table 46. Auxiliary Register Group B

REGISTER

AVBR0

AVBR1

AVBR2

AVBR3

AVBR4

AVBR5

RD/WR

RD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

G3V[7]

G3V[15]

G4V[7]

G4V[15]

REF[7]

G3V[6]

G3V[14]

G4V[6]

G4V[14]

REF[6]

G3V[5]

G3V[13]

G4V[5]

G4V[13]

REF[5]

G3V[4]

G3V[12]

G4V[4]

G4V[12]

REF[4]

G3V[3]

G3V[11]

G4V[3]

G4V[11]

REF[3]

G3V[2]

G3V[10]

G4V[2]

G4V[10]

REF[2]

G3V[1]

G3V[9]

G4V[1]

G4V[9]

REF[1]

REF[9]

G3V[0]

G3V[8]

G4V[0]

G4V[8]

REF[0]

REF[8]

RD

REF[15]

REF[14]

REF[13]

REF[12]

REF[11]

REF[10]

Table 47. Status Register Group A

REGISTER

STAR0

STAR1

STAR2

STAR3

STAR4

STAR5

RD/WR

RD

BIT 7

SC[7]

BIT 6

SC[6]

BIT 5

SC[5]

BIT 4

SC[4]

BIT 3

SC[3]

BIT 2

SC[2]

BIT 1

SC[1]

BIT 0

SC[0]

RD

SC[15]

ITMP[7]

ITMP[15]

VA[7]

SC[14]

ITMP[6]

ITMP[14]

VA[6]

SC[13]

ITMP[5]

ITMP[13]

VA[5]

SC[12]

ITMP[4]

ITMP[12]

VA[4]

SC[11]

ITMP[3]

ITMP[11]

VA[3]

SC[10]

ITMP[2]

ITMP[10]

VA[2]

SC[9]

SC[8]

RD

ITMP[1]

ITMP[9]

VA[1]

ITMP[0]

ITMP[8]

VA[0]

RD

VA[15]

VA[14]

VA[13]

VA[12]

VA[11]

VA[10]

VA[9]

VA[8]

Table 48. Status Register Group B

REGISTER

STBR0

STBR1

STBR2

STBR3

STBR4

STBR5

RD/WR

RD

BIT 7

VD[7]

VD[15]

C4OV

BIT 6

VD[6]

VD[14]

C4UV

BIT 5

VD[5]

VD[13]

C3OV

BIT 4

VD[4]

VD[12]

C3UV

BIT 3

VD[3]

VD[11]

C2OV

C6OV

RSVD

BIT 2

VD[2]

VD[10]

C2UV

C6UV

RSVD

BIT 1

VD[1]

BIT 0

VD[0]

VD[8]

C1UV

C5UV

RSVD

THSD

RD

VD[9]

RD

C1OV

RD

RSVD

REV[3]

RSVD

REV[2]

RSVD

REV[1]

MUTE

RSVD

REV[0]

C5OV

RD

RSVD

RD

MUXFAIL

Table 49. Redundant S Voltage Register Group A

REGISTER

CVCR0

CVCR1

CVCR2

CVCR3

CVCR4

CVCR5

RD/WR

RD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

S1V[7]

S1V[15]

S2V[7]

S2V[15]

S3V[7]

S3V[15]

S1V[6]

S1V[14]

S2V[6]

S2V[14]

S3V[6]

S3V[14]

S1V[5]

S1V[13]

S2V[5]

S2V[13]

S3V[5]

S3V[13]

S1V[4]

S1V[12]

S2V[4]

S2V[12]

S3V[4]

S3V[12]

S1V[3]

S1V[11]

S2V[3]

S2V[11]

S3V[3]

S3V[11]

S1V[2]

S1V[10]

S2V[2]

S2V[10]

S3V[2]

S3V[10]

S1V[1]

S1V[9]

S2V[1]

S2V[9]

S3V[1]

S3V[9]

S1V[0]

S1V[8]

S2V[0]

S2V[8]

S3V[0]

S3V[8]

RD

Rev. A

65

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Table 50. Redundant S Voltage Register Group B

REGISTER

CVDR0

CVDR1

CVDR2

CVDR3

CVDR4

CVDR5

RD/WR

RD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

S4V[7]

S4V[15]

S5V[7]

S5V[15]

S6V[7]

S6V[15]

S4V[6]

S4V[14]

S5V[6]

S5V[14]

S6V[6]

S6V[14]

S4V[5]

S4V[13]

S5V[5]

S5V[13]

S6V[5]

S6V[13]

S4V[4]

S4V[12]

S5V[4]

S5V[12]

S6V[4]

S6V[12]

S4V[3]

S4V[11]

S5V[3]

S5V[11]

S6V[3]

S6V[11]

S4V[2]

S4V[10]

S5V[2]

S5V[10]

S6V[2]

S6V[10]

S4V[1]

S4V[9]

S5V[1]

S5V[9]

S6V[1]

S6V[9]

S4V[0]

S4V[8]

S5V[0]

S5V[8]

S6V[0]

S6V[8]

RD

Table 51. COMM Register Group

REGISTER

COMM0

COMM1

COMM2

COMM3

COMM4

COMM5

RD/WR

BIT 7

ICOM0[3]

D0[3]

BIT 6

ICOM0[2]

D0[2]

BIT 5

ICOM0[1]

D0[1]

BIT 4

ICOM0[0]

D0[0]

BIT 3

D0[7]

BIT 2

D0[6]

BIT 1

D0[5]

BIT 0

D0[4]

FCOM0[3]

D1[7]

FCOM0[2]

D1[6]

FCOM0[1]

D1[5]

FCOM0[0]

D1[4]

ICOM1[3]

D1[3]

ICOM1[2]

D1[2]

ICOM1[1]

D1[1]

ICOM1[0]

D1[0]

FCOM1[3]

D2[7]

FCOM1[2]

D2[6]

FCOM1[1]

D2[5]

FCOM1[0]

D2[4]

ICOM2[3]

D2[3]

ICOM2[2]

D2[2]

ICOM2[1]

D2[1]

ICOM2[0]

D2[0]

FCOM2[3]

FCOM2[2]

FCOM2[1]

FCOM2[0]

Table 52. PWM Register Group

REGISTER

SCTL0

SCTL1

SCTL2

SCTL3

SCTL4

SCTL5

RD/WR

BIT 7

PWM2[3]

PWM4[3]

PWM6[3]

RSVD

BIT 6

PWM2[2]

PWM4[2]

PWM6[2]

RSVD

BIT 5

PWM2 [1]

PWM4[1]

PWM6[1]

RSVD

BIT 4

PWM2[0]

PWM4[0]

PWM6[0]

RSVD

BIT 3

PWM1[3]

PWM3[3]

PWM5[3]

RSVD

BIT 2

PWM1[2]

PWM3[2]

PWM5[2]

RSVD

BIT 1

PWM1[1]

PWM3[1]

PWM5[1]

RSVD

BIT 0

PWM1[0]

PWM3[0]

PWM5[0]

RSVD

Table 53. Serial ID Register Group

REGISTER

SIDR0

SIDR1

SIDR2

SIDR3

SIDR4

SIDR5

RD/WR

RD

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SID[7]

SID[6]

SID[5]

SID[4]

SID[3]

SID[2]

SID[1]

SID[0]

RD

SID[15]

SID[23]

SID[31]

SID[39]

SID[47]

SID[14]

SID[22]

SID[30]

SID[38]

SID[46]

SID[13]

SID[21]

SID[29]

SID[37]

SID[45]

SID[12]

SID[20]

SID[28]

SID[36]

SID[44]

SID[11]

SID[19]

SID[27]

SID[35]

SID[43]

SID[10]

SID[18]

SID[26]

SID[34]

SID[42]

SID[9]

SID[8]

RD

SID[17]

SID[25]

SID[33]

SID[41]

SID[16]

SID[24]

SID[32]

SID[40]

RD

Rev. A

66

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

Table 54. Memory Bit Descriptions

NAME

DESCRIPTION

VALUES

GPIOx

GPIOx Pin

Control

Write: 0 -> GPIOx pin pull down ON; 1-> GPIOx pin pull down OFF

Read: 0 -> GPIOx pin at logic 0; 1 -> GPIOx pin at logic 1

REFON

DTEN

References

Powered Up

1 -> References remain powered up until watchdog time out

0 -> References shut down after conversions

Discharge Timer 1 -> Enables the Discharge Timer for discharge switches

Enable

0 -> Disables Discharge Timer

ADCOPT

VUV

ADC Mode

Option Bit

ADCOPT: 0 -> Selects Modes 27kHz, 7kHz, 422Hz or 26Hz with MD[1:0] bits in ADC conversion commands.

1 -> Selects Modes 14kHz, 3kHz, 1kHz or 2kHz with MD[1:0] bits in ADC conversion commands.

Undervoltage

Comparison

Voltage*

Comparison voltage = VUV • 16 • 100µV

Default: VUV = 0x000

VOV

Overvoltage

Comparison

Voltage*

Comparison voltage = VOV • 16 • 100µV

Default: VUV = 0x000

MCAL

Enables

1 -> Enables multicalibration during ADC conversions, for backwards compatibility with 6811/6812/6810.

Multi-Calibration Defaults to 0, single calibration during ADC.

DCC[x]

Discharge

Cell x

x = 1 to 6 1 -> Turn ON shorting switch for Cell x, S[x] to S[x–1]

0 -> Turn OFF shorting switch for Cell x, S[x] to S[x–1] (default)

x = 0

1 -> Turn ON S0 pulldown for discharging optional 7th cell

0 -> Turn OFF S0 pulldown (default)

DCTO

Discharge Time

Out Value

DCTO

0

1

2

1

2

3

2

3

4

3

4

5

4

5

6

5

6

7

10

7

8

15

8

9

20

9

A

30

A

B

40

B

C

60

C

D

75

D

E

F

(Write)

Time

(min)

Disabled 0.5

90 120

DCTO

(Write)

0

1

E

F

Time

Left

(min)

Disabled

or Time

Out

0

0.5

to

1

to

2

to

3

to

4

to

5

to

10

to

15

to

20

to

30

to

40

to

60

to

75

to

90

to

0.5

90 120

SCONV

Enable Cell

1 -> Enables redundant measurements of the cell voltages using the S pins

0 -> Disables redundant measurements of the cell voltages

Measurement

Redundancy

Using S Pins

FDRF

Force Digital

Redundancy

Failure

1 -> Forces the digital redundancy comparison for A/D conversions to fail

0 -> Enables the normal redundancy comparison

DIS_RED

DTMEN

CxV

Disable Digital

Redundancy

Check

1 -> Disables the digital redundancy comparison for A/D conversions

0 -> Enables the digital redundancy comparison for A/D conversions

Enable

1 -> Enables the Discharge Timer Monitor function if the DTEN pin is asserted.

Discharge Timer 0 -> Disables the Discharge Timer Monitor function. The normal Discharge Timer function will be enabled if DTEN pin is

Monitor

asserted.

Cell x Voltage*

x = 1 to 6 16 bit ADC measurement value for Cell x

Cell Voltage for Cell x = CxV • 100µV

CxV is reset to 0xFFFF on power up and after Clear command

–

S0V

S0 Voltage*

16 bit ADC measurement value for S0 with respect to V

S0 Voltage = S0V • 100µV

S0V is reset to 0xFFFF on power up and after Clear command

Rev. A

67

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

NAME

DESCRIPTION

VALUES

GxV

GPIO x Voltage* x = 1 to 4 16 bit ADC measurement value for GPIOx

Voltage for GPIOx = GxV • 100µV

GxV is reset to 0xFFFF on power up and after Clear command

REF

2nd Reference

Voltage*

16 bit ADC measurement value for 2nd Reference

Voltage for 2nd Reference = REF • 100µV

Normal range is within 2.99V to 3.01V considering data sheet limits, hysteresis and long term drift

SC

Sum of All Cells

Measurement*

16 bit ADC measurement value of the Sum of All Cell Voltages

Sum of All Cells Voltage = SC • 100µV • 10

ITMP

VA

Internal Die

16 bit ADC measurement value of Internal Die temperature

Temperature*

Temperature measurement (ºC) = ITMP • 100µV/7.5mV/ºC – 273ºC

Analog Power

Supply Voltage*

16 bit ADC measurement value of Analog power supply voltage

Analog Power supply voltage = VA • 100µV

The value of VA is set by external components and should be in the range 4.5V to 5.5V for normal operation

VD

Digital Power

Supply Voltage*

16 bit ADC measurement value of Digital power supply voltage

Digital Power supply voltage = VD • 100µV

Normal range is within 2.7V to 3.6V

CxOV

CxUV

Cell ‘x’

x = 1 to 6 Cell voltage compared to VOV comparison voltage

0 -> Cell ‘x’ not flagged for overvoltage condition.

1-> Cell ‘x’ flagged

Overvoltage Flag

Cell ‘x’

Undervoltage

Flag

x = 1 to 6 Cell voltage compared to VUV comparision voltage

0 -> Cell ‘x’ not flagged for under–v

REV

Revision Code

Reserved Bits

Device Revision Code

RSVD

Read: Read back value can be 1 or 0

Read: Read back value is always 0

Read: Read back value is always 1

RSVD0

RSVD1

MUXFAIL

Multiplexer Self Read:

Test Result

0 -> Multiplexer passed self test

1 -> Multiplexer failed self test

THSD

Thermal

Shutdown

Status

Read: 0 -> Thermal shutdown has not occurred 1 -> Thermal shutdown has occurred

THSD bit cleared to ‘0’ on read of Status Register Group B

SxV

Redundant Cell x x = 1 to 6 16 bit redundant ADC measurement value for Cell x

Voltage* via the

S pins

Redundant measurement of Cell Voltage for Cell x = SxV • 100µV

SxV is reset to 0xFFFF on power up and after Clear command

PWMx[x]

PWM Discharge 0000 – Selects 0% Discharge Duty Cycle if Watchdog Timer Has Expired

Control

0001 – Selects 3.3% Discharge Duty Cycle if Watchdog Timer Has Expired

0010 – Selects 6.7% Discharge Duty Cycle if Watchdog Timer Has Expired

…

1110 – Selects 46.7% Discharge Duty Cycle if Watchdog Timer Has Expired

1111 – Selects 50% Discharge Duty Cycle if Watchdog Timer Has Expired

SID[x]

ICOMn

Serial ID

Unique 48-bit serial identification code

Initial

Communication

Control Bits

Write

0110

0001

0000

0111

2

I C

START

STOP

BLANK

1001

NO TRANSMIT

1111

1000

1010

SPI

CSB low

0110

CSB Falling Edge

0001

CSB high

0000

NO TRANSMIT

0111

Read

2

I C

START from Master

0111

STOP from Master

SDA low between bytes SDA high between bytes

SPI

Rev. A

68

For more information www.analog.com

LTC6810-1/LTC6810-2

OPERATION

NAME

DESCRIPTION

VALUES

Data transmitted(received) to(from) I C/SPI slave device

2

Dn

I C/SPI

Communication

Data Byte

FCOMn

Final

Communication

Control Bits

Write

I2C

SPI

I2C

0000

1000

1001

Master ACK

X000

Master NACK

Master NACK + STOP

1001

CSB low

0001

CSB high

Read

0111

1111

0001 1001

ACK from Master ACK from Slave

NACK from Slave ACK from Slave + NACK from Slave +

STOP from Master STOP from Master

SPI

1111

*Voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits.

Rev. A

69

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

PROVIDING DC POWER

2. Internal Regulator

+

The primary supply pin for the LTC6810 is the 5V 0.5V

At low V voltages where there is not enough headroom

V

input pin. There are three ways to generate the V

to regulate the Drive Pin, V

is driven by an internal

REG

REGA

input as follows:

regulator. The Drive pin is designed such that when used

with an external NPN, V will be set to a voltage that

REGA

1. Simple Linear Regulator

is at least 400mV greater than the internal V

voltage.

REGA

This ensures that when the DRIVE pin regulator has suffi-

The DRIVE pin can be used to form a discrete regulator

with the addition of a few external components, as shown

in Figure 36. The DRIVE pin provides a 5.6V output, capa-

ble of sourcing 1mA. When buffered with an NPN transis-

tor, this provides a stable 5V over temperature. The NPN

transistor should be chosen to have a sufficient Beta over

temperature (>40) to supply the necessary supply cur-

cient headroom the internal V

will turn off. The internal

regulator is enabled by applyi^Rn^Eg^Ga^A25µA load on the DRIVE

pin. Connecting a 100k resistor on the DRIVE pin to GND

+

allows the part to work across the entire V supply range.

+

When V is too low, the 100k resistor on the DRIVE pin

pulls enough current to enable the internal regulator that

+

sets V

to about 4.7V. When V is high, the DRIVE pin

REGA

rent. The peak V

current requirement of the LTC6810

REG

sets V_REGAto about 5.1V. The internal regulator is not

capable of sinking current and will shutdown in this case.

approaches 20mA when simultaneously communicating

over isoSPI and making ADC conversions. If the V pin

REG

is required to support any additional load, a transistor with

an even higher beta may be required.

3. External Regulator for Improved Efficiency

For improved efficiency when powering the LTC6810 from

the cell stack, the V

The NPN collector can be powered from any voltage

source that is a minimum 6V above V–. This includes the

cells that are being monitored, or an unregulated power

supply. A 100Ω/100nF RC decoupling network is recom-

mended for the collector power connection to protect the

NPN from transients. The emitter of the NPN should be

bypassed with a 1µF capacitor. Larger capacitance should

be avoided since this will increase the wake-up time of the

LTC6810. Some attention should be given to the thermal

may be powered from a DC/DC

REG

converter, rather than the NPN pass transistor. An ideal

circuit is based on Analog Devices’ LTC3990 step-down

regulator, as shown in Figure 37. A 50Ω resistor is rec-

ommended between the battery stack and the LTC3990

input; this will prevent in-rush current when connecting

to the stack and it will reduce conducted EMI. The EN pin

should be connected to the DRIVE pin which will put the

LTC3990 into a low power state when the LTC6810 is

in the sleep state. In this mode, to avoid any contention

characteristic of the NPN, as there can be significant heat

ing with a high collector voltage.

-

with the internally generated V

, the load current on

REGA

the DRIVE pin should be less than 1µA to ensure that the

internal regulator is disabled.

100Ω

LTC6810

WDT

DRIVE

0.1µF

DXT5551P5

1µF

ꢀ

ꢁꢂ

ꢜ.ꢝꢀ

V

REG

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ꢊ.ꢑꢑꢒꢓ

ꢈꢈꢒꢚ

ꢀ

ꢃꢄꢄꢅꢆ

ꢇꢆꢈꢉꢉꢊ

ꢌꢂꢍꢎꢀꢇꢄ ꢅꢋ

DTEN

ꢁꢂ

V

REF1

ꢀ

Rꢌꢐ

V

ꢝꢀ

ꢡRꢁꢀꢌ

ꢑ.ꢑꢒꢓ

REF2

ꢖꢊꢟA

ꢏꢐ

ꢃꢡ

1µF

GPIO4

ꢑꢑꢔꢓ

ꢠꢞ

1µF

–

V

Rꢆ

ꢓꢃ

ꢑꢑꢒꢓ

–

V

ꢐꢂꢡ

ꢈꢕꢖꢗ

ꢘ ꢙ ꢖꢊꢊꢗꢚꢛ

ꢈꢠꢜꢗ

GPIO3

68101 F36

ꢜꢢꢠꢊꢠ ꢓꢈꢕ

Figure 36. Simple V_REGPower Source Using NPN Pass Transistor

Figure 37. V_REGPowered from Cell Stack with High

Efficiency Regulator

Rev. A

70

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

INTERNAL PROTECTION AND FILTERING

structure is the same. Zener-like suppressors are shown

with their nominal clamp voltage, and the unmarked

diodes exhibit standard PN junction behavior.

Internal Protection Features

The LTC6810 incorporates various ESD safeguards

to ensure robust performance. An equivalent circuit

showing the specific protection structures is shown in

Figure 38. While pins 34 to 39 have different functionality

for the LTC6810-1 and LTC6810-2 variants, the protection

Filtering of Cell and GPIO Inputs

The LTC6810 uses a delta-sigma ADC, which has a delta

sigma modulator followed by a SINC3 finite impulse

response (FIR) digital filter. This greatly relaxes input

filtering requirements. Furthermore, the programmable

oversampling ratio allows the user to determine the best

trade-off between measurement speed and filter cutoff

frequency. Even with this high order low pass filter, fast

transient noise can still induce some residual noise in

measurements, especially in the faster conversion modes.

This can be minimized by adding an RC low pass decou-

pling to each ADC input, which also helps reject potentially

damaging high energy transients. Adding more than about

100Ω to the ADC inputs begins to introduce a systematic

error in the measurement, which can be improved by rais-

ing the filter capacitance or mathematically compensating

in software with a calibration procedure. For situations

that demand the highest level of battery voltage ripple

rejection, grounded capacitor filtering is recommended.

This configuration has a series resistance and capacitors

that decouple HF noise to V–. In systems where noise

is less periodic or higher oversample rates are in use, a

differential capacitor filter structure is adequate. In this

configuration there are series resistors to each input,

but the capacitors connect between the adjacent C pins.

However, the differential capacitor sections interact. As a

result, the filter response is less consistent and results

in less attenuation than predicted by the RC, by approxi-

mately a decade. Note that the capacitors only see one

cell of applied voltage (thus smaller and lower cost) and

tend to distribute transient energy uniformly across the IC

(reducing stress events on the internal protection struc-

ture). Figure 39 shows the two methods schematically.

ADC accuracy varies with R, C as shown in the Typical

Performance curves, but error is minimized if R = 100Ω

and C = 10nF. The GPIO pins will always use a grounded

capacitor configuration because the measurements are

all with respect to V–.

LTC6810

12V

+

V

WDT

SDI

3

42

41

40

39

38

37

36

35

34

33

32

31

30

27

26

25

20

19

18

24V

SDO

C6

S6

C5

S5

C4

S4

C3

S3

C2

S2

C1

S1

C0

S0

IPB/A3

IMB/A2

SCK

4

24V

12V

5

24V

6

24V

12V

CSB

7

24V

ICMP/A1

IBIAS/A0

DRIVE

8

24V

9

10

11

12

13

14

15

16

17

28

29

V

REG

V

REF2

REF1

24V

ISOMD

DTEN

GPIO4

GPIO3

GPIO2

GPIO1

–

V

25Ω

68101 F39

NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 28

Figure 38. Internal ESD Protection Structures of the LTC6810

Rev. A

71

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

100Ω

R

ꢇꢐꢀꢁꢑR

ꢀꢁꢂꢃꢄꢅꢆ

C2

S2

C1

S1

C0

S0

C2

S2

C1

ꢂ

ꢎ

ꢊꢋꢌꢅꢍ

10nF

R

DIS

R

ꢒꢐꢎꢂꢓARꢔꢑ

ꢊꢋꢌꢅꢍ

ꢂ

ꢇꢐꢀꢁꢑR

100Ω

R

ꢂ

ꢎ

ꢊꢋꢍ

LTC6810

R

DIS

ꢒꢐꢎꢂꢓARꢔꢑ

ꢊꢋꢍ

S1

C0

S0

ꢂ

ꢇꢐꢀꢁꢑR

100Ω

ꢂ

ꢎ

ꢊꢋꢏꢅꢍ

R

DIS

ꢒꢐꢎꢂꢓARꢔꢑ

ꢊꢋꢏꢅꢍ

–

V

ꢃꢄꢅꢆꢅ ꢇꢈꢅꢉ

68101 F39

GROUNDED CAPACITOR FILTER

DIFFERENTIAL CAPACITOR FILTER

a)

Figure 39. Input Filter Structure Configurations

ꢀꢁꢂꢃꢄꢅꢆ

ꢂ

ꢎ

ꢂ

ꢎ

ꢊꢋꢌꢅꢍ

R

ꢐꢑꢎꢂꢒARꢓꢔ

ꢊꢋꢌꢅꢍ

CELL BALANCING

The LTC6810 includes signals (pins S0 through S6) that

can be used to balance cells with internal or external

discharge. Cells can be discharged using the internal

N-channel NMOS at the S pins, or the S pins can act

as digital outputs to drive external transistors. Figure 40

shows an example of internal cell balancing using

the LTC6810.

ꢂ

ꢎ

ꢂ

ꢎ

ꢊꢋꢍ

ꢐꢑꢎꢂꢒARꢓꢔ

ꢊꢋꢍ

ꢂ

ꢎ

ꢂ

ꢎ

ꢊꢋꢏꢅꢍ

ꢐꢑꢎꢂꢒARꢓꢔ

ꢊꢋꢏꢅꢍ

ꢃꢄꢅꢆꢅ ꢇꢈꢅꢉ

Choosing a Discharge Resistor

b)

When sizing the balancing resistor it is important to know

the typical battery imbalance and the allowable time for

cell balancing. In most small battery applications it is rea-

sonable for the balancing circuitry to be able to correct

for a 5% SOC (State Of Charge) error with 5 hours of

balancing. For example a 5AHr battery with a 5% SOC

imbalance will have approximately 250mAHrs of imbal-

ance. Using a 50mA balancing current this could be cor-

rected in 5 hours. With a 100mA balancing current, the

error would be corrected in 2.5Hrs. In systems with very

large batteries it becomes difficult to use passive balanc-

ing to correct large SOC imbalances in short periods of

time. The excessive heat created during balancing gener-

ally limits the balancing current. In large capacity battery

Figure 40. Internal Discharge Circuits

applications if short balancing times are required an active

balancing solution should be considered. When choosing

a balance resistor the following equations can be used to

help determine a resistor value:

%SOC_Imbalance • BatteryCapacity

Balance Current =

Number of Hours to Balance

Nominal Cell Voltage

Balance Resistor =

Balance Current

Rev. A

72

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

With passive balancing, if one cell in a series stack

becomes overcharged, an S output can slowly discharge

this cell by connecting it to a resistor. Each S output is

connected to an internal N-channel MOSFET with a maxi-

mum on resistance of 4Ω. An external resistor should be

connected in series with these MOSFETs to allow most of

the heat to be dissipated outside of the LTC6810 package,

as illustrated in Figure 40.

Figure 40b shows the discharge current path thru the

internal discharge switches. Asserting adjacent discharge

switches will result in a current path shown on the right

in Figure 40b. The LTC6810 does not allow adjacent

discharge switches to be asserted, so the WRFG command

will not be executed if adjacent DCC bits in the CONFIG

register are asserted. The current path shown at the right

of Figure 40b shows that if adjacent discharges switches

were permitted to be on, discharge current would flow

through the series combination of cells instead of the

individual cells.

Cell Balancing with Internal MOSFETs

The internal discharge switches (MOSFETs) S1 through

S6 can be used to passively balance cells as shown in

Figure 40a with balancing current of 150mA or less.

Balancing current larger than 150mA is not recommended

for the internal switches due to excessive die heating.

When discharging cells with the internal discharge

switches, the die temperature should be monitored.

Cell Balancing with External Transistors

For applications that require balancing currents above

150mA, the S outputs can be used to control external

transistors. The S pins can act as digital outputs suitable

for driving the gate of an external MOSFET or the base

of an external NPN as illustrated in Figure 41. Figure 41

shows external transistor circuits that include RC filtering.

100Ω

C2

10nF

R

DIS

LTC6810

NPN

S2

C1

S1

C0

S0

S2

C1

S1

C0

S0

1k

9.1V

1k

B1

100Ω

10nF

DIS

1k

9.1V

B2

10nF

DIS

Q3

NPN

1k

9.1V

–

V

68101 F41

Figure 41. External Discharge Circuit

Rev. A

73

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

Table 55. Discharge Control During an ADCV Command with DCP = 0

CELLMEASUREMENTPERIODS

CELLCALIBRATIONPERIODS

CELL2 CELL3 CELL4 CELL5

CELL1

CELL2

CELL3

CELL4

CELL5

CELL6

CELL1

tot

CELL6

tot

DISCHARGE

t tot

0

t

1M

tot

t

2M

tot

t

tot

t

4M

tot

t

tot

t

tot

t

tot

t

tot

t

tot

t

1M

2M

3M

4M

5M

6M

1C

2C

3C

4C

5C

6C

S1

S2

S3

S4

S5

S6

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

DISCHARGE CONTROL DURING CELL

MEASUREMENTS

command. This allows the cell voltage to settle before

any measurement is taken. After the cell conversion com-

pletes an UNMUTE can be sent to re-enable all discharge

transistors that were previously ON. Using this method

maximizes the measurement accuracy with a very small

time penalty.

If the discharge permitted (DCP) bit is high at the time of

a cell measurement command, the S pin discharge states

do not change during cell measurements. However, if the

DCP bit is low, S pin discharge states will be disabled

while the corresponding cell or adjacent cells are being

measured. If using an external discharge transistor, the

relatively low 1kΩ impedance of the internal LTC6810

PMOS transistors should allow the discharge currents

to fully turn off before the cell measurement. Table 55

illustrates the ADCV command with DCP = 0. In this

table, OFF indicates that the S pin discharge is forced

off irrespective of the state of the corresponding DCC[x]

bit. ON indicates that the S pin discharge will remain on

during the measurement period if it was ON prior to the

measurement command.

Method to Verify Discharge Circuits

When using the internal and external discharge feature,

the ability to verify the discharge functionality can be

verified in software. The discharge circuits are shown in

Figures 40 and 41. The functionality of the discharge cir-

cuits can be verified by implementing a redundant S pin

measurement and comparing it to a C pin measurement.

The S pins on the LTC6810 have two purposes, to pro-

vide internal discharge or turn on the external discharge

device but also to allow for a redundant cell measure-

ment. Asserting the SCONV bit in the config register will

enable the redundant S pin cell measurements. The S pin

measurements taken when the discharge is on require

that the discharge permit bit (DCP) be set. The S pin

measurements when discharge is on will be a function of

the external discharge resistors but will generally be sub-

stantially less than C pin measurements. The resistance

of the internal discharge FET is approximately 10Ω, if the

external discharge resistor in Figure 40 is also 10Ω, the

S pin measurement when discharge is on will be 1/3 of

the C pin measurement.

In some cases it is not possible for the automatic dis-

charge control to eliminate all measurement error caused

by running the discharges. This is due to the discharge

transistor not turning off fast enough for the cell voltage

to completely settle before the measurement starts. For

the best measurement accuracy when running discharge,

the MUTE and UNMUTE commands should be used. The

MUTE command can be issued to temporarily disable

all discharge transistors before the ADCV command is

issued. After issuing a MUTE command a delay of roughly

50µS should be issued before sending a ADC conversion

Rev. A

74

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

Seven Cell Application with Redundant Measurement

is added to the C0 pin as shown in Figure 42. A redundant

measurement can be made by with the S0 pin. Asserting

the SCONV bit in the configuration register and using the

ADCVAX command will combine the six cell measure-

ments with redundancy along with measurements of S0

and GPIO1. Figure 43 shows the seven cell application

where the S pins are used to drive the gates of external

MOSFETs. An external PFET is used to discharge Cell 0.

The LTC6810 has the ability to measure an additional sev-

enth cell with redundancy and internal discharge capa-

–

bility. In six cell applications C0 is connected to V . An

additional seventh cell, Cell 0, can be connected between

–

C0 and V as shown in Figure 42. The primary cell mea-

surement is done by connecting GPIO1 to C0 and using

the ADAX command to measure Cell 0. External filtering

R

ꢇꢍꢀꢁꢎR

ꢀꢁꢂꢃꢄꢅꢆ

ꢔ

ꢍ

ꢂꢉ

ꢊꢉ

R

ꢇꢏꢀꢁꢐR

R

ꢕꢍꢊ

ꢂꢃ

ꢊꢃ

ꢂ

ꢇꢍꢀꢁꢎR

R

ꢑꢏꢊꢂꢒARꢓꢐ

ꢉꢏꢐꢆꢆꢉꢑꢒ

ꢂꢐꢀꢀꢃ

ꢂꢐꢀꢀꢋ

ꢂꢐꢀꢀꢈ

ꢂꢐꢀꢀꢉ

ꢂꢐꢀꢀꢌ

ꢂꢐꢀꢀꢅ

ꢂꢐꢀꢀꢆ

ꢂꢎꢀꢀꢉ

ꢂꢎꢀꢀꢅ

ꢂꢎꢀꢀꢆ

ꢂ

ꢇꢏꢀꢁꢐR

ꢅꢓ

ꢇꢏꢀꢁꢐR

ꢂꢋ

ꢊꢋ

ꢔ.ꢅꢋ

ꢑꢏꢊꢂꢒARꢓꢐ

R

ꢇꢍꢀꢁꢎR

ꢂ

R

ꢇꢏꢀꢁꢐR

ꢂꢅ

ꢊꢅ

ꢂꢈ

ꢊꢈ

R

ꢕꢍꢊ

ꢑꢏꢊꢂꢒARꢓꢐ

ꢂ

R

ꢇꢏꢀꢁꢐR

ꢉꢏꢐꢆꢆꢉꢑꢒ

ꢂꢉ

ꢊꢉ

ꢅꢓ

ꢑꢏꢊꢂꢒARꢓꢐ

ꢔ.ꢅꢋ

ꢂ

ꢇꢏꢀꢁꢐR

ꢂꢌ

ꢊꢌ

R

ꢇꢍꢀꢁꢎR

ꢑꢏꢊꢂꢒARꢓꢐ

ꢂꢆ

ꢊꢆ

R

ꢕꢍꢊ

ꢂ

R

ꢇꢏꢀꢁꢐR

ꢂꢅ

ꢊꢅ

ꢉꢏꢐꢆꢆꢉꢑꢒ

ꢑꢏꢊꢂꢒARꢓꢐ

ꢅꢓ

ꢂ

ꢖꢗꢍꢘꢅ

ꢇꢏꢀꢁꢐR

ꢂꢆ

ꢊꢆ

ꢕꢍꢊ

ꢑꢏꢊꢂꢒARꢓꢐ

ꢓꢕꢏꢖꢅ

Rꢙꢚꢆꢛꢆꢛꢗꢖꢕ

ꢌ

ꢂ

ꢇꢏꢀꢁꢐR

ꢎ

ꢋ

ꢍ

ꢃꢄꢅꢆꢅ ꢇꢈꢉ

ꢃꢄꢅꢆꢅ ꢇꢈꢈ

Figure 42. Seven Cell with Internal Discharge

Figure 43. Seven Cell with External Discharge

Rev. A

75

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

DIGITAL COMMUNICATIONS

The C code below provides a simple implementation of

a lookup table derived PEC calculation method. There

are two functions. The first function init_PEC15_Table()

should only be called once when the microcontroller starts

and will initialize a PEC15 table array called pec15Table[].

This table will be used in all future PEC calculations. The

PEC15 table can also be hard coded into the microcon-

troller rather than running the init_PEC15_Table() func-

tion at startup. The pec15() function calculates the PEC

and will return the correct 15 bit PEC for byte arrays of

any given length.

PEC Calculation

The Packet Error Code (PEC) can be used to ensure that

the serial data read from the LTC6810 is valid and has not

been corrupted. This is a critical feature for reliable com-

munication, particularly in environments of high noise.

The LTC6810 requires that a PEC be calculated for all

data being read from and written to the LTC6810. For

this reason it is important to have an efficient method for

calculating the PEC.

/************************************

Permission to freely use, copy, modify, and distribute this software for any

purpose with or without fee is hereby granted, provided that the above

copyright notice and this permission notice appear in all copies:

THIS SOFTWARE IS PROVIDED “AS IS” AND LTC DISCLAIMS ALL WARRANTIES

INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO

EVENT SHALL LTC BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL

DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM ANY USE OF SAME, INCLUDING

ANY LOSS OF USE OR DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE

OR OTHER TORTUOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR

PERFORMANCE OF THIS SOFTWARE.

***********************************************************/

int16 pec15Table[256];

int16 CRC15_POLY = 0x4599;

void init_PEC15_Table()

{

for (int i = 0; i < 256; i++)

{

remainder = i << 7;

for (int bit = 8; bit > 0; --bit)

{

if (remainder & 0x4000)

{

remainder = ((remainder << 1));

remainder = (remainder ^ CRC15_POLY)

}

else

{

remainder = ((remainder << 1));

}

pec15Table[i] = remainder&0xFFFF;

}

unsigned int16 pec15 (char *data , int len)

{

int16 remainder,address;

remainder = 16;//PEC seed

for (int i = 0; i < len; i++)

{

address = ((remainder >> 7) ^ data[i]) & 0xff;//calculate PEC table address

remainder = (remainder << 8 ) ^ pec15Table[address];

}

return (remainder*2);//The CRC15 has a 0 in the LSB so the final value must be multiplied by 2

}

Rev. A

76

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

isoSPI IBIAS and ICMP Setup

Select I and K (Signal Amplitude V to Receiver input

B A

threshold ratio) according to the application:

The LTC6810 allows the isoSPI links of each application to

be optimized for power consumption or for noise immu-

nity. The power and noise immunity of an isoSPI system is

determined by the programmed I_Bcurrent, which controls

For lower power links: I = 0.5mA and K = 0.5

B

For full power links: I = 1mA and K = 0.5

B

For long links (>50m): I = 1mA and K = 0.25

the isoSPI signaling currents. Bias current I can range

B

from 100μA to 1mA. Internal circuitry scales up this bias

current to create the isoSPI signal currents equal to be

20 • I_B. A low I_Breduces the isoSPI power consump-

tion in the READY and ACTIVE states, while a high I_B

increases the amplitude of the differential signal voltage

For addressable multidrop: I = 1mA and K = 0.4

B

For applications with little system noise, setting I_Bto

0.5mA is a good compromise between power consump-

tion and noise immunity. Using this I_Bsetting with a

1:1 transformer and R_M= 100Ω, R_B1should be set to

V across the matching termination resistor, R . The I

A

M

B

3.01k and R set to 1k. With typical CAT5 twisted pair,

B2

current is programmed by the sum of the R and R

B1

B2

these settings will allow for communication up to 50m.

Applications in very noisy environments or with cables

resistors connected between the 2V IBIAS pin and GND

as shown in Figure 44. The receiver input threshold is set

by the ICMP voltage that is programmed with the resistor

longer than 50m should increase the I to 1mA. Higher

B

drive current compensates for the increased insertion

loss in the cable and provides high noise immunity.

When using cables over 50m and a transformer with a

divider created by the R and R resistors. The receiver

B1

B2

differential threshold will be half of the voltage present on

the ICMP pin.

1:1 turns ratio and R = 100Ω, R would be 1.5k and

M

B1

The following guidelines should be used when setting the

bias current (100µA to 1mA) I_Band the receiver compara-

R

would be 499Ω.

B2

The length of the cable determines the maximum clock

rate of an isoSPI link. For cables 10 meters or less, the

maximum 1MHz SPI clock frequency is possible. As the

length of the cable increases, the maximum possible SPI

clock rate decreases. This dependence is a result of the

increased propagation delays that can create possible tim-

ing violations. Figure 45 shows how the maximum data

rate reduces as the cable length increases when using a

CAT 5 twisted pair.

tor threshold voltage V /2:

ICMP

R = Transmission Line Characteristic Impedance Z0

M

Signal Amplitude V = (20 • I ) • (R /2)

A

B

M

V

TCMP

V

ICMP

(Receiver Comparator Threshold) = K • V

A

(Voltage on ICMP pin) = 2 • V

TCMP

R

B2

R

B1

= V

/I = 20 • K • R

ICMP B M

= (2/I ) – R

B

B2

ꢁꢃꢄꢔAꢕꢁꢄꢛ ꢋARRꢁꢇR

ꢜꢀAꢝ ꢞꢃꢇ ꢄꢛꢇ ꢄR ꢕꢘꢄ ꢕRAꢛꢑꢄRꢀꢇRꢃꢟ

ꢁꢃꢄꢀꢅ ꢁꢂꢋ

ꢔꢕꢌꢍꢎꢏꢐ

ꢁꢂA ꢁꢃꢄꢀꢅ

ꢔꢕꢌꢍꢎꢏꢐ

ꢆ

Rꢇꢈ

ꢉ

•

ꢀAꢃꢕꢇR

R

ꢆ

A

ꢆ

A

ꢀ

ꢊ

ꢖꢆ

ꢊ

ꢖꢆ

ꢃꢅꢄ

ꢃꢅꢁ

ꢃꢌꢗ

CS

ꢀꢄꢃꢁ

ꢁꢀꢋ

ꢁꢀA

ꢕꢘꢁꢃꢕꢇꢅꢙꢂAꢁR ꢌAꢋꢔꢇ

ꢘꢁꢕꢚ ꢌꢚARAꢌꢕꢇRꢁꢃꢕꢁꢌ ꢁꢀꢂꢇꢅAꢛꢌꢇ R

ꢀꢁꢃꢄ

ꢃꢌꢗ

CS

ꢁꢋꢁAꢃ

ꢀ

R

ꢋꢏ

ꢋꢖ

ꢋꢏ

ꢋꢖ

ꢁꢌꢀꢂ

ꢍꢎꢏꢐꢏ ꢑꢒꢓ

Figure 44. isoSPI Circuit

Rev. A

77

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

ꢌ.ꢒ

they may be preferred. In this case, the addition of a split

termination resistor and a bypass capacitor (Figure 46a)

can enhance the isoSPI performance. Large center tap

capacitors greater than 10nF should be avoided as they

may prevent the isoSPI common mode voltage from

settling. Common mode chokes similar to those used

in Ethernet or CANbus applications are recommended.

Specific examples are provided in Table 57.

ꢀAꢆꢖꢗ Aꢊꢊꢘꢉꢃꢎ

ꢌ.ꢍ

ꢍ.ꢕ

ꢍ.ꢔ

ꢍ.ꢓ

ꢍ.ꢒ

ꢍ

IP

XFMR

ꢌ

ꢌꢍ

ꢌꢍꢍ

49.9Ω 100µH CMC

•

ꢀAꢁꢂꢃ ꢂꢃꢄꢅꢆꢇ ꢈꢉꢃꢆꢃRꢊꢋ

LTC6810

isoSPI LINK

ꢔꢕꢒꢍ ꢆAꢍꢌꢏ

49.9Ω

10nF

IM

Figure 45. Data Rate vs Cable Length

–

V

Cable delay affects three timing specifications, t_CLK, t₆and

7

by 100ns to allow for 50ns of cable delay. For longer

cables, the minimum timing parameters obey the follow-

ing relationship:

a)

t . In the Electrical Characteristics table, each is derated

IP

CT XFMR

51Ω

100µH CMC

•

LTC6810

isoSPI LINK

10nF

IM

10nF

t

, t and t > 0.9μs + 2 • t

(0.2m per nS)

CLK

6

7

CABLE

–

V

68101 F46

Implementing a Modular isoSPI Daisy Chain

b)

The hardware design of a daisy-chain isoSPI bus is identi-

cal for each device in the network due to the daisy-chain

point-to-point architecture. The simple design as shown in

Figure 44 is functional, but inadequate for most designs.

The use of cables between battery modules, particularly

in automotive applications, can add noise to the com-

munication lines. Therefore, the termination resistor RM

should be split and bypassed with a capacitor as shown

in Figure 46. This change provides both a differential and

a common mode termination, which increases the system

noise immunity.

Figure 46. Daisy Chain Interface Components

An important daisy chain design consideration is the num-

ber of devices in the isoSPI network, since this determines

the serial timing and affects data latency and throughput.

The maximum number of devices in an isoSPI daisy chain

is dictated by the serial timing requirements. However, it

is important to note that the serial read back time, and the

increased current consumption, might present a practical

limitation.

For a daisy chain, there are two timing consideration

that must be made (see Figure 29) to guarantee proper

operation:

For high levels of electromagnetic interference (EMC),

additional filtering is recommended. The circuit example in

Figure 46 shows the use of common-mode chokes (CMC)

to add common-mode noise rejection from transients

on the battery lines. The use of a center tapped trans-

former will also provide additional noise performance. A

bypass capacitor connected to the center tap creates a low

impedance for common-mode noise (Figure 46b). Since

transformers without a center tap can be less expensive,

1. t , the time between the last clock and the rising chip

6

select must be long enough.

2. t , the time between commands, so the time from a

5

rising chip select to the next falling chip select must

be long enough.

Rev. A

78

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

IPB

49.9Ω

LTC6810

10nF

49.9Ω

GNDD

IMB

1k

IBIAS

ICMP

GNDD

IPA

49.9Ω

10nF

GNDD

CT

10nF*

GNDD

–

V

IMA

GNDD

T1

CT

10nF*

GNDC

IPB

49.9Ω

LTC6810

10nF

49.9Ω

1k

GNDC

IMB

1k

IBIAS

ICMP

GNDC

IPA

49.9Ω

10nF

GNDC

CT

10nF*

GNDC

–

V

IMA

GNDC

T2

CT

10nF*

GNDB

IPB

49.9Ω

LTC6810

10nF

49.9Ω

1k

GNDB

IMB

1k

IBIAS

ICMP

GNDB

LTC6820

IP

•

IPA

49.9Ω

1k

IBIAS

ICMP

CT

10nF

10nF*

GNDA

GNDB GNDB

GNDA

–

V

IMA

IM

V

GNDB

GNDA

68101 F47

* IF TRANSFORMER BEING USED HAS A CENTER TAP, IT SHOULD BE BYPASSED WITH A 10nF CAP

Figure 47. Daisy Chain Interface Components on Single Board

Rev. A

79

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

Both t₅and t₆must be lengthened as the number of

LTC6810 devices in the daisy chain increase. The equa-

tions for these times are below:

on the same PCB, communicating to the bottom MCU

through a LTC6820 isoSPI driver. If a transformer with

a center tap is used, a capacitor can be added for better

noise rejection. Additional noise filtering is provided with

discrete common mode chokes (CMC) placed to both

sides of the single transformer as shown in Figure 47.

t > (#devices • 70ns) + 900ns

5

t > (#devices • 70ns) + 950ns

6

On single board designs with lower noise requirements,

it is possible for a simplified capacitor-isolated coupling

as shown in Figure 48 to replace the transformer. In this

circuit the transformer is directly replaced with two 10nF

capacitors. An optional common mode choke (CMC)

helps provides noise rejection similar to application cir-

cuits using transformers. The circuit is designed to use

IBIAS/ICMP settings identical to the transformer circuit.

Connecting Multiple LTC6810-1s on the Same PCB

When connecting multiple LTC6810-1 devices on the

same PCB, only a single transformer is required between

the LTC6810-1 isoSPI ports. The absence of the cable also

reduces the noise levels on the communication lines and

often only a split termination is required. Figure 47 shows

an example application that has multiple LTC6810-1s

10nF

V

REG

ACT45B-101-2P-TL003

IPB

LTC6810

49.9Ω 10nF

49.9Ω

C13

10nF

GNDB

IMB

1k

IBIAS

ICMP

GNDB

V

REG

IPA

49.9Ω 10nF

49.9Ω

–

V

GNDB

ACT45B-101-2P-TL003

IMA

IPB

GNDB

10nF

V

REG

LTC6810

49.9Ω 10nF

49.9Ω

GNDA

IMB

1k

IBIAS

ICMP

GNDA

V

REG

IPA

49.9Ω 10nF

49.9Ω

–

V

GNDA

IMA

GNDA

68101 F48

Figure 48. Capacitive Isolation Coupling for LTC6810-1s on the Same PCB

Rev. A

80

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

Connecting an MCU to an LTC6810-1 with an isoSPI

Data Link

since only the addressed device returns data to the mas-

ter. Generally, multi-drop systems are best confined to

compact assemblies where they can avoid excessive iso-

SPI pulse-distortion and EMC pickup.

The LTC6820 will convert standard 4-wire SPI into a

2-wire isoSPI link that can communicate directly with

the LTC6810. An example is shown in Figure 49. The

LTC6820 can be used in applications to easily provide

isolation between the microcontroller and the stack of

LTC6810s. The LTC6820 also enables system configura-

tions that have the BMS controller at a remote location

relative to the LTC6810 devices and the battery pack.

Basic Connection of the LTC6810-2 in a Multi-Drop

Configuration

In a multi-drop isoSPI bus, placing the termination at the

end of the transmission line provides the best perfor-

mance (with 100Ω typically). Each of the LTC6810 isoSPI

ports should be connected to the bus with a resistor net-

work, as shown in Figure 51a. Here again, a center-tapped

transformer offers the best performance and a common-

mode-choke (CMC) increases the noise rejection further,

as shown in Figure 51b. An RC snubber is used at the IC

connections to suppress resonances (the IC capacitance

provides sufficient out-of-band rejection). When using a

non-center-tapped transformer, a virtual CT can be gen-

erated by connecting a CMC as a voltage-splitter. Series

resistors are recommended to decouple the LTC6810 and

board parasitic capacitance from the transmission line.

Reducing these parasitics on the transmission line will

minimize reflections.

Configuring the LTC6810-2 in a Multi-Drop isoSPI Link

The addressing feature of the LTC6810-2 allows multiple

devices to be connected to a single isoSPI master by dis-

tributing them along one twisted pair. In effect, this creates

a large parallel SPI network. A basic multi-drop system

is shown in Figure 50; the twisted pair is terminated only

at the beginning (master) and the end of the cable. In

between, the additional LTC6810-2s are connected to

short stubs on the twisted pair. These stubs should be

kept short, with as little capacitance as possible, to avoid

degrading the termination along the isoSPI wiring.

When an LTC6810-2 is not addressed, it will not transmit

data pulses. This eliminates the possibility for collisions

+

IPB

V

•

LTC6810

49.9Ω

10nF

49.9Ω

1k

GNDB

IMB

1k

IBIAS

ICMP

IPA

IP

•

LTC6820

49.9Ω

1k

IBIAS

ICMP

10nF

GNDA

49.9Ω

GNDB

GNDA

–

V

GNDB

IMA

IM

V

68101 F49

GNDA

Figure 49. Interfacing an LTC6810-1 with a µC Using an LTC6820 for Isolated SPI Control

Rev. A

81

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

V

REGC

LTC6810

ISOMD

IPA

•

IBIAS

100Ω

1.21k

ICMP

IMA

806Ω

GNDC

–

V

GNDC

V

REGB

LTC6810

ISOMD

IPA

•

IBIAS

1.21k

ICMP

IMA

806Ω

GNDB

–

V

100nF

5V

1.21k

806Ω

LTC6820

DDS

GNDB

V

EN

IBIAS

ICMP

GND

SLOW

MSTR

IP

1.21k

MOSI

MISO

SCK

CS

µC

SDO

SDI

SCK

CS

V

LTC6810

ISOMD

REGA

5V

IPA

•

POL

PHA

IM

IBIAS

5V

V

DD

5V

100Ω

1.21k

806Ω

100nF

ICMP

IMA

–

V

GNDA

68101 F50

GNDA

Figure 50. Connecting the LTC6810-2 in a Multi-Drop Configuration

Rev. A

82

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

IPA

22Ω

100µH CMC HV XFMR

isoSPI

BUS

100µH CMC

10nF

402Ω

•

LTC6810

15pF

IMA

–

V

a)

IPA

22Ω

CT HV XFMR

isoSPI

BUS

100µH CMC

10nF

402Ω

•

LTC6810

15pF

IMA

–

V

68101 F51

b)

Figure 51. Preferred isoSPI Bus Couplings For Use With LTC6810-2

Rev. A

83

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

Table 56. Recommended Transformers

W

AEC-

Q200

SUPPLIER

PART NUMBER

TEMP RANGE

V

V /60S CT CMC

HIPOT

H

L

(W/ LEADS) PINS

WORKING

Recommended Dual Transformers

l

–

l

–

l

–

Bourns

Jingweida

Halo

SM91501AL

SM13105L (AS4562)

US4374

–40°C to 125°C

–40°C to 85/125°C

–40°C to 125°C

1000V

1600V

950V

4.3kVdc

5.0mm 15.0mm 14.7mm

5.0mm 15.0mm 27.9mm

4.9mm 15.6mm 24.0mm

5.0mm 14.8mm 14.8mm

12SMT

16SMT

12SMT

16SMT

10SMT

12SMT

16SMT

12SMT

4.3kVrms

4.3kVdc

1.5kVrms

l

–

S12502BA

1000V

TG110-AE050N5LF

CLP178-C20114

CLP0612-C20115

HM2100NL

60V (est)

6.4mm 12.7mm

9mm 17.5mm 15.1mm

5.7mm 12.7mm 9.4mm

9.5mm

Sumida

Pulse

1000V (est) 3.75kVrms

600Vrms

1000V

3.75kVrms

4.3kVdc

1.5kVrms

4kVrms

–

l

–

l

–

–40°C to 105°C

–40°C to 125°C

–40°C to 85°C

0°C to 70°C

3.5mm 14.7mm 15.0mm

3.5mm 14.7mm 15.5mm

l

Pulse

HM2112ZNL

HX1188FNL

1600V

Pulse

60V (est)

250Vrms

1000V (est)

250Vrms

6.0mm 12.7mm

2.1mm 12.7mm

9.7mm

Pulse

HX0068ANL

–

Wurth

7490140110

7490140111

749014018

10.9mm 24.6mm 17.0mm

8.4mm 17.1mm 15.2mm

–

4.5kVrms

4kVrms

–

l

0°C to 70°C

–

Recommended Single Transformers

l

–

l

–

l

–

Bourns

Halo

SM91502AL

SM13102AL (US4195)

TD04-QXLTAW

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 105°C

–40°C to 125°C

–40°C to 105°C

–40°C to 125°C

1000V

800V

4.3kVdc

4kVrms

5kVrms

3kVrms

5kVrms

4.3kVdc

2.5kVrms

3kVrms

6.5mm 8.5mm

8.9mm

6SMT

6TH

3.8mm 11.6mm 21.1mm

1000V (est)

300V

8.6mm 8.9mm

10mm 9.5mm

9.4mm 8.9mm

6.4mm 8.9mm

6.3mm 7.6mm

5.7mm 7.6mm

16.6mm

12.1mm

16.6mm

9.9mm

–

Halo

TGR04-6506V6LF

TGR04-A6506NA6NL

TDR04-A550ALLF

S06107BA

–

6SMT

6TH

–

l

–

Halo

300V

–

Halo

1000V

–

l

–

Jingweida

Pulse

1000V (est)

1000V

6SMT

4SMT

8SMT

4SMT

6SMT

8SMT

6SMT

4SMT

6SMT

l

–

HM2101NL

9.3mm

l

Pulse

HM2113ZNL

1600V

3.5mm

7mm

9mm

15.5mm

12.0mm

9.1mm

Sumida

TDK

CEEH96BNP-LTC6804/11 –40°C to 125°C

600V

–

9.2mm

l

–

CEP99NP-LTC6804

ESMIT-4180/A

–40°C to 125°C

–40°C to 105°C

600V

–

10mm 9.2mm

3.5mm 5.2mm

3.5mm 7.5mm

4.0mm 8.5mm

2.9mm 3.2mm

–

l

–

250Vrms

–

ESMIT-4187

–40°C to 105°C >400Vrms (est) 2.5kVrms

–

12.8mm

13.8mm

4.5mm

l

–

VMT40DR-201S2P4

ALT4532V-201-T001

VGT10/9EE-204S2P4

ALTW0806C-C03

750340848

–40°C to 125°C

–40°C to 105°C

–40°C to 125°C

–40°C to 105°C

–40°C to 85°C

600V (est)

80V

3.4kVdc

~1kV

–

TDK

–

TDK

700V

2.8kVrms

3kVrms

2.9kVrms

–

10.6mm 10.4mm 12.6mm

Sunlord

Wurth

XFMRS

300V (est)

250V

–

8.8mm 6.3mm

2.2mm 4.4mm

8.9mm

9.1mm

l

XFBMC29-BA09

1600V (est)

5.0mm 10.0mm 19.5mm

Rev. A

84

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

Transformer Selection Guide

long-term (‘permanent’) rating of the part. For example,

according to most safety standards a 1.5kV rated trans-

former is expected to handle 230V continuously, and a

3kV device is capable of 1100V long-term, though manu-

facturers may not always certify to those levels (refer to

actual vendor data for specifics). Usually the higher volt-

age transformers are called ‘high-isolation’ or ‘reinforced

insulation’ types by the suppliers. Table 56 shows a list

of transformers that have been evaluated in isoSPI links.

As shown in Figure 44, a transformer or pair of trans-

formers are used to isolate the isoSPI signals between

two isoSPI ports. The isoSPI signals have programmable

pulse amplitudes up to 1.6V and pulse widths of 50ns

P-P

and 150ns. To be able to transmit these pulses with the

necessary fidelity the system requires that the transform-

ers have primary inductances above 60µH and a 1:1 turns

ratio. It is also necessary to use a transformer with less

than 2.5µH of leakage inductance. In terms of pulse shape

the primary inductance will mostly effect the pulse droop

of the 50ns and 150ns pulses. If the primary inductance is

too low the pulse amplitude will begin to droop and decay

over the pulse period, if the pulse droop is severe the

In most applications a common mode choke is also nec-

essary for noise rejection. Table 57 includes a list of suit-

able CMCs if the CMC is not already integrated into the

transformer being used.

Table 57. Recommended Common Mode Chokes

effective pulse width seen by the receiver will drop, reduc

-

MANUFACTURER

TDK

PART NUMBER

ACT45B-101-2P

DLW43SH101XK2

ing noise margin. Some droop is acceptable as long as it

is a relatively small percentage of the total pulse ampli-

tude. The leakage inductance will primarily effect the rise

and fall times of the pulses. Slower rise and fall times will

effectively reduce the pulse width. Pulse width is deter-

mined by the receiver as the time the signal is above the

threshold set at the ICMP pin. This means that slow rise

and fall times cut into the timing margins. Generally it

is best to keep pulse edges as fast as possible. When

evaluating transformers it is also worth noting is the par-

allel winding capacitance. While transformers have very

good CMRR at low frequency, this rejection will degrade

at higher frequencies and this is largely due to the winding

to winding capacitance. So when choosing a transformer

it is best to pick one with less parallel winding capacitance

when possible.

Murata

isoSPI Layout Guidelines

Layout of the isoSPI signal lines also plays a significant

role in maximizing the noise immunity of a data link. The

following layout guidelines are recommended:

1. The transformer should be placed as close to the

isoSPI cable connector as possible. The distance

should be kept less than 2cm. The LTC6810 should

be placed close to but at least 1cm to 2cm away from

the transformer to help isolate the IC from magnetic

field coupling.

2. A V– ground plane should not extend under the trans-

former, the isoSPI connector, or in between the trans-

former and the connector.

When choosing a transformer it is equally important to

pick a part that has an adequate isolation rating for the

application. The working voltage rating of a transformer

is a key spec when selecting a part for an applications.

Interconnecting daisy chain links between LTC6810-1

devices will typically see <60V stress, so ordinary pulse

and LAN type transformers will suffice. Multi-drop con-

nections and connections to the LTC6820 in general may

need much higher working voltage ratings for good long-

term reliability. Usually matching the working voltage to

the voltage of the entire battery stack is conservative.

Unfortunately, transformer vendors will often only spec-

ify one-second HV testing, and this is not equal to the

3. The isoSPI signal traces should be as direct as pos-

sible while isolated from adjacent circuitry by ground

metal or space. No traces should cross the isoSPI

signal lines, unless separated by a ground plane on

an inner layer.

System Supply Current

The LTC6810 has various supply current specifications

for the different states of operation. The average supply

current dependents on the control loop in the system. It

Rev. A

85

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

Table 58. Daisy Chain Serial Time Equations

DATA BYTES

COMMAND TYPE

Read

CMD BYTES + CMD PEC

+ DATA PEC PER IC

TOTAL BITS

(4 + (8 • #ICs)) • 8

4 • 8 = 32

COMMUNICATION TIME

Total Bits • Clock Period

32 • Clock Period

4

8

0

Write

Operation

Table 59. Multi-Drop Serial Time Equations

DATA BYTES

COMMAND TYPE

Read

CMD BYTES + CMD PEC

+ DATA PEC PER IC

TOTAL BITS

((4 + 8) • #ICs) • 8

4 • 8 = 32

COMMUNICATION TIME

Total Bits • Clock Period

32 • Clock Period

4

8

0

Write

Operation

is necessary to know which commands are being exe-

cuted each control loop cycle, and the duration of the

control loop cycle. From this information it is possible

to determine the percentage of time the LTC6810 is in

the measure state versus the low power sleep state. The

amount of isoSPI or SPI communication will also affect

the average supply current.

Hall-Effect sensor that produces two outputs that propor-

tion to the V provided. The sensor in the figure has two

CC

bidirectional outputs centered at half of supply, CH1 is a

0A to 50A low range and CH2 is a 0A to 200A high range.

The sensor is powered from a 5V source and produces

analog outputs that are connected to GPIO pins or inputs

of the MUX application shown in Figure 54. The use of

GPIO1 and GPIO2 as the ADC inputs has the possibility

of being digitized within the same conversion sequence

as the cell inputs (using the ADCVAX command), thus

synchronizing cell voltage and cell current measurements.

Calculating Serial Throughput

For any given LTC6810 the calculation to determine com-

munication time is simple, it is the number of bits in the

transmission multiplied by the SPI clock period being

used. The control protocol of the LTC6810 is very uni-

form so almost all commands can be categorized as a

write, read or an operation. The tables below can be used

to determine the number of bits in a given LTC6810 com-

mand. Table 58 can be used for daisy-chains and Table 59

for multi-drop networks.

ꢇꢈꢉ ꢊꢋAꢌ

A

ꢍꢋꢆ

AꢎAꢇꢏꢐ → ꢐꢑꢒꢏꢆ

ꢅꢓ

ꢌ

ꢍ

ꢊ

ꢓ

ꢍꢍ

ꢕ

ꢐꢎꢊ

AꢎAꢇꢏꢐꢔꢍꢏꢉ → ꢓ

ꢍꢋꢂ

AꢎAꢇꢏꢐꢃ → ꢐꢑꢒꢏꢂ

ꢀꢁꢂꢃꢂ ꢄꢅꢆ

Figure 52. Interfacing a Typical Hall-Effect Battery Current

Sensor to Auxiliary ADC Inputs

ENHANCED APPLICATIONS

Current Measurement with a Hall-Effect Sensor

READING EXTERNAL TEMPERATURE PROBES

The LTC6810 auxiliary ADC inputs (GPIO pins) may be

used for any analog signal, including active sensors

with 0V to 5V analog outputs. For battery current mea-

surements, Hall-effect sensors provide an isolated, low

power solution. Figure 52 shows schematically a typical

Figure 53 shows the typical biasing circuit for a negative-

temperature-coefficient (NTC) thermistor. The 10kΩ @

25°C is the most popular sensor value and the V_REF2

output stage is designed to provide the current required

to bias several of these probes. The biasing resistor is

Rev. A

86

For more information www.analog.com

LTC6810-1/LTC6810-2

APPLICATIONS INFORMATION

selected to correspond to the NTC value so the circuit will

ꢑꢋꢋ

ꢔꢋ

ꢒꢋ

ꢕꢋ

ꢓꢋ

ꢖꢋ

ꢊꢋ

provide 1.5V at 25°C (V

is 3V nominal). The overall

circuit response is appr^Ro^Ex^Fi²mately –1%/°C in the range

of typical cell temperatures, as shown in the chart of

Figure 53.

ꢌ

Rꢁꢏꢐ

ꢑꢋꢘ

ꢀꢁꢂꢃ

ꢙꢀꢇ

ꢑꢋꢘ Aꢀ ꢐꢖꢆꢇ

Expanding the Number of Auxiliary Measurements

ꢗꢋ

ꢐꢋ

ꢑꢋ

ꢋ

ꢉ

ꢌ

The LTC6810 has five GPIO pins that can be used as

ADC inputs. In applications that need to measure more

than five signals a multiplexer (MUX) circuit can be imple-

mented to expand the analog measurements to sixteen

different signals (Figure 54). The GPIO1 ADC input is

used for measurement and MUX control is provided by

ꢉꢊꢋ ꢉꢐꢋ

ꢋ

ꢐꢋ

ꢊꢋ

ꢓꢋ

ꢒꢋ

ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ

ꢓꢒꢑꢋꢑ ꢏꢖꢗ

Figure 53. Typical Temperature Probe Circuit and Relative Output

2

the I C port on GPIO3 and GPIO4. The buffer amplifier

was selected for fast settling and will increase the usable

throughput rate.

ADG728

V

ANALOG1

ANALOG2

ANALOG3

ANALOG4

ANALOG5

ANALOG6

ANALOG7

ANALOG8

S1

S2

S3

S4

S5

S6

S7

S8

V

GND

A0

REG

DD

–

LTC6810-1

20k

1µF

A1

GPIO4

SCL

SDA

D

GPIO3

ꢀꢁSꢁꢂ

ADG728

–

+

100Ω

ANALOG9

ANALOG10

ANALOG11

ANALOG12

ANALOG13

ANALOG14

ANALOG15

ANALOG16

S1

S2

S3

S4

S5

S6

S7

S8

V

DD

LTC6255

GPIO1

GND

A0

68101 F54

10nF

A1

SCL

SDA

D

ꢀꢁSꢁꢂ

ANALOG INPUTS: 0.04V TO 4.5V

Figure 54. MUX Circuit Supports Sixteen Additional Analog Measurements

Rev. A

87

For more information www.analog.com

LTC6810-1/LTC6810-2

PACKAGE DESCRIPTION

G Package

44-Lead Plastic SSOP (5.3mm)

ꢍReꢩeꢪeꢫꢬe ꢓꢐꢝ ꢡꢦꢀ ꢭ ꢅꢌꢮꢅꢆꢮꢇꢗꢌꢁ Rev Aꢎ

ꢇꢋ.ꢌꢅ ꢊ ꢇꢖ.ꢇꢅꢕ

ꢍ.ꢁꢔꢋ ꢊ .ꢌꢇꢙꢎ

ꢇ.ꢋꢌ ꢅ.ꢇꢋ

ꢌ.ꢖ ꢊ ꢌ.ꢗ

ꢁꢅ ꢖꢆ

ꢁꢁ ꢁꢖ ꢁꢋ ꢁꢇ ꢖꢔ ꢖꢗ ꢖꢙ ꢖꢌ ꢖꢁ ꢖꢖ ꢖꢋ ꢖꢇ ꢖꢅ ꢋꢔ ꢋꢆ ꢋꢗ ꢋꢙ ꢋꢌ ꢋꢁ ꢋꢖ

ꢗ.ꢆ ꢊ ꢆ.ꢋ

ꢗ.ꢁꢅ ꢊ ꢆ.ꢋꢅ

ꢍ.ꢋꢔꢇ ꢊ .ꢖꢋꢖꢎ

ꢅ.ꢌꢅ

ꢜꢂꢝ

ꢅ.ꢋꢌ ꢅ.ꢅꢌ

ꢌ

ꢗ

ꢆ

Rꢈꢝꢃꢚꢚꢈꢒꢡꢈꢡ ꢂꢃꢓꢡꢈR ꢄAꢡ ꢓAꢟꢃꢢꢐ

Aꢄꢄꢓꢟ ꢂꢃꢓꢡꢈR ꢚAꢂꢨ ꢐꢃ ARꢈAꢂ ꢐꢠAꢐ ARꢈ ꢒꢃꢐ ꢂꢃꢓꢡꢈRꢈꢡ

ꢇ

ꢋ

ꢖ

ꢁ

ꢙ

ꢔ ꢇꢅ ꢇꢇ ꢇꢋ ꢇꢖ ꢇꢁ ꢇꢌ ꢇꢙ ꢇꢗ ꢇꢆ ꢇꢔ ꢋꢅ ꢋꢇ ꢋꢋ

ꢋ.ꢅ

ꢍ.ꢅꢗꢔꢎ

ꢚAꢛ

ꢌ.ꢅꢅ ꢊ ꢌ.ꢙꢅꢕ

ꢍ.ꢇꢔꢗ ꢊ .ꢋꢋꢇꢎ

ꢇ.ꢙꢌ ꢊ ꢇ.ꢆꢌ

ꢍ.ꢅꢙꢌ ꢊ .ꢅꢗꢖꢎ

ꢄARꢐꢑꢒꢀ

ꢓꢑꢒꢈ

ꢅꢏ ꢊ ꢆꢏ

ꢂꢈAꢐꢑꢒꢀ

ꢄꢓAꢒꢈ

ꢅ.ꢌꢅ

ꢍ.ꢅꢇꢔꢙꢆꢎ

ꢜꢂꢝ

ꢅ.ꢇꢅ ꢊ ꢅ.ꢋꢌ

ꢍ.ꢅꢅꢁ ꢊ .ꢅꢇꢅꢎ

ꢅ.ꢌꢌ ꢊ ꢅ.ꢔꢌꢕꢕ

ꢍ.ꢅꢋꢋ ꢊ .ꢅꢖꢗꢎ

ꢇ.ꢋꢌ

ꢍ.ꢅꢁꢔꢋꢎ

Rꢈꢘ

ꢅ.ꢅꢌ

ꢍ.ꢅꢅꢋꢎ

ꢚꢑꢒ

ꢞ

ꢅ.ꢋꢅ ꢊ ꢅ.ꢖꢇꢌ

ꢍ.ꢅꢅꢆ ꢊ .ꢅꢇꢋꢁꢎ

ꢐꢟꢄ

ꢀꢁꢁ ꢂꢂꢃꢄ ꢅꢆꢇꢁ Rꢈꢉ A

ꢒꢃꢐꢈꢥ

ꢇ.ꢡRAꢦꢑꢒꢀ ꢑꢂ ꢒꢃꢐ A ꢧꢈꢡꢈꢝ ꢃꢢꢐꢓꢑꢒꢈ

ꢕꢡꢑꢚꢈꢒꢂꢑꢃꢒꢂ ꢡꢃ ꢒꢃꢐ ꢑꢒꢝꢓꢢꢡꢈ ꢚꢃꢓꢡ ꢘꢓAꢂꢠ ꢃR ꢄRꢃꢐRꢢꢂꢑꢃꢒꢂꢣ

ꢜꢢꢐ ꢡꢃ ꢑꢒꢝꢓꢢꢡꢈ ꢚꢃꢓꢡ ꢚꢑꢂꢚAꢐꢝꢠ Aꢒꢡ ARꢈ ꢚꢈAꢂꢢRꢈꢡ Aꢐ

ꢐꢠꢈ ꢄARꢐꢑꢒꢀ ꢓꢑꢒꢈ. ꢚꢃꢓꢡ ꢘꢓAꢂꢠ ꢂꢠAꢓꢓ ꢒꢃꢐ ꢈꢛꢝꢈꢈꢡ .ꢇꢌꢤꢤ ꢄꢈR ꢂꢑꢡꢈ

ꢋ. ꢝꢃꢒꢐRꢃꢓꢓꢑꢒꢀ ꢡꢑꢚꢈꢒꢂꢑꢃꢒꢥ ꢚꢑꢓꢓꢑꢚꢈꢐꢈRꢂ

ꢚꢑꢓꢓꢑꢚꢈꢐꢈRꢂ

ꢖ. ꢡꢑꢚꢈꢒꢂꢑꢃꢒꢂ ARꢈ ꢑꢒ

ꢍꢑꢒꢝꢠꢈꢂꢎ

ꢕꢕꢓꢈꢒꢀꢐꢠ ꢃꢘ ꢓꢈAꢡ ꢘꢃR ꢂꢃꢓꢡꢈRRꢑꢒꢀ ꢐꢃ A ꢂꢢꢜꢂꢐRAꢐꢈ

ꢞ

ꢐꢠꢈ ꢚAꢛꢑꢚꢢꢚ ꢡꢑꢚꢈꢒꢂꢑꢃꢒ ꢡꢃꢈꢂ ꢒꢃꢐ ꢑꢒꢝꢓꢢꢡꢈ ꢡAꢚꢜAR ꢄRꢃꢐRꢢꢂꢑꢃꢒꢂ.

ꢡAꢚꢜAR ꢄRꢃꢐRꢢꢂꢑꢃꢒꢂ ꢡꢃ ꢒꢃꢐ ꢈꢛꢝꢈꢈꢡ ꢅ.ꢇꢖꢤꢤ ꢄꢈR ꢂꢑꢡꢈ

ꢁ. ꢡRAꢦꢑꢒꢀ ꢒꢃꢐ ꢐꢃ ꢂꢝAꢓꢈ

ꢌ. ꢘꢃRꢚꢈꢡ ꢓꢈAꢡꢂ ꢂꢠAꢓꢓ ꢜꢈ ꢄꢓAꢒAR ꢦꢑꢐꢠ Rꢈꢂꢄꢈꢝꢐ ꢐꢃ

ꢃꢒꢈ AꢒꢃꢐꢠꢈR ꢦꢑꢐꢠꢑꢒ ꢅ.ꢅꢆꢤꢤ Aꢐ ꢂꢈAꢐꢑꢒꢀ ꢄꢓAꢒꢈ

Rev. A

88

For more information www.analog.com

LTC6810-1/LTC6810-2

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

03/20 Added Automotive Qualification to Front Page Features

Order Information Updated

1

4

Electrical Characteristics, Sum of Cells Corrected to 0.6V MAX

Electrical Characteristics, Receiver Voltage Range Removed

Figure 15 Title Corrected: ADCVSC Replaced with ADVCAX

Table 56. Recommended Transformers List Updated

Related Parts Table Updated

5

8

33

81

86

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

89

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTC6810-1/LTC6810-2

TYPICAL APPLICATION

Basic 6-Cell Monitor with isoSPI Daisy Chain

10Ω

+

V

DRIVE

FCX491QTA

1µF

100nF

V

REG

100Ω

C6

V

REF1

10nF

10Ω

1µF

B6

V

S6

C5

V

REF2

100Ω

HM2100NL

10nF

10Ω

B5

V

IPA

S5

C4

49.9Ω

10nF

10Ω

10nF

49.9Ω

B4

V

S4

C3

IMA

IPA

LTC6810

10nF

10Ω

B3

V

49.9Ω

S3

C2

10nF

10Ω

IMA

B2

V

S2

C1

68101 TA02

10nF

10Ω

1k

IBIAS

ICMP

ISOMD

S1

C0

S0

B1

V

10Ω

–

V

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC6804

3rd Generation 12-Cell Battery Stack

Monitor and Balancing IC

Measures Cell Voltages for Up to 12 Series Battery Cells. Daisy-Chain Capability Allows

Multiple Devices to Be Connected to Measure 100s of Battery Cells Simultaneously Via

the Built-In 1MHz, 2-Wire Isolated Communication (isoSPI). Includes Capability for

Passive Cell Balancing.

LTC6811

LTC6812

4th Generation 12-Cell Battery Stack

Monitor and Balancing IC

Measures Cell Voltages for Up To 12 Series Battery Cells. Daisy-Chain Capability Allows

Multiple Devices to Be Connected to Measure 100s of Battery Cells Simultaneously Via

the Built-In 1MHz, 2-Wire Isolated Communication (isoSPI). Includes Capability for

Passive Cell Balancing.

4th Generation 15-Cell Battery Stack

Monitor and Balancing IC

Measures Cell Voltages for Up to 15 Series Battery Cells. The isoSPI Daisy-Chain

Capability Allows Multiple Devices to be Interconnected for Measuring Many Battery

Cells Simultaneously. The isoSPI Bus can Operate Up to 1MHz and can be Operated

Bidirectionally for Fault Conditions, such as a Broken Wire or Connector. Includes Internal

Passive CellBalancing Capability of Up to 200mA.

LTC6813

LTC6820

90

4th Generation 18-Cell Battery Stack

Monitor and Balancing IC

Measures Cell Voltages for Up to 18 Series Battery Cells. The isoSPI Daisy-Chain

Capability Allows Multiple Devices to be Interconnected for Measuring Many Battery

Cells Simultaneously. The isoSPI Bus can Operate Up to 1MHz and can be Operated

Bidirectionally for Fault Conditions, such as a Broken Wire or Connector. Includes Internal

Passive CellBalancing Capability of Up to 200mA.

isoSPI Isolated Communications

Interface

Provides an Isolated Interface for SPI Communication Up to 100 Meters, Using a Twisted

Pair. Companion to the LTC6804, LTC6806, LTC6810, LTC6811, LTC6812 and LTC6813.

Rev. A

03/20

www.analog.com

 ANALOG DEVICES, INC. 2018–2020

For more information www.analog.com


型号：	LTC6806
厂家：	ADI
描述：	36 Channel Fuel Cell Monitor
文件：	总90页 (文件大小：4015K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC6806 [ADI]

相关型号：

SI9130DB

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SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E