LTC7051-1 [ADI]
Dual SilentMOS Smart Power Stage in 5mm à 8mm LQFN;
| 型号： | LTC7051-1 |
| 厂家： | 
ADI |
| 描述： | Dual SilentMOS Smart Power Stage in 5mm à 8mm LQFN |
| 文件： | 总16页 (文件大小：1784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC7050
Dual SilentMOS Smart Power
Stage in 5mm × 8mm LQFN
FEATURES
DESCRIPTION
The LTC®7050 dual monolithic power stage fully inte-
grates high speed drivers with low resistance half-bridge
power switches plus comprehensive monitoring and
protection circuitry in an electrically and thermally opti-
mized package. With a suitable high frequency control-
ler, this power stage forms a compact, high current volt-
age regulator system with state-of-the-art efficiency and
transient response.
n
70A Peak Output Current per Channel
n
SilentMOS™ Smart Power Stage
Utilizes Low EMI/EMC Silent Switcher®2
n
Architecture
n
Ultra-low SW-Voltage Overshoot
Frequency Up to 2MHz
n
n
V Up to 14V
IN
n
n
n
n
n
n
n
n
Up to 94% Efficiency at 1MHz with 1.8V
Integrated Boost Diodes and Capacitors
Accurate Switch Current Monitoring
Power MOSFET Overcurrent Protection
Input Overvoltage and Bias Undervoltage Protection
Thermal Monitor with Overtemperature Flag
3.3V/5V Compatible Tri-State PWM Input
5mm × 8mm LQFN Package
OUT
SilentMOS technology utilizes second generation Silent
Switcher 2 architecture reducing both EMI and switch-
node voltage overshoot while maximizing efficiency at
high switching frequencies.
High speed current sensing provides low latency switch
current information, enabling tight current balancing and
immediate overcurrent protection.
APPLICATIONS
Thermally-enhanced packaging provides dual 40A rated
continuous output current capability.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 9525351.
n
High Current Servers and Workstations
n
Networking/Telecom Microprocessor Supplies
n
Small Form-Factor POL Converter
TYPICAL APPLICATION
Efficiency vs IOUT at 1MHz
95
90
85
80
75
70
65
12
10
8
12VIN, 1V/70AOUT 1MHz Dual-Phase POL Converter
EFFICIENCY
V
IN
4.5V TO 14V
10Ω
10µF
V
6
CC
PV
CC
5V
8k
V
V
INSNS
CC
POWER LOSS
V
V
PV
PV
47pF
1µF
FREQ
FB2
CC
CC
CC
CC
4
2.61k
50k
10k
LTC3861
I
10µF
×10
LIM2
2
33.2Ω
V
IN
INDUCTOR LOSS INCLUDED
L = L = VLBU9664100LT-R18L
1 2
I
SNS1N
V
SNSOUT1
SNSP1
LTC7050
8k
0
I
I
SNS1
SNS1P
RUN1
0
10
20
30
40
50
60
70
V
OUT
V
RUN1,2
PWM1
PWM2
FLTB1,2
LOAD CURRENT (A)
180nH
12k
7050 TA01b
PWM1
PWM2
RUN2
SW1
SW2
V
V
OUT
SNSN1
3.3nF
280Ω
10k
1V
180nH
VSW Waveform at 1MHz
70A
330µF
×3
FB1
100pF
5.9k
I
I
SNS2P
SNS2
12.5V
COMP1, 2
33.2Ω
100µF
×2
I
SNS2N
4.7nF
SGND PGND
7050 TA01a
I
LIM1
V
59k
SW1
I
AVG
SGND
1k
0.1µF
2V/DIV
SS1, 2
PINS NOT SHOWN IN LTC3861 CIRCUIT:
CLKIN, CONFIG, VSNSN2, VSNSOUT2,
VSNSP2, CLKOUT, PHSMD, PGOOD1,
PGOOD2, PWMEN1, PWMEN2
100pF
PINS NOT SHOWN IN LTC7050 CIRCUIT:
TDIO, TMON/FLT
0.1µF
V
OUT
= 12V
IN
I
= 60A
7050 TA01c
5ns/DIV
Rev. 0
1
Document Feedback
For more information www.analog.com
LTC7050
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V DC Voltage........................................... –0.3V to 16V
IN
V Transient Voltage ................................. –0.3V to 20V
IN
SW1, SW2 Voltage................................–0.3V to 16V DC
42
41 40 39
38 37
SW1
SW1
1
2
3
4
5
6
7
8
9
36 TDIO
35 PWM1
34 FLTB1
SW1, SW2 Voltage (20ns)............................. –2V to 20V
PV , V Voltage........................................ –0.3V to 6V
CC CC
RUN1, RUN2 .................................–0.3V to (V + 0.3V)
CC
SW1
V
IN
SW1
PGND
PWM1, PWM2 ..............................–0.3V to (V + 0.3V)
CC
SW1
33
I
SNS1
I
, I
...................................–0.3V to (V + 0.3V)
SNS1 SNS2 CC
SW1
32 RUN1
31 SGND
FLTB1, FLTB2 ................................–0.3V to (V + 0.3V)
CC
SW1
TDIO Voltage/Current..............................–0.3V to –5mA
AbsMax Junction Temperature ............................. 125°C
Storage Temperature.............................. –55°C to 150°C
Reflow (Package Body) Temperature....................260°C
PGND
PGND
PGND
30
V
CC
PGND
V
29 PV
28 PV
CC
CC
IN
SW2 10
SW2 11
SW2 12
SW2 13
SW2 14
SW2 15
27 PGND
26 RUN2
25
I
SNS2
SW2
PGND
V
IN
24 FLTB2
23 PWM2
22 TMON
16
17 18 19
20 21
LQFN PACKAGE
42-LEAD (8mm × 5mm × 0.95mm)
= 125°C, θ = 10.8°C/W ON OPTIMIZED
T
J(MAX OPER)
JA
6-LAYER 3.6 INCH × 2.8 INCH PCB
EXPOSED PADS (V , PGND, SW) MUST BE SOLDERED TO PCB
IN
ORDER INFORMATION
PACKAGE
TYPE
MSL
RATING
PART NUMBER
PART MARKING*
FINISH CODE
PAD FINISH
TEMPERATURE RANGE
LQFN (Laminate Package
with QFN Footprint)
LTC7050AV#PBF
7050
e4
Au (RoHS)
3
–40°C to 125°C
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• *Device temperature grade is identified by a label on the shipping container.
Parts ending with PBF are RoHS and WEEE compliant.
• LGA and BGA Package and Tray Drawings
Rev. 0
2
For more information www.analog.com
LTC7050
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, PVCC = VCC = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
14
UNITS
V
l
l
V
Power Input Supply Range
IN
V
V
V
V
V
V
V
V
V
Overvoltage Lockout Threshold
Overvoltage Lockout Hysteresis
Overvoltage Lockout Delay
Shutdown Current
V
Rising
IN
14.9
15.7
V
IN
0.4
1
V
IN
(Note 3)
µs
µA
V
IN
V
= 12V, RUN1 = RUN2 = 0
25
IN
IN
l
l
V
V
V
Input Supply Range
4.5
5
5.5
CC
CC
CC
CC
CC
CC
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
Supply Current in Shutdown
Supply Current in Active
V
CC
Rising
4.05
4.15
0.2
14
4.25
V
CC(UVLO)
UVLO_HYST
VCC(SD)
VCC_active
V
I
I
RUN1 = RUN2 = 0V
µA
mA
V
RUN1 = RUN2 = 5V, PWM = Float
2.5
5
l
l
PV
PV
PV
Driver Input Supply Range
PV Undervoltage Lockout Threshold
4.5
3.9
5.5
4.1
CC
PV Rising
CC
4.0
0.35
300
2.5
1
V
CC(UVLO)
UVLO_HYST
PVCC(SD)
PVCC_active
UVLO
CC
PV Undervoltage Lockout Hysteresis
CC
V
I
I
t
PV Supply Current in Shutdown
CC
RUN1 = RUN2 = 0V
µA
mA
µs
PV and V Supply Current in Active
RUN1 = RUN2 = 5V, PWM = Float
CC
CC
Undervoltage Time Lockout Delay, from V
PV , V Rising
CC
CC CC
and PV to SW Low
RUN = 5V PWM = 0 (Note 3)
CC
RUN Input
l
V
V
RUN High Threshold
RUN Rising
2.2
2.45
0.2
30
2.7
0.1
V
V
IH_RUN
RUN Hysteresis
RUN_HYS
R
EN Pull-Down Resistor
Propagation Delay for RUN Low to High
kΩ
µs
PD_RUN
d_RUNH
T
From RUN Low ≥ High to SW = 0, PWM = 0
(Note 3)
12
T
Propagation Delay for RUN High to Low
From RUN High ≥ Low to SW High Z,
PWM = 0 (Note 3)
µs
d_RUNL
PWM Input
l
l
l
V
V
V
V
PWM High Threshold
2.7
2.1
V
V
IH_PWM
IL_PWM
PWM Low Threshold
0.8
1.5
PWM Tri-State Range
V
TR_PWM
PWM_HYS
PWM Hysterisis
Active to Tri-State or Tri-State to Active
To SGND
300
9.6
18.8
10
mV
kΩ
kΩ
ns
ns
ns
ns
ns
ns
V
R
R
PWM Pull-Down Resistor
PWM Pull-Up Resistor
PD_PWM
PU_PWM
To V
CC
t
t
t
t
t
t
Delay Time, PWM High to SW High
Delay Time, PWM Low to SW Low
Tri-State to Low Propagation Delay
Tri-State to High Propagation Delay
Active to Tri-State Delay Time
PWM Minimum ON-Time
PWM Floating Voltage
No Fault Condition (Note 3)
PWMHI-SW
PWMLO-SW
Tri_Lo_Delay
Tri_Hi_Delay
Tri_Hold
No Fault Condition(Note 3)
10
PWM Going Low to SW Going Low
PWM Going High to SW Going High
PWM Going to High Z to SW High Z (Note 3)
20
30
20
20
PWM_MINON
l
V
1.6
1.7
1.8
PWM_FLOAT
Rev. 0
3
For more information www.analog.com
LTC7050
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, PVCC = VCC = 5V unless otherwise noted.
SYMBOL
Output
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
SNS
A
Current Sense Gain (I
Overall Accuracy
/I
)
V = 1.5V
ISNS
OUT
8.5
10
250 12.5
100
11.5
µA/A
µA
IMON
MON OUT
I
= 5A to 25A, PWM = 0
I
I
= 25A, V
= 1.5V, PWM = 0,
SNS
OUT
ISNS
Accuracy at Trim
I
= –10A, V
= 1.5V, PWM = 0
ISNS
µA
V
OUT
l
V
IMON Operational Voltage Range
1.2
2.0
1
IMON
FLTB Output
R
Fault Bar Open-Drain Pull-Down Resistance FLTB Low
kΩ
FLTB-PD
TMON/FLT Output
A
V
Thermal Monitor Gain
0°C < T < 150°C (Note 3)
8
mV/°C
V
TMON
J
Thermal Monitor Voltage
T = 0°C (Note 3)
J
0.6
800
1.6
150
40
TMON
T = 25°C
J
780
1
825
60
mV
V
T = 125°C (Note 3)
J
OTP
Overtemperature Protection Accuracy
Overtemperature Hysteresis
(Note 3)
(Note 3)
°C
OTP_Hys
°C
I
I
Thermal Monitor Maximum Source Current T = 25°C, T
Forced at 0V
mA
µA
SOURCE_TMON
SINK_TMON
J
MON
Thermal Monitor Maximum Sink Current
Tdiode Forward Voltage Drop
T = 25°C, T
Forced at 1.28V
J
MON
V
T = 25°C, I = 0.1mA
678
mV
mV/°C
Tdiode
J
F
Tdiode Voltage Drop Temperature Coefficient I = 0.1mA (Note 3)
–1.8
F
SW Node
V
SW Floating Voltage
V
= 12V
IN
0.7
1.2
V
SW_Float
R
SW Pull-Down Resistance
kΩ
SW-PGND
Overcurrent Limits
I
I
t
t
I
I
Positive Overcurrent Threshold
Negative Overcurrent Threshold
Positive Overcurrent Blanking Time
Negative Overcurrent Blanking Time
Positive Zero Current Threshold
Negative Zero Current Threshold
PWM = H
80
90
–45
22
55
5
100
A
A
_OCP
PWM = L
_NCP
PWM = H (Note 3)
PWM = L (Note 3)
nS
nS
A
Blank_OC
Blank_NC
_ZCP
–8
A
_ZCN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: This parameter is not tested but is guaranteed by design.
Note 4: All currents into device pins are positive; all currents out of
device pins are negative. All voltages are referenced to ground unless
otherwise specified.
Note 2: The LTC7050A is specified over the –40°C to 125°C operating
junction temperature range. High Junction temperatures degrade
operating lifetimes. Note the maximum ambient temperature consistent
with these specifications is determined by specific operating conditions
in conjunction with board layout, the rated package thermal impedance
Note 5: The LTC7050 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
and other environmental factors. The junction temperature (T , in °C) is
J
calculated from the ambient temperature (T in °C) and power dissipation
A
(P , in Watts) according to the formula:
D
T = T + (P • θ )
JA
J
A
D
where θ (in °C/W) is the package thermal impedance.
JA
Rev. 0
4
For more information www.analog.com
LTC7050
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12V, PVCC = VCC = 5V
unless otherwise noted.
12VIN to 1VOUT Efficiency
12VIN to 1.8VOUT Efficiency
Power Dissipation vs Load
95
90
85
80
75
70
65
12
10
8
100
95
90
85
80
75
70
15
10
5
12
10
8
V
V
L
= 12V
EFFICIENCY
IN
= 1V
OUT
EFFICIENCY
= L = 180nH
1
2
f
= 600kHz
SW
DUAL PHASE INTERLEAVING
INDUCTOR LOSS INCLUDED
DUAL PHASE INTERLEAVING
INDUCTOR LOSS INCLUDED
DUAL PHASE INTERLEAVING
6
6
POWER LOSS
POWER LOSS
4
4
600kHz
1MHz
600kHz
1MHz
2
2
L
= L = VLBU9664100L-R18L
2
L
= L = VLBU9664100LT-R18L
2
1
1
0
0
0
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70 80
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
7050 G01
7050 G02
7050 G03
V
SNS vs ILOAD
VSNS vs Temperature
VSNS vs VIN
50
40
30
20
10
0
30
25
20
15
10
5
30
25
20
15
10
5
V
V
= 12V
OUT
V
= 12V
OUT
IN
IN
V
V
V
= 12V
= 1V
V
= 1V
IN
= 1V
LOAD = 25A
V
LOAD = 25A
V
OUT
SNS
= I
× 100
= I
× 100
= I
× 100
SNS
SNS
SNS
SNS
SNS
–10
0
0
0
5
10 15 20 25 30 35 40
(A)
–50 –25
0
25 50 75 100 125 150
3
6
9
12
15
I
TEMPERATURE (°C)
V
(V)
IN
LOAD
7050 G04
7050 G05
7050 G06
VSNS Gain vs VIN
VSNS Gain vs Frequency
VSNS Gain vs Temperature
12.0
11.5
11.0
10.5
10.0
9.5
10.8
10.6
10.4
10.2
10.0
9.8
10.7
10.6
10.5
10.4
10.3
10.2
10.1
10.0
9.9
V
V
V
= 12V
V
V
V
= 12V
IN
V
V
V
= 12V
IN
IN
= 1V
= 1V
= 1V
OUT
SNS
OUT
SNS
OUT
SNS
= I
× 100
= I
× 100
= I
× 100
SNS
SNS
SNS
9.6
9.0
9.4
8.5
9.2
9.8
8.0
9.0
9.7
4
5
6
7
8
9
10 11 12 13 14 15
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
–50 –25
0
25 50 75 100 125 150
V
(V)
FREQUENCY (MHz)
TEMPERATURE (°C)
IN
7050 G07
7050 G08
7050 G09
Rev. 0
5
For more information www.analog.com
LTC7050
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12V, PVCC = VCC = 5V
unless otherwise noted.
IVCC vs Frequency
IPVCC vs Frequency
VCC UVLO vs Temperature
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
170
150
130
110
90
4.3
4.2
4.1
4.0
3.9
3.8
V
V
I
= 12V
V
V
I
= 12V
IN
IN
= 1V
= 1V
OUT
OUT
= 25A, DUAL PHASE
= 25A, DUAL PHASE
LOAD
LOAD
RISING
FALLING
70
50
30
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8 2.0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8 2.0
–50 –25
0
25 50 75 100 125 150
FREQUENCY (MHz)
FREQUENCY (MHz)
TEMPERATURE (°C)
7050 G10
7050 G10
7050 G11
PVCC UVLO vs Temperature
PVIN OVLO vs Temperature
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
15.7
15.5
15.3
15.1
14.9
14.7
14.5
14.3
14.1
RISING
RISING
FALLING
FALLING
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
7050 G12
7050 G13
Current Limit vs Temperature
PWM Threshold vs Temperature
100.0
97.5
95.0
92.5
90.0
87.5
85.0
82.5
80.0
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
PWM HIGH RISING
f
= 1MHz
SW
PWM HIGH FALLING
PWM LOW RISING
PWM LOW FALLING
25
50
75
100
125
150
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
7050 G14
7050 G15
Rev. 0
6
For more information www.analog.com
LTC7050
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12V, PVCC = VCC = 5V
unless otherwise noted.
RUN Threshold vs Temperature
TDIO Forward Voltage
TMON vs Temperature
800
750
700
650
600
550
500
450
400
350
300
2.5
2.4
2.3
2.2
2.1
2.0
1600
1400
1200
1000
800
ON
32μA
OFF
2μA
600
400
200
–50 –25
0
25 50 75 100 125 150
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
7050 G17
7050 G16
7050 G18
Overcurrent Protection
Switching Rising Edge
V
SNS
12.5V
500mV/DIV
I
L
100A/DIV
FLTB1
5V/DIV
V
SW1
2V/DIV
PV = 12V
IN
SW1
10V/DIV
I
= 60A, DUAL PHASE
LOAD
f
=1MHz
SW
7050 G20
7050 G19
5ns/DIV
5µs/DIV
V
= ISNSx500
SNS
Rev. 0
7
For more information www.analog.com
LTC7050
PIN FUNCTIONS
RUN1, RUN2: Run Pin. When this pin is driven high, the
is enabled. SW node is in high-Z state when RUN is low.
TDIO: Temperature Diode Pin. This pin provides a refer-
ence diode to SGND for use in measuring die temperature.
PWM1, PWM2: PWM Input Pin. With RUN driven high,
SW will nominally follow this pin high, low, and high-Z.
Nominal 3V CMOS logic levels; can be driven with 3V to
5V CMOS signals. Resistor divider holds voltage at 1.7V
when in high-Z state.
PVCC: 5V Driver Supply. This pin powers the low side
gate driver directly and the high side gate driver through
an internal bootstrapped supply riding on SW. Bypass
this pin with a 10µF ceramic capacitor to PGND in close
proximity to chip.
I
, I
: Current Sense Pin. This pin sources/sinks
V : 5V Supply. Bypass this pin with a 1µF ceramic capac-
SNS1 SNS2
CC
instantaneous current equal to 1/100,000 the SW node
itor to SGND in close proximity to chip.
current, positive and negative.
V : Power Stage Supply. This pin is connected to SW
IN
FLTB1, FLTB2: Fault Bar Pin. This open-drain pin pulls
down when the chip/channel encounters a fault condition
such as OC or OCN.
through the high side N-channel FET.
SW1, SW2: Power Stage Switch Node. The output of the
power stage, this node is connected to V through the
high side N-channel FET and to PGND thIrNough the low
side N-channel FET.
TMON/FLT: Temperature Monitor/Fault Pin. This pin pro-
vides a voltage, referred to SGND, of 0.6V to 1.8V cor-
responding to die temperature of 0°C to 150°C for a gain
of 8mV/°C. Above 150°C, the pin is pulled high to indicate
an overtemperature (OT) fault. The pin has limited current
sinking capability, so multiple like pins can be tied together
for highest temperature and single-OT-fault reporting.
PGND: Power Stage Ground. This pin is connected to
SW through the low side N-channel FET. Also powers
the drivers.
SGND: Circuit Ground.
Rev. 0
8
For more information www.analog.com
LTC7050
BLOCK DIAGRAM
PV
CC
V
IN
V
CC
LG1
SD1
BST1
–
+
2.4V
HG1
LG1
PWMHI1
PWMLO1
18.8k
SW1
PWM1
CH1 LOGIC
–
+
PV
CC
9.6k
30k
1.2k
PGND
1.2V
RUN1
SDB1
SGND
TDIO
I
SNS1
I
SNS1
AMPS AND
COMPARATORS
BIAS/SUPPLY
COMPARATORS
FLTB1
FLTB2
FAULT
LOGIC
BIAS
V
CC
TMON/FLT
×1
TMON
60µA
I
SNS2
I
SNS2
AMPS AND
COMPARATORS
PV
V
IN
CC
V
CC
LG2
SD2
BST2
–
+
2.4V
PWMHI2
PWMLO2
HG2
LG2
18.8k
9.6k
SW2
PWM2
RUN2
CH2 LOGIC
–
+
PV
CC
1.2k
PGND
1.2V
SDB2
30k
7050 BD
Rev. 0
9
For more information www.analog.com
LTC7050
OPERATION
Main Control Architecture
Temperature Monitor and Overtemperature Fault
The LTC7050 is a dual-channel or dual-phase integrated-
driver half-bridge power MOSFET stage for DC/DC step-
down applications. It is designed to be used in a synchro-
nous switching architecture with a logic-level controller
providing PWM three-state control outputs. The relation-
ship between the transition thresholds and the three input
states of the LTC7050 is illustrated in Figure 1.
Normally, TMON outputs a voltage from 0.6V to 1.8V, cor-
responding to a die temperature range of 0°C to 150°C.
The TMON voltage is calculated by:
V
TMON
(V) = 800mV + (T (°C) – 25°C) • (8mV/°C)
J
Figure 2 illustrates the relationship between V
die temperature.
and
TMON
V
TMON
V
CC
TG HIGH
V
IH(TG)
TG HIGH
TG LOW
TG LOW
V
IL(TG)
1.8V
1.6V
1.4V
1.2V
1V
IN
0.8V
0.6V
BG LOW
BG HIGH
V
IL(BG)
BG LOW
BG HIGH
V
IH(BG)
0
25
50
75
100
125
150
T (°C)
J
7050 F01
7050 F02
Figure 2. VTMON vs Die Temperature
Figure 1. Three-State Input Operation
TMON is driven by an amplifier that can source current but
has limited sinking capacity. This allows multiple TMON
pins to be paralleled, with the highest temperature being
reported. Overtemperature is triggered at 150°C (typical),
and it causes the TMON pin to be pulled high to V . The
overtemperature fault will be cleared once the iCnCternal
temperature falls 20°C (typical) below the threshold.
In normal operation, PWMHI turns on the high side FET,
and PWMLO turns on the low side FET. SW node follows
the PWM pin with a typical 10ns delay. There is <1ns dead
time before SW rises from PGND to V and a typical 3ns
IN
dead time after SW falls.
The high side FET driver is powered from the internal BST
node to SW via an internal integrated switch and capacitor,
which allows lower dropout than achievable with a typical
diode as well as higher-frequency operation.
TDIO pin is internally connected to the anode of a P/N
junction diode while the cathode is connected to SGND.
It provides an alternative measurement of die temperature
for the controllers, such as LTC3884-1, to measure the
Current Sense
die temperature using direct V method or ΔV method.
BE
BE
Real-time current sense amplifiers provide a scaled-
down version of SW current. During PWMHI or PWMLO,
Voltage Fault Conditions
When V or PV is in UVLO, or V is in OVLO, SW will
the I
pin sources or sinks, according to SW current
SNS
CC
CC
IN
direction, a current equal to 1/100,000 the instantaneous
not respond to PWM and both top FET and bottom FET
are off.
SW current.
Associated current comparators flag high side FET posi-
tive overcurrent (OC) and low side FET negative overcur-
rent (OCN) conditions. Zero-current of both FETs are also
detected by associated current comparators.
When BST-to-SW voltage is in UVLO, SW will not respond
to a PWMHI until a PWMLO is provided such that BST-
to-SW voltage is recharged sufficiently.
Rev. 0
10
For more information www.analog.com
LTC7050
OPERATION
Over Current Fault Conditions
Active Diode Mode
When the high side FET is on, instantaneous SW cur-
rent of >93A (net current flowing out of SW) will trip the
overcurrent (OC) comparator and set the internal OC state.
When this happens, regardless of PWM pin state, the high
side FET will be turned off, and the low side FET will be
turned on until SW current decreases to 5A, at which point
OC state will be reset. Normal PWMHI-to-high-side-FET
and PWMLO-to-low-side-FET operation resumes.
If PWM goes from high to Hi-Z state while large (>5A)
currents are still flowing through the top FET from V to
IN
SW, the top at FET will turn off and the bottom FET will
turn on to freewheel the current until it has been ramped
down. If PWM goes from high to Hi-Z state while large
(≥8A) currents are still flowing through the top FET from
SW to V , the top FET will not turn off until the current
IN
has been ramped down.
When the low side FET is on, instantaneous SW current
of <–45A (net current flowing into SW) will trip the OCN
comparator. When this happens, regardless of PWM pin
state, the low side FET will be turned off and the high side
FET will be turned on until SW current increases to –8A,
at which point OCN state will be reset. Normal PWMHI-
to-high-side-FET and PWMLO-to-low-side-FET operation
resumes. The trigger and reset of over current condition
are illustrated in Figure 3.
Similarly, if PWM goes from low to Hi-Z state while large
(≥8A) currents are still flowing through the bottom FET
from SW to PGND, the bottom FET will turn off, and the
top FET will turn on to freewheel the current until it has
been ramped down. If PWM goes from high to Hi-Z state
while large (>5A) currents are still flowing through the
bottom FET from PGND to SW, the bottom FET will not
turn off until the current has been ramped down.
In either OC or OCN condition, FLTB is pulled down.
PWM
ON
ON
TOP FET
ON
93A
ON
BOTTOM FET
5A
I
SW
–8A
–45A
OC
OCN
7050 F03
Figure 3. Over Current Conditions
Rev. 0
11
For more information www.analog.com
LTC7050
APPLICATIONS INFORMATION
Power Sequence
the application of high frequency high current voltage
regulator. External component selection is largely driven
by the load requirement and begins with the selection
The V and PV of LTC7050 should be biased before
CC
CC
V is present and power down after V is removed. Do
IN
IN
of the switching frequency f and inductor L. Refer to
SW
not force RUN pin voltages above V voltage. Make sure
CC
Frequency Selection and Inductor Selection sections for
that the LTC7050 has been biased appropriately and the
RUN pin of LTC7050 is pulled up before enabling the
PWM controller.
the guidance. The I
current limit.
resistors are selected to set the
SNS
In high frequency high current applications, the switching
spikes coupled to the I signal may result in a reading
Fault Management
SNS
offset in heavy load range, but does not impact the ΔISNS
/
The fault management and shutdown mode of LTC7050 is
summarized in Table 1. Connecting the open-drain output
FLTB pin to the controller’s RUN pin can prevent the con-
troller from starting up and force the converter to restart
once the LTC7050 runs into fault conditions, except BST-
to-SW undervoltage fault.
ΔI gain. An optional resistor between I pin to GND
SW
SNS
can mitigate the offset. The resistor value ROS is calcu-
lated by I pin voltage (referring to GND) divided by the
SNS
offset current observed. The resistor value may be differ-
ent for a different switching frequency. This modification
does not impact the internal overcurrent protection and
negative overcurrent protection.
Table 1. Fault Management and Shutdown Mode Summary
FLTB RESPOND TO PWM TMON
1Ω
V
V
IN
OVLO
Low No, Both FETs Off
Report Temperature
V
IN
CC
PV
CC
5V
Until I = 0
SW
10µF
1µF
10µF
×10
V
UVLO
Low No, Immediate Off
Floating
CC
PV UVLO
CC
Low No, FETs Off
Report Temperature
PV
CC
V
V
IN
CC
f
: 1MHz
SW
Until I = 0.
FLTB1
SW
PWM1
Positive OC
Negative OC
Low No, Top FET
Immediate Off
Report Temperature
Report Temperature
L1
I
SNS1
180nH
+
V
OUT1
R
SW1
OS
V
1V
SNS1
RUN1
70k
Low No, Bottom FET
Immediate Off
30A
–
V
CC
LTC7050
RUN2
L2
180nH
1.5V
–
SNS2
+
Overtemperature
BST-to-SW UV
RUN Shutdown
Low Yes
Pull Up to V
.
CC
R
70k
OS
V
V
OUT2
SW2
1V
High Ignore PWMHI
Low No, Both FETs Off
Report Temperature
Floating
I
30A
SNS2
PWM2
FLTB2
TDIO PGND SGND
7050 F04
Current Sense and Current Limit
sources and sinks a current which is 1/100,000 of
Figure 4.
I
SNS
the SW current. According to the controller’s maximum
current sense signal range, select a proper resistor to
Frequency Selection
The selection of switching frequency is a trade-off
between efficiency and component size. Low frequency
operation increases efficiency by reducing FET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage. In the selection of
switching frequency, make sure that the high side on-
time at maximum input voltage is longer than LTC7050’s
minimum on-time, tON(MIN), which is the smallest time
duration that the LTC7050 is capable of turning on the
convert the I
current into a differential voltage signal
SNS
reflecting the real-time SW current. The resistor should
be biased at a low impedance common mode voltage,
which has current sinking and sourcing capability. Make
sure that at the maximum positive current and negative
current, the I
pin voltage is in the specified range so
SNS SW
SNS
that the gain I /I remains constant.
A general LTC7050 application circuit is shown on the
first page of this data sheet. LTC7050 is optimized for
top FET. It is determined by internal timing delays, power
Rev. 0
12
For more information www.analog.com
LTC7050
APPLICATIONS INFORMATION
stage timing delays and the gate charge required to turn
on the top FET. Low duty cycle applications may approach
this minimum on-time limit (see Equation 1).
the highest input voltage. To guarantee that ripple cur-
rent does not exceed a specified maximum, the inductor
should be chosen according to Equation 5.
V
⎛
⎞
V − V
VOUT
OUT
IN
OUT
(1)
t
<
ON(MIN)
L≥
•
(5)
⎜
⎟
V
• f
SW
IN
f
•IRIPPLE
V
⎝
⎠
IN
SW
Once the inductance value is determined, the type of
inductor must be selected. Core loss is independent
of core size for a fixed inductor value, but it is very depen-
dent on inductance selected. As inductance increases,
core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase. Ferrite designs have very low core loss and
are preferred at high switching frequencies, so design
goals can concentrate on copper loss and preventing sat-
uration. Ferrite core material saturates hard, which means
that inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Input Capacitors
The LTC7050 should be connected to a VIN supply through
low impedance power planes. Ceramic input capacitors
should be placed as close to the package as physically
possible, with size and quantity appropriate for tempera-
ture rise with ripple current as calculated below.
For a buck converter, the switching duty cycle can be esti-
mated by Equation 2.
V
OUT
D =
(2)
V
IN
Without considering the inductor ripple current, for each
output, the RMS current of the input capacitor can be
estimated by Equation 3.
Output Capacitors
The LTC7050 is designed for high frequency switching
and low output voltage ripple noise. The bulk output
I
OUT(MAX)
I
=
• D• 1–D
(3)
(
)
CIN(RMS)
η
capacitors defined as C
are chosen with low enough
OUT
effective series resistance (ESR) to meet the output volt-
age ripple and transient requirements. C can be a low
where η is the estimated efficiency of the power
OUT
section.
ESR tantalum capacitor, a low ESR polymer capacitor, or
ceramic capacitors. At 1MHz, the typical output capaci-
tance range is from 500µF to 1000µF. Additional output
filtering may be required by the system designer if further
reduction of output ripple or dynamic transient spikes
is required.
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency, f , directly determine
SW
the inductor’s peak-to-peak ripple current (Equation 4).
⎛
⎞
VOUT V − V
IN
OUT
Bypassing and Grounding
IRIPPLE
=
(4)
⎜
⎟
V
fSW •L
⎝
⎠
IN
The LTC7050 requires proper bypassing on the PVCC
and V supplies due to its high speed switching (nano-
seconCdCs) and large AC currents (amperes). Careless
component placement and PCB trace routing may cause
excessive ringing and under/overshoot. Follow the fol-
lowing steps to obtain the optimum performance from
the LTC7050.
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor. A reasonable starting
point is to choose a ripple current that is about 40% of
I
. Note that the largest ripple current occurs at
OUT(MAX)
Rev. 0
13
For more information www.analog.com
LTC7050
APPLICATIONS INFORMATION
• Mount the bypass capacitors as close as possible
PCB Layout
between the V and SGND pins, and the PV and
CC
CC
Due to the LTC7050’s high power density and high speed,
high frequency operation, proper PCB layout and compo-
sition are critical to maximizing performance.
PGND pins. The traces should be shortened as much
as possible to reduce lead inductance.
• Use a low inductance, low impedance ground plane
to reduce any ground drop and stray capacitance. Any
significant ground drop will degrade signal integrity.
At a minimum, the PCB should be 4-layer with at least top
and bottom layers 2oz. copper. As much as possible, top
and bottom layers should be continuous V and PGND
areas. At least one inner layer, preferablyINthe second,
should be a continuous PGND plane.
• Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain separate ground return paths for
the input pin and the output power stage.
Copper-filled vias should be used under the package
exposed pads to connect top and bottom PCB layers.
• Be sure to solder the Exposed Pad on the back side of
the LTC7050 packages to the board. Failure to make
good thermal contact between the exposed back side
and the copper board will result in far greater thermal
resistances.
θ
is <1°C /W. Anything less than copper-filled vias
JCbottom
will compromise θ greatly.
JA
The inductor pads should be placed as close as possible
to the package, with traces as short and wide as possible.
If possible, SW traces should be doubled up with the
second layer, taking care not to couple to sensitive traces.
A recommended PCB layout is shown in Figure 5b.
C7
C6
C5
V
PGND
IN
TMON
PWM2
FLTB2
C3
L2
I
SW2
SNS2
RUN2
C13
C14
5V
PV
CC
R1
C2
V
OUT
LTC7050
V
CC
C1
SGND
L1
SW1
RUN1
C11
C12
I
SNS1
FLTB1
PWM1
TDIO
V
PGND
IN
(b) Example PCB Layout
C4
7050 F4a
C8
C9
C10
(a) Schematic
Figure 5.
Rev. 0
14
For more information www.analog.com
LTC7050
PACKAGE DESCRIPTION
Y
X
Z
M c c c
d d d
Z
Z
× 4 2
Z
Z
M
M
f f f
e e e
4 2 b
Y
X
Z
/ / b b b
Z
1 . 5 0
1 . 0 0
0 . 0 0 0
0 . 5 0
1 . 0 0
2 . 0 0
a a a
Z
× 2
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
15
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC7050
TYPICAL APPLICATIONS
LTC7050 and LTC3884-1 Schematic
V
IN
7V TO 14V
INTV
CC
1Ω
V
4.7µF
10µF
×10
CC
VDD33
PV
CC
5V
1µF
10µF
1µF
10k
V
INTV
VDD33
IN
CC
ITHR0
PV
V
V
IN
f
: 575kHz
CC
CC
SW
RUN0
FLTB1
6.8nF
L1, L2: FP1007R3-R22-R
ITH0
PWM0
PWM1
100pF
+
I
I
SENSE0
L1
SENSE1
C7
R5
215nH
10pF
V
+
OUT1
V
43.2k
V
OUT1
SENSE0
SW1
150k
3.3nF
1V/30A
SW1
–
V
1µF
SENSE0
47µF
×2
470µF
×2
–
I
SENSE0
RUN1
SDA
SCL
ALERT
2.61k
1k
LTC7050
PMBus
INTERFACE
LTC3884-1
V
CC
INTV
CC
RUN2
L2
–
I
SENSE1
215nH
10pF
V
FAULT0
FAULT1
43.2k
OUT2
SW2
150k
1.8V/30A
3.3nF
SW2
–
47µF
×2
470µF
×2
+
V
SENSE1
I
I
SENSE1
PWM1
RUN1
SENSE2
+
V
V
PWM2
SENSE1
OUT2
ITH1
FLTB2
TDIO
PGND
SGND
100pF
10k
VDD33
ITHR1
PGND SGND
TSNS0
6.8nF
10nF
7050 TA02
PINS NOT SHOWN IN LTC3884-1 CIRCUIT: PGOOD0, PGOOD1, TSNS1,
SYNC, ASEL0, ASEL1, VOUT0_CFG, VOUT1_CFG, FREQ_CFG,PHASE_CFG
PINS NOT SHOWN IN LTC7050 CIRCUIT: TMON
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC7051
SilentMOS Smart Power Stage in 5mm × 8mm LQFN
140A Peak Current, Silent Switcher 2 Architecture, V Up to
IN
14V, 5mm × 8mm LQFN Package
LTC7050-1
LTC7051-1
Dual SilentMOS Smart Power Stage in 5mm × 8mm LQFN
SilentMOS Smart Power Stage in 5mm × 8mm LQFN
70A Peak Current per Channel, Silent Switcher 2 Architecture,
IN
V
Up to 16V, 5mm × 8mm LQFN Package
140A Peak Current, Silent Switcher 2 Architecture, V Up to
IN
16V, 5mm × 8mm LQFN Package
2
LTC3888/LTC3888-1 Dual Output 8-Phase Step-Down DC/DC Controller with Digital
Power System Management
4.5V ≤ V ≤ 26.5V, 0.3V ≤ V
≤ 3.45V, I C/PMBus Control,
IN
OUT
Programmable Loop Compesation, 5mm × 8mm QFN-52
LTC3884/LTC3884-1 Dual Output PolyPhase® Step-Down Controller with Sub-
4.5V ≤ V ≤ 38V, 0.5V ≤ V
≤ 5.5V, I C/PMBus Control,
2
IN
OUT
Milliohm DCR Sensing and Digital Power System Management Programmable Loop Compesation, 5mm × 8mm QFN-52
LTC7851
Quad Output Multiphase Step-Down Voltage Mode DC/DC
Controller with Accurate Current Sharing
Operates with DrMOS, Power Blocks or External Drivers/
MOSFETs, V Range Depends on External Components,
IN
4.5V≤ V ≤ 5.5V, 0.6V ≤ V
≤ V –0.5V
CC
CC
OUT
LTC7852/LTC7252-1 Dual Output 6-Phase Current Mode Synchronous Buck
Controller with Current Monitoring
Operates with DrMOS, Power Blocks, 0.5V ≤ V
≤ 2V, Hiccup
OUT
Mode Overcurrent Protection, Flexible Phase Configuration
LTC3861
Dual, Multiphase Step-Down Voltage Mode DC/DC Controller
with Accurate Current Sharing
Operates with Power Blocks, DrMOS or External MOSFETs
3V≤ V ≤ 24V
IN
LTC3882/LTC3882-1 Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Digital Power System Management
3V ≤ V ≤ 38V, 0.5V ≤ V
≤ 5.25V, 0.5% V
Accuracy
IN
OUT1,2
OUT
2
I C/PMBus Interface, uses DrMOS or Power Blocks
LTC3887/LTC3887-1 Dual Output Multiphase Step-Down DC/DC Controller with
Digital Power System Management, 70mS Start-Up
4.5V ≤ V ≤ 24V, 0.5V ≤ V
( 0.5%) ≤ 5.5V, 70mS Start-Up,
IN
OUT0,1
2
I C/PMBus Interface, –1 Version uses DrMOS or Power Blocks
Rev. 0
09/21
www.analog.com
16
ANALOG DEVICES, INC. 2021
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