LTC7801_技术文档

LTC7883

Quad Output PolyPhase

Step-Down DC/DC Voltage Mode Controller

with Digital Power System Management

FEATURES

DESCRIPTION

2

The LTC^®7883 is a quad, PolyPhase DC/DC synchronous

step-down switching regulator controller with PMBus

compliant serial interface. It uses a constant frequency,

leading-edge modulation, voltage mode architecture for

excellent transient response and output regulation. Each

PWM channel can produce output voltages from 0.1V

to 5.25V using a wide range of 3.3V compatible power

stages, including power blocks, DrMOS or discrete FET

drivers. LTC7883 devices can operate in parallel, sup-

porting ideal phasor positioning for PolyPhase rails up

to 8-phases.

n

PMBus/I C Compliant Serial Interface

n

Monitor Voltage, Current, Temperature and Faults

n

Program Voltage, Soft-Start/Stop, Sequencing,

Margining, AVP and UV/OV/OC Limits

n

3V ≤ VINSNS ≤ 38V, 0.1V (Limited by DrMOS

t

) ≤ V

≤ 5.25V

ON_MIN

OUT

n

0.5ꢀ Output Voltage Error

Programmable PWM Frequency or External Clock

Synchronization from 250kHz to 2.5MHz

Accurate PolyPhase^®Current Sharing

Internal EEPROM with Fault Logging and ECC

IC Supply Range: 3V to 13.2V

Resistor or Inductor DCR Current Sensing

Power Good Output Voltage Monitor

Supports Start-Up Into a Prebiased Load

Optional Resistor Programming for Key Parameters

99-Lead BGA Package (9mm × 7.5mm)

n

System configuration and monitoring is supported by the

LTpowerPlay^®software tool. The LTC7883 serial interfaces

can read back input voltage, output voltage and current,

temperature and fault status. Most operating parameters

can be set via the digital interfaces or stored in internal

EEPROM for use at power-up. Switching frequency and

phase, output voltage and device address can also be set

using external configuration resistors.

APPLICATIONS

n

High Current Distributed Power Systems

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. patents, including 5396245, 5859606, 6144194, 6937178, 7420359 and 7000125.

n

Servers, Network and Storage Equipment

n

Intelligent Energy Efficient Power Regulation

TYPICAL APPLICATION

V

IN

7V TO 13.2V

V

VINSA

CCA

V

SNSA0P

FBA0

V

FDMF5820DC

PWM

IN

Load Step Transient Current Sharing

1/2 LTC7883

L0

V

(Using FDMF5820DC DrMOS)

SDA_A

SCL_A

ALERTA

RUNA0

RUNA1

OUT

SW

1V

COMPA0

COMPA1

PWMA0

TSNSA0

100A

TO/FROM

MCU

I

OUT

10A/DIV

GND

PGA0

FLTA0

CSA0P

CSA0M

TO/FROM

PGA1

V

SNSA1P

EXTERNAL DEVICES

FLT1A1

SYNCA

CLKA

CSA1M

CSA1P

I

, I

L0 L1

10A/DIV

FDMF5820DC

PWM

V

IN

7883 TA01b

L1

IAVGA0

IAVGA1

50µs/DIV

SW

PWMA1

TSNSA1

IAVGNDA

GND

V

SNSA0M

SNSA1M

7883 TA01a

GND

INDUCTORS: COOPER FP1007R1-R22

SOME DETAILS OMITTED FOR CLARITY

Rev. 0

1

Document Feedback

For more information www.analog.com

LTC7883

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

V

Supply.......................................... –0.3V to 15V

CC[A/B]

1

2

3

4

5

6

7

8

9

10 11

PIN 1

A

VINS[A/B] .................................................. –0.3V to 40V

V

.............................................. –0.3V to 1V

SNS[A/B][1:0]M

B

C

D

E

F

, CS[A/B][1:0]P/M................... –0.3V to 6V

SNS[A/B][1:0]P

FB[A/B][1:0], COMP[A/B][1:0],

TSNS[A/B][1:0], IAVGND[A/B],

IAVG[A/B][1:0] ...................................... –0.3V to 3.6V

SYNC[A/B], FLT[A/B][1:0], WP[A/B],

PG[A/B][1:0], SHCLK[A/B].................... –0.3V to 3.6V

SCL[A/B], SDA[A/B], RUN[A/B][1:0],

ALERT[A/B]............................................ –0.3V to 5.5V

ASEL0[A/B], ASEL1[A/B],

G

H

J

BGA PACKAGE

99-LEAD (9mm × 7.5mm × 1.29mm)

= 125°C, θ = 32°C/W,

VO[A/B][1:0]CFG, FCFG[A/B],

PCFG[A/B] .......................................... –0.3V to 2.75V

T

JMAX

JA

θ

= 17°C/W, θ

= 12.1°C/W, θ = 14.5°C/W,

JCbottom JB

JCtop

PWM[A/B][1:0], V

DD33[A/B]

.............................. (Note 13)

DD25[A/B]

WEIGHT = TBDg,

θ VALUES DETERMINED PER JEDEC 51-9, 51-12

V

........................................................ (Note 14)

Operating Junction Temperature

(Notes 2, 3)...................................... –40°C to 125°C*

Storage Temperature Range ............ –65°C to 150°C*

Absolute Maximum Junction Temperature ....... 125°C

*See Derating EEPROM Retention at Temperature in the

Applications Information section for junction tempera-

tures in excess of 125°C.

ORDER INFORMATION

PART MARKING*

MSL

PACKAGE

TYPE

OPERATING JUNCTION

TEMPERATURE RANGE

PART NUMBER

PAD OR BALL FINISH

DEVICE

FINISH CODE

RATING

LTC7883AY#PBF

SAC305 (RoHS)

LTC7883Y

e1

BGA

–40°C to 125°C

3

• Contact the factory for parts specified with wider operating temperature • Recommended LGA and BGA PCB Assembly and Manufacturing

ranges. *The temperature grade is identified by a label on the shipping

container.

• Pad or ball finish code is per IPC/JEDEC J-STD-609.

Procedures

• LGA and BGA Package and Tray Drawings

Rev. 0

2

For more information www.analog.com

LTC7883

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_J= 25°C (Note 2). Specifications apply to both units with V_CC= 5V,

V_SNSP= 1.8V, V_SNSM= IAVGND = GND = 0V, f_SYNC= 500kHz (externally driven) unless otherwise specified.

SYMBOL

IC Supply

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

V

Voltage Range

V

= Internal LDO

4.5

3

13.8

3.6

3

V

CC

DD33

l

Voltage Range

= V

(Note 6)

DD33

DD33_EXT

UVLO

DD33

CC

Undervoltage Lockout Threshold

Rising

Hysteresis

V

mV

DD33

42

32

35

I

t

IC Operating Current

per Unit

mA

ms

Q

Controller Initialization Time

Delay from RESTORE_USER_ALL, MFR_RESET or V

DD33

> V

INIT

Until TON_DELAY Can Begin

UVLO

V

Linear Regulators

DD33

V

Regulator Output Voltage

Current Limit

V

≥ 4.5V

3.2

3.3

3.4

V

DD33

CC

I

V

DD33

V

DD33

= 2.8V

= 0V

85

40

mA

V

Linear Regulators

DD25

V

Regulator Output Voltage

Current Limit

2.25

3

2.5

95

2.75

38

V

DD25

I

mA

PWM Control Loops

VINS

V

IN

Sense Voltage Range

V

R

VINS Input Resistance

Range 0 Maximum V

278

kΩ

VINS

V

5.25

V

%

mV

OUT_R0

OUT

l

Range 0 Set Point Error (Note 7)

Range 0 Set Point Resolution

0.6V ≤ V

≤ 5V

–0.5

0.5

OUT

1.375

2.65

V

Range 1 Maximum V

V

%

mV

OUT_R1

VSNS

OUT

Range 1 Set Point Error (Note 7)

Range 1 Set Point Resolution

≤ 2.5V

0.6875

I

V

Input Current

V

SNSP

V

SNSM

= 5.5V

= 0V

235

–335

µA

SNS

V

Line Regulation, No Output Servo 4.5V ≤ V ≤ 13.2V (See Test Circuit)

–0.02

0.02

–96

%/V

mV

LINEREG

CC

AVP

AVP ∆V

AVP = 10%, VOUT_COMMAND = 1.8V,

CS Differential Step 3mV to 12mV

with IOUT_OC_WARN_LIMIT = 15mV

–118 –108

OUT

A

Error Amplifier Open-Loop Voltage Gain

Error Amplifier Slew Rate

87

9.5

30

dB

V/µs

MHz

V(OL)

SR

f

I

Error Amplifier Bandwidth

(Note 12)

0dB

Error Amplifier Output Current

Sourcing

Sinking

–2.6

34

mA

COMP

l

R

VSFB

Resistance Between V

and FB

Range 0

Range 1

52

37

67

49

83

61

kΩ

SNSP

V

CS Differential Input Range

CSP/M Input Current

70

0.1

175

mV

µA

ISENSE

I

0V ≤ V ≤ 5.5V

–1

1

ISENSE

IAVG Current Sense Offset

Referred to CS Inputs

µV

AVG_VOS

–600

650

V

Slave Current Sharing Offset

SYNC Frequency Error

Referred to CS Inputs

300

µV

SIOS

–800

–10

700

10

l

f

250kHz ≤ f

≤ 1.25MHz

SYNC

%

SYNC

Rev. 0

3

For more information www.analog.com

LTC7883

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). Specifications apply to both units with V_CC= 5V,

V_SNSP= 1.8V, V_SNSM= IAVGND = GND = 0V, f_SYNC= 500kHz (externally driven) unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Input Voltage Supervisor

l

V

Input ON/OFF Threshold Error

15V ≤ V

≤ 35V

IN_ON

–2

2

%

ON_TOL

N

Input ON/OFF Threshold Resolution

143

5.5

mV

VON

Output Voltage Supervisors

V

Range 0 Maximum Threshold

Range 0 Error

Range 0 Threshold Resolution

Range 0 Threshold Hysteresis

V

%

mV

UVOV_R0

l

2V ≤ V

1V ≤ V

≤ 5V (Falling for UV and Rising for OV)

≤ 2.5V (Falling for UV and Rising for OV)

–1

1

OUT

11

50

Range 1 Maximum Threshold

Range 1 Error

Range 1 Threshold Resolution

Range 1 Threshold Hysteresis

2.75

V

%

mV

UVOV_R1

5.5

25

Output Current Supervisors

l

V

Output Current Limit Tolerance

CSP – CSM

15mV < CSP – CSM ≤ 30mV

30mV < CSP – CSM ≤ 50mV

50mV < CSP – CSM ≤ 70mV

–1.7

–2.5

–5.2

1.7

2.5

5.2

mV

ILIM_TOL

N

CSP – CSM Threshold Resolution

1LSB

0.4

10

mV

lLIM

ADC Readback Telemetry (Note 8)

N

VIN

VINS Readback Resolution

(Note 9)

Bits

V

VINS Total Unadjusted Readback Error 4.5V ≤ VINS ≤ 38V

0.5

2

%

IN_TUE

l

N

PWM Duty Cycle Resolution

(Note 9)

10

Bits

%

DC

PWM Duty Cycle Total Unadjusted

Readback Error

PWM Duty Cycle = 12.5%

–2

2

TUE

N

V

Readback Resolution

244

0.2

µV

VOUT

OUT

V

Total Unadjusted Readback Error 0.6V ≤ V

≤ 5.5V, Constant Load

%

OUT_TUE

OUT

l

–0.5

0.5

N

ISENSE

I

Readback Resolution

(Note 9)

10

15.625

31.25

62.5

Bits

µV

OUT

LSB Step Size (at I

)

0mV ≤ |CSP – CSM| < 16mV

16mV ≤ |CSP – CSM| < 32mV

32mV ≤ |CSP – CSM| < 63.9mV

63.9mV ≤ |CSP – CSM| ≤ 70mV

SENSE

125

l

I

Total Unadjusted Readback Error

Zero-Code Offset Voltage

|CSP – CSM| ≥ 6mV, 0V ≤ V ≤ 5.5V

OUT

1

32

%

µV

°C

SENSE_TUE

OUT

SENSE_OS

OUT

N

Temperature Resolution

External Temperature Total Unadjusted TSNS ≤ 1.85V (Note 10)

Readback Error

0.25

TEMP

T

EXT_TUE

l

MFR_PWM_MODE_LTC3882-1[6] = 0

MFR_PWM_MODE_LTC3882-1[6] = 1

–3

–7

3

7

°C

T

Internal Temperature Total Unadjusted Internal Diode (Note 10)

Readback Error

1

°C

INT_TUE

t

Update Rate

(Note 11)

90

ms

CONVERT

Internal EEPROM (Notes 4, 6)

Endurance

Retention

Number of Write Operations

Stored Data Retention

0°C ≤ T ≤ 85°C During All Write Operations

10,000

10

Cycles

Years

s

J

T ≤ 125°C

J

Mass Write Time STORE_USER_ALL Execution Duration 0°C ≤ T ≤ 85°C During All Write Operations

0.2

2

J

Rev. 0

4

For more information www.analog.com

LTC7883

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). Specifications apply to both units with V_CC= 5V,

V_SNSP= 1.8V, V_SNSM= IAVGND = 0V, f_SYNC= 500kHz (externally driven) unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Digital Inputs (SCL, SDA, RUN, FLT, SYNC, SHCLK, WP)

l

V

Input High Voltage

Input Low Voltage

SCL, SDA, RUN, FLT

1.35

1.8

V

IH

SYNC, SHCLK, WP

l

SCL, SDA, RUN, FLT

SYNC, SHCLK, WP

0.8

0.6

V

IL

Input Hysteresis

SCL, SDA

80

10

mV

µA

pF

HYST

LKG

I

Input Pull-Up Current

Input Capacitance

WP = 0V

C

IN

SCL, SDA, RUN, FLT, SYNC, SHCLK (Note 12)

10

t

Input Digital Filter Delay

FLT

RUN

3

10

µs

FILT

Digital Outputs (SCL, SDA, RUN, FLT, SYNC, SHCLK, ALERT, PWM, PG)

l

V

OL

Output Low Voltage

I

= 3mA; SCL, SDA, RUN, FLT, SYNC, SHCLK, ALERT

= 2mA; PWM, PG

0.2

0.4

0.3

V

SINK

l

V

PWM Output High Voltage

Output Leakage Current

I

= 2mA

2.7

V

OH

SOURCE

I

0V ≤ PWM, PG ≤ V

–1

–5

1

5

µA

LKG

DD33

0V ≤ FLT, SYNC, SHCLK ≤ 3.6V

0V ≤ RUN ≤ 5.5V

l

0V ≤ SCL, SDA, ALERT ≤ 5.5V

–5

5

µA

ns

t

PWM Output Rise Time

PWM Output Fall Time

C

= 30pF, 10% to 90%

= 30pF, 90% to 10%

5

4

RO

LOAD

FO

Serial Bus Timing

l

f

t

Serial Bus Operating Frequency

10

1.3

0.6

400

kHz

µs

SMB

Bus Free Time Between Stop and Start

BUF

Hold Time After (Repeated) Start

Condition. After This Period, the First

Clock Is Generated

µs

HD,STA

l

t

Repeated Start Condition Setup Time

Stop Condition Setup Time

0.6

µs

SU,STA

SU,STO

HD,DAT

Data Hold Time:

Receiving Data

Transmitting Data

l

0

0.3

ns

µs

0.9

l

t

Input Data Setup Time

Clock Low Timeout

100

25

ns

ms

µs

SU,DAT

TIMEOUT

LOW

35

Serial Clock Low Period

Serial Clock High Period

1.3

0.6

10000

µs

HIGH

Rev. 0

5

For more information www.analog.com

LTC7883

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: Minimum EEPROM endurance, retention and mass write time

specifications apply when writing data with 3.15V ≤ V

≤ 3.45V.

DD33

EEPROM read commands are valid over the entire specified V

operating range.

DD33

Note 2: The LTC7883 is specified over the –40°C to 125°C operating

junction temperature range. High Junction temperatures degrade operating

lifetimes; operating lifetime is derated for junction temperatures greater

than 125°C. Note the maximum ambient temperature consistent with

these specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal impedance and

other environmental factors.

Note 7: Specified V

set with MFR_PWM_MODE_LTC3882-1 command bit 6. Performance is

guaranteed by testing the LTC7883 in a feedback loop that servos V

a specified value.

Note 8: ADC tested with PWMs disabled. Comparable capability

error with AVP = 0% requires servo mode to be

OUT

to

OUT

demonstrated by in-circuit evaluations. Total Unadjusted Error includes all

gain and linearity errors, as well as offsets.

Note 3: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 4: EEPROM endurance, retention and mass write times are

guaranteed by design, characterization and correlation with statistical

process controls. Minimum retention applies only for devices cycled less

than the minimum endurance specification. EEPROM read commands

(e.g. RESTORE_USER_ALL) are valid over the entire specified operating

junction temperature range.

Note 9: Internal 32-bit calculations using 16-bit ADC results are limited to

10-bit resolution by PMBus Linear 11-bit data format.

Note 10: Limits guaranteed by TSNS voltage and current measurements

during test, including ADC readback.

Note 11: Data conversion is done in round robin fashion. All inputs signals

are continuously scanned in sequence resulting in a typical conversion

latency of 90ms.

Note 12: Guaranteed by design.

Note 13: Do not apply a voltage or current source directly to these pins.

They should only be connected to passive RC loads, otherwise permanent

damage may occur.

Note 14: Do not apply a voltage source to this pin unless shorted to V

.

CC

Note 5: All currents into device pins are positive; all currents out of

device pins are negative. All voltages are referenced to GND unless

otherwise specified.

See Electrical Characteristics for applicable limits beyond which permanent

damage may occur.

Rev. 0

6

For more information www.analog.com

LTC7883

TYPICAL PERFORMANCE CHARACTERISTICS

Typical LTC78883 Output Voltage

Distribution at 105°C

LTC7883 1.0V Regulated Output

vs Temperature

Typical LTC7883 Output Voltage

Distribution at 0°C

1.001

1.0005

1.0

1000

900

800

700

600

500

400

300

200

100

0

1200

1000

800

600

400

200

0

1078 UNITS

VOUT_COMMAND = 1.0V

DIGITAL SERVO

V

= 12V

1094 UNITS

IN

VOUT_COMMAND = 1.0V

DIGITAL SERVO ENGAGED

VOUT_COMMAND = 1.0V

DIGITAL SERVO

ENGAGED

I

= 6.5A

OUT

0.9995

0.999

0.9985

–5

15

35

55

75

95

–1.25 –1 –0.75–0.5–0.25 0 0.25 0.5 0.75

ERROR (mV)

1

1.25

–2.5 –2 –1.5 –1 –0.5

0

0.5

1

1.5

2

2.5

T

(°C)

V

OUT

ERROR (mV)

A

OUT

7883 G01

7883 G02

7883 G03

Efficiency vs Load Current

(1-Phase Using D12S1R880A

Power Block)

Efficiency and Loss vs Load

(2-Phase Using FDMF5820DC

DrMOS)

Efficiency and Loss vs Load

(4-Phase Using LTC7051)

92

91

90

89

88

87

86

85

84

83

82

81

80

13

95

90

85

80

75

95

90

85

80

75

70

65

60

51

44

37

30

23

16

9

V

= 12V

IN

11

9

EFFICIENCY

EFFICIENCY 500kHz

EFFICIENCY 1MHz

POWER LOSS 500kHz

POWER LOSS 1MHz

7

3.3V

2.5V

1.8V

1.5V

1.2V

1.0V

5

POWER LOSS

V

= 12V

= 1V

3

IN

OUT

V

= 12V

= 1V

IN

OUT

SYNC = 500kHz

1

2

0

10 20 30 40 50 60 70 80

0

10

20

30

40

0

20 40 60 80 100 120 140 160 180 200

LOAD CURRENT (A)

7883 G04

7883 G05

7883 G06

Typical Distribution of Slave

I_OUTOffset (Not Including DCR

Mismatch)

Typical Distribution of Slave

I_OUTOffset (Not Including DCR

Mismatch)

Typical Distribution of Slave

I_OUTOffset (Not Including DCR

Mismatch)

4000

3500

3000

2500

2000

1500

1000

500

3500

3000

2500

2000

1500

1000

500

4500

4000

3500

3000

2500

2000

1500

1000

500

9595 UNITS

8593 UNITS

11783 UNITS

FROM 3 LOTS

T

= –40°C

= –22°C

T

= 38°C

T = 121°C

A

J

CHO MASTER

0

–400–300–200–100

0

100 200 300 400

–400–300–200–100

0

100 200 300 400

–300–200–100

CH1 I OFFSET TO IDEAL (µV)

SENSE

7883 G09

0

100 200 300 400 500

CH1 I

OFFSET TO IDEAL (µV)

CH1 I

OFFSET TO IDEAL (µV)

SENSE

7883 G07

7883 G08

Rev. 0

7

For more information www.analog.com

LTC7883

TYPICAL PERFORMANCE CHARACTERISTICS

3-Phase DC Output Current

Sharing (Using D12S1R845A

Power Block

Load Step Transient Current

Sharing (Using FDMF6707B

DrMOS)

Load Dump Transient Current

Sharing (Using FDMF6707B

DrMOS)

20

18

16

14

12

10

8

CHANNEL 1

CHANNEL 2

CHANNEL 3

I

OUT

20A/DIV

V

OUT

V

20mV/DIV

OUT

20mV/DIV

I

, I

I

, I

L1 L2

10A/DIV

6

7883 G11

7883 G12

4

V

= 1V

5µs/DIV

V

= 1V

5µs/DIV

OUT

IN

OUT

IN

= 12V

2

SYNC = 500kHz

L = 320nH

SYNC = 500kHz

L = 320nH

0

10 20 30 40 50 60 70 80

TOTAL RAIL CURRENT (A)

7883 G10

Efficiency and Power Loss vs

Input Voltage

(1-Phase Using LTC4449)

1-Phase Single Cycle Response

(Using D12S1R860A Power Block

with C_OUT= 6 × 100µF X5R 1210)

3-Phase Transient Response

(Using D12S1R860A Power Block)

100

98

96

94

92

90

88

86

84

82

80

3.0

2.5

2.0

1.5

V

= 1.8V

O

V

OUT

(20mV/DIV)

I

OUT

(10A/DIV)

V

SW

(10V/DIV)

V

OUT

(10mV/DIV)

25mV

P-P

I

1.0

OUT

(10A/DIV)

7883 G14

7883 G15

0.5

0

100µs/DIV

2µs/DIV

POWER FET: BSC050N04LS G

SYNC FET: BSC010N04LS

V

= 0.9V/90A

V

= 1V/25A

OUT

IN

= 12V

V

= 12V

IN

5

10

15

V

20

(V)

25

30

SYNC = 500kHz

L = 210nH

SYNC = 1MHz

L = 210nH

IN

7883 G13

3+1 Channel Crosstalk

(Using D12S1R845A Power

Blocks)

Load Step Transient Response

Using AVP

Line Step Transient Response

(1-Phase Using LTC4449)

V

OUT0

I

O

(1-PHASE)

20mV/DIV

10A/DIV

7V

V

IN

2V/DIV

V

OUT1

(3-PHASE)

20mV/DIV

1.8V

25%

LOAD STEP

I

OUT1

V

10A/DIV

OUT

V

OUT

50mV/DIV

10mV/DIV

7883 G16

7883 G17

7883 G18

100µs/DIV

200µs/DIV

Rev. 0

8

For more information www.analog.com

LTC7883

TYPICAL PERFORMANCE CHARACTERISTICS

Soft-Start Ramp

Start-Up Into a Prebiased Load

Soft-Off Ramp

RUN

2V/DIV

V

OUT

0.5V/DIV

0V

V

OUT

I

, I

I , I

L1 L2

10A/DIV

L1 L2

1V/DIV

10A/DIV

7883 G19

7883 G20

7883 G21

V

IN

= 12V

1ms/DIV

V

IN

= 12V

1ms/DIV

5ms/DIV

TOFF_DELAY = 10ms

TOFF_FALL = 5ms

Regulated Output vs Temperature

VOUT_COMMAND INL

VOUT_COMMAND DNL

1.8000

1.7995

1.7990

1.7985

1.7980

1.7975

1.7970

1.5

1.0

0.5

0

1.0

0.8

VOUT_COMMAND = 1.8V

DIGITAL SERVO OFF

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–0.5

–1.0

–40 –20

0

20 40 60 80 100 120

0.3

1.1

1.9

2.7

3.5

(V)

4.3

5.1

0.3

1.1

1.9

2.7

3.5

(V)

4.3

5.1

TEMPERATURE (°C)

V

OUT

7883 G22

7883 G23

7883 G24

Output Overvoltage Threshold

Error vs Temperature

Output Overcurrent Threshold

Error vs Temperature

PWM Frequency vs Temperature

0.10

0.05

0

1.2

1.0

0.8

0.6

0.4

0.2

0

500.2

500.1

500.0

499.9

499.8

499.7

499.6

499.5

–0.05

–0.10

–0.15

–0.2

VOUT_OV_FAULT_LIMIT = 2V

V

RANGE = 1

FREQUENCY_SWITCH = 500kHz

OUT

–0.4

–40 –20

0

20 40 60 80 100 120

–40 –20

0

20 40 60 80 100 120

–40 –20

0

20 40 60 80 100 120

TEMPERATURE (°C)

7883 G25

7883 G26

7883 G27

Rev. 0

9

For more information www.analog.com

LTC7883

TYPICAL PERFORMANCE CHARACTERISTICS

VINS ADC TUE

V_OUTADC TUE

I_OUTADC TUE

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

0.40

0.30

0.20

0.10

0

8

6

4

2

0

–0.10

–0.20

–0.30

–0.40

–2

–4

–6

–8

0

5

10 15 20 25 30 35 40

0.5

1

1.5

2

2.5

V

3

3.5

(V)

4

4.5

5

5.5

0

5

10

OUTPUT CURRENT (A)

15

20

VINSNS (V)

OUT

7883 G28

7883 G29

7883 G30

IC Operating Current vs

Temperature

Temperature ADC TUE

SHCLK Frequency vs Temperature

1.0

0.8

31.0

30.8

30.6

30.4

30.2

30.0

29.8

29.6

29.4

110

105

100

95

V

CC

= 14V

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

90

–40 –20

0

20 40 60 80 100 120

–50 –30 –10 10 30 50 70 90 110

–45 –25 –5 15 35 55 75 95 115

TEMPERATURE (°C)

ACTUAL TEMPERATURE (°C)

7883 G33

7883 G32

7883 G31

Rev. 0

10

For more information www.analog.com

LTC7883

LTC7883 PIN (BALL) ASSIGNMENTS

PIN NAME

BALL

A1

A2

UNIT A

UNIT B

BALL

E6

E7

UNIT A

GND

UNIT B

GND

V

SNSA1P

SNSA1M

SNSA0M

V

A3

E8

GND

A4

V

E9

GND

SNSA0P

A5

A6

A7

A8

ALERTA

E10

E11

F1

F2

F3

F4

F5

F6

F7

V

DD25B

V

IAVGNDB

CCA

ALERTB

COMPA1

FBA1

V

SNSB1P

SNSB1M

SNSB0M

A9

V

DD33A

A10

A11

B1

SHCLKA

V

SHCLKB

GND

SNSB0P

ASELA1

ASELA0

GND

WPA

B2

B3

B4

B5

B6

ASELB1

ASELB0

GND

F8

F9

F10

F11

WPB

V

DD33B

GND

FBB0

COMPB0

V

CCB

B7

B8

B9

B10

B11

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

E1

GND

RUNA0

RUNA1

GND

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

J1

COMPA0

FBA0

PGA0

PGA1

GND

RUNB0

RUNB1

GND

PGB0

PGB1

FBB1

SDA_A

GND

SDA_B

GND

PCFGA

FCFGA

GND

COMPB1

GND

PCFGB

VOB1CFG

GND

CSA1M

IAVGA0

IAVGA1

TSNSA1

TSNSA0

VINSA

GND

SCL_A

SCL_B

FLTA1

FLTA0

IAVGB0

IAVGB1

TSNSB1

TSNSB0

PWMB0

FLTB1

FLTB0

VOA0CFG

GND

FCFGB

VOB0CFG

GND

CSA1P

PWMA1

CSA0M

CSA0P

J2

J3

J4

J5

J6

J7

J8

J9

GND

SYNCA

SYNCB

PWMA0

IAVGNDA

VINSB

CSB1M

CSB1P

PWMB1

CSB0M

CSB0P

E2

E3

E4

E5

E6

E7

V

DD25A

VOA1CFG

GND

J10

J11

Rev. 0

11

For more information www.analog.com

LTC7883

PIN FUNCTIONS

PWM switching frequency with a 125ns pulse width. A

pull-up resistor to 3.3V is required in the application if

SYNC is driven by any LTC7883. Minimize the capacitance

on this line to ensure its time constant is fast enough for

the application.

COMP[A/B][1:0]: Error Amplifier Outputs. PWM duty

cycle increases with this control voltage. These are true

low impedance outputs and cannot be directly connected

together when active. For PolyPhase operation, wiring

FB to V

will three-state the error amplifier output of

DD33

that channel, making it a slave. PolyPhase control is then

implemented in part by connecting all slave COMP pins

together to one master error amplifier output.

SCL[A/B]: Serial Bus Clock Input. A pull-up resistor to

3.3V is required in the application.

SDA[A/B]: Serial Bus Data Input and Output. A pull-up

resistor to 3.3V is required in the application.

TSNS[A/B][1:0]: External Temperature Sense Inputs. The

LTC7883 supports two methods of calculation of exter-

nal temperature based on forward-biased P/N junctions

between these pins and GND.

ALERT[A/B]: Open-Drain Status Output. This pin may

be connected to the system SMBALERT wire-AND inter-

rupt signal and should be left open if not used. If used, a

pull-up resistor is required in the application. Operating

VINS[A/B]: V Supply Sense. Connect to the V power

IN

supply to provide line feedforward compensation. A

change in V_INimmediately modulates the input to the

PWM comparator and inversely changes the pulse width

to provide excellent transient line regulation and fixed

modulator voltage gain. An external lowpass filter can be

added to this pin to prevent noisy signals from affecting

the loop gain.

voltage range is GND to V

.

DD33

FLT[A/B][1:0]: Programmable Digital Inputs and Open-

Drain Outputs for Fault Sharing. Used for channel-to-chan-

nel fault communication and propagation. These pins

should be left open if not used. If used, a pull-up resistor

to 3.3V is required in the application.

RUN[A/B][1:0]: Run Control Inputs and Open-Drain

Outputs. A voltage above 2V is required on these pins

to enable the respective PWM channel. The LTC7883 will

drive these pins low under certain reset/restart conditions

regardless of any PMBus command settings. A pull-up

resistor to 3.3V is required in the application.

IAVGND[A/B]: IAVG Ground Reference. The same IAVGND

should be shared between all channels of a PolyPhase

rail and connected to system ground at a single point.

IAVGND may be wired directly to GND on units that do

not share phases with other units.

PG[A/B][1:0]: Power Good Indicator Open-Drain Outputs.

These outputs are driven low through a 30µs filter when

the respective channel output is below its programmed

UV fault limit or above its programmed OV fault limit.

If used, a pull-up resistor is required in the application.

ASELA[1:0]:Unit ASerialBusAddressSelectPins. Connect

optional 1% resistor dividers between V

and GND

DD25A

to these pins to select the serial bus interface address.

ASELB[1:0]:Unit BSerialBusAddressSelectPins. Connect

Operating voltage range is GND to V

.

DD33

optional 1% resistor dividers between V

and GND

DD25B

to these pins to select the serial bus interface address.

PWM[A/B][1:0]: PWM Three-State Control Outputs.

These pins provide single-wire PWM switching control

for each channel to an external gate driver, DrMOS or

VO[A/B][1:0]CFG: Output Voltage Configuration Pins.

Connect optional 1% resistor dividers between V_DD25

and GND to these pins to select the output voltage for

each channel.

power block. Operating voltage range is GND to V

.

DD33

SYNC[A/B]: External Clock Synchronization Input and

Open-Drain Output. If desired, an external clock can

be applied to this pin to synchronize the internal PWM

channels. If an LTC7883 unit is configured as a clock

master, this pin will also pull to ground at the selected

FCFG[A/B]: Frequency Configuration Pins. Connect an

optional 1% resistor divider between V

and GND to

DD25

these pins to configure PWM switching frequency.

Rev. 0

12

For more information www.analog.com

LTC7883

PIN FUNCTIONS

PCFG[A/B]: Phase Configuration Pins. Connect an

optional 1% resistor divider between V

these pins to configure the phase of each PWM channel

relative to SYNC.

V

: Negative Output Voltage Sense Inputs.

SNS[A/B][1:0]M

and GND to

These pins must still be properly connected on slave

DD25

channels for accurate output current telemetry.

V_{SNS[A/B][1:0]P}: Positive Output Voltage Sense Inputs.

These pins must still be properly connected on slave

channels for accurate output current telemetry.

V_DD25[A/B]: Internal 2.5V Regulator Outputs. Bypass these

pins to GND with a low ESR 1µF capacitor. Do not short

these pins together or load them with external current

beyond that required for local LTC7883 configuration.

CS[A/B][1:0]M: Current Sense Amplifier Inputs. These (–)

inputs to the amplifiers are normally connected to the low

side of a DCR sensing network or output current sense

resistor for each phase.

WP[A/B]: Write Protect Inputs. If WP is above 2V, PMBus

writes are restricted and any software WRITE_PROTECT

settings for that unit are overridden. These pins have an

CS[A/B][1:0]P: Current Sense Amplifier Inputs. These

(+) inputs are normally connected to the high side of an

output current sense resistor or the R-C midpoint of a

parallel DCR sense circuit for each phase.

internal 10µA pull-up to V

.

DD33

SHCLK[A/B]: Share Clock Open-Drain Outputs (bussed).

Share Clock, nominally 100kHz, is used to sequence mul-

tiple rails in a power system utilizing more than one ADI

PSM controller. A pull-up resistor is required in the appli-

cation. Minimize the capacitance on this line to ensure the

time constant is fast enough for the application. Operating

IAVG[A/B][1:0]: Average Current Control Pins. A capac-

itor connected between these pins and IAVGND stores a

voltage proportional to the average output current of the

master channel. PolyPhase control is then implemented

in part by connecting all slave IAVG pins together to the

master IAVG output. This pin should be left open on chan-

nels that control single-phase outputs. Operating voltage

range is GND to 2.1V.

voltage range is GND to V

.

DD33

V_DD33[A/B]: Internal 3.3V Regulator Outputs. Bypass these

pins to GND with a low ESR 2.2µF capacitor. The LTC7883

may also be powered from an external 3.3V rail attached

to these pins, if also shorted to V

. Otherwise do not

short these pins together or ove^Crl^Co^[a^Ad^/B]them with external

system current. Local pull-up resistors for the LTC7883

FB[A/B][1:0]: Error Amplifier Inverting Inputs. These pins

provide an internally scaled version of the output voltage

for use in loop compensation.

itself may be powered from V

.

DD33

GND: Ground. All GND balls must be soldered to a suitable

PCB copper ground plane for proper electrical operation

and to obtain the specified package thermal resistance.

V

(Pin 25): 3.3V Regulator Input(s). Bypass these

CC[A/B]

pins, which may be shorted together, to GND with a capac-

itor (0.1µF to 1µF ceramic) in close proximity to the IC.

Rev. 0

13

For more information www.analog.com

LTC7883

BLOCK DIAGRAM ^{(“A” Side, 1 of 2 Units)}

ROM

RAM

EEPROM

VINSA

PWM0

R_CONFIG

IAVGA0

MCU AND

CUSTOM

LOGIC

SHCLKA

SYNCA

CSA0P/M

PMBus

2.5V

REGULATOR

12-BIT

DAC

V

SNSA0P/M

PGA0

PWMA0

PLL

V

REF

VOLTAGE

REFERENCE

IAVGNDA

3.3V

REGULATOR

V

CCA

PWMA1

PGA1

V

DD33A

V

BIAS AND

SNSA1P/M

12-BIT

DAC

PWM1

VINSA

HOUSEKEEPING

CSA1P/M

VINSA

IAVGA1

PWMA0

INTERNAL DATA BUS

V

SNSA0P/M

16-BIT

ADC

CSA0P/M

TSNSA0

ANALOG

MUX

PWMA1

INTERNAL

TEMPERATURE

V

SNSA1P/M

CSA1P/M

TSNSA1

7883 BD

Rev. 0

14

For more information www.analog.com

LTC7883

TEST CIRCUIT ^{(Channel A0 Example)}

LTC7883

1.024V

V

R

12-BIT

D/A

DIGITAL

+

–

EA

V

FBA0

A4 G2

COMPA0

G1

SNSA0M

SNSA0P

A3

+

–

LTC1055

TARGET = VOUT_COMMAND

1V

7883 TC

TIMING DIAGRAM

SDA

t

r

t

SU(DAT)

t

SP

t

HD(SDA)

r

t

f

t

f

BUF

LOW

SCL

t

SU(STO)

HD(STA)

SU(STA)

t

HIGH

HD(DAT)

7883 TD

START

CONDITION

REPEATED START

CONDITION

STOP

START

CONDITION CONDITION

Rev. 0

15

For more information www.analog.com

LTC7883

OPERATION

Overview

• Optional Time-Base Interconnect for Synchronization

Between Multiple Controllers

The LTC7883 is a quad channel constant frequency

analog voltage mode controller for DC/DC step-down

applications. It features PMBus compliant digital inter-

faces for monitoring and control of important power sys-

tem parameters. The IC operates from power supplies

between 3V and 13.2V and is intended for conversion

• Warning and Fault Status with Fault Event Data Logging

• PMBus Revision 1.2 Compliant Interface Up to 400kHz

Internal Structure

The LTC7883 is comprised of two dual-channel units,

each equivalent to an LTC3882-1 with the added feature

of a hardware PMBus write protect for each unit.

from V between 3V and 38V to output voltages between

IN

0.1V and 5.25V. It is designed to be used in a switching

architecture with external FET drivers, including higher

level integrations such as non-isolated power blocks.

Refer to the LTC3882-1 data sheet for a detailed descrip-

tion of operation, PMBus command set, and applications

information for each unit.

Major features include:

• Digitally Programmable Output Voltage, Current Limit

and Related Supervisors

Refer to the LTC3888 data sheet for additional details on

operation of the WP pins and their interaction with the

PMBus WRITE_PROTECT command on each unit.

• Digitally Programmable Input Voltage Supervisor

• Digitally Programmable Switching Frequency with PLL

for Synchronous PolyPhase Operation Up to 8 Phases

Unique Special ID

Each internal unit of the LTC7883 reports a unique MFR_

SPECIAL_ID to differentiate it from an LTC3882-1. Table 1

lists MFR_SPECIAL_ID values for these products. X is

adjustable by the manufacturer.

• Digitally Programmable On and Off Delay Times

• Digitally Programmable Soft-Start/Stop

• Operating Condition Telemetry

Table 1. MFR_SPECIAL_ID Values

• Fully Differential Load Sense

DEVICE

MFR_SPECIAL_ID

0x424X

MFR_MODEL

LTC3882-1

LTC7883A

LTC7883B

• Nonvolatile Configuration Memory with ECC Capable

of Standalone Operation

LTC3882-1

LTC7883 Unit A

LTC7883 Unit B

0x450X

0x451X

• Optional External Resistor Configuration of Key

Operating Parameters

Rev. 0

16

For more information www.analog.com

LTC7883

OPERATION

Additional Identification Commands

Unlike the LTC3882-1, which only allows a fixed set of

predetermined frequencies, the LTC7883 FREQUENCY_

SWITCH command supports a continuous range of values

from 250kHz to 2.5MHz. The special case of 0x0000 for

External SYNC Only is not permitted by the LTC7883.

Sending this FREQUENCY_SWITCH command value will

result in a CML fault for invalid data.

The LTC7883 features a few new PMBus product identi-

fication commands as detailed in Table 2.

Switching Frequency and Phase

There is a high degree of flexibility for setting the PWM

operating frequency of the LTC7883. The switching fre-

quency of the PWM can be established with an internal

oscillator or an external time base. The internal phase-

locked loop (PLL) synchronizes PWM control to this

timing reference with proper phase relation, whether

the clock is provided internally or externally. The device

can also be configured to provide the master clock to

other ICs through PMBus command, EEPROM setting,

or external configuration resistors as outlined in appli-

cation Table 6. For PMBus or EEPROM configuration, an

LTC7883 unit is designated as a clock master by clearing

bit 4 of MFR_CONFIG_ALL_LTC3882-1. As clock master,

an LTC7883 unit will drive its open-drain SYNC pin at the

selected rate with a pulse width of 125ns. An external

The LTC7883 will automatically accept an external SYNC

input, disabling is own SYNC drive if necessary, as long as

the external clock frequency is greater than 1/2 of the pro-

grammed internal oscillator. Whether configured to drive

SYNC or not, an LTC7883 unit can continue PWM oper-

ation at the selected frequency (FREQUENCY_SWITCH)

using its own internal oscillator if an expected external

clock signal is not present.

The MFR_PWM_CONFIG_LTC3882-1 command can be

used to configure the phase of each channel. Desired

phase can also be set from EEPROM or external configu-

ration resistors as outlined in Table 6. Phase designates

the relationship between the falling edge of SYNC and the

internal clock edge that resets the PWM latch. That reset

turns off the top power switch, producing a PWM falling

edge. Additional small propagation delays to the PWM

control pins will apply.

pull-up resistor between SYNC and V

is required in

DD33

this case. Only one unit connected to SYNC should be

designated to drive the pin. If more than one LTC7883 unit

sharing SYNC is programmed as clock master, just one

of the units is automatically elected to provide the clock.

The others disable their SYNC outputs and indicate this

with bit 10 of MFR_PADS_LTC3882-1.

Table 2. New Identification Commands

DEFAULT VALUE

COMMAND NAME

ID_DEVICE_ID

CMD CODE DESCRIPTION

TYPE

PAGED

DATA FORMAT

ASC

UNIT A

LTC7883A

C0001

UNIT B

LTC7883B

C0001

0xAD

0xAE

LTC7883 Model Number

R String

N

ID_DEVICE_REV

LTC7883 Device Revision

Code

ASC

Rev. 0

17

For more information www.analog.com

LTC7883

OPERATION

The phase relationships and frequency are independent

of each other, providing numerous application options.

Multiple LTC7883 units/ICs can be synchronized to real-

ize a PolyPhase array. In this case the phases should be

separated by 360/n degrees, where n is the number of

phases driving the output voltage rail.

pins and PMBus command values stored in on-board

EEPROM. This method of using ASEL pins to specify

some or all of each unit’s physical address is necessary

when using default factory EEPROM programing, where

both units are assigned to 0x4F. Applying external resistor

configuration for unit addresses is recommended, as it

allows for easier device recovery under a wide range of

programming errors. Refer to the values in Table 7 for full

details on setting each unit address.

Serial Bus Addressing

The LTC7883 supports four types of serial bus addressing

schemes to access the individual PWM channels sepa-

rately or jointly.

Advanced Power Stages

Some LTC7883 factory EEPROM defaults have been

modified from LTC3882-1 values to better accommodate

newer, advanced power stages that provide an output

proportional to load current. Table 3 details these val-

ues. Refer to Figure 1 for an example of interfacing the

LTC7883 to power stages or blocks of this type. If tradi-

tional DCR or discrete resistor sense of output current is

used as shown on the front page, refer to factory EEPROM

defaults given for Table 3 commands in the LTC3882-1

data sheet.

• Global Bus Addressing

• Power Rail Addressing

• Individual Unit (Device) Addressing

• Page+ Channel Addressing

Each internal unit of the LTC7883 must be given a unique

serial bus address for configuration and control. These

units addresses can be derived from a combination of

external configuration resistors attached to the ASEL

Table 3. Unique LTC7883 Default Factory EEPROM Values

COMMAND NAME

IOUT_CAL_GAIN

CMD CODE

DESCRIPTION

TYPE

PAGED DATA FORMAT UNITS DEFAULT VALUE

0x38

Ratio of I

Voltage

R/W Word

Y

L11

CF

mΩ

0.25mΩ

0xAA00

SENSE

to Sensed Current

IOUT_OC_FAULT_LIMIT

IOUT_OC_WARN_LIMIT

MFR_IOUT_CAL_GAIN_TC

0x46

0x4A

0xF6

Output Overcurrent Fault Limit

R/W Word

A

70.0A

0xEA30

Output Overcurrent Warning Limit

50.0A

0xE320

Output Current Sense Element

Temperature Coefficient

ppm/°C

0ppm/°C

0x0000

Rev. 0

18

For more information www.analog.com

LTC7883

APPLICATIONS INFORMATION

Using FREQUENCY_SWITCH

Refer to the following PCFG discussion for additional

details on controlling SYNC output enable with external

programming resistors.

Each unit in the LTC7883 that is a clock slave should have

FREQUENCY_SWITCH programmed to the same value

as its clock master, whether another LTC7883 or not. In

the case where external synchronization will be used to

control the shared SYNC line, each LTC7883 should be

programmed with a value of FREQUENCY_SWITCH that

is as close to the external clock frequency as possible.

Table 4. VOnCFGA/B Resistor Programming

R

TOP

(kΩ)

R

BOT

(kΩ)

V

(V)

OUT

0 or Open

10

Open

From EEPROM

23.2

15.8

20.5

17.4

17.8

15

5.0

3.3

10

16.2

20

2.5

1.8

Resistor Configuration Pins

1.5

Like the LTC3882-1, each LTC7883 unit is programmed

to use external resistor configuration by factory default.

This allows output voltage, PWM frequency and phasing,

and the PMBus address to be set without programming

the part through its serial interface or purchasing devices

with custom EEPROM contents. The RCONFIG pins all

20

1.35

1.25

1.2

20

12.7

11

20

24.9

30.1

Open

11.3

9.09

7.32

5.76

4.32

3.57

1.96

0

1.15

1.1

1.0

require a resistor divider between V

and GND. The

0.9

RCONFIG pins are only interrogated^Da^Dt²⁵initial power-up

and during a reset, so modifying their values on-the-fly

is not recommended. RCONFIG pins on the same unit

can share a single resistor divider if they require identical

programming, but these dividers should not be shared

across different LTC7883 units. Resistors with a tolerance

of 1% or better must be used to assure proper operation.

0.75

0.65

0.6

Output OFF*

from EEPROM)

(V

OUT

*OPERATION value and RUNn pin must both command the channel to

start from this configuration.

In Table 4 through Table 6, R

is connected between

V_DD25and the RCONFIG pin,^Tw^OPhile R_BOTis connected

between the pin and GND. Noisy clock signals should not

be routed near these pins.

Table 5. FCFGA/B Resistor Programming

SWITCHING

R

TOP

(kΩ)

R

BOT

(kΩ)

FREQUENCY (kHz)

0 or Open

10

Open

From EEPROM

2500

2250

2000

1750

1500

1250

1000

900

23.2

15.8

20.5

17.4

17.8

15

RCONFIG address selection for each LTC7883 unit follows

the values given in Table 7 of this data sheet.

10

16.2

20

Output voltage can be set as shown in Table 4. For exam-

ple, setting R

to 16.2kΩ and R

to 17.4kΩ is equiv-

TOP

BOT

alent to programming a VOUT_COMMAND value of 1.8V.

Refer to the Operation section of the LTC3882-1 data

sheet for related parameters that are also automatically

20

12.7

11

20

set as a percentage of the programmed V

if resistor

24.9

30.1

Open

11.3

9.09

7.32

5.76

4.32

3.57

1.96

0

750

OUT

600

configuration pins are used to determined output voltage.

500

Operating PWM frequency can be set as shown in

Table 5. Note that if SYNC pins are shared between

LTC7883 units, all those units should be programmed

to the same frequency, but only one SYNC output should

be enabled. All other SYNC outputs should be disabled.

450

400

350

300

250

Rev. 0

19

For more information www.analog.com

LTC7883

APPLICATIONS INFORMATION

Table 6 shows various PWM phase configurations that

can be selected with external resistor programming. This

RCONFIG pin, as with the LTC3882-1, can also be used

to control SYNC output drive for each LTC7883 unit.

However, there are more choices here, affording greater

flexibility in PolyPhase configurations.

For Unit B, R

of 10kΩ and R

of 15.8kΩ selects

BOT

TOP

phase angles for PWMB0 of 90° and PWMB1 of 270°,

configuring SYNCB as an input to accept the master clock

from Unit A. The result, when wired as a 4-phase rail

as described in PolyPhase Operation and Load Sharing

under Applications Information in the LTC3882-1 data

sheet, will be four non-overlapping phases operating in

quadrature as desired. In this case, either Unit A or Unit

B may be defined and wired as the voltage loop master,

since this function is independent of clock mastering.

For example, to build a four-phase rail, one approach

might be to select R

of 24.9kΩ and R

of 5.76kΩ for

TOP

PHAS_CFG of Unit A (PCFGA). This pro^Bg^Or^Tams the phase

angles of PWMA0 to 0° and PWMA1 to 180°, relative to

the falling edge of SYNC. Unit A is enabled to drive the

shared SYNC clock line through the SYNCA pin (open-

drain output).

Only mix phase selections on PolyPhase rails that have

the same maximum duty cycle specified in Table 6.

Table 6. CFGA/B Resistor Programming

R

TOP

(kΩ)

R

BOT

(kΩ)

θ

SYNC

TO θ

θ

SYNC

TO θ

1

MAXIMUM DUTY CYCLE

SYNC OUTPUT DISABLED

0

0 or Open

10

Open

From EEPROM

315°

See MFR_PWM_CONFIG

From EEPROM

23.2

15.8

20.5

17.4

17.8

15

135°

90°

45°

0°

10

270°

87.5%

83.3%

87.5%

83.3%

Yes

No

16.2

20

225°

180°

120°

60°

0°

300°

20

240°

20

12.7

11

180°

20

0°

120°

24.9

30.1

Open

11.3

9.09

7.32

5.76

4.32

3.57

1.96

0

135°

90°

45°

0°

315°

270°

225°

180°

120°

60°

0°

300°

240°

No

180°

0°

120°

Rev. 0

20

For more information www.analog.com

LTC7883

APPLICATIONS INFORMATION

Table 7. ASELn Resistor Programming

solution volume. Placing the power stage directly beneath

the LTC7883 on the other side of the PCB allows direct

through-hole via connections to the power block for PWM

controls, as well as output voltage and current sense.

Table 8 shows the recommended channel mapping for

the most efficient interconnect in this case. CCM opera-

tion, fast boost refresh, low V_OUTrange and digital output

voltage servo are selected by programming MFR_PWM_

MODE_LTC3882-1 to 0xC0 on all channels.

ASEL1

ASEL0

LTC3882-1 DEVICE

ADDRESS BITS[6:4]

LTC3882-1 DEVICE

ADDRESS BITS[3:0]

R

TOP

(kΩ)

R

(kΩ)

BOT

BINARY

HEX

BINARY

HEX

0 or Open

10

Open

from EEPROM

1111

23.2

15.8

20.5

17.4

17.8

15

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

10

1110

16.2

20

1101

1100

1011

Table 8. Suggested Power Block Channel Mapping

PMBus PAGE

20

1010

LTC7883 PWM LTC7883 UNIT

(CH)

PB PWM

20

12.7

11

1001

A0

A1

B0

B1

A

0

1

0

1

2

1

4

3

20

1000

24.9

30.1

Open

11.3

9.09

7.32

5.76

4.32

3.57

1.96

0

111

110

101

100

011

010

001

000

7

6

5

4

3

2

1

0

0111

B

0110

0101

0100

The regulated output is established by programming the

VOUT_COMMAND stored in EEPROM for PWMA0 (the

master channel) to 1.5V. The other PWMs are designated

0011

0010

0001

as slaves to PWMA0 by wiring their FB pins to V

and

0000

DD33

shorting their COMP control pins to COMPA0 as shown.

The frequency and phase are also set by EEPROM val-

ues. Both units are programmed to operate at 500kHz

(default FREQUENCY_SWITCH), with Unit A providing

the clock master (see Figure 3, SYNCB output disabled

by bit 4 of MFR_CONFIG_ALL_LTC3882-1 on Unit B).

MFR_PWM_CONFIG_LTC3882-1 is programmed to 0x14

on Unit A to put PWMA0 phase at 0° and PWMA1 phase

at 180°. This register is programmed to 0x16 on Unit B

to put PWMB0 phase at 90° and PWMB1 phase at 270°,

producing optimum 4-phase separation for minimum

input and output ripple.

Design Example

As a design example, consider a 180W 4-phase applica-

tion such as the one shown in Figure 1, where V = 12V,

IN

V_OUT= 1.5V, and I_OUT= 120A. An auxiliary 7V source

supplies the LTC7883 V pins and the power stage FET

CC

gate drive voltage with a 2.2µF ceramic bypass, in addi-

tion to a smaller 0.1µF ceramic placed near the LTC7883

filtering HF components. Bypassing is also provided for

each V

(2.2µF) and V

(1µF) LDO output. These

DD33

DD25

LDO outputs should not be shared with each other or

separate ICs that might have outputs of the same name,

because they have independent, internal control loops.

With these configurations, the inductors on the

power block (160nH nominal) create an I_OUTripple of

The Delta D12S1R8140D power block is chosen for its

high level of integration, power efficiency and direct

interface to the LTC7883 using 3.3V three-state control.

The use of a power block with the LTC7883 creates an

efficient solution in terms of power, parts count and total

16.4A . Each channel supplies 40ADC to the output at

P-P

full load, resulting in a peak phase current of 48A. Setting

IOUT_FAULT_LIMIT to 50A per phase adequately protects

against the typical inductor saturation current of 55A.

Rev. 0

21

For more information www.analog.com

LTC7883

APPLICATIONS INFORMATION

Two 100μF SUNCON capacitors and four 22μF ceramic

capacitors are selected to provide acceptable input AC

impedance against the designed converter ripple current.

Ten 220μF ceramic capacitors are chosen for the output to

maintain supply regulation during severe transient condi-

tions and to minimize output voltage ripple.

ASEL pins to program the three most significant PMBus

address bits from EEPROM (MFR_ADDRESS, 0x4X).

Then each unit is given its own unique lower address

nibble, setting the two addresses to 0x4C (Unit A) and

0x4D (Unit B). Ensure the selected addresses do not col-

lide with global addresses or any other specific devices

in the system. Identical MFR_RAIL_ADDRESS should be

set in EEPROM for all four channels to allow single-com-

mand control of common rail parameters such as IOUT_

OC_FAULT_LIMIT. The LTC7883 units also respond to

7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS

and MFR_RAIL_ADDRESS should not be set to either of

these values.

The power block provides its own output current monitor

signals for use by the LTC7883. The interface network,

shown in detail for differential input CSA1, is also repli-

cated for the other three channels. These remove high

frequency noise from the power block outputs and scale

those signals to be compatible with the LTC7883 inputs. A

fixed common mode reference voltage is required for the

power block –CS[4:1] outputs. A filtered resistor divider

PMBus connections, as well as shared RUN control

and fault propagation (FLT) are provided. SYNC can be

used to synchronize other PWMs to this rail if required.

Recommended PMBus connections and shared PSM con-

nections are shown in more detail in Figure 3.

from V

(10k/12.1k/4.3μF) fulfills this requirement,

DD33

driving the negative side of the differential current sense

(CSx) signals.

External temperature sense will employ an accurate ∆V

BE

method. Q1 serves to sense the temperature of the PCB

as close to the power block as physically possible, and

the 10nF filter capacitor should be placed with the BJT.

Unused TSNS inputs are loaded with 2.74k to produce

a benign reading of about 25^ºC with factory EEPROM

Pull-ups are provided on all shared open-drain signals

(Figure 1 and Figure 3). The values shown assume a

maximum 100pF line load and PMBus rate of 100kHz.

These pins should not be left floating. Termination to

3.3V ensures the absolute maximum ratings for the pins

are not exceeded. All other operating parameters such

as soft start/stop and desired faults responses are pro-

grammed via PMBus command values stored in internal

LTC7883 EEPROM.

settings, if the direct V interface mode is selected by

BE

MFR_PWM_MODE_LTC3888-1 on these channels.

Each internal LTC7883 unit must be configured for a

unique address. Resistor configuration is used on the

Rev. 0

22

For more information www.analog.com

LTC7883

TYPICAL APPLICATIONS

V

12V

IN

22µF

4×

+

V

7V

DR

100µF

2×

0.1µF

2.2µF

+7V

V

IN

V

DD33

V

CCA

VINSB

V

CCB

VINSA

PGA0

10k

PWMA1

CSA1P

V

OUT

1.5V

120A

+CS1

PGA1

PGB1

PGB0

N

4.99k

2k

220µF

10×

V

OUT

V

100pF

SNSA1P

DS12S18R140D

V

SNSB1P

SNSB0P

–CS1

CSA1M

PWMA0

CSA0P

CSA0M

PWMB1

CSB1P

CSB1M

PWMB0

CSB0P

CSB0M

V

DD33

FBA1

FBB1

FBB0

+CS2

–CS2

N

THREE ADDITIONAL

IDENTICAL POWER

STAGES AND

EXTERNAL

CS FILTER

NETWORKS (N)

+CS3

–CS3

V

SNSA1M

SNSB1M

SNSB0M

+CS4

–CS4

COMPA1

COMPB1

COMPB0

COMP

V

121k

LTC7883

V

DD33

0.01µF

×4*

10nF

Q1

100k

10k

RUNA1

RUNA0

TSNSA0

V

SNSA0P

RUNB1

V

DD25

V

SNSA0M

RUN

RUNB0

470pF

4.12k

60.4k

2

16.2k

FBA0

ASEL1A/B

ASEL0A

ASEL0B

18pF

180pF

COMP

2

4

FCFGA/B

PCFGA/B

20.5k

17.4k

*1 PER PHASE

COMPA0

IAVGA1

IAVGA0

IAVGB1

SEE FIGURE 2 FOR PMBus

AND SHARED PSM PIN DETAILS

VO[A/B][1:0]CFG

TSNSA1

100pF

TSNSB1

IAVGB0

2.74k

TSNSB0

2

IAVGNDA/B

2.74k

V

DD25B

DD33

DD33B

V

DD25A

DD33A

GND

2.2µF

V

DD25

7883 F01

2.2µF

1µF

Figure 1. High Density 1.5V/120A 500kHz 4-Phase Converter Using Quad Power Block

Rev. 0

23

For more information www.analog.com

LTC7883

TYPICAL APPLICATIONS

See Figure 2 for the LTC7883 controller plus the LTC7050/

LTC7051 SilentMOS™ smart power stage. The LTC7050/

LTC7051 have an on-chip diode that can be used by

the LTC7883 to sense the temperature. Use the direct

V_BEmeasurement option in MFR_PWM_MODE of the

LTC7883. Consult the factory or review the LTC3882 DS

for more information on this temperature sensing method.

PWM

L1

V

SW

OUT

LTC7050/

LTC7051

I

MON

R2

140k

R1

49.9Ω

C1

4.7nF

C

OUT

TDIO

I

REF

V

CC

GND

V

CC

R

T

750Ω

C

0.1µF

R

B

237Ω

FIL

PWM TSNS

LTC7883

V

OUT

–

+

I

SNS

I

SNS

7883 F02

Figure 2. LTC7883 with LTC7050/LTC7051 SilentMOS Smart Power Stage

Rev. 0

24

For more information www.analog.com

LTC7883

PACKAGE DESCRIPTION

Z

/ / b b b

Z

4 . 0 0 0

3 . 2 0 0

2 . 4 0 0

1 . 6 0 0

0 . 8 0 0

0 . 0 0

0 . 8 0 0

1 . 6 0 0

2 . 4 0 0

3 . 2 0 0

4 . 0 0 0

a a a

Z

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

25

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTC7883

TYPICAL APPLICATION ^{(Also See Figure 1)}

WPA

V

DD33

WPB

PMBus

WRITE

ENABLE

4.99k

LTC7883

VN2222

V

SHARE_CLK

DD33

10k

SHCLKA

SHCLKB

FLTA1

FLTA0

FLTB1

FLTB0

SYNCA

FAULT

SMBALERT

1k

2k

ALERTA

PSM

SHARED

PINS

SYNC

SDA

ALERTB

PMBus

1k

SDA_A

SDA_B

SCL_A

SCL

SCL_B

SYNCB

GND

7883 F03

Figure 3. LTC7883 PMBus Interface and Configuration

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

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Accurate Output Voltage Measurement and Trim

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16 Output Voltages, 2 Input Voltages and Die Temperature

2

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24-Channel PMBus Power System Manager Featuring

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24 Output Voltages, 3 Input Voltages and Die Temperature

LTC7851/

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Controller with Soft-Start and Accurate Current Share

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up to 27V, 0.6V ≤ V

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LTC7851-1

Drivers, DrMOS Devices and Power Blocks

V Up to 26.5V; 0.1V ≤ V ( 0.5%) ≤ 3.45V, Fault Logging, I C/PMBus

IN

2

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Dual Loop, 8-Phase Step-Down DC/DC Controller with Digital

Power System Management

OUT

Interface with NVM and 16-Bit ADC and Load Step Emulation

Rev. 0

12/21

www.analog.com

 ANALOG DEVICES, INC. 2021

26

For more information www.analog.com


型号：	LTC7801
厂家：	ADI
描述：	100V Half-Bridge Driver with Floating Grounds and Adjustable Dead-Time
文件：	总26页 (文件大小：1853K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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