LTC7817IUHF [ADI]
40V, Low IQ, 3MHz, Triple Output Buck/Buck/Boost Synchronous Controller;
| 型号： | LTC7817IUHF |
| 厂家： | 
ADI |
| 描述： | 40V, Low IQ, 3MHz, Triple Output Buck/Buck/Boost Synchronous Controller |
| 文件： | 总44页 (文件大小：2904K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC7817
40V, Low I , 3MHz,
Q
Triple Output Buck/Buck/Boost Synchronous Controller
FEATURES
DESCRIPTION
The LTC®7817 is a high performance triple output (buck/
buck/boost) synchronous DC/DC switching regulator con-
troller that drives all N-channel power MOSFET stages.
Its constant frequency current mode architecture allows
a phase-lockable switching frequency of up to 3MHz.
The LTC7817 operates from a wide 4.5V to 40V input
supply range. When biased from the output of the boost
converter or another auxiliary supply, the LTC7817 can
operate from an input supply as low as 1V after start-up.
n
Dual Buck Plus Single Boost Synchronous Controllers
n
Low Operating I :
Q
14μA (14V to 3.3V, Channel 1 On)
Outputs Remain in Regulation Through Cold Crank
Down to 1V Input Supply Voltage
n
n
n
n
n
Wide Bias Input Voltage Range: 4.5V to 40V
Buck and Boost Output Voltages up to 40V
R
or DCR Current Sensing
SENSE
Pass-Thru™ Operation: 100% Duty Cycle for
The very low no-load quiescent current extends operating
run time in battery powered systems. OPTI-LOOP® com-
pensation allows the transient response to be optimized
over a wide range of output capacitance and ESR values.
The LTC7817 features a precision 0.8V reference for the
bucks, 1.2V reference for the boost and a power good
output indicator.
Boost Synchronous MOSFET
n
n
n
Programmable Fixed Frequency (100kHz to 3MHz)
Phase-Lockable Frequency (100kHz to 3MHz)
Selectable Continuous, Pulse-Skipping, or Low
Ripple Burst Mode Operation at Light Loads
Very Low Buck Dropout Operation: 99% Duty Cycle
n
n
n
n
Low Shutdown I : 1.5μA
Q
Small 38-Lead 5mm × 7mm QFN Package
The LTC7817 synchronous boost Pass-Thru capability
minimizes losses in automotive start-stop applications.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258.
AEC-Q100 Automotive Qualification in Process
APPLICATIONS
n
Automotive and Transportation
n
Industrial
n
Military/Avionics
TYPICAL APPLICATION
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LTC7817 Response to a Cold
ꢀꢁꢂ
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Crank Automotive Waveform
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1.5mΩ
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2mΩ
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ꢀꢁ
ꢀ0ꢁ
3mΩ
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0ꢀꢁꢂꢃ
ꢀꢁꢂ
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ꢀꢁꢂꢀ ꢃꢄ0ꢂꢅ
Rev 0
1
Document Feedback
For more information www.analog.com
LTC7817
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ꢅꢆꢇ ꢈꢉꢊꢋ
Bias Input Supply Voltage (V
).............. –0.3V to 40V
BIAS
BOOST1, BOOST2, BOOST3....................... –0.3V to 46V
Switch Voltage (SW1, SW2, SW3)................ –5V to 40V
RUN1, RUN2, RUN3 Voltages..................... –0.3V to 40V
ꢁꢖ ꢁꢛ ꢁꢄ ꢁꢃ ꢁꢂ ꢁꢁ ꢁꢨ
+
–
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ꢝꢝꢁ
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ꢨ
ꢁ
ꢂ
ꢃ
ꢄ
ꢛ
ꢖ
ꢌ
ꢁꢀ ꢝꢋꢀ
SENSE1 , SENSE1 Voltages...................... –0.3V to 40V
+
+
–
–
ꢁ0 ꢧꢆꢆꢝꢅꢀ
SENSE2 , SENSE2 Voltages ..................... –0.3V to 40V
ꢧꢍꢀ
ꢨꢌ
SENSE3 , SENSE3 Voltages..................... –0.3V to 40V
ꢩ
ꢝꢊꢎꢝꢊꢁ
ꢝꢋꢁ
ꢨꢖ
EXTV Voltage ......................................... –0.3V to 30V
CC
CC
ꢪ
ꢝꢊꢎꢝꢊꢁ
ꢨꢛ ꢅꢍꢁ
INTV , (BOOST1-SW1),
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ꢒꢧꢁ
ꢧꢆꢆꢝꢅꢁ
ꢨꢄ
ꢁꢌ
ꢇꢍꢎꢏ
(BOOST2-SW2), (BOOST3-SW3)............. –0.3V to 6V
TRACK/SS1, TRACK/SS2, SS3 Voltages...... –0.3V to 6V
ITH1, ITH2, ITH3 Voltages............................ –0.3V to 2V
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Rꢐꢎꢨ ꢀ0
ꢨꢨ ꢉꢎꢅꢈ
ꢨꢀ ꢧꢍꢨ
V
V
Voltage............................................... –0.3V to 40V
FB1 FB2,
FB3
Rꢐꢎꢁ ꢀꢀ
, V
PLLIN/MODE Voltages ............... –0.3V to 6V
ꢪ
ꢨ0
ꢝꢊꢎꢝꢊꢨ ꢀꢨ
ꢧꢆꢆꢝꢅꢨ
VPRG3, FREQ, PGOOD1 Voltages ................ –0.3V to 6V
BG1, BG2, BG3, TG1, TG2, TG3..........................(Note 9)
Operating Junction Temperature Range (Notes 2,8)
LTC7817E, LTC7817I.......................... –40°C to 125°C
LTC7817J, LTC7817H......................... –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
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ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
38-Lead (5mm x 7mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
LTC7817EUHF#PBF
LTC7817EUHF#TRPBF
7817
AUTOMOTIVE PRODUCTS**
LTC7817IUHF#WPBF
LTC7817JUHF#WPBF
LTC7817HUHF#WPBF
LTC7817IUHF#WTRPBF
LTC7817JUHF#WTRPBF
LTC7817HUHF#WTRPBF
7817
7817
7817
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
38-Lead (5mm x 7mm) Plastic QFN
38-Lead (5mm x 7mm) Plastic QFN
38-Lead (5mm x 7mm) Plastic QFN
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev 0
2
For more information www.analog.com
LTC7817
The l indicates specifications which apply over the specified operating
ELECTRICAL CHARACTERISTICS
junction temperature range, otherwise specifications are for TA = 25°C, VBIAS = 12V, RUN1,2,3 > 1.25V, EXTVCC = 0V, VPRG3 = FLOAT
unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
, V )
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply (V
BIAS IN
V
V
Bias Input Supply Operating Voltage Range
4.5
1
40
40
V
V
BIAS
IN
Boost Converter Input Supply Operating
Range
V
≥ 4.5V
BIAS
Front Page Circuit, 14V to 3.3V, No Load,
RUN2,3 = 0V
14
µA
Controller Operation
V
V
V
Buck Output Voltage Operating Range
Boost Output Voltage Operating Range
Buck Regulated Feedback Voltage
0.8
40
40
V
V
OUT1,2
OUT3
(Note 4) V
= 4.5V to 40V,
BIAS
FB1,2
l
ITH1,2 Voltage = 0.6V to 1.2V
0ºC to 85ºC, All Grades
0.788 0.800 0.812
0.792 0.800 0.808
V
V
V
Boost Regulated Feedback Voltage
(Note 4) V
= 4.5V to 40V,
BIAS
FB3
ITH3 Voltage = 0.6V to 1.2V,
VPRG3 = FLOAT
l
l
l
1.177 1.195 1.213
V
V
V
VPRG3 = 0V
VPRG3 = INTV
7.81
9.77
8.00
10.0
8.13
10.17
CC
Buck Feedback Current
Boost Feedback Current
5
50
nA
VPRG3 = FLOAT
RUN3 = 0V, VPRG3 = 0V or INTV
RUN3 = 2V, VPRG3 = 0V or INTV
5
5
1
50
50
nA
nA
µA
CC
CC
Buck Feedback Overvoltage Protection
Threshold
Measured at V
Relative to
7
10
13
%
FB1,2
FB1,2
Regulated V
g
Transconductance Amplifier g
(Note 4) ITH1,2,3=1.2V, Sink/Source=5μA
1.8
50
mmho
mV
m1,2,3
m
–
l
V
Maximum Current Sense Threshold
V
FB1,2
V
= 0.7V, V
= 3.3V
45
55
SENSE(MAX)
SENSE1,2
+
= 1.1V, V
= 12V
FB3
SENSE3
–
Matching for Channels 1 & 2
V
V
V
V
= 3.3V
–3.5
0
3.5
1
mV
µA
µA
SENSE1,2
+
+
+
I
I
I
SENSE1,2 Pin Current
= 3.3V
SENSE1,2
SENSE1,2
–
–
–
SENSE3 Pin Current
= 12V
1
SENSE3
SENSE3
–
–
–
SENSE1 Pin Current
≤ 2.7V
SENSE1
> INTV + 0.5V
2
µA
µA
µA
SENSE1
SENSE1
–
3.2V ≤ V
< INTV – 0.5V
40
CC
–
V
660
SENSE1
CC
–
–
–
I
I
–
SENSE2 Pin Current
V
V
= 3.3V
2
2
µA
µA
SENSE2
SENSE2
SENSE2
> INTV + 0.5V
620
CC
+
+
+
+
SENSE3 Pin Current
V
V
= 3.3V
> INTV + 0.5V
µA
µA
SENSE3
SENSE3
SENSE3
660
12.5
1.20
100
CC
Soft-Start Charge Current
RUN Pin ON Threshold
RUN Pin Hysteresis
V
V
V
= 0V, V
= 0
SS3
10
15
µA
V
TRACK/SS1,2
l
Rising
1.15
1.25
RUN1,2,3
RUN1,2,3
Falling
mV
Rev 0
3
For more information www.analog.com
LTC7817
ELECTRICAL CHARACTERISTICS
The l indicates specifications which apply over the specified operating
junction temperature range, otherwise specifications are for TA = 25°C, VBIAS = 12V, RUN1,2,3 > 1.25V, EXTVCC = 0V, VPRG3 = FLOAT
unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Supply Current (Note 5)
V
V
Shutdown Current
Sleep Mode Current
RUN1, 2, 3 = 0V
1.5
µA
BIAS
BIAS
–
V
< 3.2V, EXTV = 0V
CC
SENSE1
One Channel On
15
18
24
30
µA
µA
All Channels On
–
Sleep Mode Current (Note 3)
Only Channel 1 On
V
V
V
≥ 3.2V
SENSE1
BIAS
BIAS
Current, EXTV = 0V
5
1
9
4
10
18
µA
µA
µA
µA
CC
CC
CC
Current, EXTV = 4.8V
EXTV Current, EXTV ≥ 4.8V
5
CC
–
SENSE1 Current
10
–
Sleep Mode Current (Note 3)
All Channels On
V
V
≥ 3.2V, EXTV ≥4.8V
SENSE1
BIAS
CC
Current
1
8
16
4
14
26
µA
µA
µA
EXTV Current
CC
–
SENSE1 Current
Pulse-Skipping or Forced Continuous Mode One Channel On
1.5
3
mA
mA
V
or EXTV Current (Note 3)
All Channels On
BIAS
CC
Gate Drivers
TG or BG On-Resistance
Pull-up
Pull-down
2.0
1.0
Ω
Ω
TG or BG Transition Time
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
C
C
= 3300pF
= 3300pF
25
15
ns
ns
TG Off to BG On Delay
Synchronous Switch-On Delay Time
C
= 3300pF Each Driver
LOAD
Bucks (Channels 1, 2)
Boost (Channel 3)
15
15
ns
ns
BG Off to TG On Delay
Top Switch-On Delay Time
C
= 3300pF Each Driver
LOAD
Bucks (Channels 1, 2)
Boost (Channel 3)
15
15
ns
ns
t
t
Buck TG Minimum On-Time
Boost BG Minimum On-Time
Maximum Duty Factor for TG
(Note 7)
(Note 7)
40
80
ns
ns
ON(MIN)1,2
ON(MIN)3
Bucks (Channels 1,2), FREQ = 0V
Boost (Channel 3) in Overvoltage
98
20
99
%
%
100
Maximum Duty Factor for BG
Bucks (Channels 1,2) in Overvoltage
Boost (Channel 3), FREQ = 0V
100
93
%
%
BOOST3 Charge Pump Available
Output Current
V
= 16V, V
= 12V, FREQ = 0V,
50
µA
BOOST3
SW3
Forced Continuous Mode
Rev 0
4
For more information www.analog.com
LTC7817
ELECTRICAL CHARACTERISTICS
The l indicates specifications which apply over the specified operating
junction temperature range, otherwise specifications are for TA = 25°C, VBIAS = 12V, RUN1,2,3 > 1.25V, EXTVCC = 0V, VPRG3 = FLOAT
unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INTV Low Dropout (LDO) Linear Regulator
CC
INTV Regulation Point
4.9
5.1
5.3
V
CC
INTV Load Regulation
I
CC
I
CC
= 0mA to 100mA, V
= 0mA to 100mA, V
≥ 6V
1.2
1.2
2
2
%
%
CC
BIAS
EXTVCC
≥ 6V
EXTV LDO Switchover Voltage
EXTV Rising
4.5
4.7
4.8
V
CC
CC
EXTV Switchover Hysteresis
250
mV
CC
l
l
UVLO
Undervoltage Lockout
INTV Rising
4.10
3.75
4.20
3.90
4.35
4.00
V
V
CC
INTV Falling
CC
Oscillator and Phase-Locked Loop
f
Low Fixed Frequency
High Fixed Frequency
Programmable Frequency
V
V
= 0V, PLLIN/MODE = DC Voltage
330
2.0
380
430
2.5
kHz
OSC
FREQ
FREQ
l
= INTV , PLLIN/MODE = DC Voltage
2.25
MHz
CC
R
R
R
= 374kΩ, PLLIN/MODE = DC Voltage
= 75kΩ, PLLIN/MODE = DC Voltage
= 12kΩ, PLLIN/MODE = DC Voltage
100
500
3
kHz
kHz
MHz
FREQ
FREQ
FREQ
450
550
3
l
Synchronizable Frequency Range
PLLIN/MODE = External Clock
0.1
2.2
MHz
l
l
PLLIN Input High Level
PLLIN Input Low Level
V
V
0.5
PGOOD1 Output
PGOOD1 Voltage Low
PGOOD1 Leakage Current
PGOOD1 Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGOOD1
V
µA
PGOOD1
V
Rising
7
10
2.5
13
%
%
FB1
V
Relative to Set Regulation Point
Hysteresis
FB1
V
Falling
–13
–10
2.5
–7
%
%
FB1
Hysteresis
PGOOD1 Delay for Reporting a Fault
25
µs
Rev 0
5
For more information www.analog.com
LTC7817
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
when biased by a buck channel output. To minimize input supply current,
select channel 1 to be the lowest output voltage greater than 3.2V and
connect EXTV to the lowest output voltage greater than 4.8V.
CC
Note 4: The LTC7817 is tested in a feedback loop that servos V
ITH1,2,3
Note 2: The LTC7817 is tested under pulsed load conditions such
to a specified voltage and measures the resultant V
. The
FB1,2,3
that T ≈ T . The LTC7817E is guaranteed to meet specifications from
specifications at 0°C and 85°C are not tested in production and are
assured by design, characterization and correlation to production testing
at other temperatures (125°C for the LTC7817E/LTC7817I, 150°C for the
LTC7817J/LTC7817H)
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
J
A
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC7817I is guaranteed over the –40°C to 125°C operating junction
temperature range, the LTC7817J is guaranteed over the –40°C to 150°C
operating junction temperature range, and the LTC7817H is guaranteed
over the –40°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
peak-to-peak ripple current > 40% of I
(See Minimum On-Time
L(MAX)
Considerations in the Applications Information section).
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 9: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
factors. The junction temperature (T , in °C) is calculated from the ambient
J
temperature (T , in °C) and power dissipation (P , in Watts) according
A
D
to the formula: T = T + (P • θ ), where θ (in °C/W) is the package
J
A
D
JA
JA
thermal impedance.
Note 3: When SENSE1 ≥ 3.2V or EXTV ≥ 4.8V, V
–
supply current is
CC
BIAS
transferred to these pins to reduce the total input supply quiescent current.
–
SENSE1 bias current is reflected to the buck channel 1 input supply (V
)
IN1
–
by the formula I
= I
• V
/(V • η), where η is the efficiency.
VIN1
SENSE1
OUT1 IN1
EXTV bias current is similarly reflected to a buck channel input supply
CC
Rev 0
6
For more information www.analog.com
LTC7817
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current (Buck)
Efficiency and Power Loss
vs Output Current (Buck)
Efficiency vs Input Voltage (Buck)
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀ0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀꢁRꢂꢃ ꢄꢅꢅꢆꢇꢆꢄꢈꢇꢉ
ꢀ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ ꢁꢂ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ
ꢀꢁꢂ ꢃꢀꢀꢄꢁꢄꢃꢅꢁꢆ
ꢀ
ꢀ
ꢀꢁꢂ ꢃꢄꢅꢅ
0ꢀꢁ
ꢀꢁꢂꢃR ꢄꢁꢅꢅ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ
ꢀꢁꢂꢂ
0ꢀꢁ
0ꢀ0ꢁ
0ꢀ00ꢁ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁ
ꢀꢁRꢂꢃ
ꢀꢁꢂꢂ
0ꢀ0ꢁ
0ꢀ00ꢁ
0ꢀ000ꢁ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ ꢁ0ꢂ
ꢀꢁ
ꢀ
ꢀ
ꢀ ꢁꢂ0ꢃꢄꢅ ꢆꢇꢈꢉꢊRꢋ ꢌ0ꢍ
ꢀ ꢁꢂꢁꢃꢄꢅꢆ ꢇꢈꢉꢊꢋRꢌ ꢍꢎꢏ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂ0ꢃꢄꢅ ꢆꢇꢈꢉꢊRꢋ ꢌ0ꢍ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢁꢃꢄꢅꢆ ꢇꢈꢉꢊꢋRꢌ ꢍꢎꢏ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
0ꢀꢁ ꢀ0
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
0ꢀ000ꢁ 0ꢀ00ꢁ
0ꢀ0ꢁ
0ꢀꢁ
ꢀ
ꢀ0
0ꢀ000ꢁ 0ꢀ00ꢁ
0ꢀ0ꢁ
ꢀ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢀ ꢃ0ꢄ
ꢀꢁꢂꢀ ꢃ0ꢄ
ꢀꢁꢂꢀ ꢃ0ꢂ
Load Step (Buck)
Burst Mode Operation
Load Step (Buck)
Pulse-Skipping Mode
Load Step (Buck)
Forced Continuous Mode
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢀ ꢃ0ꢄ
ꢀꢁꢂꢀ ꢃ0ꢄ
ꢀꢁꢂꢀ ꢃ0ꢄ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ ꢁꢂ
ꢀ ꢁꢂ
ꢀ ꢁꢂ
ꢀ00ꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
ꢀ00ꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
ꢀ00ꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
Inductor Current at Light Load
(Buck)
Buck Regulated Feedback Voltage
vs Temperature
Soft Start-Up
ꢀ0ꢀ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢂꢅꢁꢅꢆ
ꢀꢁꢂꢃ
Rꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ
ꢀꢁꢂRꢃꢄꢅꢀꢆ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃꢂꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢀ ꢃ0ꢀ
ꢀꢁꢂꢀ ꢃ0ꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢅꢁꢆꢇRꢈ ꢄ0 ꢉꢁRꢉꢇꢁꢊ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢃ ꢄ0ꢀ
ꢁꢂ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ ꢂꢁꢃꢄ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁꢂꢀ ꢃ0ꢄ
Rev 0
7
For more information www.analog.com
LTC7817
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current (Boost)
Efficiency
vs Output Current (Boost)
Efficiency vs Input Voltage (Boost)
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
ꢀꢁRꢂꢃ ꢄꢅꢅꢆꢇꢆꢄꢈꢇꢉ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ ꢊꢋꢌꢄ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ ꢃꢀꢀꢄꢁꢄꢃꢅꢁꢆ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ ꢃꢄꢅꢅ
0ꢀꢁ
0ꢀ0ꢁ
0ꢀ00ꢁ
ꢀꢁRꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃꢂꢄꢅ
ꢀꢁꢂꢂ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
ꢀꢁ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ ꢅꢈꢇRꢉꢃꢊꢅꢋ
ꢀꢁꢂ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
0ꢀꢁ ꢀ0
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
0ꢀ000ꢁ 0ꢀ00ꢁ
0ꢀ0ꢁ
ꢀ
0ꢀ000ꢁ 0ꢀ00ꢁ
0ꢀ0ꢁ
0ꢀꢁ
ꢀ
ꢀ0
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢀ ꢃꢂꢄ
ꢀꢁꢂꢀ ꢃꢂ0
ꢀꢁꢂꢀ ꢃꢂꢂ
Load Step (Boost)
Burst Mode Operation
Load Step (Boost)
Pulse-Skipping Mode
Load Step (Boost)
Forced Continuous Mode
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢀ ꢃꢂꢄ
ꢀꢁꢂꢀ ꢃꢂꢄ
ꢀꢁꢂꢀ ꢃꢂꢄ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁ0ꢂ
ꢀ
ꢀ ꢁ0ꢂ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀ00ꢁꢂ ꢃꢄ ꢀꢅꢀꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
ꢀ00ꢁꢂ ꢃꢄ ꢀꢅꢀꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
ꢀ00ꢁꢂ ꢃꢄ ꢀꢅꢀꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
Inductor Current at Light Load
(Boost)
Boost Regulated Feedback
Voltage vs Temperature
Soft Start-Up (Boost)
ꢀꢁꢂ0ꢃ
ꢀꢁꢂ0ꢃ
ꢀꢁꢂ0ꢀ
ꢀꢁꢀꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢁRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢂꢅꢁꢅꢆ
ꢀꢁꢂꢃ
Rꢀꢁꢂ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ
ꢀꢁꢂRꢃꢄꢅꢀꢆ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢃꢂꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
ꢃ ꢄꢀ
ꢀ
ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢀ ꢃꢂꢀ
ꢀꢁꢂꢀ ꢃꢂꢄ
ꢀꢁꢂꢃꢄꢅꢆ
ꢅꢁꢆꢇRꢈ ꢉ0 ꢊꢁRꢊꢇꢁꢋ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢃ ꢄꢀ
ꢁꢂ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁ ꢂꢁꢃꢄ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢃRꢄ ꢅ0 ꢆꢁRꢆꢃꢁꢇ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁꢂꢀ ꢃꢂꢁ
Rev 0
8
For more information www.analog.com
LTC7817
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense
Current Sense Threshold vs ITH
Voltage
SENSE1,2– and SENSE3+ Current
vs Voltage
Threshold vs SENSE Common
Mode Voltage
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
0
ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀꢁRRꢂꢃꢄ
ꢀ0
ꢀ0
ꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀR ꢁꢂꢃꢁꢂꢄ ꢀꢁRRꢂꢃꢄ
ꢀ0
0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢀ
0
0ꢀꢁ 0ꢀꢁ 0ꢀꢁ 0ꢀꢁ ꢀꢁ0 ꢀꢁꢂ ꢀꢁꢂ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢂ ꢃꢄꢅꢁꢆꢇꢈ ꢉꢃꢊ
ꢀꢁꢂꢀꢁ ꢃꢄꢅꢆꢇꢈꢁ ꢉꢃꢊ
ꢀꢁꢂꢀꢁ ꢃꢄꢅꢆꢇꢈꢁ ꢉꢃꢊ
ꢀꢁꢂꢀ ꢃꢂꢄ
ꢀꢁꢂꢀ ꢃꢄ0
ꢀꢁꢂꢀ ꢃꢄꢂ
SENSE1,2– and SENSE3+ Input
Current vs Temperature
SENSE1,2+ and SENSE3− Input
Current vs Temperature
Buck Foldback Current Limit
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁ0
0ꢀꢁ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢀ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢀ
ꢀꢁꢂꢀꢁ ꢃ ꢄꢂꢅꢆ ꢀ0ꢁꢂꢃ
ꢀꢀ
0ꢀꢁ
ꢀꢁꢂꢀꢁ ꢃ ꢄꢅꢄꢆ
0ꢀꢁ
ꢀꢁꢂꢀꢁ ꢃ ꢄꢅꢆ
0ꢀꢁ
0ꢀ0
ꢀꢁꢂꢀꢁ ꢃ ꢄꢅ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀꢁꢂ0
ꢀꢁꢂꢀꢁ ꢃ 0ꢄ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁꢂꢃꢄ ꢀ0ꢁꢂꢃ
ꢀꢀ
ꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀꢁꢂꢃꢁꢂꢄ ꢀ ꢁꢂꢃꢄ ꢀ0ꢁꢂꢃ
ꢀꢀ
ꢀꢁ00
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
0
ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁꢁꢂꢃꢄꢅꢆ ꢇꢈꢉꢊꢄꢋꢁ ꢌꢍꢇꢎ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁꢂꢀ ꢃꢄꢅ
ꢀꢁꢂꢀ ꢃꢄꢄ
ꢀꢁꢂꢀ ꢃꢄꢅ
Oscillator Frequency
vs Temperature
BOOST3 Charge Pump Output
Current vs Frequency
BOOST3 Charge Pump Output
Current vs SW3 Voltage
ꢀ0
ꢀ
ꢀ00
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁꢁꢂꢃꢄꢅꢂꢆꢄ ꢇ ꢈꢉ
ꢀRꢁꢂ ꢃ 0ꢄ
ꢀꢁꢁꢂꢃꢄ ꢅ ꢆꢇꢈ
ꢀ0 ꢀꢁꢂ ꢃ ꢄꢅꢆ
R
R
R
ꢀꢁꢂꢃꢄ ꢅꢆ00ꢄꢇꢈꢉ
ꢀꢁꢂꢃ ꢄꢂ00ꢃꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉꢊꢋ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀRꢁꢂꢃꢄꢅꢆ ꢇꢈꢉ0ꢊꢋꢌꢍ
ꢀRꢁꢂꢃꢄꢅꢆꢇ ꢀꢁꢂꢁꢃꢄꢅꢆꢇ
ꢀ
ꢀꢀ
ꢀ
ꢀ
0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ0ꢂꢃ
ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ0ꢂꢃ
ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢃ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
0
ꢀ00 ꢀ000 ꢀꢁ00 ꢀ000 ꢀꢁ00 ꢀ000
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀꢁꢂ ꢃꢄꢅꢆꢇꢈꢉ ꢊꢃꢋ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁꢂꢀ ꢃꢄꢀ
ꢀꢁꢂꢀ ꢃꢄꢅ
ꢀꢁꢂꢀ ꢃꢄꢅ
Rev 0
9
For more information www.analog.com
LTC7817
TYPICAL PERFORMANCE CHARACTERISTICS
EXTVCC Switchover and INTVCC
Voltage vs Temperature
INTVCC Undervoltage Lockout
Thresholds vs Temperature
INTVCC Voltage vs Current
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢀꢁꢂꢃꢄꢅe
ꢀꢀ
ꢀꢁꢂꢃ ꢀ 0ꢁ
ꢀꢀ
ꢀꢁꢂꢃ Rꢄꢅꢄꢆꢇ
ꢀꢁꢂꢃ ꢀ ꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃ ꢀ ꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃ Rꢀꢁꢀꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ ꢄꢅꢂꢂꢆꢇꢈ
ꢀꢁꢂꢃ ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢀ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢊꢂꢋ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢀ
ꢀꢁꢂꢀ ꢃꢄ0
ꢀꢁꢂꢀ ꢃꢄꢁ
ꢀꢁꢂꢀ ꢃꢄꢅ
RUN Pin Thresholds
vs Temperature
VBIAS Sleep Mode Quiescent
Current vs Temperature
Shutdown Current
vs VBIAS Input Voltage
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂ0
ꢀꢁꢀꢂ
ꢀꢁꢀꢂ
ꢀꢁꢀꢂ
ꢀꢁꢀꢂ
ꢀꢁꢀ0
ꢀꢁ0ꢂ
ꢀꢁ0ꢂ
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
0
ꢀ
ꢀ ꢁꢂꢃ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀ
0
ꢀꢁꢂꢃ ꢀ 0ꢁꢂ ꢃꢄꢅꢃꢄꢆ ꢀ0ꢁ
ꢀꢀ
ꢀ
ꢀꢁꢂꢃ ꢀ 0ꢁꢂ ꢃꢄꢅꢃꢄꢆ ꢀꢁꢂꢁꢃ
ꢀꢀ
ꢀ
ꢀꢁꢂꢃ ꢀ ꢁꢂꢃꢄ ꢅꢆꢇꢅꢆꢁ ꢀꢁꢂꢁꢃ
ꢀꢀ
0
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ ꢃꢄꢅ
ꢀꢁꢂꢀ ꢃꢄꢂ
ꢀꢁꢂꢀ ꢃꢄꢄ
Rev 0
10
For more information www.analog.com
LTC7817
PIN FUNCTIONS
FREQ (Pin 1): Frequency Control Pin for the Internal
INTV (Pin 22): Output of the Internal 5.1V Low Dropout
CC
Oscillator. Connect to ground to set the switching fre-
Regulator. The driver and control circuits are powered by
this supply. Must be decoupled to ground with a minimum
of 4.7μF ceramic or tantalum capacitor.
quency to 380KHz. Connect to INTV to set the switch-
CC
ing frequency to 2.25MHz. Frequencies between 100kHz
and 3MHz can be programmed using a resistor between
the FREQ pin and ground. Minimize the capacitance on
this pin.
EXTVCC (Pin 23): External Power Input to an Internal LDO
Connected to INTV . This LDO supplies INTV power,
CC
CC
bypassing the internal LDO powered from V
whenever
BIAS
PLLIN/MODE (Pin 2): External Synchronization Input and
Mode Select Input. When an external clock is applied to
this pin, the phase-locked loop forces the rising TG1 sig-
nal to be synchronized with the rising edge of the external
clock, and the regulators operate in forced continuous
mode. When not synchronizing to an external clock, this
input, which acts on all three channels, determines how
the LTC7817 operates at light loads. Pulling this pin to
ground selects Burst Mode operation. An internal 100k
resistor to ground also invokes Burst Mode operation
EXTVCC is higher than 4.7V. See INTVCC Regulators in the
Applications Information section. Do not exceed 30V on
this pin. Connect this pin to ground if the EXTV LDO
CC
is not used.
VBIAS (Pin 24): Main Bias Input Supply Pin. A bypass
capacitor should be tied between this pin and ground.
BG1, BG2, BG3 (Pins 29, 21, 25): High Current Gate
Drives for Bottom N-Channel MOSFETs. Voltage swing at
these pins is from ground to INTV .
CC
when the pin is floating. Tying this pin to INTV forces
CC
BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26):
Bootstrapped Supplies to the Top Side Floating Drivers.
Connect capacitors between the corresponding BOOST
and SW pins for each channel. Also connect Schottky
diodes between the BOOST1 and INTVCC pins, the
BOOST2 and INTV pins, and the BOOST3 and INTV
continuous inductor current operation. Tying this pin to
INTV through a 100k resistor selects pulse-skipping
CC
operation.
SGND (Pin 8): Small Signal Ground common to all three
controllers, must be routed separately from high current
grounds to the common (-) terminals of the CIN capacitors.
CC
CC
CC
pins. Voltage swing at the BOOST1, 2 pins is from INTV
to (V +INTV ). Voltage swing at the BOOST3 pin is from
INTVIN to (VCC + INTV ).
RUN1, RUN2, RUN3 (Pins 9, 10, 11): Run Control Inputs
for Each Controller. Forcing any of these pins below
1.1V disables switching of the corresponding controller.
Forcing all of these pins below 0.7V shuts down the entire
LTC7817, reducing the quiescent current to approximately
1.5µA. These pins can be tied to V or V
on operation.
CC
OUT3
CC
SW1, SW2, SW3 (Pins 31, 19, 28): Switch Node
Connections to Inductors.
TG1, TG2, TG3 (Pins 32, 18, 27): High Current Gate
Drives for Top N-Channel MOSFETs. These are the out-
for always-
IN
BIAS
puts of floating drivers with a voltage swing of INTV
superimposed on the switch node voltage SW.
CC
VPRG3 (Pin 17): Boost Output Voltage Programming Pin.
This pin sets the boost channel to adjustable output volt-
age or to a fixed output voltage. Floating this pin allows
the boost channel output to be programmed through the
PGOOD1 (Pin 33): Open-Drain Power Good Output. The
VFB1 pin is monitored to ensure that VOUT1 is in regulation.
When V
is not within 10% of its regulation point,
OUT1
V
pin using external resistors, regulating V
to the
FB3
FB3
the PGOOD1 pin is pulled low.
1.2V reference. Connecting this pin to GND or INTV
CC
programs the boost channel output to 8V or 10V (respec-
tively), with V directly connected to the output.
FB3
Rev 0
11
For more information www.analog.com
LTC7817
PIN FUNCTIONS
TRACK/SS1, TRACK/SS2, SS3 (Pins 34, 16, 3): External
VFB3 (Pin 6): Boost Controller Feedback Input. When
VPRG3 is floating, connect an external resistor divider
between the boost output voltage and the VFB3 pin to
set the regulated voltage. When VPRG3 is connected to
Tracking and Soft-Start Input. For the buck channels, the
LTC7817 regulates the V
voltage to the lesser of 0.8V
FB1,2
or the voltage on the TRACK/SS1,2 pin. For the boost
channel, the LTC7817 regulates V to the lesser of 1.2V
ground or INTV , tie V directly to the boost converter
FB3
CC FB3
or the voltage on the SS3 pin. Internal 12.5µA pull-up
current sources are connected to these pins. A capacitor
to ground sets the startup ramp time to the final regu-
lated output voltage. The ramp time is equal to 0.65ms
for every 10nF of capacitance for the buck channels and
1ms for every 10nF for the boost channel. Alternatively,
a resistor divider on another voltage supply connected
to the TRACK/SS pins of the buck channels allows the
LTC7817 output to track the other supply during startup.
output.
SENSE1+, SENSE2+, SENSE3+ (Pins 37, 13, 4): The
Positive (+) Input to the Differential Current Comparators.
The ITH pin voltage and controlled offsets between the
SENSE– and SENSE+ pins in conjunction with RSENSE
set the current trip threshold. For the boost channel, the
+
SENSE3 pin supplies current to the current comparator
when it is greater than INTV .
CC
SENSE1–, SENSE2–, SENSE3– (Pins 38, 12, 5): The
ITH1, ITH2, ITH3 (Pins 35, 15, 7): Error Amplifier Outputs
and Regulator Compensation Points. Each associated
channel’s current comparator trip point increases with
this control voltage. Place compensation components
between the ITH pins and ground.
Negative (–) Input to the Differential Current Comparators.
–
When SENSE1 is 3.2V or greater, it supplies the major-
ity of the sleep mode quiescent current instead of V
,
BIAS
further reducing the input-referred quiescent current. For
the buck channels, the SENSE– pins supply current to the
current comparators when they are greater than INTV .
VFB1, VFB2 (Pins 36, 14): Buck Controller Feedback
CC
Inputs. Connect an external resistor divider between the
PGND (Exposed Pad Pin 39): Driver Power Ground.
Connects to the sources of bottom N-channel MOSFETs
and the (–) terminal(s) of decoupling capacitors. The
exposed pad must be soldered to PCB ground for rated
electrical and thermal performance.
output voltage and the V pin to set the regulated output
FB
voltage. Tie V to INTV to configure the bucks for a
FB2
CC
two-phase single output application, in which both buck
channels share V , ITH1, and TRACK/SS1.
FB1
Rev 0
12
For more information www.analog.com
LTC7817
FUNCTIONAL DIAGRAM
ꢀꢁꢂꢃ ꢂꢄꢅꢆꢆꢇꢈꢉ ꢊ ꢅꢆꢋ ꢌ
ꢀꢁꢂꢃ
ꢀꢀ
Rꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀꢁ
ꢀꢁꢁꢂꢃꢃ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀRꢁꢂꢁꢃꢄ
ꢀꢁꢂꢁꢃꢂ
ꢀRꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢄꢅꢆꢀR
ꢀꢁꢂ ꢃꢄꢄ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂ ꢁꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢀ
R
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃ
0ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢂꢃ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀ
R
ꢀꢁꢂꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀR
ꢀ00ꢁ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢃ
ꢀꢁꢂꢀꢁ
ꢀꢁꢂꢃ
ꢀꢀ
ꢃ
ꢀꢁꢂꢀꢁ
ꢀꢁꢂꢃꢄ ꢅꢂꢆꢃ
ꢀꢁꢂꢃ
R
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
0ꢀꢁꢂ
R
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢀꢁꢂ
ꢀꢀ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢀ
0ꢀꢁꢁꢂ
R
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
0ꢀꢁꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀRꢁꢂꢃꢄꢅꢅ
ꢀ
ꢀꢁꢀ
ꢀꢁꢁꢂꢃꢃ
ꢀ
ꢀꢀ
0ꢀꢁꢂꢃ
ꢀꢁꢁꢂꢃ ꢄꢅꢆꢇꢇꢈꢉ ꢊ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁ
ꢀꢁꢂRꢃꢄ
ꢀꢁꢂꢀ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
ꢀꢁ
Rꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ ꢁꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀꢀ
R
ꢀꢁꢂ
ꢀꢁꢂ
0ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀꢁ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈ
R
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢀꢁꢂ
ꢀR
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
R
ꢀ
Rꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁRꢂꢃ
ꢀꢁꢂꢃꢄ ꢅꢂꢆꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅꢀꢆꢇꢈ
ꢀꢁ ꢂꢃꢄꢅꢆ
ꢀ0ꢁ ꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂ
Rꢀ
R
ꢀ
ꢀꢁꢂꢃ
ꢀꢁRꢂꢃ
ꢀꢀ
ꢀꢁ
R
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂꢃꢃ
ꢀ
ꢀꢀꢁ
ꢀꢁꢂꢀ ꢃꢄ
Rev 0
13
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LTC7817
OPERATION (Refer to Functional Diagram)
Main Control Loop
pin allows the INTV power to be derived from a high
CC
efficiency external source such as one of the LTC7817
The LTC7817 is a synchronous three-channel controller
utilizing a constant frequency, peak current mode archi-
tecture. The two step-down (buck) controllers, channels
1 and 2, operate 180° out of phase with each other. The
step-up (boost) controller, channel 3, operates in phase
with channel 1. During normal operation, the main switch
(external top MOSFET for the buck channels or the exter-
nal bottom MOSFET for the boost channel) is turned on
when the clock for that channel sets the SR latch, causing
the inductor current to increase. The main switch is turned
off when the main current comparator, ICMP, resets the
SR latch. After the main switch is turned off each cycle,
the synchronous switch (the bottom MOSFET for the buck
channels or the top MOSFET for the boost channel) is
turned on which causes the inductor current to decrease
until either the inductor current starts to reverse, as indi-
cated by the current comparator IR, or the beginning of
the next clock cycle.
switching regulator outputs.
Each top MOSFET driver is biased from the floating boot-
strap capacitor C , which normally recharges during each
cycle through anBexternal diode when the switch voltage
goes low.
For buck channels 1 and 2, if the buck’s input voltage
decreases to a voltage close to its output, the loop may
enter dropout and attempt to turn on the top MOSFET
continuously. The dropout detector detects this and forces
the top MOSFET off for a short time every tenth cycle to
allow CB to recharge, resulting in a 99% duty cycle at
380kHz operation and approximately 98% duty cycle at
2MHz operation.
Shutdown and Start-Up (RUN1, RUN2, RUN3 and
TRACK/SS1, TRACK/SS2, SS3 Pins)
The three channels of the LTC7817 can be independently
shut down using the RUN1, RUN2 and RUN3 pins. Pulling
a RUN pin below 1.1V shuts down the main control loop
for that channel. Pulling all three pins below 0.7V disables
all controllers and most internal circuits, including the
INTVCC LDOs. In this state, the LTC7817 draws only 1.5μA
of quiescent current.
The peak inductor current at which ICMP trips and resets
the latch is controlled by the voltage on the ITH pin, which
is the output of the error amplifier EA. The error amplifier
compares the output voltage feedback signal at the V
FB
pin, (which is generated with an external resistor divider
connected across the output voltage, V , to ground)
OUT
to the internal reference voltage (0.8V for the bucks or
1.2V for the boost). When the load current increases, it
The RUN pins may be externally pulled up or driven
directly by logic. Each pin can tolerate up to 40V (abso-
causes a slight decrease in V relative to the reference,
FB
lute maximum), so it can be conveniently tied to V
or
BIAS
which causes the EA to increase the ITH voltage until the
to an input supply in always-on applications where one
or more controllers are enabled continuously and never
shut down. Additionally, a resistive divider from the input
supply to a RUN pin can be used to set a precise input
undervoltage lockout so that the power supply does not
operate below a user-adjustable level.
average inductor current matches the new load current.
Power and Bias Supplies (V , EXTV , and INTV )
BIAS CC CC
The INTVCC pin supplies power for the top and bottom
MOSFET drivers and most of the internal circuitry. LDOs
(low dropout linear regulators) are available from both the
The start-up of each channel’s output voltage V
is con-
V
and EXTV pins to provide power to INTV , which
OUT
BIAS
CC CC
trolled by the voltage on the TRACK/SS pin (TRACK/SS1
for channel 1, TRACK/SS2 for channel 2, SS3 for chan-
nel 3). When the voltage on the TRACK/SS pin is less than
the internal reference voltage (0.8V for the bucks or 1.2V
has a regulation point of 5.1V. When the EXTV pin is left
open or tied to a voltage less than 4.7V, theCVC
LDO
BIAS
(low dropout linear regulator) supplies power to INTV .
CC
If EXTV is taken above 4.7V, the V
LDO is turned
CC
BIAS
for the boost), the LTC7817 regulates the V voltage to
off and an EXTV LDO is turned on. Once enabled, the
FB
CC
the TRACK/SS pin voltage instead of the corresponding
EXTV LDO supplies power to INTV . Using the EXTV
CC
CC
CC
Rev 0
14
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LTC7817
OPERATION
reference voltage. This allows the TRACK/SS pin to be
used as a soft-start which smoothly ramps the output
voltage on startup, thereby limiting the input supply
inrush current. An external capacitor from the TRACK/
SS pin to GND is charged by an internal 12.5μA pull-up
current, creating a voltage ramp on the TRACK/SS pin. As
the TRACK/SS voltage rises linearly from 0V to 0.8V/1.2V
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC7817 draws.
If one channel is in sleep mode and the other two are shut
down, the LTC7817 draws only 15μA of quiescent current.
If all three channels are in sleep mode, the LTC7817 draws
only 18µA of quiescent current. When V
on channel 1
OUT
is 3.2V or higher, the majority of this quiescent current is
–
(and beyond), the output voltage V
from zero to its final value.
rises smoothly
supplied by the SENSE1 pin, which further reduces the
OUT
input-referred quiescent current by the ratio of V /V
IN OUT
multiplied by the efficiency.
Alternatively, the TRACK/SS pins for buck channels 1 and
2 can be used to make the start-up of V track that
of another supply. Typically this requires connecting to
the TRACK/SS pin through an external resistor divider
from the other supply to ground (see the Applications
Information section).
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s out-
put begins to rise. When the output voltage drops enough,
the ITH pin is reconnected to the output of the EA, the
sleep signal goes low, and the controller resumes normal
operation by turning on the main switch on the next cycle
of the internal oscillator.
OUT
Light Load Operation: Burst Mode Operation, Pulse-
Skipping, or Forced Continuous Mode (PLLIN/MODE Pin)
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the synchronous switch
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous operation.
The LTC7817 can be set to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping
mode or forced continuous conduction mode at low load
currents.
To select Burst Mode operation, tie the PLLIN/MODE pin
to ground. To select forced continuous operation, tie the
PLLIN/MODE pin to INTVCC. To select pulse-skipping
mode, tie the PLLIN/MODE pin to a DC voltage greater
than 1.2V and less than INTV – 1.3V. An internal 100k
resistor to ground invokes BCuCrst Mode operation when
the PLLIN/MODE pin is floating and pulse-skipping mode
In forced continuous operation the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to audio circuitry. In forced continuous mode,
the output ripple is independent of load current.
when the PLLIN/MODE pin is tied to INTV through an
external 100k resistor.
CC
When the controllers are enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
approximately 25% of its maximum value even though
the voltage on the ITH pin might indicate a lower value. If
the average inductor current is higher than the load cur-
rent, the error amplifier EA will decrease the voltage on
the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.45V.
When the PLLIN/MODE pin is connected for pulse-skip-
ping mode, the LTC7817 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator ICMP may remain tripped for several
cycles and force the main switch to stay off for the same
Rev 0
15
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LTC7817
OPERATION
number of cycles (i.e., skipping pulses). The inductor cur-
rent is not allowed to reverse (discontinuous operation).
This mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference as compared to Burst Mode operation. It pro-
vides higher low current efficiency than forced continuous
mode, but not nearly as high as Burst Mode operation.
Boost Controller Operation When V > V
IN OUT
When the input voltage to the boost channel rises above
its regulated V voltage, the controller can behave dif-
OUT
ferently depending on the mode, inductor current and VIN
voltage. When V exceeds the regulated V in forced
IN
OUT
continuous mode, the loop works to keep the top MOSFET
on continuously. An internal charge pump delivers current
to the boost capacitor from the BOOST3 pin to maintain
a sufficiently high TG3 voltage.
When synchronizing to an external clock applied to the
PLLIN/MODE pin, the LTC7817 operates in forced con-
tinuous mode.
If V is between 100% and 110% of the regulated V
IN
OUT
voltage and pulse-skipping mode is selected, TG3 turns
on if the inductor current rises above approximately 4%
of the programmed current limit. Similarly, if Burst Mode
operation is selected, then TG3 turns on as long as at
least one channel is awake. If both buck channels are
asleep or shut down, TG3 remains off regardless of the
inductor current.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The free running switching frequency of the LTC7817
controllers is selected using the FREQ pin. Tying FREQ to
GND selects 380kHz while tying FREQ to INTV selects
2.25MHz. Placing a resistor between FREQ CaCnd GND
allows the frequency to be programmed between 100kHz
and 3MHz.
If V rises above 110% of the regulated V
voltage
OUT
IN
in any mode, the controller turns on TG3 continuously
regardless of the inductor current. In Burst Mode opera-
tion, however, the internal charge pump is disabled when
none of the channels are awake. With the charge pump
off, the boost capacitor may discharge, resulting in an
insufficient TG3 voltage needed to keep the top MOSFET
completely on.
A phase-locked loop (PLL) is available on the LTC7817
to synchronize the internal oscillator to an external clock
source connected to the PLLIN/MODE pin. The LTC7817’s
PLL aligns the turn-on of controller 1’s external top
MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external top MOSFET
is 180° out-of-phase to the rising edge of the external
clock source.
Boost Controller at Low Input Voltage
The PLL frequency is prebiased to the free running fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL only needs to make slight changes in order to
synchronize the rising edge of the external clock to the
rising edge of TG1. For more rapid lock-in to the external
clock, use the FREQ pin to set the internal oscillator to
approximately the frequency of the external clock. The
LTC7817’s PLL is guaranteed to lock to an external clock
source whose frequency is between 100kHz and 3MHz.
The LTC7817 features a rail-to-rail current comparator for
the boost channel which functions down to zero volts. The
minimum boost converter input voltage is therefore deter-
mined by the practical limitations of the boost converter
architecture. Since the input voltage could be lower than
the 4.5V V
limit, V
can be connected to the output
BIAS
BIAS
of the boost controller, as illustrated in the typical applica-
tion circuit in Figure 10. This allows the boost controller to
handle very low input voltage transients while maintaining
output voltage regulation.
The PLLIN/MODE pin is TTL compatible with thresholds
of 1.6V (rising) and 1.1V (falling) and is guaranteed to
operate with a clock signal swing of 0.5V to 2.5V.
Rev 0
16
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LTC7817
OPERATION
Buck Controller Output Overvoltage Protection
interval (as long as the V voltage is keeping up with
FB
the TRACK/SS1,2 voltage). There is no foldback current
The two buck channels have an overvoltage comparator
that guards against transient overshoots as well as other
more serious conditions that may overvoltage their out-
limiting for the boost channel.
Channel 1 Power Good (PGOOD1)
puts. When the V
pin rises more than 10% above its
FB1,2
Channel 1 has a PGOOD1 pin that is connected to an
open drain of an internal N-channel MOSFET. The MOSFET
regulation point of 0.8V, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared.
turns on and pulls the PGOOD1 pin low when the V
FB1
pin voltage is not within 10% of the 0.8V reference. The
PGOOD1 pin is also pulled low when the RUN1 pin is
Buck Foldback Current
low (shut down). When the V pin voltage is within the
FB1
When the buck output voltage falls to less than 50% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
10% requirement, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to a
source no greater than 6V, such as INTV .
CC
Rev 0
17
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LTC7817
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic
LTC7817 application circuit. External component selection
is largely driven by the load requirement and begins with
the selection of the inductor, current sense components,
operating frequency, and light load operating mode. The
remaining power stage components, consisting of the
input and output capacitors, and power MOSFETs can
then be chosen. Next, feedback resistors are selected
to set the desired output voltage. Then, the remaining
external components are selected, such as for soft-start,
biasing, and loop compensation.
current limit for a given VIN is exceeded, VOUT will decrease
until the I
= I
• V /V
equation is satis-
OUT(MAX) L(MAX)
IN OUT
fied. Additionally, when the output is in overvoltage (V >
IN
VOUT), the top switch is on continuously and the maximum
load current is equal to I
. The inductor ripple cur-
L(MAX)
rent ΔI for a boost regulator increases with higher V
:
L
OUT
�
�
÷
�
1
V
IN
� I =
V
1�
�
�
L
IN
(f)(L)
V
OUT
Accepting larger values of ΔIL allows the use of low induc-
tances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for set-
Inductor Value Calculation
ting ripple current is ΔI = 0.3 • I
L
. The maximum
L
L(MAX)
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET switching and gate charge losses. In addi-
tion to this basic trade-off, the effect of inductor value
on ripple current and low current operation must also
be considered. The inductor value has a direct effect on
ripple current.
ΔI occurs at the maximum input voltage for a buck and
at V = V /2 for a boost.
IN
OUT
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ΔI ) will cause this to occur at
L
lower load currents, which can cause a dip in efficiency
in the upper range of low current operation.
Inductor Core Selection
For a buck regulator, the maximum average inductor cur-
Once the value for L is known, the type of inductor must
be selected. High efficiency regulators generally can-
not afford the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite or
molypermalloy cores. Actual core loss is very dependent
on inductance value selected. As inductance increases,
core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
rent I
is equal to the maximum output current. The
L(MAX)
peak current is equal to the average inductor current plus
half of the inductor ripple current, ΔI , which for a buck
L
regulator decreases with higher inductance or higher fre-
quency and increases with higher V :
IN
�
�
1
V
OUT
� I =
V
1�
L
OUT
�
÷
(f)(L)
V
IN
�
�
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
For a boost regulator, the maximum average output
current in continuous conduction mode is equal to the
maximum average inductor current multiplied by a factor
of V /V , or I
= I
• V /V . Be aware
IN OUT
OUT(MAX)
L(MAX) IN OUT
that the maximum output current from a boost regulator
decreases with decreasing VIN. The choice of IL(MAX) there-
fore depends on the maximum load current for a regulated
V
at the minimum normal operating V . If the load
OUT
IN
Rev 0
18
For more information www.analog.com
LTC7817
APPLICATIONS INFORMATION
Current Sense Selection
Filter components mutual to the sense lines should be
placed close to the LTC7817, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
The LTC7817 can be configured to use either DCR (induc-
tor resistance) sensing or low value resistor sensing.
The choice between the two current sensing schemes
is largely a design trade-off between cost, power con-
sumption and accuracy. DCR sensing has become popular
because it saves expensive current sensing resistors and
is more power efficient, particularly in higher current and
lower frequency applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
ꢄꢅ ꢆꢇꢈꢆꢇ ꢃꢉꢊꢄꢇR
ꢈꢇꢋꢄ ꢄꢅ ꢄꢌꢇ ꢍꢅꢈꢄRꢅꢊꢊꢇR
ꢍꢏRRꢇꢈꢄ ꢃꢊꢅꢐ
ꢀꢁꢂꢀ ꢃ0ꢂ
ꢉꢈꢎꢏꢍꢄꢅR ꢅR R
ꢆꢇꢈꢆꢇ
R
SENSE
(if R
is used) and inductor value.
SENSE
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
+
–
The SENSE and SENSE pins are the inputs to the cur-
rent comparators. The common mode voltage range on
these pins is 0V to 40V (absolute maximum), enabling
the LTC7817 to regulate output voltages up to a maxi-
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small signal nodes.
+
+
–
mum of 40V. The SENSE1 , SENSE2 , and SENSE3 pins
are high impedance, drawing less than ≈1μA. This high
impedance allows the current comparators to be used in
–
inductor DCR sensing. The impedance of the SENSE1 ,
–
+
Low Value Resistor Current Sensing
SENSE2 , and SENSE3 pins changes depending on the
common mode voltage. When less than INTV – 0.5V,
A typical sensing circuit using a discrete resistor is shown
CC
these pins are relatively high impedance, drawing ≈1μA.
in Figure 2a. R
is chosen based on the required out-
SENSE
When above INTV + 0.5V, a higher current (≈600μA)
put current. Each controller’s current comparator has a
maximum threshold VSENSE(MAX) of 50mV. The current
comparator threshold voltage sets the peak inductor
current.
CC
flows into each pin. Between INTV – 0.5V and INTV
CC
CC
+ 0.5V, the current transitions from the smaller current
to the higher current. Channel 1’s SENSE1– pin has an
additional ≈40μA current when its voltage is above 3.2V
to bias internal circuitry from VOUT1, thereby reducing the
input-referred supply current.
Using the maximum inductor current (I
) and ripple
L(MAX)
current (ΔI ) from the Inductor Value Calculation section,
L
the target sense resistor value is:
V
SENSE(MAX)
R
�
SENSE
� I
L
I
+
L(MAX)
2
Rev 0
19
For more information www.analog.com
LTC7817
APPLICATIONS INFORMATION
ꢋ
ꢉꢊꢂꢒꢄ
ꢔꢋ
ꢗ
ꢎꢘꢇꢕ
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
ꢉꢊꢇꢋ
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ꢉꢊꢛꢘꢈꢇꢚꢊꢈꢑ
ꢍꢎꢎꢏꢇ
R
ꢆ
ꢑꢏꢆ
ꢏꢑꢊꢏꢑ
ꢋ
ꢎꢘꢇꢂꢒꢄ
ꢔꢋ
ꢏꢐ
ꢍꢌ
To avoid potential jitter or instability due to PCB noise cou-
pling into the current sense signal, the AC current sensing
ꢗ
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R
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ꢃ ꢏꢑꢊꢏꢑ
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R
ꢃ
ripple of ΔV
= ΔI • R
should also be checked
SENSE
L
SENSE
ꢓ
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ꢖ
ꢔꢏꢑꢊꢏꢑꢕ ꢗ
to ensure a good signal-to-noise ratio. In general, for a
reasonably good PCB layout, a target ΔV voltage of
ꢈ
ꢃ
ꢖ
ꢏꢑꢊꢏꢑꢂꢒ ꢄ
SENSE
ꢓ
ꢔꢏꢑꢊꢏꢑꢕ ꢗ
ꢙꢆꢚꢈꢑ R ꢚꢊꢛ ꢈ ꢊꢑꢚR ꢏꢑꢊꢏꢑ ꢙꢉꢊꢏ
ꢃ
ꢃ
10mV to 20mV at nominal input voltage for the bucks or
ꢀꢁꢂꢀ ꢃ0ꢄꢅ
at 50% duty cycle for the boost is recommended for both
2a. Using a Resistor to Sense Current
R
and DCR sensing applications.
SENSE
The parasitic inductance (ESL) of the sense resistor
introduces significant error in the current sense signal
for lower inductor value (<3uH) or higher current (>5A)
applications. For a buck converter, this error is propor-
tional to the input voltage and may degrade line regulation
or cause loop instability. An RC filter into the sense pins,
as shown in Figure 2a, can be used to compensate for
this error. Set the RC filter time constant R • C = ESL/
ꢋ
ꢉꢊꢂꢒꢄ
ꢍꢙꢇꢕ
ꢔꢋ
ꢗ
ꢉꢊꢇꢋ
ꢈꢈ
ꢌꢍꢍꢎꢇ
ꢇꢏ
ꢉꢊꢘꢙꢈꢇꢍR
ꢘꢈR
ꢆꢇꢈꢀꢁꢂꢀ
ꢆ
ꢋ
ꢍꢙꢇꢂꢒꢄ
ꢉꢊꢕ
ꢎꢐ
ꢌꢏ
ꢔꢋ
ꢗ
Rꢂ
F
F
R
for optimal cancellation of the ESL. In general,
SENSE
ꢓ
ꢖ
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ꢔꢎꢑꢊꢎꢑꢕ ꢗ
select C to be in the range of 1nF to 10nF and calculate
F
ꢈꢂꢚ
Rꢄ
ꢖ
ꢓ
the corresponding R . Surface mount sense resistors in
ꢎꢑꢊꢎꢑꢂꢒ ꢄ
ꢔꢎꢑꢊꢎꢑꢕ ꢗ
F
low ESL wide footprint geometries are recommended to
minimize this error. If not specified on the manufacturer's
data sheet, the ESL can be approximated as 0.4nH for
a resistor with a 1206 footprint and 0.2nH for a 1225
footprint.
ꢏꢊꢘ
ꢀꢁꢂꢀ ꢃ0ꢄꢅ
ꢔRꢂꢠꢠRꢄꢗ ꢡ ꢈꢂ ꢞ ꢆꢟꢘꢈR
R ꢞ ꢘꢈRꢔRꢄꢟꢔRꢂꢓRꢄꢗꢗ
ꢎꢑꢊꢎꢑꢔꢑꢝꢗ
ꢚꢛꢆꢜꢈꢑ ꢈꢂ ꢊꢑꢜR ꢎꢑꢊꢎꢑ ꢛꢉꢊꢎ
2b. Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
Inductor DCR Current Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC7817 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
Rev 0
20
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If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1+R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
The sense resistor values are:
R1 R2 R1• R
D
R1=
; R2 =
R
1� R
D
D
The maximum power loss in R1 is related to duty cycle.
For the buck controllers, the maximum power loss occurs
in continuous mode at the maximum input voltage:
(V
� V
) • V
IN(MAX)
OUT OUT
P
R1=
LOSS
R1
For the boost controller, the maximum power loss occurs
in continuous mode at V = V /2:
IN
OUT
Using the maximum inductor current (I
) and ripple
L(MAX)
current (ΔI ) from the Inductor Value Calculation section,
(V
� V ) • V
L
IN
IN
OUT(MAX)
P
R1=
the target sense resistor value is:
LOSS
R1
V
SENSE(MAX)
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing
or sense resistors. Light load power loss can be mod-
estly higher with a DCR network than with a sense resis-
tor, due to the extra switching losses incurred through
R1. However, DCR sensing eliminates a sense resistor,
reduces conduction losses and provides higher efficiency
at heavy loads. Peak efficiency is about the same with
either method.
R
�
SENSE(EQUIV)
� I
L
I
+
L(MAX)
2
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
Setting the Operating Frequency
0.4%/°C. A conservative value for T
is 100°C. To
L(MAX)
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing gate charge and transition losses, but requires
larger inductance values and/or more output capacitance
to maintain low output ripple voltage.
scale the maximum inductor DCR to the desired sense
resistor value (R ), use the divider ratio:
D
R
SENSE(EQUIV)
R =
D
DCR
at T
L(MAX)
MAX
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1||R2 to around 2k, reducing error that might
In higher voltage applications transition losses contrib-
ute more significantly to power loss, and a good balance
between size and efficiency is generally achieved with a
switching frequency between 300kHz and 900kHz. Lower
voltage applications benefit from lower switching losses
and can therefore more readily operate at higher switching
frequencies up to 3MHz if desired.
+
have been caused by the SENSE pin’s ≈1μA current.
The target equivalent resistance R1||R2 is calculated from
the nominal inductance, C1 value, and DCR:
L
R1 R2 =
(DCR at 20°C) • C1
Rev 0
21
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LTC7817
APPLICATIONS INFORMATION
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
A further constraint on the operating frequency is due
to the maximum duty cycle of the boost channel. The
maximum duty cycle, which can be approximated as
DC
≈ (1-V
/V
)*100%, is limited as shown
MAX
IN(MIN) OUT3
in Figure 3a. At low frequencies, the output will dropout
if the required duty cycle is higher than 93%. At high
frequencies, the maximum duty cycle available to main-
tain constant frequency operation is reduced further. In
this region, if a higher duty cycle is required to keep the
output voltage in regulation, the controller will skip the
top MOSFET (TG3) turn-on and keep the bottom MOSFET
(BG3) on for more than one clock cycle to achieve the
higher duty cycle at an effectively lower frequency. Choose
a frequency that limits the maximum duty cycle to a value
lower than the curve shown in Figure 3a. The switching
frequency is set using the FREQ and PLLIN/MODE pins
as shown in Table 1.
ꢀꢀꢁꢂꢃ ꢄꢅ ꢆꢁꢆꢂꢇꢈꢉ
ꢀ00ꢁ
ꢀꢁ
ꢀꢁ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀꢁꢂꢀ ꢃ0ꢄꢅ
3a. Relationship Between Oscillator Frequency
and Boost Channel Maximum Duty Cycle
ꢀ0ꢁ
Table 1.
FREQ PIN
PLLIN/MODE PIN
DC Voltage
FREQUENCY
380kHz
0V
ꢀꢁ
INTV
DC Voltage
2.25MHz
CC
Resistor to GND
Any of the Above
DC Voltage
100kHz to 3MHz
External Clock
100kHz to 3MHz
Phase-Locked to
External Clock
ꢀ00ꢁ
Tying the FREQ pin to ground selects 380kHz while
ꢀ0ꢁ
ꢀ00ꢁ
ꢀ00ꢁ
tying FREQ to INTV selects 2.25MHz. Placing a resis-
ꢀRꢁꢂ ꢃꢄꢅ RꢁꢆꢄꢆꢇꢈR ꢉꢈꢊꢋꢌꢍ
CC
ꢀꢁꢂꢀ ꢃ0ꢄꢅ
tor between FREQ and ground allows the frequency to
be programmed anywhere between 100kHz and 3MHz.
Choose a FREQ pin resistor from Figure 3b or the follow-
ing equation:
3b. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
Figure 3. Setting the Operating Frequency
37MHz
R
(in k� )=
FREQ
f
OSC
Rev 0
22
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A phase-locked loop (PLL) is also available on the
LTC7817 to synchronize the internal oscillator to an exter-
nal clock source connected to the PLLIN/MODE pin. After
the PLL locks, TG1 is synchronized to the rising edge of
the external clock signal, and TG2 is 180° out of phase
from TG1. See the Phase-Locked Loop and Frequency
Synchronization section for details.
In general, the requirements of each application will dictate
the appropriate choice for light-load operating mode. In
Burst Mode operation, the inductor current is not allowed
to reverse. The reverse current comparator turns off the
bottom MOSFET just before the inductor current reaches
zero, preventing it from reversing and going negative.
Thus, the regulator operates in discontinuous operation.
In addition, when the load current is very light, the induc-
tor current will begin bursting at frequencies lower than
the switching frequency, and enter a low current sleep
mode when not switching. As a result, Burst Mode opera-
tion has the highest possible efficiency at light load.
Selecting the Light-Load Operating Mode
The LTC7817 can be set to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode
or forced continuous conduction mode at light load cur-
rents. To select Burst Mode operation, tie the PLLIN/
MODE to ground. To select forced continuous operation,
In forced continuous mode, the inductor current is
allowed to reverse at light loads and switches at the same
frequency regardless of load. In this mode, the efficiency
at light loads is considerably lower than in Burst Mode
operation. However, continuous operation has the advan-
tage of lower output voltage ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
tie the PLLIN/MODE pin to INTV . To select pulse-skip-
CC
ping mode, tie the PLLIN/MODE pin to INTV through a
CC
100k resistor. An internal 100k resistor from the PLLIN/
MODE pin to ground selects Burst Mode if the pin is float-
ing. When synchronized to an external clock through the
PLLIN/MODE pin, the LTC7817 operates in forced con-
tinuous mode. Table 2 summarizes the use of the PLLIN/
MODE pin to select the light load operating mode.
In pulse-skipping mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the PWM
comparator may remain tripped for several cycles and
force the top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output rip-
ple as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
light load efficiency than forced continuous mode, but not
nearly as high as Burst Mode operation. Consequently,
pulse-skipping mode represents a compromise between
light load efficiency, output ripple and EMI.
Table 2.
PLLIN/MODE PIN
LIGHT-LOAD OPERATING MODE WHEN
MODE
SYNCHRONIZED
Forced Continuous
Forced Continuous
Forced Continuous
0V or Floating
Burst Mode
100k to INTV
Pulse-Skipping
Forced Continuous
CC
INTV
CC
Rev 0
23
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LTC7817
APPLICATIONS INFORMATION
V
In some applications, it may be desirable to change light
load operating mode based on the conditions present in
the system. For example, if a system is inactive, one might
select high efficiency Burst Mode operation by keeping
the PLLIN/MODE pin set to 0V. When the system wakes,
one might send an external clock to PLLIN/MODE, or tie
PLLIN/MODE to INTVCC to switch to low noise forced con-
tinuous mode. Such on-the-fly mode changes can allow
an individual application to benefit from the advantages
of each light load operating mode.
OUT
Buck Main Switch Duty Cycle =
Buck Sync Switch Duty Cycle =
Boost Main Switch Duty Cycle =
Boost Sync Switch Duty Cycle =
V
IN
V � V
IN
OUT
V
IN
V
� V
IN
OUT
V
OUT
V
IN
V
OUT
For a buck converter, the MOSFET power dissipations at
maximum output current are given by:
Power MOSFET Selection
Two external power MOSFETs must be selected for each
controller in the LTC7817: one N-channel MOSFET for the
top switch (main switch for the buck, synchronous for the
boost), and one N-channel MOSFET for the bottom switch
(main switch for the boost, synchronous for the buck).
2
V
OUT
P
=
I
1+ � R
+
DS(ON)
(
)
(
)
MAIN_BUCK
OUT(MAX)
V
IN
�
�
�
�
I
OUT(MAX)
2
(V )
(R )(C
) •
MILLER
÷
IN
DR
2
�
The peak-to-peak gate drive levels are set by the INTV
�
�
�
CC
1
1
+
(f)
�
regulation point of 5.1V. Consequently, logic level thresh-
old MOSFETs must be used in most applications. Pay
close attention to the BVDSS specification for the MOSFETs
as well; many of the logic level MOSFETs are limited to
30V or less.
V
� V
V
�
�
THMIN
THMIN
OUT
INTVCC
2
V � V
IN
P
=
I
(
1+ � R
(
)
)
SYNC_BUCK
OUT(MAX)
DS(ON)
V
IN
Similarly, for a boost converter:
� V
Selection criteria for the power MOSFETs include the on
resistance RDS(ON), Miller capacitance CMILLER, input volt-
age and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge
curve usually provided on the MOSFET manufacturers’
V
V
OUT
2
(
)
IN
OUT
P
=
I
•
(
)
MAIN_BOOST
OUT(MAX)
2
V
IN
3
�
�
÷
�
�
�
I
V
OUT(MAX)
OUT
�
�
1+ � R
+
•
(
(
)
�
÷
�
DS(ON)
data sheet. C
is equal to the increase in gate charge
÷
along the horMizIoLLnEtRal axis while the curve is approximately
V
2
�
IN
�
�
�
�
�
flat divided by the specified change in V . This result is
1
1
DS
R
C
•
+
(f)
)
�
(
)
DR
MILLER
then multiplied by the ratio of the application applied V
to the gate charge curve specified VDS. When the ICDisS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
V
� V
V
THMIN
�
THMIN
INTVCC
2
V
OUT
P
=
I
(
1+ � R
DS(ON)
(
)
)
SYNC_BOOST
OUT(MAX)
V
IN
where δ is the temperature dependency of RDS(ON)
(δ≈ 0.005/°C) and RDR is the effective driver resistance at
Rev 0
24
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the MOSFET’s Miller threshold voltage (RDR≈2Ω). VTHMIN
is the typical MOSFET minimum threshold voltage.
The output current in a boost converter is discontinuous,
so C
should be selected to meet output voltage ripple
OUT
requirements. The effects of ESR (equivalent series resis-
tance) and the bulk capacitance must be considered when
choosing the right capacitor for a given output ripple volt-
age. The ripple due to charging and discharging the bulk
2
Both MOSFETs have I R losses while the main N channel
equations for the buck and boost controllers include an
additional term for transition losses, which are highest
at high input voltages for the bucks and high output volt-
capacitance of C
is given by:
OUT
ages for the boost. For V < 20V for the bucks (or V
IN
OUT
I
• V
� V
IN(MIN)
< 20V for the boost) the high current efficiency generally
(
)
OUT(MAX)
OUT
Ripple =
V
improves with larger MOSFETs, while for V > 20V for the
IN
C
• V
• f
OUT
OUT
bucks (V
> 20V for the boost) the transition losses rap-
OUT
The ripple due to the voltage drop across the ESR is given
by:
idly increase to the point that the use of a higher R
DS(ON)
device with lower C
actually provides higher effi-
MILLER
ciency. The synchronous MOSFET losses for the buck
controllers are greatest at high input voltage when the top
switch duty factor is low or during a short-circuit when
the synchronous switch is on close to 100% of the period.
�
�
�
�
1
� V
= I
+ � I �ESR
÷
÷
L(MAX) L
�
�
ESR
�
�
�
�
2
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings such as OS-CON and POSCAP.
Boost C and C
Selection
OUT
IN
The input ripple current in a boost converter is relatively
low (compared to the output ripple current) because this
current is continuous. The boost input capacitor C volt-
IN
age rating should comfortably exceed the maximum input
voltage. Although ceramic capacitors can be relatively
tolerant of overvoltage conditions, aluminum electrolytic
capacitors are not. Be sure to characterize the input volt-
age for any possible overvoltage transients that could
apply excess stress to the input capacitors.
Buck C and C
Selection
OUT
IN
The selection of C for the two buck controllers is sim-
IN
plified by the two-phase architecture and its impact on
the worst-case RMS current drawn through the input
network (battery/fuse/capacitor). It can be shown that
the worst-case capacitor RMS current occurs when only
one controller is operating. The controller with the high-
The value of CIN is a function of the source impedance, and
in general, the higher the source impedance, the higher
the required input capacitance. The required amount of
input capacitance is also greatly affected by the duty cycle.
High output current applications that also experience high
duty cycles can place great demands on the input supply,
both in terms of DC current and ripple current.
est V
• I
product needs to be used in the formula
showOnUTin EOqUuTation 1 to determine the maximum RMS
capacitor current requirement.
Rev 0
25
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Increasing the output current drawn from the other con-
troller will actually decrease the input RMS ripple current
from its maximum value. The out-of-phase technique typi-
cally reduces the input capacitor’s RMS ripple current by
a factor of 30% to 70% when compared to a single phase
power supply solution.
source impedance of the power supply/battery is included
in the efficiency testing.
The drains of the top MOSFETs should be placed within
1cm of each other and share a common C (s). Separating
IN
the drains and C may produce undesirable resonances
IN
at V .
IN
In continuous mode, the source current of the top
A small (0.1μF to 1μF) bypass capacitor between the chip
MOSFET is a square wave of duty cycle V /V . To pre-
OUT IN
V
pin and ground, placed close to the LTC7817, is
BIAS
vent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. At maximum load current IMAX, the maximum RMS
capacitor current is given by:
also suggested. An optional 1Ω to 10Ω resistor placed
between C and the V pin provides further isolation
IN
BIAS
from a noisy input supply.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
I
1/2
MAX
�
�
C Required I
�
V
V � V
IN
OUT
(
)(
)
�
�
IN
RMS
OUT
V
IN
This formula has a maximum at VIN = 2VOUT, where
= I /2. This simple worst-case condition is com-
output ripple (ΔV ) is approximated by:
OUT
I
RMS
OUT
�
�
1
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufactur-
ers’ ripple current ratings are often based on only 2000
hours of life. This makes it advisable to further derate
the capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be par-
alleled to meet size or height requirements in the design.
Due to the high operating frequency of the LTC7817,
� V
� � I ESR +
L
OUT
�
÷
8fC
�
�
OUT
where f is the operating frequency, C
is the output
OUT
capacitance and ΔI is the ripple current in the inductor.
The output ripple iLs highest at maximum input voltage
since ΔI increases with input voltage.
L
Setting the Buck Output Voltage
ceramic capacitors can also be used for C . Always con-
sult the manufacturer if there is any question.
IN
The LTC7817 output voltages for the buck channels are
each set by an external feedback resistor divider care-
fully placed across the output, as shown in Figure 4 The
regulated output voltage is determined by:
The benefit of the LTC7817 two-phase operation can be
calculated by using this equation for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a two-phase system. The overall benefit
of a multiphase design will only be fully realized when the
�
�
÷
�
R
R
B
A
V
= 0.8V 1+
�
OUT, BUCK
�
Place resistors R and R very close to the V pin to
A
B
FB
minimize PCB trace length and noise on the sensitive V
FB
node. Great care should be taken to route the V trace
FB
away from noise sources, such as the inductor or the
SW trace. To improve frequency response, a feedforward
capacitor (C ) may be used.
FF
Rev 0
26
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ꢉ
ꢏꢒꢇꢋ
ꢊ
ꢍꢎꢈ
ꢆꢇꢈꢀꢁꢂꢀ
ꢉꢌRꢍꢋ
R
R
ꢈ
ꢃꢃ
ꢊ
R
R
ꢉ
ꢃꢃ
ꢋ
ꢌ
ꢂꢅꢆ ꢇꢈꢉꢀꢁꢂꢀ
ꢎꢃꢆꢏꢐꢇꢑ
ꢉ
ꢃꢊꢋ
ꢊ
ꢃꢋ
ꢐ
ꢀꢁꢂꢀ ꢃ0ꢄꢅ
ꢀꢁꢂꢀ ꢃ0ꢄ
5a. Setting Boost Output Using External Resistors
Figure 4. Setting Buck Output Voltage
ꢆꢇꢈꢀꢁꢂꢀ
For applications with multiple output voltage levels, select
ꢉ
ꢒꢓꢇꢋ
ꢍꢎꢏꢐꢑꢎꢇꢉ
ꢉꢌRꢍꢋ
ꢉ
ꢃꢊꢋ
ꢈꢈ
channel 1 to be the lowest output voltage that is greater
ꢁꢉꢐꢂ0ꢉ
ꢈ
ꢒꢓꢇ
–
than 3.2V. When the SENSE1 pin (connected to V
)
OUT1
ꢀꢁꢂꢀ ꢃ0ꢄꢅ
is above 3.2V, it biases some internal circuitry instead of
VBIAS, thereby increasing light load Burst Mode efficiency.
Similarly, connect EXTVCC to the lowest output voltage
that is greater than the 4.7V EXTV rising switch-over
threshold. EXTVCC then supplies tChCe high current gate
drivers and relieves additional quiescent current from
5b. Setting Boost to Fixed 8V/10V Output
Figure 5. Setting Boost Output Voltage
RUN pins below 0.7V disables the controllers and most
internal circuits, including the INTV LDOs. In this state,
V
, further reducing the V
pin current to ≈1μA in
CC
BIAS
BIAS
the LTC7817 draws only ≈1.5μA of quiescent current.
sleep.
The RUN pins are high impedance and must be externally
pulled up/down or driven directly by logic. Each RUN pin
can tolerate up to 40V (absolute maximum), so it can
be conveniently tied to VBIAS in always-on applications
where the controller is enabled continuously and never
shut down. Do not float the RUN pins.
Setting Boost Output Voltage (VPRG3 Pin)
The VPRG3 pin selects whether the boost controller out-
put voltage is set by an external feedback resistor divider
or programmed to a fixed 8V or 10V output. Floating
VPRG3 allows the boost output voltage to be set by an
external feedback resistor divider as shown in Figure 5a.
The regulated output voltage is then determined by:
The RUN pins can also be configured as precise under-
voltage lockouts (UVLOs) on a supply such as V
OUT3
or
BIAS
�
�
÷
�
R
R
V
with a resistor divider from the supply to ground.
B
A
V
= 1.195V 1+
�
OUT,BOOST
For example, a simple resistor divider can be used as
�
shown in Figure 6 to satisfy a V
UVLO requirement.
BIAS
Tying the VPRG3 to GND or INTV configures the boost
CC
controller for a fixed output voltage of 8V or 10V, respec-
ꢍ
ꢎꢏꢐꢑ
tively. As shown in Figure 5b, directly connect V to the
FB3
ꢂꢅꢆ ꢇꢈꢉꢀꢁꢂꢀ
Rꢊꢋ
Rꢂ
output when configured for a fixed output voltage.
Rꢌ
RUN Pins and Undervoltage Lockout
ꢀꢁꢂꢀ ꢃ0ꢄ
The three channels of the LTC7817 are enabled using the
RUN1, RUN2, and RUN3 pins. The RUN pins have a ris-
ing threshold of 1.2V with 100mV of hysteresis. Pulling
a RUN pin below 1.1V shuts down the main control loop
and resets the soft-start for that channel. Pulling all three
Figure 6. Using the RUN Pins as a UVLO
Rev 0
27
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as shown in Figure 8. During start-up V
will track V
X
The V
UVLO thresholds can be computed as:
OUT
BIAS
according to the ratio set by the resistor divider:
�
�
÷
�
R1
R2
UVLO Rising = 1.2V 1+
�
V
R
R
+R
TRACKA
�
�
X
A
TRACKB
R +R
A B
=
•
V
R
OUT
TRACKA
�
R1
R2
UVLO Falling = 1.1V 1+
�
÷
�
�
Set R
= R and R
X
= R for coincident track-
TRACKA
A
TRACKB B
ing (V
= V during start-up).
OUT
The current that flows through the R1-R2 divider directly
adds to the shutdown, sleep, and active current of the
LTC7817, and care should be taken to minimize the impact
of this current on the overall efficiency of the application
circuit. Resistor values in the MΩ range may be required
to keep the impact on quiescent shutdown and sleep cur-
rents low.
ꢅ
ꢅ
ꢆꢇꢈꢉꢊꢋꢌRꢍ
ꢎꢏꢋꢇꢊꢐꢉꢅꢌꢍ
Soft-Start and Tracking (TRACK/SS1, TRACK/SS2, SS3
Pins)
ꢀꢁꢂꢀ ꢃ0ꢀꢄ
ꢋꢒꢈꢌ
The start-up of each V
is controlled by the voltage on
OUT
7a. Coincident Tracking
the TRACK/SS pin (TRACK/SS1 for channel 1, TRACK/
SS2 for channel 2, SS3 for channel 3). When the voltage
on the TRACK/SS pin is less than the internal 0.8V refer-
ence (1.2V reference for the boost channel), the LTC7817
regulates the V pin voltage to the voltage on the TRACK/
SS pin insteadFBof the internal reference. The TRACK/SS
pin can be used to program an external soft-start function
ꢅ
ꢅ
ꢆꢇꢈꢉꢊꢋꢌRꢍ
ꢎꢏꢋꢇꢊꢐꢉꢅꢌꢍ
or to allow V
to track another supply during start-up.
OUT
ꢀꢁꢂꢀ ꢃ0ꢀꢄ
ꢋꢒꢈꢌ
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground. An internal 12.5μA
current source charges the capacitor, providing a linear
ramping voltage at the TRACK/SS pin. The LTC7817 will
7b. Ratiometric Tracking
Figure 7. Two Different Modes of Output Voltage Tracking
regulate its feedback voltage (and hence V ) according
OUT
to the voltage on the TRACK/SS pin, allowing V
to rise
ꢇ
OUT
ꢏꢐꢅ
smoothly from 0V to its final regulated value. For a desired
soft-start time, tSS, select a soft-start capacitor CSS
=
R
R
ꢈ
ꢉ
t • 15μF/sec for the buck channels and C = t • 10μF/
ꢇ
SS
SS SS
ꢃꢈ
sec for the boost channel.
ꢇ
ꢑ
ꢄꢅꢆꢀꢁꢂꢀ
Alternatively, the TRACK/SS1 and TRACK/SS2 pins can
be used to track two or more supplies during start-up,
as shown qualitatively in Figures 7a and 7b. To do this, a
resistor divider should be connected from the master sup-
R
R
ꢅRꢉꢆꢊꢈ
ꢅRꢉꢆꢊꢉ
ꢅRꢉꢆꢊꢋꢌꢌꢂꢍꢎ
ply (V ) to the TRACK/SS pin of the slave supply (V ),
X
OUT
ꢀꢁꢂꢀ ꢃ0ꢁ
Figure 8. Using the TRACK/SS Pin for Tracking
Rev 0
28
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LTC7817
APPLICATIONS INFORMATION
Single Output Two-Phase Operation
is limited to less than 44mA from a 36V supply when not
using the EXTV supply at a 70°C ambient temperature:
CC
For high power applications, the two buck channels can
be operated in a two-phase single output configuration.
The buck channels switch 180° out-of-phase, which
reduces the required output capacitance in addition to
the required input capacitance and power supply induced
noise. To configure the LTC7817 for two-phase operation,
T = 70°C + (44mA)(36V)(34.7°C/W) = 125°C
J
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked
while operating in continuous conduction mode (PLLIN/
MODE = INTV ) at maximum V
.
CC
BIAS
tie V to INTV , ITH2 to ground, and RUN2 to RUN1.
FB2
CC
When the voltage applied to EXTVCC rises above 4.7V, the
The RUN1, VFB1, ITH1, TRACK/SS1 pins are then used
to control both buck channels, but each channel uses its
own ICMP and IR comparators to monitor their respec-
tive inductor currents. Figure 11 is a typical application
configured for single output two-phase operation.
V
LDO is turned off and the EXTV LDO is enabled.
BIAS
CC
The EXTVCC LDO remains on as long as the voltage applied
to EXTV remains above 4.5V. The EXTV LDO attempts
to regulCaCte the INTV voltage to 5.1V, so while EXTV
CC
CC
CC
CC
CC
is less than 5.1V, the LDO is in dropout and the INTV
INTV Regulators
voltage is approximately equal to EXTV . When EXTV
CC
CC
is greater than 5.1V (up to an absolute maximum of 30V),
The LTC7817 features two separate internal low dropout
linear regulators (LDOs) that supply power at the INTV
INTV is regulated to 5.1V.
CC
CC
pin from either the V
pin or the EXTV pin depending
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from one of the LTC7817’s
BIAS
CC
on the EXTV pin voltage. INTV powers the MOSFET
CC
CC
gate drivers and most of the internal circuitry. The V
switching regulator outputs (4.7V ≤ V
≤ 30V) during
BIAS
OUT
LDO and the EXTV LDO each regulate INTV to 5.1V
normal operation and from the V
LDO when the output
CC
CC
BIAS
and can provide a peak current of at least 100mA.
is out of regulation (e.g., start-up, short-circuit). If more
current is required through the EXTVCC LDO than is speci-
fied, an external Schottky diode can be added between the
The INTVCC pin must be bypassed to ground with a
minimum of 4.7μF ceramic capacitor, placed as close as
possible to the pin. An additional 1μF ceramic capacitor
EXTV and INTV pins. In this case, do not apply more
CC
CC
than 6V to the EXTV pin.
CC
placed directly adjacent to the INTV and GND pins is
CC
also highly recommended to supply the high frequency
Significant efficiency and thermal gains can be realized by
transient currents required by the MOSFET gate drivers.
powering INTV from a buck output, since the V cur-
CC
IN
rent resulting from the driver and control currents will be
scaled by a factor of VOUT/(VIN • Efficiency). For 5V to 30V
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC7817 to be
exceeded. The INTV current, which is dominated by the
regulator outputs, this means connecting the EXTV pin
CC
directly to V . Tying the EXTV pin to an 8.5V supply
OUT
CC
gate charge currentC, Cmay be supplied by either the V
reduces the junction temperature in the previous example
BIAS
from 125°C to:
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
pin is less than 4.7V, the V
LDO is enabled. Power dis-
T = 70°C + (44mA)(8.5V)(34.7°C/W) = 83°C
J
BIAS
sipation for the IC in this case is equal to V
• I
.
BIAS INTVCC
However, for 3.3V and other low voltage outputs, addi-
The gate charge current is dependent on operating fre-
quency as discussed in the Efficiency Considerations
section. The junction temperature can be estimated by
using the equations given in Note 2 of the Electrical
Characteristics. For example, the LTC7817 INTVCC current
tional circuitry is required to derive INTV power from
CC
the output.
Rev 0
29
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LTC7817
APPLICATIONS INFORMATION
The following list summarizes the four possible connec-
100 times that of the total input capacitance of the topside
MOSFET(s). For a typical application, a value of CB = 0.1μF
is generally sufficient.
tions for EXTV :
CC
1. EXTV grounded. This will cause INTV to be pow-
CC
CC
ered from the internal V
LDO resulting in an effi-
The external diode DB can be a Schottky diode or sili-
con diode, but in either case it should have low leakage
and fast recovery. The reverse breakdown of the diode
ciency penalty of up toB1IA0S% or more at high input
voltages.
must be greater than V . Pay close attention to the
IN(MAX)
2. EXTV connected directly to one of the buck regu-
lator CoCutputs. This is the normal connection for an
application with an output in the range of 5V to 30V
and provides the highest efficiency. If both buck out-
reverse leakage at high temperatures where it generally
increases substantially.
A leaky diode not only increases the quiescent current
of the buck converter, but it can create current path from
puts are in the 5V to 30V range, connect EXTV to
the lesser of the two outputs to maximize efficiency.
CC
the BOOST pin to INTV . This will cause INTV to rise
CC CC
if the diode leakage exceeds the current consumption on
INTV , which is primarily a concern in Burst Mode opera-
3. EXTVCC connected to an external supply. If an external
CC
supply is available, it may be used to power EXTV
CC
tion where the load on INTV can be very small. There
CC
provided that it is compatible with the MOSFET gate
drive requirements. This supply may be higher or
lower than VBIAS; however, a lower EXTVCC voltage
results in higher efficiency.
is an internal voltage clamp on INTV that prevents the
CC
INTV voltage from running away, but this clamp should
be reCgCarded as a failsafe only.
The topside MOSFET driver for the boost channel includes
4. EXTVCC connected to an output-derived boost or
charge pump. For regulators where both of the buck
channel outputs are below 5V, efficiency gains can still
be realized by connecting EXTVCC to an output-derived
voltage that has been boosted to greater than 5.1V.
an internal charge pump that delivers current to the boot
-
strap capacitor from the BOOST3 pin. This charge cur-
rent maintains the bias voltage required to keep the top
MOSFET on continuously during dropout/overvoltage
conditions. Curves displaying the available charge pump
current under different operating conditions can be found
in the Typical Performance Characteristics section.
Topside MOSFET Driver Supply (C , D )
B
B
External bootstrap capacitors CB connected to the
BOOST pins supply the gate drive voltages for the top-
Minimum On-Time Considerations
side MOSFETs. Capacitor C in the Functional Diagram is
B
Minimum on-time tON(MIN) is the smallest time dura-
tion that the LTC7817 is capable of turning on the top
MOSFET (or bottom MOSFET for the boost controller).
It is determined by internal timing delays and the gate
charge required to turn on the MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that:
charged though external diode D from INTV when the
B
CC
SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the C voltage across the gate-source of the
B
desired MOSFET. This enhances the MOSFET and turns
on the topside switch. The switch node voltage, SW, rises
to V for the buck channels (V
for the boost channel)
OUT
IN
V
OUT
and the BOOST pin follows. With the topside MOSFET on,
t
t
<
ON(MIN)_BUCK
V • f
IN
the boost voltage is above the input supply: V
= V
OUT
BOOST
IN
+
+ V
INTVCC
(or for the boost controller, V
= V
V
� V
IN
• f
INTVCC
BOOST
OUT
<
ON(MIN)_BOOST
V
). The value of the boost capacitor C needs to be
B
V
OUT
Rev 0
30
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LTC7817
APPLICATIONS INFORMATION
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase. The mini-
mum on-time for the LTC7817 is approximately 40ns for
the bucks and 80ns for the boost. However, as the peak
sense voltage decreases the minimum on-time for the
bucks gradually increases up to about 60ns. This is of par-
ticular concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
If a buck output voltage rises 10% above the set regula-
tion point, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously
for as long as the overvoltage condition persists; if V
returns to a safe level, normal operation automaticOalUlyT
resumes.
A shorted top MOSFET will result in a high current con-
dition which will open the system fuse. The switching
regulator will regulate properly with a leaky top MOSFET
by altering the duty cycle to accommodate the leakage.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self-heating (such as
a short from INTV to ground) internal overtemperature
shutdown circuitrCyCwill shut down the LTC7817. When
Fault Conditions: Buck Current Limit and Foldback
The LTC7817 includes current foldback for the buck chan-
nels to reduce the load current when the output is shorted
to ground. If the output voltage falls below 50% of its
regulation point, then the maximum sense voltage is pro-
gressively lowered from 100% to 40% of its maximum
value. Under short-circuit conditions with very low duty
cycles, the LTC7817 will begin cycle skipping to limit the
short circuit current. In this situation the bottom MOSFET
dissipates most of the power but less than in normal oper-
ation. The short-circuit ripple current is determined by the
the internal die temperature exceeds 180°C, the INTV
CC
LDO and gate drivers are disabled. When the die cools
to 160°C, the LTC7817 enables the INTVCC LDO and
resumes operation beginning with a soft-start startup.
Long-term overstress (TJ > 125°C) should be avoided
as it can degrade the performance or shorten the life of
the part.
minimum on-time, t
inductor value:
≈ 40ns, the input voltage and
ON(MIN)
Phase-Locked Loop and Frequency Synchronization
The LTC7817 has an internal phase-locked loop (PLL)
which allows the turn-on of the top MOSFET of control-
ler 1 to be synchronized to the rising edge of an external
clock signal applied to the PLLIN/MODE pin. The turn on
of controller 2’s top MOSFET is thus 180° out of phase
with the external clock.
ΔI
L(SC)
= t
• V /L
ON(MIN) IN
The resulting average short-circuit current is:
= 40% • I − ΔI /2
I
SC
LIM(MAX)
L(SC)
Fault Conditions: Buck Overvoltage Protection
(Crowbar)
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. Before synchronization,
the PLL is prebiased to the frequency set by the FREQ
pin. Consequently, the PLL only needs to make minor
adjustments to achieve phase-lock and synchronization.
Although it is not required that the free-running frequency
be near the external clock frequency, doing so will pre-
vent the oscillator from passing through a large range of
frequencies as the PLL locks.
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the con-
troller is operating.
Rev 0
31
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LTC7817
APPLICATIONS INFORMATION
When synchronized to an external clock, the LTC7817
operates in forced continuous mode. The LTC7817 is
guaranteed to synchronize to an external clock applied to
the PLLIN/MODE pin that swings up to at least 2.5V and
down to 0.5V or less. Note that the LTC7817 can only be
synchronized to an external clock frequency within the
range of 100kHz to 3MHz.
Supplying INTVCC from an output-derived source
power through EXTVCC will scale the VIN current
required for the driver and control circuits by a fac-
tor of V /(V • Efficiency). For example, in a 20V
OUT IN
to 5V application, 10mA of INTV current results in
CC
approximately 2.5mA of VIN current. This reduces the
mid-current loss from 10% or more (if the driver was
powered directly from V ) to only a few percent.
IN
Efficiency Considerations
2
3. I R losses are predicted from the DC resistances of
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
the input fuse (if used), MOSFET, inductor, current
sense resistor, and input and output capacitor ESR.
In continuous mode the average output current flows
through L and R
, but is “chopped” between the
SENSE
top and bottom MOSFETs. If the two MOSFETs have
approximately the same R
, then the resistance
DS(ON)
of one MOSFET can simply be summed with the resis-
%Efficiency = 100% – (L1 + L2 + L3 + ...)
2
tances of L, R
and ESR to obtain I R losses.
SENSE
where L1, L2, etc. are the individual losses as a percent-
age of input power.
For example, if each R
= 30mΩ, R = 50mΩ,
L
DS(ON)
RSENSE = 10mΩ and ESR = 40mΩ (sum of both input
and output capacitance losses), then the total resis-
tance is 130mΩ. This results in losses ranging from
3% to 13% as the output current increases from 1A
to 5A for a 5V output, or a 4% to 20% loss for a
3.3V output. This loss varies as the inverse square
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC7817 circuits: 1) IC V
current, 2) INTV
BIAS
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET tran-
sition losses.
of V
for the same external components and out-
1. The V
current is the DC supply current given in
OUT
the ElBeIcAtSrical Characteristics table, which excludes
MOSFET driver and control currents. Other than at
put power level. The combined effects of increasingly
lower output voltages and higher currents required
by high performance digital systems is not doubling
but quadrupling the importance of loss terms in the
switching regulator system!
very light loads in burst mode, V
results in a small (<0.1%) loss. BIAS
current typically
2. INTV current is the sum of the MOSFET driver and
CC
4. Transition losses apply only to the top MOSFETs
for the bucks (bottom MOSFET for the boost), and
become significant only when operating at higher
input voltages (typically 15V or greater). Transition
losses can be estimated from the equation for the
main switch power dissipation in the Power MOSFET
Selection section.
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge,
dQ, moves from INTV to ground. The resulting dQ/
dt is a current out ofCICNTV that is typically much
CC
larger than the control circuit current. In continuous
mode, I
= f (Q + Q ), where Q and Q are
GATECHG
SW T B T B
the gate charges of the top and bottom MOSFETs.
Rev 0
32
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LTC7817
APPLICATIONS INFORMATION
The ITH series R -C filter sets the dominant pole-zero
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
C
C
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their initial values) to optimize tran-
sient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
losses can be minimized by making sure that C has ade-
IN
quate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum
of 20μF to 40μF of capacitance having a maximum of
20mΩ to 50mΩ of ESR. The LTC7817 2-phase architec-
ture typically halves this input capacitance requirement
over competing solutions. Other losses including induc-
tor core losses generally account for less than 2% total
additional loss.
Placing a power MOSFET directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better to
look at the ITH pin signal which is in the feedback loop and
is the filtered and compensated control loop response.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
shifts by an
OUT
amount equal to ΔILOAD • (ESR), where ESR is the effective
series resistance of C . ΔI
also begins to charge or
OUT
generating tLhOeAfDeedback error signal that
The gain of the loop will be increased by increasing RC and
the bandwidth of the loop will be increased by decreas-
discharge C
OUT
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
ing C . If RC is increased by the same factor that C is
C
decreCased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over-
all supply performance.
time V
can be monitored for excessive overshoot or
OUT
ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capaci-
tance and ESR values. The availability of the ITH pin not
only allows optimization of control loop behavior, but it
also provides a DC coupled and AC filtered closed loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The ITH external components shown in the Typical
Application circuits provide an adequate starting point for
most applications.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C , causing a rapid drop in V . No regulator can
OUT
alter itOsUdTelivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
should be controlled so that the load rise time is limited
to approximately C • 25μs/μF. Thus a 10μF capacitor
LOAD
would require a 250μs rise time, limiting the charging
current to about 200mA.
Rev 0
33
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LTC7817
APPLICATIONS INFORMATION
Buck Design Example
To allow for additional margin, a lower value R
SENSE
may be used (for example, 1.8mΩ); however, be
As a design example for one of the buck channels,
sure that the inductor saturation current has suffi-
assume V
OUT
= 12V, V
= 22V, V
= 3.3V,
IN(NOMINAL)
IN(MAX)
OUT
cient margin above V
/R
, where the
SENSE(MAX)
SENSE(MAX) SENSE
maximum value of 55mV is used for V
I
= 20A, and f = 1MHz.
SW
.
1. Set the operating frequency. The frequency is not one
of the internal preset values, so a resistor from the
FREQ pin to GND is required, with a value of:
For this low inductor value and high current applica-
tion, an RC filter into the sense pins should be used
to compensate for the parasitic inductance (ESL) of
the sense resistor. Assuming an RSENSE geometry of
1225 with a parasitic inductance of 0.2nH, the RC filter
37MHz
R
(in k� )=
= 37k�
FREQ
1MHz
time constant should be R = ESL/R
= 0.2nH /
C
SENSE
2. Determine the inductor value. Initially select a value
based on an inductor ripple current of 30%. The
inductor value can then be calculated from the fol-
lowing equation:
2mΩ = 100ns, which may be implemented with 100Ω
resistor in series with the SENSE+ pin and 1nF capaci-
+
−
tor between SENSE and SENSE .
5. Select the feedback resistors. If very light load effi-
ciency is required, high value feedback resistors may
be used to minimize the current due to the feedback
divider. However, in most applications a feedback
divider current in the range of 10μA to 100μA or more
is acceptable. For a 50μA feedback divider current,
�
�
V
V
OUT
V
IN(NOM)
OUT
�
1–
÷
L =
= 0.4µH
�
�
÷
f
� I
(
)
L
SW
�
The highest value of ripple current occurs at the maxi-
mum input voltage. In this case the ripple at V = 22V
IN
is 35%
R = 0.8V/50μA = 16kΩ. R can then be calculated
A
B
3. Verify that the minimum on-time of 40ns is not vio-
as R = R (3.3V/0.8V – 1) = 50kΩ.
B
A
lated. The minimum on-time occurs at V
:
IN(MAX)
6. Select the MOSFETs. The best way to evaluate
MOSFET performance in a particular application is
to build and test the circuit on the bench, facilitated
by an LTC7817 demo board. However, an educated
guess about the application is helpful to initially select
MOSFETs. Since this is a high current, low voltage
V
OUT
t
=
= 150ns
ON(MIN)
V
(f
)
IN(MAX)
SW
This is more than sufficient to satisfy the minimum
on time requirement. If the minimum on time is vio-
lated, the LTC7817 skips pulses at high input volt-
age, resulting in lower frequency operation and higher
inductor current ripple than desired. If undesirable,
this behavior can be avoided by decreasing the fre-
quency (with the inductor value accordingly adjusted)
to avoid operation near the minimum on-time.
2
application, I R losses will likely dominate over tran-
sition losses for the top MOSFET. Therefore, choose
a MOSFET with lower R
as opposed to lower
DS(ON)
gate charge to minimize the combined loss terms.
The bottom MOSFET does not experience transition
losses, and its power loss is generally dominated by
I2R losses. For this reason, the bottom MOSFET is
4. Select the R
resistor value. The peak inductor
SENSE
current is the maximum DC output current plus half of
the inductor ripple current. Or 20A • (1+0.30/2) = 23A
typically chosen to be of lower R
and subse-
DS(ON)
quently higher gate charge than the top MOSFET.
in this case. The R
resistor value can then be
SENSE
Due to the high current in this application, two
MOSFETs may needed in parallel to more evenly bal-
calculated based on the minimum value for the maxi-
mum current sense threshold (45mV):
ance the dissipated power and to lower the R
.
DS(ON)
45mV
Be sure to select logic-level threshold MOSFETs, since
the gate drive voltage is limited to 5.1V (INTV ).
R
�
� 2m�
SENSE
23A
CC
Rev 0
34
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APPLICATIONS INFORMATION
7. Select the input and output capacitors. C is chosen
1. Are the top N-channel MOSFETs located within 1cm of
IN
for an RMS current rating of at least 10A (I /2, with
each other with a common drain connection at C ?
OUT
IN
margin) at temperature assuming only this channel is
Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
on. C
is chosen with an ESR of 3mΩ for low out-
OUT
put ripple. Multiple capacitors connected in parallel
may be required to reduce the ESR to this level. The
output ripple in continuous mode will be highest at
the maximum input voltage. The output voltage ripple
due to ESR is approximately:
2. Are the signal and power grounds kept separate? The
combined IC ground pin and the ground return of
C
must return to the combined C
(–) termi-
INTVCC
OUT
nals. The path formed by the top N-channel MOSFET
and the C capacitor should have short leads and
IN
V
= ESR • ΔI = 3mΩ • 6A = 18mV
P-P
PC trace lengths. The output capacitor (–) terminals
should be connected as close as possible to the
(–) terminals of the input capacitor by placing the
capacitors next to each other and away from the loop
described above.
ORIPPLE
L
On the 3.3V output, this is equal to 0.55% of peak to
peak voltage ripple.
8. Determine the bias supply components. Since the
regulated output is not greater than the EXTV swi-
tchover threshold (4.7V), it cannot be used CtoC bias
3. Do the LTC7817 V pins’ resistive dividers connect
to the (+) terminaFlsB of C ? The resistive divider
OUT
INTV . However, if another supply is available, for
CC
must be connected between the (+) terminal of C
OUT
example if the other buck channel is regulating to
5V, connect that supply to EXTVCC to improve the
efficiency. For an 6.5ms soft start, select a 0.1μF
capacitor for the TRACK/SS pin. As a first pass esti-
and signal ground. Place the divider close to the V
pin to minimize noise coupling into the sensitive V
FB
FB
node. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
mate for the bias components, select C
= 4.7μF,
INTVCC
boost supply capacitor C = 0.1μF and low forward
B
–
+
drop boost supply diode CMDSH-4E from Central
Semiconductor.
4. Are the SENSE and SENSE leads routed together
with minimum PC trace spacing? Route these traces
away from the high frequency switching nodes, on
an inner layer if possible. The filter capacitor between
9. Determine and set application-specific parameters.
Set the PLLIN/MODE pin based on the trade-off of
light load efficiency and constant frequency opera-
tion. The RUN pin can be used to control the mini-
mum input voltage for regulator operation or can be
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
tied to V for always-on operation. Use ITH compen-
5. Is the INTV decoupling capacitor connected close
CC
IN
sation components from the typical applications as a
first guess, check the transient response for stability,
and modify as necessary.
to the IC, between the INTV and the power ground
CC
pin? This capacitor carries the MOSFET drivers’
current peaks. An additional 1μF ceramic capacitor
placed immediately next to the INTV and GND pins
CC
PC Board Layout Checklist
can help improve noise performance substantially.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. Figure 9 illustrates the current waveforms present
in the various branches of the 2-phase synchronous buck
regulators operating in the continuous mode. Check the
following in your layout:
6. Keep the switching nodes (SW1, SW2, SW3), top gate
nodes (TG1, TG2, TG3), and boost nodes (BOOST1,
BOOST2, BOOST3) away from sensitive small-signal
nodes, especially from the other channel’s voltage
and current sensing feedback pins. All of these nodes
have very large and fast-moving signals and therefore
Rev 0
35
For more information www.analog.com
LTC7817
APPLICATIONS INFORMATION
should be kept on the output side of the LTC7817 and
occupy minimum PC trace area. Minimize the induc-
tance of the TG and BG gate drive traces and their
respective return paths to the controller IC (SW and
GND) by using wide traces and multiple parallel vias.
comparator trip point when the other channel is turning
on its top MOSFET. This occurs around 50% duty cycle
on either channel due to the phasing of the internal clocks
and may cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation. Investigate
whether any problems exist only at higher output cur-
rents or only at higher input voltages. If problems coincide
with high input voltages and low output currents, look for
capacitive coupling between the BOOST, SW, TG, and pos-
sibly BG connections and the sensitive voltage and current
pins. The capacitor placed across the current sensing pins
needs to be placed immediately adjacent to the pins of
the IC. This capacitor helps to minimize the effects of dif-
ferential noise injection due to high frequency capacitive
coupling. If problems are encountered with high current
output loading at lower input voltages, look for inductive
7. Use a modified star ground technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decoupling capacitor, the bottom of the voltage feed-
back resistive divider and the GND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age as well. Check for proper performance over the oper-
ating voltage and current range expected in the applica-
tion. The frequency of operation should be maintained
over the input voltage range down to dropout and until
the output load drops below the low current operation
threshold—typically 25% of the maximum designed cur-
rent level in Burst Mode operation.
coupling between C , the top MOSFET, and the bottom
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop
will be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or volt-
age sensing inputs or inadequate loop compensation.
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is not
required. Only after each controller is checked for its indi-
vidual performance should both controllers be turned on
at the same time. A particularly difficult region of opera-
tion is when one controller channel is nearing its current
Rev 0
36
For more information www.analog.com
LTC7817
APPLICATIONS INFORMATION
ꢂꢃꢁ
ꢀꢁ
R
ꢂꢄꢅꢂꢄꢁ
ꢆ
ꢇꢈꢉꢁ
ꢊ
ꢇꢈꢉꢁ
R
ꢀꢁ
ꢆ
ꢋꢅ
R
ꢋꢅ
ꢊ
ꢋꢅ
ꢂꢃꢌ
ꢀꢌ
R
ꢂꢄꢅꢂꢄꢌ
ꢆ
ꢇꢈꢉꢌ
ꢊ
ꢇꢈꢉꢌ
R
ꢀꢌ
ꢍꢇꢀꢎ ꢀꢋꢅꢄꢂ ꢋꢅꢎꢋꢊꢏꢉꢄ
ꢐꢋꢑꢐ ꢂꢃꢋꢉꢊꢐꢋꢅꢑ
ꢊꢈRRꢄꢅꢉꢒ ꢓꢄꢄꢔ ꢀꢋꢅꢄꢂ
ꢉꢇ ꢏ ꢕꢋꢅꢋꢕꢈꢕ ꢀꢄꢅꢑꢉꢐꢒ
ꢖꢗꢁꢖ ꢘ0ꢙ
Figure 9. Branch Current Waveforms for Bucks
Rev 0
37
For more information www.analog.com
LTC7817
TYPICAL APPLICATIONS
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀ0ꢁ ꢂꢃꢄꢅ ꢁ ꢇꢀ0ꢁ
ꢀꢀ
ꢀꢁ
ꢆꢅ
ꢀ
ꢀꢁꢂꢂꢁꢃꢄ ꢅ ꢀꢁꢂꢃ ꢄ ꢆꢇ0ꢄ
ꢀ
ꢀꢁꢂꢃ
Rꢀꢁꢂ Rꢀꢁꢂ Rꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢅꢃ
ꢀꢁ
ꢀꢁ0ꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁ
2mΩ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
1.5mΩ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢀꢂꢃꢄꢅꢆ
0ꢀꢁꢂꢃ
0ꢀꢁꢂꢃ
ꢀꢁ ꢂꢃ ꢄꢅꢁꢆ
ꢀ
ꢀꢁꢂꢃ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀꢁꢂꢃ ꢄꢅꢆRꢅꢇꢈꢉꢊ
20Ω
ꢀꢁꢂ
ꢀꢀ0ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀ00ꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢃ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁ0ꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁRꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄ
3mΩ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ0ꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀꢀ0ꢁꢂ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀRꢁꢂ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢀꢁ
ꢀꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ00ꢁꢂ
ꢀ00ꢁꢂ
ꢀꢀ0ꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀꢁꢂ
0ꢀꢁꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢁꢀꢂꢃ
0ꢀꢁꢂꢃ
0ꢀꢁꢂꢃ
0
ꢀꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢏꢐꢉ0ꢑꢒꢍꢓ
ꢀꢌꢂꢁꢄꢅꢆꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢆꢆꢉ0ꢑꢒꢍꢓ
ꢀꢁꢂꢃꢔꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢆꢆꢉ0ꢑꢒꢍꢓ
ꢀꢌꢂꢁꢔꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢏꢐꢉ0ꢑꢒꢍꢓ
ꢒꢄꢇ ꢕꢖRꢁꢗ ꢘꢑꢑꢔꢏꢏ0ꢐ0
ꢀꢁꢂꢃꢂꢄꢅ ꢆꢇꢈꢉRꢊꢋ ꢌꢇꢍꢎ ꢆꢍꢀꢌꢏꢐꢑꢇ
ꢀ
ꢀ ꢁꢂ0ꢃꢄꢅ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄꢅꢃ ꢆꢇꢄꢈꢉ00ꢊꢋ
ꢀꢁ
ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ
ꢇ ꢈꢉꢊꢉꢃ ꢃꢋꢆ0ꢌꢍꢍꢎꢊ00ꢏꢐꢃꢉ0ꢄꢋ ꢀ ꢁꢂꢃꢄ ꢅ ꢀ ꢁꢂꢃ ꢄꢅꢆꢇꢄꢈꢄ ꢉꢊꢅꢋ ꢌꢈRRꢍꢎꢏ ꢅꢂꢅꢇꢉꢅꢐꢉꢍ ꢇꢑ Rꢍꢋꢈꢌꢍꢋ
ꢀꢁ
ꢀ ꢁꢂꢃꢄꢅꢃ ꢆ0ꢇꢈꢉꢊꢋꢆ0ꢌ
ꢀ ꢁꢂꢃꢄꢂꢃ ꢅꢂRRꢆꢇꢃ ꢅꢈꢄꢈꢉꢊꢋꢊꢃꢌ ꢈꢃ ꢍꢊꢎꢍ ꢊꢇꢄꢂꢃ ꢏꢁꢋꢃꢈꢎꢆꢐ ꢑꢈꢌ ꢉꢆ ꢋꢊꢑꢊꢃꢆꢒ ꢉꢌ ꢃꢍꢆ ꢃꢍꢆRꢑꢈꢋ
ꢀꢁꢂRꢂꢀꢃꢄRꢅꢆꢃꢅꢀꢆ ꢇꢈ ꢃꢁꢄ ꢇꢉꢄRꢂꢊꢊ ꢆꢋꢆꢃꢄꢌ ꢂꢍꢎ ꢏRꢅꢍꢃꢄꢎ ꢀꢅRꢀꢐꢅꢃ ꢑꢇꢂRꢎ ꢎꢄꢆꢅꢒꢍ
ꢒꢆꢇ ꢕꢖRꢁꢗ ꢘꢑꢑꢔꢄꢔꢄꢙ0
ꢒꢔꢇ ꢕꢖRꢁꢗ ꢘꢑꢑꢔꢏꢏ0ꢄꢑ0
(10a)
No-Load Burst Mode Input
Current vs Input Voltage
Efficiency vs Load Current
Short-Circuit Response
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢁ ꢂꢃRꢄꢄ ꢅꢃꢀꢆꢆꢄꢁꢇ ꢈꢆ
ꢀꢁꢂꢃ ꢄꢅꢆꢁꢁeꢂ ꢇ ꢀꢁ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢁ ꢂꢃꢄꢅꢅeꢁꢆ ꢇꢅ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆR
ꢀꢁRRꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
0ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ ꢃꢂ0ꢄ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁ
ꢀꢁꢂꢀ ꢃꢂ0ꢄ
ꢀꢁꢂꢀ ꢃꢂ0ꢄ
(10b)
(10c)
(10d)
Figure 10. High Efficiency Wide Input Range Dual 5V/3.3V Regulator
Rev 0
38
For more information www.analog.com
LTC7817
TYPICAL APPLICATIONS
ꢀ
ꢀꢁ
ꢀꢁꢂ ꢃꢄꢅꢆꢃꢇꢈ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃꢄꢅꢆꢃ
ꢀ
Rꢀꢁꢂ Rꢀꢁꢂ Rꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ00ꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
4mΩ
ꢄ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢀꢁꢃ
2mΩ
0ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
0ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢃ
ꢀꢁꢂꢃꢀꢄ
ꢄ
ꢀ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ0ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂ
ꢀ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢀ
ꢀꢀ0ꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁRꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂ
0ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀRꢁꢂ
2mΩ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢁꢂꢃ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢁꢂꢃ
ꢀꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀ00ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
0ꢀꢁꢂꢃ
0ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢀ ꢃꢄ0ꢅ
ꢀꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢏꢐꢉ0ꢑꢒꢍꢓ
ꢀꢌꢂꢁꢄꢅꢆꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢆꢆꢉ0ꢑꢒꢍꢓ
ꢀꢁꢂꢃꢔꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢏꢐꢉ0ꢑꢒꢍꢓ
ꢀꢌꢂꢁꢔꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢏꢐꢉ0ꢑꢒꢍꢓ
ꢒꢄꢅꢆꢇ ꢎꢂꢈꢒꢎRꢕꢊꢁ ꢖꢕꢒꢄꢏꢗ0ꢘꢄ0ꢆꢀꢋ
ꢒꢔꢇ ꢎꢂꢈꢒꢎRꢕꢊꢁ ꢖꢕꢒꢄ0ꢄ0ꢘꢑꢙꢆꢀꢋ
ꢀꢁꢂꢃꢂꢄꢅ ꢆꢇꢈꢉRꢊꢋ ꢌꢇꢍꢎ ꢆꢍꢀꢌꢏꢐꢑꢇ
ꢀ
ꢀꢁꢂ0ꢃꢄꢅ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄꢅꢃ ꢆꢇꢈꢉꢊꢋꢌ00ꢍ
ꢀ
ꢀꢁꢂꢂꢁꢃꢄ ꢅ ꢀꢁꢂꢃ ꢄ ꢆ ꢇꢄ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢀꢁ ꢅꢃ
ꢀ ꢁꢂꢃꢂꢄꢅꢃꢆꢇ ꢈꢉꢁꢊꢋꢋ0ꢌꢍꢎ
ꢀ ꢁꢂꢃꢄꢅꢃ ꢆꢇꢄꢈꢉꢊꢋꢌ
ꢀ
ꢀꢁꢂꢂꢁꢃꢄ ꢅ ꢀꢁꢂꢃ ꢄ ꢆ ꢇꢈꢄ
ꢀꢁꢂꢃ
ꢀꢁ
ꢅꢃ
(11a)
Two-Phase Buck Load Step
Transient Response
Efficiency vs Load Current
Efficiency vs Input Voltage
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁꢂꢃ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀꢁ ꢂꢃꢄꢅꢆꢇꢈR
ꢀꢁRRꢂꢃꢄ
ꢀ0ꢁꢂꢃꢄꢅ
ꢀꢁ ꢂꢃꢄꢅꢆꢇꢈR
ꢀꢁRRꢂꢃꢄ
ꢀ0ꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢀ ꢃꢂꢂꢄ
ꢀꢁꢂꢃꢄ ꢅ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂꢃꢄ ꢅ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄ ꢅ
ꢀꢁ0ꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁ0ꢂ
ꢀꢁ0ꢂ
ꢀ
ꢀ
ꢀꢁ0ꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ0ꢂ
ꢀꢁꢂꢃ
ꢀ0ꢁ ꢂꢃ ꢄ0ꢁ ꢅꢃꢁꢆ ꢇꢂꢈꢉ
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
0ꢀ00ꢁ
0ꢀ0ꢁ
0ꢀꢁ
ꢀ
ꢀ0 ꢀ0
ꢀ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁ
ꢀꢁꢂꢀ ꢃꢂꢂꢄ
ꢀꢁꢂꢀ ꢃꢂꢂꢄ
(11b)
(11c)
(11d)
Figure 11. High Efficiency 380kHz Wide Input Range 24V/2A Boost and Two-Phase 5V/30A Buck Regulator
Rev 0
39
For more information www.analog.com
LTC7817
TYPICAL APPLICATIONS
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ0ꢁ ꢂꢃ ꢄꢅꢁꢆꢆꢆ
ꢀꢀ
ꢀꢁ
ꢀ
ꢀ
Rꢀꢁꢂ Rꢀꢁꢂ Rꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ0ꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
3mΩ
0ꢀꢁꢂꢃ
ꢀ0ꢁ ꢂꢃ ꢀꢄꢁꢅ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂ
ꢀ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢀꢁꢂ
ꢀ00ꢁꢂ
2mΩ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
0ꢀꢁꢂꢃ
ꢀꢁ ꢂꢃ ꢄꢅꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢃ
ꢀꢁꢂꢃ ꢄꢅꢆRꢅꢇꢈꢉꢊ
ꢀ
ꢀꢁ
ꢀꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀ0ꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁRꢂꢃ
ꢀꢁ
ꢀꢁꢀꢂꢃ
6mΩ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁ ꢂ ꢀꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢄꢅ
ꢀRꢁꢂ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀ0ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
ꢀ0ꢁꢂ
0ꢀꢁꢂꢃ
ꢀꢁꢀꢂꢃ
0ꢀꢁꢂꢃ
ꢀꢁꢂꢀ ꢃꢄ0ꢅ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢌ0ꢍꢍꢇ0ꢎꢀꢋ
ꢀꢊꢂꢁꢄꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢌ0ꢍꢍꢇ0ꢎꢀꢋ
ꢀꢁꢂꢃꢏꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢐ0ꢑꢒꢇ0ꢓꢔꢋꢕ
ꢀꢊꢂꢁꢏꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢐ00ꢖꢇ0ꢓꢔꢋꢕ
ꢀꢁꢂꢃꢎꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢐ00ꢖꢇ0ꢓꢔꢋꢕ
ꢀꢊꢂꢁꢎꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢐ0ꢑꢒꢇ0ꢓꢔꢋꢕ
ꢗꢄꢘꢏꢘꢎꢅ ꢐꢉꢇꢁRꢙꢔ ꢋꢉꢀꢆ ꢐꢀꢗꢋꢚꢛꢓꢉ
ꢀ
ꢀ
ꢀ
ꢃ ꢄꢅꢂꢀꢆꢂ ꢇ0ꢈꢉꢈꢊꢊꢋ
ꢀ
ꢀꢁꢂ0ꢃꢄꢅ
ꢀꢁ
ꢁꢂ
ꢀ ꢁ
ꢀ ꢁ0ꢂ ꢃꢄꢅꢆ ꢂ ꢀ ꢁ0ꢂ
ꢀꢁ
ꢃ ꢎꢏꢋꢏꢌ ꢌꢇꢍꢐꢑꢐ0ꢒꢋ0ꢍꢇꢓꢌꢏ0ꢔ0
ꢃ ꢄꢅꢂꢀꢆꢂ ꢇ0ꢈꢉꢕꢖꢐꢇ0ꢋ
ꢀꢁꢂꢃ
ꢀ ꢁꢂꢃ ꢄꢅꢆꢇ ꢃ ꢀ ꢁꢂꢃ
ꢆꢅꢌꢍ
ꢆꢅꢌꢊ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀꢁꢂꢂꢁꢃꢄ ꢅ ꢀꢁꢂꢃ ꢄ ꢅꢆ ꢇ0ꢄ ꢈꢉ ꢇꢊꢄ
ꢀꢁ ꢅꢃ
ꢗꢐꢃ ꢘꢅRꢌꢈ ꢒꢙꢙꢊꢍꢇꢊꢊ0
ꢗꢍꢃ ꢘꢅRꢌꢈ ꢒꢙꢙꢊꢚꢊꢔꢚ0ꢊꢊ
ꢗꢊꢃ ꢘꢅRꢌꢈ ꢒꢙꢙꢊꢊꢍ0ꢐ00
ꢀꢀ ꢁꢂꢃꢄ ꢅ ꢀ ꢁꢂꢃ ꢄꢅꢆꢇꢄꢈꢄ ꢉꢊꢅꢋ ꢌꢈRRꢍꢎꢏ ꢅꢂꢅꢇꢉꢅꢐꢉꢍ ꢇꢑ Rꢍꢋꢈꢌꢍꢋ
ꢀꢁ
ꢀꢀꢀ ꢁ
ꢀ
ꢀ ꢁ0ꢂ ꢃꢄꢅꢆ ꢂ ꢀ ꢁ0ꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢂꢁꢃꢄ ꢅ ꢀꢁꢂꢃ ꢄ ꢆ ꢇ0ꢄ
ꢀꢁ
ꢅꢃ
(12a)
Output Voltage vs Input Voltage
VOUT1 Efficiency vs Input Voltage
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ ꢅꢈꢇRꢉꢃꢊꢅꢋ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁ00ꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
0
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢀ ꢃꢂꢄꢅ
ꢀꢁꢂꢀ ꢃꢂꢄꢅ
(12b)
(12c)
Figure 12. Wide Input Range 10V-16V Pass-Thru Cascaded Regulator and 5V Buck Regulator
Rev 0
40
For more information www.analog.com
LTC7817
TYPICAL APPLICATIONS
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁ
ꢀ
ꢀ0ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ0ꢂꢃ
ꢀ
Rꢀꢁꢂ Rꢀꢁꢂ Rꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀ0ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
3mΩ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢀꢂꢃ
ꢀ0ꢁꢂ
ꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
1.5mΩ
ꢀ
ꢃꢀ ꢇ
ꢁꢂ ꢄꢅꢆꢆ
0ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ ꢃꢄꢅꢆꢃꢇꢈ
ꢀꢁ ꢂꢃ ꢄꢅꢁ
ꢀꢁꢂ
0ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢃ
ꢀ0ꢁꢂ
ꢃꢄ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄꢅꢆRꢅꢇꢈꢉꢊ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁRꢂꢃ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀRꢁꢂ
ꢀꢁ
ꢀꢁꢀꢂꢃ
6mΩ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢀꢂ ꢃ ꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢀꢁꢂ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
0ꢀꢁꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢀꢁꢂ
0ꢀꢁꢂꢃ
0ꢀꢁꢂꢃ
ꢀꢁꢂꢀ ꢃꢄ0ꢅ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢌ0ꢍꢍꢇ0ꢎꢀꢋ
ꢀꢊꢂꢁꢄꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢌ0ꢍꢍꢇ0ꢎꢀꢋ
ꢀꢁꢂꢃꢏꢐꢎꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢑ0ꢒꢓꢇ0ꢔꢕꢋꢖ
ꢀ
ꢀ
ꢀ
ꢃ ꢄꢅꢂꢀꢆꢂ ꢇ0ꢈꢉꢊꢇꢋꢌ
ꢀ
ꢀꢁ00ꢂꢃꢄ
ꢀꢁ
ꢁꢂ
ꢀ ꢁꢂꢃꢄ ꢅ ꢀ ꢁꢂꢃ ꢄꢅꢆꢇꢄꢈꢄ ꢉꢊꢄꢋꢇꢌꢍꢎ ꢏꢊꢅꢎ ꢉꢈRRꢍꢌꢐ ꢅꢂꢅꢇꢏꢅꢋꢏꢍ ꢇꢑ Rꢍꢎꢈꢉꢍꢎ
ꢃ ꢏꢐꢌꢐꢍ ꢍꢇꢎꢑꢒꢓꢔꢋꢌ0ꢑꢋꢕꢍꢐꢓꢇ
ꢆꢅꢍꢎ
ꢃ ꢄꢅꢂꢀꢆꢂ ꢇ0ꢈꢉꢊꢗꢑꢇ0ꢌ
ꢆꢅꢍꢖ
ꢀꢁ
ꢀ ꢁꢂꢃ ꢄꢅꢆꢇ ꢃ ꢀ ꢁꢂꢃ
ꢀꢀ ꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢂꢁꢃꢄ ꢅ ꢀꢁꢂꢃ ꢄ ꢆ ꢇꢈꢄ
ꢀꢊꢂꢁꢏꢐꢎꢅ ꢆꢇꢈꢆꢇꢉꢂꢇ ꢊꢋꢑ0ꢒꢓꢇ0ꢔꢕꢋꢖ ꢘꢑꢃ ꢀꢆꢁꢘꢀRꢕꢗꢍ ꢙꢕꢘꢋ0ꢖ00ꢚꢎꢎꢎꢌꢐ
ꢀꢁꢂꢃ
ꢀꢁ
ꢅꢃ
ꢗꢄꢐꢏꢐꢎꢅ ꢑꢉꢇꢁRꢘꢕ ꢋꢉꢀꢆ ꢑꢀꢗꢋꢙꢚꢔꢉ
ꢘꢎꢃ ꢀꢆꢁꢘꢀRꢕꢗꢍ ꢙꢕꢘꢛ0ꢛ0ꢚꢎꢎꢎꢌꢐ
ꢘꢖꢃ ꢀꢆꢁꢘꢀRꢕꢗꢍ ꢙꢕꢘꢑ0ꢑ0ꢚꢋꢛꢑꢌꢐ
(13a)
V
OUT2 Typical Current Limit
vs VIN Input Voltage
Cold Crank Transient Response
VOUT2 Efficiency vs Load Current
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁꢂ
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ ꢅꢈꢇRꢉꢃꢊꢅꢋ
ꢀꢁꢁ ꢂꢃꢀꢄꢄꢅꢁꢆ ꢇꢄ
ꢀꢁꢁ ꢂꢃꢀꢄꢄꢅꢁꢆ ꢇꢄ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂ ꢃꢂꢄꢅ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀ
0
0ꢀ
ꢀꢁꢂꢀ ꢃꢂꢄꢅ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅ0ꢆꢇꢈꢉꢁꢊꢋ
0ꢀ00ꢁ
0ꢀ0ꢁ
0ꢀꢁ
ꢀ
ꢀ0
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁ
ꢀꢁꢂꢀ ꢃꢂꢄꢅ
ꢀꢁꢂꢀ ꢃꢂꢄꢅ
(13b)
(13c)
(13d)
Figure 13. High Efficiency Wide Input Range 12V Regulator
Rev 0
41
For more information www.analog.com
LTC7817
TYPICAL APPLICATIONS
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢁ ꢂꢃꢄꢅ ꢁ ꢀꢁꢂ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀ0ꢁ
ꢀꢁꢂꢂꢁꢃꢄ ꢅ ꢀꢁꢂꢃ ꢄ ꢆꢇꢄ
ꢀ
Rꢀꢁꢂ Rꢀꢁꢂ Rꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂ
ꢀꢁ
ꢅꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢅꢆ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁ
3mΩ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢀꢂꢃꢄ0ꢅ
2mΩ
ꢀ
ꢀꢁ
ꢀꢁꢂ
0ꢀꢁꢂꢃꢄ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁ ꢂꢃ ꢄꢅꢁꢆ
ꢀꢁꢂꢃ ꢄꢅꢆRꢅꢇꢈꢉꢊ
ꢀꢁꢂꢃꢄ
ꢅꢀ
ꢀꢁꢂꢃ
0ꢀꢁꢂꢃꢄ
ꢀꢁ0ꢂꢃ
100Ω
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢀ0ꢁꢂ
ꢃꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢃ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁ0ꢂ
ꢀꢁꢂꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀRꢁꢂ
ꢀꢁ
0ꢀꢁꢁꢂꢃ
5mΩ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀ00ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀ
75Ω
ꢀ0ꢁꢂ
ꢀꢁRꢂꢃ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ0ꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
0ꢀꢁꢂꢃ
ꢀꢁ0ꢂꢃ
ꢀꢁꢀꢂꢃ
0ꢀꢁꢂꢃ
0ꢀꢁꢂꢃ
0
ꢀꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢏꢐꢉ0ꢑꢒꢍ
ꢀꢌꢂꢁꢄꢅꢆꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢏꢐꢉ0ꢑꢒꢍ
ꢀꢁꢂꢃꢐ ꢓꢔꢆꢕꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢆꢖꢉ0ꢑꢒꢍ
ꢀꢌꢂꢁꢐꢇ ꢈꢉꢊꢈꢉꢋꢂꢉ ꢌꢍꢎ0ꢗꢏꢉ0ꢑꢒꢍ
ꢒꢄꢅꢐꢇ ꢎꢂꢈꢒꢎRꢘꢊꢁ ꢙꢘꢒꢗ0ꢐ0ꢚꢄꢛꢄꢀꢋ
ꢒꢆꢇ ꢎꢂꢈꢒꢎRꢘꢊꢁ ꢙꢘꢒꢗ0ꢐ0ꢚꢐꢐꢄꢀꢋ
ꢀꢁꢂꢃꢂꢄꢅ ꢆꢇꢈꢆꢇꢉꢊꢇ ꢋꢌꢍꢁꢎ0ꢏꢉꢐꢄꢃꢑꢒꢓꢍꢌꢁ
ꢀ
ꢀꢁꢂꢁꢃꢄꢅꢆ
ꢀꢁ
ꢔ
ꢔ
ꢔ
ꢔ
ꢅ ꢍꢕꢇꢔꢊꢇ ꢐꢄꢔꢉꢃꢃ0ꢖꢗ
ꢆꢇ
ꢀ ꢁꢂꢃꢄ ꢅ ꢀ ꢁꢂꢃ ꢄꢅꢆꢇꢄꢈꢄ ꢉꢊꢄꢋꢇꢌꢍꢎ ꢏꢊꢅꢎ ꢉꢈRRꢍꢌꢐ ꢅꢂꢅꢇꢏꢅꢋꢏꢍ ꢇꢑ Rꢍꢎꢈꢉꢍꢎ
ꢅ ꢘꢉꢙꢉꢓ ꢓꢚꢃ0ꢋꢁꢚꢑꢙ00ꢎꢌꢓꢉ0ꢁꢚ
ꢀꢁ
ꢊꢕꢓꢁ
ꢊꢕꢓꢃ
ꢊꢕꢓꢄ
ꢀ ꢁꢂꢃꢄꢂꢃ ꢅꢂRRꢆꢇꢃ ꢅꢈꢄꢈꢉꢊꢋꢊꢃꢌ ꢈꢃ ꢍꢊꢎꢍ ꢊꢇꢄꢂꢃ ꢏꢁꢋꢃꢈꢎꢆꢐ ꢑꢈꢌ ꢉꢆ ꢋꢊꢑꢊꢃꢆꢒ ꢉꢌ ꢃꢍꢆ ꢃꢍꢆRꢑꢈꢋ
ꢅ ꢘꢉꢙꢉꢓ ꢓꢚꢃ0ꢋꢁ0ꢑꢙ00ꢐꢌꢛꢉ0ꢑ0
ꢅ ꢛꢌꢇꢌꢍꢊꢇꢆꢔ ꢚ0ꢍꢜꢛꢈꢐꢝꢙ
ꢀꢁꢂRꢂꢀꢃꢄRꢅꢆꢃꢅꢀꢆ ꢇꢈ ꢃꢁꢄ ꢇꢉꢄRꢂꢊꢊ ꢆꢋꢆꢃꢄꢌ ꢂꢍꢎ ꢏRꢅꢍꢃꢄꢎ ꢀꢅRꢀꢐꢅꢃ ꢑꢇꢂRꢎ ꢎꢄꢆꢅꢒꢍ
(14a)
Efficiency and Power Loss vs
Load Current
Efficiency vs Input Voltage
V
OUT1 Switch Node Waveform
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
ꢀ0
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ
ꢀ
ꢀꢁꢂꢃR ꢄꢁꢅꢅ
0ꢀꢁ
0ꢀ0ꢁ
0ꢀ00ꢁ
ꢀꢁꢁ ꢂꢃRꢄꢄ ꢅꢃꢀꢆꢆꢄꢁꢇ ꢈꢆ
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ ꢅꢈꢇRꢉꢃꢊꢅꢋ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ ꢁ00ꢂꢃ
ꢀ ꢁꢂ
ꢀ
ꢀ
ꢀ ꢁ00ꢂꢃ
ꢀ ꢁꢂ
0
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢁ ꢂꢃRꢄꢄ ꢅꢃꢀꢆꢆꢄꢁꢇ ꢈꢆ
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ ꢅꢈꢇRꢉꢃꢊꢅꢋ
ꢀꢁ
ꢀꢁꢂꢀ ꢃꢂꢄꢅ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
0ꢀ000ꢁ 0ꢀ00ꢁ
0ꢀ0ꢁ
0ꢀꢁ
ꢀ
ꢀ0
ꢀ00ꢁꢂꢃꢄꢅv
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁ
ꢀꢁꢂꢀ ꢃꢂꢄꢅ
ꢀꢁꢂꢀ ꢃꢂꢄꢅ
(14b)
(14c)
(14d)
Figure 14. High Efficiency Wide Input Range 2.25MHz Dual 5V/3.3V Regulator
Rev 0
42
For more information www.analog.com
LTC7817
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
ꢛReꢪeꢫeꢬꢭe ꢕꢅꢍ ꢈꢊꢌ ꢮ 0ꢀꢖ0ꢟꢖꢂꢞ0ꢂ Rev ꢍꢝ
0ꢁꢞ0 0ꢁ0ꢀ
ꢀꢁꢀ0 0ꢁ0ꢀ
ꢧꢁꢂ0 0ꢁ0ꢀ
ꢚꢁ00 Rꢆꢎ
ꢀꢁꢂꢀ 0ꢁ0ꢀ
ꢚꢁꢂꢀ 0ꢁ0ꢀ
ꢒꢉꢍꢓꢉꢌꢆ
ꢄꢔꢅꢕꢋꢃꢆ
0ꢁꢗꢀ 0ꢁ0ꢀ
0ꢁꢀ0 ꢠꢐꢍ
ꢀꢁꢀ Rꢆꢎ
ꢜꢁꢂ0 0ꢁ0ꢀ
ꢞꢁꢀ0 0ꢁ0ꢀ
Rꢆꢍꢄꢏꢏꢆꢃꢈꢆꢈ ꢐꢄꢕꢈꢆR ꢒꢉꢈ ꢕꢉꢤꢄꢔꢅ
ꢉꢒꢒꢕꢤ ꢐꢄꢕꢈꢆR ꢏꢉꢐꢓ ꢅꢄ ꢉRꢆꢉꢐ ꢅꢙꢉꢅ ꢉRꢆ ꢃꢄꢅ ꢐꢄꢕꢈꢆRꢆꢈ
ꢒꢋꢃ ꢂ ꢃꢄꢅꢍꢙ
R ꢣ 0ꢁꢚ0 ꢅꢤꢒ ꢄR
0ꢁꢚꢀ × ꢧꢀ° ꢍꢙꢉꢏꢎꢆR
0ꢁꢞꢀ 0ꢁ0ꢀ
0ꢁ00 ꢦ 0ꢁ0ꢀ
ꢚꢁ00 Rꢆꢎ
ꢀꢁ00 0ꢁꢂ0
ꢚꢞ
ꢚꢟ
0ꢁꢧ0 0ꢁꢂ0
ꢒꢋꢃ ꢂ
ꢅꢄꢒ ꢏꢉRꢓ
ꢂ
ꢗ
ꢛꢐꢆꢆ ꢃꢄꢅꢆ ꢜꢝ
ꢀꢁꢂꢀ 0ꢁꢂ0
ꢀꢁꢀ0 Rꢆꢎ
ꢞꢁ00 0ꢁꢂ0
ꢚꢁꢂꢀ 0ꢁꢂ0
ꢛꢔꢙꢝ ꢥꢎꢃ Rꢆꢎ ꢍ ꢂꢂ0ꢞ
0ꢁꢗ00 Rꢆꢎ 0ꢁꢗꢀ 0ꢁ0ꢀ
0ꢁꢀ0 ꢠꢐꢍ
R ꢣ 0ꢁꢂꢗꢀ
ꢅꢤꢒ
R ꢣ 0ꢁꢂ0
ꢅꢤꢒ
ꢠꢄꢅꢅꢄꢏ ꢘꢋꢆꢊꢡꢆꢢꢒꢄꢐꢆꢈ ꢒꢉꢈ
ꢃꢄꢅꢆꢇ
ꢂꢁ ꢈRꢉꢊꢋꢃꢌ ꢍꢄꢃꢎꢄRꢏꢐ ꢅꢄ ꢑꢆꢈꢆꢍ ꢒꢉꢍꢓꢉꢌꢆ
ꢄꢔꢅꢕꢋꢃꢆ ꢏ0ꢖꢗꢗ0 ꢘꢉRꢋꢉꢅꢋꢄꢃ ꢊꢙꢓꢈ
ꢗꢁ ꢈRꢉꢊꢋꢃꢌ ꢃꢄꢅ ꢅꢄ ꢐꢍꢉꢕꢆ
ꢧꢁ ꢈꢋꢏꢆꢃꢐꢋꢄꢃꢐ ꢄꢎ ꢆꢢꢒꢄꢐꢆꢈ ꢒꢉꢈ ꢄꢃ ꢠꢄꢅꢅꢄꢏ ꢄꢎ ꢒꢉꢍꢓꢉꢌꢆ ꢈꢄ ꢃꢄꢅ ꢋꢃꢍꢕꢔꢈꢆ
ꢏꢄꢕꢈ ꢎꢕꢉꢐꢙꢁ ꢏꢄꢕꢈ ꢎꢕꢉꢐꢙꢨ ꢋꢎ ꢒRꢆꢐꢆꢃꢅꢨ ꢐꢙꢉꢕꢕ ꢃꢄꢅ ꢆꢢꢍꢆꢆꢈ 0ꢁꢗ0ꢩꢩ ꢄꢃ ꢉꢃꢤ ꢐꢋꢈꢆ
ꢀꢁ ꢆꢢꢒꢄꢐꢆꢈ ꢒꢉꢈ ꢐꢙꢉꢕꢕ ꢠꢆ ꢐꢄꢕꢈꢆR ꢒꢕꢉꢅꢆꢈ
ꢜꢁ ꢐꢙꢉꢈꢆꢈ ꢉRꢆꢉ ꢋꢐ ꢄꢃꢕꢤ ꢉ RꢆꢎꢆRꢆꢃꢍꢆ ꢎꢄR ꢒꢋꢃ ꢂ ꢕꢄꢍꢉꢅꢋꢄꢃ
ꢄꢃ ꢅꢙꢆ ꢅꢄꢒ ꢉꢃꢈ ꢠꢄꢅꢅꢄꢏ ꢄꢎ ꢒꢉꢍꢓꢉꢌꢆ
ꢚꢁ ꢉꢕꢕ ꢈꢋꢏꢆꢃꢐꢋꢄꢃꢐ ꢉRꢆ ꢋꢃ ꢏꢋꢕꢕꢋꢏꢆꢅꢆRꢐ
Rev 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
43
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC7817
TYPICAL APPLICATION
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃ
ꢀ0ꢁ ꢂꢃꢄꢅ ꢁ ꢇ ꢀ0ꢁ
ꢀꢀ
ꢀꢁ
ꢆꢅ
ꢀ
ꢀꢁꢂꢃ
ꢀ0ꢁ
ꢀꢁꢂꢂꢁꢃꢄ ꢅ ꢀꢁꢂꢃ ꢄ ꢆ ꢇ0ꢄ
ꢀ
Rꢀꢁꢂ Rꢀꢁꢂ Rꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂ
ꢀꢁ
ꢅꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄ
ꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁ
0ꢀꢁꢂꢃꢄ
2mΩ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
2mΩ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢀꢂꢃꢄ0ꢅ
0ꢀꢁꢂꢃ
ꢀ
ꢀꢁ ꢂꢃ ꢄꢅꢁꢆ
ꢀꢁꢂꢃ ꢄꢅꢆRꢅꢇꢈꢉꢊ
ꢀꢁꢂꢃ
0ꢀꢁꢂꢃꢄ
ꢀ0ꢁꢂ
ꢀ00ꢁꢂ
100Ω
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢀ0ꢁꢂ
ꢃꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢃ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁ0ꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄ
9mΩ
0ꢀꢁꢂꢃ
ꢀ
ꢀRꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁRꢂꢃ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈ
50Ω
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀꢀ
ꢀꢁꢂ
ꢀ00ꢁ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢀꢁ
ꢀꢁꢀꢂ
ꢀꢁꢂꢀꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
0ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢀꢂꢃ
0ꢀꢁꢂꢃ
0ꢀꢁꢂꢃ
0
ꢀꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢊꢋꢌꢍ ꢊꢎRꢏꢐꢑꢒꢃ
ꢀꢓꢂꢁꢄꢅꢆꢇ ꢈꢉꢊꢋꢌꢍ ꢊꢎRꢏꢐꢑꢒꢃ
ꢀꢁꢂꢃꢐꢇ ꢈꢉꢊꢋꢌꢍ ꢊꢎRꢑꢔ0ꢒꢃ
ꢀꢓꢂꢁꢐꢇ ꢈꢉꢊꢋꢌꢍ ꢊꢎRꢑꢔ0ꢒꢃ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢀꢅRꢈꢉꢊ ꢋꢈꢀꢌ0ꢃ0ꢍꢁꢎꢁꢏꢐ
ꢀꢑꢄ ꢅꢆꢇꢀꢅRꢈꢉꢊ ꢋꢈꢀꢌ0ꢃ0ꢍꢁꢑꢑꢏꢐ
ꢀ
ꢀꢁꢂꢁꢃꢄꢅꢆ
ꢀꢁ
ꢀ ꢁꢂꢃꢄ ꢅ ꢀ ꢁꢂꢃ ꢄꢅꢆꢇꢄꢈꢄ ꢉꢊꢄꢋꢇꢌꢍꢎ ꢏꢊꢅꢎ ꢉꢈRRꢍꢌꢐ ꢅꢂꢅꢇꢏꢅꢋꢏꢍ ꢇꢑ Rꢍꢎꢈꢉꢍꢎ
ꢅ
ꢅ
ꢅ
ꢄ ꢓꢔꢒꢅꢆꢒ ꢎꢃꢅꢐꢑꢑ0ꢀꢋ
ꢀꢁ
ꢇꢒ
ꢀ ꢁꢂꢃꢄꢂꢃ ꢅꢂRRꢆꢇꢃ ꢅꢈꢄꢈꢉꢊꢋꢊꢃꢌ ꢈꢃ ꢍꢊꢎꢍ ꢊꢇꢄꢂꢃ ꢏꢁꢋꢃꢈꢎꢆꢐ ꢑꢈꢌ ꢉꢆ ꢋꢊꢑꢊꢃꢆꢒ ꢉꢌ ꢃꢍꢆ ꢃꢍꢆRꢑꢈꢋ
ꢄ ꢕꢈꢒꢈꢓꢆꢒꢇꢅ ꢎꢊꢕꢐꢁ00ꢏꢕꢖ
ꢄ ꢕꢈꢒꢈꢓꢆꢒꢇꢅ ꢌ0ꢓꢗꢕꢉꢘꢑꢏ
ꢆꢔꢊꢁ
ꢆꢔꢊꢃ
ꢀꢁꢂRꢂꢀꢃꢄRꢅꢆꢃꢅꢀꢆ ꢇꢈ ꢃꢁꢄ ꢇꢉꢄRꢂꢊꢊ ꢆꢋꢆꢃꢄꢌ ꢂꢍꢎ ꢏRꢅꢍꢃꢄꢎ ꢀꢅRꢀꢐꢅꢃ ꢑꢇꢂRꢎ ꢎꢄꢆꢅꢒꢍ
ꢒꢄꢅꢆꢅꢐꢇ ꢕꢖꢗꢁRꢌꢘ ꢊꢖꢀꢉ ꢕꢀꢒꢊꢋꢙꢔꢖ
Figure 15. High Efficiency Wide Input Range 2.25MHz Dual 3.3V/8.5V Regulator
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC7818
LTC7804
LTC7803
LTC7815
LTC3859AL
LTC3899
LTC7800
LTC3892
40V, Low I , 3MHz, Triple Output Buck/Buck/Boost
4.5V ≤ V ≤ 40V, I = 14µA, 100% Duty Cycle Capable Boost
Q
IN
Q
Synchronous Controller with Spread Spectrum
Buck and Boost V
Up to 40V, PLL Fixed Frequency 100kHZ to 3MHz
OUT
40V Low I , 3MHz Synchronous Boost Controller
4.5V(Down to 1V after Start-up) ≤ V ≤ 40V, V
up to 40V, I = 14µA
Q
IN
OUT Q
100% Duty Cycle Capable
PLL Fixed Frequency 100kHZ to 3MHHz, 3mm x 3mm QFN-16, MSOP-16E
40V Low I , 3MHz 100% Duty Cycle Synchronous
4.4V≤ V ≤ 40V, 0.8V ≤ V ≤ 40V, I = 12µA
Q
IN
OUT
Q
Step-Down Controller
PLL Fixed Operating Frequency 50kHz to 900kHz
38V Low I , Triple Output, Buck/Buck/Boost Synchronous
4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, I = 28μA
Q
IN
OUT
Q
Controller PLL Fixed Operating Frequency 320kHz to 2.25MHz Buck V
Range: 0.8V to 24V, Boost V
Up to 60V
OUT
38V Low I , Triple Output, Buck/Buck/Boost Synchronous
4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, I = 28μA
Q
IN
OUT
Q
Controller PLL Fixed Operating Frequency 50kHz to 900kHz Buck V
Range: 0.8V to 24V, Boost V
Up to 60V
OUT
60V Low I , Triple Output, Buck/Buck/Boost Synchronous
4.5V (Down to 2.2V After Start-Up) ≤ V ≤ 60V, I = 28μA
IN Q
Q
Controller PLL Fixed Operating Frequency 50kHz to 900kHz Buck & Boost V
Up to 60V
OUT
60V Low I , High Frequency Synchronous Step-Down
4V ≤ V ≤ 60V, 0.8V ≤ V
≤ 24V, I = 50μA
OUT Q
Q
IN
Controller
PLL Fixed Frequency 320kHz to 2.25MHz
60V Low I , Dual 2-Phase Synchronous Step-Down
4.5V ≤ V ≤ 60V, 0.8V ≤ V ≤ 0.99V , I = 50μA
Q
IN
OUT
IN Q
Controller with Adjustable Gate Drive Voltage
PLL Fixed Frequency 50kHz to 900kHz
Rev 0
09/20
www.analog.com
ANALOG DEVICES, INC. 2020
44
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