LTM4626 [ADI]
20VIN, 8A Step-Down DC/DC μModule Regulator;
| 型号： | LTM4626 |
| 厂家： | 
ADI |
| 描述： | 20VIN, 8A Step-Down DC/DC μModule Regulator |
| 文件： | 总28页 (文件大小：1995K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4657
20VIN, 8A Step-Down DC/DC
µModule Regulator
FEATURES
DESCRIPTION
2
n
Complete Solution in <1cm (Single-Sided PCB) or
The LTM®4657 is a complete 8A step-down switching
mode µModule (micromodule) regulator in a tiny 6.25mm
× 6.25mm × 3.87mm BGA package. Included in the pack-
age are the switching controller, power FETs, inductor and
support components. Operating over an input voltage
range of 3.1V to 20V, the LTM4657 supports an output
voltage range of 0.5V to 5.5V, set by a single external
resistor. Its high efficiency design delivers up to 8A con-
tinuous output current. Only bulk input and output capac-
itors are needed.
2
0.5cm (Dual-Sided PCB)
n
n
n
n
n
6.25mm × 6.25mm × 3.87mm BGA Package
Wide Input Voltage Range: 3.1V to 20V
0.5V to 5.5V Output Voltage
8A DC Output Current
1.5ꢀ Maximum Total DC Output Voltage Error
Over Line, Load and Temperature
Differential Remote Sensing Amp
Current Mode Control, Fast Transient Response
External Frequency Synchronization
Multiphase Parallel Current Sharing with
Multiple LTM4657s
n
n
n
n
The LTM4657 supports selectable discontinuous mode
operation and output voltage tracking for supply rail
sequencing. Its high switching frequency and current
mode control enable a very fast transient response to
line and load changes without sacrificing stability.
n
n
n
n
Output Voltage Tracking
Selectable Discontinuous Mode
Power Good Indicator
Overvoltage, Overcurrent and Overtemperature
Protection
Pin Compatible with LTM4626(12A) and LTM4638(15A)
Fault protection features incl0ude overvoltage, overcur-
rent and overtemperature protection.
n
The LTM4657 is available with SnPb or RoHS compliant
terminal finish.
APPLICATIONS
All registered trademarks and trademarks are the property of their respective owners.
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Telecom, Datacom, Networking and
Industrial Equipment
n
Medical Diagnostic Equipment
n
Data Storage Rack Units and Cards
n
Test and Debug Systems
TYPICAL APPLICATION
Efficiency vs Load Current for VOUT = 1V
8A, 1.0V Output DC/DC µModule® Step-Down Regulator
ꢐꢑ
ꢑꢋꢋꢛꢜꢝ
ꢐꢋ
ꢓꢑ
ꢓꢋ
ꢒꢑ
ꢒꢋ
ꢔRꢉꢕ
ꢅꢋꢌꢇꢃꢄ
ꢀ
ꢀ
ꢗ.ꢘꢀ
ꢝA
ꢇꢃꢄ
ꢀ
ꢁꢂ
ꢀ
ꢇꢃꢄ
ꢖ
ꢁꢂ
ꢜ.ꢗꢀ ꢄꢇ ꢛꢘꢀ
ꢗꢘꢘꢙꢔ
ꢚꢛ
ꢗꢘꢙꢔ
ꢀ
ꢇꢍꢂꢍ
Rꢃꢂ
ꢁꢂꢄꢀ
ꢋꢄꢆꢐꢑꢒꢓ
ꢅꢅ
ꢎꢟꢇꢇꢈ
ꢅꢇꢆꢎꢠ
ꢅꢇꢆꢎꢡ
ꢆꢇꢈꢉꢊꢅꢋꢌꢁꢂ
ꢄRAꢅꢌꢊꢍꢍ
ꢎꢏꢆꢇꢈꢉ
ꢘ.ꢗꢙꢔ
ꢔꢞ
ꢑꢘ.ꢐꢢ
ꢖꢙꢚ
ꢑꢚ
ꢍꢈ
ꢍꢈ
ꢣ
ꢟꢂꢈ
ꢀ
ꢇꢍꢂꢍ
ꢔꢑ
ꢋ
ꢖ
ꢙ
ꢘ
ꢕ
ꢑ
ꢔ
ꢒ
ꢓ
ꢐꢑꢒꢓ ꢄAꢘꢗꢠ
ꢀꢁꢂꢃꢁꢂ ꢄꢀAꢅ ꢆꢁRRꢇꢈꢂ ꢉAꢊ
ꢕꢔꢑꢒ ꢂAꢋꢖꢗ
Rev. A
1
Document Feedback
For more information www.analog.com
LTM4657
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
(See Pin Functions, Pin Configuration Table)
V ............................................................. –0.3V to 22V
OUT
IN
ꢕꢟꢂ ꢡꢢꢅꢞ
ꢧꢞ
V
............................................................. –0.3V to 6V
ꢕ
ꢕ
ꢫ
ꢧꢅꢤꢧꢅ
INTV ...................................................... –0.3V to 3.6V
CC
ꢓ
ꢌ
ꢎ
ꢆ
ꢑ
ꢍ
ꢚ
ꢁꢤꢊ
ꢬ
RUN ........................................................... –0.3V to 22V
ꢧꢅꢤꢧꢅ
PGOOD, FREQ, COMPa, COMPb,
ꢂꢁꢟꢟꢊ
ꢡ
ꢟꢦꢕ
ꢂꢩꢗꢟꢊꢅ
PHMODE, CLKOUT, FB.............................. –0.3V to 3.6V
Rꢦꢤ
ꢢꢤꢕꢡ
MODE/CLKIN, TRACK/SS .....................–0.3V to INTV
CC
ꢡ
ꢡ
ꢢꢤ
+
V
V
......................................................... –0.3V to 6V
OSNS
OSNS
ꢃꢃ
–
ꢟꢦꢕ
...................................................... –0.3V to 0.3V
ꢗꢟꢊꢅꢝꢃꢉꢄꢢꢤ
ꢕRAꢃꢄꢝꢧꢧ
ꢡ
ꢫ
ꢟꢧꢤꢧ
ꢟꢧꢤꢧ
Internal Operating Temperature Range
ꢡ
ꢬ
ꢃꢉꢄꢟꢦꢕ
(Notes 2, 3)............................................ –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Body Temperature.................250°C
ꢣꢀ
ꢃꢟꢗꢂꢯ
ꢃꢟꢗꢂꢭ
ꢣRꢅꢮ
A
ꢀ
ꢃ
ꢊ
ꢅ
ꢣ
ꢁ
ꢀꢁA ꢂAꢃꢄAꢁꢅ
ꢆꢇꢈꢉꢅAꢊ ꢋꢌ.ꢍꢎꢏꢏ ꢐ ꢌ.ꢍꢎꢏꢏ ꢐ ꢑ.ꢒꢓꢏꢏꢔ
ꢕ
ꢙ ꢚꢍꢎꢛꢃꢜ θ ꢙ ꢚꢓꢛꢃꢝꢞꢜ
ꢖꢗAꢘ
ꢖA
ꢙ ꢆ.ꢠꢛꢃꢝꢞ
ꢖꢃꢀꢟꢕꢕꢟꢗ
θ
ꢙ ꢇ.ꢆꢛꢃꢝꢞꢜ θ
ꢖꢃꢕꢟꢂ
ꢤꢟꢕꢅꢥ
1) θ ꢡAꢉꢦꢅꢧ ARꢅ ꢊꢅꢕꢅRꢗꢢꢤꢅꢊ ꢀꢨ ꢧꢢꢗꢦꢉAꢕꢢꢟꢤ ꢂꢅR ꢖꢅꢧꢊꢎꢚ ꢃꢟꢤꢊꢢꢕꢢꢟꢤꢧ.
2) θ ꢡAꢉꢦꢅ ꢢꢧ ꢟꢀꢕAꢢꢤꢅꢊ ꢞꢢꢕꢩ ꢊꢅꢗꢟ ꢀꢟARꢊ.
ꢖA
ꢑꢔ RꢅꢣꢅR ꢕꢟ ꢂAꢁꢅ ꢚꢇ ꢣꢟR ꢉAꢀ ꢗꢅAꢧꢦRꢅꢗꢅꢤꢕ Aꢤꢊ ꢊꢅꢈRAꢕꢢꢤꢁ ꢢꢤꢣꢟRꢗAꢕꢢꢟꢤ.
ꢆꢔ ꢞꢅꢢꢁꢩꢕ ꢙ ꢆꢇꢓꢏꢪ
ORDER INFORMATION
PART MARKING*
PACKAGE
TYPE
MSL
TEMPERATURE RANGE
(Note 2)
PART NUMBER
LTM4657EY#PBF
LTM4657IY#PBF
LTM4657IY
PAD OR BALL FINISH
SAC305 (RoHS)
SAC305 (RoHS)
SnPb
DEVICE
FINISH CODE
RATING
4657
4657
4657
e1
e1
e0
BGA
BGA
BGA
3
3
3
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V per the typical application shown on the
front page.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Regulator Section: per Channel
l
l
V
V
V
Input DC Voltage
V
3.1
0.5
20
V
V
IN
IN
Output Voltage Range
Output Voltage, Total
Variation with Line and Load MODE = INTV , I
5.5
OUT
C
= 22µF, C
= 100µF Ceramic, R = 30.2k,
FB
CC OUT
OUT(DC)
IN
OUT
= 0A to 8A (Note 3)
l
–40°C to 125°C
V Rising
RUN
1.477
1.05
1.50
1.20
1.523
1.35
V
V
V
RUN Pin On Threshold
RUN
Rev. A
2
For more information www.analog.com
LTM4657
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V per the typical application shown on the
front page.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input Supply Bias Current
V
V
= 12V, V
= 12V, V
= 1.5V, MODE = INTV
= 1.5V, MODE = GND
70
18
70
mA
mA
µA
Q(VIN)
IN
IN
OUT
OUT
CC
Shutdown, RUN = 0, V = 12V
IN
I
I
Input Supply Current
V
V
= 12V, V
= 12V, V
= 1.5V, I
= 1.5V
= 8A
OUT
1.15
A
A
S(VIN)
IN
IN
OUT
OUT
Output Continuous Current
Range
0
8
OUT(DC)
l
l
ΔV
ΔV
(Line)/V
Line Regulation Accuracy
Load Regulation Accuracy
Output Ripple Voltage
V
V
= 1.5V, V = 3.1V to 20V, I = 0A
OUT
0.04
0.2
5
0.15
1.2
ꢀ
ꢀ
OUT
OUT
OUT
OUT
OUT
OUT
IN
(Load)/V
= 1.5V, I
= 0A to 8A
OUT
OUT
V
I
V
= 0A, C
= 1.5V
= 100µF Ceramic, V = 12V,
mV
OUT(AC)
OUT
IN
OUT
ΔV
Turn-On Overshoot
Turn-On Time
I
= 0A, C
= 1.5V
= 100µF Ceramic, V = 12V,
30
2.5
160
40
mV
ms
mV
µs
OUT(START)
OUTLS
OUT
OUT
OUT
IN
V
t
C
V
= 100µF Ceramic, No Load, TRACK/SS = 0.01µF,
= 1.5V
START
OUT
= 12V, V
IN
OUT
ΔV
Peak Deviation for Dynamic
Load
Load: 0ꢀ to 50ꢀ to 0ꢀ of Full Load, C
Ceramic, V = 12V, V
= 47µF
OUT
= 1.5V
IN
OUT
t
Settling Time for Dynamic
Load Step
Load: 0ꢀ to 50ꢀ to 0ꢀ of Full Load, C
Ceramic, V = 12V, V = 1.5V
= 47µF
SETTLE
OUT
IN
OUT
I
Output Current Limit
Voltage at FB Pin
Current at FB Pin
V
= 12V, V
= 1.5V
13
A
V
OUTPK
IN
OUT
OUT
l
V
I
= 0A, V
= 1.5V
0.495
60.05
0.50
0.505
50
FB
OUT
I
(Note 4)
nA
kΩ
FB
R
Resistor Between V
and
OUT
60.40
6
60.75
FBHI
FB Pins
I
Track Pin Soft-Start Pull-Up
Current
TRACK/SS = 0V
10
µA
TRACK/SS
V
V
IN
Undervoltage Lockout
V
IN
V
IN
Falling
Hysteresis
2.5
2.7
250
2.9
V
mV
IN(UVLO)
t
t
Minimum On-Time
Minimum Off-Time
PGOOD Trip Level
(Note 4)
(Note 4)
25
50
ns
ns
ON(MIN)
OFF(MIN)
V
V
With Respect to Set Output
Ramping Negative
Ramping Positive
PGOOD
FB
V
V
–11
5
–8
8
–5
11
ꢀ
ꢀ
FB
FB
I
PGOOD Leakage
2
µA
V
PGOOD
V
V
PGOOD Voltage Low
I
= 1mA
PGOOD
0.02
3.3
0.1
3.4
PGL
Internal V Voltage
V = 4V to 20V
IN
3.2
V
INTVCC
OSC
CC
f
Oscillator Frequency
500
kHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
controls. The LTM4657I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
Note 2: The LTM4657 is tested under pulsed load conditions such that
T ≈ T . The LTM4657E is guaranteed to meet performance specifications
J
A
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
Note 3: See output current derating curves for different V , V
Note 4: 100ꢀ tested at wafer level.
and T .
IN OUT A
Rev. A
3
For more information www.analog.com
LTM4657
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
from 3.3VIN
Efficiency vs Load Current
from 5VIN
Efficiency vs Load Current
from 12VIN
ꢐꢋꢋ
ꢑꢒ
ꢑꢋ
ꢓꢒ
ꢓꢋ
ꢔꢒ
ꢔꢋ
ꢐꢋꢋ
ꢑꢒ
ꢑꢋ
ꢓꢒ
ꢓꢋ
ꢔꢒ
ꢔꢋ
ꢕꢒ
ꢐꢋꢋ
ꢑꢒ
ꢑꢋ
ꢓꢒ
ꢓꢋ
ꢔꢒ
ꢔꢋ
ꢕꢒ
ꢐꢖꢚ ꢛ ꢐꢚ ꢛ ꢒꢋꢋꢜꢝꢞ
ꢍꢈ
ꢀꢁꢂ
ꢒꢚ ꢛ ꢐꢚ ꢛ ꢒꢋꢋꢜꢝꢞ
ꢐꢖꢚ ꢛ ꢐ.ꢒꢚ ꢛ ꢕꢒꢋꢜꢝꢞ
ꢍꢈ ꢀꢁꢂ
ꢍꢈ
ꢀꢁꢂ
ꢗ.ꢗꢚ ꢛ ꢐꢚ ꢛ ꢒꢋꢋꢜꢝꢞ
ꢒꢚ ꢛ ꢐ.ꢒꢚ ꢛ ꢕꢒꢋꢜꢝꢞ
ꢐꢖꢚ ꢛ ꢖ.ꢒꢚ ꢛ ꢓꢋꢋꢜꢝꢞ
ꢍꢈ ꢀꢁꢂ
ꢍꢈ
ꢀꢁꢂ
ꢍꢈ
ꢍꢈ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢗ.ꢗꢚ ꢛ ꢐ.ꢒꢚ ꢛ ꢘꢒꢋꢜꢝꢞ
ꢒꢚ ꢛ ꢖ.ꢒꢚ ꢛ ꢓꢋꢋꢜꢝꢞ
ꢐꢖꢚ ꢛ ꢘ.ꢘꢚ ꢛ ꢐꢋꢋꢋꢜꢝꢞ
ꢍꢈ ꢀꢁꢂ
ꢍꢈ
ꢍꢈ
ꢀꢁꢂ
ꢀꢁꢂ
ꢗ.ꢗꢚ ꢛ ꢕ.ꢒꢚ ꢛ ꢓꢋꢋꢜꢝꢞ
ꢒꢚ ꢛ ꢘ.ꢘꢚ ꢛ ꢐꢋꢋꢋꢜꢝꢞ
ꢐꢖꢚ ꢛ ꢒꢚ ꢛ ꢐꢖꢒꢋꢜꢝꢞ
ꢍꢈ ꢀꢁꢂ
ꢍꢈ
ꢋ
ꢐ
ꢕ
ꢗ
ꢖ
ꢒ
ꢘ
ꢔ
ꢓ
ꢋ
ꢐ
ꢖ
ꢘ
ꢗ
ꢒ
ꢕ
ꢔ
ꢓ
ꢋ
ꢐ
ꢖ
ꢘ
ꢗ
ꢒ
ꢕ
ꢔ
ꢓ
ꢀꢁꢂꢃꢁꢂ ꢄꢀAꢅ ꢆꢁRRꢇꢈꢂ ꢉAꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢀAꢅ ꢆꢁRRꢇꢈꢂ ꢉAꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢀAꢅ ꢆꢁRRꢇꢈꢂ ꢉAꢊ
ꢖꢘꢒꢔ ꢙꢋꢐ
ꢗꢕꢒꢔ ꢙꢋꢖ
ꢗꢕꢒꢔ ꢙꢋꢘ
1V Output Transient Response
1.5V Output Transient Response
2.5V Output Transient Response
ꢌꢍꢎꢝꢍꢎ
ꢇꢌꢢꢎAꢣꢛ
ꢏꢁꢤꢇꢄꢅꢆꢇ
ꢌꢍꢎꢜꢍꢎ
ꢇꢌꢡꢎAꢢꢚ
ꢒꢁꢣꢇꢄꢅꢆꢇ
ꢌꢍꢎꢝꢍꢎ
ꢇꢌꢢꢎAꢣꢛ
ꢏꢁꢤꢇꢄꢅꢆꢇ
ꢢꢌAꢅ
ꢗꢍRRꢛꢈꢎ
ꢀAꢄꢅꢆꢇ
ꢡꢌAꢅ
ꢖꢍRRꢚꢈꢎ
ꢀAꢄꢅꢆꢇ
ꢢꢌAꢅ
ꢗꢍRRꢛꢈꢎ
ꢀAꢄꢅꢆꢇ
ꢥꢓꢏꢦ ꢣꢁꢏ
ꢤꢥꢒꢦ ꢢꢁꢤ
ꢥꢦꢏꢧ ꢣꢁꢦ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢇ
ꢖ
ꢉ ꢀꢊꢇꢋ ꢇ
ꢉ ꢀꢇꢋ ꢏ ꢉ ꢒꢁꢁꢓꢔꢕꢋ
ꢇ
ꢗ
ꢉ ꢀꢊꢇꢋ ꢇ ꢉ ꢊ.ꢏꢇꢋ ꢐ ꢉ ꢓꢁꢁꢔꢕꢖꢋ
ꢌꢍꢎ ꢑꢒ
ꢇ
ꢗ
ꢉ ꢀꢊꢇꢋ ꢇ
ꢉ ꢀ.ꢏꢇꢋ ꢐ ꢉ ꢓꢏꢁꢔꢕꢖꢋ
ꢌꢍꢎ ꢑꢒ
ꢆꢈ
ꢌꢍꢎ
ꢐꢑ
ꢆꢈ
ꢆꢈ
ꢉ ꢊꢗ ꢀꢁꢁꢂꢘ ꢙ ꢊꢊꢂꢘ ꢖꢚRAꢛꢆꢖ ꢖAꢜꢝ
ꢉ ꢊꢘ ꢀꢁꢁꢂꢙ ꢚ ꢊꢊꢂꢙ ꢗꢛRAꢜꢆꢗ ꢗAꢝꢞ
ꢉ ꢊꢘ ꢀꢁꢁꢂꢙ ꢚ ꢊꢊꢂꢙ ꢗꢛRAꢜꢆꢗ ꢗAꢝꢞ
ꢌꢍꢎ
ꢌꢍꢎ
ꢌꢍꢎ
ꢖꢌꢛꢜꢞ ꢉ ꢖꢌꢛꢜꢟ
ꢗꢌꢜꢝꢟ ꢉ ꢗꢌꢜꢝꢠ
ꢗꢌꢜꢝꢟ ꢉ ꢗꢌꢜꢝꢠ
ꢖ
ꢉ ꢀꢁꢁꢠꢘ
ꢗ
ꢉ ꢀꢁꢁꢡꢙ
ꢗ
ꢉ ꢀꢁꢁꢡꢙ
ꢘꢘ
ꢙꢙ
ꢙꢙ
3.3V Output Transient Response
5V Output Transient Response
ꢌꢍꢎꢜꢍꢎ
ꢌꢍꢎꢜꢍꢎ
ꢇꢌꢡꢎAꢢꢚ
ꢏꢁꢣꢇꢄꢅꢆꢇ
ꢇꢌꢡꢎAꢢꢚ
ꢣꢁꢤꢇꢄꢅꢆꢇ
ꢡꢌAꢅ
ꢖꢍRRꢚꢈꢎ
ꢀAꢄꢅꢆꢇ
ꢡꢌAꢅ
ꢖꢍRRꢚꢈꢎ
ꢀAꢄꢅꢆꢇ
ꢥꢦꢣꢧ ꢢꢁꢧ
ꢤꢥꢏꢦ ꢢꢁꢧ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢉ ꢏ.ꢏꢇꢋ ꢐ ꢉ ꢀꢁꢁꢁꢓꢔꢕꢋ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢇ
ꢖ
ꢉ ꢀꢊꢇꢋ ꢇ
ꢌꢍꢎ
ꢇ
ꢖ
ꢉ ꢀꢊꢇꢋ ꢇ
ꢉ ꢏꢇꢋ ꢐ ꢉ ꢀꢊꢏꢁꢓꢔꢕꢋ
ꢌꢍꢎ ꢑꢒ
ꢉ ꢊꢗ ꢀꢁꢁꢂꢘ ꢙ ꢊꢊꢂꢘ ꢖꢚRAꢛꢆꢖ ꢖAꢜꢝ
ꢆꢈ
ꢌꢍꢎ
ꢑꢒ
ꢆꢈ
ꢉ ꢊꢗ ꢀꢁꢁꢂꢘ ꢙ ꢊꢊꢂꢘ ꢖꢚRAꢛꢆꢖ ꢖAꢜꢝ
ꢌꢍꢎ
ꢖꢌꢛꢜꢞ ꢉ ꢖꢌꢛꢜꢟ
ꢖꢌꢛꢜꢞ ꢉ ꢖꢌꢛꢜꢟ
ꢖ
ꢉ ꢀꢁꢁꢠꢘ
ꢖ
ꢉ ꢀꢁꢁꢠꢘ
ꢘꢘ
ꢘꢘ
Rev. A
4
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LTM4657
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up with No Load Current
Start-Up with 8A Load Current
Rꢌꢇ
ꢑꢆꢃꢄꢅꢆ
Rꢌꢇ
ꢑꢆꢃꢄꢅꢆ
ꢝꢣꢋꢋꢄ
ꢑꢆꢃꢄꢅꢆ
ꢝꢤꢋꢋꢄ
ꢑꢆꢃꢄꢅꢆ
ꢆ
ꢆ
ꢋꢌꢍ
ꢋꢌꢍ
ꢉꢆꢃꢄꢅꢆ
ꢉꢆꢃꢄꢅꢆ
ꢅ
ꢅ
ꢅꢇ
ꢅꢇ
ꢀꢒꢒꢁAꢃꢄꢅꢆ
ꢑꢒꢒꢁAꢃꢄꢅꢆ
ꢤꢥꢑꢦ ꢣꢒꢧ
ꢢꢓꢏꢣ ꢤꢀꢀ
ꢦꢧꢑꢨ ꢩꢀꢪ
ꢥꢦꢑꢧ ꢤꢉꢒ
ꢀꢁꢂꢃꢄꢅꢆ
ꢈ ꢉꢆꢊ ꢎ ꢈ ꢑꢒꢒꢓꢔꢕꢊ
ꢀꢁꢂꢃꢄꢅꢆ
ꢆ
ꢖ
ꢈ ꢉꢀꢆꢊ ꢆ
ꢋꢌꢍ
ꢆ
ꢖ
ꢈ ꢉꢀꢆꢊ ꢆ
ꢈ ꢉꢆꢊ ꢎ ꢈ ꢑꢒꢒꢓꢔꢕꢊ
ꢋꢌꢍ ꢏꢐ
ꢈ ꢀꢗ ꢉꢒꢒꢘꢙ ꢚ ꢀꢀꢘꢙ ꢖꢛRAꢜꢅꢖ ꢖAꢝꢞ
ꢅꢇ
ꢋꢌꢍ
ꢏꢐ
ꢅꢇ
ꢈ ꢀꢗ ꢉꢒꢒꢘꢙ ꢚ ꢀꢀꢘꢙ ꢖꢛRAꢜꢅꢖ ꢖAꢝꢞ
ꢋꢌꢍ
ꢖꢋꢜꢝꢟ ꢈ ꢖꢋꢜꢝꢠ
ꢖꢋꢜꢝꢟ ꢈ ꢖꢋꢜꢝꢠ
ꢖ
ꢈ ꢉꢒꢒꢡꢙꢊ ꢜꢋꢄꢛꢢ ꢖꢖꢜꢊ ꢅ
ꢈ ꢒA
ꢖ
ꢈ ꢉꢒꢒꢡꢙꢊ ꢜꢋꢄꢛꢢ ꢖꢖꢜꢊ ꢅ
ꢈ ꢣA
ꢙꢙ
ꢋꢌꢍ
ꢙꢙ
ꢋꢌꢍ
Short-Circuit with No Load
Applied
Short-Circuit with 8A Load
Applied
ꢆ
ꢆ
ꢆꢈ
ꢆꢈ
ꢀAꢄꢅꢆꢇ
ꢀAꢄꢅꢆꢇ
ꢇ
ꢇ
ꢌꢍꢎ
ꢀꢇꢄꢅꢆꢇ
ꢌꢍꢎ
ꢀꢇꢄꢅꢆꢇ
ꢢꢓꢏꢣ ꢤꢀꢊ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢇ
ꢗ
ꢉ ꢀꢊꢇꢋ ꢇ
ꢌꢍꢎ
ꢉ ꢀ.ꢏꢇꢋ ꢐ ꢉ ꢓꢏꢁꢔꢕꢖꢋ
ꢇ
ꢗ
ꢉ ꢀꢊꢇꢋ ꢇ
ꢉ ꢀ.ꢏꢇꢋ ꢐ ꢉ ꢓꢏꢁꢔꢕꢖꢋ
ꢆꢈ
ꢌꢍꢎ
ꢑꢒ
ꢆꢈ
ꢌꢍꢎ
ꢌꢍꢎ ꢑꢒ
ꢉ ꢊꢘ ꢀꢁꢁꢂꢙ ꢚ ꢊꢊꢂꢙ ꢗꢛRAꢜꢆꢗ ꢗAꢝꢞ
ꢉ ꢊꢘ ꢀꢁꢁꢂꢙ ꢚ ꢊꢊꢂꢙ ꢗꢛRAꢜꢆꢗ ꢗAꢝꢞ
ꢗꢌꢜꢝꢟ ꢉ ꢗꢌꢜꢝꢠ
ꢗꢌꢜꢝꢟ ꢉ ꢗꢌꢜꢝꢠ
ꢗ
ꢉ ꢀꢁꢁꢡꢙ
ꢗ
ꢉ ꢀꢁꢁꢡꢙ
ꢙꢙ
ꢙꢙ
Steady-State Output Voltage
Ripple
Start Into Pre-Biased Output
Rꢖꢇ
ꢤꢆꢃꢄꢅꢆ
ꢝꢣꢋꢋꢄ
ꢤꢆꢃꢄꢅꢆ
ꢆ
ꢋꢌꢍ
ꢉꢒꢣꢆꢃꢄꢅꢆ
ꢆ
ꢋꢖꢌ
ꢀꢆꢃꢄꢅꢆ
Aꢖꢤꢖꢋꢌꢜꢥꢚꢄ
ꢅ
ꢅꢇ
ꢀꢑꢑꢁAꢃꢄꢅꢆ
ꢥꢦꢤꢧ ꢣꢉꢥ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢆ
ꢖ
ꢈ ꢀꢉꢆꢊ ꢆ
ꢈ ꢀꢆꢊ ꢎ ꢈ ꢑꢒꢒꢓꢔꢕꢊ
ꢆ
ꢕ
ꢈ ꢉꢀꢆꢊ ꢆ ꢈ ꢉ.ꢀꢆ ꢌꢋ ꢍ.ꢍꢆꢊ ꢎ ꢈ ꢉꢑꢑꢑꢒꢓꢔꢊ
ꢋ ꢏꢐ
ꢅꢇ
ꢋꢌꢍ
ꢏꢐ
ꢅꢇ
ꢈ ꢉꢗ ꢀꢒꢒꢁꢘ ꢙ ꢉꢉꢁꢘ ꢖꢚRAꢛꢅꢖ ꢖAꢜꢝ
ꢈ ꢀꢗ ꢉꢑꢑꢘꢙ ꢚ ꢀꢀꢘꢙ ꢕꢛRAꢜꢅꢕ ꢕAꢝꢞ
ꢋꢌꢍ
ꢋꢖꢌ
ꢖꢋꢛꢜꢞ ꢈ ꢖꢋꢛꢜꢟ
ꢕꢋꢜꢝꢟ ꢈ ꢕꢋꢜꢝꢠ
ꢖ
ꢈ ꢀꢒꢒꢠꢘꢊ ꢛꢋꢄꢚꢡ ꢖꢖꢛꢊ ꢅ
ꢈ ꢢA
ꢕ
ꢈ ꢉꢑꢑꢡꢙꢊ ꢜꢋꢄꢛꢢ ꢕꢕꢜꢊ ꢅ ꢈ ꢑA
ꢘꢘ
ꢋꢌꢍ
ꢙꢙ ꢋ
ꢛꢚAꢏꢌRꢚꢄ AꢖRꢋꢏꢏ ꢉꢉꢁꢘ ꢖꢚRAꢛꢅꢖ ꢖAꢜ
Rev. A
5
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LTM4657
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
PHMODE (G5): Control Input to the Phase Selector of the
Switching Mode Regulator. Determines the phase rela-
tionship between internal oscillator and CLKOUT. Tie it to
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
VOUT (A1-A5, F3, G1-G3): Power Output Pins of the
Switching Mode Regulator. Apply output load between
these pins and GND pins. Recommend placing output
decoupling capacitance directly between these pins and
GND pins. See the Applications Information section for
paralleling outputs.
INTV for 2-phase operation, tie it to GND for 3-phase
CC
operation, and tie it to INTV /2 for 4-phase operation.
CC
See Application Information section for details.
TRACK/SS (E2): Output Tracking and Soft-Start Pin of the
Switching Mode Regulator. Allows the user to control the
rise time of the output voltage. Putting a voltage below
0.5V on this pin bypasses the internal reference input
to the error amplifier, instead it servos the FB pin to the
TRACK voltage. Above 0.5V, the tracking function stops
and the internal reference resumes control of the error
amplifier. There’s an internal 6µA pull-up current from
COMPb (F1): Internal Loop Compensation Network.
Connect to COMPa to use the internal compensation in
majority of applications.
FREQ (E1): Switching Frequency Program Pin. Frequency
is set internally to 500kHz. An external resistor can be
placed from this pin to GND to increase frequency, or from
this pin to INTVCC to reduce frequency. See the Applications
Information section for frequency adjustment.
INTV on this pin, so putting a capacitor here provides
CC
soft-start function. See the Applications Information sec-
tion for details.
MODE/CLKIN (D2): Discontinuous Mode Select Pin and
External Synchronization Input to Phase Detector. Tie
MODE/CLKIN to GND for discontinuous mode of opera-
tion. Floating MODE/CLKIN or tying it to a voltage above
1V will select forced continuous mode. Furthermore, con-
necting MODE/CLKIN to an external clock will synchronize
the system clock to the external clock and puts the part
in forced continuous mode. See Applications Information
section for details.
COMPa (D1): Current control threshold and error ampli-
fier compensation point of the switching mode regulator
channel. The internal current comparator threshold is
linearly proportional to this voltage. Tie the COMPa pins
from different channels together for parallel operation.
The device is internal compensated. Connect to COMPb
to use the internal compensation. Or connect to a Type-II
C-R-C network to use customized compensation.
FB (C1): The Negative Input of the Error Amplifier for
the switching mode regulator. This pin is internally con-
nected to VOSNS+ with a 60.4kΩ precision resistor. Output
–
VOSNS (C2): Negative Input to the Differential Remote
Sense Amplifier. Connect an external resistor between FB
–
and V
pin to set the output voltage of the specific
voltages can be programmed with an additional resistor
channOeSl.NSSee the Applications Information section for
details.
–
between FB and V
pins. In PolyPhase® operation,
OSNS
tying the FB pins together allows for parallel operation.
See the Applications Information section for details.
CLKOUT (F2): Output Clock Signal for PolyPhase
Operation. The phase of CLKOUT with respect to CLKIN
is determined by the state of the respective PHMODE pin.
+
VOSNS (B1): Positive Input to the Differential Remote
Sense Amplifier. Internally, this pin is connected to FB
with a 60.4k 0.5ꢀ precision resistor. See the Applications
Information section for details.
CLKOUT’s peak-to-peak amplitude is INTV to GND. See
CC
Application Information section for details.
Rev. A
6
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LTM4657
PIN FUNCTIONS
V (D3-D4, E3-E4, F4, G4): Power input pins connect to
GND (B2, B6, C3-C7, D5-D7, E5-E7, F5-F7, G6-G7):
Power Ground Pins for Both Input and Output Returns.
Use large PCB copper areas to connect all GND together.
IN
the drain of the internal top MOSFET and signal V to the
IN
internal 3.3V regulator for the control circuitry for each
switching mode regulator channel. Apply input voltages
between these pins and GND pins. Recommend placing
PGOOD (B5): Output Power Good Pin with Open-Drain
Logic. PGOOD is pulled to ground when the voltage on
the FB pin is not within 8ꢀ of the internal 0.5V reference.
input decoupling capacitance directly between V pins
and GND pins.
IN
–
TSENSE (A7): Low Side of the Internal Temperature
INTVCC (B3): Internal 3.3V Regulator Output of the
Switching Mode Regulator Channel. The internal power
drivers and control circuits are powered from this voltage.
Decouple each pin to GND with a minimum of 2.2µF local
low ESR ceramic capacitor.
Monitor.
SW (B7): Switching node of each channel that is used
for testing purposes. Also an R-C snubber network can
be applied to reduce or eliminate switch node ringing, or
otherwise leave floating. See the Applications Information
section.
RUN (B4): Run Control Input Pin. Enable regulator oper-
ation by tying the specific RUN pin above 1.2V. Tying it
below 1.1V shuts down the specific regulator channel.
+
T
(A6): Temperature Monitor Pin. An internal diode
SENSE
+
connected NPN transistor is placed between T
and
SENSE
–
T
pins. See the Applications Information section.
SENSE
Rev. A
7
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LTM4657
BLOCK DIAGRAM
ꢏꢎꢜ
ꢆꢝꢇꢇꢗ
ꢐꢃꢀꢒ
ꢉꢉ
ꢐꢃꢀꢒ
ꢉꢉ
ꢐꢃꢀꢒ
ꢉꢉ
ꢒ
ꢐꢃ
ꢒ
ꢐꢃ
ꢋ.ꢋꢌꢍ
ꢡ.ꢏꢒ ꢀꢇ ꢋꢎꢒ
ꢉ
ꢏꢎꢌꢍ
ꢋꢑꢒ
ꢐꢃ
ꢎ.ꢏꢌꢍ
ꢖꢇꢗꢂꢔꢉꢊꢓꢐꢃ
ꢎ.ꢡꢞꢌꢘ
ꢒ
ꢏ.ꢑꢒ
ꢞA
ꢒ
ꢇꢕꢀ
ꢇꢕꢀ
ꢉꢊꢓꢇꢕꢀ
ꢆꢘꢖꢇꢗꢂ
ꢉ
ꢇꢕꢀ
ꢏꢎꢎꢌꢍ
ꢤꢋ
ꢏꢌꢍ
ꢆꢇꢈꢂR ꢉꢇꢃꢀRꢇꢊ
ꢠ.ꢡꢒ
ꢝꢃꢗ
ꢀRAꢉꢓꢔꢁꢁ
ꢎ.ꢏꢌꢍ
ꢄ
ꢒ
ꢒ
ꢇꢁꢃꢁ
R
ꢍꢛ
Rꢕꢃ
ꢟꢎ.ꢋꢜ
ꢒ
ꢐꢃ
ꢍꢛ
ꢉꢇꢖꢆꢙ
ꢠꢎ.ꢟꢜ
ꢅ
ꢇꢁꢃꢁ
ꢉꢇꢖꢆꢚ
ꢐꢃꢀꢂRꢃAꢊ
ꢍꢐꢊꢀꢂR
ꢅ
ꢀ
ꢀ
ꢁꢂꢃꢁꢂ
ꢁꢂꢃꢁꢂ
ꢐꢃꢀꢂRꢃAꢊ
ꢉꢇꢖꢆ
ꢄ
ꢡꢡꢋꢜ
ꢍRꢂꢣ
ꢝꢃꢗ
ꢟꢠꢑꢢ ꢛꢗ
Figure 1. Simplified LTM4657 Block Diagram
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
C
External Input Capacitor Requirement
IN
I
= 8A
10
22
µF
IN
OUT
(V = 3.1V to 20V, V
= 1.0V)
OUT
External Output Capacitor Requirement
(V = 3.1V to 20V, V = 1.0V)
I
= 8A
150*
330*
µF
OUT
OUT
IN
OUT
*Additional capacitance may be required under extreme temperature and/or capacitor bias voltage conditions due to variation of actual capacitance over bias voltage and temperature.
Rev. A
8
For more information www.analog.com
LTM4657
OPERATION
The LTM4657 is a standalone nonisolated switch mode
DC/DC power supply. It can deliver up to 8A DC output
current with few external input and output capacitors.
This module provides precisely regulated output voltage
adjustable between 0.5V to 5.5V via one external resistor
over a 3.1V to 20V input voltage range. The typical appli-
cation schematic is shown in Figure 23.
Furthermore, in order to protect the internal power
MOSFET devices against transient voltage spikes, the
LTM4657 constantly monitors the VIN pin for an over-
voltage condition. When V rises above 24.5V, the reg-
IN
ulator suspends operation by shutting off both power
MOSFETs. Once VIN drops below 21.5V, the regulator
immediately resumes normal operation. The regulator
does not execute its soft-start function when exiting an
overvoltage condition.
The LTM4657 contains an integrated constant on-time
valley current mode regulator, power MOSFETs, inductor,
and other supporting discrete components. The default
switching frequency is 500kHz. For switching noise-sensi-
tive applications, the switching frequency can be adjusted
by external resistors and the μModule regulator can be
externally synchronized to a clock within 30ꢀ of the set
frequency. See the Applications Information section.
Multiphase operation can be easily employed with the
synchronization and phase mode controls. Up to 6 phases
can be cascaded to run simultaneously with respect to
each other by programming the PHMODE pin to different
levels. The LTM4657 has MODE/CLKIN and CLKOUT pins
for PolyPhase operation of multiple devices or frequency
synchronization.
With current mode control and internal feedback loop
compensation, the LTM4657 module has sufficient sta-
bility margins and good transient performance with a
wide range of output capacitors, even with all ceramic
output capacitors.
Pulling the RUN pin to GND forces the controller into its
shutdown state, turning off both power MOSFETs and
most of the internal control circuitry. At light load currents,
discontinuous mode (DCM) operation can be enabled to
achieve higher efficiency compared to continuous mode
(CCM) by pulling the MODE/CLKIN pin to GND. The
TRACK/SS pin is used for power supply tracking
and soft-start programming. See the Applications
Information section.
Current mode control provides cycle-by-cycle fast current
limiting. Internal output overvoltage and undervoltage
comparators pull the open-drain PGOOD output low if the
output feedback voltage exits a 8ꢀ window around the
regulation point. Continuous operation is forced during
OV and UV condition except during start-up when the
TRACK pin is ramping up to 0.5V.
Rev. A
9
For more information www.analog.com
LTM4657
APPLICATIONS INFORMATION
The typical LTM4657 application circuit is shown in
Figure 23. External component selection is primarily deter-
mined by the input voltage, the output voltage and the
maximum load current. Refer to Table 7 for specific exter-
nal capacitor requirements for a particular application.
shown in Figure 2, thus tying one of the internal 60.4k
resistors to the output. All of the VFB pins tie together with
one programming resistor as shown in Figure 2.
See Figure 25 for an example of parallel operation.
ꢇꢈꢉꢊ
ꢌ
ꢋ.ꢂꢌꢍꢋꢁA
ꢈꢎꢏ
ꢒ
V to V
Step-Down Ratios
ꢕꢏꢉꢀꢁꢂꢃ
IN
OUT
ꢌ
ꢌ
ꢌ
ꢈꢐꢑꢐ
There are restrictions in the maximum V and V
step-
OUT
down ratios that can be achieved for a giIvNen input voltage
due to the minimum off-time and minimum on-time limits
of the regulator. The minimum off-time limit imposes a
maximum duty cycle which can be calculated as:
ꢌ
ꢄꢔ
ꢓ
ꢏRAꢇꢖꢍꢐꢐ
ꢇꢈꢉꢊ
ꢈꢐꢑꢐ
ꢌ
ꢈꢎꢏ
ꢕꢏꢉꢀꢁꢂꢃ
D
MAX
= 1 – (t
• f
)
ꢒ
OFF(MIN) SW
ꢈꢐꢑꢐ
where tOFF(MIN) is the minimum off-time, typically 50ns
for LTM4657, and fSW (Hz) is the switching frequency.
Conversely the minimum on-time limit imposes a minimum
duty cycle of the converter which can be calculated as:
ꢌ
ꢄꢔ
R
ꢄꢔ
ꢘꢅ.ꢋꢙ
ꢏRAꢇꢖꢍꢐꢐ
ꢓ
ꢌ
ꢅ.ꢋꢗꢄ
ꢈꢐꢑꢐ
ꢀꢁꢂꢃ ꢄꢅꢆ
D
= t
• f
ON(MIN) SW
MIN
Figure 2. 2-Phase Parallel Configurations
where t
is the minimum on-time, typically 25ns
ON(MIN)
Input Decoupling Capacitors
for LTM4657. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain
in regulation, but the switching frequency will decrease
from its programmed value. Note that additional thermal
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet.
The LTM4657 module should be connected to a low AC
impedance DC source. For the regulator, a 10µF input
ceramic capacitor is required for RMS ripple current
decoupling. Bulk input capacitance is only needed when
the input source impedance is compromised by long
inductive leads, traces or not enough source capacitance.
The bulk capacitor can be an aluminum electrolytic capac-
itor or polymer capacitor.
Output Voltage Programming
The PWM controller has an internal 0.5V reference
voltage. As shown in the Block Diagram, a 60.4k internal
Without considering the inductor ripple current, the RMS
current of the input capacitor can be estimated as:
feedback resistor connects the V
and FB pins together.
Adding a resistor, R , from FB OpUinT to V
programs
–
FB
OSNS
IOUT(MAX)
the output voltage:
ICIN(RMS)
=
• D• 1–D
( )
η%
0.5V
RFB =
•60.4k
VOUT –0.5V
where ηꢀ is the estimated efficiency of the power module.
Table 1. RFB Resistor Table vs Various Output Voltages
Output Decoupling Capacitors
V
OUT
(V) 0.5
1.0
1.2
1.5
1.8
2.5
3.3
5.0
With an optimized high frequency, high bandwidth design,
only a single low ESR output ceramic capacitor is required
for the LTM4657 to achieve low output ripple voltage and
very good transient response. In extreme cold or hot tem-
R
(kΩ) OPEN 60.4 43.2 30.1 23.2
15
10.7 6.65
FB
For parallel operation of multiple channels the same feed-
back setting resistor can be used for the parallel design.
+
This is done by connecting the V
to the output as
OSNS
perature or high output voltage case, additional ceramic
Rev. A
10
For more information www.analog.com
LTM4657
APPLICATIONS INFORMATION
capacitor or tantalum-polymer capacitor is required due
to variation of actual capacitance over bias voltage and
temperature. Table 7 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 2A load-step transient.
Additional output filtering may be required by the sys-
tem designer if further reduction of output ripple or
dynamic transient spikes is required. The Analog Devices
LTpowerCAD™ design tool is available to download online
for output ripple, stability and transient response analysis
for further optimization.
by adding a resistor, R
, between the FREQ pin and
FSET
GND, as shown in Figure 24. The operating frequency
can be calculated as:
1.67•1011
f Hz =
(
)
332k||R
Ω
FSET ( )
The programmable operating frequency range is from
400kHz to 3MHz.
Frequency Synchronization and Clock In
The power module has a phase-locked loop comprised of
an internal voltage controlled oscillator and a phase detec-
tor. This allows the internal top MOSFET turn-on to be
locked to the rising edge of the external clock. The exter-
nal clock frequency range must be within 30ꢀ around
the resistor set operating frequency. A pulse detection
circuit is used to detect a clock on the CLKIN pin to turn
on the phase-locked loop. The pulse width of the clock has
to be at least 100ns. The clock high level must be above
1V and clock low level below 0.3V. During the start-up of
the regulator, the phase-locked loop function is disabled.
Discontinuous Current Mode (DCM)
In applications where low output ripple and high efficiency
at intermediate current are desired, discontinuous current
mode (DCM) should be used by connecting the MODE/
CLKIN pin to GND. At light loads the internal current com-
parator may remain tripped for several cycles and force the
top MOSFET to stay off for several cycles, thus skipping
cycles. The inductor current does not reverse in this mode.
Forced Continuous Current Mode (CCM)
In applications where fixed frequency operation is more
critical than low current efficiency, and where the low-
est output ripple is desired, forced continuous opera-
tion should be used. Forced continuous operation can
Multiphase Operation
For output loads that demand more than 8A of current,
multiple LTM4657s can be paralleled to run out of phase
to provide more output current without increasing input
and output voltage ripples.
be enabled by tying the MODE/CLKIN pin to INTV . In
CC
this mode, inductor current is allowed to reverse during
low output loads, the COMP voltage is in control of the
current comparator threshold throughout, and the top
MOSFET always turns on with each oscillator pulse.
During start-up, forced continuous mode is disabled and
inductor current is prevented from reversing until the
LTM4657’s output voltage is in regulation.
The CLKOUT signal can be connected to the MODE/CLKIN
pin of the following LTM4657 stage to line up both the
frequency and the phase of the entire system. Tying the
PHMODE pin to INTV , GND or FLOAT generates a phase
CC
difference (between CLKIN and CLKOUT) of 180°, 120°, or
90° respectively, which corresponds to 2-phase, 3-phase
or 4-phase operation. A total of 6 phases can be cascaded
to run simultaneously out of phase with respect to each
other by programming the PHMODE pin of each LTM4657
to different levels. Figure 3 shows a 4-phase design and
a 6-phase design example for clock phasing.
Operating Frequency
The operating frequency of the LTM4657 is optimized
to achieve the compact package size and the minimum
output ripple voltage while still keeping high efficiency.
The default operating frequency is 500kHz. In most appli-
cations, no additional frequency adjustment is required.
Table 2. PHMODE Pin Status and Corresponding Phase
Relationship (Relative to CLKIN)
PHMODE
INTV
GND
FLOAT
CC
If an operating frequency other than 500kHz is required by
the application, the operating frequency can be increased
CLKOUT
180°
120°
90°
Rev. A
11
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LTM4657
APPLICATIONS INFORMATION
ꢅ
ꢔꢅ
ꢕꢖꢅ
ꢗꢃꢅ
ꢘꢔꢅ
ꢘꢔꢅ
ꢘꢔꢅ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢕ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢗ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢆ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢀ
ꢚꢀꢗꢅꢛ
ꢁꢅ
ꢅ
ꢕꢗꢅ
ꢗꢀꢅ
ꢕꢖꢅ
ꢆꢅꢅ
ꢘꢕꢗꢅ
ꢘꢕꢗꢅ
ꢘꢕꢖꢅ
ꢘꢕꢗꢅ
ꢘꢕꢗꢅ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢇꢈꢉꢊꢋ ꢇꢈꢉꢏꢒꢓ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢕ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢆ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢂ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢗ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢀ
ꢌꢍꢎꢏꢐꢑ
ꢌꢍAꢙꢑ ꢁ
ꢊꢋꢓꢜ
ꢊꢋꢓꢜ
ꢇꢇ
ꢇꢇ
ꢀꢁꢂꢃ ꢄꢅꢆ
Figure 3. 4-Phase, 6-Phase Operation
ꢀ.ꢅꢀ
ꢀ.ꢂꢂ
ꢀ.ꢂꢀ
ꢀ.ꢄꢂ
ꢀ.ꢄꢀ
ꢀ.ꢇꢂ
ꢀ.ꢇꢀ
ꢀ.ꢈꢂ
ꢀ.ꢈꢀ
ꢀ.ꢉꢂ
ꢀ.ꢉꢀ
ꢀ.ꢀꢂ
ꢉ ꢛꢜAꢚꢑ
ꢈ ꢛꢜAꢚꢑ
ꢇ ꢛꢜAꢚꢑ
ꢄ ꢛꢜAꢚꢑ
ꢅ ꢛꢜAꢚꢑ
ꢀ
ꢀ.ꢉ ꢀ.ꢉꢂ ꢀ.ꢈ ꢀ.ꢈꢂ ꢀ.ꢇ ꢀ.ꢇꢂ ꢀ.ꢄ ꢀ.ꢄꢂ ꢀ.ꢂ ꢀ.ꢂꢂ ꢀ.ꢅ ꢀ.ꢅꢂ ꢀ.ꢁ ꢀ.ꢁꢂ ꢀ.ꢃ ꢀ.ꢃꢂ ꢀ.ꢊ
ꢋꢌꢍꢎ ꢏꢎꢏꢐꢑ ꢒꢓ ꢕꢓ
ꢘ
ꢔꢌꢍ ꢖꢗ
ꢄꢅꢂꢁ ꢆꢀꢄ
Figure 4. RMS Input Ripple Current to DC Load Current Ratio as a Function of Duty Cycle
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input voltage is
greater than the number of phases used times the output
voltage). The output ripple amplitude is also reduced by
the number of phases used when all of the outputs are tied
together to achieve a single high output current design.
The LTM4657 device is an inherently current mode con-
trolled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Please tie the RUN, TRACK/SS, FB and COMP pins
of each paralleling channel together. Figure 25 shows an
example of parallel operation and pin connection.
Rev. A
12
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LTM4657
APPLICATIONS INFORMATION
Input RMS Ripple Current Cancellation
0.5V, it will take over the internal 0.5V reference voltage
to control the output voltage. The total soft-start time can
be calculated as:
Application Note 77 provides a detailed explanation of mul-
tiphase operation. The input RMS ripple current cancella-
tion mathematical derivations are presented, and a graph
is displayed representing the RMS ripple current reduc-
tion as a function of the number of interleaved phases.
Figure 4 shows this graph.
CSS
tSS =0.5•
6µA
where C is the capacitance on the TRACK/SS pin. Cur-
SS
rent foldback and forced continuous mode are disabled
Soft-Start And Output Voltage Tracking
during the soft-start process.
The TRACK/SS pin provides a means to either soft start
the regulator or track it to a different power supply. A
capacitor on the TRACK/SS pin will program the ramp
rate of the output voltage. An internal 6µA current source
will charge up the external soft-start capacitor towards
Output voltage tracking can also be programmed exter-
nally using the TRACK/SS pin. The output can be tracked
up and down with another regulator. Figure 5 and Figure 6
show an example waveform and schematic of ratiometric
tracking where the slave regulator’s output slew rate is
proportional to the master’s.
INTV voltage. When the TRACK/SS voltage is below
CC
ꢂAꢄꢀꢃR ꢇꢈꢀꢉꢈꢀ
ꢄꢅAꢆꢃ ꢇꢈꢀꢉꢈꢀ
ꢀꢁꢂꢃ
ꢋꢌꢍꢎ ꢏꢐꢍ
Figure 5. Output Ratiometric Tracking Waveform
ꢃ
ꢄꢅ
ꢘ.ꢚꢃ ꢇꢊ ꢡꢙꢃ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢃ
ꢚ.ꢟꢃ
ꢣA
ꢃ
ꢚ.ꢙꢃ
ꢣA
ꢊꢆꢇꢖꢉAꢗ
ꢊꢆꢇꢖꢎꢜꢗ
ꢃ
ꢃ
ꢃ
ꢃ
ꢄꢅ
ꢊꢆꢇ
ꢑ
ꢄꢅ
ꢊꢆꢇ
ꢚꢙꢙꢢꢀ
ꢞ.ꢘꢃ
ꢤꢡ
ꢚꢙꢙꢢꢀ
ꢞ.ꢘꢃ
ꢤꢡ
ꢡꢡꢢꢀ
ꢡꢟꢃ
ꢡꢡꢢꢀ
ꢡꢟꢃ
ꢜꢇꢉꢝꢞꢟꢠ
ꢜꢇꢉꢝꢞꢟꢠ
ꢑ
ꢃ
ꢃ
Rꢆꢅ
ꢄꢅꢇꢃ
Rꢆꢅ
ꢄꢅꢇꢃ
ꢉꢊꢋꢁ
ꢊꢎꢅꢎ
ꢊꢎꢅꢎ
ꢈꢈ
ꢈꢈ
R
ꢇRꢖꢇꢊꢏꢗ
ꢞꢙ.ꢝꢛ
ꢉꢊꢋꢁ
ꢀꢒ
ꢀꢒ
ꢇRAꢈꢌꢍꢎꢎ
ꢏꢐꢊꢊꢋ
ꢇRAꢈꢌꢍꢎꢎ
ꢏꢐꢊꢊꢋ
ꢈꢊꢉꢏꢓ
ꢈꢊꢉꢏꢓ
R
R
ꢀꢒꢖꢎꢜꢗ
ꢞꢙ.ꢝꢛ
ꢀꢒꢖꢉAꢗ
R
ꢈꢊꢉꢏꢔ
ꢕ
ꢈꢊꢉꢏꢔ
ꢕ
ꢇRꢖꢒꢊꢇꢗ
ꢘꢙ.ꢚꢛ
ꢘꢙ.ꢚꢛ
ꢐꢅꢋ
ꢃ
ꢐꢅꢋ
ꢃ
ꢊꢎꢅꢎ
ꢊꢎꢅꢎ
ꢝꢞꢟꢠ ꢀꢙꢞ
Figure 6. Example Schematic of Ratiometric Output Voltage Tracking
Rev. A
13
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LTM4657
APPLICATIONS INFORMATION
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a R
/R
resistor
TR(TOP) TR(BOT)
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.5V, the slave
output voltage and the master output voltage should sat-
isfy the following equation during start-up:
ꢂAꢄꢀꢃR ꢅꢆꢀꢇꢆꢀ
ꢄꢈAꢉꢃ ꢅꢆꢀꢇꢆꢀ
RFB(SL)
VOUT(SL)
•
=
RFB(SL) +60.4k
RTR(BOT)
VOUT(MA)
•
ꢀꢁꢂꢃ
RTR(TOP) +RTR(BOT)
ꢋꢌꢍꢎ ꢏꢐꢎ
Figure 7. Output Coincident Tracking Waveform
The RFB(SL) is the feedback resistor and the RTR(TOP)
TR(BOT)
the slave regulator, as shown in Figure 6.
/
R
is the resistor divider on the TRACK/SS pin of
From the equation, we could easily find that, in coinci-
dent tracking, the slave regulator’s TRACK/SS pin resistor
divider is always the same as its feedback divider:
Following the previous equation, the ratio of the master’s
output slew rate (MR) to the slave’s output slew rate (SR)
is determined by:
RFB(SL)
RTR(BOT)
=
RFB(SL)
RFB(SL) +60.4k RTR(TOP) +RTR(BOT)
60.4k+RFB(SL)
RTR(BOT)
MR
SR
=
For example, R
= 60.4k and R
= 60.4k is a
TR(TOP)
TR(BOT)
good combination for coincident tracking for a V
OUT(MA)
RTR(TOP) +RTR(BOT)
= 1.5V and V
= 1.0V application.
OUT(SL)
For example, VOUT(MA)=1.5V, MR = 1.5V/1ms and VOUT(SL)
= 1.0V, SR = 1.0V/1ms. From the equation, we could solve
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin is pulled
low when the output voltage exceeds a 8ꢀ window
around the regulation point. To prevent unwanted PGOOD
glitches during transients or dynamic V
LTM4657’s PGOOD falling edge includes a blanking delay
of approximately 25 switching cycles.
that R
= 60.4k and R
= 30.1k are a good
TR(TOP)
TR(BOT)
combination for the ratiometric tracking.
The TRACK/SS pin will have the 2µA current source on
when a resistive divider is used to implement tracking
on the slave regulator. This will impose an offset on the
TRACK/SS pin input. Smaller value resistors with the
same ratios as the resistor values calculated from the
above equation can be used. For example, where the 60.4k
is used then a 6.04k can be used to reduce the TRACK/SS
pin offset to a negligible value.
changes, the
OUT
RUN Enable
Pulling the RUN pin to ground forces the LTM4657 into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Bringing the RUN pin
above 0.6V turns on the internal reference only, while still
keeping the power MOSFETs off. Increasing the RUN pin
voltage above 1.2V will turn on the entire chip.
Coincident output tracking can be recognized as a special
ratiometric output tracking in which the master’s output
slew rate (MR) is the same as the slave’s output slew rate
(SR), waveform as shown in Figure 7.
Rev. A
14
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LTM4657
APPLICATIONS INFORMATION
Pre-Biased Output Start-Up
Stability Compensation
There may be situations that require the power supply to
start up with some charge on the output capacitors. The
LTM4657 can safely power up into a pre-biased output
without discharging it.
The LTM4657 has already been internally optimized and
compensated for all output voltages and capacitor combi-
nations including all ceramic capacitor applications when
COMPb is tied to COMPa. Please note that a 22pF to
47pF feedforward capacitor (C ) is required connecting
FF
The LTM4657 accomplishes this by forcing discontinuous
mode (DCM) operation until the TRACK/SS pin voltage
reaches 0.5V reference voltage. This will prevent the BG
from turning on during the pre-biased output start-up
which would discharge the output.
from V
to V pin for all ceramic capacitor application
to achiOeUvTe high bandwidth control loop compensation
with enough phase margin. Table 7 is provided for most
application requirements using the optimized internal
compensation. For specific optimized requirement, dis-
connect COMPb from COMPa and apply a Type II C-R-C
compensation network from COMPa to GND to achieve
external compensation. The LTpowerCAD design tool is
available to download online to perform specific control
loop optimization and analyze the control stability and
load transient performance.
FB
SW Pins and Snubbering Circuit
The SW pin is generally for testing purposes by moni-
toring the pin. The SW pin can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current path. Usually a series R-C combination
is used called a snubber circuit. The resistor will dampen
the resonance and the capacitor is chosen to only affect
the high frequency ringing across the resistor.
Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is built into
the LTM4657 to sense output voltages accurately at the
remote load points. This is especially true for high current
If the stray inductance or capacitance can be measured
or approximated then a somewhat analytical technique
can be used to select the snubber values. The inductance
is usually easier to predict. It combines the power path
board inductance in combination with the MOSFET inter-
connect bond wire inductance.
+
–
loads. It is very important that the V
and V
are
OSNS
OSNS
connected properly at the remote output sense point, and
the feedback resistor R is connected to between V
pin to VOSNS pin. Review the schematics in Figure 23
for reference.
FB
FB
–
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre-
quency can be measured for its value. The impedance Z
can be calculated:
In multiphase single output application. Only one set of
differential sensing amplifier and one set of feedback
resistor are required while connecting RUN, TRACK/SS,
V
, V and COMPa of different channels together. See
Z = 2π • f • L
L
OUT FB
Figure 25 for paralleling application.
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by:
Input Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTM4657 constantly
monitors each VIN pin for an overvoltage condition. When
V rises above 24.5V, the regulator suspends operation
IN
1
ZC =
by shutting off both power MOSFETs on the correspond-
2π •f•C
ing channel. Once V drops below 21.5V, the regulator
IN
immediately resumes normal operation. The regulator
These values are a good place to start. Modification to
these components should be made to attenuate the ring-
ing with the least amount the power loss.
executes its soft-start function when exiting an overvolt-
age condition.
Rev. A
15
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LTM4657
APPLICATIONS INFORMATION
Temperature Monitoring
relationship (Figure 8), which is at odds with the equation.
In fact, the IS term increases with temperature, reduc-
Measuring the absolute temperature of a diode is possible
due to the relationship between current, voltage and tem-
perature described by the classic diode equation:
ing the ln(I /I ) absolute value yielding an approximate
D S
–2mV/°C composite diode voltage slope.
ꢋ.ꢔ
ꢋ.ꢕ
ꢋ.ꢗ
ꢋ.ꢊ
ꢋ.ꢖ
ꢋ.ꢍ
⎛
⎞
VD
η•V
ID =IS •e
⎜
⎟
⎝
⎠
T
or
I
IS
VD = η•VT •In D
where I is the diode current, V is the diode voltage, η
D
D
is the ideal factor (typically close to 1.0) and I (satura-
S
ꢉꢊꢋ ꢉꢌꢊ
ꢋ
ꢌꢊ
ꢊꢋ
ꢕꢊ ꢘꢋꢋ ꢘꢌꢊ
tion current) is a process dependent parameter. V can
T
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢖꢗꢌꢗ ꢙꢋꢔ
be broken out to:
Figure 8. Diode Voltage VD vs Temperature T(°C)
k •T
VT =
q
To obtain a linear voltage proportional to temperature we
cancel the IS variable in the natural logarithm term to
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. V is
remove the I dependency from the equation 1. This is
S
T
accomplished by measuring the diode voltage at two cur-
rents I1, and I2, where I1 = 10 • I2) and subtracting we get:
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable tem-
I
I
2
1
∆VD = T(KELVIN)•K •IN –T(KELVIN)•K •IN
D
D
perature sensors. The I term in the previous equation is
S
I
I
S
S
the extrapolated current through a diode junction when
Combining like terms, then simplifying the natural log
terms yields:
the diode has zero volts across the terminals. The I term
S
varies from process to process, varies with temperature,
and by definition must always be less than I . Combining
D
ΔV = T(KELVIN) • K • lN(10)
D
D
all of the constants into one term:
and redefining constant
η•k
KD =
q
198µV
K' =K •IN(10) =
D
D
K
−5
where K = 8.62 , and knowing ln(I /I ) is always pos-
D
D S
yields
itive because I is always greater than I , leaves us with
D
S
the equation that:
ΔV = K’ • T(KELVIN)
D
D
I
IS
Solving for temperature:
V = T KELVIN •K •In D
(
)
D
D
∆VD
T(KELVIN)=
(°CELSIUS)= T(KELVIN)–273.15
K'
D
where VD appears to increase with temperature. It is
common knowledge that a silicon diode biased with a
current source has an approximate –2mV/°C temperature
where
300°K = 27°C
Rev. A
16
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LTM4657
APPLICATIONS INFORMATION
means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198μV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
2. θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule reg-
ulator, the bulk of the heat flows out the bottom of
the package, but there is always heat flow out into the
ambient environment. As a result, this thermal resis-
tance value may be useful for comparing packages,
but the test conditions don’t generally match the user’s
application.
+
The diode connected NPN transistor across the T
SENSE
−
pin and T
pin can be used to monitor the internal
SENSE
temperature of the LTM4657.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD 51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients
is found in JESD 51-12 (Guidelines for Reporting and
Using Electronic Package Thermal Information).
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the typ-
ical µModule regulator are on the bottom of the pack-
age, it is rare for an application to operate such that
most of the heat flows from the junction to the top of
the part. As in the case of θ
useful for comparing packages but the test conditions
don’t generally match the user’s application.
, this value may be
JCbottom
Many designers may opt to use laboratory equipment and
a test vehicle such as the demo board to anticipate the
µModule regulator’s thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are, in and of themselves, not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in this data sheet can
be used in a manner that yields insight and guidance per-
taining to one’s application usage, and can be adapted to
correlate thermal performance to one’s own application.
4. θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resis-
tance where almost all of the heat flows through the
bottom of the µModule package and into the board,
and is really the sum of the θ
and the thermal
JCbottom
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from the
package.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 9; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule package.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
Rev. A
17
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LTM4657
APPLICATIONS INFORMATION
FEA software is used to accurately build the mechanical
geometry of the LTM4657 and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JESD51-12 to predict power loss heat flow and tempera-
ture readings at different interfaces that enable the cal-
culation of the JEDEC-defined thermal resistance values;
(3) the model and FEA software is used to evaluate the
LTM4657 with heat sink and airflow; (4) having solved
for and analyzed these thermal resistance values and
simulated various operating conditions in the software
model, a thorough laboratory evaluation replicates the
simulated conditions with thermocouples within a con-
trolled environment chamber while operating the device
at the same power loss as that which was simulated. An
outcome of this process and due diligence yields the set
of derating curves shown in this data sheet. After these
laboratory tests have been performed and correlated to
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule regulator. For example,
in normal board-mounted applications, never does 100ꢀ
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
for θ
and θ , respectively. In practice, power
JCbottom
JCtop
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4657 be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to differ-
ent junctions of components or die are not exactly linear
with respect to total package power loss. To reconcile
this complication without sacrificing modeling sim-
plicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
the LTM4657 model, then the θ and θ are summed
JB
BA
together to provide a value that should closely equal the
θJA value because approximately 100ꢀ of power loss
flows from the junction through the board into ambient
with no airflow or top mounted heat sink.
ꢇꢈꢉꢊꢋꢌe ꢍꢎꢏꢐꢑꢎ
θ
ꢒꢕꢖꢑꢗꢐꢘꢖꢙꢗꢘꢙAꢈꢞꢐꢎꢖꢗ RꢎꢚꢐꢚꢗAꢖꢑꢎ
ꢒA
θ ꢒꢕꢖꢑꢗꢐꢘꢖꢙꢗꢘꢙꢑAꢚꢎ
ꢒꢑꢓꢉꢔ
ꢛꢗꢘꢜꢝ RꢎꢚꢐꢚꢗAꢖꢑꢎ
ꢑAꢚꢎ ꢛꢗꢘꢜꢝꢙꢗꢘꢙAꢈꢞꢐꢎꢖꢗ
RꢎꢚꢐꢚꢗAꢖꢑꢎ
ꢒꢕꢖꢑꢗꢐꢘꢖ
Aꢈꢞꢐꢎꢖꢗ
θ ꢒꢕꢖꢑꢗꢐꢘꢖꢙꢗꢘꢙꢑAꢚꢎ
ꢒꢑꢟꢉꢓ
ꢛꢞꢘꢗꢗꢘꢈꢝ RꢎꢚꢐꢚꢗAꢖꢑꢎ
ꢑAꢚꢎ ꢛꢞꢘꢗꢗꢘꢈꢝꢙꢗꢘꢙꢞꢘARꢍ
RꢎꢚꢐꢚꢗAꢖꢑꢎ
ꢞꢘARꢍꢙꢗꢘꢙAꢈꢞꢐꢎꢖꢗ
RꢎꢚꢐꢚꢗAꢖꢑꢎ
ꢀꢁꢂꢃ ꢄꢅꢆ
Figure 9. Graphical Approximation of the Thermal Coefficients, Including JESD 51-12 Terms
Rev. A
18
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LTM4657
APPLICATIONS INFORMATION
ꢎ.ꢏ
ꢎ.ꢋ
ꢋ.ꢏ
ꢋ
ꢎ.ꢏ
ꢎ.ꢋ
ꢋ.ꢏ
ꢋ
ꢎ.ꢏ
ꢎ.ꢋ
ꢐ.ꢏ
ꢐ.ꢋ
ꢋ.ꢏ
ꢋ
ꢒ.ꢒꢗ ꢙ ꢎꢗ ꢙ ꢏꢋꢋꢚꢛꢜ
ꢒ.ꢒꢗ ꢙ ꢎ.ꢏꢗ ꢙ ꢓꢏꢋꢚꢛꢜ
ꢏꢗ ꢙ ꢒ.ꢒꢗ ꢙ ꢐꢋꢋꢋꢚꢛꢜ
ꢘꢈ ꢀꢁꢂ
ꢐꢎꢗ ꢙ ꢒ.ꢒꢗ ꢙ ꢐꢋꢋꢋꢚꢛꢜ
ꢘꢈ ꢀꢁꢂ
ꢘꢈ
ꢀꢁꢂ
ꢘꢈ
ꢀꢁꢂ
ꢏꢗ ꢙ ꢎꢗ ꢙ ꢏꢋꢋꢚꢛꢜ
ꢏꢗ ꢙ ꢎ.ꢏꢗ ꢙ ꢓꢏꢋꢚꢛꢜ
ꢘꢈ
ꢀꢁꢂ
ꢘꢈ
ꢀꢁꢂ
ꢎꢐꢗ ꢙ ꢎꢗ ꢙ ꢏꢋꢋꢚꢛꢜ
ꢎꢐꢗ ꢙ ꢎ.ꢏꢗ ꢙ ꢓꢏꢋꢚꢛꢜ
ꢘꢈ ꢀꢁꢂ
ꢘꢈ
ꢀꢁꢂ
ꢋ
ꢎ
ꢐ
ꢒ
ꢑ
ꢏ
ꢓ
ꢔ
ꢖ
ꢋ
ꢎ
ꢐ
ꢒ
ꢑ
ꢏ
ꢓ
ꢔ
ꢖ
ꢋ
ꢐ
ꢎ
ꢒ
ꢑ
ꢏ
ꢓ
ꢔ
ꢖ
ꢀꢁꢂꢃꢁꢂ ꢄꢀAꢅ ꢆꢁRRꢇꢈꢂ ꢉAꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢀAꢅ ꢆꢁRRꢇꢈꢂ ꢉAꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢀAꢅ ꢆꢁRRꢇꢈꢂ ꢉAꢊ
ꢑꢓꢏꢔ ꢕꢎꢋ
ꢑꢓꢏꢔ ꢕꢎꢎ
ꢑꢓꢏꢔ ꢕꢐꢎ
Figure 10. Power Loss at 1V Output
Figure 11. Power Loss at 1.5V Output
Figure 12. Power Loss at 3.3V Output
ꢎ.ꢏ
ꢎ.ꢋ
ꢐ.ꢏ
ꢐ.ꢋ
ꢋ.ꢏ
ꢋ
ꢌ
ꢌ
ꢐꢎꢗ ꢙ ꢏꢗ ꢙ ꢐꢎꢏꢋꢚꢛꢜ
ꢅꢆꢕꢖ
ꢐꢅꢅꢆꢕꢖ
ꢏꢅꢅꢆꢕꢖ
ꢅꢆꢕꢖ
ꢐꢅꢅꢆꢕꢖ
ꢏꢅꢅꢆꢕꢖ
ꢘꢈ
ꢀꢁꢂ
ꢍ
ꢑ
ꢎ
ꢒ
ꢏ
ꢓ
ꢐ
ꢔ
ꢅ
ꢍ
ꢑ
ꢎ
ꢒ
ꢏ
ꢓ
ꢐ
ꢔ
ꢅ
ꢋ
ꢐ
ꢎ
ꢒ
ꢑ
ꢏ
ꢓ
ꢔ
ꢖ
ꢅ
ꢐꢅ
ꢏꢅ
ꢎꢅ
ꢁꢂꢃꢄ
ꢍꢅ
ꢔꢅꢅ
ꢔꢐꢅ
ꢅ
ꢐꢅ
ꢏꢅ
ꢎꢅ
ꢁꢂꢃꢄ
ꢍꢅ
ꢔꢅꢅ
ꢔꢐꢅ
ꢀꢁꢂꢃꢁꢂ ꢄꢀAꢅ ꢆꢁRRꢇꢈꢂ ꢉAꢊ
ꢀ
ꢀ
A
A
ꢑꢓꢏꢔ ꢕꢐꢒ
ꢏꢎꢒꢑ ꢕꢔꢏ
ꢏꢎꢒꢑ ꢕꢔꢒ
Figure 15. 12V to 1V Derating
Curve, No Heat Sink
Figure 14. 5V to 1V Derating Curve,
No Heat Sink
Figure 13. Power Loss at 5V Output
ꢌ
ꢌ
ꢅꢆꢕꢖ
ꢅꢆꢕꢖ
ꢍ
ꢑ
ꢎ
ꢒ
ꢏ
ꢓ
ꢐ
ꢔ
ꢅ
ꢍ
ꢑ
ꢎ
ꢒ
ꢏ
ꢓ
ꢐ
ꢔ
ꢅ
ꢐꢅꢅꢆꢕꢖ
ꢏꢅꢅꢆꢕꢖ
ꢐꢅꢅꢆꢕꢖ
ꢏꢅꢅꢆꢕꢖ
ꢅ
ꢐꢅ
ꢏꢅ
ꢎꢅ
ꢁꢂꢃꢄ
ꢍꢅ
ꢔꢅꢅ
ꢔꢐꢅ
ꢅ
ꢐꢅ
ꢏꢅ
ꢎꢅ
ꢁꢂꢃꢄ
ꢍꢅ
ꢔꢅꢅ
ꢔꢐꢅ
ꢀ
ꢀ
A
A
ꢏꢎꢒꢑ ꢕꢔꢎ
ꢏꢎꢒꢑ ꢕꢔꢑ
Figure 16. 5V to 1.5V
Derating Curve, No Heat Sink
Figure 17. 12V to 1.5V Derating
Curve, No Heat Sink
Rev. A
19
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LTM4657
APPLICATIONS INFORMATION
ꢌ
ꢍ
ꢑ
ꢎ
ꢒ
ꢏ
ꢓ
ꢐ
ꢔ
ꢅ
ꢌ
ꢍ
ꢑ
ꢎ
ꢒ
ꢏ
ꢓ
ꢐ
ꢔ
ꢅ
ꢌ
ꢍ
ꢑ
ꢎ
ꢒ
ꢏ
ꢓ
ꢐ
ꢔ
ꢅ
ꢅꢆꢕꢖ
ꢐꢅꢅꢆꢕꢖ
ꢏꢅꢅꢆꢕꢖ
ꢅꢆꢕꢖ
ꢐꢅꢅꢆꢕꢖ
ꢏꢅꢅꢆꢕꢖ
ꢅꢆꢕꢖ
ꢐꢅꢅꢆꢕꢖ
ꢏꢅꢅꢆꢕꢖ
ꢅ
ꢐꢅ
ꢏꢅ
ꢎꢅ
ꢁꢂꢃꢄ
ꢍꢅ
ꢔꢅꢅ
ꢔꢐꢅ
ꢅ
ꢐꢅ
ꢏꢅ
ꢎꢅ
ꢁꢂꢃꢄ
ꢍꢅ
ꢔꢅꢅ
ꢔꢐꢅ
ꢅ
ꢐꢅ
ꢏꢅ
ꢎꢅ
ꢁꢂꢃꢄ
ꢍꢅ
ꢔꢅꢅ
ꢔꢐꢅ
ꢀ
ꢀ
ꢀ
A
A
A
ꢏꢎꢒꢑ ꢕꢔꢍ
ꢏꢎꢒꢑ ꢕꢔꢌ
ꢏꢎꢒꢑ ꢕꢐꢅ
Figure 18. 5V to 3.3V Derating
Curve, No Heat Sink
Figure 19. 12V to 3.3V Derating
Curve, No Heat Sink
Figure 20. 12V to 5V Derating
Curve, No Heat Sink
Table 3. 1.0V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 10
AIR FLOW (LFM)
HEAT SINK
None
θ
θ
θ
θ
IN
JA(°C/W)
Figure 14, Figure 15
Figure 14, Figure 15
Figure 14, Figure 15
5, 12
5, 12
5, 12
0
17
Figure 10
200
400
None
14.5
13.5
Figure 10
None
Table 4. 1.5V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 11
AIR FLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
Figure 16, Figure 17
Figure 16, Figure 17
Figure 16, Figure 17
5, 12
0
17
5, 12
5, 12
Figure 11
200
400
None
14.5
13.5
Figure 11
None
Table 5. 3.3V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 12
AIR FLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
Figure 18, Figure 19
Figure 18, Figure 19
Figure 18, Figure 19
5, 12
0
17
5, 12
5, 12
Figure 12
200
400
None
14.5
13.5
Figure 12
None
Table 6. 5V Output
DERATING CURVE
Figure 20
V
(V)
POWER LOSS CURVE
Figure 13
AIR FLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
12
0
17
Figure 20
12
12
Figure 13
200
400
None
14.5
13.5
Figure 20
Figure 13
None
Rev. A
20
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LTM4657
APPLICATIONS INFORMATION
The 1.0V, 1.5V, 3.3V and 5V power loss curves in
Figure 10 to 13 can be used in coordination with the load
current derating curves in Figure 14 to 20 for calculating
is subtracted from the 120°C junction temperature,
then the difference of 20°C divided by 1.2W equals a
16.8°C/W θJA thermal resistance. Table 4 specifies a
17°C/W value which is very close. Table 3, Table 4, Table 5
and Table 6 provide equivalent thermal resistances for
1.0V, 1.5V, 3.3V and 5V outputs with and without air-
flow and heat sinking. The derived thermal resistances
in Table 3, Table 4, Table 5 and Table 6 for the various
conditions can be multiplied by the calculated power loss
as a function of ambient temperature to derive tempera-
ture rise above ambient, thus maximum junction tem-
perature. Room temperature power loss can be derived
from the efficiency curves in the Typical Performance
Characteristics section and adjusted with the above ambi-
ent temperature multiplicative factors. The printed circuit
board is a 1.6mm thick 4-layer board with two ounce
copper for the two outer layers and one ounce copper
for the two inner layers. The PCB dimensions are 95mm
× 76mm. A Typical thermal image based on this PCB is
shown in Figure 21.
an approximate θ thermal resistance for the LTM4657
JA
with various airflow conditions. The power loss curves
are taken at room temperature, and are increased with a
multiplicative factor according to the ambient tempera-
ture. This approximate factor is: 1.2 for 120°C at junction
temperature. Maximum load current is achievable while
increasing ambient temperature as long as the junction
temperature is less than 120°C, which is a 5°C guard band
from maximum junction temperature of 125°C. When the
ambient temperature reaches a point where the junction
temperature is 120°C, then the load current is lowered to
maintain the junction at 120°C while increasing ambient
temperature up to 120°C. The derating curves are plotted
with the output current starting at 8A and the ambient
temperature at 30°C. The output voltages are 1.0V, 1.5V,
3.3V and 5V. These are chosen to include the lower and
higher output voltage ranges for correlating the thermal
resistance. Thermal models are derived from several
temperature measurements in a controlled temperature
chamber along with thermal modeling analysis. The junc-
tion temperatures are monitored while ambient tempera-
ture is increased with and without airflow. The power loss
increase with ambient temperature change is factored
into the derating curves. The junctions are maintained at
120°C maximum while lowering output current or power
with increasing ambient temperature. The decreased
output current will decrease the internal module loss as
ambient temperature is increased. The monitored junction
temperature of 120°C minus the ambient operating tem-
perature specifies how much module temperature rise can
be allowed. As an example, in Figure 17 the load current
is derated to ~5.5A at ~100°C with no air flow or heat sink
and the power loss for the 12V to 1.5V at 5.5A output is
about 1.2W. The 1.2W loss is calculated with the ~1W
room temperature loss from the 12V to 1.5V power loss
curve at 5.5A, and the 1.2 multiplying factor at 120°C
junction temperature. If the 100°C ambient temperature
Figure 21. Thermal Image of LTM4657 Running from 12V Input
and 1V Output at 8A Load at 25°C Ambient Without Airflow and
Heat Sink
Rev. A
21
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LTM4657
APPLICATIONS INFORMATION
Table 7. Output Voltage Response vs Component Matrix (Refer to Figure 23)
C
OUT1
PART NUMBER
VALUE
C
PART NUMBER
VALUE
OUT2
Murata
GRM31CR60J107M
100µF, 6.3V, 1206, X5R
Murata
GRM31CR71A226K
22µF, 10V, 1206, X7R
LOAD STEP
P-P
RECOVERY
TIME
V
V
f
C
C
C
FF
(pF)
LOAD STEP
(A)
IN
OUT
SW
OUT1
OUT2
COMPENSATION
SLEW RATE DEVIATION
(V)
(V)
(kHz) (CER CAP) (CER CAP)
(A/µs)
(mV)
(µs)
5
12
5
1
500
500
2× 100µF
2× 100µF
2× 100µF
2× 100µF
2× 100µF
2× 100µF
2× 100µF
2× 100µF
2× 100µF
22µF
22µF
22µF
22µF
22µF
22µF
22µF
22µF
22µF
Internal, COMPa = COMPb
Internal, COMPa = COMPb
Internal, COMPa = COMPb
Internal, COMPa = COMPb
Internal, COMPa = COMPb
Internal, COMPa = COMPb
Internal, COMPa = COMPb
Internal, COMPa = COMPb
Internal, COMPa = COMPb
100
100
100
100
100
100
100
100
100
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
2
2
2
2
2
2
2
2
2
62
30
30
30
30
30
30
50
50
50
1
65
1.5
1.5
2.5
2.5
3.3
3.3
5
650
59
12
5
650
67
800
75
12
5
800
82
1000
1000
1250
92
12
12
107
142
Safety Considerations
The LTM4657 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
• Do not put via directly on the pad, unless they are
capped or plated over.
• Bring out test points on the signal pins for monitoring.
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and over current protection.
• Keep separation between CLKIN, CLKOUT and FREQ
pin traces to minimize possibility of noise due to cross-
talk between these signals.
Figure22givesagoodexampleoftherecommendedlayout.
Layout Checklist/Example
The high integration of LTM4657 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
ꢀ
ꢃꢄꢅ
• Use large PCB copper areas for high current paths,
including V , GND and V . It helps to minimize the
IN
OUT
PCB conduction loss and thermal stress.
ꢀ
ꢁꢂ
• Place high frequency ceramic input and output capac-
itors next to the V , PGND and V
pins to minimize
IN
OUT
high frequency noise.
ꢌꢂꢍ
• Place a dedicated power ground layer underneath
the unit.
ꢆꢇꢈꢉ ꢊꢋꢋ
Figure 22. Recommended PCB Layout
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
Rev. A
22
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LTM4657
APPLICATIONS INFORMATION
ꢕRꢉꢖ
ꢅꢋꢌꢇꢃꢄ
ꢀ
ꢀ
ꢚꢀ
ꢟA
ꢇꢃꢄ
ꢀ
ꢁꢂ
ꢜ.ꢚꢀ ꢄꢇ ꢘꢛꢀ
ꢀ
ꢇꢃꢄ
ꢁꢂ
ꢚꢛꢛꢙꢕ
ꢒ.ꢜꢀ
ꢝꢘ
ꢘꢘꢙꢕ
ꢘꢓꢀ
ꢗ
ꢀ
ꢇꢏꢂꢏ
Rꢃꢂ
ꢁꢂꢄꢀ
ꢋꢄꢆꢑꢒꢓꢔ
ꢘꢘꢙꢕ
ꢅꢅ
ꢆꢇꢈꢉꢊꢅꢋꢌꢁꢂ
ꢍꢎꢆꢇꢈꢉ
ꢄRAꢅꢌꢊꢏꢏ
ꢍꢐꢇꢇꢈ
ꢅ
ꢕꢕ
ꢚꢛꢛꢞꢕ
ꢕꢠ
ꢛ.ꢚꢙꢕ
ꢅꢇꢆꢍꢡ
ꢅꢇꢆꢍꢢ
ꢤ
ꢐꢂꢈ
ꢀ
ꢇꢏꢂꢏ
ꢒꢛ.ꢑꢣ
ꢑꢒꢓꢔ ꢕꢘꢜ
Figure 23. 3.1VIN to 20VIN, 1V Output at 8A Design
ꢕꢕꢖꢗ
ꢘRꢉꢙ
ꢅꢋꢌꢇꢃꢄ
ꢀ
ꢀ
ꢖ.ꢖꢀ
ꢟA
ꢇꢃꢄ
ꢀ
ꢁꢂ
ꢀ
ꢇꢃꢄ
ꢚ
ꢁꢂ
ꢓꢀ ꢄꢇ ꢛꢞꢀ
ꢛꢛꢜꢘ
ꢛꢓꢀ
ꢀ
ꢇꢏꢂꢏ
Rꢃꢂ
ꢁꢂꢄꢀ
ꢑꢔꢜꢘ
ꢒ.ꢖꢀ
ꢝꢛ
ꢋꢄꢆꢑꢒꢓꢔ
ꢚ
ꢛꢛꢞꢜꢘ
ꢒ.ꢖꢀ
ꢅꢅ
ꢆꢇꢈꢉꢊꢅꢋꢌꢁꢂ
ꢍꢎꢆꢇꢈꢉ
ꢄRAꢅꢌꢊꢏꢏ
ꢍꢐꢇꢇꢈ
ꢛꢆꢎꢤ ꢅꢋꢇꢅꢌ
ꢞ.ꢕꢜꢘ
ꢘꢠ
ꢅꢇꢆꢍꢡ
ꢕꢞ.ꢔꢗ
ꢅꢇꢆꢍꢢ
ꢣ
ꢐꢂꢈ
ꢀ
ꢇꢏꢂꢏ
ꢑꢒꢓꢔ ꢘꢛꢑ
Figure 24. 5VIN to 20VIN, 3.3V Output with 2MHz External Clock
Rev. A
23
For more information www.analog.com
LTM4657
APPLICATIONS INFORMATION
ꢘRꢋꢡ ꢈꢉꢊꢋꢍ ꢅꢐꢌꢉꢃꢄ
ꢀ
ꢙ.ꢓꢀ
ꢙꢒA
ꢉꢃꢄ
ꢀ
ꢁꢂ
ꢅꢐꢌꢁꢂ
ꢀ
ꢀ
ꢉꢃꢄ
ꢕ
ꢁꢂ
ꢛ.ꢙꢀ ꢄꢉ ꢖꢚꢀ
ꢖꢖꢗꢘ
ꢖꢓꢀ
×ꢖ
Rꢃꢂ
ꢀ
ꢉꢎꢂꢎ
ꢙꢚꢚꢗꢘ
ꢒ.ꢛꢀ
ꢐꢄꢈꢑꢒꢓꢔ
ꢁꢂꢄꢀ
ꢅꢅ
×ꢒ
ꢆꢇꢈꢉꢊꢋ
ꢄRAꢅꢌꢍꢎꢎ
ꢆꢏꢉꢉꢊ
ꢘꢝ
ꢅꢉꢈꢆꢞ
ꢅꢉꢈꢆꢟ
ꢚ.ꢙꢗꢘ
ꢠ
ꢏꢂꢊ
ꢀ
ꢉꢎꢂꢎ
ꢘRꢋꢡ ꢈꢉꢊꢋꢍ ꢅꢐꢌꢉꢃꢄ
ꢅꢐꢌꢁꢂ
ꢀ
ꢀ
ꢉꢃꢄ
ꢕ
ꢁꢂ
Rꢃꢂ
ꢀ
ꢉꢎꢂꢎ
ꢐꢄꢈꢑꢒꢓꢔ
ꢁꢂꢄꢀ
ꢅꢅ
ꢆꢇꢈꢉꢊꢋ
ꢄRAꢅꢌꢍꢎꢎ
ꢆꢏꢉꢉꢊ
ꢘꢝ
ꢅꢉꢈꢆꢞ
ꢅꢉꢈꢆꢟ
ꢛꢚ.ꢙꢜ
ꢠ
ꢏꢂꢊ
ꢀ
ꢉꢎꢂꢎ
ꢑꢒꢓꢔ ꢘꢖꢓ
Figure 25. 3.1VIN to 20VIN, Two Phases, 1.5V at 16A Design
Rev. A
24
For more information www.analog.com
LTM4657
APPLICATIONS INFORMATION
ꢘRꢉꢣ
ꢁꢂ
ꢅꢋꢌꢇꢃꢄ
ꢀ
ꢙ.ꢓꢀ
ꢞA
ꢇꢃꢄ
ꢀ
ꢁꢂ
ꢀ
ꢀ
ꢇꢃꢄ
ꢛ.ꢙꢀ ꢄꢇ ꢖꢚꢀ
ꢖꢖꢗꢘ
ꢖꢓꢀ
×ꢖ
ꢙꢚꢚꢗꢘ
ꢒ.ꢛꢀ
ꢜꢖ
ꢕ
ꢀ
ꢇꢏꢂꢏ
Rꢃꢂ
ꢁꢂꢄꢀ
ꢋꢄꢆꢑꢒꢓꢔ
ꢅꢅ
ꢆꢇꢈꢉꢊꢅꢋꢌꢁꢂ
ꢍꢎꢆꢇꢈꢉ
ꢄRAꢅꢌꢊꢏꢏ
ꢍꢐꢇꢇꢈ
ꢘꢟ
ꢚ.ꢙꢗꢘ
ꢛꢚ.ꢙꢝ
ꢅꢇꢆꢍꢠ
ꢅꢇꢆꢍꢡ
ꢢ
ꢐꢂꢈ
ꢀ
ꢇꢏꢂꢏ
ꢘRꢉꢣ
ꢅꢋꢌꢇꢃꢄ
ꢀ
ꢙ.ꢚꢀ
ꢞA
ꢇꢃꢄꢖ
ꢀ
ꢀ
ꢇꢃꢄ
ꢁꢂ
ꢙꢚꢚꢗꢘ
ꢒ.ꢛꢀ
ꢜꢖ
ꢕ
ꢀ
ꢇꢏꢂꢏ
Rꢃꢂ
ꢋꢄꢆꢑꢒꢓꢔ
ꢁꢂꢄꢀ
ꢅꢅ
ꢆꢇꢈꢉꢊꢅꢋꢌꢁꢂ
ꢍꢎꢆꢇꢈꢉ
ꢄRAꢅꢌꢊꢏꢏ
ꢍꢐꢇꢇꢈ
ꢒꢚ.ꢑꢝ
ꢘꢟ
ꢅꢇꢆꢍꢠ
ꢅꢇꢆꢍꢡ
ꢢ
ꢒꢚ.ꢑꢝ
ꢒꢚ.ꢑꢝ
ꢐꢂꢈ
ꢀ
ꢇꢏꢂꢏ
ꢑꢒꢓꢔ ꢘꢖꢒ
Figure 26. 3.1VIN to 20VIN, 1.0V and 1.5V with Coincident Tracking
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4657 Component BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1
B1
C1
D1
E1
F1
V
A2
B2
C2
D2
E2
F2
V
A3
B3
C3
V
A4
B4
C4
D4
E4
F4
V
A5
B5
C5
D5
E5
F5
V
A6
B6
C6
D6
E6
F6
T
+
A7
B7
C7
D7
E7
F7
T
–
OUT
OUT
OUT
OUT
OUT
SENSE
SENSE
+
V
GND
INTV
RUN
GND
PGOOD
GND
GND
SW
OSNS
CC
–
FB
V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
OSNS
COMPa
FREQ
MODE/CLKIN D3
V
V
V
V
V
V
GND
IN
IN
IN
IN
IN
IN
TRACK/SS
CLKOUT
E3
F3
G3
GND
COMPb
V
V
GND
OUT
OUT
G1
V
G2
V
G4
G5
PHMODE
G6
G7
OUT
OUT
Rev. A
25
For more information www.analog.com
LTM4657
PACKAGE DESCRIPTION
ꢠ
ꢠ
ꢵ ꢵ ꢡ ꢡ ꢡ
ꢠ
ꢔ . ꢊ ꢢ ꢢ
ꢌ . ꢖ ꢢ ꢢ
ꢢ . ꢣ ꢢ ꢢ
ꢢ . ꢢ ꢢ ꢢ
ꢢ . ꢣ ꢢ ꢢ
ꢌ . ꢖ ꢢ ꢢ
ꢔ . ꢊ ꢢ ꢢ
ꢮ ꢮ ꢮ
ꢠ
ꢔ ꢯ
Rev. A
26
For more information www.analog.com
LTM4657
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
03/21 Added LTM4657IY (SnPb) and changed part marking to 4657 on the Ordering Information table
2
7
8
8
8
+
Changed text from PNP to NPN on T
SENSE
+
–
Added T
and T
on Block Diagram
SENSE
SENSE
Removed unnecessary symbol from Block Diagram
Changed R resistor value from 60.4k to 30.1k
FB
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
27
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTM4657
PACKAGE PHOTO
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4626
LTM4638
LTM4625
LTM4649
LTM4622
12A µModule Regulator. Pin Compatible with LTM4657. 3.1V ≤ V ≤ 20V. 0.6V ≤ V
≤ 5.5V. 6.25mm x 6.25mm x 3.87mm BGA.
≤ 5.5V. 6.25mm x 6.25mm x 5.02mm BGA.
IN
OUT
15A µModule Regulator. Pin Compatible with LTM4657. 3.1V ≤ V ≤ 20V. 0.6V ≤ V
IN
OUT
5A µModule Regulator
4V ≤ V ≤ 20V. 0.6V ≤ V
≤ 5.5V. 6.25mm x 6.25mm x 5.01mm BGA.
IN
OUT
10A µModule Regulator
4.5V ≤ V ≤ 16V. 0.6V ≤ V
≤ 3.3V. 9mm x 15mm x 4.92mm BGA.
IN
OUT
Dual 2.5A or Single 5A µModule Regulator
3.6V ≤ V ≤ 20V. 0.6V ≤ V
≤ 5.5V. 6.25mm x 6.25mm x 1.82mm LGA,
IN
OUT
2.42mm BGA.
LTM4646
LTM4662
Dual 10A or Single 20A µModule Regulator
Dual 15A or Single 30A µModule Regulator
Configurable Quad 1.2A µModule Regulator
4.5V ≤ V ≤ 20V. 0.6V ≤ V
≤ 5.5V. 11.25mm x 15mm x 5.01mm BGA.
≤ 5.5V. 11.25mm x 15mm x 5.74mm BGA.
≤ 1.8V (5.5V for LTM4668A). 6.25mm x
IN
OUT
OUT
OUT
4.5V ≤ V ≤ 20V. 0.6V ≤ V
IN
LTM4668/
LTM4668A
2.7V ≤ V ≤ 17V. 0.6V ≤ V
IN
6.25mm x 2.1mm BGA.
LTM4643
Configurable Quad 3A µModule Regulator
Configurable Quad 4A µModule Regulator
4V ≤ V ≤ 20V. 0.6V ≤ V
≤ 3.3V. 9mm x 15mm x 1.82mm LGA, 2.42mm
≤ 5.5V. 9mm x 15mm x 5.01mm BGA.
IN
OUT
OUT
BGA.
LTM4644
4V ≤ V ≤ 14V. 0.6V ≤ V
IN
Rev. A
03/21
www.analog.com
28
ANALOG DEVICES, INC. 2020-2021
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