LTM4650_技术文档

LTM4664A

30V to 58V Input, Dual 30A, Single 60A µModule

Regulator with Digital Power System Management

FEATURES

DESCRIPTION

The LTM^®4664A is a complete nonisolated 48V input

high efficiency step-down µModule^®regulator with dual

30A outputs. The switching controllers, power MOSFETs,

inductors and supporting components are included. Only

external capacitors are needed to complete the design.

Operating over a 30V to 58V input voltage range, the

LTM4664A supports an output voltage of 0.5V to 1.5V at up

to 75W. An intermediate output at 25% •V is also available.

The LTM4664A product video is available ^Io^Nn the website.

n

Complete 48V Input to Low Voltage Dual 30A Supply

that Can Scale to 300A, Nonisolated

n

Dual Analog Loops with Digital Interface for

Compensation, Control and Monitoring

n

Input Voltage Range: 30V to 58V

Output Voltage Range: 0.5V to 1.2V at 30A/Channel

3% Output Current Readback Accuracy (–20° to 125°C)

87% Efficiency for 48V to 1V at 60A, 90% at 40A

0.5% Output Voltage Accuracy Over Temperature

400kHz PMBus-Compliant I C Serial Interface

16mm × 16mm × 7.72mm BGA Package

2

The LTM4664A dual 30A regulators utilize digitally pro-

grammable analog control loops, precision data acquisition

circuitry and EEPROM with ECC. The LTM4664A’s 2-wire

serial interface allows the 30A outputs to be margined,

tuned and ramped up and down at programmable slew

rates and sequencing delay times. True input current sense,

output currents and voltages, input and output power, tem-

peratures, uptime and peak values are all readable for Dual

30A Power System Management (PSM) channels.

APPLICATIONS

n

48V Systems

n

Computer and Networking Equipment

n

Electronic Test Equipment

n

Storage Systems

Click to view associated TechClip Videos.

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258,

7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.

TYPICAL APPLICATION

48V to VCORE at 60A

48V to 1V Up to 60A

95

PINS NOT SHOWN FOR 4:1 VOLTAGE DIVIDER:

48V

CER

+

–

VOUT2_SET, OVP_TRIP, VP_SET, INSNSS2 , INSNSS2 ,

UVS1, UVS2, HYS_PRGM1, HYS_PRGM2, TIMERS1,

90

85

80

75

70

INTV

CER

CBULK

CCS1

+

–

C

FLY1

FLY2

TIMERS2, INSNSS1 , INSNSS1 , FAULTS1, FAULTS2

10k

PINS NOT SHOWN FOR 2-PHASE 60A SECTION:

ON/OFF

VOUTC0_CFG, VTRIMC0_CFG, VOUTC1_CFG, VTRIMC1_CFG,

FSWPH_CFG, TSNSC0a, TSNSC0b, TSNSC1a, TSNSC1b,

PWM_C0, PWM_C1, GL_C0, GL_C1, PHFLT_C0, PHFLT_C1,

INTV

CC

EXTV SHARE_CLK, SCL, SDA, ALERT, SYNC

CC,

10k

PGOODVCORE

V

PGOOD_C0

OUT2

V

OUT2

CER

C

SWC0

BULK

FREQS1

48V , 1.0V

IN

EFFICIENCY

OUT

VCORE 60A

R

FREQS1

V

OUTC0

0

10

20

30

40

50

60

FREQS2

OUTPUT CURRENT (A)

C

OUT3

R

GND

FREQS2

4664A TA01c

SGND_C0_C1

INTV

CCS1

+

V

_C0

OSNS

4.7µF

–

V

OSNS

EXTV

LTM4664A

CCS1

V

OUT2

PGOOD_C1

PGOODVCORE

EXTV

CCS2

1µF

LOAD

SWC1

V

OUTC1

INTV

CCS2

4.7µF

+

C

OUT4

IN

LTM4664A

GND

V

OUT2

CER

IN

SGND_C0_C1

V

OUTC0

V

_

INS3 C0

0.5V TO 1.2V/30A

+

DUAL

PSM

BUCK

V /4

IN

V

_C1

OSNS

V

_

INS3 C1

48V

IN

4:1 DIVIDER

V

DD33

OUTC1

–

V

OSNS

V

0.5V TO 1.2V/30A

DD33

10k

V

/2

V

OUT2

OUT1

IN

PGOODS2

4664A TA01b

PGOODS2

4664A TA01a

INTV

CC

4.7µF

PMBus

R

SEL

V

DD25

COMPH1

COMPH0

Rev. 0

1

Document Feedback

For more information www.analog.com

LTM4664A

TABLE OF CONTENTS

Features..................................................... 1

Applications ................................................ 1

Typical Application ........................................ 1

Description.................................................. 1

Absolute Maximum Ratings.............................. 4

Pin Configuration .......................................... 4

Order Information.......................................... 5

Electrical Characteristics................................. 5

Typical Performance Characteristics ..................15

4:1 Divider Block Diagram ..............................25

Dual 25A/30A Power System Management (PSM)

Block Diagram.............................................26

4:1 Divider Operation ....................................27

4:1 Divider Description ...........................................27

Main Control...........................................................27

INTV /EXTV Power ..........................................40

CC CC

Output Current Sensing and Sub Milliohm DCR

Current Sensing ..................................................... 41

Input Current Sensing ............................................ 41

PolyPhase Load Sharing ........................................ 41

External/Internal Temperature Sense .....................42

RCONFIG (Resistor Configuration) Pins .................42

Fault Detection and Handling .................................45

Status Registers and ALERT Masking ....................46

Mapping Faults to FAULT Pins ...............................48

Power Good Pins ...................................................48

CRC Protection ......................................................48

Serial Interface ......................................................48

Communication Protection ....................................48

Device Addressing .................................................48

INTV

/EXTV

Power................................27

Responses to V

and I /I

Faults ..................49

CCS1,2

OUT

IN OUT

Start-Up and Shutdown..........................................28

Fault Protection and Thermal Shutdown.................28

High Side Current Sensing......................................28

Frequency Selection................................................28

Power Good and UV (PGOODSn and UVSn pins)....29

Additional Overvoltage Protection ..........................29

4:1 Divider Application Information....................30

Voltage Divider Pre-Balance Before Switching........30

Overcurrent Protection ...........................................31

Window Comparator Programming........................31

Effective Open Loop Output Resistance and

Load Regulation......................................................32

Undervoltage Lockout.............................................32

Fault Response and Timer Programming................32

Design Example......................................................33

Dual 25A/30A PSM Operation...........................35

PSM Section Overview, Major Features..................35

EEPROM with ECC .................................................36

Power-Up and Initialization ....................................37

Soft-Start ...............................................................38

Time-Based Sequencing ........................................38

Voltage-Based Sequencing ....................................38

Shutdown ..............................................................39

Light-Load Current Operation ................................39

Switching Frequency and Phase.............................40

PWM Loop Compensation .....................................40

Output Voltage Sensing .........................................40

Output Overvoltage Fault Response .......................49

Output Undervoltage Response .............................50

Peak Output Overcurrent Fault Response ..............50

Responses to Timing Faults ...................................50

Responses to V OV Faults ...................................50

IN

Responses to OT/UT Faults ....................................50

Internal Overtemperature Fault Response ..............50

External Overtemperature and Undertemperature

Fault Response .................................................... 51

Responses to Input Overcurrent and Output

Undercurrent Faults ............................................... 51

Responses to External Faults ................................. 51

Fault Logging ......................................................... 51

Bus Timeout Protection ......................................... 51

2

Similarity Between PMBus, SMBus and I C

2-Wire Interface .....................................................52

PMBus Serial Digital Interface ...............................52

Figure 11 thru Figure 28 PMBus Protocols .............54

PMBus Command Summary ............................57

PMBus Commands ................................................57

Dual 25A/30A PSM Applications Information.........63

V to V

Step-Down Ratios ...............................63

IN

OUT

Input Capacitors ....................................................63

Output Capacitors ..................................................63

Light Load Current Operation .................................63

Switching Frequency and Phase ............................64

Output Current Limit Programming .......................65

Rev. 0

2

For more information www.analog.com

LTM4664A

TABLE OF CONTENTS

Minimum On-Time Considerations .........................66

Variable Delay Time, Soft-Start and Output

PWM Configuration ................................................95

Voltage....................................................................98

Input Voltage and Limits.........................................98

Output Voltage and Limits ......................................99

Output Current and Limits .................................... 102

Input Current and Limits ......................................104

Temperature.......................................................... 105

External Temperature Calibration.......................... 105

Timing ..................................................................106

Timing—On Sequence/Ramp...............................106

Timing—Off Sequence/Ramp .............................. 107

Precondition for Restart ....................................... 108

Fault Response ..................................................... 108

Fault Responses All Faults.................................... 108

Fault Responses Input Voltage.............................. 109

Fault Responses Output Voltage........................... 109

Fault Responses Output Current........................... 112

Fault Responses IC Temperature .......................... 113

Fault Responses External Temperature................. 114

Fault Sharing......................................................... 115

Fault Sharing Propagation .................................... 115

Fault Sharing Response........................................ 117

Scratchpad ........................................................... 117

Identification......................................................... 118

Fault Warning and Status...................................... 119

Telemetry.............................................................. 126

NVM Memory Commands .................................... 130

Store/Restore ....................................................... 130

Fault Logging........................................................ 131

Block Memory Write/Read.................................... 135

Package Description ................................... 136

Typical Applications.................................... 138

Related Parts............................................ 138

Voltage Ramping ...................................................66

Digital Servo Mode ................................................66

Soft Off (Sequenced Off) .......................................67

Undervoltage Lockout ............................................68

Fault Detection and Handling .................................68

Open-Drain Pins ....................................................68

Phase-Locked Loop and Frequency

Synchronization .....................................................69

Input Current Sense Amplifier ................................70

Programmable Loop Compensation ......................70

Checking Transient Response ................................71

PolyPhase^®Configuration ......................................72

2

Connecting the USB to I C/SMBus/PMBus Controller

to the LTM4664A In-System ..................................72

LTpowerPlay: An Interactive GUI for Digital Power .73

PMBus Communication and

Command Processing ............................................73

Thermal Considerations and Output

Current Derating ....................................................75

Table 10 and Table 11: Output Current Derating

(Based on Demo Board) .........................................78

Dual 25A/30A PSM Applications Information–

Derating Curves...........................................81

EMI Performance ...................................................82

Safety Considerations ............................................82

Layout Checklist/Example .....................................83

Typical Applications......................................84

PMBus Command Details ...............................90

Addressing and Write Protect.................................90

General Configuration Commands..........................92

On/Off/Margin ........................................................93

Rev. 0

3

For more information www.analog.com

LTM4664A

ABSOLUTE MAXIMUM RATINGS

(Note 1)

EXTV ........................................................ –0.3V to 6V

CC

4:1 Divider

INS1

V

...................................................... –0.3V to 3.6V

_Cn................................................... –0.3V to 6V

_Cn................................................ –0.3V to 0.3V

OUTCn

+

–

+

V

, SW1, SW2, INSNSS1 , INSNSS1 ,

OSNS

–

FAULTS1, FAULTS2.............................................–0.3V to 60V

OSNS

+

–

V

, V

, INSNSS2 , INSNSS2 , PGOODS1,

INS2 INS2F

PGOODS2, EXTV

RUN_Cn, SDA, SCL, ALERT....................... –0.3V to 5.5V

FSWPH_CFG, VOUTCn_CFG, VTRIMCn_CFG, ASEL,

, EXTV

, SW3, SW4,

CCS1

CCS2

OVP_SET, VOUT2_SET, OVP_TRIP, V

.......–0.3V to 40V

OUT1

COMP_1a, COMP_1b, COMP_0a, COMP_0b........–0.3V to 2.75V

FAULT_Cn, SYNC, SHARE_CLK, WP, PGOOD_Cn,

PWM_Cn, PHFLT_Cn ................................. –0.3V to 3.6V

TSNS_Cna, ............................................... –0.3V to 2.2V

TSNS_Cnb .................................... –0.3V to 0.8V, < 5mA

V

OUT2

........................................................... 0.3V to 20V

INTV

, INTV

...............OUTPUT ONLY, RATED 6V

CCS1

CCS2

RUNS1, RUNS2............................................ –0.3V to 6V

UVS1, UVS2, HYS_PRGMS1, HYS_PRGMS2,

TIMERS1, TIMERS2, FREQS1,

OVP-SET I

CC DD33 DD25

Internal Operating Temperature

Sink.................................... ………. 5mA

MAX

FREQS2.....................–0.3V to INTV

, –0.3 to INTV

CCS1

CCS2

INTV

V

, V

and GL_Cn are Outputs.

DUAL 25A/30A PSM SECTION

+

–

V

, IN , IN ...................................... –0.3V to 18V

INS3_Cn

(V

Range (Notes 2, 14, 15)............................–40°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

Peak Solder Reflow (Package Body) Temperature 245°C

+

–

– IN ), (IN – IN )...................... –0.3V to 0.3V

INS3_Cn

SWC0, SWC1.............. –1V to 18V, –5V to 18V Transient

PIN CONFIGURATION

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

B

C

D

E

V

OUTC0

OUTC1

V

OUT1

INS2

+

V

INSNSS2

INTV

CCS1

PGOODS1

FREQS1

SW3

INS2F

SW2

–

INSNSS2

EXTV

CCS1

OVP_TRIP

UVS1

FAULTS1

HYS_PRGMS2

EXTV

INTV

CCS2

RUNS1 TIMERS1

HYS_PRGMS1

OVP_SET

F

TIMERS2

SW4

V

OUT2_SET

SW1

V

CCS2

FREQS2

G

H

J

RUNS2

OUT2

PGOODS2

UVS2

FSWPH_CFG

+

V

INSNSS1

–

FAULTS2

ASEL

ALERT

INSNSS1

INS1

VTRIMC1_CFG

VTRIMC0_CFG

PHFLT_C1

VOUTC0_CFG

VOUTC1_CFG

RUN_C0

WP RUN_C1

K

L

FAULT_C0

V

FAULT_C1

DD25

PWM_C1

SHARE_CLK SDA SCL TSNSC_0a

COMP_1b SGN_DC0_C1

V

DD33

PWM_C0

SYNC

V

C0

V

C1

INS3_

PHFLT_C0

M

N

P

R

T

TSNSC_1a

COMP_1a

–

PGOOD_C1

SGND_C0_C1

COMP_0b

GL_C0

–

V

_C1

OSNS

IN

GL_C1

–

+

V

C0

OSNS

_

INTV

CC

EXTV

CC

IN

_C1

COMP_0a

PGOOD_C0

TSNS_C0b

OSNS

+

TSNS_C1b

GND

SWC1

SWC0

BGA PACKAGE

240-PIN (16mm × 16mm × 7.72mm)

= 5.47 C/W, θ = 2.15 C/W, θ = 5.3 C/W

T

θ

= 125°C, θ

JMAX

JC

JCTOP

JCBOTTOM

JA

VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS.

VALUE IS OBTAINED FROM MEASUREMENTS WITH DEMO BOARD. WEIGHT = 7.26 GRAMS.

REFER TO PAGE 78 FOR LAB MEASUREMENT AND DERATING INFORMATION.

θ

JA

NOTE: NOT RECOMMENDED FOR BACK-SIDE REFLOW SOLDERING. SEE WEBSITE FOR MORE INFORMATION.

Rev. 0

4

For more information www.analog.com

LTM4664A

ORDER INFORMATION

PART MARKING

PACKAGE

TYPE

MSL

TEMPERATURE RANGE

(SEE NOTE 2)

PART NUMBER

PAD OR BALL FINISH

DEVICE

LTM4664AY

FINISH CODE

RATING

LTM4664AIY#PBF

SAC305 (RoHS)

e1

BGA

3

–40°C to 125°C

• Contact the factory for parts specified with wider operating temperature

ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Recommended LGA and BGA PCB Assembly and Manufacturing

Procedures

• LGA and BGA Package and Tray Drawings

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the internal operating

junction temperature. T_A= 25°C, V_INS1= 48V, and RUNn = 5V where n = stage # unless otherwise noted. See Figure 46 configuration

for setup. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

4:1 Divider Section

V

Input DC Voltage Stage 1

Input DC Voltage Stage 2

Note 4

30

15

58

29

V

INS1

INS2

OUT1

OUT2

Note 4

Range

V

OUT1

V

OUT2

Output Range

Note 4

15

29

V

Note 4

7.5V

14.5

75

V

Maximum Power

Maximum Output Power

All Conditions, Note 4

Note 4, Based on Figure 49

W

V

l

V

OUTPUT

23.5

11.5

24

12

24.5

OUT1(DC)

OUT2(DC)

UVLO

OUT1

V

INS1

= 48V, RUN = 5V, IV

= 0A

OUT1

V

OUTPUT

Note 4, Based on Figure 49

= 24V, RUN = 5V, IV

12.5

V

OUT2

V

INS2

OUT2

Undervoltage Lockout

INTV Falling

4.85

5.05

V

CC

INTV Rising

CC

IQ V

V

, V Quiescent Current Each RUNn = 0V

150

1.6

44

µA

mA

INSn

INS1 INS2

Stage

RUNn = 5V, No Switching

RUNn = 5V, Switching

Overcurrent Protection Section

+

–

+

–

INSNSS1

INSNSS2

INSNSS1

INSNSS2

Stage 1 Current Sense

INSNSS1 = INSNSS1 = 60V

= 30V, RUNS1 = 5V

220

1

350

5

µA

V

OUT1

+

–

+

–

Stage 2 Current Sense

Stage 1 Current Sense

Stage 2 Current Sense

INSNSS2 = INSNSS2 = 30V

= 15V, RUNS2 = 5V

V

OUT2

+

–

l

INSNSS1 = INSNSS1 = 60V,

RUNS1 = 0V

–5

45

µA

+

–

INSNSS2 = INSNSS2 = 30V,

RUNS2 = 0V

1

5

µA

INSNSS1, INSNSS2 Current Limit Threshold

Threshold

50

55

mV

for Each Stage

Pre Charge Balance

R

VINS2F

R

VF2

V

Resistance to GND

INS2

See Block Diagram (Note 10)

1

MΩ

kΩ

Resistance Between Pins

to V

See Block Diagram

Part of a RC Filter Stage 2

V

INS2

INS2F

+

INSNSS1 Balance Stage 1 Current Sense + Source

Current

Pre-Balance Phase V

= 60V

95

mA

INS1

–

+

INSNSS1 = INSNSS1 = 60V, V

= 15V , Timer = 1V

OUT1

+

INSNSS2 Balance Stage 2 Current Sense + Source

Pre-Balance Phase V

= 30V

INS2

–

+

Current

INSNSS2 = INSNSS2 = 30V, V

= 10V, Timer = 1V

OUT2

I

V

I

Current to Pre-Start Up Bal- INSNSSn = V

= 24V V

= 10V, Timer = 0.8V

SOURCE OUTn

SOURCE

INSn

OUTn

ance V

and C , n = Stage #

See Block Diagram

OUTn

FLYn

Rev. 0

5

For more information www.analog.com

LTM4664A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the internal operating

junction temperature. T_A= 25°C, V_INS1= 48V, and RUNn = 5V where n = stage # unless otherwise noted. See Figure 46 configuration

for setup. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

V

I

Current to Pre-Start Up Balance INSNSSn = V

= 24V V = 11V, Timer = 0.8V

OUTn

50

mA

SINK OUTn

SINK

INSn

V

and C , n = Stage #

See Block Diagram

OUTn

FLYn

RUNn Pins

l

V

_

Run PIN Threshold

V

Rising

RUN

1.1

1.22

90

1.4

V

TH RUNn

n = Stage #

V

HYS

Run Pin Hysteresis

n = Stage #

mV

RUNn

OVP Comparator

OVP-SET In

OVP-SET Input Range MAX

25

30

3

V

Range MAX

OUT2-SET

I

Input Bias I

V

= 0V to 25V

CM

mA

mV

db

µs

V

B

V

Input Offset

0.5V < V < 25V

CM

OS

PSRR

Power Supply Rejection

Common Mode Rejection

Propagation Delay

OVP_Trip Sink

0.5V < V < 25V (Note 10)

85

80

10

0.35

CM

CMRR

0.5V < V < 25V (Note 10)

CM

Delay

OVP_Trip Sink

I

= 5mA (Note 10)

SINK

INTV Regulators

CC

VINTV

Internal (LDO) Low Drop Out

30V < V

15V < V

< 58V, V

< 19V, V

= 0V, Stage 1

= 0V, Stage 2

5.4

5.6

5.9

2

V

CCSn

INS1

INS2

EXTVCCS1

EXTVCCS2

Regulator, n = Stage #

VINTV

Load

LDO Load Regulation

I

= 50mA, VEXTV

= 0V

0.5

150

5.6

%

mA

V

CCSn

CC

CCSn

INTV

IPeak

INTV Stage Peak Output Current

CC

CCSn

VINTV

with

LDO Output Range with EXTV

n = Stage #

,

12V < VEXTV < 24V,

CCn

5.9

2

CCSn

CCn

EXTV

V

= 12V

INSn

CC

VINTV

EXT

Load

LDO Load Regulation with EXTV

I

CC

= 50mA, VEXTV = 6.5V

CCn

1

%

CCSn

CC

VEXTV

Threshold EXTV

Switch Over

Hysteresis

VEXTV Ramping Positive

6.3

6.5

6.65

V

CCn

HYS

EXTV

400

mV

CCn

Switching Oscillator

Frequency Range n Frequency Range

n = Stage #

100

1000

kHz

f

Stage 1

Stage 2

Optimized Efficiency Freq. Stage 1

Optimized Efficiency Freq. Stage 2

FREQS1. Pin Resistor = 36.5k

FREQS2. Pin Resistor = 60.4k

100

200

NOM

Output Specifications

ΔV /V

Stage 1 Load Regulation Accuracy

V

C

= 24V, 0A to 3.2A Maximum = 75W

3.5

%

OUT OUT

OUT1

INS1

INB1

IN1

OUT1

Stage 1

= 48V, FREQS1 = 100kHz

= 33µF (Bulk Input Capacitor)

= 2.2µF 100V Ceramic, C

= 10µF 50V X6

FLY1

= 10µF 50V

V

OUT1

Output Load

V

Max Load Current

V

C

= 24V, 0A to 3.2A Maximum = 75W

= 48V, FREQS1 = 100kHz

3.2

A

OUT1

INS1

INB1

IN1

OUT1

(Note 4)

= 33µF (Bulk Input Capacitor)

= 2.2µF 100V Ceramic, C

= 10µF 50V X6

FLY1

= 10µF 50V

M1-M4 RDS-ON

Stage 1 MOSFET On Resistance

VGS = 5V (Note 16)

18

mΩ

Rev. 0

6

For more information www.analog.com

LTM4664A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the internal operating

junction temperature. T_A= 25°C, V_INS1= 48V, and RUNn = 5V where n = stage # unless otherwise noted. See Figure 46 configuration

for setup. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ΔV /V

Stage 2 Load Regulation Accuracy

V

C

= 12V, 0A to 6.3A Maximum = 75W

= 24V, FREQS2 = 200kHz

5

%

OUT OUT

OUT2

INS2

INB2

IN2

FLY2

Stage 2

= 33µF (Bulk Input Capacitor)

= 10µF 50V Ceramic,

= 22µF 25V X6, C

= 22µF 25V

OUT2

V

OUT2

Output Load

V

Max Load Current

V

C

= 12V, 0A to 6.3A Maximum = 75W

= 24V, FREQS2 = 200kHz

6.3

A

OUT1

OUT2

INS2

INB2

IN2

FLY2

(Note 4)

= 33µF (Bulk Input Capacitor)

= 10µF 50V Ceramic,

= 22µF 25V X6, C

= 22µF 25V

OUT2

M5-M8 RDS-ON

Stage 2 MOSFET On Resistance

Output Ripple Voltage

VGS = 5V (Note 16)

10

mΩ

V

, (AC)

OUT1

V

C

= 24V, 0A to 3A V = 48V, FREQS1 = 100kHz

INS1

150

mV_pk-pk

OUT1

INB1

IN1

= 33µF (Input Bulk Capacitor)

= 2.2µF 100V Ceramic, C

= 10µF 50V

= 10µF 50V X6

FLY1

OUT1

V

, (AC)

OUT2

Output Ripple Voltage

V

C

= 12V, 0A to 6A

50

mV_pk-pk

OUT2

INS2

INB2

IN2

FLY2

= 12V, FREQS2 = 200kHz

= 33µF (Input Bulk Capacitor)

= 10µF 50V Ceramic,

= 22µF 25V X6, C

= 22µF 25V

OUT2

t

Stage 1

Stage 2

Turn-on Time

From RUN 1

V

= 0V at Start Up to 24V, 0A, V

= 48V,

START

OUT1

INS1

FREQS1 = 100kHz

C

= 33µF (Input Bulk Capacitor)

40

75

msec

INB1

IN1

OUT1

= 2.2µF 100V Ceramic, C

= 10µF 50V X6

FLY1

= 10µF 50V, C

= 0.22µF

TIMERS1

Turn-on Time Stage 2

From RUN 2

V

= 0V at Start Up to 12V, 0A, V

= 24V,

START

OUT2

INS2

FREQS2 = 200kHz

C

= 33µF (Input Bulk Capacitor)

INB2

IN1

OUT2

= 2.2µF 100V Ceramic, C

= 22µF, 25V X6

FLY1

= 22µF 25V, C

= 0.47µF

TIMERS2

HYS_PRGMn and FAULTSn

V

FAULT Voltage Low

I

= 2mA

= 5V

0.2

10

0.5

1

V

µA

FAULTSn

FAULT

I

FAULT Leakage Current

HYS_PRGM Setting Current

V

FAULT_LEAKSn

HYS_PRGMSn

FAULT

l

9

11

V

Fault Trip Level

V

= 24V, V

, HYS_PRGMSn = 0V,

FAULTSn

OUTSn

INSn

OUTn

l

Ramp Up

12.2 12.3 12.45

V

OUTSn

Ramp Down

= 24V, V , HYS_PRGMSn = 5V,

OUTn

11.6 11.7

11.8

V

INSn

OUTSn

l

Ramp Up

12.7 12.8

11.1 11.2

12.9

11.4

V

Ramp Down

= 24V, V , HYS_PRGMSn = 2.4V,

OUTn

Ramp Up

Ramp Down

V

INSn

OUTSn

l

14.15 14.3 14.45

V

9.5

9.65

9.8

UV COMPARATORn and PGOODn

V

Undervoltage Threshold

Undervoltage Hysteresis

PGOOD Voltage Low

UV Pin Voltage Rising

0.99 1.01

120

1.03

V

mV

V

UVTHSSn

HYS_PRGMSn

PGOODSn

I

= 2mA

= 5V

0.35

0.5

1

PGOOD

I

PGOOD Leakage Current

V

µA

PGOODSn_LEAK

PGOOD

TimerSn

TimerSn Current

I

V

< 0.5V or V

> 1.2V

3.5

7

µA

TIMERn

TIMER

0.5V < V

< 1.2V

TIMER

Rev. 0

7

For more information www.analog.com

LTM4664A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). T_A= 25°C,

V_INS3= 12V, RUN_Cn = 3.3V, EXTV_CC= 0V, FREQUENCY_SWITCH = 350kHz and V_OUTCncommanded to 1.000V unless otherwise noted.

Configured with factory default EEPROM settings, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DUAL 25A/30A PSM OUTPUT

l

V

Input DC Voltage Operating

7

16

V

INS3

+

–

Range of Output Voltage

Regulation

V

OUTCn

Diff Sensed on V

_Cn/V _Cn-Pin-Pair;

OSNS

0.5

1.5

OUTCn

OSNS

Commanded by Serial Bus or with Resistors

Present at Start-Up on VOUTCn_CFG, Differential

Remote Sense Path Voltage (Notes 4, 6)

l

V

Output Voltage, Total Variation with

Line and Load

Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)

Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)

0.995 1.000 1.005

0.985 1.000 1.015

V

OUTCn(DC)

VOUTCn_CFG Commanded to 1.000V, V

Low

OUTCn

Range (MFR_PWM_MODEn[1] = 1b) (Note 6)

VINS3 UVLO

Undervoltage Lockout Threshold

Input Inrush Current at Start-Up

VINTV Falling

3.55

3.9

V

CC

VINTV Rising

CC

I

V

=1V, V = 12V; No Load Besides Capacitors;

INS3

400

mA

INRUSH(VINS3)

S(VINS3,DCM)

S(VINS3,FCM)

OUTCn

TON_RISEn = 3ms

Input Supply Current in

Discontinuous Mode Operation

Discontinuous Mode, MFR_PWM_MODEn[0] = 0b,

I = 100mA

OUTCn

60

mA

Input Supply Current in

Forced-Continuous Mode Operation

Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b

I

= 100mA

80

3.0

mA

A

OUTn

= 30A V

= 12V, V

= 1V

INS3

OUTn

I

Input Supply Current in Shutdown

Shutdown, RUN_Cn = 0V

25

mA

S(VINS3,SHUTDOWN)

Output Specifications

I

Output Continuous Current Range

Utilizing MFR_PWM_MODE[7] = 0 ,

and Using ~I = 34A , Page103, (Note 4)

0

30

A

OUTCn

OUT

ΔV_OUTn(LINE)

Line Regulation Accuracy

Digital Servo Engaged (MFR_PWM_MODEn[6] = 0b)

Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)

0.03

%/V

0.2

V_OUTn

Open Circuit; I

= 0A, 7V ≤ V ≤ 16V, V

Low

OUTCn

IN

OUT

Range (MFR_PWM_MODEn[1] = 1b),

FREQUENCY_SWITCH = 350kHz (Note 6)

ΔV_OUTn(LOAD)

Load Regulation Accuracy

Output Voltage Ripple

Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)

Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)

0.03

0.2

%

l

0.5

V_OUTn

0A ≤ I

≤ 30A, V

Low Range,

OUTn

OUT

(MFR_PWM_MODEn [1] = 1b) (Note 6)

V

10

350

8

mV

kHz

mV

ms

OUTn(AC)

f

V

Ripple Frequency

OUTCn

FREQUENCY_SWITCH Set to 350kHz (0xFABC)

320

2.9

380

S (Each Channel)

ΔV

Turn-On Overshoot

TON_RISEn = 3ms (Note 7)

OUTCn(START)

t

Turn-On Start-Up Time

Time from V Toggling from 0V to 12V to Rising Edge

30

START

IN

PGOOD_Cn, TON_DELAYn = 0ms, TON_RISEn = 3ms

l

t

Turn-On Delay Time

Time from First Rising Edge of RUN_Cn to Rising Edge

of PGOOD_Cn. TON_DELAYn = 0ms, TON_RISEn =

3.3

40

30

3.7

ms

mV

µs

DELAY(0ms)

3ms, V

Having Been Established for at Least 70ms

INS3

ΔV

Peak Output Voltage

Deviation for Dynamic Load Step

Load: 0A to 12.5A and 12.5A to 0A at 12.5A/μs,

V = 1V, V = 12V (Note 7) See Load Transient

OUTn

OUTn(LS)

INS3

Graph

Load: 0A to 12.5A and 12.5A to 0A at 12.5A/μs,

= 1V, V = 12V (Note 7) See Load Transient

t

Settling Time for

Dynamic Load Step

SETTLE

V

OUTn

Graph

INS3

Rev. 0

8

For more information www.analog.com

LTM4664A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). T_A= 25°C,

V_INS3= 12V, RUN_Cn = 3.3V, EXTV_CC= 0V, FREQUENCY_SWITCH = 350kHz and V_OUTCncommanded to 1.000V unless otherwise noted.

Configured with factory default EEPROM settings, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Output Current Limit, Time Averaged

Time-Averaged Output Inductor Current Limit Inception

Threshold, Commanded by IOUT_OC_FAULT_LIMITn

(Note 7) Utilizing MFR_PWM_MODE[7] = 0b, and Using

34

A

OUTn(OCL_AVg)

~I

= 34A , Page103

OUT

Control Section

–

l

V

Feedback Input

V

OSNS

V

OSNS

_Cn Valid Input Range (Referred to SGND)

–0.1

–0.5

0.3

3.6

V

FBCMn

+

Common Mode Range

_Cn Valid Input Range (Referred to SGND)

V

Full-Scale Command Voltage

Range Low (0.5V to 2.75V)

Set Point Accuracy

Resolution

Limit Design to 1.5V Operating for Module

MFR_PWM_MODEn[1] = 1b, VOUTn Commanded to

2.75V (Notes 8, 10)

OUTn-RNGL

2.75

V

%

Bits

mV

0.5

12

0.688

LSB Step Size

V

Full-Scale Command Voltage

Range High (0.5V to 3.6V)

Set Point Accuracy

Resolution

Limit Design to 1.5V Operating for Module

MFR_PWM_MODEn[1] = 0b, VOUTn Commanded to

3.60V (Notes 8, 10)

OUTn-RNGH

3.60

V

%

Bits

mV

–0.5

12

1.375

LSB Step Size

+

R

V

_Cn Impedance to SGND

0.05V ≤ V

_Cn – VSGND ≤ 3.3V

50

60

kΩ

VSENSEn

OSNS

VOSNS

t

Minimum On-Time

(Note 10 )

nsec

ON(MIN)

g

m0,1

Resolution

COMP0,1 = 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7

MFR_PWW_CONFIG Section (Note 10)

3

Bits

mmho

Error Amplifier g

LSB Step Size

5.76

1

m(max)

m(min)

0.68

RCOMP0, 1

Resolution

MFR_PWM_CONFIG[4:0] = 0 to 31

5

62

0.5

Bits

kΩ

Compensation Resistor RCOMP(MAX) (See Figure 1, Note 10)

Compensation Resistor RCOMP(MIN)

Analog OV/UV Ch 0,1(Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_

LIMIT Monitors)

N

Resolution, Output

Voltage Supervisors

(Notes 9, 10)

9

Bits

OV/UV_COMP

V

Output OV Comparator

(Notes 9, 10) Limit Design to 1.5V Operating for Module

Low Range Scale, MFR_PWM_MODEn[1] = 1b

High Range Scale, MFR_PWM_MODEn[1] = 0b

OV-RNG

Threshold Detection Range

0.5

1

2.7

3.6

V

Output OV and UV

Comparator Threshold

Programming LSB Step Size

(Notes 9, 10)

Low Range Scale, MFR_PWM_MODEn[1] = 1b

High Range Scale, MFR_PWM_MODEn[1] = 0b

OUSTP

5.6

mV

11.2

Output OV Threshold Accuracy

Range Low

(Notes 9, 10)

OV-ACC-Cn

+

–

l

0.5V ≤ V

_Cn – V

_Cn ≤ 2.7V, MFR_PWM_

40

mV

%

VOSNS

MODEn[1] = 1b

+

–

Range High

1V ≤ V

_Cn – V

_Cn ≤ 3.6V, MFR_PWM

1.5

VOSNS

MODEn[1] = 0b

Rev. 0

9

For more information www.analog.com

LTM4664A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). T_A= 25°C,

V_INS3= 12V, RUN_Cn = 3.3V, EXTV_CC= 0V, FREQUENCY_SWITCH = 350kHz and V_OUTCncommanded to 1.000V unless otherwise noted.

Configured with factory default EEPROM settings, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Output UV Comparator

Threshold Detection Range

(Note 10) Limit Design to 1.5V Operating for Module

Low Range Scale, MFR_PWM_MODEn[1] = 1b

High Range Scale, MFR_PWM_MODEn[1] = 0b

UV-RNG

0.5

1

2.7

3.6

V

Output UV Threshold Accuracy

Range Low

(Notes 9, 10)

UV-ACC Cn

+

–

l

0.5V ≤ V

_Cn – V

_Cn ≤ 2.7V, MFR_PWM_

40

mV

%

VOSNS

MODEn[1] = 1b

+

–

Range High

1V ≤ V

_Cn – V

_Cn ≤ 3.6V, MFR_PWM_

1.5

VOSNS

MODEn[1] = 0b

t

Output OV Comparator

Response Times

Overdrive to 10% Above Programmed Threshold

Underdrive to 10% Below Programmed Threshold

100

µs

PROP-OV

Output UV Comparator

Response Times

PROP-UV

Analog OV/UV V

Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF)

INS3

N

V

OV/UV Comparator

INS3

(Notes 9, 10)

9

Bits

V

VINS3-OV/UV-COMP

Threshold-Programming Resolution

l

V

OV/UV Comparator

ABS MAX = 18V for Module Design

(Note 10)

4.5

16

INS3-OU-RANGE

INS3-OU-STP

INS3

Threshold-Programming Range

V

OV/UV Comparator

76

mV

INS3

Threshold-Programming

LSB Step Size

l

V

OV/UV Comparator

4.5V < V

≤ 16V, Operating Range, 16V Max for

INS3

350

mV

INS3-OU-ACC

INS3

Threshold Accuracy

Module

t_{PROP-VINS3-LOW-VIN}

V

OV/UV Comparator

Test Circuit 1, and:

VIN_ON = 9V; V

INS3

Response Time, High V

Driven from 8.775V to 9.225V

Driven from 9.225V to 8.775V

100

µs

IN

INS3

Operating Configuration

VIN_OFF = 9V; V

INS3

t_{PROP-VINS3-LOW-VIN}

V

OV/UV Comparator

Test Circuit 2, and:

VIN_ON = 4.5V; V

INS3

Response Time, Low V

Driven from 4.225V to 4.725V

Driven from 4.725V to 4.225V

100

µs

IN

INS3

Operating Configuration

VIN_OFF = 4.5V; V

Input Voltage (V ) Readback (READ_VIN)

INS3

N

Input Voltage Readback

Resolution and LSB Step Size

(Notes 5, 10)

10

15.625

Bits

mV

VINS3-RB

V

Input Voltage Full-Scale

Digitizable Range

(Notes 7, 11) 18V for Module Design

READ_VIN, 4.5V ≤ V ≤ 16V, (V = V )

INS3

43

V

INS3-F/S

l

V

Input Voltage Readback Accuracy

2

%

INS3-RB-ACC

INS3

IN

t

Input Voltage Readback

Update Rate

MFR_ADC_CONTROL = 0.00 (Notes 10, 12)

MFR_ADC_CONTROL = 0.01 (Notes 10, 12)

90

8

ms

CONVERT-VINS3-RB

Channels 0 and 1 Output Voltage Readback (READ_VOUTn)

N

VO-RB

Output Voltage Readback

Resolution and LSB Step Size

(Note 10)

16

244

Bits

µV

V

O-F/S

Output Voltage Full-Scale

Digitizable Range

V

= 0V (Note 10)

8

V

RUNn

Design Limited to 1.5V

+

–

l

V

Output Voltage Readback Accuracy

0.5V ≤ V

_Cn – V _Cn ≤ 1.0V

VOSNS

Within 5mV, Reading

Within 0.5%, Reading

O-RB-AC-Cn

VOSNS

1V ≤ V

+_Cn – V

– _Cn ≤ 3.6V

VOSNS

Channels 0 and 1 Output Current (READ_IOUTn)

N

Output Current Readback

Resolution and LSB Step Size

(Notes 5, 10) Based on MFR_PWM_MODE[7] = 1

Using the OUT_OC_FAULT_LIMIT of 34A

10

34.1

Bits

mA

IO-RB

I

Output Current Full-Scale Digitizable

Range

(Notes 5, 10) Based on MFR_PWM_MODE[7] = 1

Using the IOUT_OC_FAULT_LIMIT of 40A

34

A

O-F/S

Rev. 0

10

For more information www.analog.com

LTM4664A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). T_A= 25°C,

V_INS3= 12V, RUN_Cn = 3.3V, EXTV_CC= 0V, FREQUENCY_SWITCH = 350kHz and V_OUTCncommanded to 1.000V unless otherwise noted.

Configured with factory default EEPROM settings, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Output Current, Readback Accuracy

READ_IOUTn, Channels 0 and 1, 0 ≤ I

≤ 25A,

O-RB-ACC

OUTn

l

Forced-Continuous Mode, MFR_PWM_MODEn[0] = 1b

With Offset Adjustment (–20°C to 125°C) (Note 7)

See Histograms in Typical Performance Characteristics Section

5

3.5

%

I

t

Full Load Output Current Readback

I

= 30A Max by Module Design Up to 1.2V (Note 7)

25

30

A

O-RB(25A)

OUTn

Output Current Readback Update Rate MFR_ADC_CONTROL = 0×00 (Notes 10, 12)

MFR_ADC_CONTROL = 0×06 (CH0 I )or 0×0A (CH1

90

8

ms

CONVERT-IO-RB

OUT

I

) (Notes 9, 17) See MFR_ADC_CONTROL Section

OUT

Input Current Readback

Resolution

(Notes 5, 10)

10

Bits

N

+

–

V

IINSTP

LSB Step Size Full-Scale Range = 16mV Gain = 8, 0V ≤ |V

LSB Step Size Full-Scale Range = 32mV Gain = 4, 0V ≤ |V

LSB Step Size Full-Scale Range = 64mV Gain = 2, 0V ≤ |V

– V | ≤ 5mV

15.26

30.52

61

µV

IIN

–

– V | ≤ 20mV

IIN

– V | ≤ 50mV

IIN

+

–

l

I

Total Unadjusted Error

Gain = 8, 2.5mV ≤ |V

– V | (Note 13)

3.5

2.5

1.8

%

IN_TUE

IIN

+

–

Gain = 4, 4mV ≤ |V

Gain = 2, 6mV ≤ |V

– V | (Note 13)

IIN

+

–

IIN

V

Zero-Code Offset Voltage

Update Rate

(Note 10)

(Note 12)

50

µV

OS

t

90

ms

CONVERT

Internal Controller Supply Current Readback V

INS3

N

Resolution

(Notes 5,12) See MFR_ADC_CONTROL Section for

Faster Update Rates

10

Bits

µV

%

V

LSB Step Size Full-Scale

Range = 256mV

244

ICONTROL STP

I

Total Unadjusted Error

20mV ≤ |V SV | ≤ 150mV)

IINS3_C1– IN

3

CONTROL TUE

See Block Diagram (Note 10)

(Note 12)

t

Update Rate

90

ms

CONVERT

Temperature Readback (TSNS_C0, TSNS_C1)

T

Resolution

0.25

3

°C

RES_T

T0_TUE

External Temperature Total

Unadjusted Readback Error

Supporting Only Delta V Sensing

BE

(Note 13)

T1_TUE

Internal TSNS TUE

Update Rate

V

= 0.0, f

= 0kHz (Note 8)

3

°C

RUN_C0,C1

SYNC

t

MFR_ADC_CONTROL = 0×04 or 0×0C

(Notes 9, 12, 15)

90

8

ms

CONVERT

INTV Regulator/EXTV

CC

V

Internal V Voltage No Load

6V ≤ V ≤ 16V

5.25

4.5

5.5

0.5

4.7

340

60

5.75

2

V

%

INTVCC

CC

IN

INTV Load Regulation

I = 0mA to 20mA, 6V ≤ V ≤ 16V

CC IN

LDO_INT

EXTVCC

LDO_HYS

LDO_EXT

IN_THR

CC

EXTV Switchover Voltage

V

≥ 7V, EXTV Rising

4.9

V

CC

INS3_C1

CC

EXTV Hysteresis

mV

V

CC

EXTV Voltage Drop

I

CC

= 20mA, VEXTV = 5.5V

120

CC

V

Threshold to Enable EXTV

V

IN

Rising

7.1

IN

CC

Switchover

Hysteresis to Disable EXTV

CC

V

IN

Falling

600

mV

IN_THF_HYS

IN

Switchover

Rev. 0

11

For more information www.analog.com

LTM4664A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). T_A= 25°C,

V_INS3= 12V, RUN_Cn = 3.3V, EXTV_CC= 0V, FREQUENCY_SWITCH = 350kHz and V_OUTCncommanded to 1.000V unless otherwise noted.

Configured with factory default EEPROM settings, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Regulator

DD33

LIM

V

Internal V

Voltage

4.5V < V

or 4.8V < V

EXTVCC

3.2

3.3

100

3.5

3.1

3.4

V

mA

V

DD33

INTVCC

I

V

Current Limit

V = GND, V = INTV = 4.5V

DD33 IN CC

DD33

V

Overvoltage Threshold

Undervoltage Threshold

(Note 10)

DD33_OV

DD33_UV

V

Regulator

DD25

IM

Internal V

Voltage

2.5

80

V

DD25

L

V

Current Limit

V

DD25

= GND, V = INTV = 4.5V

mA

DD25

IN

CC

Oscillator and Phase-Locked Loop

l

f

PLL SYNC Range

Synchronized with Falling Edge of SYNC

250

1000

7.5

kHz

%

RANGE

OSC

Oscillator Frequency Accuracy

SYNC Input Threshold

Frequency Switch = 250.0kHz to 1000.0kHz (Note 10)

V

SYNC

V

SYNC

Falling

Rising

1

1.5

V

TH(SYNC)

V

SYNC Low Output Voltage

I

= 3mA

0.2

0.4

5

V

OL(SYNC)

LOAD

I

SYNC Leakage Current in Slave Mode

0V ≤ V ≤ 3.6V

µA

LEAK(SYNC)

θSYNC-θ0

SYNC to Ch0 Phase Relationship

MFR_PWM_CONFIG[2:0] = 0,2,3

0

Deg

Based on the Falling Edge of Sync and MFR_PWM_CONFIG[2:0] = 5

60

Rising Edge of SWC0)

MFR_PWM_CONFIG[2:0] = 1

MFR_PWM_CONFIG[2:0]= 4,6 (Note 10)

90

120

θSYNC-θ1

SYNC to Ch1 Phase Relationship

MFR_PWM_CONFIG[2:0] = 3

120

180

240

270

300

Deg

Based on the Falling Edge of Sync and MFR_PWM_CONFIG[2:0] = 0

Rising Edge of SWC1

MFR_PWM_CONFIG[2:0] = 2,4,5

MFR_PWM_CONFIG[2:0] = 1

MFR_PWM_CONFIG[2:0] = 6 (Note 10)

EEPROM Characteristics

l

Endurance

Retention

(Notes 15, 16)

0°C < T < 85°C EEPROM Write Operations

10,000

10

Cycles

Years

ms

J

(Notes 15, 16)

T < 125°C

J

Mass_Write

Mass Write Operation Time

STORE_USER_ALL, 0°C < T < 85°C

440

4100

J

During EEPROM Write Operation

Input Leakage Current SDA, SCL, ALERT, RUN

Input Leakage Current

Leakage Current FAULTn, PGOOD_Cn

Input Leakage Current

Digital Inputs SCL, SDA, RUN_Cn, FAULT_Cn (Note 10)

l

I

OV ≤ V ≤ 5.5V

5

2

µA

OL

I

OV ≤ V ≤ 3.6V

LEAK

l

V

C

Input High Threshold Voltage

Input Low Threshold Voltage

Input Hysteresis

1.35

V

IH

0.8

IL

SCL, SDA

WP

0.08

10

V

HYST

Input Capacitance

10

pF

Digital Input WP (Note 10)

Input Pull-Up Current

I

µA

PUWP

Open-Drain Outputs SCL, SDA, FAULT_Cn, ALERT, RUN_Cn, SHARE_CLK, PGOOD_Cn

Output Low Voltage = 3mA

V

OL

I

0.4

V

SINK

Rev. 0

12

For more information www.analog.com

LTM4664A

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified internal

operating temperature range (Note 1, 2, 3). Specified as each individual output channel designated with n (Note 3). T_A= 25°C,

V_INS3= 12V, RUN_Cn = 3.3V, EXTV_CC= 0V, FREQUENCY_SWITCH = 350kHz and V_OUTCncommanded to 1.000V unless otherwise noted.

Configured with factory default EEPROM settings, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Inputs SHARE_CLK, WP (Note 10)

l

V

Input High Threshold Voltage

Input Low Threshold Voltage

I

= 3mA

1.5

1

1.8

V

IH

SINK

0.6

IL

Digital Filtering of FAULTCn (Note 10)

Input Digital Filtering FAULTn

Digital Filtering of PGOOD_Cn (Note 10)

Output Digital Filtering PGOOD_Cn

Digital Filtering of RUN_Cn (Note 10)

Input Digital Filtering RUN_Cn

PMBus Interface Timing Characteristics (Note 10)

T

3

µs

FLTF

T

60

10

PGF

T

RUNF

l

f

t

Serial Bus Operating Frequency

10

1.3

0.6

400

kHz

µs

SCL

Bus Free Time Between Stop and Start

BUF

Hold Time After Repeated Start

Condition After This Period, the First

Clock is Generated

µs

HD(STA)

l

t

Repeated Start Condition Setup Time

Stop Condition Setup Time

0.6

10000

0.9

µs

SU(STA)

SU(ST0)

HD(DAT)

l

Date Hold Time

Receiving Data

Transmitting Data

0

0.3

µs

t

Data Setup Time

Receiving Data

0.1

µs

SU(DAT)

Stuck PMBus Timer Non-Block Reads Measured from the Last PMBus Start Event

Stuck PMBus Timer Block Reads

3

255

ms

TIMEOUT_SMB

l

t

Serial Clock Low Period

Serial Clock High Period

1.3

0.6

10000

0.6

µs

LOW

HIGH

Channel 0 and Channel 1 Power Stages (Note 10)

PWM_Cn LOW

PWM_Cn HIGH

PHFLT_Cn T

PWM Drive Low Level, C0, C1

PWM Drive High Level, C0, C1

Warning Temperature

Thermal Warning Accuracy

Hysteresis

V

2.6

140

C

PHFLT_Cn ACC

PHFLT_Cn HYS

PHFLT_Cn Res

PHFLT_Cn Leak

–10

10

Kelvin

Ω

10

37.5

0.1

10

On Resistance

Sink = 8mA

80

5

µA

PHFLT_Cn Pull-Up Pull-Up Resistor

Tied to V

kΩ

DD33

Rev. 0

13

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LTM4664A

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime. All voltages are referred to GND pin unless

otherwise specified.

Note 8: Even though V

maximum, the maximum recommended command voltage to regulate

output channels 0 and 1 is 1.5V with V

MFR_PWM_MODEn[1].

Note 9: Channel n OV/UV comparator threshold accuracy for MFR_PWM_

MODEn[1] = 1b tested in ATE at V

and V

are specified for 3.6V absolute

OUTC0

OUTC1

range-setting bit set using

OUT

+

–

Note 2: The LTM4664A is tested under pulsed load conditions such that

_Cn – V

Cn = 0.5V and

VOSNS

T ≈ T . Note that the maximum ambient temperature consistent with

2.7V. MFR_PWM_MODEn[1] = 1b is the Low Range.

J

A

these specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal resistance and

other environmental factors.

Note 3: All Currents into the device pins are positive, all currents out of

the device are negative. Each channel of PSM is tested independently in

production. A shorthand notation is used in this document that allows

Note 10: Tested at IC-level ATE

Note 11: The absolute maximum rating for the V

pin is 18V. Input

INS3

voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled

down from the V pin.

INS3

Note 12: The data conversion is done by default in round robin fashion.

All inputs signals are continuously converted for a typical latency of 90ms.

Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4664A can do fast

data conversion with only 8ms to 10ms. See section PMBus Command

for details.

Note 13: Part tested with PWM disabled. Evaluation in application

demonstrates capability. TUE(%) = ADC Gain Error (%) +100 • (Zero code

Offset + ADC Linearity Error)/Actual Value.

Note 14: EEPROM endurance and retention are guaranteed by wafer-level

testing for data retention. The minimum retention specification applies

for devices whose EEPROM has been cycled less than the minimum

endurance specification, and whose EEPROM data was written to at 0°C

these parameters to be referred to by “V " and “V ”, where n

INS3_Cn OUTCn

is permitted to take on a value of 0 or 1. This italicized “n” notation and

convention is extended to encompass all such pin names, as well as

register names with channel-specific, i.e., paged data. For example, VOUT_

COMMANDn refers to the VOUT_COMMAND command code data located

in Pages 0 and 1, which in turn relate to channel 0 (V ) and channel 1

OUTC0

(V

). Registers containing non-page-specific data, i.e., whose data is

OUTC1

“global” to the module or applies to both of the module’s channels lack the

italicized, “n”, e.g., FREQUENCY_SWITCH.

Note 4: See output current derating curves for different V , V , Load

IN OUT

Current and T , located in the Dual 25A/30A PSM Applications Information

A

≤ T ≤ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over

J

section. For output voltage up to 1.2V, Dual 30A loads are rated.

the entire operating temperature range and does not influence EEPROM

characteristics.

Note 15: Write operations above T = 85°C or below 0°C are possible

although the Electrical Characteristics are not guaranteed and the EEPROM

will be degraded. Read operations performed at temperatures below 125°C

will not degrade the EEPROM Writing to the EEPROM above 85°C will

result in a degradation of retention characteristics.

Note 16: M1-M8 power MOSFET are final tested separately before

assembly in to the µModule.

Note 17: MFR_PWM_MODE[2] = 1 or 0 sets device in low DCR mode or

regular DCR mode respectively. MFR_PWM_MODE[7]=1 or 0 sets device in

high output current range or low current range. See “Output Current Sensing

and sub milliohm DCR Current Sensing” in Operation Section for details.

Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits

mantissa (signed). This limits the output resolution to 10 bits though the

internal ADC is 16 bits and the calculations use 32-bit words.

J

Note 6: V

n (DC) and line and load regulation tests are performed

OUTC

in production with digital servo disengaged (MFR_PWM_MODEn[6] =

0b) and low VOUTCn range selected MFR_PWM_MODEn[1] = 1b. The

digital servo control loop is exercised in production (setting MFR_PWM_

MODEn[6] = 1b), but convergence of the output voltage to its final settling

value is not necessarily observed in final test—due to potentially long

time constants involved—and is instead guaranteed by the output voltage

readback accuracy specification. Evaluation in application demonstrates

capability; see the Typical Performance Characteristics section.

Note 7: These typical parameters are based on bench measurements and

are not production tested.

Only V

codes 2–8 are supported for DCR sensing.

ILIMIT

Rev. 0

14

For more information www.analog.com

LTM4664A

TYPICAL PERFORMANCE CHARACTERISTICS

0.9V Individual Single Output

1st Stage = 100kHz,

1V Individual Single Output

1st Stage = 100kHz,

1.2V Individual Single Output

1st Stage = 100kHz,

2nd Stage = 200kHz,

Final 25A/30A Stages = 250kHz,

EXTV_CC= 5V

2nd Stage = 200kHz,

Final 25A/30A Stages = 250kHz,

EXTV_CC= 5V

Final 25A/30A Stages = 250kHz,

EXTV_CC= 5V

95

90

85

80

75

95

90

85

80

75

95

90

85

80

75

30V INPUT

36V INPUT

48V INPUT

54V INPUT

30V INPUT

36V INPUT

48V INPUT

54V INPUT

30V INPUT

36V INPUT

48V INPUT

54V INPUT

0

5

10

15

20

25

0

5

10

15

20

25

0

5

10

15

20

25

OUTPUT CURRENT (A)

4664A G01

4664A G02

4664A G03

1.5V Individual Single Output

1st Stage = 100kHz,

54V Input, 2-Phase 50A Single Output

1st Stage = 100kHz,

2nd Stage = 200kHz,

54V Input Voltage Change,

No Load

Final 25A/30A Stages = 350kHz,

EXTV_CC= 5V

Final 25A/30A Stages = 350kHz,

EXTV_CC= 5V

95

90

85

80

75

95

90

85

80

75

70

65

60

V

30V TO 54V

TRANSIENT

20V/DIV,

IN

50ms/DIV

FIRST STAGE

SWITCH 20V/DIV

SECOND STAGE

SWITCH 20V/DIV

FINAL 25A/30

STAGES

30V INPUT

36V INPUT

48V INPUT

54V INPUT

0.9V OUTPUT

1V OUTPUT

1.2V OUTPUT

1.5V OUTPUT

OUTPUT 1V/DIV

4664A G06

54V TO 1V, NO LOAD

4:1 DIVIDER: FIRST STAGE 100kHz,

SECOND STAGE 200kHz,

0

5

10

15

20

25

0

10

20

30

40

50

FINAL 25A/30A STAGES 250kHz

OUTPUT CURRENT (A)

4664A G04

4664A G05

54V Input Voltage Change,

Load 25A Each

Dual Output Tracking

Start-Up/Shutdown

V

30V TO 54V

TRANSIENT

20V/DIV,

IN

V

= 1V,

OUTC0

V

= 1.5V

50ms/DIV

OUTC1

500mV/DIV,

2ms/DIV

FIRST STAGE

SWITCH 20V/DIV

I

OUT0

5A/DIV

SECOND STAGE

SWITCH 20V/DIV

RUN_Cn

5V/DIV

FINAL 25A/30A

STAGES

OUTPUT 1V/DIV

4664A G08

4664A G07

48V , 10A LOAD ON V

, NO LOAD ON V

,

IN

OUT0

OUTC1

54V TO 1V, 25A LOAD EACH

4:1 DIVIDER: FIRST STAGE 100kHz,

SECOND STAGE 200kHz,

TON_RISE 0 = 3ms, TON_RISE 1 = 4.5ms,

TOFF_DELAY 1 = 0ms, TOFF_DELAY 0 = 1.5ms

TOFF_FALL 1 = 4.5ms, TOFF_FALL 0 = 3ms,

ON_OFF_CONFIGn = 0x1E

FINAL 25A/30A STAGES 250kHz

Rev. 0

15

For more information www.analog.com

LTM4664A

TYPICAL PERFORMANCE CHARACTERISTICS

Dual Output Start-Up/Shutdown

with a Prebiased Load

Start-Up

INPUT VOLTAGE

USED LAB SUPPLY

SWITCH (HP6012B)

20V/DIV, 100ms/DIV

V

= 1.5V

OUTC1

500mV/DIV

V

= 1V

OUTC0

FIRST STAGE OUTPUT

20V/DIV, 100ms/DIV

500mV/DIV

SECOND STAGE

OUTPUT 10V/DIV

I

DIODE

20mA/DIV

FINAL 25A/30A STAGE

OUTPUTS

RUN_Cn

5V/DIV

500mV/DIV

4664A G09

4664A G10

2mS/DIV

48V , 10A LOAD ON V , 7.5mA LOAD ON

OUT1 OUT1

TON_RISE 0 = 3ms, TON_RISE 1 = 4.5ms,

TOFF_DELAY 1 = 0ms, TOFF_DELAY 0 = 1.5ms

TOFF_FALL 1 = 4.5ms, TOFF_FALL 0 = 3ms,

ON_OFF_CONFIGn = 0x1E

48V TO 1V AT 0A LOAD, EACH 25A/30A STAGE

FINAL STAGE TON DELAY AND TON RISE SET

TO 100ms

IN

OUT0

V

, V

PREBIASED THROUGH A DIODE

Shutdown

Full Sequence Turn On

INPUT VOLTAGE

USED LAB SUPPLY

SWITCH (HP6012B)

20V/DIV, 100ms/DIV

RUNS1

2V/DIV, 50ms/DIV

TIMERS1 = 0.047µF

0.5V/DIV

1ST STAGE SWITCH

20V/DIV

FIRST STAGE OUTPUT

20V/DIV, 100ms/DIV

SECOND STAGE

OUTPUT 10V/DIV

1ST STAGE OUTPUT

20V/DIV

FINAL 25A/30A STAGE

OUTPUTS

RUNS2

2V/DIV, 50ms/DIV

500mV/DIV

TIMERS2 = 0.047µF

0.5V/DIV

4664A G11

48V TO 1V AT 0A LOAD, EACH 25A/30A STAGE

FINAL STAGE TON DELAY AND TON RISE SET

TO 100ms

2ND STAGE SWITCH

10V/DIV

2ND STAGE OUTPUT

10V/DIV

Full Sequence Turn Off

RUN_Cn

2V/DIV, 50ms/DIV

RUNS1

2V/DIV, 50ms/DIV

FINAL 25A/30A STAGE SWITCHS

10V/DIV

TIMERS1 = 0.047µF

0.5V/DIV

1ST STAGE SWITCH

20V/DIV

FINAL 25A/30A STAGE OUTPUTS

1V/DIV

4664A G12

48V TO 1V AT 50A LOAD

1ST STAGE OUTPUT

20V/DIV

RUNS2

5V/DIV, 50ms/DIV

TIMERS2 = 0.047µF

0.5V/DIV

2ND STAGE SWITCH

10V/DIV

2ND STAGE OUTPUT

10V/DIV

RUN_C1

2V/DIV, 50ms/DIV

FINAL STAGE SWITCH

10V/DIV

FINAL STAGE OUTPUT

1V/DIV

4664A G13

48V TO 1V AT 50A LOAD

Rev. 0

16

For more information www.analog.com

LTM4664A

TYPICAL PERFORMANCE CHARACTERISTICS

V_OUTCn(1V) Load Transient

V_OUTCn(1.5V) Load Transient

V

OUTCn

50mV/DIV

V

OUTCn

AC-COUPLED

50mV/DIV

AC-COUPLED

I

OUT

5A/DIV

I

OUT

5A/DIV

4664A G14

50µs/DIV

4664A G15

48V TO 1V SINGLE CHANNEL,

0A TO 12.5A/µs LOAD STEP

OUT

COMP_Cna = 2200pF, COMP_Cnb = 100pF,

EA-GM = 3.69ms, RCOMP = 5k,

50µs/DIV

48V TO 1.5V SINGLE CHANNEL, 0A TO 12.5A/µs

LOAD STEP

C

= 470µF ×2 POSCAP, 100µF ×5 CER,

C

OUT

= 470µF ×1 POSCAP, 330µF ×2 CER,

COMP_Cna = 2200pF, COMP_Cnb = 220pF,

EA-GM = 3.02ms, RCOMP = 6k,

PSM FREQ = 350kHz

PSM FREQ = 250kHz, I

OUT

RANGE = LOW

LIMIT

V

RANGE = LOW

Dual Phase (50A/0.9V)

Load Transient

Dual Phase (50A/1V) Load Transient

V

OUT

50mV/DIV

AC-COUPLED

I

OUT

10A/DIV

4664A G17

4664A G16

50µs/DIV

48V TO 1V DUAL PHASE SINGLE OUTPUT, 0A TO

25A/µs LOAD STEP

48V TO 0.9V DUAL PHASE SINGLE OUTPUT, 0A

TO 25A/µs LOAD STEP

C

= 470µF ×2 POSCAP, 5 × 330µF CER,

C

= 470µF ×2 POSCAP, 330µF ×5 CER,

OUT

COMP_C0,1 = 1500pF, COMP_C01b = 100pF,

EA-GM = 4.36ms, RCOMP = 13k,

COMP_C0, 1 = 1500pF, COMP_C01b = 100pF,

EA-GM = 4.36ms, RCOMP = 13k,

PSM FREQ = 350kHz, I

OUT

RANGE = LOW

PSM FREQ = 250kHz, I

OUT

RANGE = LOW

LIMIT

V

RANGE = LOW

V

RANGE = LOW

25A AC Ripple Noise

SWC0

SWC1

V

OUTC0

10mV/DIV

AC-COUPLED

V

OUTC1

10mV/DIV

AC-COUPLED

4664A G18

48V TO V

= 1V, AND V

= 1V

OUTC0

OUTC1

Rev. 0

17

For more information www.analog.com

LTM4664A

TYPICAL PERFORMANCE CHARACTERISTICS

48V to 1V, Second Stage (12V)

Shorted

48V to 1V at 50A Shorted

48V

SWITCH V

OUTC0

INPUT CURRENT

10V/DIV, 20µs/DIV

SWITCH V

5A/DIV, 20µs/DIV

OUTC1

CURRENT ACROSS R

SENSE

5A/DIV, 20µs/DIV

10V/DIV, 20µs/DIV

FINAL STAGE V

0.5V/DIV, 20µs/DIV

OUT

SW1

20V/DIV, 20µs/DIV

PGOOD_C0

2V/DIV, 20µs/DIV

SW3

SW2

20V/DIV, 20µs/DIV

FAULTS1

10V/DIV, 20µS/DIV

5V/DIV, 20µs/DIV

FIRST STAGE V

OUT1

20V/DIV, 20µs/DIV

SW3

SW4

10V/DIV, 20µs/DIV

SECOND STAGE V

OUT2

SW4

10V/DIV, 20µs/DIV

SECOND STAGE V

OUT2

4664A G20

10V/DIV, 20µs/DIV

FAULTS2

48V TO 1V AT 50A SHORTED LAST STAGE 1V

OUTPUT V AND V IN PARALLEL

2V/DIV, 20µs/DIV

OUTC0

OUTC1

SWITCH V

OUTC0

10V/DIV, 20µs/DIV

SWITCH V

OUT1

10V/DIV, 20µs/DIV

FINAL STAGE V AND V

OUTC0

OUTC1

0.5V/DIV, 20µs/DIV

PGOOD_C0

2V/DIV, 20µs/DIV

4664A G19

48V TO 1V AT 50A V

OUTPUT SHORTED

STAGE 12V

OUT2

READ_IOUT of 16 LTM4664A

Channels 12V_IN, 1V_OUT, T_J= –40°C,

Channels 12V_IN, 1V_OUT, T_J= 25°C,

Channels 12V_IN, 1V_OUT, T_J= 125°C,

I_OUTn= 25A, System Having

Reached Thermally Steady-State

Condition, No Airflow

Reached Thermally Steady-State

Condition, No Airflow

Reached Thermally Steady-State

Condition, No Airflow

4

3

4

3

4

3

2

1

2

1

2

1

0

25.4 26.0 25.2 25.2 25.7 25.8 25.9 25.5

READ_IOUT CHANNEL READBACK (A)

25.2 25.7 24.9 24.9 25.3 25.5

READ_IOUT CHANNEL READBACK (A)

24.4 25.0 24.2 24.6 24.7 24.9 24.3 24.3

READ_IOUT CHANNEL READBACK (A)

4664A G21

4664A G22

4664A G23

Rev. 0

18

For more information www.analog.com

LTM4664A

PIN FUNCTIONS

4:1 Divider Section (Stage 1)

Use FAULTS1 or PGOODS1 to sequence on RUNS2 for

the second stage.

GND: (A8-A9, B1-B3, B8-B9, B14-B16, C4-C13,

D4,D8,D9, D13, E1-E4, E8-E9, E13-E16, F1-F4, F8-F10,

G4, G8-G11, H4, H9-H11, J1-J4, J11, K1-K4, K11, L3,

L11, L14-L16, M3-M5, M11, M14, N1-N4, N7, N11-N16,

P1-P4, P7-P9, P13-P15, R1-R6, R9, R13-16, T2-T3,

T8-T9, T14-T15) Main ground pins for all ground returns.

Input and output capacitors are connected to these pin.

See recommended layout Figure 45.

FREQS1: (E12) Frequency Set Pin. There is a precision

10μA current flowing out of this pin. A resistor to ground

sets a voltage which in turn programs the frequency.

See the 4:1 Divider Application Information section for

detailed information.

RUNS1: (F11) Stage 1 Run Control Input. Forcing RUNS1

below 1.2V shuts down the controller. When RUNS1 is

higher than 1.2V, internal circuitry starts up. There is a

1μA pull-up current flowing out of RUNS1 pin when the

RUNS1 pin voltage is below 1.2V and an additional 5μA

current flowing out of RUNS1 pin when the RUNS1 pin

voltage is above 1.2V.

V_OUT1: (C14-C16) 1st stage divide by two output

pins. These pins connect to the 2nd stage V_INS2pins.

Recommend placing output decoupling capacitance

directly between these pins and GND pins.

INTV_CCS1: (D10) Output of the 5.5V internal linear low

dropout regulator. The driver and control circuits are pow-

ered from this voltage source. Must be bypassed to power

ground with a minimum of 4.7μF ceramic or other low ESR

TIMERS1: (F12) Charge Balance and Fault Timer Control

Input. A capacitor between this pin and ground sets the

amount of time to charge V

to (V )/2. It also sets

INS1

OUT1

capacitor. Do not use the INTV

pin for any other ICs.

the short-circuit retry time. See the 4:1 Divider Application

Information.

CCS1

EXTV_CCS1: (D11) External Power Input to the Internal

LDO Connected to INTV . This LDO supplies INTV

HYS_PRGMS1: (G12) A resistor connected between

this pin and ground will set the window threshold of the

window comparator that monitors the voltage difference

CCS1

INS1

power, bypassing the internal LDO powered from V

whenever EXTV_CCS1is higher than 6.5V and V_INS1is

higher than 7V. Do not exceed 30V on this pin. This

pin can be driven with the V_OUT2output to limit power

loss in LDO with V_INS1at higher input voltage. See

Applications section.

between (V

)/2 and V

. There is a 10μA current

INS1

OUT1

flowing out of this pin. See Applications section.

SW1, SW2: (G14-G16), (D14-D16) Switching nodes for

the 1st stage C Flying capacitor. See Block Diagram.

FLY

PGOODS1: (D12) This is an open drain output pin.

PGOODS1 is pulled to ground if there are any faults or

the voltage at UVS1 pin is lower than 1V. Use PGOODS1

or FAULTS1 to sequence on RUNS2 for the second stage.

–

I INSNSS1 : (J13) Current sense comparator negative

input, connected to the negative node of the current sens-

ing resistor. Short to INSNSS1 if not used.

+

NSNSS1⁺: (J14) Current sense comparator positive input,

connected to the positive node of the external current

sensing resistor. The current sensing resistor has to

be placed on the drain of the very top MOSFET. When

the voltage between INSNSS1⁺pin and INSNSS1^–pin

is higher than 50mV, the Stage 1 controller indicates

an overcurrent fault by pulling the FAULTS1 pin down.

UVS1: (E10) Undervoltage Comparator. If the UVS1 pin

voltage is lower than 1V, the PGOODS1 pin is pulled down.

If the UV pin voltage is higher than 1V and no faults,

PGOODS1 pin is released. Connect to INTV_CCS1if not

used. This pin is used to validate proper output regulation.

FAULTS1: (E11) This is an open drain output pin. FAULTS1

is pulled to ground when the V_OUT1voltage is out of

the (V_INS1)/2 window threshold or the voltage between

+

The INSNSS1 pin is also used to source 95mA current

to the V

pin during the pre-balance time in divider

OUT1

+

–

INSNSS1 and INSNSS1 is higher than 50mV. FAULTS1

applications. Connect directly to the drain of the very top

MOSFET if not used. See application schematic section.

pin is released after INTV_CCS1starts up and passes UVLO.

Rev. 0

19

For more information www.analog.com

LTM4664A

PIN FUNCTIONS

V_INS1: (J15-J16) Power input pins to the first stage

divide by two. Place input capacitance between these

pins and GND.

RBOT set to 7.5k. If not used, tie this pin to INTV

. See

CCS2

4:1 Divider Application Information section.

OVP_TRIP: (E7) Open collector output that is used to trip

4:1 Divider Section (Stage 2)

off input power and clamp hold up energy during an over

voltage fault on V . See Applications section.

OUT2

V_INS2: (C1-C3) Power input pins to the second stage

divide by two. Place input capacitance between these pin

and GND.

TIMERS2: (F5) Charge Balance and Fault Timer Control

Input. A capacitor between this pin and ground sets the

amount of time to charge V

to (V )/2. It also sets

INS2

OUT2

SW3, SW4: (D1-D3), (G1-G3) Switching nodes for the

the short-circuit retry time. See the 4:1 Divider Application

Information.

2nd stage C Flying capacitor. See Block Diagram.

FLY

V_INS2F: (D5) Input Voltage Sensing with Filtering. This

pin has a 1kΩ resistor in series from V

capacitor to GND. The pin has a 1MΩ resistance to GND.

See Block Diagram.

INSNSS2^–: (D6) Current sense comparator negative input,

connected to the negative node of the current sensing

resistor. Short to INSNSS2 if not used.

VOUT2_SET: (F6) External – comparator input for setting

, and a 4700pf

INS2

the V

trip reference level. This can be done with a

OUT2

resistor and 5.1V Zener from V_IN. This secondary fault

protection is in and above the Fault protection for Stage

1 and Stage 2. The overall input voltage is divided down

by four, so V

will be 1/4 of V . The OVP_SET pin will

OUT2

IN

+

have a voltage divider to monitor the V

voltage and

OUT2

+

set to trip when the divider midpoint on the OVP_SET pin

exceeds the reference trip level. If not used, tie this pin to

ground. See 4:1 Divider Application Information section.

INSNSS2 : (D7) Current sense comparator positive input,

connected to the positive node of the external current

sensing resistor. The current sensing resistor has to be

placed on the drain of the very top MOSFET. When the

voltage between INSNSS2⁺pin and INSNSS2^–pin is

higher than 50mV, the controller indicates an overcurrent

EXTV

: (F7) External Power Input to the Internal LDO

Conn^Ce^Cc^Ste²d to INTV_CCS2. This LDO supplies INTV_CCS2

power, bypassing the internal LDO powered from V_IN2

whenever EXTV_CCS2is higher than 6.5V and V_INS2is

higher than 7V. Do not exceed 30V on this pin. This pin

+

fault by pulling the FAULTS2 pin down. The INSNSS2

pin is also used to source 95mA current to the V_OUT2

pin during the pre-balance time in divider applications.

Connect directly to the drain of the very top MOSFET if

not used. See Application Schematic section.

can be driven with the V

in LDO with V

Application Information section.

output to limit power loss

OUT2

at higher input voltage. See 4:1 Divider

INS2

HYS_PRGMS2: (E5) A resistor connected between this

pin and ground will set the window threshold of the win-

dow comparator that monitors the voltage difference

FREQS2: (G5) Frequency Set Pin. There is a precision

10μA current flowing out of this pin. A resistor to ground

sets a voltage which in turn programs the frequency.

See the 4:1 Divider Application Information section for

detailed information.

between (V

)/2 and V

. There is a 10μA current

INS2

OUT2

flowing out of this pin. See applications section.

OVP_SET: (E6) External + input for setting the V_OUT2

trip level. The OVP_SET pin will have a voltage divider

to monitor the V_OUT2voltage and set to trip when the

divider midpoint on the OVP_SET pin exceeds the ref-

erence trip level on the VOUT2_SET pin. For example, if

RUNS2: (G6) Stage 2 Run Control Input. Forcing RUNS2

below 1.2V shuts down the controller. When RUNS2 is

higher than 1.2V, internal circuitry starts up. There is a

1μA pull-up current flowing out of RUNS2 pin when the

RUNS2 pin voltage is below 1.2V and an additional 5μA

current flowing out of RUNS2 pin when the RUNS2 pin

voltage is above 1.2V. Use PGOODS1, and FAULTS1 from

stage one to enable stage 2.

the OVP_SET trip point was set for V

, then RTOP =

TRIP

((V_TRIP/5.1V)-1) • 7.5K, with RTOP being the top resistor in

the divider, and RBOT is the bottom resistor in the divider.

Rev. 0

20

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LTM4664A

PIN FUNCTIONS

INTV_CCS2: (G7) Output of the 5.5V internal linear low

dropout regulator. The driver and control circuits are

powered from this voltage source. Must be bypassed to

power ground with a minimum of 4.7μF ceramic or other

low ESR capacitor. Do not use the INTV

other ICs.

(FREQUENCY_SWITCH) and channel phase relation-

ships (with respect to the SYNC clock; MFR_PWM_

CONFIG[2:0]) are dictated at SV power-up according

IN

to the LTM4664A’s NVM contents. Default factory values

are: 350kHz operation; Channel 0 at 0°; and Channel 1 at

180°C (convention throughout this document: a phase

angle of 0° means the channel’s switch node rises coinci-

dent with the falling edge of the SYNC pulse). Connecting

pin for any

CCS2

V_OUT2: (H1-H3) 2nd stage divide by two output pins.

These pins connect to the V input of dual 25A/30A

PMBus converter. Recommend placing output decoupling

capacitance directly between these pins and GND pins.

INS3

a resistor divider from V

to SGND_C0_C1, see page

DD25

4 (and using the factory default NVM setting of MFR_

CONFIG_ALL[6] = 0b) allows a convenient way to con-

figure multiple LTM4664As with identical NVM contents

for different switching frequencies of operation and phase

interleaving angle settings of intra- and extra-module-par-

alleled channels—all, without GUI intervention or the

need to “custom preprogram” module NVM contents.

(See the Dual 25A/30A PSM Applications Information

section.) Minimize capacitance—especially when the pin

is left open—to assure accurate detection of the pin state.

PGOODS2: (H5) This is an Open Drain Output Pin.

PGOODS2 is pulled to ground if there are any faults or

the voltage at UVS2 pin is lower than 1V. Use PGOOD2 or

FAULTS2 to sequence on RUN_C0, and RUN_C1 for the

dual 25A/30A stage.

FAULTS2: (H6) This is an Open Drain Output Pin. FAULTS2

is pulled to ground when the V_OUT2voltage is out of

the (V_INS2)/2 window threshold or the voltage between

+

–

INSNSS2 and INSNSS2 is higher than 50mV. FAULTS2

pin is released after INTV_CCS2starts up and passes UVLO.

Use FAULTS2 or PGOOD2 to sequence on RUN_C0, and

RUN_C1 for the dual 25A/30A PSM stage.

VTRIMC1_ CFG (J5): Output Voltage Select Pin for V_OUTC1

,

Fine Setting. Works in combination with VOUTC1_CFG

to affect the VOUT_COMMAND (and associated output

voltage monitoring and protection/fault-detection thresh-

olds) of Channel 1, at SV power-up. (See VOUTC1_CFG

IN

UVS2: (H7) Undervoltage Comparator. If the UVS2 pin

voltage is lower than 1V, the PGOODS2 pin is pulled

down. If the UV pin voltage is higher than 1V and no faults,

PGOODS2 pin is released. Connect to INTV_CCS2if not

used. This pin is used to validate proper output regulation.

and the Dual 25A/30A PSM Applications Information sec-

tion.) Minimize capacitance—especially when the pin is

left open—to assure accurate detection of the pin state.

Note that use of RCONFIGs on VOUTC1_CFG/VTRIMC1_

CFG can affect the V_OUTC1range setting (MFR_PWM_

PMBus Dual 25A/30A Section

MODE1 [1]) and loop gain. A resistor divider from V

DD25

to SGND_C0_C1 can set the trim value, see page 43.

V

(A1-A7, B4-B7): Channel 1 Output Voltage. Place

OUTC1

recommended output capacitors from this connection to

VOUTC0_CFG (J6): Output Voltage Select Pin for V_OUTC0

,

GND. See recommended layout in Figure 45.

Coarse Setting. If the VOUTC0_CFG and VTRIMC0_CFG

pins are both left open—or, if the LTM4664A is con-

figured to ignore pin-strap (RCONFIG) resistors, i.e.,

MFR_CONFIG_ALL[6] = 1b—then the LTM4664A's tar-

V

: (A10-A16, B10-B13): Channel 0 Output Voltage.

OUTC0

Place recommended output capacitors from this connec-

tion to GND. See recommended layout in Figure 45.

get V

output voltage setting (VOUT_COMMAND0)

OUTC0

FSWPH_CFG (H8): Switching Frequency, Channel

Phase Interleaving Angle and Phase Relationship to

SYNC Configuration Pin. If this pin is left open—or, if

the dual 25A/30A regulator is configured to ignore pin-

strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6]

= 1b—then the LTM4664A’s switching frequency

and associated power good and OV/UV warning and fault

thresholds are dictated at SV_INpower-up according to

the LTM4664A’s NVM contents. A resistor connected

from this pin to SGND—in combination with resistor pin

settings on VTRIMC0_CFG, and using the factory-default

NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used

Rev. 0

21

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LTM4664A

PIN FUNCTIONS

to configure the LTM4664A’s Channel 0 output to pow-

er-up to a VOUT_COMMAND value (and associated output

voltage monitoring and protection/fault-detection thresh-

olds) different from those of NVM contents. (See the 4:1

Divider Application Information section.) Minimize capac-

itance especially when the pin is left open to assure accu-

rate detection of the pin state. Note that use of RCONFIGs

outputs of the LTM4664A. These open-drain output pins

hold the pin low until the LTM4664A is out of reset and

IN3_C1

V

is detected to exceed VIN_ON. A pull-up resis-

tor to 3.3V is required in the application. The LTM4664A

pulls RUN_C0 and/or RUN_C1 low, as appropriate, when

a global fault and/or channel-specific fault occurs whose

fault response is configured to latch off and cease reg-

2

on VOUTC0_CFG/VTRIMC0_CFG can affect the V

ulation; issuing a CLEAR_FAULTS command via I C or

OUTC0

range setting (MFR_PWM_MODE0 [1]) and loop gain.

power cycling SV is necessary to restart the module, in

IN

such cases. Do not pull RUN logic high with a low imped-

ance source. Use PGOODS2 and FAULTS2 to sequence on

RUN_C0, and RUN_C1 for the dual 25A/30A stage.

VOUTC1_CFG (J7): Output Voltage Select Pin for V_OUTC1

,

Coarse Setting. If the VOUTC1_CFG and VTRIMC1_CFG

pins are both left open or, if the LTM4664A is config-

ured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_

ALERT (J10): Open-Drain Digital Output. A pull-up

resistor to 3.3V is required in the application only if

SMBALERT interrupt detection is implemented in one’s

SMBus system.

CONFIG_ALL [6] = 1b then the LTM4664A’s target V

OUTC1

output voltage setting (VOUT_COMMAND1) and associ-

ated OV/UV warning and fault thresholds are dictated at

SV power up according to the LTM4664A’s NVM con-

IN

VTRIMC0_CFG (K5): Output Voltage Select Pin for V_OUTC0

,

tents, in precisely the same fashion that the VOUTC1_CFG

Fine Setting. Works in combination with VOUTC0_CFG

to affect the VOUT_COMMAND (and associated output

voltage monitoring and protection/fault-detection thresh-

and VTRIMC1_CFG pins affect the respective settings of

V /Channel 1. (See VOUTC1_CFG, VTRIMC1_CFG and

OUT1

the 4:1 Divider Application Information section.) Minimize

capacitance—especially when the pin is left open—to

assure accurate detection of the pin state. Note that use

of RCONFIGs on VOUTC1_CFG/VTRIMC1_CFG can affect

olds) of Channel 0, at SV power-up. (See VOUTC0_CFG

IN

and the Dual 25A/30A PSM Applications Information sec-

tion.) Minimize capacitance especially when the pin is left

open to assure accurate detection of the pin state. Note

that use of RCONFIGs on VOUTC0_CFG/VTRIMC0_CFG

the V

range setting (MFR_PWM_MODE1 [1]) and

OUTC1

loop gain. A resistor divider from V

See page 43.

to SGND_C0_C1.

DD25

can affect the V

range setting (MFR_PWM_MODE0

OUTC0

[1]) and loop gain.

ASEL (J8): Serial Bus Address Configuration Pin. On any

given I²C/SMBus serial bus segment, every device

must have its own unique slave address. If this pin is

left open, the LTM4664A powers up to a slave address

set by MFR_ADDRESS[6:0] (see Table 4). The facto-

ry-default setting is 0x4F (hexadecimal), i.e., 1001111b

(industry standard convention is used throughout this

document: 7-bit slave addressing). The lower four bits of

the LTM4664A’s slave address can be altered from the

NVM-set value by connecting a resistor from this pin to

SGND. Minimize capacitance—especially when the pin is

left open—to assure accurate detection of the pin state.

See 4:1 Divider Application Information section.

V_DD25(K6): Internally Generated 2.5V Power Supply

Output Pin. Do not load this pin with external current;

it is used strictly to bias internal logic and provides cur-

rent for the internal pull-up resistors connected to the

configuration-programming pins. No external decoupling

is required.

WP (K7): Write Protect Pin, Active High. An internal 10μA

current source pulls this pin to V

. If WP is open cir-

DD33

2

cuit or logic high, only I C writes to PAGE, OPERATION,

CLEAR_FAULTS, MFR_CLEAR_PEAKS and MFR_EE_

UNLOCK are supported. Additionally, Individual faults

can be cleared by writing 1b’s to bits of interest in reg-

isters prefixed with “STATUS”. If WP is low, I²C writes

are unrestricted.

RUN_C0, RUN_C1 (J9, K8 Respectively): Enable Run

Input for Channels 0 and 1, respectively. Open-drain input

and output. Logic high on these pins enables the respective

Rev. 0

22

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LTM4664A

PIN FUNCTIONS

FAULT_C0/FAULT_C1 (K10/K9): Digital Programmable

FAULT Inputs and Outputs. Open-drain output. A pull-up

resistor to 3.3V is required in the application.

above 100kHz is required, the user’s SMBus master(s)

needs to implement clock stretching support to assure

solid serial bus communications, and only then should

MFR_CONFIG_ALL [1] be set to 1b. When clock stretch-

ing is enabled, SCL becomes a bidirectional, open-drain

output pin on LTM4664A.

V_INS3__C1, V_INS3__C0: (L1-L2, M1-M2), (L12-L13, M12-

M13): Main power input to channel 0, and channel 1

power stages. Provide sufficient decoupling capacitance

in the form of multilayer ceramic capacitors (MLCCs) and

low ESR electrolytic (or equivalent) to handle reflected

input current ripple from the step-down switching

stages. MLCCs should be placed as close to the V_INS3

TSNS_C0a, TSNS_C0b (L10 and T16, Respectively):

Channel 0 Temperature Excitation/Measurement and

Thermal Sensor Pins, respectively. Connect TSNS_C0a

to TSNS_C0b. This allows the LTM4664A to monitor the

Power Stage Temperature of Channel 0.

as physically possible. The V

input provides the

INS3_C1

input power for the INTV LDO regulator. See Layout

CC

SYNC (M8): External Clock Synchronization Input and

Open-Drain Output Pin. If an external clock is present at

this pin, the switching frequency will be synchronized to

the external clock. If clock master mode is enabled, this

pin will pull low at the switching frequency with a 500ns

pulse to ground. A resistor pull-up to 3.3V is required in

the application if the LTM4664A is the master.

Recommendations in the Dual 25A/30A PSM Applications

Information section.

V

(L6): Internally Generated 3.3V Power Supply Output

P^Din^D.³³This pin should only be used to provide external

current for the pull-up resistors required for FAULT_Cn,

SHARE_CLK, and SYNC, and may be used to provide exter-

nal current for pull-up resistors on RUN_Cn, SDA, SCL,

ALERT and PGOOD_Cn. No external decoupling is required.

SGND_C0_C1 (M9, N8-N9): SGND_C0_C1 is the signal

ground return path of the dual 25A/30A control. SGND_C0_

C1 is not internally connected to GND. Connect SGND_C0_C1

to GND at the A9, B9, and C9 pins that is close to the output

capacitor ground connections. See recommended layout.

SHARE_CLK (L7): Share_Clock, Bidirectional Open- Drain

Clock Sharing Pin. Nominally 100kHz. Used for synchro-

nizing the time base between multiple LTM4664As (and

any other Analog Devices products with a SHARE_ CLK

pin)—to realize well-defined rail sequencing and rail track-

ing. Tie the SHARE_CLK pins of all such devices together;

all devices with a SHARE_CLK pin will synchronize to the

fastest clock. A pull-up resistor to 3.3V is required.

TSNS_C1a, TSNS_C1b (M10 and T1, Respectively):

Channel 1 Temperature Excitation/Measurement and

Thermal Sensor Pins, respectively. In most applica-

tions, connect TSNS_C1a to TSNS_C1b. This allows the

LTM4664A to monitor the Power Stage Temperature of

Channel 1. See the Applications section.

SDA (L8): Serial Bus Data Open-Drain Input and Output.

A pull-up resistor to 3.3V is required in the application.

PWM_C0, PWM_C1 (M15, L4): PWM drive signal to

Channel 0, Channel 1 power stage. Utilized for debugging

or monitoring purposes.

SCL (L9): Serial Bus Clock Open-Drain Input (Can Be an

Input and Output, if Clock Stretching is enabled). A pull-up

resistor to 3.3V is required in the application for digital

communication to the SMBus master(s) that nominally

drive this clock. The LTM4664A will never encounter sce-

narios where it would need to engage clock stretching

unless SCL communication speeds exceed 100kHz—and

even then, LTM4664A will not clock stretch unless clock

stretching is enabled by means of setting MFR_CONFIG_

ALL[1] = 1b. The factory-default NVM configuration set-

ting has MFR_CONFIG_ALL [1] = 0b: clock stretching

disabled. If communication on the bus at clock speeds

PHFLT_C0, PHFLT_C1 (M16, L5): Thermal Warning for

Channel 0 and Channel 1. When the thermal protection

threshold is tripped, the PHFLT_Cn pin is being pulled

low. The power stage does not shut off, and is only a

thermal monitor. These pins are internally pulled up to

3.3V through 10k resistor. COMP_0b/COMP_1b (N10/

M7): Current Control Threshold and Error Amplifier

Compensation Nodes. Each associated channel’s current

comparator tripping threshold increases with its Comp

voltage. Each channel has a 22pF to SGND.

Rev. 0

23

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LTM4664A

PIN FUNCTIONS

V_OSNS^–_C1 (N6): Channel 1 Negative Differential. Voltage

EXTV (R8): External Power Input to an Internal Switch

Sense Input. See V

_C1.

Conn^Ce^Ccted to INTV . This switch closes and supplies

+

OSNS

CC

the IC power, bypassing the internal regulator whenever

EXTV_CCis higher than 4.7V and V_INis higher than 7V.

EXTV_CCalso powers up V_DD33when EXTV_CCis higher than

+

V

OSNS

_C1 (P6): Channel 1 Positive Differential Voltage

+

–

Sense Input. Together, V

_C1 and V

_C1 serve

OSNS

to kelvin sense the V_OUTC1output voltage at V_OUTC1’s point

of load (POL) and provide the differential feedback signal

directly to Channel 1’s feedback loop. Command V_OUTC1’s

target regulation voltage by serial bus. Its initial command

4.7V and INTV is lower than 3.8V. Do not exceed 6V

CC

on this pin. Decouple this pin to PGND with a minimum

of 4.7μF low ESR tantalum or ceramic capacitor. If the

EXTV pin is not used to power INTV , the EXTV pin

CC

value at V

power-up is dictated by NVM (non-volatile

INS3

must be tied GND. Its recommended to use this pin if a

memory) contents (factory default: 1.000V)—or, option-

ally, may be set by configuration resistors; see VOUTC1_

CFG and the 4:1 Divider Application Information section.

bias is available to reduce power loss.

+

IN (R10): Positive Current Sense Amplifier Input. If the

input current sense amplifier is not used, this pin must

be shorted to the IN^–and V_INS3pins. See 4:1 Divider

Application Information section for detail about the input

current sensing.

IN^–(P10): Negative Current Sense Amplifier Input. If

the input current sense amplifier is not used, this pin

+

must be shorted to the IN and V pins. See 4:1 Divider

IN3

Application Information section for detail about the input

current sensing.

PGOOD_C0/PGOOD_C1 (R11/N5): Power Good Indicator

Outputs. Open-drain logic output that is pulled to ground

when the output exceeds the UV and OV regulation win-

dow. The output is deglitched by an internal 100μs filter.

A pull-up resistor to 3.3V is required in the application.

COMP_0a/COMP_1a (P11/M6): Loop Compensation

Nodes. The internal PWM loop compensation resistors

RCOMPn of the LTM4664A can be adjusted using bit

[4:0] of the MFR_PWM_COMP command. The transcon-

ductance of the LTM4664A PWM error amplifier can be

adjusted using bit [7:5] of the MFR_PWM_COMP com-

mand. These two loop compensation parameters can be

programmed when device is in operation. Refer to the

Programmable Loop Compensation subsection in the 4:1

Divider Application Information section for further details.

See MFR_PWM_COMP section.

V_OSNS⁺_C0: (R12) Channel 0 Positive Differential Voltage

Sense Input. Together, V_OSNS⁺_C0 and V_OSNS^–_C0 serve to

kelvin-sense the V

output voltage at V ’s point

OUTC0

of load (POL) and provide the differential feedback signal

directly to Channel 0’s feedback loop. Command V_OUTC0’s

target regulation voltage by serial bus. Its initial command

value at V

power-up is dictated by NVM (non-volatile

INS3

memory) contents (factory default: 1.000V)—or, option-

ally, may be set by configuration resistors; see VOUTC0_

CFG and the 4:1 Divider Application Information section.

V_OSNS^–_C0: (P12): Channel 0 Negative Differential Voltage

+

Sense Input. See V

_C0.

OSNS

GL_C0, GL_C1 (P16, P5): Bottom MOSFET gate drive

in the Channel 0 power stage, Channel 1 power stage.

Utilized for debugging or monitoring purposes.

SWC0, SWC1 (T10-T13), (T4-T7): Switching Node of

Channel 0 and Channel 1. Used for test purposes or

EMI snubbing.

INTV (R7): Internal Regulator, 5.5V output. When oper-

ating^Ct^Che V

from 7V ≤ V

INS3_C1

≤ 16V, a LDO generates

INS3

INTV from V

INS3

to bias internal control circuits and

CC

the MOSFET drivers of the dual 25A/30A power supply. An

external 2.2µF ceramic decoupling is required. INTV is

CC

regulated regardless of the RUN_Cn pin state.

Rev. 0

24

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LTM4664A

4:1 DIVIDER BLOCK DIAGRAM

Rev. 0

25

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LTM4664A

DUAL 25A/30A POWER SYSTEM MANAGEMENT (PSM) BLOCK DIAGRAM

W P

T

O

I

O

I

O U

V

O U

V

I N

V

I

Rev. 0

26

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LTM4664A

4:1 DIVIDER OPERATION

4:1 DIVIDER DESCRIPTION

voltage is always close to half of the top voltage at the

drain of MOSFET M1 (refer to GND pin) and in steady state

and it is not sensitive to variable loads due to the very

low impedance at its output. Stage 2 operates exactly the

same way, the N-channel MOSFETs M5 and M7 are turned

on and off in the same phase with around 50% duty cycle

at a pre-programmed 300kHz switching frequency. The

N-channel MOSFETs M6 and M8 are turned on and off

complementary to MOSFETs M5 and M7. The main input

The LTM4664A incorporates a high performance 4:1

switched capacitor divider that divides down the input

voltage by a factor of four over an input voltage range of 30V

to 58V. This 4:1 divider then powers a dual 25A/30A PMBus

compliant core power rails that can regulate from 0.5V to

1.5V at up to 25A, per channel—and from 0.5V to 1.2V at

up to 30A per channel. The LTM4664A will convert this

high input range down directly to the low output voltages.

voltage rail is connected to V

, and V

is connected

INS1

directly into the V

. The LTM4664A^Of^Uro^T1nt end divider

INS2

MAIN CONTROL

stages do not regulate the output voltage with a closed-

loop feedback system. However, it stops switching when

The LTM4664A internal 4:1 divider utilizes two constant

frequency, open loop switched capacitor/charge pump

stages for high voltage step down. The conversion effi-

ciency is very high at ~ 99% for stage 1, and ~98.6% effi-

cient for stage 2. Refer to Figure 1 for the block diagram.

In stage 1 steady state operation, the N-channel MOSFETs

M1 and M3 are turned on and off in the same phase with

around 50% duty cycle at a pre-programmed 100kHz

switching frequency. The N-channel MOSFETs M2 and

M4 are turned on and off complementary to MOSFETs M1

and M3. The gate drive waveforms are shown in Figure 3.

fault conditions occur, such as V

pin overvoltage or

OUT

undervoltage, an overcurrent event, or an over tempera-

ture protection event.

The V_OUT2(V_INS1/4) is connected to the V_{INS3_Cn}which is

the inputs to the dual 25A/30A PMBus channels. This will

be discussed in more detail in the dual 25A/30A operation

section. There is a secondary fault protection comparator

circuit that can be used to monitor V_OUT2for over voltage.

This will be discussed in more detail in the application

section. The LTM4664A can operate over a 30V to 58V

input range that does have abrupt input voltage changes

that move quicker than a few milliseconds after reaching

steady state. See the window comparator section.

During phase 1, M1 and M3 are on and the flying capaci-

tor C

is in series with C

. During phase 2, M2 and

FLY1

OUT1

M4 are on and C

is in parallel with C

. The V

FLY1

OUT1 OUT1

V

GS

INTV /EXTV

CCS1,2

POWER

CCS1,2

~ 50% DUTY CYCLE

Power for the quad N-channel MOSFET drivers and most

other internal circuitry is derived from the INTV pin.

M1

M2

M3

M4

CCSn

Normallyaninternal5.5VlinearregulatorsuppliesINTV_CCS1,2

power from either V or V as indicated in Figure 1.

T

S

INS1

INS2

Both of these input supplies have high input voltage, and

increases power loss due to the LDO drop. An optional

external voltage source on EXTV

pin enables a sec-

CCS1,2

ond 5.5V linear regulator and supplies INTV

power

CCS1,2

from the EXTV

pin. To enable this more efficient

CCS1,2

second regulator, V

has to be higher than 7V and

INS1,2

the EXTV_CCS1,2pin voltage has to be higher than 6.5V.

Do not exceed 40V on the EXTV pin. Figure 1 shows

CCSn

the V

EXTV

supply (12V) connected to both EXTV

and

OUT2

CCS2

CCS1

PHASE 1

PHASE 2

PHASE 1

PHASE 2

4664A F03

to lower power loss in the LDO after startup.

Figure 3. Stage 1 MOSFET Switching Waveforms

Rev. 0

27

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LTM4664A

4:1 DIVIDER OPERATION

Each of these can supply a peak current of 150mA. No

matter what type of bulk capacitor is used, an additional

0.1μF ceramic capacitor placed directly adjacent to the

FAULT PROTECTION AND THERMAL SHUTDOWN

The LTM4664A divider stages monitor system voltage,

current and temperature for faults. The stage 1 or 2 stops

switching and pulls down its FAULT pin when fault condi-

INTV

and GND pins is highly recommended. Good

CCSn

bypassing is needed to supply the high transient currents

required by the MOSFET gate drivers. These high input

voltages along with the power MOSFETs being driven at

high frequencies may cause the maximum junction tem-

perature rating for the LTM4664A to be exceeded. The

tions occur. To clear voltage faults, the V

pin voltage

OUTn

has to be within the programmed window around half of

the V voltage or the V and V voltages must

INSn

OUTSn

be lower than 1V and 0.5V respectively. To clear current

faults, the voltage drop from INSNSn⁺pin to INSNSn^–pin

has to be lower than 50mV. To clear temperature faults,

the IC temperature has to be lower than 165°C. The FAULT

pin is allowed to be pulled up by external resistors to

voltages up to 60V. It can also be used to control discon-

nect FETs that isolates the input and output during fault

conditions. See Figure 1 block diagram.

INTV

current, which is dominated by the gate charge

CCSn

current, may be supplied by either the 5.5V linear regu-

lator from V or the linear regulator from EXTV

.

CCSn

INSn

When the voltage on the EXTV

pin is less than 6.5V,

CCSn

the linear regulator from V

is enabled. Power dissipa-

INSn

tion for the internal controller in this case is highest and

is equal to V • IINTV . The gate charge current is

INSn

CCSn

dependent on operating frequency. This is why it is highly

recommended to use the V voltage to supply power

HIGH SIDE CURRENT SENSING

OUT2

to the EXTV

pins.

For over current protection, the LTM4664A uses a sensing

resistor R_SENSEto monitor the current. The sensing resis-

tor has to be placed at the drain of the very top MOSFET

M1. See Typical Application section for examples. In most

applications, the current through the sensing resistor is a

CCS1,2

START-UP AND SHUTDOWN

The LTM4664A divider stages are in shutdown mode

when their RUNS pins are pulled down and lower than

1.1V. In this mode, most internal circuitry is turned off

pulse current and the peak value is much higher than the

–

average load current. An internal RC filter on the I

SENSE

including the INTV

regulators and the 4:1 divider

CCS1,2

pin, with a time constant lower than switching frequency,

consumes less than 200μA current per stage. All gates

drives are actively pulled low to turn off the external

power MOSFETs in shutdown. Releasing RUNS1,2 allows

an internal 1μA current to pull up these pins and enable

the controller stage. Once the RUNS1,2 pin raises above

1.22V, an additional 5μA is flowing out of the respective

pin. Alternately, the RUNS pin may be externally pulled

up or driven directly by logic. Do not exceed the Absolute

Maximum Rating of 6V on these pins. After RUNS1,2 pin

is released and the INTV_CCS1,2voltage passes UVLO,

is used to set the precision average current protection. If

+

over current protection is not desired, short the I

SENSE

–

and I

pins together and connect them to the drain

SENSE

of top MOSFET M1 directly. This is done in stage 2 since

stage 1 already monitors for current faults. See Figure 1.

FREQUENCY SELECTION

The selection of switching frequency is a trade-off

between efficiency and component size. Low frequency

operation increases efficiency by reducing MOSFET

switching losses, but requires larger capacitance to main-

tain low output ripple voltage and low output impedance.

The FREQSn pin can be used to program the controller’s

operating frequency from 100kHz to 1MHz. There is a

precision 10μA current flowing out of the FREQSn pin, so

the user can program the controller’s switching frequency

then that particular stage starts up and monitors the V

INn

and V

voltage continuously. The LTM4664A divider

OUTn

stages start switching only if the V

voltage is close

OUTn

voltage or both V

to half of the V

and V

volt-

INSn

OUTn

INSn

ages are close to GND. In voltage divider applications,

V_OUT1,2is pre-balanced to half the V_INS1,2voltage and the

LTM4664A divider stages may start up with capacitors at

different initial conditions and balancing will be invoked

if necessary.

Rev. 0

28

For more information www.analog.com

LTM4664A

4:1 DIVIDER OPERATION

with a single resistor to GND. The voltage on the FREQSn

pin is equal to the resistance multiplied by 10μA cur-

rent (e.g. the voltage is 1V with a 100k resistor from the

FREQSn pin to GND). A curve is provided below showing

the relationship between the voltages on the FREQSn pin

and switching frequency. Stage 1 is operated at 100kHz,

and Stage 2 is operated at 200kHz for optimal efficiency.

See Figure 4.

POWER GOOD AND UV (PGOODSn AND UVSn PINS)

When the UVSn pin voltage is lower than 1V, the PGOODSn

pin is pulled low. The PGOODSn pin is also pulled low

when the RUNSn pin is low or when the LTM4664A divider

stages are starting up. The PGOODSn pin is released only

when the LTM4664A stage is switching and UVSn pin is

higher than 1V. The PGOODSn pin will flag power bad

immediately when the UVSn pin is low. However, there is

an internal 20μs power good mask and 100mV hystere-

sis when UVSn is higher than 1V. The PGOODSn pin is

1400

1200

1000

800

600

400

200

0

pulled up by external resistor to INTV . The UVS1 pin

CC

is used to monitor the V

level for proper regulation,

OUT1

the PGOODS1 signal is used to sequence on the stage 2's

RUNS2 pin. Then PGOODS2 is used to sequence on the

downstream dual 25A/30A regulators. Proper setup on

the UV pin to set a specific regulation point will release

the PGOODn pin when the output voltage is at that value.

See Figure 1 block diagram.

0

0.5

1

1.5

2

2.5

FREQ PIN VOLTAGE (V)

ADDITIONAL OVERVOLTAGE PROTECTION

4664A F04

The OVP_SET, VOUT2_SET, and OVP_TRIP pins can be

Figure 4. Relationship Between Switching

Frequency and Voltage at FREQ Pin

used to monitor the V

voltage for an overvoltage fault.

These pins can be us^Oe^Ud^Ti²n conjunction with the circuit in

Figure 46 to provide a secondary OVP protection in and

above the 4:1 divider fault protection. This feature can be

used to trip off the input power, and further protect the

low voltage outputs.

f_SW(kHz) = R_FREQ(kΩ) • 8 – 317kHz

Rev. 0

29

For more information www.analog.com

LTM4664A

4:1 DIVIDER APPLICATION INFORMATION

A Typical Application in the Figure 1 block diagram shows

the 4:1 voltage divider circuit. For the 1st stage voltage

divider, the VINS1 input voltage is at the drain of very top

When switches M2 and M4 are on or it is limited by the

power MOSFET saturation current in the 1st stage, and

M6 and M8 in the 2nd stage:

MOSFET M1 and the output voltage is at the V

OUT1

V_CFLYn– V_OUTn

I=

which is connected to the source of MOSFET M2 and the

drain of MOSFET M3. The output voltage is around half of

the input voltage in steady state. For the 2nd stage voltage

R

_ONMn+R_ONMn

With very low R

of the power MOSFETs, the inrush

DS(ON)

divider, the V

input voltage is at the drain of very top

INS2

charge current could easily achieve several hundreds of

Amperes which can be higher than the MOSFET’s Safe

Operating Area (SOA).

MOSFET M5 and the output voltage is at the V

OUT2

which is connected to the source of MOSFET M6 and the

drain of MOSFET M7. This completes the 4:1 divider.

The LTM4664A provides a proprietary pre-balance

method to minimize the inrush charging current in voltage

divider applications. The LTM4664A controller detects

the V_OUTnpin voltage before switching and compares

For divider applications, if the load current is applied

before startup or heavy resistive loads are connected to

the VOUTn pin, the divider stages may not start up due to

the limited drive current of the pre-balance circuit.

it with the V

/2 internally. If the V

pin voltage is

INSn

OUTn

Therefore the PGOODS1 signal is used to sequence on

stage 2 RUN2 pin, and the PGOODS2 pin is used to stage

on the dual 25A/30A regulator.

much lower than the V_INSn/2, a current source will source

95mA current to the V pin to pull the V pin up.

OUTn

If the V

pin voltage is much higher than the V

/2,

OUTn

INSn

pin to

another current source will sink 50mA from V

OUTn

pull the V

pin down.

VOLTAGE DIVIDER PRE-BALANCE BEFORE SWITCHING

OUTn

If the V_OUTnpin voltage is close to V_INSn/2 and within

the pre-programmed window, both current sources are

disabled and the divider stages start switching. After 68

In voltage divider applications, the V

voltage should

OUTn

be always close to V

/2 in the steady state. The volt-

INSn

ages on the flying capacitors (C_FLYn) and V_OUTncapacitors

are all very close to each other and equal to the half of

the input voltage. The charging inrush current is mini-

mized during each switching cycle because the voltage

difference between capacitors is small. However, without a

special charging method such as the LTM4664A control-

ler pre-charging circuitry, during start-up or fault condi-

tions such as V_OUTnshort to GND, the difference between

capacitors can be large and huge charging currents may

be large enough to cause very large MOSFETs currents.

When switches M1 and M3 are on in the 1st stage, and

M5 and M7 are on in the 2nd stage. Ideally, the inrush

charge current is:

switching cycles and the V

pin is still within the win-

OUTn

dow, the FAULTSn pin is released.

For the 4:1 voltage divider with pre-balance startup, the

LTM4664A assumes no load current or very small load

current (less than 50mA) at the V

(output) otherwise

the V_OUTncannot reach V_INSn/2^Oa^Un^Tnd LTM4664A never

starts up. This no load condition can be achieved by con-

necting the PGOODn pin to the enable pins of the follow-

ing electrical loads. If load current cannot be controlled off

such as resistive loads, a disconnected FETs is required to

disconnect the load to the V

during startup as shown

in the typical applications. ^OT^Uh^Teⁿinput power source can

operate over the 30V to 58V range, but the supply varia-

tion needs to be constrained to move much slower than

the switching frequency and not exceed the hysteresis set

by the HYS_PRGMSn pin. Large fast voltage excursions

changes will force the 4:1 divider into pre-balance phase.

V

_INSn– V_CFLYn– V_OUTn

I=

R

_ONMn+R_ONMn

Rev. 0

30

For more information www.analog.com

LTM4664A

4:1 DIVIDER APPLICATION INFORMATION

Usually front end circuit breakers control the rate change

and slew rate on the main input power which will eliminate

this problem. As long as the input supply moves much

slower than the operating frequency of the 4:1 divider,

then the regulator will be able to balance without a need

to pre-balance.

WINDOW COMPARATOR PROGRAMMING

In normal operation, V_OUTnvoltage should be always

close to half of the V_INSnvoltage. A floating window

comparator monitors the voltage on the V

pin and

OUTn

compares it with V_INSn/2. The window hysteresis volt-

age can be programmed and is equal to the voltage at

the HYS_PRGMSn pin. There is a precision 10μA cur-

rent flowing out of HYS_PRGMSn pin. A single resistor

from HYS_PRGMSn pin to GND sets the HYS_PRGMSn

pin voltage, which equals the resistor value multiplied by

10μA current (e.g. the voltage is 1V with a 100k resis-

tor from the HYS_PRGMSn pin to GND). With a 100k

resistor on the HYS_PRGMSn pin, the V_INSn/2 voltage

OVERCURRENT PROTECTION

The LTM4664A 4:1 divider provides overcurrent protection

through a sensing resistor placed on the high voltage side.

A precision rail to rail comparator monitors the differential

+

–

voltage between INSNSSn pin and INSNSSn pin which

are Kelvin connected to a sensing resistor. Whenever the

INSNSSn⁺pin voltage is 50mV higher than INSNSSn^–pin

voltage, overcurrent fault is triggered and the FAULTSn pin

is pulled down to ground. At the same time the divider

stage stops switching and starts retry mode based on

the timer pin setup. The overcurrent fault will be cleared

when the TIMERSn pin voltage reaches 4V and the voltage

across the sensing resistor is less than 50mV.

has to be within (V

1V) window during startup and

OUTn

normal operation, otherwise a fault is triggered and the

LTM4664A divider stages stop switching.

The window hysteresis voltage can be linearly pro-

grammed from 0.3V to 2.4V with different resistor values

on HYS_PRGMNSn pin. If the HYS_PRGMSn pin is tied

to INTV , a default 0.8V hysteresis window is applied

CC

internally. The hysteresis window voltage has to be pro-

The current through the sensing resistor is a pulse cur-

rent during charging/discharging of the flying capacitors,

which may result a voltage higher than the 50mV thresh-

old at heavy loads. To prevent the inrush current from

falsely triggering the overcurrent protection, an RC filter

grammed large enough to tolerate the V

pin voltage

OUTn

ripple and voltage drop at maximum load conditions. See

Figure 5. Small internal RC filters can be used on these two

pins to reject noise higher than the switching frequency.

+

–

is required at the INSNSSn pin and INSNSSn The RC

filter timer constant has to be larger than a switching

period. Typically a 100Ω and 0.1μF filter is good for most

of applications, and this filter is already included inside the

LTM4664A. The current limit can be selected by choos-

ing different sense resistor values. For example, 10mΩ

sensing resistor sets current limit at 50mV/10mΩ = 5A

ideally. Due to the switching ripple, the actual current limit

is always lower than the ideal case. In real circuits, the

current limit is around 4.2A with the 0.1μF/100Ω filter and

200kHz switching frequency. If overcurrent protection is

not used, short INSNSSn pin and INSNSSn pin together

and connect them to the drain of the top as shown in

Figure 1 stage 2. Stage 2 current limit is not usually nec-

essary since stage 1 already has it implemented. Also

the dual 25A/30A regulators have overcurrent protection

discussed later in the data sheet.

2.5

2

1.5

1

0.5

0

1

2

3

(V)

4

5

+

–

V

HYS_PRGM

4664A F05

Figure 5. Relationship Between HYS_PRGM Pin Voltage

and VOUTn_SENSE Window Comparator Voltage

Rev. 0

31

For more information www.analog.com

LTM4664A

4:1 DIVIDER APPLICATION INFORMATION

EFFECTIVE OPEN LOOP OUTPUT RESISTANCE AND

conditions, the output voltage will drop from V

/2 by

INSn

LOAD REGULATION

R

• I

. In many applications, multi-layer ceramic

TH

LOAD

capacitors (MLCC) are selected as flying capacitors. The

voltage coefficients of MLCC capacitors strongly depend

on the type and size of capacitors. Normally larger size

X7R MLCC capacitors are better than X5R in terms of

voltage coefficient. The capacitance still drops 20% to

30% capacitance with high DC bias voltage. Capacitance

derating needs to be considered when estimating the out-

put resistance of the switched capacitor circuits.

The LTM4664A divider stages do not regulate the output

voltage through a closed loop feedback system. However,

the output voltage is not sensitive to load conditions due

to the low output resistance when it is operating with

a certain quantity of flying capacitors and high switch-

ing frequency. The Thevenin equivalent circuit of voltage

divider circuit is shown in the Figure 6.

R

TH

V

IN

UNDERVOLTAGE LOCKOUT

G1

The LTM4664A divider stages have a precision UVLO

SW1

comparator constantly monitoring the INTV

voltage

CCSn

to ensure that an adequate gate drive voltage is present.

It locks out the switching action when INTV is below

G2

G3

CCSn

MID

C

FLY

V

/2

IN

C

MID

4.9V. To prevent oscillation when there is a distu rbance

on the INTV

, the UVLO comparator has 20^S0mV of

CCSn

C

precision hysteresis. Another way to detect an under

voltage condition is to monitor the input supply. Because

the RUN pin has a precision turn-on reference of 1.22V,

MID

SW3

G4

one can use a resistor divider to the V

to turn on the

INSn

4664A F06

stage when the input voltage is high enough. An extra 5μA

of current flows out of the RUN pin once the RUNSn pin

voltage passes 1.22V. One can program the hysteresis

of the RUNSn comparator by adjusting the values of the

resistive divider.

Figure 6.

When duty cycle is around 50%:

1

–

4f_SR_DS(ON)C_FLY

1+e

R_OUT

=

FAULT RESPONSE AND TIMER PROGRAMMING

1

⎛

⎞

⎟

⎠

–

⎜

4f_SR_DS(ON)C_FLY

The LTM4664A divider stages stop switching and pull

the FAULTSn pins low during fault conditions. A capac-

itor connected from the TIMERSn pin to GND sets retry

time to start-up if fault conditions are removed. The typ-

ical waveform on TIMERSn pin during fault condition is

shown in Figure 7.

4f_SC_FLY1–e

⎜

⎝

Where:

f is the switching frequency.

S

After the FAULTSn pin is pulled low, a 3.5μA pull-up current

flows out of TIMER pin and starts to charge the TIMERSn

capacitor. The pull-up current increases to 7μA when then

TIMERSn pin voltage is higher than 0.5V and back to

3.5μA when the TIMERSn pin voltage is higher than 1.2V.

The TIMERSn pin will be strongly pulled down whenever

the fault conditions are removed or the TIMERSn pin

C

is the flying capacitor.

FLY

R

is the on resistance of one MOSFET.

DS(ON)

At low switching frequencies, R = 1/(4f C ). As fre-

TH

S FLY

quency increases, the R will finally approach 2R

.

TH

DS(ON)

In high power applications, it is suggested to select the

switching frequency around 1/(16C

R

) or higher

FLY DS(ON)

voltage is higher than 4V. When the TIMERSn pin voltage

for decent load regulation and efficiency. At heavy load

Rev. 0

32

For more information www.analog.com

LTM4664A

4:1 DIVIDER APPLICATION INFORMATION

3.5µA CHARGE

TIMER PIN

3.5µA CHARGE

TIMER PIN

4V

7µA CHARGE

TIMER PIN

1.2V

0.5V

FAULT

LOW

FAULT

RELEASE

PRE-BALANCE TIME

4664A F07

TURN ON

TIME

Figure 7. Timer Behavior During Fault or Startup

is between 0.5V and 1.2V, the internal pre-balance circuit

will source or sink current to the V pin and regulate

Design Example

As a design example using LTM4664A divider stages for

a the 4:1 divider at 72W, assume V = 48V (nominal),

OUTn

the V

pin to V

/2 with around 95mA/50mA capa-

OUTn

INSn

INS1

bility. The pre-balance time can be calculated based on the

capacitor C on the TIMERSn pin: T

V

= 60V (maximum), V

= 24V (nominal), I

=

INS1

OUT1

=

PRE-BALANCE

TIMERSn

3A (maximum) for stage 1. For high power and high voltage

applications, always start with a low switching frequency

e.g. 100kHz to minimize the switching losses. To set the

stage 1 to 100kHz switching frequency, a 36.5k 1% resistor

C

TIMER

• 0.7V/7μA, so the pre-balance time is 100ms/μF

(e.g. the pre-balance time is 10ms with 0.1μF C_TIMER). For

voltage divider applications, if the flying capacitor C

FLYn

and the V

capacitor are very large and input voltage

OUTn

is connected from FREQS1 pin to ground. Set the C

FLY1

is high, it may take several pre-balance time periods to

pre-balance the V pin to V /2 with a fixed C

voltage ripple to be 2% of the output voltage is a good start-

ing point with tradeoff between efficiency and power density.

.

TIMER

OUTn

INSn

A longer start-up time is expected. Assuming zero initial

conditions, the time to charge the capacitors, τcharge can

be estimated from the equation:

The C

can be calculated based on the equation below:

FLY1

I_OUT1_(MAX)=3A

τCharge=(C_OUT+C_FLY)•(V /2/93mA)

I_OUT1(MAX)

IN

C_FLY

=

2•f_SW•V_{CFLY1(RIPPLE)}

Keep in mind that the approximate capacitor value will be

the value at both voltage bias and temperature, this infor-

mation can be derived from the capacitor data sheet curves.

3A

∼31µF =

2•100kHz •0.48V

Input/Output Capacitor and Flying Capacitor Selection

Consider the ceramic capacitance derating at 24VDC bias

voltage, 8 of 10μF/X7R/50V ceramic capacitors are paral-

leled as flying capacitors.

In high power switched capacitor applications, large AC

currents flow through the flying capacitors and input/

output capacitors. Low ESR ceramic capacitors are

highly recommended for high power switch capacitor

applications.

The 4:1 divider at 72W, assume V

= 24V (nominal),

INS2

V = 30V (maximum), V

= 12V (nominal), I

= 6A

IN

OUT2

(maximum) for stage 2. For stage 2 start with a switching

frequency of 200kHz to minimize the switching losses. To

set the 200kHz switching frequency, a 60.4k 1% resis-

tor is connected from FREQS2 pin to ground. Set the

Make sure the maximum RMS capacitor current is within

the spec or higher rated capacitors are preferred. Note

that capacitor manufacturers’ ripple current ratings are

often based on only 2000 hours of life. This makes it

advisable to further derate the capacitor.

C

voltage ripple to be 2% of the output voltage is a

FLY2

good starting point with trade-off between efficiency and

Rev. 0

33

For more information www.analog.com

LTM4664A

4:1 DIVIDER APPLICATION INFORMATION

The output capacitor selection is similar to the flying

capacitor selection. More output capacitors result smaller

output voltage ripple. The output capacitor has less than

1/3 the CFLY RMS current, and the output capacitor can

be much less than the flying capacitor. Some of output

capacitors may be connected between input and output

to serve as input capacitors at the same time. However

the voltage rating of those capacitors has to be selected

based on the input voltage instead of the output voltage.

power density. The C

can be calculated based on the

FLY2

equation below:

I_OUT2(MAX)=6A

I_OUT2(MAX)

C_FLY

=

2•f_SW•V_{CFLY2(RIPPLE)}

6A

∼62µF =

2•200kHz •0.24V

Capacitors to use for 4:1 Divider

CAPACITOR

VENDOR

VALUE

(μF)

VOLTAGE

(V)

Consider the ceramic capacitance derating at 12VDC bias

voltage, 8 of 10μF/X7R/50V ceramic capacitors are paral-

leled as flying capacitors.

PART NUMBER

Murata

TDK

10

22

50

25

GRM32ER71H106KA12

C3225X7R1H106M250AC

GRM32ER71G226KE15L

TMK325BJ226MMHT

Consider the ceramic capacitance derating at 24V and

12V DC bias voltage.

Murata

Taiyo Yuden

The worst case RMS current may be 40% higher than the

maximum output current. So the worst case RMS on each

capacitor can be estimated by this equation:

I_OUT1(MAX)• 140%

I_RMS1(MAX)

=

,

N

N= #of C_FLY1capacitors inparallelin stage1

3A •1.4

0.525A =

8

Each capacitor israted for 2A IRMS,no issue

I_OUT2(MAX)• 140%

I_RMS2(MAX)

=

,

N

N= #of C_FLY1capacitors inparallelin stage1

6A •1.4

1.05A =

8

Rev. 0

34

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM OPERATION

n

The LTM4664A Power System Management (PSM)

includes a highly configurable dual 25A/30A output

standalone nonisolated switching mode step-down

DC/DC power supply with built-in EEPROM NVM (non-

volatile memory) with ECC and I²C-based PMBus/ SMBus

2-wire serial communication interface capable of 400kHz

SCL bus speed. Two output voltages can be regulated

(V_OUTC0, V_OUTC1—collectively, V_OUTn) with a few exter-

nal input and output capacitors and pull-up resistors.

Readback telemetry data of input and output voltages and

input and output currents, and module temperatures are

continually digitized cyclically by an integrated 16-bit ADC

(analog-to-digital converter). Many fault thresholds and

responses are customizable. Data can be autonomously

saved to EEPROM when a fault occurs, and the resulting

Programmable Input Voltage On and Off Threshold

Voltage

n

Programmable Current Limit per channel

Programmable Switching Frequency

Programmable OV and UV Threshold voltage

Programmable ON and Off Delay Times

Programmable Output Rise/Fall Times

Phase-Locked Loop for Synchronous PolyPhase

Operation (2, 3, 4 or 6 Phases)

n

Nonvolatile Configuration Memory with ECC

Optional External Configuration Resistors for Key

Operating Parameters

2

fault log can be retrieved over I C at a later time, for anal-

n

Optional Timebase Interconnect for Synchronization

Between Multiple Controllers

ysis. See Figure 2 for Block Diagram.

n

PSM SECTION OVERVIEW, MAJOR FEATURES

WP Pin to Protect Internal Configuration

Major Features Include:

Stand Along Operation After User Factory

Configuration

n

Dedicated Power Good Indicators

n

PMBus, Version 1.2, 400kHz Compliant Interface

n

Direct Input and Chip Current Sensing

The PMBus interface provides access to important power

management data during system operation including:

n

Programmable Loop Compensation Parameters

n

T

Start-Up Time: 30ms

INIT

n

Internal Controller Temperature

n

PWM Synchronization Circuit, (See Frequency and

Phasing Section for Details)

n

Internal Power Channel Temperature Average

Output Current

MFR_ADC_CONTROL for Fast ADC Sampling of One

Parameter (as Fast as 8ms) (See PMBus Command

for Details)

n

Average Output Voltage

n

Average Input Voltage

n

Fully Differential Output Sensing for Both Channels;

OUT0 OUT1

Average Input Current

V

/V

Both Programmable Up to 1.5V

n

Average Chip Input Current from V

IN

n

Power-Up and Program EEPROM with EXTV

Input Voltage Up to 18V

CC

n

Configurable, Latched and Unlatched Individual Fault

and Warning Status

ΔV Temperature Sensing

Individual channels are accessed through the PMBus

using the PAGE command, i.e., PAGE 0 or 1.

BE

SYNC Contention Circuit (Refer to Frequency and

Phase Section for Details)

Fault reporting and shutdown behavior are fully configu-

rable. Two individual FAULT_C0, FAULT_C1 outputs are

provided, both of which can be masked independently.

n

Fault Logging

Programmable Output Voltage

Rev. 0

35

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LTM4664A

DUAL 25A/30A PSM OPERATION

Three dedicated pins for ALERT, PGOOD_C0/PGOOD_C1

functions are provided. The shutdown operation also

allows all faults to be individually masked and can be

operated in either unlatched (hiccup) or latched modes.

The degradation in EEPROM retention for temperatures

>125°C can be approximated by calculating the dimen-

sionless acceleration factor using the following equation:

⎡

⎤

⎥

⎦

⎛

⎜

⎝

⎞

Ea

k

1

⎛

⎞

•

–

⎢

⎜

⎟

⎠

⎟

AF = e^⎣⎝

T

_USE+273 T_STRESS+273

⎠

Individual status commands enable fault reporting over

the serial bus to identify the specific fault event. Fault or

warning detection includes the following:

where:

n

AF = acceleration factor

Output Undervoltage/Overvoltage

Ea = activation energy = 1.4eV

K = 8.617 • 10 eV/°K

n

Input Undervoltage/Overvoltage

–5

n

Input and Output Overcurrent

T

= 125°C specified junction temperature

USE

n

Internal Overtemperature

= actual junction temperature in °C

STRESS

n

Communication, Memory or Logic (CML) Fault

Example: Calculate the effect on retention when operating

at a junction temperature of 135°C for 10 hours.

EEPROM WITH ECC

T

= 130°C

STRESS

The LTM4664A PSM dual 25A/30A regulators contain

internal EEPROM with ECC (Error Correction Coding) to

store user configuration settings and fault log informa-

tion. EEPROM endurance retention and mass write oper-

ation time are specified in the Electrical Characteristics

and Absolute Maximum Ratings sections. Write opera-

= 125°C,

–5

([(1.4/8.617 • 10 ) • (1/398 – 1/403)] )

USE

AF = e

= 16.6

The equivalent operating time at 125°C = 16.6 hours.

Thus the overall retention of the EEPROM was degraded

by 16.6 hours as a result of operating at a junction tem-

perature of 130°C for 10 hours. The effect of the over-

stress is negligible when compared to the overall EEPROM

retention rating of 87,600 hours at a maximum junction

temperature of 125°C.

tions above T = 85°C are possible although the Electrical

J

Characteristics are not guaranteed and the EEPROM will

be degraded. Read operations performed at temperatures

between –40°C and 125°C will not degrade the EEPROM.

Writing to the EEPROM above 85°C will result in a deg-

radation of retention characteristics. The fault logging

function, which is useful in debugging system problems

that may occur at high temperatures, only writes to fault

log EEPROM locations. If occasional writes to these reg-

isters occur above 85°C, the slight degradation in the data

retention characteristics of the fault log will not take away

from the usefulness of the function.

The integrity of the entire onboard EEPROM is checked with

a CRC calculation each time its data is to be read, such as

after a power-on reset or execution of a RESTORE_USER_

ALL command. If a CRC error occurs, the CML bit is set in

the STATUS_BYTE and STATUS_WORD commands, the

EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC

command is set, and the ALERT and RUN pins pulled

low (PWM channels off). At that point the device will only

respond at special address 0x7C, which is activated only

after an invalid CRC has been detected. The chip will also

respond at the global addresses 0x5A and 0x5B, but use

of these addresses when attempting to recover from a

CRC issue is not recommended. All power supply rails

associated with either PWM channel of a device reporting

an invalid CRC should remain disabled until the issue is

resolved. See the application Information section or contact

Rev. 0

It is recommended that the EEPROM not be written when

the die temperature is greater than 85°C. If the die tem-

perature exceeds 130°C, the LTM4664A PSM will disable

all EEPROM write operations. All EEPROM write opera-

tions will be re-enabled when the die temperature drops

below 125°C. (The controller will also disable all the

switching when the die temperature exceeds the internal

overtemperature fault limit 160°C with a 10°C hysteresis).

36

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LTM4664A

DUAL 25A/30A PSM OPERATION

the factory for details on efficient in-system EEPROM pro-

gramming, including bulk EEPROM Programming, which

the LTM4664A PSM also supports.

is available for transient and stability analysis, and experi-

enced users who prefer to adjust the module’s feedback

loop compensation parameters can use this tool.

The LTM4664A PSM contains dual integrated constant fre-

quency current mode control buck regulators (channel 0

and channel 1) whose built-in power MOSFETs are capable

of fast switching speed. The factory NVM-default switching

frequency clocks SYNC at 350kHz, to which the regulators

synchronize their switching frequency. The default phase-in-

terleaving angle between the channels is 180°. A pin-strap-

ping resistor on FSWPH_CFG configures the frequency of

the SYNC clock (switching frequency) and the channel phase

relationship of the channels to each other and with respect

to the falling edge of the SYNC signal. (Most possible com-

binations of switching frequency and phase-angle assign-

ments are settable by resistor pin programming; see Table 3.

Configure the LTM4664A’s PSM NVM to implement settings

not available by resistor-pin strapping.) When a FSWPH_CFG

pin-strap resistor sets the channel phase relationship of the

LTM4664A’s PSM channels, the SYNC clock is not driven by

the module; instead, SYNC becomes strictly a high imped-

ance input and channel switching frequency is then synchro-

nized to SYNC provided by an externally-generated clock or

POWER-UP AND INITIALIZATION

The LTM4664A dual 25A/30A regulators are designed

to provide standalone supply sequencing and controlled

turn-on and turn-off operation. It operates from a single

input supply (4.5V to 16V) while three on-chip linear reg-

ulators generate internal 2.5V, 3.3V and 5.5V. The con-

troller configuration is initialized by an internal threshold

based UVLO where V_INmust be approximately 4V and

the 5.5V, 3.3V and 2.5V linear regulators must be within

approximately 20% of the regulated values. In addition

to the power supply, a PMBus RESTORE_USER_ALL or

MFR_RESET command can initialize the part too.

The EXTV_CCpin is driven by an external regulator to

improve efficiency of the circuit and minimize power loss

when V

is high. The EXTV pin must exceed approx-

imately^IN4^S.7³V, and V

mus^Ct^Cexceed approximately 7V

INS3

before the INTV_CCLDO operates from the EXTV_CCpin.

To minimize application power, the EXTV_CCpin can be

supplied by a switching regulator.

sibling LTM4664A with pull-up resistor to V

. Switching

DD33

2

During initialization, the external configuration resistors

are identified and/or contents of the NVM are read into the

controller’s commands and the power train is held off. The

RUN_Cn and FAULT_Cn and PGOOD_Cn are held low. The

LTM4664A dual 25A/30A regulators will use the contents

of Table 1 thru Table 5 to determine the resistor defined

parameters. See the Resistor Configuration section for more

details. The resistor configuration pins only control some

of the preset values of the controller. The remaining values

are programmed in NVM either at the factory or by the user.

frequency and phase relationship can be altered via the I C

interface, but only when switching action is off, i.e., when the

module is not regulating either output. See the Dual 25A/30A

PSM Applications Information section for details.

Programmable analog feedback loop compensation for

channel 0 and channel 1 is accomplished with a capacitor

connection from COMP_C0a, 1a to SGND, and a capac-

itor from COMP_C0b, 1b to SGND.) The COMP_C0b, 1b

pin is for the high frequency gain roll off and is the g

m

amplifier output that has a programmable range, and the

COMP_C0a, 1a pin has the programmable resistor range

along with a capacitor to SGND that sets the frequency

compensation. See Programmable Loop Compensation

section. The LTM4664A dual 25A/30A regulators module

have sufficient stability margins and good transient per-

formance with a wide range of output capacitors—even

all-ceramic MLCCs. Table 12 provides guidance on input

and output capacitors recommended for many common

operating conditions along with the programmable com-

pensation settings. The Analog Devices LTpowerCAD tool

If the configuration resistors are not inserted or if the ignore

RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_ALL

configuration command), the LTM4664A PSM will use

only the contents of NVM to determine the DC/DC char-

acteristics. The ASEL value read at power-up or reset is

always respected unless the pin is open. The ASEL will set

the bottom 4LSBs and the MSBs are set by NVM. See the

Dual 25A/30A PSM Applications Information section for

more details.

Rev. 0

37

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LTM4664A

DUAL 25A/30A PSM OPERATION

After the part has initialized, an additional comparator

(TON_DELAY) prior to initiating this output voltage ramp.

The rise time of the voltage ramp can be programmed

using the TON_RISE command to minimize inrush cur-

rents associated with the start-up voltage ramp. The soft-

start feature is disabled by setting the value of TON_RISE

to any value less than 0.25ms. The LTM4664A PWM_Cn

always uses discontinuous mode during the TON_RISE

operation. In discontinuous mode, the bottom MOSFET

is turned off as soon as reverse current is detected in

the inductor. This will allow the regulator to start up into

a prebiased load. When the TON_MAX_FAULT_LIMIT is

reached, the part transitions to continuous mode, if so

programmed. If TON_MAX_FAULT_LIMIT is set to zero,

there is no time limit and the part transitions to the desired

monitors V_INS3. The VIN_ON threshold must be exceeded

before the output power sequencing can begin. After V

IN

is initially applied, the part will typically require 70ms to

initialize and begin the TON_DELAY timer. The readback

of voltages and currents may require an additional 0ms

to 90ms.

SOFT-START

The method of start-up sequencing described below is

time-based. The part must enter the run state prior to

soft-start. Stage 2 of the 4:1 Divider will release RUN_C0

and RUN_C1 once it has reached regulation defined by

the program valve set by UV , and FAULTn is released.

The RUN_Cn pins are releas^Se²d by the LTM4664A PSM

conduction mode after TON_RISE completes and V

OUT

has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC

is not present. However, setting TON_MAX_FAULT_LIMIT

to a value of 0 is not recommended.

after the part is initialized and V

is greater than the

INS3

VIN_ON threshold. If multiple LTM4664A PSMs are used

in an application, they all hold their respective RUN_Cn

pins low until all devices are initialized and V

exceeds

INS3

TIME-BASED SEQUENCING

the VIN_ON threshold for every device. The SHARE_CLK

pin assures all the devices connected to the signal use

the same time base. The SHARE_CLK pin is held low until

The default mode for sequencing the outputs on and

off is time-based. Each output is enabled after waiting

TON_DELAY amount of time following either a RUN_Cn

the part has been initialized after V

is applied. The

INS3

LTM4664A PSM can be set to turn-off (or remain off)

if SHARE_CLK is low (set bit 2 of MFR_CHAN_CONFIG

to 1). This allows the user to assure synchronization

across numerous PSM devices even if the RUN_Cn pins

cannot be connected together due to board constraints. In

general, if the user cares about synchronization between

chips it is best not only to connect all the respective RUN_

Cn pins together but also to connect all the respective

pin going high, a PMBus command to turn on or the V

IN

rising above a preprogrammed voltage. Off sequencing is

handled in a similar way. To assure proper sequencing,

make sure all ICs connect the SHARE_CLK pin together and

RUN_Cn pins together. If the RUN_Cn pins cannot be con-

nected together for some reasons, set bit 2 of MFR_CHAN_

CONFIG to 1. This bit requires the SHARE_CLK pin to be

clocking before the power supply output can start. When

the RUN_Cn pin is pulled low, the LTM4664A PSM will hold

the pin low for the MFR_ RESTART_DELAY. The minimum

MFR_RESTART_ DELAY is TOFF_DELAY + TOFF_FALL +

136ms. This delay assures proper sequencing of all rails.

The LTM4664A PSM calculates this delay internally and will

not process a shorter delay. However, a longer commanded

MFR_RESTART_DELAY can be used by the part. The max-

imum allowed value is 65.52 seconds.

SHARE_CLK pins together and pulled up to V

with a

DD33

10k resistor. This assures all chips begin sequencing at

the same time and use the same time base.

After the RUN_Cn pins release and prior to entering a

constant output voltage regulation state, the LTM4664A

PSM performs a monotonic initial ramp or “soft-start” on

each of the 25A/30A outputs. Soft-start is performed by

actively regulating the load voltage while digitally ramping

the target voltage from 0V to the commanded voltage set-

point. Once the LTM4664A dual 25A/30A regulators are

commanded to turn on (after power up and initialization),

the controller waits for the user specified turn-on delay

VOLTAGE-BASED SEQUENCING

The sequence can also be voltage-based. As shown in

Figure 8, The PGOOD_Cn pins are asserted when the

Rev. 0

38

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LTM4664A

DUAL 25A/30A PSM OPERATION

UV threshold is exceeded for each output. It is possible

to feed the PGOOD_Cn pin from one LTM4664A PSM

channel into the RUN_Cn pin of the next LTM4664A

PSM channel in the sequence, especially across multi-

ple LTM4664As. The PGOOD_Cn has a 60µs filter. If the

There are two ways to respond to faults; which are retry

mode and latched off mode. In retry mode, the controller

responds to a fault by shutting down and entering the inac-

tive state for a programmable delay time (MFR_RETRY_

DELAY). This delay minimizes the duty cycle associated

with autonomous retries if the fault that causes the shut-

down disappears once the output is disabled. The retry

delay time is determined by the longer of the MFR_RETRY_

DELAY command or the time required for the regulated

output to decay below 12.5% of the programmed value.

If multiple outputs are controlled by the same FAULT_Cn

pin, the decay time of the faulted output determines the

retry delay. If the natural decay time of the output is too

long, it is possible to remove the voltage requirement of

the MFR_RETRY_DELAY command by asserting bit 0

of MFR_CHAN_CONFIG. Alternatively, latched off mode

means the controller remains latched-off following a fault

and clearing requires user intervention such as toggling

RUN_Cn or commanding the part OFF then ON.

V

voltage bounces around the UV threshold for a long

OUT

period of time it is possible for the PGOOD_Cn output to

toggle more than once. To minimize this problem, set the

TON_RISE time under 100ms.

If a fault in the string of rails is detected, only the faulted

rail and downstream rails will fault off. The rails in the

string of devices in front of the faulted rail will remain on

unless commanded off.

RUN_C0

PGOOD_C0

START

LTM4664A

RUN_C1

PGOOD_C1

RUN_C0

RUN_C1

PGOOD_C0

PGOOD_C1

LTM4664A

LIGHT-LOAD CURRENT OPERATION

4664A F08

The LTM4664A PSM Regulators have two modes of oper-

ation: high efficiency discontinuous conduction mode or

forced continuous conduction mode. Mode selection is

done using the MFR_PWM _MODE command (discon-

tinuous conduction is always the start-up mode, forced

continuous is the default running mode).

TO NEXT CHANNEL

IN THE SEQUENCE

Figure 8. Event (Voltage) Based Sequencing

SHUTDOWN

The LTM4664A PSM Regulators supports two shutdown

modes. The first mode is closed-loop shutdown response,

with user defined turn-off delay (TOFF_DELAY) and ramp

down rate (TOFF_FALL). The controller will maintain the

mode of operation for TOFF_FALL. The second mode is dis-

continuous conduction mode, the controller will not draw

current from the load and the fall time will be set by the

output capacitance and load current, instead of TOFF_FALL.

If a controller is enabled for discontinuous operation, the

inductor current is not allowed to reverse. The reverse

current comparator’s output turns off the bottom MOSFET

just before the inductor current reaches zero, preventing

it from reversing and going negative.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined solely

by the voltage on the COMP_Cn pins. In this mode, the

efficiency at light loads is lower than in discontinuous

mode operation. However, continuous mode exhibits

lower output ripple and less interference with audio cir-

cuitry, but may result in reverse inductor current, which

can cause the input supply to boost. The VIN_OV_FAULT_

LIMIT can detect this and turn off the offending channel.

However, this fault is based on an ADC read and can take

Rev. 0

The shutdown occurs in response to a fault condition

or loss of SHARE_CLK (if bit 2 of MFR_CHAN_ CONFIG

is set to a 1) or V falling below the VIN_OFF thresh-

old or FAULT pulled low externally (if the MFR_FAULT_

RESPONSE is set to inhibit). Under these conditions, the

power stage is disabled in order to stop the transfer of

energy to the load as quickly as possible. The shutdown

state can be entered from the soft-start or active regula-

tion states or through user intervention.

IN

39

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LTM4664A

DUAL 25A/30A PSM OPERATION

up to t

to detect. If there is a concern about the

edge that sets the PWM latch to turn on the top power

switch. Additional small propagation delays to the PWM

control pins will also apply. Both PSM channels must be

off before the FREQUENCY_SWITCH and MFR_PWM_

CONFIG commands can be written to the LTM4664A PSM.

CONVERT

input supply boosting, keep the part in discontinuous

conduction mode.

If the part is set to discontinuous mode operation, as

the inductor average current increases, the controller will

automatically modify the operation from discontinuous

mode to continuous mode.

The phase relationships and frequency options provide

for numerous application options. Multiple LTM4664A

PSM channels modules can be synchronized to realize a

PolyPhase array. In this case the phases should be sepa-

rated by 360/n degrees, where n is the number of phases

driving the output voltage rail.

SWITCHING FREQUENCY AND PHASE

The switching frequency of the PWM_C1 can be estab-

lished with an internal oscillator or an external time base.

The internal phase-locked loop (PLL) synchronizes the

PWM control to this timing reference with proper phase

relation, whether the clock is provided internally or exter-

nally. The device can also be configured to provide the

master clock to other devices through PMBus command,

NVM setting, or external configuration resistors as out-

lined in Table 3.

PWM LOOP COMPENSATION

The internal PWM loop compensation resistors R

COMPna

of the LTM4664A PSM can be adjusted using bit[4:0] of

the MFR_PWM_COMP command.

The transconductance (gm) of the LTM4664A PSM chan-

nel PWM error amplifier can be adjusted using bit[7:5]

of the MFR_PWM_COMP command. These two loop

compensation parameters can be programmed when

the device is in operation. Refer to the Programmable

Loop Compensation subsection in the Dual 25A/30A PSM

Applications Information section for further details.

As clock master, a LTM4664A PSM device will drive its

open-drain SYNC pin at the selected rate with a pulse width

of 500ns. An external pull-up resistor between SYNC and

V

is required in this case. Only one device connected

DD33

to SYNC should be designated to drive the pin. The other

LTM4664A PSM devices will automatically revert to an

external SYNC input, disabling its own SYNC, as long as

the external SYNC frequency is greater than 80% of the

programmed SYNC frequency. The external SYNC input

shall have a duty cycle between 20% and 80%.

OUTPUT VOLTAGE SENSING

Both PSM channels in LTM4664A have differential ampli-

fiers, which allow the remote sensing of the load voltage

+

–

between V and V pins. The telemetry ADC is also fully

+

Whether configured to drive SYNC or not, the LTM4664A

PSM devices can continue PWM operation using its own

internal oscillator if an external clock signal is subse-

quently lost.

differential and makes measurements between V

_

OSNS

–

+

Cn and V

_Cn voltages for both channels at the V

OSNS

–

and V pins, respectively. The maximum allowed is 1.5V,

but the LTM4664A design is limited to 1.8V.

The device can also be programmed to always require an

external oscillator for PWM operation by setting bit 4 of

MFR_CONFIG_ALL. The status of the SYNC driver circuit

is indicated by bit 10 of MFR_PADS.

INTV /EXTV POWER

CC

Power for the internal MOSFET drivers and most other

internal circuitry is derived from the INTV pin. When the

CC

The MFR_PWM_CONFIG command can be used to con-

figure the phase of each channel. Desired phase can also

be set from EEPROM or external configuration resistors

as outlined in Table 3. Designated phase is the relationship

between the falling edge of SYNC and the internal clock

EXTV pin is shorted to GND or tied to a voltage less than

4.7V,^Ca^Cn internal 5.5V linear regulator supplies INTV

CC

power from V

4.7V and V

. If EXTV is taken above approximately

INS3_C1

lator is turned off and an internal switch is turned on,

INS3

is hig^Ch^Cer than 7.0V, the 5.5V regu-

Rev. 0

40

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LTM4664A

DUAL 25A/30A PSM OPERATION

connecting EXTV to INTV . Using the EXTV allows

telemetry ADC with an input range of 128mV, a noise floor

CC

the INTV power to be de^Cri^Cved from a high efficiency

of 7µV , and a peak-peak noise of approximately 46.5µV.

CC

RMS

external source such as a switching regulator output.

The LTM4664A PSM computes the inductor current using

the DCR value stored in the IOUT_CAL_GAIN command and

the temperature coefficient stored in command MFR_IOUT_

CAL_GAIN_TC. The resulting current value is returned by the

READ_IOUT command.

EXTV can provide power to the internal 3.3V linear reg-

CC

ulator even when V

is not present, which allows the

INS3

LTM4664A PSM to be initialized and programmed even

without main power being applied.

The INTV regulator is powered from the V

pin,

CC

INS3_C1

INPUT CURRENT SENSING

the power through the IC is equal to V_{INS3_C1}• I_INTVCC. The

gate charge current is dependent on operating frequency.

The INTV_CCregulator can supply up to 100mA, and the

typical INTV_CCcurrent for the LTM4664A PSM is ~50mA. A

12V input voltage would equate to a difference of 7V drop

across the internal controller, when multiplied by 50mA

equals a 350mW power loss. This loss can be eliminated

To sense total input current consumed by the LTM4664A's

25A/30A two power stages , a sense resistor is placed

+

between the supply voltage and V

path. The I and

INS3

IN

–

I

IN

pins are connected to the sense resistor. The filtered

voltage is amplified by the internal high side current

sense amplifier and digitized by the LTM4664A’s PSM

telemetry ADC. The input current sense amplifier has

three gain settings of 2x, 4x, and 8x set by the bit[6:5] of

the MFR_PWM_CONFIG command. The maximum input

sense voltage for the three gain settings is 50mV, 20mV,

and 5mV respectively. The LTM4664A PSM computes the

by providing an external 5V bias on the EXTV pin.

CC

Do not tie INTV on the LTM4664A PSM to an external

CC

supply because INTV will attempt to pull the external

CC

supply high and hit current limit, significantly increasing

the die temperature.

input current using the internal R

value stored in the

SENSE

IIN_CAL_GAIN command. The resulting measured power

OUTPUT CURRENT SENSING AND SUB MILLIOHM

DCR CURRENT SENSING

stage current is returned by the READ_IIN command.

The LTM4664A uses a 1Ω resistor to measure the chip

supply current being consumed by the LTM4664A PSM

Controller. This value is returned by the MFR_READ_ICHIP

command. The chip current is calculated by using the 1Ω

value stored in the MFR_RVIN command. Refer to the

subsection titled Input Current Sense Amplifier in the

Dual 25A/30A PSM Applications Information section for

further details.

The LTM4664A PSM channels use a unique sub-mil-

liohm inductor current sensing technique that provides

a high level signal to noise ratio while sensing very low

signals in current mode operation. This enables higher

conversion efficiencies with the use of the internal

sub-milliohm inductors in heavy load applications. The

current limit threshold can be accurately set with the

MFR_PWM_MODE[7] for high and low range. The low

range setting MFR_PWM_MODE [7] = 0 should be used

(see page103).

PolyPhase LOAD SHARING

Multiple LTM4664As can be arrayed in order to provide

a balanced load-share solution by bussing the necessary

pins. Figure 48 illustrates a 4-Phase design sharing con-

nections required for load sharing.

The internal DCR sensing network, thus current limit are calcu-

lated based on the DCR of the inductor at room temperature.

The DCR of the inductor has a large temperature coefficient,

approximately 3900ppm/°C. The temperature coefficient of

the inductor is written to the MFR_IOUT_CAL_GAIN_TC reg-

ister. The external temperature is sensed near the inductor

and used to modify the internal current limit circuit to main-

tain an essentially constant current limit with temperature.

The current sensed is then digitized by the LTM4664A PSM

If an external oscillator is not provided, the SYNC pin

should only be enabled on one of the LTM4664A's

PSM Channels. The other(s) should be programmed to

disable SYNC using bit 4 of MFR_CONFIG_ALL. If an

external oscillator is present, the chip with the SYNC

Rev. 0

41

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LTM4664A

DUAL 25A/30A PSM OPERATION

pin enabled will detect the presence of the external

clock and disable its output.

switcher off unless the voltage configuration pins are

installed. The VTRIMn_CFG pins in Table 2 are used to set

the output voltage fine adjustment setting. Both combine

to offer several distinct output voltages.

+

Multiple channels need to tie all the V_{OSNS _}Cn pins

–

together, and all the V

Cn pins together, C

na

OMP_

OSNS _

and C

nb pins together as well. Do not assert bit[4]

of MFR_CONFIG_ALL except in a PolyPhase application.

The following parameters are set as a percentage of the

output voltage if the RCONFIG pins are used to determine

the output voltage:

OMP_

The user must share the SYNC, SHARE_CLK, FAULT_Cn,

and ALERT pins of these parts. Be sure to use pull-up

resistors on SYNC, FAULT_Cn, SHARE_CLK and ALERT.

n

VOUT_OV_FAULT_LIMIT....................................+10%

n

VOUT_OV_WARN_LIMIT....................................+7.5%

n

VOUT_MAX.........................................................+7.5%

n

VOUT_MARGIN_HIGH........................................+5%

EXTERNAL/INTERNAL TEMPERATURE SENSE

n

VOUT_MARGIN_LOW.........................................–5%

Temperature is measured using the internal diode-connected

PNP transistors on either of the TSNS_C0b or TSNS_C1b

pins corresponding to channel 0 or 1. TSNS_Cnb pins

should be connected to their respective TSNS_Cna pins,

and these returns are directly connected to the LTM4664A

PSM SGND_C0_C1 pin. Two different currents are applied to

the diode (nominally 2µA and 32µA) and the temperature is

calculated from a ΔV measurement made with the internal

16-bit monitor ADC ^B(s^Eee Figure 2, Block Diagram).

n

VOUT_UV_FAULT_LIMIT....................................–7%

The FSWPH_CFG pin settings are described in Table 3.

This pin selects the switching frequency and phase of each

channel. The phase relationships between the two channels

and SYNC pin are determined in Table 3. To synchronize

to an external clock, the part should be put into external

clock mode (SYNC output disabled but frequency set to the

nominal value). If no external clock is supplied, the part will

clock at the programmed frequency. If the application is

multiphase and the SYNC signal between chips is lost, the

parts will not operate at the designed phase even if they are

programmed and trimmed to the same frequency.

The LTM4664A PSM channels will only implement ΔV

BE

temperature sensing, therefore MFR_PWM_MODE bit[5]

is reserved.

This may increase the ripple voltage on the output, pos-

sibly produce undesirable operation. If the external SYNC

signal is being generated internally and external SYNC is

not selected, bit 10 of MFR_PADS will be asserted. If no

frequency is selected and the external SYNC frequency

is not present, a PLL_FAULT will occur. If the user does

not wish to see the ALERT from a PLL_FAULT even if

there is not a valid synchronization signal at power-up,

the ALERT mask for PLL_FAULT must be written. See

the description on SMBALERT_MASK for more details.

If the SYNC pin is connected between multiple ICs only

one of the ICs should have the SYNC pin enabled using

the MFR_CONFIG_ALL[4] =1, and all other ICs should

be configured to have the SYNC pin disabled with MFR_

CONFIG_ALL[4] =0.

RCONFIG (RESISTOR CONFIGURATION) PINS

There are six input pins utilizing 1% resistors for these pins

to select key operating parameters. The pins are ASEL,

FSWPH_CFG, VOUTC0_CFG, VOUTC1_CFG, VTRIMC0_

CFG, VTRIMC1_CFG. If pins are floated, the value stored in

the corresponding NVM command is used. If bit 6 of the

MFR_CONFIG_ALL configuration command is asserted in

NVM, the resistor input is ignored upon power-up except

for ASEL which is always respected. The resistor config-

uration pins are only measured during a power-up reset

or after a MFR_RESET or after a RESTORE_USER_ALL

command is executed.

The VOUTn_CFG pin settings are described in Table 1.

These pins set the LTM4664A V

and V

output

voltage coarse settings. If the ^Op^Uin^TCi⁰s open^O, ^Uth^TCe¹VOUT_

COMMAND command is loaded from NVM to determine

the output voltage. The default setting is to have the

The ASEL pin settings are described in Table 4. ASEL

selects slave address for the LTM4664A PSM. For more

detail, refer to Table 5.

Rev. 0

42

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LTM4664A

DUAL 25A/30A PSM OPERATION

NOTE: Per the PMBus specification, pin programmed

parameters can be overridden by commands from the

digital interface with the exception of ASEL which is

always honored. Do not set any part address to 0x5A or

0x5B because these are global addresses and all parts will

respond to them.

Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the

LTM4664A’s PSM Output Voltages, Fine Adjustment Setting

(Not Applicable if MFR_CONFIG_ALL[6] = 1b)

V

(mV) FINE ADJUSTMENT

OUTn

RESPECTIVE

TRIM

TO V

R

*

SETTING WHEN

R

VTRIMn_CFG

BOT (kΩ)

TOP (kΩ)

14.3

Open

32.4

22.6

18.0

15.4

12.7

10.7

9.09

7.68

6.34

5.23

4.22

3.24

2.43

1.65

0.787

0

99

Table 1. VOUTCn _CFG Pin Strapping Look-Up Table for

the LTM4664A’s PSM Output Voltages, Coarse Setting (Not

Applicable if MFR_CONFIG_ALL[6] = 1b)

86.625

74.25

61.875

49.5

V

(V)

OUTn

SETTING

COARSE

R

*

MFR_PWM

MODEn[1] BIT

VOUTn_CFG

BOT (kΩ)

TOP (kΩ)

37.125

24.75

12.375

14.3

Open

32.4

22.6

18.0

15.4

12.7

10.7

NVM

3.3

NVM

14.3

NVM

14.3

0

–12.375

–24.75

–37.125

–49.5

14.3

3.1

14.3

2.9

14.3

2.7

14.3

2.5

0, if V

1, if V

> 0mV

≤ 0mV

TRIMn

–61.875

–74.25

–86.625

–99

14.3

9.09

7.68

6.34

5.23

4.22

3.24

2.43

1.65

0.787

0

2.3

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

1

*R

value indicated is nominal. Select R

from

VTRIMCn_CFG

a resistor vendor such that its value is always within 3% of the value

indicated in the table. Take into account resistor initial tolerance, T.C.R. and

resistor operating temperatures, soldering heat/IR reflow, and endurance

of the resistor over its lifetime. Thermal shock/cycling, moisture

(humidity) and other effects (depending on one’s specific application)

could also affect R ’s value over time. All such effects must be

VTRIMCn_CFG

taken into account in order for resistor pin strapping to yield the expected

result at every SV power-up and/or every execution of MFR_RESET, or

IN

RESTORE_USER_ALL over the lifetime of one’s product.

*R

VOUTCn_CFG

value indicated is nominal. Select R

from a

VOUTCn_CFG

resistor vendor such that its value is always within 3% of the value

indicated in the table. Take into account resistor initial tolerance, T.C.R.

and resistor operating temperatures, soldering heat/IR reflow, and

endurance of the resistor over its lifetime. Thermal shock/cycling,

moisture (humidity) and other effects (depending on one’s specific

Example:

V

DD25

R

_CFG TOP

OUTCn

V

_CFG PIN

OUTCn

application) could also affect R

’s value over time. All such

VOUTCn_CFG

effects must be taken into account in order for resistor pin strapping to

R

OUTCn

_CFG BOT

yield the expected result at every SV power-up and/or every execution

of MFR_RESET or RESTORE_ USER_ALL, over the lifetime of one’s

product.

IN

SGND_C0_C1

Rev. 0

43

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LTM4664A

DUAL 25A/30A PSM OPERATION

Table 3. FSWPH_CFG Pin Strapping Look-Up Table to Set the LTM4664A’s PSM Switching Frequency and Channel Phase-Interleaving

Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b)

R

*

SWITCHING

FREQUENCY (kHz)

bits [2:0] of

MFR_PWM_CONFIG

bit [4] of

MFR_CONFIG_ALL

FSWPH_CFG

BOT (kΩ)

TOP (kΩ)

θSYNC TO θ0

θSYNC TO θ1

NVM; LTM4664A

PSM

NVM; LTM4664A

PSM

NVM; LTM4664A

Default = 0°

NVM; LTM4664A PSM NVM; LTM4664A PSM

14.3

Open

32.4

22.6

18.0

15.4

12.7

10.7

7.68

6.34

5.23

4.22

3.24

2.43

1.65

0.787

0

Default = 500

Default = 180°

Default = 000b

Default = 0b

250

350

0°

180°

240°

270°

240°

120°

240°

300°

270°

180°

240°

000b

0b

1b

000b

425

0°

000b

575

0°

000b

650

0°

000b

750

0°

000b

500

120°

90°

0°

100b

500

001b

External**

010b

0°

011b

60°

120°

90°

0°

101b

110b

001b

000b

120°

100b

*R

FSWPH_CFG

value indicated is nominal. Select R

from a resistor vendor such that its value is always within 3% of the value indicated in the

FSWPH_CFG

table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over

its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect R ’s value

FSWPH_CFG

over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every SV power-up and/or every

IN

execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.

**External setting corresponds to FREQUENCY_SWITCH (Register 0x33) value set to 0x0000; the device synchronizes its switching frequency to that of

the clock provided on the SYNC pin, provided MFR_CONFIG_ALL[4] = 1b.

Example:

V

DD25

R

CFG TOP

FSWPH_

FSWPH_CFG PIN

CFG BOT

R

FSWPH_

Rev. 0

44

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LTM4664A

DUAL 25A/30A PSM OPERATION

Table 4. ASEL Pin Strapping Look-Up Table to Set the

LTM4664A’s PSM Slave Address (Applicable Regardless of

MFR_CONFIG_ALL[6] Setting)

Table 5. LTM4664A PSM MFR_ADDRESS Command Examples

Expressed in 7- and 8-Bit Addressing

HEX DEVICE

ADDRESS

BIT

R * (kΩ)

ASEL

SLAVE ADDRESS

DESCRIPTION

7-BIT

8-BIT

0xB4

0xB6

0x9E

0x80

0x82

7

0

1

6

1

0

5

0

4

1

0

3

2

0

1

0

1

0

1

0

1

0

R/W

0

Open

MFR_ADDRESS[6:0]_R/W

4

Rail

0x5A

0x5B

0x4F

0x40

0x41

1

0

32.4

22.6

18.0

15.4

12.7

10.7

9.09

7.68

6.34

5.23

4.22

3.24

2.43

1.65

0.787

0

MFR_ADDRESS[6:4]_1111_R/W

MFR_ADDRESS[6:4]_1110_R/W

MFR_ADDRESS[6:4]_1101_R/W

MFR_ADDRESS[6:4]_1100_R/W

MFR_ADDRESS[6:4]_1011_R/W

MFR_ADDRESS[6:4]_1010_R/W

MFR_ADDRESS[6:4]_1001_R/W

MFR_ADDRESS[6:4]_1000_R/W

MFR_ADDRESS[6:4]_0111_R/W

MFR_ADDRESS[6:4]_0110_R/W

MFR_ADDRESS[6:4]_0101_R/W

MFR_ADDRESS[6:4]_0100_R/W

MFR_ADDRESS[6:4]_0011_R/W

MFR_ADDRESS[6:4]_0010_R/W

MFR_ADDRESS[6:4]_0001_R/W

MFR_ADDRESS[6:4]_0000_R/W

4

Global

0

Default

0

Example 1

Example 2

0

2,3

Disabled

0

Note 1. This table can be applied to the MFR_RAIL_ADDRESSn

commands, but not the MFR_ADDRESS command.

Note 2. A disabled value in one command does not disable the device, nor

does it disable the global address.

Note 3. A disabled value in one command does not inhibit the device from

responding to device addresses specified in other commands.

Note 4. It is not recommended to write the value 0x00, 0x0C (7-bit), 0x5A

(7-bit), 0x5B (7-bit) or 0x7C(7-bit) to the MFR_CHANNEL_ADDRESSn or

the MFR_RAIL_ADDRESSn commands.

FAULT DETECTION AND HANDLING

A variety of fault and warning reporting and handling

mechanisms are available. Fault and warning detection

capabilities include:

Where:

R/W = Read/Write bit in control byte

All PMBus device addresses listed in the specification are 7 bits wide

unless otherwise noted.

Note: The LTM4664A PSM will always respond to slave address 0x5A and

0x5B regardless of the NVM or ASEL resistor configuration values.

n

Input OV FAULT Protection and UV Warning

n

Average Input OC Warn

*R

value indicated is nominal. Select R

from a resistor vendor

CFG

such that its value is always within 3% of the value indicated in the table.

Take into account resistor initial tolerance, T.C.R. and resistor operating

temperatures, soldering heat/IR reflow, and endurance of the resistor

over its lifetime. Thermal shock cycling, moisture (humidity) and other

n

Output OV/UV Fault and Warn Protection

n

Output OC Fault and Warn Protection

n

Internal control Die and Internal Module

Overtemperature Fault and Warn Protection

effects (depending on one’s specific application) could also affect R ’s

CFG

value over time. All such effects must be taken into account in order for

resistor pin-strapping to yield the expected result at every SV power-up

IN

n

Internal Undertemperature Fault and Warn Protection

and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the

lifetime of one’s product.

Example:

n

CML Fault (Communication, Memory or Logic)

n

External Fault Detection via the Bidirectional FAULT_Cn

Pins

ASEL PIN

R

ASEL

In addition, the LTM4664A PSM can map any combi-

nation of fault indicators to their respective FAULT_Cn

pin using the propagate FAULTn response commands,

MFR_FAULT_ PROPAGATE. Typical usage of a FAULT_Cn

pin is as a driver for an external crowbar device, over-

temperature alert, overvoltage alert or as an interrupt

SGND_C0_C1

Rev. 0

45

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LTM4664A

DUAL 25A/30A PSM OPERATION

to cause a microcontroller to poll the fault commands.

Alternatively, the FAULT_Cn pins can be used as inputs

to detect external faults downstream of the controller that

require an immediate response.

In general, any asserted bit in a STATUS_x register also

pulls the ALERT pin low. Once set, ALERT will remain low

until one of the following occurs.

n

A CLEAR_FAULTS or MFR_RESET Command Is Issued

Any fault or warning event will always cause the ALERT

pin to assert low unless the fault or warning is masked by

the SMBALERT_MASK. The pin will remain asserted low

until the CLEAR_FAULTS command is issued, the fault bit

is written to a 1 or bias power is cycled or a MFR_RESET

command is issued, or the RUN pins are toggled OFF/

ON or the part is commanded OFF/ON via PMBus or an

ARA command operation is performed. The MFR_FAULT_

PROPAGATE command determines if the FAULT_Cn pins

are pulled low when a fault is detected.

n

The Related Status Bit Is Written to a One

n

The Faulted Channel Is Properly Commanded Off and

Back On

n

The LTM4664A PSM Successfully Transmits Its

Address During a PMBus ARA

n

Bias Power Is Cycled

With some exceptions, the SMBALERT_MASK command

can be used to prevent the LTM4664A PSM from assert-

ing ALERT for bits in these registers on a bit-by-bit basis.

These mask settings are promoted to STATUS_WORD

and STATUS_BYTE in the same fashion as the status bits

themselves. For example, if ALERT is masked for all bits

in channel 0 STATUS_VOUT, then ALERT is effectively

Output and input fault event handling is controlled by the

corresponding fault response byte as specified in Table 3

thru 17. Shutdown recovery from these types of faults

can either be autonomous or latched. For autonomous

recovery, the faults are not latched, so if the fault con-

ditions not present after the retry interval has elapsed, a

new soft-start is attempted.

masked for the V

bit in STATUS_WORD for PAGE 0.

OUT

The BUSY bit in STATUS_BYTE also asserts ALERT low

and cannot be masked. This bit can be set as a result of

various internal interactions with PMBus communication.

This fault occurs when a command is received that cannot

be safely executed with one or both channels enabled.

As discussed in the 4:1 Divider Application Information,

BUSY faults can be avoided by polling MFR_COMMON

before executing some commands.

If the fault persists, the controller will continue to retry.

The retry interval is specified by the MFR_RETRY_DELAY

command and prevents damage to the regulator com-

ponents by repetitive power cycling, assuming the fault

condition itself is not immediately destructive. The MFR_

RETRY_DELAY must be greater than 120ms. It can not

exceed 83.88 seconds.

If masked faults occur immediately after power up, ALERT

may still be pulled low because there has not been time

to retrieve all of the programmed masking information

from EEPROM.

Status Registers and ALERT Masking

Figure 9 summarizes the internal LTM4664A PSM status

registers accessible by PMBus command. These contain

indication of various faults, warnings and other import-

ant operating conditions. As shown, the STATUS_BYTE

and STATUS_WORD commands also summarize con-

tents of other status registers. Refer to PMBus Command

Summary for specific information.

Status information contained in MFR_COMMON and

MFR_PADS can be used to further debug or clarify the

contents of STATUS_BYTE or STATUS_WORD as shown,

but the contents of these registers do not affect the state

of the ALERT pin and may not directly influence bits in

STATUS_BYTE or STATUS_WORD.

NONE OF THE ABOVE in the STATUS_BYTE indicates that

one or more of the bits in the most-significant nibble of

STATUS_WORD are also set.

Rev. 0

46

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LTM4664A

DUAL 25A/30A PSM OPERATION

STATUS_WORD

STATUS_VOUT*

VOUT_OV Fault

VOUT_OV Warning

VOUT_UV Warning

VOUT_UV Fault

VOUT_MAX Warning

TON_MAX Fault

TOFF_MAX Warning

(reads 0)

15 VOUT

14 IOUT

13 INPUT

12 MFR_SPECIFIC

11 POWER_GOOD#

10 (reads 0)

7

6

5

4

3

2

1

0

STATUS_INPUT

7

6

5

4

3

2

1

0

VIN_OV Fault

(reads 0)

VIN_UV Warning

(reads 0)

Unit Off for Insuffcient VIN

(reads 0)

9

8

(reads 0)

STATUS_BYTE

(PAGED)

IIN_OC Warning

(reads 0)

7

6

5

4

3

2

1

0

BUSY

OFF

VOUT_OV

IOUT_OC

(reads 0)

TEMPERATURE

CML

NONE OF THE ABOVE

STATUS_IOUT

STATUS_MFR_SPECIFIC

7

6

5

4

3

2

1

0

IOUT_OC Fault

(reads 0)

IOUT_OC Warning

(reads 0)

7

6

5

4

3

2

1

0

Internal Temperature Fault

Internal Temperature Warning

EEPROM CRC Error

Internal PLL Unlocked

Fault Log Present

VDD33 UV or OV Fault

VOUT Short Cycled

FAULT Pulled Low By External Device

(PAGED)

(reads 0)

MFR_COMMON

7

6

5

4

3

2

1

0

Chip Not Driving ALERT Low

Chip Not Busy

(PAGED)

Internal Calculations Not Pending

Output Not In Transition

EEPROM Initialized

(reads 0)

SHARE_CLK_LOW

WP Pin High

STATUS_TEMPERATURE

MFR_PADS

7

6

5

4

3

2

1

0

OT Fault

15 VDD33 OV Fault

14 VDD33 UV Fault

13 (reads 0)

OT Warning

(reads 0)

UT Fault

(reads 0)

12 (reads 0)

11 Invalid ADC Result(s)

10 SYNC Clocked by External Source

MFR_INFO

9

8

7

6

5

4

3

2

1

0

Channel 1 is POWER_GOOD

Channel 0 is POWER_GOOD

LTM4664A Forcing RUN1 Low

LTM4664A Forcing RUN0 Low

RUN1 Pin State

15 Reserved

14 Reserved

13 Reserved

12 Reserved

11 Reserved

10 Reserved

(PAGED)

STATUS_CML

7

6

5

4

3

2

1

0

Invalid/Unsupported Command

Invalid/Unsupported Data

Packet Error Check Failed

Memory Fault Detected

Processor Fault Detected

(reads 0)

RUN0 Pin State

LTM4664A Forcing FAULT1 Low

LTM4664A Forcing FAULT0 Low

FAULT1 Pin State

9

8

7

6

5

4

3

2

1

0

Reserved

FAULT0 Pin State

4664A F09

Other Communication Fault

Other Memory or Logic Fault

Reserved

EEPROM ECC Status

Reserved

DESCRIPTION

MASKABLE GENERATES ALERT BIT CLEARABLE

General Fault or Warning Event

General Non-Maskable Event

Dynamic

Yes

No

Yes

No

Yes

No

Status Derived from Other Bits

Not Directly

No

Figure 9. LTM4664A PSM Status Register Summary

Rev. 0

47

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LTM4664A

DUAL 25A/30A PSM OPERATION

Mapping Faults to FAULT Pins

command, and the ALERT pin will be pulled low. NVM

repair can be attempted by writing the desired configura-

tion to the controller and executing a STORE_USER_ALL

command followed by a CLEAR_FAULTS command.

Channel-to-channel fault (including channels from multiple

LTM4664A PSMs) dependencies can be created by con-

necting FAULT_Cn pins together. In the event of an internal

fault, one or more of the channels is configured to pull the

bussed FAULT_Cn pins low. The other channels are then

configured to shut down when the FAULT_Cn pins are

pulled low. For autonomous group retry, the faulted chan-

nel is configured to let go of the FAULT_Cn pin(s) after a

retry interval, assuming the original fault has cleared. All

the channels in the group then begin a soft-start sequence.

If the fault response is LATCH_OFF, the FAULT_Cn pin

remains asserted low until either the RUN_Cn pin is tog-

gled OFF/ON or the part is commanded OFF/ON. The tog-

gling of the RUN_Cn either by the pin or OFF/ON command

will clear faults associated with the channel. If it is desired

to have all faults cleared when either RUN_Cn pin is tog-

gled or, set bit 0 of MFR_CONFIG_ALL to a 1.

The LTM4664A manufacturing section of the NVM is

mirrored. If both copies are corrupted, the “NVM CRC

Fault” in the STATUS_MFR_SPECIFIC command is set.

If this bit remains set after being cleared by issuing a

CLEAR_FAULTS or writing a 1 to this bit, an irrecoverable

internal fault has occurred. The user is cautioned to dis-

able both output power supply rails associated with this

specific part. There are no provisions for field repair of

NVM faults in the manufacturing section.

SERIAL INTERFACE

The LTM4664A serial interface is a PMBus compliant

slave device and can operate at any frequency between

10kHz and 400kHz. The address is configurable using

either the NVM or an external resistor divider. In addition

the LTM4664A always responds to the global broadcast

address of 0x5A (7-bit) or 0x5B (7-bit).

The status of all faults and warnings is summarized in the

STATUS_WORD and STATUS_BYTE commands.

Additional fault detection and handling capabilities are:

See Table 18.

The serial interface supports the following protocols defined

in the PMBus specifications:1) send command, 2) write byte,

3) write word, 4) group, 5) read byte, 6) read word and 7) read

block. 8) write block. All read operations will return a valid

PEC if the PMBus master requests it. If the PEC_REQUIRED

bit is set in the MFR_CONFIG_ALL command, the PMBus

write operations will not be acted upon until a valid PEC has

been received by the LTM4664A.

Power Good Pins

The PGOOD_Cn pins of the LTM4664A PSM are con-

nected to the open drains of internal MOSFETs. The

MOSFETs turn on and pull the PGOOD_Cn pins low when

the channel output voltage is not within the channel’s

UV and OV voltage thresholds. During TON_DELAY and

TON_RISE sequencing, the PGOOD_Cn pin is held low.

The PGOOD_Cn pin is also pulled low when the respective

RUN_Cn pin is low. The PGOOD_Cn pin response is deg-

litched by an internal 100µs digital filter. The PGOOD_Cn

pin and PGOOD status may be different at times due to

communication latency of up to 10µs.

Communication Protection

PEC write errors (if PEC_REQUIRED is active), attempts

to access unsupported commands, or writing invalid data

to supported commands will result in a CML fault. The

CML bit is set in the STATUS_BYTE and STATUS_WORD

commands, the appropriate bit is set in the STATUS_CML

command, and the ALERT pin is pulled low.

CRC Protection

The integrity of the NVM memory is checked after a power

on reset. A CRC error will prevent the controller from leav-

ing the inactive state. If a CRC error occurs, the CML bit is

set in the STATUS_BYTE and STATUS_WORD commands,

the appropriate bit is set in the STATUS_MFR_SPECIFIC

DEVICE ADDRESSING

The LTM4664A PSM offers four different types of addressing

over the PMBus interface, specifically: 1) global, 2) device,

3) rail addressing and 4) alert response address (ARA).

Rev. 0

48

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM OPERATION

Global addressing provides a means of the PMBus master

to address all LTM4664A PSM devices on the bus. The

LTM4664A PSM global address is fixed 0x5A (7-bit) or

0xB4 (8-bit) and cannot be disabled. Commands sent to

the global address act the same as if PAGE is set to a

value of 0xFF. Commands sent are written to both chan-

nels simultaneously. Global command 0x5B (7-bit) or

0xB6 (8-bit) is paged and allows channel specific com-

mand of all LTM4664A PSM devices on the bus. Other LTC

device types may respond at one or both of these global

addresses. Reading from global addresses is strongly

discouraged.

The I and I

overcurrent monitors are performed by

ADC ^Ir^Neading^Os^Ua^Tnd calculations. Thus these values are

based on average currents and can have a time latency

of up to t

. The I

calculation accounts for the

DCR and^Ct^Oh^Ne^Vir^ERt^Tempera^Otu^Ur^Te coefficient. The input cur-

rent is equal to the voltage measured across the R

resistor divided by the resistors value as set wit^Sh^ENth^Se^E

MFR_IIN_CAL_GAIN command. If this calculated input

current exceeds the IN_OC_WARN_LIMIT the ALERT pin

is pulled low and the IIN_OC_WARN bit is asserted in the

STATUS_INPUT command.

The digital processor within the LTM4664A PSM provides

the ability to ignore the fault, shut down and latch off or

shut down and retry indefinitely (hiccup). The retry inter-

val is set in MFR_RETRY_ DELAY and can be from 120ms

to 83.88 seconds in 1ms increments. The shutdown for

OV/UV and OC can be done immediately or after a user

selectable deglitch time.

Device addressing provides the standard means of the

PMBus master communicating with a single instance of

an LTM4664A PSM. The value of the device address is set

by a combination of the ASEL configuration pin and the

MFR_ ADDRESS command. When this addressing means

is used, the PAGE command determines the channel being

acted upon. Device addressing can be disabled by writing

a value of 0x80 to the MFR_ADDRESS.

Output Overvoltage Fault Response

A programmable overvoltage comparator (OV) guards

against transient overshoots as well as long-term over-

voltages at the output. In such cases, the top MOSFET

is turned off and the bottom MOSFET is turned on.

However, the reverse output current is monitored while

device is in OV fault. When it reaches the limit, both top

and bottom MOSFETs are turned off. The top and bot-

tom MOSFETs will keep their state until the overvoltage

condition is cleared regardless of the PMBus VOUT_OV_

FAULT_RESPONSE command byte value. This hardware

level fault response delay is typically 2µs from the over-

voltage condition to BG asserted high. Using the VOUT_

OV_FAULT_RESPONSE command, the user can select

any of the following behaviors:

Rail addressing provides a means for the bus master to

simultaneously communicate with all channels connected

together to produce a single output voltage (PolyPhase).

While similar to global addressing, the rail address can

be dynamically assigned with the paged MFR_RAIL_

ADDRESS command, allowing for any logical grouping of

channels that might be required for reliable system control.

Reading from rail addresses is also strongly discouraged.

All four means of PMBus addressing require the user to

employ disciplined planning to avoid addressing conflicts.

Communication to LTM4664A PSM devices at global and rail

addresses should be limited to command write operations.

RESPONSES TO V

AND I /I

FAULTS

OUT

IN OUT

n

OV Pull-Down Only (OV Cannot Be Ignored)

V

OV and UV conditions are monitored by compara-

OUT

n

Shut Down (Stop Switching) Immediately—Latch Off

tors. The OV and UV limits are set in three ways:

n

Shut Down Immediately—Retry Indefinitely at the Time

Interval Specified in MFR_RETRY_DELAY

n

As a Percentage of the V_OUTif Using the Resistor

Configuration Pins

Either the Latch Off or Retry fault responses can be

de-glitched in increments of (0-7) • 10µs. See Table 14.

n

In NVM if Either Programmed at the Factory or Through

the GUI

n

By PMBus Command

Rev. 0

49

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LTM4664A

DUAL 25A/30A PSM OPERATION

Output Undervoltage Response

sequence is started. The resolution of the TON_MAX_

FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT _LIMIT

is not reached within the TON_MAX_FAULT_LIMIT time,

the response of this fault is determined by the value of

the TON_MAX_FAULT_RESPONSE command value. This

response may be one of the following:

The response to an undervoltage comparator output can

be the following:

n

Ignore

n

Shut Down Immediately—Latch Off

n

Ignore

n

Shut Down Immediately—Retry Indefinitely at the Time

Interval Specified in MFR_RETRY_DELAY.

n

Shut Down (Stop Switching) Immediately—Latch Off

The UV responses can be deglitched. See Table 14.

Shut Down Immediately—Retry Indefinitely at the Time

Interval Specified in MFR_RETRY_DELAY.

Peak Output Overcurrent Fault Response

This fault response is not deglitched. A value of 0 in

TON_MAX_FAULT_LIMIT means the fault is ignored. The

TON_MAX_FAULT_LIMIT should be set longer than the

TON_RISE time. It is recommended TON_MAX_FAULT_

LIMIT always be set to a non-zero value, otherwise the

output may never come up and no flag will be set to the

user. See Table 16.

Due to the current mode control algorithm, peak out-

put current across the inductor is always limited on a

cycle-by-cycle basis. The value of the peak current limit

is specified in Electrical Characteristics table. The cur-

rent limit circuit operates by limiting the COMP_Cn max-

imum voltage. Since internal DCR sensing is used, the

COMP_Cn maximum voltage has a temperature depen-

dency directly proportional to the TC of the DCR of the

inductor. The LTM4664A PSM automatically monitors

the external temperature sensors and modifies the maxi-

mum allowed COMP_Cn to compensate for this term. The

IOUT_OC_FAULT_LIMIT section provides data points for

RESPONSES TO V OV FAULTS

IN

V overvoltage is measured with the ADC. The response

IN

is naturally deglitched by the 100ms typical response time

of the ADC. The fault responses are:

I

Limiting on page103.

OUT

n

Ignore

The overcurrent fault processing circuitry can execute the

following behaviors:

n

Shut Down Immediately—Latch Off

n

Shut Down Immediately—Retry Indefinitely at the

Time Interval Specified in MFR_RETRY_DELAY. See

Table 16.

n

Current Limit Indefinitely

n

Shut Down Immediately—Latch Off

n

Shut Down Immediately—Retry Indefinitely at the Time

Interval Specified in MFR_RETRY_DELAY.

RESPONSES TO OT/UT FAULTS

The overcurrent responses can be deglitched in incre-

ments of (0-7) • 16ms. See Table 15.

Internal Overtemperature Fault Response

An internal temperature sensor protects against NVM

damage. Above 85°C, no writes to NVM are recom-

mended. Above 130°C, the internal overtemperature warn

threshold is exceeded and the part disables the NVM and

does not re-enable until the temperature has dropped

to 125°C. When the die temperature exceed 160°C the

internal temperature fault response is enabled and the

PWM is disabled until the die temperature drops below

150°C. Temperature is measured by the ADC. Internal

RESPONSES TO TIMING FAULTS

TON_MAX_FAULT_LIMIT is the time allowed for V

to

OUT

rise and settle at start-up. The TON_MAX_FAULT_LIMIT

condition is predicated upon detection of the VOUT_UV_

FAULT_LIMIT as the output is undergoing a SOFT_START

sequence. The TON_MAX_ FAULT_LIMIT time is started

after TON_DELAY has been reached and a SOFT_START

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LTM4664A

DUAL 25A/30A PSM OPERATION

temperature faults cannot be ignored. Internal tempera-

ture limits cannot be adjusted by the user. See Table 14.

FAULT LOGGING

The LTM4664A PSM has fault logging capability. Data is

logged into memory in the order shown in Table 19. The data

is stored in a continuously updated buffer in RAM. When a

fault event occurs, the fault log buffer is copied from the RAM

buffer into NVM. Fault logging is allowed at temperatures

above 85°C; however, retention of 10 years is not guaranteed.

When the die temperature exceeds 130°C the fault logging is

delayed until the die temperature drops below 125°C. The fault

log data remains in NVM until a MFR_FAULT _LOG_CLEAR

command is issued. Issuing this command re-enables the

fault log feature. Before re-enabling fault log, be sure no faults

are present and a CLEAR_FAULTS command has been issued.

External Overtemperature and Undertemperature

Fault Response

Two internal temperature sensors are used to sense the

temperature of critical circuit elements like inductors

and power MOSFETs on each channel. The OT_FAULT_

RESPONSE and UT_FAULT_ RESPONSE commands are

used to determine the appropriate response to an overtem-

perature and under temperature condition, respectively. If

no external sense elements are used (not recommended)

set the UT_FAULT_ RESPONSE to ignore—and set the

UT_FAULT_LIMIT to 275°C. The fault responses are:

When the LTM4664A PSM powers-up or exits its reset

state, it checks the NVM for a valid fault log. If a valid fault

log exists in NVM, the “Valid Fault Log” bit in the STATUS_

MFR_SPECIFIC command will be set and an ALERT event

will be generated. Also, fault logging will be blocked until

the LTM4664A PSM has received a MFR_FAULT_LOG_

CLEAR command before fault logging will be re-enabled.

n

Ignore

n

Shut Down Immediately—Latch Off

n

Shut Down Immediately—Retry Indefinitely at the Time

Interval Specified in MFR_RETRY_DELAY. See Table 16.

RESPONSES TO INPUT OVERCURRENT AND OUTPUT

UNDERCURRENT FAULTS

Input overcurrent and output undercurrent are measured

with the ADC. The fault responses are:

The information is stored in EEPROM in the event of

any fault that disables the controller on either channel. A

FAULT_Cn being externally pulled low will not trigger a

fault logging event.

n

Ignore

BUS TIMEOUT PROTECTION

n

Shut Down Immediately—Latch Off

The LTM4664A PSM implements a timeout feature to avoid

persistent faults on the serial interface. The data packet timer

begins at the first START event before the device address

write byte. Data packet information must be completed within

30ms or the LTM4664A PSM will three-state the bus and

ignore the given data packet. If more time is required, assert

bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts of

255ms. Data packet information includes the device address

byte write, command byte, repeat start event (if a read oper-

ation), device address byte read (if a read operation), all data

bytes and the PEC byte if applicable.

n

Shut Down Immediately—Retry Indefinitely at the Time

Interval Specified in MFR_RETRY_DELAY. See Table 15.

RESPONSES TO EXTERNAL FAULTS

When either FAULT_Cn pin is pulled low, the OTHER bit is

set in the STATUS_WORD command, the appropriate bit

is set in the STATUS_MFR_SPECIFIC command, and the

ALERT pin is pulled low. Responses are not deglitched.

Each channel can be configured to ignore or shut down

then retry in response to its FAULT_Cn pin going low by

modifying the MFR_FAULT_RESPONSE command. To

avoid the ALERT pin asserting low when FAULT_Cn is

pulled low, assert bit 1 of MFR_CHAN_CONFIG, or mask

the ALERT using the SMBALERT_MASK command.

The LTM4664A PSM allows longer PMBus timeouts for

block read data packets. This timeout is proportional to

the length of the block read. The additional block read

timeout applies primarily to the MFR_FAULT_LOG com-

mand. The timeout period defaults to 32ms.

Rev. 0

51

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LTM4664A

DUAL 25A/30A PSM OPERATION

The user is encouraged to use as high a clock rate as

possible to maintain efficient data packet transfer between

all devices sharing the serial bus interface. The LTM4664A

PSM supports the full PMBus frequency range from

10kHz to 400kHz.

signals on the bus. The two-bus lines, SDA and SCL, must

be high when the bus is not in use. External pull-up resis-

tors or current sources are required on these lines. The

LTM4664A is a slave device. The master can communicate

with the LTM4664A using the following formats:

n

Master Transmitter, Slave Receiver

2

SIMILARITY BETWEEN PMBus, SMBus AND I C

2-WIRE INTERFACE

n

Master Receiver, Slave Transmitter

The following PMBus protocols are supported:

The PMBus 2-wire interface is an incremental extension

2

n

of the SMBus. SMBus is built upon I C with some minor

Write Byte, Write Word, Send Byte

differences in timing, DC parameters and protocol. The

PMBus/SMBus protocols are more robust than simple

I²C byte commands because PMBus/SMBus provide

timeouts to prevent persistent bus errors and optional

packet error checking (PEC) to ensure data integrity. In

n

Read Byte, Read Word, Block Read, Block Write

n

Alert Response Address

Figure 11 thru Figure 28 illustrate the aforementioned

PMBus protocols. All transactions support PEC and GCP

(group command protocol). The Block Read supports 255

bytes of returned data. For this reason, the PMBus time-

out may be extended when reading the fault log.

2

general, a master device that can be configured for I C

communication can be used for PMBus communication

with little or no change to hardware or firmware. Repeat

2

start (restart) is not supported by all I C controllers but

Figure 11 is a key to the protocol diagrams in this section.

PEC is optional.

is required for SMBus/PMBus reads. If a general purpose

2

I C controller is used, check that repeat start is supported.

A value shown below a field in the following figures is

mandatory value for that field.

The LTM4664A PSM supports the maximum SMBus

clock speed of 100kHz and is compatible with the higher

speed PMBus specification (between 100kHz and 400kHz)

if MFR_ COMMON polling or clock stretching is enabled.

For robust communication and operation refer to the Note

section in the PMBus command summary. Clock stretch-

ing is enabled by asserting bit 1 of MFR_CONFIG_ALL.

The data formats implemented by PMBus are:

n

Master transmitter transmits to slave receiver. The

transfer direction in this case is not changed.

n

Master reads slave immediately after the first byte. At

the moment of the first acknowledgment (provided by

the slave receiver) the master transmitter becomes a

master receiver and the slave receiver becomes a slave

transmitter.

For a description of the minor extensions and exceptions

PMBus makes to SMBus, refer to PMBus Specification

Part 1 Revision 1.2: Paragraph 5: Transport.

For a description of the differences between SMBus

and I²C, refer to System Management Bus (SMBus)

Specification Version 2.0: Appendix B—Differences

n

Combined format. During a change of direction within

a transfer, the master repeats both a start condition

and the slave address but with the R/Wbit reversed. In

this case, the master receiver terminates the transfer

by generating a NACK on the last byte of the transfer

and a STOP condition.

2

Between SMBus and I C.

PMBus SERIAL DIGITAL INTERFACE

The LTM4664A PSM communicates with a host (master)

using the standard PMBus serial bus interface. The Timing

Diagram, Figure 10, shows the timing relationship of the

Rev. 0

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LTM4664A

DUAL 25A/30A PSM OPERATION

Refer to Figure 11 for a legend.

Handshaking features are included to ensure robust system communication. Please refer to the PMBus Communication

and Command Processing subsection of the Dual 25A/30A PSM Applications Information section for further details.

SDA

t

r

t

SU(DAT)

t

SP

t

HD(SDA)

r

t

f

t

f

BUF

LOW

SCL

t

SU(STO)

HD(STA)

SU(STA)

t

HIGH

HD(DAT)

4664A F10

START

CONDITION

REPEATED START

CONDITION

STOP

START

CONDITION CONDITION

Figure 10. PMBus Timing Diagram

Table 6. Abbreviations of Supported Data Formats

PMBus

SPECIFICATION

REFERENCE

LTC

TERMINOLOGY DEFINITION

TERMINOLOGY

EXAMPLE

N

L11

Linear

Part II ¶7.1

Linear_5s_11s Floating point 16-bit data: value = Y • 2 ,

where N = b[15:11] and Y = b[10:0], both

two’s compliment binary integers

b[15:0] = 0x9807 = 10011_000_0000_0111

–13

value = 7 • 2 = 854E-6

–12

L16

CF

Linear

Part II ¶8.2

Part II ¶7.2

Part II ¶10.3

Linear_16u

Varies

Reg

Floating point 16-bit data: value = Y • 2

where Y = b[15:0], an unsigned integer

,

b[15:0] = 0x4C00 = 0100_1100_0000_0000

–12

VOUT_MODE

value = 19456 • 2 = 4.75

DIRECT

16-bit data with a custom format defined in Often an unsigned or two’s compliment

the detailed PMBus command description integer

Reg

ASC

Register Bits

Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command

command description

Text Characters Part II ¶22.2.1

ASCII

ISO/IEC 8859-1 [A05]

LTC (0x4C5443)

Rev. 0

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LTM4664A

DUAL 25A/30A PSM OPERATION

FIGURE 11 THRU FIGURE 28 PMBus PROTOCOLS

S

START CONDITION

Sr

REPEATED START CONDITION

Rd READ (BIT VALUE OF 1)

Wr WRITE (BIT VALUE OF 0)

A

ACKNOWLEDGE (THIS BIT POSITION MAY BE 0

FOR AN ACK OR 1 FOR A NACK)

P

STOP CONDITION

PEC PACKET ERROR CODE

MASTER TO SLAVE

SLAVE TO MASTER

...

CONTINUATION OF PROTOCOL

4664A F11

Figure 11. PMBus Packet Protocol Diagram Element Key

1

7

1

S

SLAVE ADDRESS Rd/Wr

A

P

4664A F12

Figure 12. Quick Command Protocol

1

7

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

P

4664A F13

Figure 13. Send Byte Protocol

1

7

1

8

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

PEC

A

P

4664A F14

Figure 14. Send Byte Protocol with PEC

1

7

1

8

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

DATA BYTE

A

P

4664A F15

Figure 15. Write Byte Protocol

1

7

1

8

1

8

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

DATA BYTE

A

PEC

A

P

4664A F16

Figure 16. Write Byte Protocol with PEC

1

7

1

8

1

8

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

DATA BYTE

A

DATA BYTE

A

P

4664A F17

Figure 17. Write Word Protocol

1

7

1

8

1

8

1

8

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

DATA BYTE

A

DATA BYTE

A

PEC

A

P

4664A F18

Figure 18. Write Word Protocol with PEC

Rev. 0

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LTM4664A

DUAL 25A/30A PSM OPERATION

1

7

1

8

1

7

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

Sr SLAVE ADDRESS Rd

A

DATA BYTE

A

P

4664A F19

Figure 19. Read Byte Protocol

1

7

1

8

1

7

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

Sr SLAVE ADDRESS Rd

A

DATA BYTE

A

PEC

A

P

4664A F20

Figure 20. Read Byte Protocol with PEC

1

7

1

8

1

7

1

8

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

Sr SLAVE ADDRESS Rd

A

DATA BYTE LOW

A

DATA BYTE HIGH

A

P

4664A F21

Figure 21. Read Word Protocol

1

7

1

8

1

7

1

8

1

8

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

Sr SLAVE ADDRESS Rd

A

DATA BYTE LOW

A

DATA BYTE HIGH

A

PEC

A

P

4664A F22

Figure 22. Read Word Protocol with PEC

1

7

1

8

1

7

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

Sr SLAVE ADDRESS Rd

A

BYTE COUNT = N

A

…

8

1

8

1

…

8

1

DATA BYTE 1

A

DATA BYTE 2

A

DATA BYTE N

A

P

4664A F23

Figure 23. Block Read Protocol

1

7

1

8

1

7

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

Sr SLAVE ADDRESS Rd

A

BYTE COUNT = N

A

…

8

1

8

1

…

8

1

8

1

DATA BYTE 1

A

DATA BYTE 2

A

DATA BYTE N

A

PEC

A

P

4664A F24

Figure 24. Block Read Protocol with PEC

Rev. 0

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LTM4664A

DUAL 25A/30A PSM OPERATION

1

7

1

8

1

8

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

BYTE COUNT = M

A

DATA BYTE 1

A

…

8

1

8

1

DATA BYTE 2

A

…

DATA BYTE M

A

…

1

7

1

8

1

8

1

Sr SLAVE ADDRESS Rd

A

BYTE COUNT = N

A

DATA BYTE 1

A

…

8

1

…

8

1

DATA BYTE 2

A

DATA BYTE N

A

P

4664A F25

Figure 25. Block Write – Block Read Process Call

1

7

1

8

1

8

1

8

1

S

SLAVE ADDRESS Wr

A

COMMAND CODE

A

BYTE COUNT = M

A

DATA BYTE 1

A

…

8

1

8

1

DATA BYTE 2

A

…

DATA BYTE M

A

…

1

7

1

8

1

8

1

Sr SLAVE ADDRESS Rd

A

BYTE COUNT = N

A

DATA BYTE 1

A

…

8

1

…

8

1

8

1

DATA BYTE 2

A

DATA BYTE N

A

PEC

A

P

4678A F22

Figure 26. Block Write – Block Read Process Call with PEC

1

7

1

8

1

ALERT RESPONSE

ADDRESS

S

Rd

A

DEVICE ADDRESS

A

P

4664A F27

Figure 27. Alert Response Address Protocol

1

7

1

8

1

8

1

ALERT RESPONSE

ADDRESS

S

Rd

A

DEVICE ADDRESS

A

PEC

A

P

4664A F28

Figure 28. Alert Response Address Protocol with PEC

Rev. 0

56

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LTM4664A

PMBus COMMAND SUMMARY

PMBus COMMANDS

not supported by the manufacturer. Attempting to access

non-supported or reserved commands may result in a

CML command fault event. All output voltage settings and

Table 7 lists supported PMBus commands and manu-

facturer specific commands. A complete description of

these commands can be found in the “PMBus Power

System Mgt Protocol Specification – Part II – Revision

1.2”. Users are encouraged to reference this specifica-

tion. Exceptions or manufacturer specific implementations

are listed in Table 7. Floating point values listed in the

“DEFAULT VALUE” column are either Linear 16-bit Signed

(PMBus Section 8.3.1) or Linear_5s_11s (PMBus Section

7.1) format, whichever is appropriate for the command.

All commands from 0xD0 through 0xFF not listed in

Table 7 are implicitly reserved by the manufacturer. Users

should avoid blind writes within this range of commands

to avoid undesired operation of the part. All commands

from 0x00 through 0xCF not listed in Table 7 are implicitly

measurements are based on the VOUT_MODE setting of

–12

0x14. This translates to an exponent of 2

.

If PMBus commands are received faster than they are

being processed, the part may become too busy to handle

new commands. In these circumstances the part follows

the protocols defined in the PMBus Specification v1.2,

Part II, Section 10.8.7, to communicate that it is busy.

The part includes handshaking features to eliminate busy

errors and simplify error handling software while ensur-

ing robust communication and system behavior. Please

refer to the subsection titled PMBus Communication

and Command Processing in the Dual 25A/30A PSM

Applications Information section for further details.

Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations are Detailed in Table 8)

CMD

DATA

DEFAULT

VALUE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

PAGE

0x00 Provides integration with multi-page

PMBus devices.

R/W Byte

N

Y

Reg

0x00

0x80

0x1E

NA

90

OPERATION

0x01 Operating mode control. On/off, margin

high and margin low.

R/W Byte

Y

94

ON_OFF_CONFIG

0x02 RUN pin and PMBus bus on/off command

configuration.

CLEAR_FAULTS

0x03 Clear any fault bits that have been set.

Send Byte

W Block

N

119

90

PAGE_PLUS_WRITE

0x05 Write a command directly to a

specified page.

PAGE_PLUS_READ

WRITE_PROTECT

0x06 Read a command directly from a

specified page.

Block R/W

R/W Byte

N

90

91

0x10 Level of protection provided by the device

against accidental changes.

Reg

Y

0x00

STORE_USER_ALL

0x15 Store user operating memory to EEPROM. Send Byte

N

NA

130

RESTORE_USER_ALL

0x16 Restore user operating memory from

EEPROM.

Send Byte

CAPABILITY

0x19 Summary of PMBus optional communication

protocols supported by this device.

R Byte

N

0xB0

118

SMBALERT_MASK

VOUT_MODE

0x1B Mask ALERT activity

Block R/W

R Byte

Y

Reg

See CMD

119

100

–12

0x20 Output voltage format and exponent (2 ).

2

0x14

VOUT_COMMAND

VOUT_MAX

0x21 Nominal output voltage set point.

R/W Word

Y

L16

V

Y

1.0

101

100

0x1000

0x24 Upper limit on the commanded output

voltage including VOUT_MARGIN_HI.

1.8

0x1CCD

Rev. 0

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LTM4664A

PMBus COMMAND SUMMARY

CMD

DATA

DEFAULT

VALUE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

PAGE

VOUT_MARGIN_HIGH

0x25 Margin high output voltage set point. Must R/W Word

be greater than VOUT_COMMAND.

Y

N

Y

L16

L11

L16

Reg

L16

Reg

L11

Reg

L11

Reg

L11

Reg

V

Y

1.05

101

0x10CD

VOUT_MARGIN_LOW

VOUT_TRANSITION_ RATE

FREQUENCY_SWITCH

VIN_ON

0x26 Margin low output voltage set point. Must R/W Word

be less than VOUT_COMMAND.

V

0.95

0x0F33

101

107

98

0X27 Rate the output changes when V

commanded to a new value.

R/W Word

V/ms

kHz

V

0.25

0x8042

OUT

0x33 Switching frequency of the controller.

R/W Word

350k

0xFABC

0x35 Input voltage at which the unit should start R/W Word

power conversion.

4.75

0xCA60

99

VIN_OFF

0x36 Input voltage at which the unit should stop R/W Word

power conversion.

V

4.5

0xCA40

99

VOUT_OV_FAULT_LIMIT

0x40 Output overvoltage fault limit.

R/W Word

R/W Byte

R/W Word

R/W Byte

R/W Word

R/W Byte

R/W Word

R/W Byte

R/W Word

R/W Byte

V

1.1

0x119A

100

109

100

101

110

103

112

104

105

114

105

106

114

VOUT_OV_FAULT_

RESPONSE

0x41 Action to be taken by the device when an

output overvoltage fault is detected.

0xB8

VOUT_OV_WARN_LIMIT

VOUT_UV_WARN_LIMIT

VOUT_UV_FAULT_LIMIT

0x42 Output overvoltage warning limit.

0x43 Output undervoltage warning limit.

0x44 Output undervoltage fault limit.

V

1.075

0x1133

0.925

0x0ECD

0.9

0x0E66

VOUT_UV_FAULT_

RESPONSE

0x45 Action to be taken by the device when an

output undervoltage fault is detected.

0xB8

IOUT_OC_FAULT_LIMIT

0x46 Output overcurrent fault limit.

A

40

0xE280

IOUT_OC_FAULT_ RESPONSE 0x47 Action to be taken by the device when an

output overcurrent fault is detected.

0x00

IOUT_OC_WARN_LIMIT

0x4A Output overcurrent warning limit.

A

C

30.0

0xDBC0

OT_FAULT_LIMIT

0x4F External overtemperature fault limit.

128

0xF200

OT_FAULT_RESPONSE

OT_WARN_LIMIT

0x50 Action to be taken by the device when an

external overtemperature fault is detected,

0xB8

0x51 External overtemperature warning limit.

C

125

0xEBE8

UT_FAULT_LIMIT

0x53 External undertemperature fault limit.

–45

0xE530

UT_FAULT_RESPONSE

0x54 Action to be taken by the device when

an external undertemperature fault is

detected.

0xB8

VIN_OV_FAULT_LIMIT

0x55 Input supply overvoltage fault limit.

R/W Word

R/W Byte

R/W Word

N

Y

N

L11

Reg

L11

V

Y

15.5

100

109

99

0xD3E0

VIN_OV_FAULT_ RESPONSE 0x56 Action to be taken by the device when an

input overvoltage fault is detected.

0x80

VIN_UV_WARN_LIMIT

0x58 Input supply undervoltage warning limit.

V

A

4.68

0xCA53

IIN_OC_WARN_LIMIT

0x5D Input supply overcurrent warning limit.

10.0

0xD280

104

Rev. 0

58

For more information www.analog.com

LTM4664A

PMBus COMMAND SUMMARY

CMD

DATA

PAGED FORMAT UNITS NVM

DEFAULT

VALUE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGE

TON_DELAY

0x60 Time from RUN and/or Operation on to

output rail turn-on.

R/W Word

Y

L11

ms

Y

0.0

0x8000

106

TON_RISE

0x61 Time from when the output starts to rise

R/W Word

R/W Byte

Y

L11

ms

Y

3

106

107

until the output voltage reaches the V

commanded value.

0xC300

OUT

TON_MAX_FAULT_LIMIT

0x62 Maximum time from the start of

Y

L11

ms

Y

5

TON_RISE for VO to cross the

0xCA80

UT

VOUT_UV_FAULT_LIMIT.

TON_MAX_FAULT_

RESPONSE

0x63 Action to be taken by the device when a

TON_ MAX_FAULT event is detected.

Y

Reg

L11

Y

0xB8

112

107

108

TOFF_DELAY

0x64 Time from RUN and/or Operation off to the R/W Word

start of TOFF_FALL ramp.

ms

0.0

0x8000

TOFF_FALL

0x65 Time from when the output starts to fall

until the output reaches zero volts.

R/W Word

3

0xC300

TOFF_MAX_WARN_ LIMIT

0x66 Maximum allowed time, after TOFF_FALL

completed, for the unit to decay below

12.5%.

R/W Word

0

0x8000

STATUS_BYTE

STATUS_WORD

0x78 One byte summary of the unit’s fault

condition.

R/W Byte

Y

Reg

NA

120

121

0x79 Two byte summary of the unit’s fault

condition.

R/W Word

STATUS_VOUT

0x7A Output voltage fault and warning status.

0x7B Output current fault and warning status.

0x7C Input supply fault and warning status.

R/W Byte

Y

N

Y

Reg

NA

121

122

123

STATUS_IOUT

STATUS_INPUT

STATUS_TEMPERATURE

0x7D External temperature fault and warning

status for READ_TEMERATURE_1.

STATUS_CML

0x7E Communication and memory fault and

warning status.

R/W Byte

N

Y

Reg

NA

123

124

STATUS_MFR_SPECIFIC

0x80 Manufacturer specific fault and state

information.

READ_VIN

0x88 Measured input supply voltage.

0x89 Measured input supply current.

0x8B Measured output voltage.

0x8C Measured output current.

R Word

N

Y

L11

L16

L11

V

A

V

A

C

NA

127

READ_IIN

READ_VOUT

READ_IOUT

READ_TEMPERATURE_1

0x8D External temperature sensor temperature.

This is the value used for all temperature

related processing, including

IOUT_CAL_GAIN.

READ_TEMPERATURE_2

0x8E Internal die junction temperature. Does

not affect any other commands.

R Word

N

L11

C

NA

127

READ_FREQUENCY

READ_POUT

0x95 Measured PWM switching frequency.

0x96 Measured output power

R Word

R Byte

Y

N

L11

Reg

Hz

W

NA

N/A

127

128

118

READ_PIN

0x97 Calculated input power

N/A

PMBus_REVISION

0x98 PMBus revision supported by this device.

Current revision is 1.2.

0x22

MFR_ID

0x99 The manufacturer ID of the LTM4664A in

ASCII.

R String

N

ASC

LTC

118

Rev. 0

59

For more information www.analog.com

LTM4664A

PMBus COMMAND SUMMARY

CMD

DATA

DEFAULT

VALUE

COMMAND NAME

MFR_MODEL

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

PAGE

0x9A Manufacturer part number in ASCII.

R String

R Word

N

Y

ASC

L16

LTM4664 118

MFR_VOUT_MAX

0xA5 Maximum allowed output voltage

including VOUT_OV_FAULT_LIMIT.

V

1.8

0x1CCD

102

128

118

MFR_PIN_ACCURACY

USER_DATA_00

0xAC Returns the accuracy of the READ_PIN

command

R Byte

N

%

5.0%

NA

0xB0 OEM RESERVED. Typically used for part

serialization.

R/W Word

Reg

Y

USER_DATA_01

USER_DATA_02

0xB1 Manufacturer reserved for LTpowerPlay^®.

R/W Word

Y

N

Reg

Y

NA

118

0xB2 OEM RESERVED. Typically used for part

serialization

USER_DATA_03

USER_DATA_04

MFR_EE_UNLOCK

MFR_EE_ERASE

MFR_EE_DATA

0xB3 An NVM word available for the user.

0xB4 An NVM word available for the user.

0xBD Contact factory.

R/W Word

Y

N

Reg

Y

0x0000

118

135

92

0xBE Contact factory.

0xBF Contact factory.

MFR_CHAN_CONFIG

0xD0 Configuration bits that are channel

specific.

R/W Byte

Y

Reg

Y

0x1D

MFR_CONFIG_ALL

0xD1 General configuration bits.

N

Y

Reg

Y

0x21

93

MFR_FAULT_ PROPAGATE

0xD2 Configuration that determines which faults R/W Word

0x6993

115

are propagated to the FAULT pin.

MFR_PWM_COMP

0xD3 PWM loop compensation configuration

0xD4 Configuration for the PWM engine.

R/W Byte

Y

Reg

Y

0x28

0xC7

0xC0

96

95

MFR_PWM_MODE

MFR_FAULT_RESPONSE

0xD5 Action to be taken by the device when the

113

FAULT pin is externally asserted low.

MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when an

internal overtemperature fault is detected.

R Byte

N

Y

Reg

L11

0xC0

NA

113

128

MFR_IOUT_PEAK

0xD7 Report the maximum measured

value of READ_ IOUT since last

MFR_CLEAR_PEAKS.

R Word

A

MFR_ADC_CONTROL

MFR_RETRY_DELAY

MFR_RESTART_DELAY

MFR_VOUT_PEAK

MFR_VIN_PEAK

0xD8 ADC telemetry parameter selected for

repeated fast ADC read back

R/W Byte

N

Y

N

Y

Reg

L11

L16

L11

0x00

129

108

128

0xDB Retry interval during FAULT retry mode.

R/W Word

ms

V

Y

250.0

0xF3E8

0xDC Minimum time the RUN pin is held low by R/W Word

the LTM4664A.

150

0xF258

0xDD Maximum measured value of READ_VOUT

since last MFR_CLEAR_PEAKS.

R Word

NA

0xDE Maximum measured value of READ_VIN

since last MFR_CLEAR_PEAKS.

V

MFR_TEMPERATURE_1_ PEAK 0xDF Maximum measured value of external

Temperature (READ_TEMPERATURE_1)

C

since last MFR_CLEAR_PEAKS.

MFR_READ_IIN_PEAK

0xE1 Maximum measured value of READ_IIN

command since last MFR_CLEAR_PEAKS

R Word

N

L11

A

NA

128

MFR_CLEAR_PEAKS

MFR_READ_ICHIP

0xE3 Clears all peak values.

Send Byte

R Word

N

NA

120

128

0xE4 Measured supply current of the SV pin

IN

Rev. 0

60

For more information www.analog.com

LTM4664A

PMBus COMMAND SUMMARY

CMD

DATA

PAGED FORMAT UNITS NVM

DEFAULT

VALUE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGE

MFR_IOUT_CAL_GAIN

0xDA The ratio of the voltage at the current

sense pins to the sensed current. For

devices using a fixed current sense

resistor. It is the resistance value in mohm.

OxAA8B set at factory

R Word

Y

L11

0.350mΩ 102

MFR_PADS

0xE5 Digital status of the I/O pads.

R Word

R/W Byte

R Word

N

Reg

Y

NA

124

92

2

MFR_ADDRESS

MFR_SPECIAL_ID

0xE6 Sets the 7-bit I C address byte.

0x4F

0xE7 Manufacturer code representing the

LTM4664A and revision

0x4100

118

MFR_IIN_CAL_GAIN

0xE8 The resistance value of the input current

sense element in mΩ.

R/W Word

Send Byte

N

L11

mΩ

Y

2.0

104

131

0xC200

MFR_FAULT_LOG_ STORE

0xEA Command a transfer of the fault log from

RAM to EEPROM.

NA

MFR_INFO

0xB6 Contact factory.

135

MFR_FAULT_LOG_ CLEAR

0xEC Initialize the EEPROM block reserved for

fault logging.

Send Byte

N

NA

MFR_FAULT_LOG

MFR_COMMON

0xEE Fault log data bytes.

R Block

R Byte

N

Reg

Y

NA

131

125

0xEF Manufacturer status bits that are common

across multiple LTC chips.

MFR_COMPARE_USER_ ALL

0xF0 Compares current command contents

with NVM.

Send Byte

R Word

N

Y

N

Y

NA

130

129

97

MFR_TEMPERATURE_2_ PEAK 0xF4 Peak internal die temperature since last

MFR_ CLEAR_PEAKS.

L11

Reg

CF

C

MFR_PWM_CONFIG

MFR_IOUT_CAL_GAIN_ TC

MFR_RVIN

0xF5 Set numerous parameters for the DC/DC

controller including phasing.

R/W Byte

R/W Word

R Word

Y

N

Y

0x10

0xF6 Temperature coefficient of the current

sensing element.

ppm/

˚C

3900

0x0F3C

102

99

0xF7 The resistance value of the V pin filter

L11

CF

mΩ

1000

0x03E8

IN

element in mΩ. Set at Factory

MFR_TEMP_1_GAIN

MFR_TEMP_1_OFFSET

MFR_RAIL_ADDRESS

0xF8 Sets the slope of the external temperature R/W Word

sensor.

0.9

0x3FAE

105

92

0xF9 Sets the offset of the external temperature R/W Word

sensor with respect to –273.1°C

L11

Reg

CF

C

0.0

0x8000

0xFA Common address for PolyPhase outputs

to adjust common parameters.

R/W Byte

0x80

MFR_REAL_TIME

MFR_RESET

0xFB 48-bit share-clock counter value.

R Block

N

NA

xx

0xFD Commanded reset without requiring a

power down.

Send Byte

94

Note 1. Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and

RESTORE_USER_ALL commands, respectively.

Note 2. Commands with a default value of NA indicate “not applicable”. Commands with a default value of FS indicate “factory set on a per part basis”.

Note 3. The LTM4664A contains additional commands not listed in Table 7. Reading these commands is harmless to the operation of the IC; however, the

contents and meaning of these commands can change without notice.

Note 4. Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written.

Note 5. Writing to commands not published in Table 7 is not permitted.

Note 6. The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s

data sheet for each part for a complete definition of a command’s function. LTC strives to keep command functionality compatible between all LTC

devices. Differences may occur to address specific product requirements.

Rev. 0

61

For more information www.analog.com

LTM4664A

PMBus COMMAND SUMMARY

Table 8. Data Format Abbreviations

L11

Linear_5s_11s

PMBus data field b[15:0]

N

Value = Y • 2

where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer

Example:

For b[15:0] = 0x9807 = ‘b10011_000_0000_0111

–13

–6

Value = 7 • 2 = 854 • 10

From “PMBus Spec Part II: Paragraph 7.1”

L16

Linear_16u

PMBus data field b[15:0]

N

Value = Y • 2

where Y = b[15:0] is an unsigned integer and N = VOUT_MODE_PARAMETER is a 5-bit two’s complement exponent that is

hardwired to –12 decimal

Example:

For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000

–12

Value = 19456 • 2 = 4.75 From “PMBus Spec Part II: Paragraph 8.2”

Reg

L16

Register

PMBus data field b[15:0] or b[7:0].

Bit field meaning is defined in detailed PMBus Command Description.

Integer Word

PMBus data field b[15:0]

Value = Y

where Y = b[15:0] is a 16-bit unsigned integer

Example:

For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111

Value = 38919 (decimal)

CF

Custom Format

ASCII Format

Value is defined in detailed PMBus Command Description.

This is often an unsigned or two’s complement integer scaled by an MFR specific constant.

ASC

A variable length string of text characters conforming to ISO/IEC 8859-1 standard.

Rev. 0

62

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

V TO V

STEP-DOWN RATIOS

OUTPUT CAPACITORS

IN

OUT

There are restrictions in the maximum V and V

step-

The LTM4664A PSM channel outputs are designed for low

output voltage ripple noise and good transient response.

IN

OUT

down ratio that can be achieved for a given input voltage.

Each output of the LTM4664A PSM is capable of 95% duty

The bulk output capacitors defined as C

are chosen

OUT

cycle at 500kHz, but the V to V

minimum dropout is

with low enough effective series resistance (ESR) to meet

the output voltage ripple and transient requirements. C

IN

OUT

still a function of its load current and will limit output current

OUT

capability related to high duty cycle on the topside switch.

can be a low ESR tantalum capacitor, a low ESR polymer

capacitor or ceramic capacitor. The typical output capac-

itance range for each output is from 400µF to 1000µF.

Additional output filtering may be required by the system

designer, if further reduction of output ripple or dynamic

transient spikes is required. Table 12 shows a matrix of dif-

ferent output voltages and output capacitors to minimize

the voltage droop and overshoot during a 12.5A to 25A

step, 12A/µs transient each channel. Table 12 optimizes

total equivalent ESR and total bulk capacitance to optimize

the transient performance. Stability criteria are consid-

ered in the Table 12 matrix, and the LTpowerCAD Design

Tool will be provided for stability analysis. Multiphase

operation reduces effective output ripple as a function

of the number of phases. Application Note 77 discusses

this noise reduction versus output ripple current cancel-

lation, but the output capacitance should be considered

carefully as a function of stability and transient response.

The LTpowerCAD Design Tool can calculate the output

ripple reduction as the number of implemented phases

Minimum on-time t_ON(MIN)is another consideration in oper-

ating at a specified duty cycle while operating at a certain

frequency due to the fact that t

< D/f , where D is

ON(MIN)

SW

duty cycle and f is the switching frequency. t

is

SW

ON(MIN)

specified in the electrical parameters as 60ns. See Note 6

in the Electrical Characteristics section for output current

guideline. Since the LTM4664A front end 4:1 divider feeds

the two 25A/30A PSM channels with a V_OUT2range of 7.5V

to 14.5V, there should be no minimum on time issue.

INPUT CAPACITORS

The LTM4664A PSM channels should be connected to

a low AC impedance DC source. For the regulator input,

four 22µF input ceramic capacitors are used to handle

the RMS ripple current. A 47µF to 100µF surface mount

aluminum electrolytic bulk capacitor can be used for more

input bulk capacitance. This bulk input capacitor is only

needed if the input source impedance is compromised by

long inductive leads, traces or not enough source capaci-

tance. If low impedance power planes are used, then this

bulk capacitor is not needed.

increases by N times. A small value 10Ω resistor can be

+

placed in series from V

to the V

pin to allow for

OSNS0

a bode plot analyzer to^Oin^Uj^Teⁿct a signal into the control loop

and validate the regulator stability. The LTM4664A PSM

stability compensation can be adjusted using two external

capacitors, and the MFR_PWM_COMP commands.

For a buck converter, the switching duty-cycle can be

estimated as:

V_OUTn

D_n=

V

LIGHT LOAD CURRENT OPERATION

INn

Without considering the inductor current ripple, for each

output, the RMS current of the input capacitor can be

estimated as:

The LTM4664A PSM channels have two modes of oper-

ation including high efficiency, discontinuous conduction

mode or forced continuous conduction mode. The mode of

operation is configured by bit 0 of the MFR_PWM_MODEn

command (discontinuous conduction is always the start-up

mode, forced continuous is the default running mode).

I

I_CINn(RMS)

=

^OUTn(MAX)• D • 1−D

(

)

n

η%

In the above equation, η% is the estimated efficiency of the

power module. The bulk capacitor can be a switcher-rated

electrolytic aluminum capacitor, or a polymer capacitor.

If a channel is enabled for discontinuous mode operation,

the inductor current is not allowed to reverse. The reverse

Rev. 0

63

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

current comparator, I , turns off the bottom MOSFET

MFR_CONFIG_ALL[4] = 1b. This can be easily imple-

mented with resistor pin-strap settings on the FSWPH_

CFG pin (see Table 3). Using MFR_CONFIG_ALL[4] = 1b,

the LTM4664As SYNC pin becomes a high impedance

input, only—i.e., it does not drive SYNC low. The module

synchronizes its frequency to that of the clock applied to

its SYNC pin. The only shortcoming of this approach is:

in the absence of an externally applied clock, the switch-

ing frequency of the module will default to the low end of

its frequency-synchronization capture range (~225kHz).

REV

(MBn) just before the inductor current reaches zero, pre-

venting it from reversing and going negative. Thus, the

controller can operate in discontinuous (pulse-skipping)

operation. In forced continuous operation, the induc-

tor current is allowed to reverse at light loads or under

large transient conditions. The peak inductor current is

determined solely by the voltage on the COMP_Cna pin.

In this mode, the efficiency at light loads is lower than

in discontinuous mode operation. However, continuous

mode exhibits lower output ripple and less interference

with audio circuitry. Forced continuous conduction mode

may result in reverse inductor current, which can cause

the input supply to boost. The VIN_OV_FAULT_LIMIT

If fault-tolerance to the loss of an externally applied SYNC

clock is desired, the FREQUENCY_SWITCH command of

a “sync slave” can be left at the nominal target switching

frequency of the application, and not 0x0000 However,

it is then still necessary to configure MFR_CONFIG_

ALL[4] = 1b. With this combination of configurations,

the LTM4664A’s SYNC pin becomes a high impedance

input and the module synchronizes its frequency to

that of the externally applied clock, provided that the

frequency of the externally applied clock exceeds ~½.

of the target frequency (FREQUENCY_SWITCH). If the

SYNC clock is absent, the module responds by operating

at its target frequency, indefinitely. If and when the SYNC

clock is restored, the module automatically phase-locks

to the SYNC clock as normal. The only shortcoming of

this approach is: the EEPROM must be configured per

above guidance; resistor pin-strapping options on the

FSWPH_CFG pin alone cannot provide fault-tolerance to

the absence of the SYNC clock.

can detect this on V and turn off the offending chan-

IN3

nel. However, this fault is based on an ADC read and can

nominally take up to 100ms to detect. If there is a concern

about the input supply boosting, keep the part in discon-

tinuous conduction operation.

SWITCHING FREQUENCY AND PHASE

The switching frequency of the LTM4664A’s PSM chan-

nels is established by its analog phase-locked-loop (PLL)

locking on to the clock present at the module’s SYNC pin.

The clock waveform on the SYNC pin can be generated by

the LTM4664A’s PSM internal circuitry when an external

pull-up resistor to 3.3V (e.g., V_DD33) is provided, in combi-

nation with the LTM4664A PSM control IC’s FREQUENCY_

SWITCH command being set to one of the following sup-

ported values: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz,

650kHz, 750kHz. In this configuration, the module is called

a “sync master”: (using the factory-default setting of MFR_

CONFIG_ALL[4] = 0b), SYNC becomes a bidirectional

open-drain pin, and the LTM4664A PSM pulls SYNC logic

low for nominally 500ns at a time, at the prescribed clock

rate. The SYNC signal can be bused to other LTM4664A

PSM device modules (configured as “sync slaves”), for

purposes of synchronizing switching frequencies of mul-

tiple modules within a system—but only one LTM4664A

PSM devices should be configured as a “sync master”; the

other LTM4664A(s) should be configured as “sync slaves”.

2

The FREQUENCY_SWITCH register can be altered via I C

commands, but only when switching action is disengaged,

i.e., the module’s outputs are turned off. The FREQUENCY_

SWITCH command takes on the value stored in NVM at

V

power-up, but is overridden according to a resis-

INS3

tor pin-strap applied between the FSWPH_CFG pin and

SGND only if the module is configured to respect resistor

pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3

highlights available resistor pin-strap and corresponding

FREQUENCY_SWITCH settings.

The relative phasing of all active channels in a PolyPhase

rail should be optimally phased. The relative phasing of

each rail is 360°/n, where n is the number of phases in the

rail. MFR_PWM_CONFIG[2:0] configures channel relative

The most straightforward way is to set its

FREQUENCY_ SWITCH command to 0x0000 and

Rev. 0

64

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

phasing with respect to the SYNC pin. Phase relationship

values are indicated with 0° corresponding to the falling

edge of SYNC being coincident with the turn-on of the

top MOSFETs, MTn.

Table 9. Recommended PSM Switching Frequency for Various

V_IN-to-V_OUTStep-Down Scenarios

V

7.5V

10V

12V

14.5V

IN

0.5

0.7

0.8

0.9

1.0

1.2

1.5

The MFR_PWM_CONFIG command can be altered via

250kHz

350kHz

250kHz

350kHz

250kHz

350kHz

250kHz

350kHz

2

I C commands, but only when switching action is dis-

engaged, i.e., the module’s outputs are turned off. The

MFR_PWM_CONFIG command takes on the value stored

in NVM at SV power-up, but is overridden according

IN

to a resistor pin-strap applied between the FSWPH_CFG

pin and SGND only if the module is configured to respect

resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b).

Table 3 highlights available resistor pin-strap and corre-

sponding MFR_PWM_CONFIG[2:0] settings.

OUTPUT CURRENT LIMIT PROGRAMMING

The cycle-by-cycle current limit (= V /DCR) is pro-

ISENSE

portional to COMP_Cn, which can be programmed from

1.45V to 2.2V using the PMBus command IOUT_OC_

FAULT_LIMIT. The LTM4664A PSM uses only the sub-mil-

liohm sensing to detect current levels. See page103. The

LTM4664A PSM has two ranges of current limit program-

ming. The value of MFR_PWM_MODE[2] is reserved and

the MFR_PWM_MODE[7], and IOUT_OC_FAULT_LIMIT

are used to set the current limit level, see the section of

the PMBus commands, the device can regulate output

voltage with the peak current under the value of IOUT_OC_

FAULT_LIMIT in normal operation. In case of output cur-

rent exceeding that current limit, a OC fault will be issued.

Each of the IOUT_OC_FAULT_LIMIT ranges will effects the

loop gain, and subsequently effects the loop stability, so

setting the range of current limiting is a part of loop design.

Some combinations of FREQUENCY_SWITCH and

MFR_PWM_CONFIG[2:0] are not available by resistor

pin-strapping the FSWPH_CFG pin. All combinations of

supported values for FREQUENCY_SWITCH and MFR_

PWM_CONFIG[2:0] can be configured by NVM program-

2

ming—or, I C transactions, provided switching action is

disengaged, i.e., the module’s outputs are turned off.

Care must be taken to minimize capacitance on SYNC

to assure that the pull-up resistor versus the capacitor

load has a low enough time constant for the application

to form a “clean” clock. (See “Open-Drain Pins”, later in

this section.)

When an LTM4664A PSM is configured as a sync slave,

it is permissible for external circuitry to drive the SYNC

pin from a current-limited source (less than 10mA), rather

than using a pull-up resistor. Any external circuitry must

The LTpowerCAD Design Tool can be used to look at the loop

stability changes if current limit is adjusted. The LTM4664A

PSM will automatically update the current limit as the induc-

tor temperature changes. Keep in mind this operation is on

a cycle-by-cycle basis and is only a function of the peak

inductor current. The average inductor current is monitored

by the ADC converter and can provide a warning if too much

average output current is detected. The overcurrent fault is

detected when the COMP_Cn voltage hits the maximum

value. The digital processor within the LTM4664A PSM

provides the ability to either ignore the fault, shut down

and latch off or shut down and retry indefinitely (hiccup).

Refer to the overcurrent portion of the Dual 25A/30A PSM

Operation section for more detail. The READ_POUT can be

used to readback calculated output power.

not drive high with arbitrarily low impedance at SV pow-

IN

er-up, because the SYNC output can be low impedance

until NVM contents have been downloaded to RAM.

Recommended LTM4664A PSM switching frequencies of

operation for many common V_IN-to-V_OUTapplications are

indicated below. When the two channels of an LTM4664A

PSM are stepping input voltage(s) down to output volt-

ages whose recommended switching frequencies below

are significantly different, operation at the higher of the

two recommended switching frequencies is preferable,

but minimum on-time must be considered. (See Minimum

On-Time Considerations section.)

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LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

MINIMUM ON-TIME CONSIDERATIONS

10% in frequency, thus the actual time delays will have

some variance.

Minimum on-time, t , is the smallest time duration

ON(MIN)

that the LTM4664A PSM is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

Soft-start is performed by actively regulating the load

voltage while digitally ramping the target voltage from 0V

to the commanded voltage set point. The rise time of the

voltage ramp can be programmed using the TON_RISEn

command to minimize inrush currents associated with the

start-up voltage ramp. The soft-start feature is disabled by

setting TON_RISEn to any value less than 0.250ms. The

LTM4664A PSM performs the necessary math internally to

assure the voltage ramp is controlled to the desired slope.

However, the voltage slope can not be any faster than the

V_OUTn

_INn•f_OSC

t_ON(MIN)

<

V

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

V

fundamental limits of the power stage. The number

OUTn

of t_ON(MIN)< steps in the ramp is equal to TON_RISE/0.1ms.

Therefore, the shorter the TON_RISEn time setting, the

more discrete steps in the soft-start ramp appear.

The minimum on-time for the LTM4664A is 60ns.

The LTM4664A PSM PWM always operates in discon-

tinuous mode during the TON_RISEn operation. In dis-

continuous mode, the bottom MOSFET (MBn) is turned

off as soon as reverse current is detected in the inductor.

This allows the regulator to start up into a prebiased load.

VARIABLE DELAY TIME, SOFT-START AND OUTPUT

VOLTAGE RAMPING

The LTM4664A PSM must enter its run state prior to soft-

start. The RUN_Cn pins are released after the part initial-

izes, and V

is greater than the VIN_ON threshold and

INS3

There is no analog tracking feature in the LTM4664A PSM;

however, two outputs can be given the same TON_RISEn

and TON_DELAYn times to achieve ratiometric rail track-

ing. Because the RUNn pins are released at the same time

and both units use the same time base (SHARE_CLK), the

outputs track very closely. If the circuit is in a PolyPhase

configuration, all timing parameters must be the same.

Stage 2 PGood pin releases the RUN_Cn pins. If multiple

LTM4664As are used in an application, they should be

configured to share the same RUN_Cn pins. They all hold

their respective RUN_Cn pins low until all devices initialize

and V

exceeds the VIN_ON threshold for all devices.

INS3

The SHARE_CLK pin assures all the devices connected to

the signal use the same time base.

After the RUN_Cn pin releases, the controller waits for the

user-specified turn-on delay (TON_DELAYn) prior to ini-

tiating an output voltage ramp. Multiple LTM4664As and

other LTC parts can be configured to start with variable

delay times. To work correctly, all devices use the same

timing clock (SHARE_CLK) and all devices must share

the RUN_Cn pin.

DIGITAL SERVO MODE

For maximum accuracy in the regulated output voltage,

enable the digital servo loop by asserting bit 6 of the

MFR_PWM_MODE command. In digital servo mode, the

LTM4664A PSM will adjust the regulated output voltage

based on the ADC voltage reading. Every 90ms the dig-

ital servo loop will step the LSB of the DAC (nominally

1.375mV or 0.6875mV depending on the voltage range

bit) until the output is at the correct ADC reading. At pow-

er-up this mode engages after TON_MAX_FAULT_LIMIT

unless the limit is set to 0 (infinite). If the TON_MAX_

FAULT_LIMIT is set to 0 (infinite), the servo begins

This allows the relative delay of all parts to be synchro-

nized. The actual variation in the delay will be dependent

on the highest clock rate of the devices connected to the

SHARE_CLK pin (all Analog Devices ICs are configured

to allow the fastest SHARE_CLK signal to control the

timing of all devices). The SHARE_CLK signal can be

after TON_RISE is complete and V

has exceeded the

OUT

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LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

VOUT_UV_FAULT_LIMIT. This same point in time is

when the output changes from discontinuous to the pro-

grammed mode as indicated in MFR_PWM_MODE bit 0.

Refer to Figure 29 for details on the V_OUTwaveform under

time-based sequencing. If the TON_MAX_FAULT_LIMIT

is set to a value greater than 0 and the TON_MAX_FAULT_

RESPONSE is set to ignore 0x00, the servo begins:

SOFT OFF (SEQUENCED OFF)

In addition to a controlled start-up, the LTM4664A PSM

also supports controlled turn-off. The TOFF_DELAY and

TOFF_FALL functions are shown in Figure 30. TOFF_FALL

is processed when the RUN pin goes low or if the part is

commanded off. If the part faults off or FAULT_Cn is pulled

low externally and the part is programmed to respond to

this, the output will three-state rather than exhibiting a

controlled ramp. The output will decay as a function of the

load. The output voltage will operate as shown in Figure 30

as long as the part is in forced continuous mode and the

TOFF_FALL time is sufficiently slow that the power stage

can achieve the desired slope. The TOFF_FALL time can

only be met if the power stage and controller can sink

sufficient current to assure the output is at zero volts by

the end of the fall time interval. If the TOFF_FALL time is

set shorter than the time required to discharge the load

capacitance, the output will not reach the desired zero

volt state. At the end of TOFF_FALL, the controller will

1. After the TON_RISE sequence is complete

2. After the TON_MAX_FAULT_LIMIT time is reached;

and

3. After the VOUT_UV_FAULT_LIMIT has been exceeded

or the IOUT_OC_FAULT_LIMIT is no longer active.

If the TON_MAX_FAULT_LIMIT is set to a value greater

than 0 and the TON_MAX_FAULT_RESPONSE is not set

to ignore 0x00, the servo begins:

1. After the TON_RISE sequence is complete

2. After the TON_MAX_FAULT_LIMIT time has expired

and both VOUT_UV_FAULT and IOUT_OC_FAULT are

not present.

cease to sink current and V

will decay at the natural

OUT

rate determined by the load impedance. If the controller is

in discontinuous mode, the controller will not pull negative

current and the output will be pulled low by the load, not

the power stage. The maximum fall time is limited to 1.3

seconds. The shorter TOFF_FALL time is set, the larger

the discrete steps in the TOFF_FALL ramp will appear. The

number of steps in the ramp is equal to TOFF_FALL/0.1ms.

The maximum rise time is limited to 1.3 seconds.

In a PolyPhase configuration it is recommended only one

of the control loops have the digital servo mode enabled.

This will assure the various loops do not work against each

other due to slight differences in the reference circuits.

DIGITAL SERVO

MODE ENABLED

FINAL OUTPUT

VOLTAGE REACHED

TON_MAX_FAULT_LIMIT

TIME DELAY OF

200-400ms

DAC VOLTAGE

ERROR (NOT

TO SCALE)

V

OUT

V

OUT

4664A F30

TIME

4664A F29

TOFF_DELAY

TOFF_FALL

TIME

TON_RISE

TON_DELAY

Figure 29. Timing Controlled V_OUTRise

Figure 30. TOFF_DELAY and TOFF_FALL

Rev. 0

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LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

UNDERVOLTAGE LOCKOUT

pins can be pulled low by external sources indicating a fault

in some other portion of the system. The fault response is

configurable and allows the following options:

The LTM4664A PSM is initialized by an internal thresh-

old-based UVLO where V

must be approximately 4V

INS3

n

and INTV , V

, and V

must be within approxi-

Ignore

CC DD33

DD25

mately 20% of their regulated values. In addition, V

DD33

n

Shut Down Immediately—Latch Off

must be within approximately 7% of the targeted value

n

Shut Down Immediately—Retry Indefinitely at the Time

Interval Specified in MFR_RETRY_DELAY

before the RUN_Cn pin is released. After the part has

initialized, an additional comparator monitors V

. The

INS3

VIN_ON threshold must be exceeded before the power

Refer to the PMBus section of the data sheet and the

PMBus specification for more details.

sequencing can begin. When V drops below the VIN_

INS3

OFF threshold, the SHARE_CLK pin will be pulled low and

The OV response is automatic. If an OV condition is

detected, TGn goes low and BGn is asserted.

V

must increase above the VIN_ON threshold before

INS3

the controller will restart. The normal start-up sequence

will be allowed after the VIN_ON threshold is crossed. If

Fault logging is available on the LTM4664A PSM. The fault

logging is configurable to automatically store data when

a fault occurs that causes the unit to fault off. The header

portion of the fault logging table contains peak values. It

is possible to read these values at any time. This data will

be useful while troubleshooting the fault.

FAULTB is held low when V

is applied, ALERT will be

INS3

asserted low even if the part is programmed to not assert

2

ALERT when FAULTB is held low. If I C communication

occurs before the LTM4664A is out of reset and only a

portion of the command is seen by the part, this can be

interpreted as a CML fault. If a CML fault is detected,

ALERT is asserted low.

If the LTM4664A PSM internal temperature is in excess

of 85°C, writes into the NVM (other than fault logging)

are not recommended. The data will still be held in RAM,

unless the 3.3V supply UVLO threshold is reached. If the

die temperature exceeds 130°C all NVM communication

is disabled until the die temperature drops below 120°C.

It is possible to program the contents of the NVM in

the application if the V_DD33supply is externally driven

directly to V

or through EXTV . This will activate the

DD33

digital portion of the LTM4664A ^CP^CSM without engaging

the high voltage sections. PMBus communications are

valid in this supply configuration. If V

has not been

INS3

OPEN-DRAIN PINS

applied to the LTM4664A PSM, bit 3 (NVM Not Initialized)

in MFR_COMMON will be asserted low. If this condition is

detected, the part will only respond to addresses 5A and

5B. To initialize the part issue the following set of com-

mands: global address 0x5B command 0xBD data 0x2B

followed by global address 5B command 0xBD and data

0xC4. The part will now respond to the correct address.

Configure the part as desired then issue a STORE_USER_

The LTM4664A PSM has the following open-drain pins:

3.3V Pins

1. FAULT_Cn

2. SYNC

3. SHARE_CLK

ALL. When V is applied a MFR_RESET command must

4. PGOOD_Cn

IN

be issued to allow the PWM to be enabled and valid ADC

conversions to be read.

5V Pins (5V pins operate correctly when pulled to 3.3V.)

1. RUN_Cn

2. ALERT

3. SCL

FAULT DETECTION AND HANDLING

The LTM4664A FAULT_Cn pins are configurable to indicate

a variety of faults including OV, UV, OC, OT, timing faults,

and peak over current faults. In addition, the FAULT_Cn

4. SDA

Rev. 0

68

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LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

All the above pins have on-chip pull-down transistors that

can sink 3mA at 0.4V. The low threshold on the pins is

0.8V; thus, there is plenty of margin on the digital signals

with 3mA of current. For 3.3V pins, 3mA of current is

a 1.1k resistor. Unless there are transient speed issues

associated with the RC time constant of the resistor

pull-up and parasitic capacitance to ground, a 10k resis-

tor or larger is generally recommended.

PHASE-LOCKED LOOP AND FREQUENCY

SYNCHRONIZATION

The LTM4664A PSM has a phase-locked loop (PLL) com-

prised of an internal voltage-controlled oscillator (VCO)

and a phase detector. The PLL is locked to the falling edge

of the SYNC pin. The phase relationship between the PWM

controller and the falling edge of SYNC is controlled by

the lower 3 bits of the MFR_PWM_ CONFIG command.

For PolyPhase applications, it is recommended that all

the phases be spaced evenly. Thus for a 2-phase system

the signals should be 180° out of phase and a 4-phase

system should be spaced 90°.

For high speed signals such as the SDA, SCL and SYNC,

a lower value resistor may be required. The RC time con-

stant should be set to 1/3 to 1/5 the required rise time

to avoid timing issues. For a 100pF load and a 400kHz

PMBus communication rate, the rise time must be less

than 300ns. The resistor pull-up on the SDA and SCL pins

with the time constant set to 1/3 the rise time is:

The phase detector is an edge-sensitive digital type that

provides a known phase shift between the external and

internal oscillators. This type of phase detector does not

exhibit false lock to harmonics of the external clock.

t_RISE

3•100pF

R_PULLUP

=

=1k

The output of the phase detector is a pair of complemen-

tary current sources that charge or discharge the internal

filter network. The PLL lock range is guaranteed between

200kHz and 1MHz. Nominal parts will have a range beyond

this; however, operation to a wider frequency range is not

guaranteed.

The closest 1% resistor value is 1k. Be careful to minimize

parasitic capacitance on the SDA and SCL pins to avoid

communication problems. To estimate the loading capac-

itance, monitor the signal in question and measure how

long it takes for the desired signal to reach approximately

63% of the output value. This is a one time constant. The

SYNC pin has an on-chip pull-down transistor with the

output held low for nominally 500ns. If the internal oscil-

lator is set for 500kHz and the load is 100pF and a 3x time

constant is required, the resistor calculation is as follows:

The PLL has a lock detection circuit. If the PLL should

lose lock during operation, bit 4 of the STATUS_MFR_

SPECIFIC command is asserted and the ALERT pin is

pulled low. The fault can be cleared by writing a 1 to the

bit. If the user does not wish to see the ALERT pin assert

if a PLL_FAULT occurs, the SMBALERT_MASK command

can be used to prevent the alert.

2µs–500ns

3•100pF

R_PULLUP

=

=5k

If the SYNC signal is not clocking in the application, the

nominal programmed frequency will control the PWM

circuitry. However, if multiple parts share the SYNC pins

and the signal is not clocking, the parts will not be syn-

chronized and excess voltage ripple on the output may be

present. Bit 10 of MFR_PADS will be asserted low if this

condition exists.

The closest 1% resistor is 4.99k.

If timing errors are occurring or if the SYNC frequency is

not as fast as desired, monitor the waveform and deter-

mine if the RC time constant is too long for the applica-

tion. If possible reduce the parasitic capacitance. If not,

reduce the pull-up resistor sufficiently to assure proper

timing. The SHARE_CLK pull-up resistor has a similar

equation with a period of 10µs and a pull-down time of

1µs. The RC time constant should be approximately 3µs

or faster.

If the PWM signal appears to be running at too high a

frequency, monitor the SYNC pin. Extra transitions on

the falling edge will result in the PLL trying to lock on to

noise versus the intended signal. Review routing of digital

control signals and minimize crosstalk to the SYNC signal

Rev. 0

69

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LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

to avoid this problem. Multiple LTM4664As PSM sections

are required to share one SYNC pin in PolyPhase config-

urations. For other configurations, connecting the SYNC

pins to form a single SYNC signal is optional. If the SYNC

pin is shared between LTM4664As PSM sections, only

one LTM4664A section can be programmed with a fre-

quency output. All the other LTM4664As sections should

be programmed to disable the SYNC output. However

their frequency should be programmed to the nominal

desired value. See application schematic in Figure 51.

PROGRAMMABLE LOOP COMPENSATION

The LTM4664A offers programmable loop compensation

to optimize the transient response without any hardware

Ω

change. The error amplifier gain g varies from 1.0m

m

Ω

to 5.73m , and the compensation resistor R

varies

COMP

from 0kΩ to 62kΩ inside the controller. Two compensa-

tion capacitors, COMP_na and COMP_nb, are required in

the design and the typical ratio between COMP_na and

COMP_nb is 10. Also see Figure 2 Block Diagram, and

Figure 31.

By adjusting the g_mand R_COMPonly, the LTM4664A PSM

can provide a flexible Type II compensation network to

optimize the loop over a wide range of output capacitors.

Adjusting the g_mwill change the gain of the compensation

over the whole frequency range without moving the pole

and zero location, as shown in Figure 32.

INPUT CURRENT SENSE AMPLIFIER

The LTM4664A input current sense amplifier can sense

the supply current into the V

_

power stages pins

INS3 Cn

using an external sense resistor as shown in the Figure 2

Block Diagram. The R value can be programmed

SENSE

using the MFR_IIN_CAL_GAIN command. Kelvin sensing

is recommended across the R resistor to eliminate

Adjusting the R

will change the pole and zero loca-

COMP

SENSE

tion, as shown in Figure 33. It is recommended that the

user determines the appropriate value for the g_mand

errors. The MFR_PWM_CONFIG [6:5] sets the input cur-

rent sense amplifier gain. See the MFR_PWM_CONFIG

section. The IIN_OC_WARN_LIMIT command sets the

value of the input current measured by the ADC, in

amperes, that causes a warning indicating the input cur-

rent is high. The READ_IIN value will be used to determine

if this limit has been exceeded. The READ_IIN command

returns the input current, in Amperes, as measured across

the input current sense resistor.

R

COMP

using the LTpowerCAD tool.

V

+

–

REF

g

m

FB

R

COMP

4664A F31

There is an IR voltage drop from the supply to the V

COMP_na

COMP_nb

INS3

controller pin due to the current flowing into the V_INS3con-

troller pin. To compensate for this voltage drop, the MFR_

RVIN will be automatically set to the 1Ω internal sense

resistor in the Figure 2 Block Diagram. The LTM4664A

PSM will multiply the MFR_READ_ICHIP measurement

value by this 1Ω resistor and add this voltage to the

Figure 31. Programmable Loop Compensation

TYPE II COMPENSATION

GAIN

measured voltage at the V

controller pin. Therefore,

INS3

READ_VIN = VIN_CNTLPIN + (MFR_READ_ICHIP • 1Ω)

The MFR_READ_ICHIP command is used to measure the

internal controller current. Using the READ_PIN com-

mand allows for reading calculated input power.

INCREASE g

m

FREQUENCY

4664A F32

Figure 32. Error Amp g_mAdjust

Rev. 0

70

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LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

TYPE II COMPENSATION

The COMP_Cnaseries internal R_COMPand external C_{COMP_Cna}

GAIN

filter sets the dominant pole-zero loop compensation. The

internal R

value can be modified (from 0Ω to 62kΩ)

COMP

using bits[4:0] of the MFR_PWM_ COMP command.

Adjust the value of R to optimize transient response once

the final PCB layout is done and the particular C

COMP

filter

COMP_bn

capacitor and output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1µs to 10µs will

produce output voltage and COMP pin waveforms that will

give a sense of the overall loop stability without break-

ing the feedback loop. Placing a power MOSFET with a

resistor to ground directly across the output capacitor and

driving the gate with an appropriate signal generator is

a practical way to produce to a load step. The MOSFET

+ R_SERIESwill produce output currents approximately

INCREASE R

COMP

FREQUENCY

4664A F33

Figure 33. R_COMPAdjust

CHECKING TRANSIENT RESPONSE

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V

shifts by an

OUT

equal to V /R

. R

values from 0.1Ω to 2Ω

OUT SERIES SERIES

amount equal to ΔI

, where ESR is the effective

LOAD(ESR)

are valid depending on the current limit settings and the

programmed output voltage. The initial output voltage step

resulting from the step change in output current may not

be within the bandwidth of the feedback loop, so this signal

cannot be used to determine phase margin. This is why

it is better to look at the COMP pin signal which is in the

feedback loop and is the filtered and compensated control

loop response. The gain of the loop will be increased by

series resistance of C . ΔI

also begins to charge or

generating the feedback error signal that

OUT

LOAD

discharge C

OUT

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recov-

OUT

ery time V

can be monitored for excessive overshoot

OUT

or ringing, which would indicate a stability problem. The

availability of the COMP pin not only allows optimization

of control loop behavior but also provides a DC-coupled

and AC-filtered closed-loop response test point. The DC

step, rise time and settling at this test point truly reflects

the closed-loop response. Assuming a predominantly

second order system, phase margin and/or damping fac-

tor can be estimated using the percentage of overshoot

seen at this pin. The bandwidth can also be estimated by

examining the rise time at the pin. The COMP_Cna exter-

nal capacitor shown in the Typical Application circuit will

provide an adequate starting point for most applications.

The programmable parameters that affect loop gain are

the voltage range, bit[1] of the MFR_PWM_CONFIG com-

mand, the current range bit[7] of the MFR_PWM_MODE

increasing R

by the same factor that C ^COMP_Cna

and the bandwidth of the loop will be

COMP

increased by decreasing C

. If R

is increased

COMP

is decreased, the zero fre-

COMP

quency will be kept the same, thereby keeping the phase

shift the same in the most critical frequency range of the

feedback loop. The gain of the loop will be proportional to

the transconductance of the error amplifier which is set

using bits[7:5] of the MFR_PWM_COMP command. The

output voltage settling behavior is related to the stability

of the closed-loop system and will demonstrate the actual

overall supply performance. A second, more severe tran-

sient is caused by switching in loads with large (>1µF)

supply bypass capacitors. The discharged bypass capac-

itors are effectively put in parallel with C_OUT, causing a

command, the g of the PWM channel amplifier bits [7:5]

m

of MFR_PWM_COMP, and the internal R

compensa-

COMP

rapid drop in V . No regulator can alter its delivery of

OUT

tion resistor, bits[4:0] of MFR_PWM_COMP. Be sure to

establish these settings prior to compensation calculation.

current quickly enough to prevent this sudden step change

in output voltage if the load switch resistance is low and

Rev. 0

71

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LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

2

it is driven quickly. If the ratio of C

than 1:50, the switch rise time should be controlled so that

the load rise time is limited to approximately 25 • C

Thus a 10µF capacitor would require a 250µs rise time,

limiting the charging current to about 200mA.

to C

is greater

CONNECTING THE USB TO I C/SMBUS/PMBUS

LOAD

OUT

CONTROLLER TO THE LTM4664A IN-SYSTEM

.

The LTC USB-to-I²C/SMBus/PMBus adapter (DC1613A

or equivalent) can be interfaced to the LTM4664A PSM

on the user’s board for programming, telemetry and sys-

tem debug. The adapter, when used in conjunction with

LTpowerPlay, provides a powerful way to debug an entire

power system. Faults are quickly diagnosed using telem-

etry, fault status commands and the fault log. The final

configuration can be quickly developed and stored to the

LTM4664A PSM EEPROM. Figure 34 illustrates the appli-

cation schematic for powering, programming and com-

munication with one or more LTM4664As PSM via the

LOAD

PolyPhase^®Configuration

When configuring a PolyPhase rail with multiple

LTM4664As, the user must share the SYNC, COMP_na,

COMP_nb SHARE_CLK, FAULT_Cn, and ALERT pins of

these parts. Be sure to use pull-up resistors on FAULT_

Cn, SHARE_CLK and ALERT. One of the part’s SYNC pins

must be set to the desired switching frequency, and all

other FREQUENCY_SWITCH commands must be set to

External Clock. If an external oscillator is provided, set

the FREQUENCY_SWITCH command to External Clock for

all parts. The relative phasing of all the channels should

be spaced equally. The MFR_RAIL_ ADDRESS of all the

devices should be set to the same value.

2

LTC I C/SMBus/PMBus adapter regardless of whether or

not system power is present. If system power is not pres-

ent, the dongle will power the LTM4664A PSM through

the V

supply pin. To initialize the part when V is not

DD33

applied and the V

IN

pin is powered, use global address

DD33

0x5B command 0xBD data 0x2B followed by address 0x5B

command 0xBD data 0xC4.The LTM4664A PSM can now

communicate with, and the project file Figure 34. Controller

Connection can be updated. To write the updated project file

to the NVM issue a STORE_USER _ALL command. When

+

Multiple channels need to tie all the V

pins together,

OSNS

–

and all the V

pins together COMP_na and COMP_

nb pins toge^Oth^Se^Nr^Sas well. Do not assert bit[4] of MFR_

CONFIG_ALL except in a PolyPhase application. See

application example Figure 50.

V is applied, a MFR_RESET must be issued to allow the

IN

PWM POWER to be enabled and valid ADCs to be read.

V

IN

LTC

CONTROLLER

HEADER

100k

V

IN

ISOLATED

3.3V

SDA

SCL

V

DD33

DD25

TP0101K

1µF

LTM4664A PSM

10k

SDA

SCL

WP PGND/SGND

TO LTC DC1613

2

USB TO I C/SMBus/PMBus

CONTROLLER

V

IN

V

DD33

DD25

TP0101K

1µF

LTM4664A PSM

SDA

SCL

VGS MAX ON THE TP0101K IS 8V IF V > 16V

IN

WP PGND/SGND

CHANGE THE RESISTOR DIVIDER ON THE PFET GATE

4664A F34

Figure 34. Controller Connection

Rev. 0

72

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

Because of the adapter’s limited current sourcing capa-

programming board, or a customer target system. The

software also provides an automatic update feature to

keep the revisions current with the latest set of device

drivers and documentation.

bility, only the LTM4664As, PSM their associated pull-up

2

resistors and the I C pull-up resistors should be powered

from the ORed 3.3V supply. In addition any device sharing

2

the I C bus connections with the LTM4664A PSM should

A great deal of context sensitive help is available with

LTpowerPlay along with several tutorial demos. Complete

information is available at:

not have body diodes between the SDA/SCL pins and their

respective V node because this will interfere with bus

DD

communication in the absence of system power. If V

INS3

LTpowerPlay

is applied, the DC1613A will not supply the power to the

LTM4664As PSM on the board. It is recommended the

RUN_Cn pins be held low or no voltage configuration

resistors inserted to avoid providing power to the load

until the part is fully configured.

PMBus COMMUNICATION AND COMMAND

PROCESSING

The LTM4664A PSM has a one deep buffer to hold the

last data written for each supported command prior to

processing as shown in Figure 36, Write Command Data

Processing. When the part receives a new command from

the bus, it copies the data into the Write Command Data

Buffer, indicates to the internal processor that this com-

mand data needs to be fetched, and converts the com-

mand to its internal format so that it can be executed.

Two distinct parallel blocks manage command buffering

and command processing (fetch, convert, and execute) to

ensure the last data written to any command is never lost.

Command data buffering handles incoming PMBus writes

by storing the command data to the Write Command Data

Buffer and marking these commands for future process-

ing. The internal processor runs in parallel and handles

the sometimes slower task of fetching, converting and

executing commands marked for processing. Some com-

putationally intensive commands (e.g., timing parame-

ters, temperatures, voltages and currents) have internal

processor execution times that may be long relative to

PMBus timing. If the part is busy processing a command,

and new command(s) arrive, execution may be delayed or

processed in a different order than received. The part indi-

cates when internal calculations are in process via bit 5 of

MFR_COMMON (“calculations not pending”). When the

part is busy calculating, bit 5 is cleared. When this bit is

set, the part is ready for another command. An example

polling loop is provided in Figure 37 which ensures that

commands are processed in order while simplifying error

handling routines.

The LTM4664A PSM is fully isolated from the host PC’s

ground by the DC1613A.The 3.3V from the adapter

and the LTM4664A V_DD33pin must be driven to each

LTM4664A with a separate PFET. If both V

and EXTV

INS3

CC

are not applied, the V

pins can be in parallel because

DD33

the on-chip LDO is off. The controller 3.3V current limit

is 100mA but typical V

currents are under 15mA. The

V

does back drive^Dt^Dh³e³INTV /EXTV pin. Normally

DD33

CC

this is not an issue if V is open.

IN

LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL

POWER

LTpowerPlay (Figure 35) is a powerful Windows-based

development environment that supports Analog Devices

digital power system management ICs including the

LTM4664A PSM section. The software supports a variety

of different tasks. LTpowerPlay can be used to evaluate

Analog Devices ICs by connecting to a demo board or

the user application. LTpowerPlay can also be used in

an off-line mode (with no hardware present) in order to

build multiple IC configuration files that can be saved and

reloaded at a later time. LTpowerPlay provides unprec-

edented diagnostic and debug features. It becomes a

valuable diagnostic tool during board bring-up to pro-

gram or tweak the power system or to diagnose power

issues when bring up rails. LTpowerPlay utilizes Analog

2

Devices’ USB-to-I C/SMBus/PMBus adapter to commu-

nication with one of the many potential targets includ-

ing the DC2165A demo board, the DC2298A socketed

Rev. 0

73

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

Figure 35. LTpowerPlay Screen Shot

CMD

WRITE COMMAND

DATA BUFFER

PMBus

WRITE

DECODER

INTERNAL

PAGE

•

0x00

0x21

PROCESSOR

CMDS

FETCH,

CONVERT

DATA

AND

EXECUTE

DATA

MUX

VOUT_COMMAND

•

MFR_RESET

x1

0xFD

S

R

CALCULATIONS

PENDING

4664A F36

Figure 36. Write Command Data Processing

Rev. 0

74

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

When the part receives a new command while it is busy,

it will communicate this condition using standard PMBus

protocol. Depending on part configuration it may either

NACK the command or return all ones (0xFF) for reads.

It may also generate a BUSY fault and ALERT notifica-

tion, or stretch the SCL clock low. For more information

refer to PMBus Specification v1.1, Part II, Section 10.8.7

and SMBus v2.0 section 4.3.3. Clock stretching can be

enabled by asserting bit 1 of MFR_CONFIG_ ALL. Clock

stretching will only occur if enabled and the bus commu-

nication speed exceeds 100kHz.

It is recommended that all command writes (write byte,

write word, etc.) be preceded with a polling loop to avoid

the extra complexity of dealing with busy behavior and

unwanted ALERT notification. A simple way to achieve this

is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_

WORD() subroutine. The above polling mechanism allows

your software to remain clean and simple while robustly

communicating with the part. For a detailed discussion

of these topics and other special cases please refer to the

Analog Devices Application Notes.

When communicating using bus speeds at or below

100kHz, the polling mechanism shown here provides a

simple solution that ensures robust communication with-

out clock stretching. At bus speeds in excess of 100kHz,

it is strongly recommended that the part be configured to

enable clock stretching. This requires a PMBus master that

supports clock stretching. System software that detects

and properly recovers from the standard PMBus NACK/

BUSY faults as described in the PMBus Specification v1.1,

Par II, Section 10.8.7 is required to communicate The

LTM4664A PSM is not recommended in applications with

bus speeds in excess of 400kHz.

// wait until chip is not busy

do

{

mfrCommonValue = PMBUS_READ_BYTE(0xEF);

partReady = (mfrCommonValue & 0x68) == 0x68;

}while(!partReady)

// now the part is ready to receive the next

command

PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_

COMMAND to 2V

Figure 37. Example of a Command Write of VOUT_COMMAND

PMBus busy protocols are well accepted standards, but

can make writing system level software somewhat com-

plex. The part provides three ‘hand shaking’ status bits

which reduce complexity while enabling robust system

level communication.

THERMAL CONSIDERATIONS AND

OUTPUT CURRENT DERATING

The thermal resistances reported in the Pin Configuration

section of this data sheet are consistent with those

parameters defined by JESD51-12 and are intended for

use with finite element analysis (FEA) software model-

ing tools that leverage the outcome of thermal modeling,

simulation, and correlation to hardware evaluation per-

formed on a µModule package mounted to a hardware

test board defined by JESD51-9 (“Test Boards for Area

Array Surface Mount Package Thermal Measurements”).

The motivation for providing these thermal coefficients is

found in JESD51-12 (“Guidelines for Reporting and Using

Electronic Package Thermal Information”).

The three hand shaking status bits are in the MFR_

COMMON register. When the part is busy executing an

internal operation, it will clear bit 6 of MFR_COMMON

(‘chip not busy’). When the part is busy specifically

because it is in a transitional V

state (margining hi/lo,

OUT

power off/on, moving to a new output voltage set point,

etc.) it will clear bit 4 of MFR_COMMON (‘output not in

transition’). When internal calculations are in process, the

part will clear bit 5 of MFR_COMMON (‘calculations not

pending’). These three status bits can be polled with a

PMBus read byte of the MFR_COMMON register until all

three bits are set. A command immediately following the

status bits being set will be accepted without NACKing or

generating a BUSY fault/ALERT notification. The part can

NACK commands for other reasons, however, as required

by the PMBus spec (for instance, an invalid command or

data). An example of a robust command write algorithm

for the VOUT_COMMAND register is provided in Figure 33.

Many designers may opt to use laboratory equipment

and a test vehicle such as the demo board to predict the

µModule regulator’s thermal performance in their appli-

cation at various electrical and environmental operating

conditions to compliment any FEA activities. Without

FEA software, the thermal resistances reported in the

Rev. 0

75

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

Pin Configuration section are in-and-of themselves not

relevant to providing guidance of thermal performance;

instead, the derating curves provided later in this data

sheet can be used in a manner that yields insight and

guidance pertaining to one’s application-usage, and can

be adapted to correlate thermal performance to one’s own

application.

3. θ

, the thermal resistance from junction to top of

JCtop

the product case, is determined with nearly all of the

component power dissipation flowing through the top

of the package. As the electrical connections of the typ-

ical µModule regulator are on the bottom of the pack-

age, it is rare for an application to operate such that

most of the heat flows from the junction to the top of

the part. As in the case of θ

useful for comparing packages but the test conditions

don’t generally match the user’s application.

, this value may be

JCbottom

The Pin Configuration section gives four thermal coeffi-

cients explicitly defined in JESD51-12; these coefficients

are quoted or paraphrased below:

4. θ , the thermal resistance from junction to the printed

JB

1. θ , the thermal resistance from junction to ambient,

JA

circuit board, is the junction-to-board thermal resis-

tance where almost all of the heat flows through the

bottom of the µModule regulator and into the board,

is the natural convection junction-to-ambient air ther-

mal resistance measured in a one cubic foot sealed

enclosure. This environment is sometimes referred to

as “still air” although natural convection causes the

air to move. This value is determined with the part

mounted to a JESD51-9 defined test board, which does

not reflect an actual application or viable operating

condition.

and is really the sum of the θ

and the thermal

JCbottom

resistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured a specified distance from the

package, using a two sided, two layer board. This board

is described in JESD51-9.

2. θ

, the thermal resistance from junction to the

JCbottom

A graphical representation of the aforementioned thermal

resistances is given in Figure 38; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package.

bottom of the product case, is determined with all of

the component power dissipation flowing through the

bottom of the package. In the typical µModule regulator,

the bulk of the heat flows out the bottom of the pack-

age, but there is always heat flow out into the ambient

environment. As a result, this thermal resistance value

may be useful for comparing packages but the test

conditions don’t generally match the user’s application.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

µModule DEVICE

θ

JA

JUNCTION-TO-AMBIENT RESISTANCE

θ

JUNCTION-TO-CASE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JCTOP

(TOP) RESISTANCE

θ

JB

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

AMBIENT

θ

JUNCTION-TO-CASE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JCBOTTOM

(BOTTOM) RESISTANCE

4664A F38

Figure 38. Graphical Representation of JESD51-12 Thermal Coefficients

Rev. 0

76

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

Configuration section replicates or conveys normal oper-

ating conditions of a µModule regulator. For example, in

normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through the

bottom of the µModule package—as the standard defines

The 1.0V and 1.5V power loss curves in Figure 39 and

40 respectively can be used in coordination with the load

current derating curves in Figure 41 to 44 for calculating

an approximate θ_JAthermal resistance for the LTM4664A

with various heat sinking and airflow conditions. These

thermal resistances represent demonstrated performance

of the LTM4664A on hardware; a 8-layer FR4 PCB mea-

suring 99mm × 145mm × 1.6mm using 2oz copper on

all layers. The power loss curves are taken at room tem-

perature, and are increased with multiplicative factors of

1.35 when the junction temperature reaches 125°C. The

derating curves are plotted with the LTM4664A’s paral-

leled outputs initially sourcing up to 50A and the ambient

temperature at 50°C. The output voltages are 1.0V and

1.5V. These are chosen to include the lower and higher

output voltage ranges for correlating the thermal resis-

tance. Thermal models are derived from several tempera-

ture measurements in a controlled temperature chamber

along with thermal modeling analysis. The junction tem-

peratures are monitored while ambient temperature is

increased with and without airflow.

for θ

and θ

, respectively. In practice, power

JCtop

JCbottom

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4664A, be aware there are multiple

power devices and components dissipating power, with

a consequence that the thermal resistances relative to

different junctions of components or die are not exactly

linear with respect to total package power loss. To rec-

oncile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the LTM4664A and the specified PCB with

all of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-9 and JESD51-12 to predict power loss heat

flow and temperature readings at different interfaces

that enable the calculation of the JEDEC-defined thermal

resistance values; (3) the model and FEA software is used

to evaluate the LTM4664A with heat sink and airflow; (4)

having solved for and analyzed these thermal resistance

values and simulated various operating conditions in the

software model, a thorough laboratory evaluation repli-

cates the simulated conditions with thermocouples within

a controlled environment chamber while operating the

device at the same power loss as that which was sim-

ulated. The outcome of this process and due diligence

yields the set of derating curves provided in later sections

of this data sheet, along with well-correlated JESD51-12-

defined θ values provided in the Pin Configuration section

of this data sheet.

The power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at 125°C maximum while lowering output cur-

rent or power while increasing ambient temperature. The

decreased output current decreases the internal module

loss as ambient temperature is increased. The monitored

junction temperature of 120°C minus the ambient operat-

ing temperature specifies how much module temperature

rise can be allowed. As an example in Figure 41, the load

current is derated to ~30A at ~97°C ambient with no air

or heat sink and the room temperature (25°C) power loss

for this 48V to 1.0V

at 30A

condition is ~3.2W. A

OUT

4.32W loss^Ii^Ns calculated by mu^Olt^Uip^Tlying the ~3.2W room

temperature loss from the 48V to 1.0V

power loss

IN

OUT

curve at 30A (Figure 41), with the 1.35 multiplying fac-

tor. If the 97°C ambient temperature is subtracted from

the 120°C junction temperature, then the difference of

23°C divided by 4.32W yields a thermal resistance, θ ,

JA

of 5.3°C/W—in good agreement with Table 11. Table 10

and 11 provide equivalent thermal resistances for 1.0V

and 1.5V outputs with and without airflow. The derived

Rev. 0

77

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

thermal resistances in Table 10 and Table 11 are for the

various conditions can be multiplied by the calculated

power loss as a function of ambient temperature to

derive temperature rise above ambient, thus maximum

junction temperature. Room temperature power loss

can be derived from the efficiency curves in the Typical

Performance Characteristics section and adjusted with the

above ambient temperature multiplicative factors.

Thermal performance expectations at up to 60A output (at

up to 1.2V ) can be suitably approximated by studying

OUT

this section's figures at analogous nearby output power

conditions. For example: 1.2V

at 60A is 72W output.

OUT

For thermal purposes, this operating point can be approx-

imated by 1.5V_OUTat 48A output (observe: also 72W out-

put). The 1.5V

curves shown in this section can thus

OUT

be utilized to infer thermal performance at currents higher

than 25A, per channel (for output voltages up to 1.2V ).

OUT

TABLE 10 AND TABLE 11: OUTPUT CURRENT DERATING (BASED ON DEMO BOARD)

Table 10. 1.0V Output

DERATING CURVE

Figure 41, 42

V

(V)

POWER LOSS CURVE

Figure 39, 40

AIRFLOW (LFM)

HEAT SINK

None

θ

(°C/W)

5.3

IN

JA

48, 54

0

Figure 39, 40

200

400

None

4.5

Figure 39, 40

None

4.0

Table 11. 1.5V Output

DERATING CURVE

Figure 43, 44

V

(V)

POWER LOSS CURVE

Figure 39, 40

AIRFLOW (LFM)

HEAT SINK

None

θ

(°C/W)

5.3

IN

JA

48, 54

0

Figure 43, 44

Figure 39, 40

200

400

None

4.5

Figure 43, 44

Figure 39, 40

None

4.0

Rev. 0

78

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

Table 12. LTM4664A Dual 25A/30A PSM Output Capacitor Matrix

All Below Parameters are Typical and Are Dependent on Board Layout

Murata

220μF 6.3V

GRM32ER60J227ME05

AMK325ABJ227MMHT

GRM32ER60J107M

PANASONIC SP-CAP

PANASONIC POSCAP

470μF 2.5V

1000μF 2.5V

EEFSX0E471E4

ETPF470M5H

Taiyo Yuden

Murata

220μf 4V

100μF 6.3V

100μF 4V

Murata

GRM21BR60G107ME15

AMK325AD7MMHP

ETCF1000M5H

Taiyo Yuden

Single 25A/30A Output

Programmed Values

PEAK-

TO-PEAK

RECOVERY

C

V

OUT

TIME(µs)

LOAD

OUT1

OUT2

V

(CERAMIC) (BULK) COMPna COMPnb EA-GM

R

I

LOW-

V

INS3

DROOP DEVIATION LTpowerCAD/ STEP FREQ.

OUT

COMP

LIM

INS1

(V)

0.9

1

(μF)

(pF)

100

220

100

220

100

220

(ms)

3.69

3.02

3.69

3.02

3.69

1.68

3.02

1.68

3.02

(kΩ) HI-RANGE RANGE (V)

C1, C2

(mV)

MEASURE (A/µs) (kHz)

5 × 100

2 × 470 2200

5

4

5

4

3

4

5

6

5

6

Yes

48 (V

) or 12V 42.5

) or 12V 55.5

85

36

40

50

36

40

50

27

20

33

30

27

12.5 250

12.5 350

INS1/4

5 × 100 1 × 1000 3300

111

150

85

6 × 220

5 × 100

None

4700

) or 12V

75

2 × 470 2200

) or 12V 42.5

1

5 × 100 1 × 1000 3300

) or 12V

56

75

112

150

135

120

170

136

230

140

1

6 × 220

3 × 100

3 × 220

1 × 100

3 × 220

1 × 100

None

4700

1.2

1.5

1 × 470 2200

) or 12V 67.5

) or 12V

60

85

68

None

1 × 470 2200

None 2200

1 × 470 2200

2200

) or 12V 115

) or 12V 70

Rev. 0

79

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

Table 13. LTM4664A Dual 25A/30A PSM Output Capacitor Matrix. All Below Parameters Are Typical and Are Dependent on Board Layout

Murata

220µF 6.3V

220µF 4V

100µF 6.3V

100µF 4V

GRM32ER60J227ME05

AMK325ABJ227MMHT

GRM32ER60J107M

PANASONIC SP-CAP

PANASONIC POSCAP

470µF 2.5V EEFSX0E471E4

470µF 2.5V ETPF470M5H

1000µF 2.5V ETPF1000M5H

1000µF 2.5V ETCF1000M5H

Taiyo Yuden

Murata

GRM21BR60G107ME15

AMK325AD7MMHP

Taiyo Yuden

Dual Phase Single 50A/60A Output

PEAK-

RECOVERY

TIME(µs)

C

V

OUT

TO-PEAK

LOAD

OUT1

OUT2

V

OUT

(CERAMIC) (BULK) COMPna COMPnb EA-GM

R

I

LOW-

V

INS3

DROOP DEVIATION LTpowerCAD/ STEP FREQ.

COMP

LIM

INS1

(V)

0.9

1

(μF)

4 × 470

None

(pF)

220

100

220

(ms)

3.69

3.02

3.69

3.02

(kΩ) HI-RANGE RANGE (V)

C1, C2

(mV)

47.5

35

(mV)

62/95

64

MEASURE (A/µs) (kHz)

Yes

(V

) or 12V

8

4

6

4

×

100

3300

5600

3300

7500

3300

7500

8

No

48

30

35

25

30

25

250

350

INS1/4

) or 12V

100

330

100

220

100

220

1.2

1.5

5

2 × 470

None

6

70

100/140

126/-

260

5

63

None

2.5

3

130

100

70

None

200

2 × 470

None

6

140

5

63

126

Rev. 0

80

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION–DERATING CURVES

60

50

40

30

20

10

0

11

10

9

11

10

9

OLFM

200LFM

400LFM

0.9V OUTPUT

1V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

0.9V OUTPUT

1V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

8

7

6

5

4

3

2

1

0

1

0

20

40

60

(°C)

80

100

120

0

10

20

30

40

50

0

10

20

30

40

50

T

OUTPUT CURRENT (A)

A

4664A F41

4664A F39

4664A F40

Figure 39. 48V Input Power Loss

2-Phase 50A Output

Figure 40. 54V Input Power Loss

2-Phase 50A Output

Figure 41. LTM4664A 48V_IN1V_OUT

Derating Curve

No Heat Sink

60

50

40

30

20

10

0

60

50

40

30

20

10

0

60

50

40

30

20

10

0

OLFM

200LFM

400LFM

OLFM

200LFM

400LFM

OLFM

200LFM

400LFM

0

20

40

60

(°C)

80

100

120

0

20

40

60

(°C)

80

100

120

0

20

40

60

(°C)

80

100

120

T

A

4664A F42

4664A F43

4664A F44

Figure 42. LTM4664A 54V_IN1V_OUT

Derating Curve

No Heat Sink

Figure 43. LTM4664A 48V_IN1.5V_OUT

350kHz Derating Curve

No Heat Sink

Figure 44. LTM4664A 54V_IN

1.5V_OUT350kHz Derating Curve

No Heat Sink

Rev. 0

81

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

A 2.2nF snubber capacitor is a good value to start with in

EMI PERFORMANCE

series with the snubber resistor to ground. The no load

input quiescent current can be monitored while selecting

different RC series snubber components to get a increased

power loss versus switch node ringing attenuation.

The SW_Cn pin provides access to the midpoint of the

power MOSFETs in LTM4664A’s power stages.

Connecting an optional series RC network from SW_Cn to

GND can dampen high frequency (~30MHz+) switch node

ringing caused by parasitic inductances and capacitances

in the switched-current paths. The RC network is called a

snubber circuit because it dampens (or “snubs”) the res-

onance of the parasitics, at the expense of higher power

loss. To use a snubber, choose first how much power to

allocate to the task and how much PCB real estate is avail-

able to implement the snubber. For example, if PCB space

allows a low inductance 0.5W resistor to be used then the

capacitor in the snubber network (CSW) is computed by:

SAFETY CONSIDERATIONS

The LTM4664A modules do not provide galvanic isolation

from V to V . There is no internal fuse. If required,

IN

OUT

a slow blow fuse with a rating twice the maximum input

current needs to be provided to protect each unit from

catastrophic failure.

The fuse or circuit breaker should be selected to limit the

current to the regulator during overvoltage in case of an

internal top MOSFET fault. If the internal top MOSFET

fails, then turning it off will not resolve the overvoltage,

thus the internal bottom MOSFET will turn on indefinitely

trying to protect the load. Under this fault condition, the

input voltage will source very large currents to ground

through the failed internal top MOSFET and enabled

internal bottom MOSFET. This can cause excessive heat

and board damage depending on how much power the

input voltage can deliver to this system. A fuse or circuit

breaker can be used as a secondary fault protector in

this situation. The device does support over current and

overtemperature protection.

P_SNUB

C_SW

=

V

²•f_SW

INS3n(MAX)

where V

is the maximum input voltage that the

IN3n(MAX)

input to the power stage (V ) will see in the application,

INn

and f is the DC/DC converter’s switching frequency

SW

of operation. C should be NPO, C0G or X7R-type (or

SW

better) material.

The snubber resistor (R ) value is then given by:

SW

5nH

C_SW

R_SW

=

The snubber resistor should be low ESL and capable of

withstanding the pulsed currents present in snubber cir-

cuits. A value between 0.7Ω and 4.2Ω is normal.

Rev. 0

82

For more information www.analog.com

LTM4664A

DUAL 25A/30A PSM APPLICATIONS INFORMATION

n

LAYOUT CHECKLIST/EXAMPLE

Do not put vias directly on pads, unless they are capped

or plated over.

The high integration of LTM4664A makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

n

Use a separate SGND copper plane for components

connected to signal pins. Connect SGND to GND local

to the LTM4664A.

n

Use large PCB copper areas for high current paths,

Use Kelvin sense connections across the input R

resistor if input current monitoring is used.

SENSE

including V , GND and V

. It helps to minimize

INn

OUTSn

the PCB conduction loss and thermal stress.

+

For parallel modules, tie the V_OUTCn, ,V_{OSNS _Cn}

/

–

n

Place high frequency ceramic input and output capaci-

tors next to the V_INSn, GND and V_OUTnpins to minimize

high frequency noise.

V

_{OSNS _Cn}voltage-sense differential pair lines, RUN_n,

COMP_Cna, COMP_nb pin together. The user must

share the SYNC, SHARE_CLK, FAULT, and ALERT pins

of these parts. Be sure to use pull-up resistors on

FAULT, SHARE_CLK and ALERT.

n

Place a dedicated power ground layer underneath the

module.

n

Bring out test points on the signal pins for monitoring.

To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

Figure 45 gives a good example of the recommended lay-

out. Reference DC2672A demo manual.

TOP 3 (1210) FLYING CAPS 1ST STAGE

BOTTOM 4 (1210) FLYING CAPS

1ST STAGE

1ST STAGE INPUT CAP (1210)

BOTTOM LAYER

TOP LAYER

LTM4664A 16 ×16 × 8mm

OUTPUT CAPS

INPUT CAP TO

60A CORE (1206)

2ND STAGE INPUT CAP (1206)

TOP 4 (1206) FLYING CAPS

2ND STAGE

BOTTOM 3 (1206) FLYING CAPS

2ND STAGE

4664A F48

Figure 45. Recommended PCB Layout Package Top and Bottom View

Rev. 0

83

For more information www.analog.com

LTM4664A

TYPICAL APPLICATIONS

10µF ×2

50V

48V

V

OUT1

1%

100k

49.9k

2.2µF

100V

×2

100V

V

10µF

×8

50V

OUT2

19.6k

MAIN BULK

10µF

×8

50V

1%

6.04k

5.1V

R

SENSE

100k 100k

10mΩ

OVP_SET

0.068µF

CIRCUIT

BREAKER

TRIP

7.5k

4:1 VOLTAGE DIVIDER

GND

INTV

CCS2

CCS1

4.7µF

V

OUT2

EXTV

4.7µF

CCS2

CCS1

10k

1µF

GND

PGOODS1

PGOODS2

PGOODS1

PGOODS2

FAULTS1

FAULTS2

ON/OFF

PGOODS1

RUNS1

RUNS2

INTV

CC

FREQS1

FREQS2

1%

36.5k

10k

1%

60.4k

UVS2

PGOODVCORE

1%

PGOOD_C0

100k

12.1k

V

OUT2

V

OUT2

SWC0

+

IN

LTM4664A

0.9V/60A

10µF

25V

×4

V

OUTC0

0.004Ω*

330µF

4V

×2

–

GND

IN

+

V

OSNS

SGND_C0_C1

V

_C0

_C1

INS3

V

INS3

+

V

_C0

+

OSNS

INTV

CC

470µF

×3

INTV

CC

DD33

LOAD

–

V

4.7µF

V

OSNS

DD33

V

DD33

PGOODVCORE

V

DD25

–

PGOOD_C1

V

OSNS

DD25

10k

SWC1

RUN_C0

RUN_C1

V

OUTC1

PGOODS2

330µF

4V

×3

10k

GND

FAULT

FAULT_C0

FAULT_C1

SYNC

10k

SGND_C0_C1

+

V

OSNS

SYNC

+

V

_C1

OSNS

10k

10k 10k 10k

SHARE_CLK

–

SHARE_CLK

SCL

V

OSNS

V

OSNS

SCL

SDA

5V BIAS AT 50mA

EXTV

CC

SDA

ALERT

PINS NOT

SHOWN:

GL_C0

GL_C1

PHFLT_C0

1%

14.7k

14.3k

PWMC1

PWMC0

TWO PHASE PSM 60A SECTION

PROGRAM EA-GM = 3.02ms

RANGE = LOW R

V

DD25

V

DD25

1%

22.6k

100pF

3300pF

1%

1.65k

1%

32.4k

V

= 8k

COMP

OUT

RANGE = LOW

I

LIM

*OPTIONAL SENSE RESISTOR

PHFLT_C1

4664A F46

Figure 46. 0.9V at 60A Output DC/DC µModule Regulator with I²C/SMBus/PMBus

Serial Interface Including Hot Swap Front End with V_OUT2OVP Protection

Rev. 0

84

For more information www.analog.com

LTM4664A

TYPICAL APPLICATIONS

CH1 18V PULSE ON V

OUT2

20V/DIV, 500mS/DIV

CH2 V HOT SWAP TURN OFF

IN

50V/DIV

CH3 CIRCUITBREAKERTRIP SIGNAL

10V/DIV

CH4 1.5V V

PSM

OUT

500mV/DIV

4664A G46b

Figure 46b. V_OUT2Overvoltage Protection

THIS CIRCUIT CAN BE DUPLICATED AND CONNECTED

TO ADDITIONAL LTM4664As USING EACH LTM4664A’S OVP CIRCUIT

20m

DRIVEN BY LTM4664A OVP CIRCUIT

V

28V TO 58V, 60V MAX

10nF

100k

IN

V

OUT2

1k

+

BSC046N10NS3G

33k

470µF

100V

10k

CIRCUITBREAKERTRIP

10k

MMBT3906

100nF

100V

2M

V

1µF

OUT2SET

100nF

100V

30k

V

GATE

SNS

OUT

CC

100k

4664A F46c

562k

FB

U1

SHDN

UV

NEXT DUPLICATE

UV=27V

10nF

10k

V

ON/OFF

FLTB

OVP TRIP POINT AT 16.5V

LT4363-1

OUT2

ENOUT

28k

GND

TMR

47nF

Figure 46c. Hot Swap Circuit Breaker Front End

Rev. 0

85

For more information www.analog.com

LTM4664A

TYPICAL APPLICATIONS

10µF

×2

V

IN

OUT1

30V–58V

1%

49.9k

100k

2.2µF

100V

×2

MAIN BULK

100k

10µF

×8

50V

10µF

×8

50V

V

OUT2

19.6k

100V

1%

10k

5.1V

R

SENSE

10mΩ

0.068µF

100k

0.068µF

V

OUT2_SET

CIRCUIT

BREAKER

TRIP

7.5k

4:1 VOLTAGE DIVIDER

GND

INTV

CCS2

INTV

CCS1

V

OUT2

4.7µF

EXTV

CCS2

EXTV

CCS1

4.7µF

1µF

10k

GND

PGOODS1

PGOODS2

PGOODS1

PGOODS2

FAULTS1

FAULTS2

ON/OFF

RUNS1

PGOODS1

RUNS2

INTV

CC

FREQS1

FREQS2

1%

36.5k

1% 60.4k

10k

UVS2

PGOODVCORE

1%

PGOOD_C0

V

1%

20k

OUT2

V

OUT2

100k

SWC0

+

IN

LTM4664A

1V/30A

V

OUTC0

0.004*

10µF

25V

x4

100µF

×2

–

GND

IN

+

470µF

×2

4V

V

OSNS

4V

SGND_C0_C1

V

INS3

_C0

_C1

220µF

×2

V

INS3

+

V

_C0

OSNS

LOAD0

–

INTV

CC

DD33

DD25

V

_C0

OSNS

INTV

CC

V

PGOODVCORE

4.7µF

–

V

DD33

V

DD33

PGOOD_C1

V

OSNS

V

DD25

SWC1

10k

1.5V/25A

RUN_C0

RUN_C1

V

OUTC1

100µF

PGOODS2

GND

×3

10k

+

470µF

4V

FAULT

SGND_C0_C1

LOAD1

×1

4V

FAULT_C0

FAULT_C1

SYNC

+

10k

V

OSNS

+

V

_C1

OSNS

–

V

OSNS

SYNC

SHARE_CLK

–

V

_C1

OSNS

10k 10k 10k 10k

SHARE_CLK

SCL

EXTV

+5V BIAS 50mA

CC

SCL

SDA

ALERT

PINS NOT SHOWN:

GL_C0

GL_C1

PHFLT_C0

PHFLT_C1

1%

PWMC1

PWMC0

14.5k

TWO PHASE PSM 25A/30A SECTION

1%

14.3k

1%

V

DD25

14.3k

2200pF

100pF

V

DD25

V

RANGE = LOW CH0 PROGRAM EA-GM = 3.69ms

OUT

RANGE = LOW

2200pF

100pF

1%

2.43k

1%

22.6k

1%

I

R

= 5k

LIM

COMP

CH1 PROGRAM EA-GM = 3.69ms

= 3k

4.22k

22.6k

R

*OPTIONAL SENSE RESISTOR

COMP

4664A F47

Figure 47. 54V to 1.0V at 30A and 1.5V Outputs at 25A With Providing I²C/SMBus/PMBus Serial Interface

Rev. 0

86

For more information www.analog.com

LTM4664A

TYPICAL APPLICATIONS

10µF

×2

50V

V

40V–58V

OUT1A

IN

49.9k

1%

100k

2.2µF

×2

100V

MAIN BULK

10µF

100k

10µF

×6

50V

100V

V

OUT2A

5.1V

1%

6.04k

×6

R

SENSE

10mΩ

50V

100k

19.6k

0.068µF

OVP_SET

CIRCUIT

BREAKER

TRIP

7.5k

4:1 VOLTAGE DIVIDER

GND

INTV

CCS1

CCS2

4.7µF

V

OUT2A

4.7µF

EXTV

CCS1

CCS2

1µF

GND

PGOODS1

FAULTS1

10k

PGOODS1A

PGOODS2A

PGOODS2

FAULTS2

ON/OFFA

PGOODS1A

RUNS1

RUNS2

INTV

CCA

FREQS1

FREQS2

1%

36.5k

10k

1%

60.4k

UVS2

PGOODVCORE

PGOOD_C0

1%

V

OUT2A

100k

12.1k

V

OUT2

SWC0

LTM4664A

(A)

0.9V/120A

+

IN

V

OUTC0

GND

10µF

25V

×4

220µF

–

×4

4V

+

V

SGND_C0_C1

OSNS

_C0

_C1

INS3

V

INS3

+

V

_C0

OSNS

INTV

CCA

INTV

CC

–

V

LOAD

OSNS

4.7µF

V

DD33A

V

DD33

PGOODVCORE

DD33A

–

V

PGOOD_C1

DD25A

V

OSNS

V

DD25

10k

SWC1

_C0

RUN

V

OUTC1

PGOODS2A

220µF

×4

4V

RUN_C1

GND

10k

FAULT

SGND_C0_C1

FAULT_C0

FAULT_C1

SYNC

10k

+

V

+

OSNS

SYNC

V

_C1

OSNS

10k 10k 10k 10k

SHARE_CLK

–

SHARE_CLK

SCL

V

OSNS

–

V

_C1

SCL

SDA

OSNS

+5V BIAS ≥ 50mA

EXTV

CC

SDA

ALERT

PINS NOT SHOWN:

GL_C0

GL_C1

1%

14.3k

1%

PWMC1A

14.3k

V

DD25A

TWO PHASE PSM 60A SECTION

DD25A

PWMC0A

100pF

6800pF

1%

1.65Ω

PHFLT_C0

PHFLT_C1

32.4k

V

RANGE = LOW PROGRAM EA-GM = 3.02ms

OUT

RANGE = LOW

I

R

COMP

= 4k ALL CHANNELS

LIM

FOR ALL CHANNELS

COMPH

COMPL

10µF

×2

50V

V

IN

40V–58V

OUT1B

1%

49.9k

2.2µF

100V

×2

100k

100V

V

10µF

×6

MAIN BULK

100k

10µF

×6

59V

OUT2B

5.1V

1%

6.04k

R

50V

SENSE1

19.6k

0.068µF

100k

10mΩ

OVP_SET

CIRCUIT

BREAKER

7.5k

4:1 VOLTAGE DIVIDER

TRIP

GND

INTV

CCS2

INTV

CCS1

4.7µF

V

OUT2B

EXTV

CCS2

EXTV

CCS1

4.7µF

1µF

GND

10k

PGOODS1B

PGOODS2A

PGOODS1

PGOODS2

FAULTS1

FAULTS2

ON/OFFB

PGOODS1B

RUNS1

RUNS2

FREQS1

FREQS2

1%

36.5k

1%

60.4k

UVS2

PGOODVCORE

1%

100k

PGOOD_C0

1%

12.1k

V

OUT2B

V

OUT2

SWC0

LTM4664A

(B)

+

IN

V

OUTC0

GND

10µF

×4

25V

220µF

×4

4V

470µF

×2

4V

–

SGND_C0_C1

_C0

_C1

INS3

+

V

OSNS

V

+

INS3

V

_C0

OSNS

–

INTV

CCB

DD33B

DD25B

V

OSNS

–

INTV

CC

V

_C0

OSNS

V

4.7µF

V

DD33

PGOODVCORE

PGOOD_C1

V

DD25

SWC1

RUN_C0

RUN_C1

V

OUTC1

GND

PGOODS2A

220µF

×4

4V

SGND_C0_C1

FAULT

FAULT_C0

FAULT_C1

SYNC

+

V

OSNS

+

V

_C1

OSNS

SYNC

–

V

OSNS

SHARE_CLK

SCL

–

_C1

V

OSNS

SHARE_CLK

SCL

+5V BIAS ≥ 50mA

EXTV

CC

SDA

ALERT

V

DD25B

1%

PWMC1B

14.3k

TWO PHASE PSM 60A SECTION

COMPL

COMPH

PWMC0B

1%

22.6k

1%

1.65k

1%

1.65k

PINS NOT SHOWN:

GL_C0

PHFLT_C0

PHFLT_C1

GL_C1

1%

14.3k

4664A F48

Figure 48. Two Paralleled LTM4664A Producing 54V to 0.9V_OUTat 120A. Integrated Power System Management Features

Accessible Over 2-Wire I²C/SMBus/PMBus Serial Interface

Rev. 0

87

For more information www.analog.com

LTM4664A

TYPICAL APPLICATIONS

10µF

×2

50V

V

30V TO 58V

IN

OUT1

1%

100k

49.9k

2.2µF

×2

100V

MAIN BULK

V

10µF

×8

50V

100k

10µF

×8

50V

OUT2

19.6k

100V

5.1V

1%

10k

R

SENSE

10mΩ

0.068µF

100k

OVP_SET

CIRCUIT

BREAKER

TRIP

7.5k

4:1 VOLTAGE DIVIDER

GND

INTV

CCS1

CCS2

V

4.7µF

V

OUT2

EXTV

CCS1

4.7µF

CCS2

1µF

10k

GND

PGOODS1

PGOODS2

PGOODS1

PGOODS2

FAULTS1

FAULTS2

ON/OFF

PGOODS1

RUNS1

INTV

CC

RUNS2

FREQS1

FREQS2

1%

36.5k

10k

1%

ADDITIONAL 30W FROM V

60.4k

OUT2

UVS2

PGOODVCORE

PGOOD_C0

1%

PGOODS2

V

20k

OUT2

ENABLE

100k

V

OUT2

SWC0

1V/15A

LTM4664A

V

IN/4

+

IN

V

INPUT

OUTPUT

OUTC0

10µF

25V

×4

–

56µF

35V

+

GND

100µF

×6

OTHER DC/DC REGS

NO LOAD UNTIL

ENABLED

470µF

SGND_C0_C1

_C0

_C1

INS3

V

+

INS3

V

_C0

OSNS

INTV

CC

DD33

DD25

INTV

CC

–

V

OSNS

V

4.7µF

V

10k

DD33

INTV

CC

V

PGOOD_C1

V

DD25

10k

SWC1

RUN_C0

RUN_C1

1.2V/15A

10k

V

OUTC1

PGOODS2

+

GND

100µF

×6

470µF

FAULT

SGND_C0_C1

FAULT_C0

FAULT_C1

SYNC

10k

+

V

_C1

OSNS

10k 10k 10k 10k

–

_C1

OSNS

SHARE_CLK

SCL

V

+5V 50mA

EXTV

CC

SDA

ALERT

PINS NOT SHOWN:

GL_C0

GL_C1

PHFLT_C0

PHFLT_C1

V

DD25

1%

14.3k

PWMC1

100pF

TWO PHASE PSM SECTION

PWMC0

2200pF

100pF

1%

22.6k

1%

2.43k

1%

2200pF

CHANNEL 0 AND 1 V

RANGE = LOW CHANNEL 0 AND 1

OUT

LIM

32.4k 22.6k

1%

14.3k

I

RANGE = LOW

EA-GM = 3.69ms

= 5k

R

COMP

1%

14.3k

4664A F49

Figure 49. 30V – 58V to 1V and 1.2V at 15A, with Additional 30W from V_OUT2. Integrated Power System Management Features

Accessible Over 2-Wire I²C/SMBus/PMBus Serial Interface. For Evaluation and More Information, See Demo Boards DC2143

Rev. 0

88

For more information www.analog.com

LTM4664A

TYPICAL APPLICATIONS

10µF

×2

50V

V

OUT1A

V

40V – 58V

IN

49.9k

1%

100k

2.2µF

×2

100V

V

OUT2A

MAIN BULK

10µF

×8

50V

100k

10µF

5.1V

1%

6.04k

×8

R

50V

SENSE1

10mΩ

0.068µF

19.6k

100k

OVP_SET

CIRCUIT

BREAKER

TRIP

7.5k

4:1 VOLTAGE DIVIDER

GND

INTV

CCS2

CCS1

4.7µF

V

OUT2A

EXTV

CCS1

4.7µF

CCS2

1µF

GND

SGNDS1

PGOODS1

FAULTS1

10k

PGOODS1A

PGOODS2A

PGOODS2

FAULTS2

ON/OFFA

PGOODS1A

RUNS1

RUNS2

INTV

CCA

10k

FREQS1

FREQS2

1%

36.5k

1%

60.4k

UVS2

PGOOD1P2V

PGOOD_C0

1%

12.1k 100k

1%

V

OUT2A

V

OUT2

SWC0

1.2V/30A

LTM4664

(A)

+

IN

V

OUTC0

GND

100µF

×3

10µF

–

+

×4

470µF

SGND_C0_C1

_C0

_C1

25V

INS3

V

+

INS3

V

_C0

OSNS

INTV

CCA

DD33A

DD25A

LOAD

–

V

INTV

OSNS

CC

V

4.7µF

PGOODVCORE

V

DD33A

DD33

PGOOD_C1

V

DD25

10k

SWC1

RUN_C0

RUN_C1

V

OUTC1

GND

PGOODS2A

220µF

×2

4V

10k 10k

SGND_C0_C1

FAULT_C0

FAULT_C1

SYNC

+

10k

V

OSNS

FAULT

SYNC

+

V

_C1

OSNS

–

V

10k 10k 10k 10k

OSNS

–

V

_C1

CLK SHARE

SCL

OSNS

SHARE_CLK

SCL

+5V BIAS 50mA

EXTV

CC

SDA

ALERT

V

DD25A

1%

14.3k

PWMC1A

PWMC0A

DUAL 30A PSM SECTION

220pF

2200pF

1%

32.4

1%

3.24k

1.65k

1%

32.4k

PINS NOT SHOWN:

GL_C0

GL_C1

1%

14.3k

PHFLT_C0

PHFLT_C1

COMPH

COMPL

1%

14.3k

10µF

×2

50V

V

OUT1B

V

40V – 58V

IN

1%

100k

49.9k

2.2µF

100V

×2

100V

V

OUT2B

10µF

×8

MAIN BULK

10µF

×8

50V

100k

1%

6.04k

5.1V

R

50V

SENSE2

10mΩ

0.068µF

19.6k

100k

OVP_SET

CIRCUIT

BREAKER

TRIP

7.5k

4:1 VOLTAGE DIVIDER

GND

INTV

CCS2

CCS1

4.7µF

V

OUT2B

EXTV

CCS1

4.7µF

CCS2

1µF

GND

SGNDS1

PGOODS1

FAULTS1

10k

PGOODS1B

PGOODS2A

PGOODS2

FAULTS2

ON/OFFB

RUNS1

PGOODS1B

RUNS2

FREQS1

FREQS2

1%

36.5k

1%

INTV

CCB

60.4k

10k

UVS2

PGOODVCORE

PGOOD_C0

1%

12.1k 100k

1%

V

OUT2B

V

OUT2

SWC0

LTM4664A

(B)

0.9V/90A

+

IN

V

OUTC0

GND

10µF

+

–

220µF

×2

4V

V

OSNS

IN

×4

25V

470µF

×4

4V

SGND_C0_C1

V

_C0

_C1

INS3

+

V

INS3

+

OSNS

V

_C0

OSNS

LOAD

INTV

CCB

–

INTV

V

OSNS

CC

–

OSNS

V

DD33B

4.7µF

–

V

DD33

V

OSNS

PGOODVCORE

V

DD25B

PGOOD_C1

V

DD25

SWC1

RUN_C0

RUN_C1

V

OUTC1

PGOODS2A

220µF

×2

4V

GND

FAULT

SGND_C0_C1

FAULT_C0

FAULT_C1

SYNC

+

V

OSNS

+

V

_C1

OSNS

SYNC

SHARECLK

SCL

–

V

OSNS

–

SHARE_CLK

SCL

V

_C1

OSNS

+5V BIAS 50mA

EXTV

CC

SDA

ALERT

1%

V

PWMC1B

DD25B

14.3k

TWO PHASE PSM 60A SECTION

COMPH

COMPL

PWM C0B

1%

22.6k

1%

1.65k

1%

1.65k

100pF

4700pF

PINS NOT SHOWN:

GL_C0

GL_C1

ALL CHANNELS HAVE

RANGE = LOW

0.9V CHANNELS

GM = 3.69ms

1%

14.3k

V

I

OUT

RANGE = LOW

R

COMP

= 3.4k

LIM

1.2V GM = 3.69ms

CHANNEL R = 4k

4664A F50

PHFLT_C0

COMP

Figure 50. 48V-58V Input, Converting 1.2V at 30A, and 0.9V at 90A. Power System Management Features Accessible Through

LTM4664A Over 2-Wire I²C/SMBus/PMBus Serial Interface.

Rev. 0

89

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

ADDRESSING AND WRITE PROTECT

CMD

DATA

DEFAULT

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM VALUE

PAGE

0x00 Provides integration with multi-page PMBus devices.

R/W Byte

N

Reg

0x00

PAGE_PLUS_WRITE

PAGE_PLUS_READ

0x05 Write a supported command directly to a PWM channel. W Block

0x06 Read a supported command directly from a PWM

channel.

Block

R/W

WRITE_PROTECT

0x10 Level of protection provided by the device against

accidental changes.

R/W Byte

N

Y

0x00

2

MFR_ADDRESS

0xE6 Sets the 7-bit I C address byte.

R/W Byte

N

Y

Reg

Y

0x4F

0x80

MFR_RAIL_ADDRESS

0xFA Common address for PolyPhase outputs to adjust

common parameters.

PAGE

The PAGE command provides the ability to configure, control and monitor both PWM channels through only one

physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands

for one PWM channel.

Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.

Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTM4664A

will respond to read commands as if PAGE were set to 0x00 (Channel 0 results).

This command has one data byte.

PAGE_PLUS_WRITE

The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send

the data for the command, all in one communication packet. Commands allowed by the present write protection level

may be sent with PAGE_PLUS_WRITE.

The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send

a non-paged command, the Page Number byte is ignored.

This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a

command that has two data bytes is shown in Figure 51.

1

7

1

8

1

8

1

8

1

8

1

SLAVE

ADDRESS

PAGE_PLUS

COMMAND CODE

BLOCK COUNT

(= 4)

PAGE

NUMBER

COMMAND

CODE

S

W

A

…

8

1

8

1

8

1

LOWER DATA

BYTE

UPPER DATA

BYTE

A

PEC BYTE

A

P

4664A F54

Figure 51. Example of PAGE_PLUS_WRITE

PAGE_PLUS_READ

The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read

the data returned by the command, all in one communication packet .

Rev. 0

90

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access

data from a non-paged command, the Page Number byte is ignored.

This command uses the Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown

in Figure 52.

1

7

1

8

1

8

1

8

1

8

1

SLAVE

ADDRESS

PAGE_PLUS

COMMAND CODE

BLOCK COUNT

(= 2)

PAGE

NUMBER

COMMAND

CODE

S

W

A

…

1

7

1

8

1

8

1

8

1

8

1

SLAVE

ADDRESS

BLOCK COUNT

LOWER DATA

BYTE

UPPER DATA

BYTE

Sr

R

A

PEC BYTE

NA

P

(= 2)

4664A F55

Figure 52. Example of PAGE_PLUS_READ

Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another

PAGE_PLUS command. If this is attempted, the LTM4664A will NACK the entire PAGE_PLUS packet and issue a CML

fault for Invalid/Unsupported Data.

WRITE_PROTECT

The WRITE_PROTECT command is used to control writing to the LTM4664A device. This command does not indicate

the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the

value of this command.

BYTE MEANING

0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_

EE_UNLOCK, and STORE_USER_ALL commands.

0x40 Disable all writes except to the WRITE_PROTECT, PAGE,

MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,

OPERATION and CLEAR_FAULTS command. Individual fault

bits can be cleared by writing a 1 to the respective bits in the

STATUS commands.

0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,

MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,

PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_

ALL. Individual fault bits can be cleared by writing a 1 to the

respective bits in the STATUS commands.

0x10 Reserved, must be 0

0x08 Reserved, must be 0

0x04 Reserved, must be 0

0x02 Reserved, must be 0

0x01 Reserved, must be 0

Enable writes to all commands when WRITE_PROTECT is set to 0x00.

If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT and CLEAR_

FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the

STATUS commands.

Rev. 0

91

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

MFR_ADDRESS

The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.

Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,

cannot be deactivated. If RCONFIG is set to ignore, the ASEL pin is still used to determine the LSB of the channel

address. If the ASEL pin is open, the LTM4664A will use the MFR_ADDRESS value stored in NVM to construct the

effective address of the part.

This command has one data byte.

MFR_RAIL_ADDRESS

The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value

of this command should be common to all devices attached to a single power supply rail.

The user should only perform command writes to this address. If a read is performed from this address and the rail

devices do not respond with EXACTLY the same value, the LTM4664A will detect bus contention and may set a CML

communications fault.

Setting this command to a value of 0x80 disables rail device addressing for the channel.

This command has one data byte.

GENERAL CONFIGURATION COMMANDS

DATA

DEFAULT

VALUE

COMMAND NAME

MFR_CHAN_CONFIG

MFR_CONFIG_ALL

CMD CODE DESCRIPTION

TYPE

Configuration bits that are channel specific. R/W Byte

General configuration bits. R/W Byte

PAGED FORMAT UNITS NVM

0xD0

0xD1

Y

N

Reg

Y

0x10

0x21

MFR_CHAN_CONFIG

General purpose configuration command common to multiple LTC products.

BIT MEANING

7

6

5

4

3

2

1

Reserved

Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF.

Enable short cycle recognition if this bit is set to a 1.

SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled.

No FAULT ALERT, ALERT is not pulled low if FAULT is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are

propagated on FAULT.

0

Disables the V

decay value requirement for MFR_RETRY_TIME and t

processing. When this bit is set to a 0, the output must decay to

OUT

OFF(MIN)

less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from

high to low to high.

This command has one data byte.

Rev. 0

92

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

A short cycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been

commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned

ON and OFF through either the RUN pin and or the PMBus OPERATION command.

If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following:

1. Immediately tri-state the PWM channel output;

2. Start the retry delay timer as specified by the t

.

OFF(MIN)

3. After the t

value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_

OFF(MIN)

MFR_SPECIFIC bit #1 will assert.

If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following:

1. Stop ramping down the PWM channel output;

2. Immediately tri-state the PWM channel output;

3. Start the retry delay timer as specified by the t

.

OFF(MIN)

4. After the t

value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_

OFF(MIN)

MFR_SPEFIFIC bit #1 will assert.

If the short cycle event occurs and the short cycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine

will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user.

MFR_CONFIG_ALL

General purpose configuration command common to multiple LTC products.

BIT MEANING

7

6

5

4

3

2

Enable Fault Logging

Ignore Resistor Configuration Pins

Mask PMBus, Part II, Section 10.9.1 Violations

Disable SYNC output

Enable 255ms PMBus timeout

A valid PEC required for PMBus writes to be accepted. If this bit is not

set, the part will accept commands with invalid PEC.

1

0

Enable the use of PMBus clock stretching

Execute CLEAR_FAULTS on rising edge of either RUN pin.

This command has one data byte.

ON/OFF/MARGIN

CMD

DATA

DEFAULT

VALUE

COMMAND NAME

ON_OFF_CONFIG

OPERATION

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte

Y

Reg

Y

0x1E

0x80

0x01 Operating mode control. On/off, margin high and margin R/W Byte

low.

MFR_RESET

0xFD Commanded reset without requiring a power-down.

Send Byte

N

NA

Rev. 0

93

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

ON_OFF_CONFIG

The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to

turn the PWM channel on and off.

Supported Values:

VALUE

MEANING

0x1F

OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.

OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off.

RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.

RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.

0x1E

0x17

0x16

Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.

This command has one data byte.

OPERATION

The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It

is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in

the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin

instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET

or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed

to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation

command is sequence off. If V is applied to a part with factory default programming and the VOUT_CONFIG resistor

IN

configuration pins are not installed, the outputs will be commanded off.

The part defaults to the Sequence Off state.

This command has one data byte.

Supported Values:

VALUE

MEANING

0xA8

Margin high.

Margin low.

0x98

0x80

On (V

back to nominal even if bit 3 of ON_OFF_CONFIG is not set).

OUT

0x40*

0x00*

Soft off (with sequencing).

Immediate off (no sequencing).

*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.

Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored.

This command has one data byte.

MFR_RESET

This command provides a means to reset the LTM4664A PSM from the serial bus. This forces the LTM4664A PSM

to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a

soft-start of both PWM channels, if enabled.

This write-only command has no data bytes.

Rev. 0

94

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

PWM CONFIGURATION

DATA

DEFAULT

COMMAND NAME

MFR_PWM_COMP

MFR_PWM_MODE

MFR_PWM_CONFIG

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM VALUE

0xD3

0xD4

0xF5

PWM loop compensation configuration

R/W Byte

Y

N

Reg

Y

0x28

0xC7

0x10

Configuration for the PWM engine.

Set numerous parameters for the DC/DC controller

including phasing.

FREQUENCY_SWITCH

0x33

Switching frequency of the controller.

R/W

Word

N

L11

kHz

Y

350kHz

0xFABC

MFR_PWM_MODE

The MFR_PWM_MODE command sets important PWM controls for each channel.

The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping

mode), or forced continuous conduction mode.

BIT

7

0b

1b

6

MEANING

Use High Range of I

Low Current Range

High Current Range

Enable Servo Mode

LIMIT

5

External temperature sense:

0: ΔV measurement.

BE

Now reserved, ΔV only supported.

BE

[4:3]

2

Reserved

Reserved, always low DCR current sense

1

V

OUT

Range

1b

0b

The maximum output voltage is 2.75V

The maximum output voltage is 3.6V

Bit[0] Mode

0b

1b

Discontinuous

Forced Continuous

Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.

Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the

channel output is active. Writing this bit when the channel is active will generate a CML fault.

Bit [6] The LTM4664A PSM will not servo while the part is OFF, ramping on or ramping off. When set to a one, the

output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the

READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value).

The LTM4664A PSM computes temperature in °C from ∆V measured by the ADC at the TSNSn pin as

BE

T = (G • ΔV • q/(K • ln(16))) – 273.15 + O

BE

Rev. 0

95

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

For both equations,

–14

G = MFR_TEMP_1_GAIN • 2 , and

O = MFR_TEMP_1_OFFSET

Bit[2] is now reserved, and Ultra Low DCR mode is default.

Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes

the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing

this bit when the channel is active will generate a CML fault.

B

it[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous con-

duction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of

this bit. This command has one data byte.

MFR_PWM_COMP

The MFR_PWM_COMP command sets the g of the PWM channel error amplifiers and the value of the internal R

m

ITHn

compensation resistors. This command affects the loop gain of the PWM output which may require modifications to

the external compensation network.

BIT

MEANING

BIT [7:5]

000b

Error Amplifier GM Adjust (ms)

1.00

1.68

2.35

3.02

3.69

4.36

5.04

5.73

001b

010b

011b

100b

101b

110b

111b

BIT [4:0]

00000b

00001b

00010b

00011b

00100b

00101b

00110b

00111b

01000b

01001b

01010b

01011b

01100b

01101b

01110b

R

(kΩ)

COMP

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.5

3

3.5

4

4.5

5

Rev. 0

96

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

01111b

10000b

10001b

10010b

10011b

10100b

10101b

10110b

10111b

11000b

11001b

11010b

11011b

11100b

11101b

11110b

11111b

5.5

6

7

8

9

11

13

15

17

20

24

28

32

38

46

54

62

This command has one data byte.

MFR_PWM_CONFIG

The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the

SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the

channels must be commanded off. If either channel is in the RUN state and this command is written, the command

will be NACK’d and a BUSY fault will be asserted.

BIT

MEANING

7

Reserved

[6:5]

00b

01b

10b

11b

Input current sense gain.

2x gain. 0mV to 50mV range.

4x gain. 0mV to 20mV range.

8x gain. 0mV to 5mV range.

Reserved

4

Share Clock Enable : If this bit is 1, the

SHARE_CLK pin will not be released until

IN

V

> VIN_ON. The SHARE_CLK pin will be

pulled low when V < VIN_OFF. If this bit is 0, the SHARE_

IN

CLK pin will not be pulled low when VIN < VIN_OFF except

for the initial application of VIN.

BIT [2:0]

000b

001b

010b

011b

100b

101b

110b

CHANNEL 0 (DEGREES)

CHANNEL 1 (DEGREES)

0

90

0

180

270

240

120

240

300

0

120

60

120

Rev. 0

97

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

FREQUENCY_SWITCH

The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTM4664A.

Supported Frequencies:

VALUE [15:0]

0x0000

0xF3E8

RESULTING FREQUENCY (TYP)

External Oscillator

250kHz

0xFABC

0xFB52

0xFBE8

0x023F

350kHz

425kHz

500kHz

575kHz

0x028A

0x02EE

0x03E8

650kHz

750kHz

1000kHz

The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be

commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY

fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be

detected as the PLL locks onto the new frequency.

This command has two data bytes and is formatted in Linear_5s_11s format.

VOLTAGE

Input Voltage and Limits

CMD

DATA

PAGED FORMAT

DEFAULT

VALUE

COMMAND NAME

CODE DESCRIPTION

TYPE

UNITS

NVM

VIN_OV_FAULT_LIMIT

0x55 Input supply overvoltage fault limit.

R/W

N

L11

V

Y

15.5

Word

0xD3E0

VIN_UV_WARN_LIMIT

VIN_ON

0x58 Input supply undervoltage warning limit.

R/W

Word

V

Y

N

4.65

0xCA53

0x35 Input voltage at which the unit should start

power conversion.

R/W

Word

4.75

0xCA60

VIN_OFF

0x36 Input voltage at which the unit should stop

power conversion.

R/W

Word

V

4.5

0xCA40

MFR_RVIN

The resistance value of the V pin filter element R Word

mΩ

1000

0x03E8

IN

in milliohms set at factory.

VIN_OV_FAULT_LIMIT

The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes

an input overvoltage fault.

This command has two data bytes in Linear_5s_11s format.

Rev. 0

98

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

VIN_UV_WARN_LIMIT

The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under

-

voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON

command and the unit has been enabled. If the V Voltage drops below the VIN_OV_WARN_LIMIT the device:

IN

• Sets the INPUT Bit Is the STATUS_WORD

• Sets the V Undervoltage Warning Bit in the STATUS_INPUT Command

IN

• Notifies the Host by Asserting ALERT, unless Masked

VIN_ON

The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion.

This command has two data bytes and is formatted in Linear_5s_11s format.

VIN_OFF

The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion.

This command has two data bytes and is formatted in Linear_5s_11s format.

MFR_RVIN

The MFR_RVIN command is not available, MFR_RVIN is set at factory assembly with 1Ω.

This command has two data bytes and is formatted in Linear_5s_11s format.

Output Voltage and Limits

DATA

DEFAULT

VALUE

2

0x14

1.8

0x2CCD

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

R Byte

PAGED FORMAT

Y

UNITS

NVM

–12

VOUT_MODE

0x20

Output voltage format and exponent

Reg

L16

–12

(2 ).

VOUT_MAX

0x24

Upper limit on the output voltage

the unit can command regardless of

any other commands.

R/W

Word

Y

V

Y

VOUT_OV_FAULT_ LIMIT

VOUT_OV_WARN_ LIMIT

VOUT_MARGIN_HIGH

0x40

0x42

0x25

Output overvoltage fault limit.

R/W

Y

L16

V

Y

1.1

Word

0x119A

Output overvoltage warning limit.

R/W

Word

R/W

Word

1.075

0x1133

1.05

0x10CD

Margin high output voltage set

point. Must be greater than

VOUT_COMMAND.

VOUT_COMMAND

0x21

0x26

Nominal output voltage set point.

R/W

Y

L16

V

Y

1.0

Word

0x1000

VOUT_MARGIN_LOW

Margin low output voltage

set point. Must be less than

VOUT_COMMAND.

R/W

Word

0.95

0x0F33

VOUT_UV_WARN_ LIMIT

VOUT_UV_FAULT_ LIMIT

MFR_VOUT_MAX

0x43

0x44

0xA5

Output undervoltage warning limit.

Output undervoltage fault limit.

Maximum allowed output voltage.

R/W

Y

L16

V

Y

0.925

Word

0x0ECD

R/W

Word

R Word

0.9

0x0E66

7.8

0x1CCD

Rev. 0

99

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

VOUT_MODE

The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode

(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write

commands.

This read-only command has one data byte.

VOUT_MAX

The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com-

mand regardless of any other commands or combinations. The maximum allowed value of this command is 3.6V.

The maximum output voltage the LTM4664A PSM can produce is 1.8V including VOUT_MARGIN_HIGH. However, the

VOUT_OV_FAULT_LIMIT can be commanded as high as 3.6V.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_OV_FAULT_LIMIT

The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor comparator

at the sense pins, in volts, which causes an output overvoltage fault.

If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modified

to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of

MFR_COMMON. Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND is mod-

ified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior

and possible damage to the switcher.

If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if VOUT_OV_FAULT

is propagated. The LTM4664A PSM will pull the TG low and assert the BG bit as soon as the overvoltage condition is

detected.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_OV_WARN_LIMIT

The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins,

in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this

limit has been exceeded.

In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command

• Notifies the host by asserting ALERT pin, unless masked

This condition is detected by the ADC so the response time may be up to t

This command has two data bytes and is formatted in Linear_16u format.

.

CONVERT

Rev. 0

100

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

VOUT_MARGIN_HIGH

The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts,

when the OPERATION command is set to “Margin High”. The value should be greater than VOUT_COMMAND. The

maximum guaranteed value on VOUT_MARGIN_HIGH is 3.6V.

This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_

RATE will be used if this command is modified while the output is active and in a steady-state condition.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_COMMAND

The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed

value on VOUT is 3.6V.

This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_

RATE will be used if this command is modified while the output is active and in a steady-state condition.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_MARGIN_LOW

The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,

when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.

This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_

RATE will be used if this command is modified while the output is active and in a steady-state condition.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_UV_WARN_LIMIT

The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins,

in volts, which causes an output voltage low warning.

In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command

• Notifies the host by asserting ALERT pin, unless masked

This command has two data bytes and is formatted in Linear_16u format.

VOUT_UV_FAULT_LIMIT

The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor com-

parator at the sense pins, in volts, which causes an output undervoltage fault.

This command has two data bytes and is formatted in Linear_16u format.

Rev. 0

101

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

MFR_VOUT_MAX

The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_

LIMIT. If the output voltages are set to high range (Bit 6 of MFR_PWM_CONFIG set to a 0) MFR_VOUT_MAX is 3.6V. If

the output voltage is set to low range (Bit 6 of MFR_PWM_CONFIG set to a 1) the MFR_VOUT_MAX is 2.75V. Entering

a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped to

the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set. The

maximum value to program is 1.8V and maximum operating is 1.5V.

This read only command has 2 data bytes and is formatted in Linear_16u format.

OUTPUT CURRENT AND LIMITS

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

MFR_IOUT_CAL_GAIN

0xDA

The ratio of the voltage at the current

R Word

Y

L11

mΩ

Y

0.375

0xD018

sense pins to the sensed current. For

devices using a fixed current sense

resistor, it is the resistance value in

mΩ.

MFR_IOUT_CAL_GAIN_TC

IOUT_OC_FAULT_LIMIT

IOUT_OC_WARN_LIMIT

0xF6

0x46

0x4A

Temperature coefficient of the current R/W Word

sensing element.

Y

CF

Y

3900

0x0F3C

Output overcurrent fault limit.

R/W Word

L11

A

45.0

0xE2D0

Output overcurrent warning limit.

R/W Word

34.0

0xE230

MFR_IOUT_CAL_GAIN

The MFR_IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms.

(see also MFR_IOUT_CAL_GAIN_TC).

This command has two data bytes and is formatted in Linear_5s_11s format.

MFR_IOUT_CAL_GAIN_TC

The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_

GAIN sense resistor or inductor DCR in ppm/°C.

This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •

–6

10 . Nominal temperature is 27°C. The MFR_IOUT_CAL_GAIN is multiplied by:

[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)].

DCR sensing will have a typical value of 3900.

The MFR_IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT,

MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.

Rev. 0

102

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

IOUT_OC_FAULT_LIMIT

The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the controller

is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the

+

–

progammable peak output current limit value in mV between I

and I

. The actual value of current limit is

SENSE

+

–

(I

– I

)/MFR_IOUT_CAL_GAIN in Amperes.

SENSE

MFR_PWM_MODE[7] = 0b,

Use ILIM Low Range Low

Current Range (mV)

MFR_PWM_MODE[7] = 1b,

High Current Range (mV)

ILPEAK (A)

Not Needed

IOUT (A)

ILPEAK (A)

29.9

IOUT (A)

23.9

18.86

20.42

21.14

22.27

23.41

24.55

25.68

26.82

Not Needed

10.48

11.34

32.4

26.4

11.74*

12.37

33.54

35.3

27.54

29.3

13.01**

13.64

37.1

31.1

38.9

32.9

14.27

40.8

34.8

14.90

42.6

36.6

* = Recommended for 25A Current Limit Plus Some Headroom

** = Recommended for 30A Current Limit Plus Some Headroom for Up to 1.2V Output

Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output

current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:

Peak Current Limit = MFR_IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).

The LTM4664A automatically converts currents to the appropriate internal bit value.

The I

range is set with bit 7 of the MFR_PWM_MODE command.

OUT

The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.

If the IOUT_OC_FAULT_LIMIT is exceeded, the device:

• Sets the IOUT bit in the STATUS word

• Sets the IOUT Overcurrent fault bit in the STATUS_IOUT

• Notifies the host by asserting ALERT, unless masked

This command has two data bytes and is formatted in Linear_5s_11s format.

**MFR_PWM_MODE[7]=1 is the high current range for ultra low DCR sensing. This range should be used since these

current threshold values are too large for the LTM4664A.

*Recommended for 35% up above 25A current limit

Rev. 0

103

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

IOUT_OC_WARN_LIMIT

This command sets the value of the output current measured by the ADC that causes an output overcurrent warning

in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded.

In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the IOUT bit in the STATUS_WORD

• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and

• Notifies the host by asserting ALERT pin, unless masked

The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.

This command has two data bytes and is formatted in Linear_5s_11s format

Input Current and Limits

CMD

DATA

FORMAT

DEFAULT

VALUE

COMMAND NAME

CODE DESCRIPTION

TYPE

UNITS

NVM

MFR_IIN_CAL_GAIN

0xE8 The resistance value of the input current sense

element in mΩ.

R/W Word

L11

mΩ

Y

2

0xC200

MFR_IIN_CAL_GAIN

The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms.

(see also READ_IIN).

This command has two data bytes and is formatted in Linear_5s_11s format.

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

0x5D Input overcurrent warning

limit.

TYPE

PAGED

FORMAT

UNITS

NVM

IIN_OC_WARN_LIMIT

R/W Word

N

L11

A

Y

10.0

0xD280

IIN_OC_WARN_LIMIT

The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes

a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been

exceeded.

In response to the IIN_OC_WARN_LIMIT being exceeded, the device:

• Sets the OTHER bit in the STATUS_BYTE

• Sets the INPUT bit in the upper byte of the STATUS_WORD

• Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and

• Notifies the host by asserting ALERT pin

This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. 0

104

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

TEMPERATURE

External Temperature Calibration

DATA

DEFAULT

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM VALUE

MFR_TEMP_1_GAIN

0xF8

Sets the slope of the external temperature

sensor.

R/W Word

Y

CF

Y

0.995

0x3FAE

MFR_TEMP_1_OFFSET

0xF9

Sets the offset of the external temperature R/W Word

sensor.

Y

L11

C

Y

0.0

0x8000

MFR_TEMP_1_GAIN

The MFR_TEMP_1_GAIN command will modify the slope of the external temperature sensor to account for nonidealities

in the element and errors associated with the remote sensing of the temperature in the inductor.

This command has two data bytes and is formatted in 16-bit 2’s complement integer. The effective gain adjustment is

–14

N • 2 . The nominal value is 1.

MFR_TEMP_1_OFFSET

The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for noni-

dealities in the element and errors associated with the remote sensing of the temperature in the inductor.

This command has two data bytes and is formatted in Linear_5s_11s format.

External Temperature Limits

DATA

FORMAT

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED

UNITS

NVM

OT_FAULT_LIMIT

0x4F

0x51

0x53

Power stage overtemperature fault

R/W Word

Y

L11

C

Y

128

limit.

0xF200

OT_WARN_LIMIT

UT_FAULT_LIMIT

Power stage overtemperature

warning limit.

R/W Word

Y

C

Y

125

0xEBE8

Power stage undertemperature fault

limit.

–45

0xE530

OT_FAULT_LIMIT

The OT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees

Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this

limit has been exceeded.

This command has two data bytes and is formatted in Linear_5s_11s format.

OT_WARN_LIMIT

The OT_WARN_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees

Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if

this limit has been exceeded.

Rev. 0

105

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

In response to the OT_WARN_LIMIT being exceeded, the device:

• Sets the TEMPERATURE bit in the STATUS_BYTE

• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and

• Notifies the host by asserting ALERT pin, unless masked

This command has two data bytes and is formatted in Linear_5s_11s format.

UT_FAULT_LIMIT

TheUT_FAULT_LIMITcommandsetsthevalueofthepowerstagesensetemperaturemeasuredbytheADC,indegreesCelsius,

which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been

exceeded.

Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response

set to ignore to avoid ALERT being asserted.

This command has two data bytes and is formatted in Linear_5s_11s format.

TIMING

Timing—On Sequence/Ramp

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

TON_DELAY

0x60

Time from RUN and/or Operation on to

R/W Word

Y

L11

ms

Y

0.0

output rail turn-on.

0x8000

TON_RISE

0x61

Time from when the output starts to

rise until the output voltage reaches the

VOUT commanded value.

Maximum time from the start of

TON_RISE for VOUT to cross the

VOUT_UV_FAULT_LIMIT.

R/W Word

Y

ms

Y

3

0xC300

TON_MAX_FAULT_LIMIT

VOUT_TRANSITION_RATE

TON_DELAY

0x62

0x27

Y

L11

ms

5

0xCA80

Rate the output changes when VOUT

commanded to a new value.

V/ms

0.001

0x8042

The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output

voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of

270µs for TON_DELAY = 0 and an uncertainty of 50µs for all values of TON_DELAY.

This command has two data bytes and is formatted in Linear_5s_11s format.

TON_RISE

The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output

enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during

TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4664A digital slope will be bypassed and the output voltage

transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE

is equal to TON_RISE (in ms)/0.1ms with an uncertainty of 0.1ms.

This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. 0

106

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

TON_MAX_FAULT_LIMIT

The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power

up the output without reaching the output undervoltage fault limit.

A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.

The maximum limit is 83 seconds.

This command has two data bytes and is formatted in Linear_5s_11s format.

VOUT_TRANSITION_RATE

When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the

output voltage to change this command set the rate in V/ms at which the output voltage changes. The commanded

rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms.

This command has two data bytes and is formatted in Linear_5s_11s format.

Timing—Off Sequence/Ramp

DATA

FORMAT UNITS

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED

NVM

TOFF_DELAY

0x64

0x65

0x66

Time from RUN and/or Operation off to

the start of TOFF_FALL ramp.

Time from when the output starts to fall R/W Word

until the output reaches zero volts.

Maximum allowed time, after TOFF_FALL R/W Word

completed, for the unit to decay below

12.5%.

R/W Word

Y

L11

ms

Y

0.0

0x8000

TOFF_FALL

Y

3

0xC300

TOFF_MAX_WARN_LIMIT

0

0x8000

TOFF_DELAY

The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output

voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of

270µs for TOFF_DELAY = 0 and an uncertainty of 50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied

when a fault event occurs

This command has two data bytes and is formatted in Linear_5s_11s format.

TOFF_FALL

The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output voltage

is commanded to zero. It is the ramp time of the V

to high impedance state.

DAC. When the V

DAC is zero, the PWM output will be set

OUT

The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part

to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.

The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum

fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty

of 0.1ms.

In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by

the output capacitance and load current.

This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. 0

107

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

TOFF_MAX_WARN_LIMIT

The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds

12.5% of the programmed voltage before a warning is asserted. The output is considered off when the V

voltage

OUT

is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete.

A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage

indefinitely. Other than 0, values from 120ms to 524 seconds are valid.

This command has two data bytes and is formatted in Linear_5s_11s format.

Precondition for Restart

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

0xDC Minimum time the RUN pin is held

low by the LTM4664A.

TYPE

PAGED

FORMAT

UNITS

NVM

MFR_RESTART_ DELAY

R/W Word

Y

L11

ms

Y

150

0xF258

MFR_RESTART_DELAY

This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length

of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.

Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after

which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_

FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time,

set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_

RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the

output takes a long time to decay below 12.5% of the programmed value.

This command has two data bytes and is formatted in Linear_5s_11s format.

FAULT RESPONSE

Fault Responses All Faults

DATA

FORMAT

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED

UNITS

NVM

MFR_RETRY_ DELAY

0xDB

Retry interval during FAULT retry R/W Word

mode.

Y

L11

ms

Y

250

0xF3E8

MFR_RETRY_DELAY

This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified

intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has

been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments.

Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required

for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is

too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of

MFR_CHAN_CONFIG.

This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. 0

108

For more information www.analog.com

LTM4664A

PMBus COMMAND DETAILS

Fault Responses Input Voltage

DATA

PAGED FORMAT UNITS

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

NVM

VIN_OV_FAULT_RESPONSE

0x56

Action to be taken by the device when an R/W Byte

input supply overvoltage fault is detected.

Y

Reg

Y

0x80

VIN_OV_FAULT_RESPONSE

The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over-

voltage fault. The data byte is in the format given in Table 17.

The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Set the INPUT bit in the upper byte of the STATUS_WORD

• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and

• Notifies the host by asserting ALERT pin, unless masked

This command has one data byte.

Fault Responses Output Voltage

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

VOUT_OV_FAULT_RESPONSE

0x41

0x45

0x63

Action to be taken by the device when an R/W Byte

output overvoltage fault is detected.

Y

Reg

Y

0xB8

VOUT_UV_FAULT_RESPONSE

Action to be taken by the device when an R/W Byte

output undervoltage fault is detected.

Y

TON_MAX_FAULT_

RESPONSE

Action to be taken by the device when a

TON_MAX_FAULT event is detected.

R/W Byte

VOUT_OV_FAULT_RESPONSE

The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output

overvoltage fault. The data byte is in the format given in Table 13.

The device also:

• Sets the VOUT_OV bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command

• Notifies the host by asserting ALERT pin, unless masked

The only values recognized for this command are:

0x00–Part performs OV pull down only, or OV_PULLDOWN.

0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).

Rev. 0

109

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LTM4664A

PMBus COMMAND DETAILS

0xB8–The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until

it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault

condition causes the unit to shut down.

0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is com-

manded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN.

The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.

0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared

or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or

removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.

Any other value will result in a CML fault and the write will be ignored.

This command has one data byte.

Table 14. VOUT_OV_FAULT_RESPONSE Data Byte Contents

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

Part performs OV pull down only or OV_PULLDOWN

(i.e., turns off the top MOSFET and turns on lower MOSFET

while V is > VOUT_OV_FAULT).

For all values of bits [7:6], the LTM4664A:

• Sets the corresponding fault bit in the status commands and

• Notifies the host by asserting ALERT pin, unless masked.

OUT

01

The PMBus device continues operation for the delay time

specified by bits [2:0] and the delay time unit specified for that

particular fault. If the fault condition is still present at the end of

the delay time, the unit responds as programmed in the Retry

Setting (bits [5:3]).

The fault bit, once set, is cleared only when one or more of the

following events occurs:

• The device receives a CLEAR_FAULTS command.

10

11

The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3].

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

Not supported. Writing this value will generate a CML fault.

• Bias power is removed and reapplied to the LTM4664A.

Retry Setting

5:3

2:0

000

111

The unit does not attempt to restart. The output remains

disabled until the fault is cleared until the device is commanded

OFF bias power is removed.

The PMBus device attempts to restart continuously, without

limitation, until it is commanded OFF (by the RUN pin or

OPERATION command or both), bias power is removed, or

another fault condition causes the unit to shut down without

retry. Note: The retry interval is set by the MFR_RETRY_DELAY

command.

Delay Time

000-111 The delay time in 10µs increments. This delay time determines

how long the controller continues operating after a fault is

detected. Only valid for deglitched off state.

VOUT_UV_FAULT_RESPONSE

The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output

undervoltage fault. The data byte is in the format given in Table 8.

The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command

• Notifies the host by asserting ALERT pin, unless masked

Rev. 0

110

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LTM4664A

PMBus COMMAND DETAILS

The UV fault and warn are masked until the following criteria are achieved:

1) The TON_MAX_FAULT_LIMIT has been reached

2) The TON_DELAY sequence has completed

3) The TON_RISE sequence has completed

4) The VOUT_UV_FAULT_LIMIT threshold has been reached

5) The IOUT_OC_FAULT_LIMIT is not present

The UV fault and warn are masked whenever the channel is not active.

The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.

This command has one data byte.

Table 15. VOUT_UV_FAULT_RESPONSE Data Byte Contents

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

The PMBus device continues operation without interruption.

(Ignores the fault functionally)

For all values of bits [7:6], the LTM4664A:

• Sets the corresponding fault bit in the status commands and

• Notifies the host by asserting ALERT pin, unless masked.

01

The PMBus device continues operation for the delay time

specified by bits [2:0] and the delay time unit specified for

that particular fault. If the fault condition is still present at the

end of the delay time, the unit responds as programmed in the

Retry Setting (bits [5:3]).

The fault bit, once set, is cleared only when one or more of the

following events occurs:

• The device receives a CLEAR_FAULTS command.

10

11

The device shuts down (disables the output) and responds

according to the retry setting in bits [5:3].

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

Not supported. Writing this value will generate a CML fault.

• The device receives a RESTORE_USER_ALL command.

• The device receives a MFR_RESET command.

• The device supply power is cycled.

Retry Setting

5:3

2:0

000

111

The unit does not attempt to restart. The output remains

disabled until the fault is cleared until the device is commanded

OFF bias power is removed.

The PMBus device attempts to restart continuously, without

limitation, until it is commanded OFF (by the RUN pin or

OPERATION command or both), bias power is removed, or

another fault condition causes the unit to shut down without

retry. Note: The retry interval is set by the MFR_RETRY_DELAY

command.

Delay Time

000-111 The delay time in 10µs increments. This delay time determines

how long the controller continues operating after a fault is

detected. Only valid for deglitched off state.

Rev. 0

111

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LTM4664A

PMBus COMMAND DETAILS

TON_MAX_FAULT_RESPONSE

The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX

fault. The data byte is in the format given in Table 13.

The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and

• Notifies the host by asserting ALERT pin, unless masked

A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.

Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded.

This command has one data byte.

Fault Responses Output Current

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

IOUT_OC_FAULT_RESPONSE

0x47

Action to be taken by the device when an R/W Byte

output overcurrent fault is detected.

Y

Reg

Y

0x00

IOUT_OC_FAULT_RESPONSE

The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output

overcurrent fault. The data byte is in the format given in Table 9.

The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the IOUT_OC bit in the STATUS_BYTE

• Sets the IOUT bit in the STATUS_WORD

• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and

• Notifies the host by asserting ALERT pin, unless masked

This command has one data byte.

Rev. 0

112

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LTM4664A

PMBus COMMAND DETAILS

Table 16. IOUT_OC_FAULT_RESPONSE Data Byte Contents

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

The LTM4664A PSM continues to operate indefinitely while

maintaining the output current at the value set by

For all values of bits [7:6], the LTM4664A:

• Sets the corresponding fault bit in the status commands and

• Notifies the host by asserting ALERT pin, unless masked.

IOUT_OC_FAULT_LIMIT without regard to the output

voltage (known as constant-current or brick-wall limiting).

01

10

Not supported.

The fault bit, once set, is cleared only when one or more of the

following events occurs:

The LTM4664A PSM continues to operate, maintaining the

output current at the value set by IOUT_OC_FAULT_LIMIT

without regard to the output voltage, for the delay time set by

bits [2:0]. If the device is still operating in current limit at the

end of the delay time, the device responds as programmed by

the Retry Setting in bits [5:3].

• The device receives a CLEAR_FAULTS command.

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

11

The LTM4664A PSM shuts down immediately and responds as

programmed by the Retry Setting in bits [5:3].

• The device receives a RESTORE_USER_ALL command.

• The device receives a MFR_RESET command.

• The device supply power is cycled.

Retry Setting

5:3

2:0

000

111

The unit does not attempt to restart. The output remains

disabled until the fault is cleared by cycling the RUN pin or

removing bias power.

The device attempts to restart continuously, without limitation,

until it is commanded OFF (by the RUN pin or OPERATION

command or both), bias power is removed, or another fault

condition causes the unit to shut down. Note: The retry interval

is set by the MFR_RETRY_DELAY command.

Delay Time

000-111 The number of delay time units in 16ms increments. This

delay time is used to determine the amount of time a unit is

to continue operating after a fault is detected before shutting

down. Only valid for deglitched off response.

Fault Responses IC Temperature

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

MFR_OT_FAULT_RESPONSE

0xD6

Action to be taken by the device when an

internal overtemperature fault is detected.

R Byte

N

Reg

0xC0

MFR_OT_FAULT_RESPONSE

The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal

overtemperature fault. The data byte is in the format given in Table 12.

The LTM4664A also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the MFR bit in the STATUS_WORD, and

• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command

• Notifies the host by asserting ALERT pin, unless masked

This command has one data byte.

Rev. 0

113

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LTM4664A

PMBus COMMAND DETAILS

Table 17. Data Byte Contents MFR_OT_FAULT_RESPONSE

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

01

10

Not supported. Writing this value will generate a CML fault.

For all values of bits [7:6], the LTM4664A:

• Sets the corresponding fault bit in the status commands and

• Notifies the host by asserting ALERT pin, unless masked.

Not supported. Writing this value will generate a CML fault

The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3].

11

The device’s output is disabled while the fault is present.

Operation resumes and the output is enabled when the fault

condition no longer exists.

The fault bit, once set, is cleared only when one or more of the

following events occurs:

• The device receives a CLEAR_FAULTS command.

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

• Bias power is removed and reapplied to the LTM4664A.

Retry Setting

5:3

2:0

000

The unit does not attempt to restart. The output remains

disabled until the fault is cleared.

001-111 Not supported. Writing this value will generate CML fault.

Delay Time

XXX

Not supported. Value ignored

Fault Responses External Temperature

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

OT_FAULT_ RESPONSE

0x50

Action to be taken by the device when an

external overtemperature fault is detected,

R/W Byte

Y

Reg

Y

0xB8

UT_FAULT_ RESPONSE

0x54

Action to be taken by the device when an

external undertemperature fault is detected.

R/W Byte

Y

0xB8

OT_FAULT_RESPONSE

The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtem-

perature fault on the external temp sensors. The data byte is in the format given in Table 8.

The device also:

• Sets the TEMPERATURE bit in the STATUS_BYTE

• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and

• Notifies the host by asserting ALERT pin, unless masked

This command has one data byte.

UT_FAULT_RESPONSE

The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under-

temperature fault on the external temp sensors. The data byte is in the format given in Table 13.

The device also:

• Sets the TEMPERATURE bit in the STATUS_BYTE

• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and

• Notifies the host by asserting ALERT pin, unless masked

Rev. 0

114

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LTM4664A

PMBus COMMAND DETAILS

This condition is detected by the ADC so the response time may be up to t

.

CONVERT

This command has one data byte.

Table 18. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,

OT_FAULT_RESPONSE, UT_FAULT_RESPONSE

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

01

10

The PMBus device continues operation without interruption.

Not supported. Writing this value will generate a CML fault.

For all values of bits [7:6], the LTM4664A:

• Sets the corresponding fault bit in the status commands, and

• Notifies the host by asserting ALERT pin, unless masked.

The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3].

11

Not supported. Writing this value will generate a CML fault.

The fault bit, once set, is cleared only when one or more of the

following events occurs:

• The device receives a CLEAR_FAULTS command.

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

• The device receives a RESTORE_USER_ALL command.

• The device receives a MFR_RESET command.

• The device supply power is cycled.

Retry Setting

5:3

2:0

000

111

The unit does not attempt to restart. The output remains

disabled until the fault is cleared until the device is commanded

OFF bias power is removed.

The PMBus device attempts to restart continuously, without

limitation, until it is commanded OFF (by the RUN pin or

OPERATION command or both), bias power is removed, or

another fault condition causes the unit to shut down without

retry. Note: The retry interval is set by the MFR_RETRY_DELAY

command.

Delay Time

XXX

Not supported. Values ignored

FAULT SHARING

Fault Sharing Propagation

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

0xD2 Configuration that determines which faults

are propagated to the FAULT pins.

TYPE

PAGED FORMAT UNITS

NVM

MFR_FAULT_

PROPAGATE

R/W Word

Y

Reg

Y

0x6993

MFR_FAULT_PROPAGATE

The MFR_FAULT_PROPAGATE command enables the faults that can cause the FAULTn pin to assert low. The com-

mand is formatted as shown in Table 15. Faults can only be propagated to the FAULTn pin if they are programmed to

respond to faults.

This command has two data bytes.

Rev. 0

115

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LTM4664A

PMBus COMMAND DETAILS

Table 19. FAULTn Propagate Fault Configuration

The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output

channels. Others are specific to an output channel. They can also be used to share faults between channels.

BIT(S)

SYMBOL

OPERATION

B[15]

VOUT disabled while not decayed.

This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG is a zero. If the

channel is turned off, by toggling the RUN pin or commanding the part OFF, and then the RUN

is reasserted or the part is commanded back on before the output has decayed, VOUT will not

restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition if bit 15

is asserted.

B[14]

b[13]

Mfr_fault_propagate_short_CMD_cycle 0: No action

1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high

after sequence off.

t

OFF(MIN)

Mfr_fault_propagate_ton_max_fault

0: No action if a TON_MAX_FAULT fault is asserted

1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted

FAULT0 is associated with page 0 TON_MAX_FAULT faults

FAULT1 is associated with page 1 TON_MAX_FAULT faults

b[12]

b[11]

Reserved

Mfr_fault0_propagate_int_ot,

Mfr_fault1_propagate_int_ot

Reserved

0: No action if the MFR_OT_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted

b[10]

b[9]

Reserved

b[8]

Mfr_fault0_propagate_ut,

Mfr_fault1_propagate_ut

0: No action if the UT_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 UT faults

FAULT1 is associated with page 1 UT faults

b[7]

Mfr_fault0_propagate_ot,

Mfr_fault1_propagate_ot

0: No action if the OT_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 OT faults

FAULT1 is associated with page 1 OT faults

b[6]

b[5]

b[4]

Reserved

Mfr_fault0_propagate_input_ov,

Mfr_fault1_propagate_input_ov

Reserved

0: No action if the VIN_OV_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted

b[3]

b[2]

Mfr_fault0_propagate_iout_oc,

Mfr_fault1_propagate_iout_oc

0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 OC faults

FAULT1 is associated with page 1 OC faults

b[1]

b[0]

Mfr_fault0_propagate_vout_uv,

Mfr_fault1_propagate_vout_uv

0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 UV faults

FAULT1 is associated with page 1 UV faults

Mfr_fault0_propagate_vout_ov,

Mfr_fault1_propagate_vout_ov

0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 OV faults

FAULT1 is associated with page 1 OV faults

Rev. 0

116

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LTM4664A

PMBus COMMAND DETAILS

Fault Sharing Response

DATA

PAGED FORMAT UNITS

Reg

DEFAULT

COMMAND NAME

CMD CODE DESCRIPTION

0xD5 Action to be taken by the device when the

FAULT pin is asserted low.

TYPE

R/W Byte

NVM

Y

VALUE

MFR_FAULT_RESPONSE

Y

0xC0

MFR_FAULT_RESPONSE

The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAULTn pin

being pulled low by an external source.

Supported Values:

VALUE

MEANING

0xC0

FAULT_INHIBIT The LTM4664A will three-state the output in response to the FAULT pin pulled low.

FAULT_IGNORE The LTM4664A continues operation without interruption.

0x00

The device also:

• Sets the MFR Bit in the STATUS_WORD.

• Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULTn Is Being Pulled Low

• Notifies the Host by Asserting ALERT, Unless Masked

This command has one data byte.

SCRATCHPAD

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

USER_DATA_00

0xB0

OEM reserved. Typically used for part

serialization.

R/W Word

N

Reg

Y

NA

USER_DATA_01

USER_DATA_02

0xB1

0xB2

Manufacturer reserved for LTpowerPlay.

R/W Word

Y

N

Reg

Y

NA

OEM reserved. Typically used for part

serialization.

USER_DATA_03

USER_DATA_04

0xB3

0xB4

A NVM word available for the user.

R/W Word

Y

N

Reg

Y

0x0000

Rev. 0

117

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LTM4664A

PMBus COMMAND DETAILS

USER_DATA_00 through USER_DATA_04

These commands are non-volatile memory locations for customer storage. The customer has the option to write any

value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of

these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable

inventory control and incompatibility with these products.

These commands have 2 data bytes and are in register format.

IDENTIFICATION

DATA

FORMAT UNITS

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED

NVM

PMBus_REVISION

0x98

PMBus revision supported by this device.

R Byte

N

Reg

FS

0x22

Current revision is 1.2.

CAPABILITY

0x19

Summary of PMBus optional communication

protocols supported by this device.

R Byte

N

0xB0

MFR_ID

0x99

0x9A

0xE7

The manufacturer ID of the LTM4664A in ASCII.

Manufacturer part number in ASCII.

R String

R Word

N

ASC

Reg

LTC

MFR_MODEL

MFR_SPECIAL_ID

LTM4664

0x020X

Manufacturer code representing the LTM4664A.

PMBus_REVISION

The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4664A

is PMBus Version 1.2 compliant in both Part I and Part II.

This read-only command has one data byte.

CAPABILITY

This command provides a way for a host system to determine some key capabilities of a PMBus device.

The LTM4664A supports packet error checking, 400kHz bus speeds, and ALERT pin.

This read-only command has one data byte.

MFR_ID

The MFR_ID command indicates the manufacturer ID of the LTM4664A using ASCII characters.

This read-only command is in block format.

MFR_MODEL

The MFR_MODEL command indicates the manufacturer’s part number of the LTM4664A using ASCII characters.

This read-only command is in block format.

MFR_SPECIAL_ID

The 16-bit word representing the part name and revision. 0x4C denotes the part is an LTM4664A, XX is adjustable by

the manufacturer.

This read-only command has two data bytes.

Rev. 0

118

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LTM4664A

PMBus COMMAND DETAILS

FAULT WARNING AND STATUS

DEFAULT

COMMAND NAME

CLEAR_FAULTS

SMBALERT_MASK

CMD CODE DESCRIPTION

TYPE

PAGED

N

Y

FORMAT UNITS

NVM

VALUE

0x03

0x1B

Clear any fault bits that have been set. Send Byte

Mask activity.

NA

See CMD

Details

Block R/W

Reg

Y

MFR_CLEAR_PEAKS

STATUS_BYTE

0xE3

0x78

Clears all peak values.

One byte summary of the unit’s fault

condition.

Two byte summary of the unit’s fault

condition.

Output voltage fault and warning

status.

Output current fault and warning

status.

Input supply fault and warning status.

External temperature fault and warning R/W Byte

status for READ_TEMERATURE_1.

Send Byte

R/W Byte

Y

NA

Reg

STATUS_WORD

STATUS_VOUT

STATUS_IOUT

0x79

0x7A

0x7B

R/W Word

R/W Byte

Y

NA

STATUS_INPUT

STATUS_ TEMPERATURE

0x7C

0x7D

N

Y

Reg

NA

STATUS_CML

0x7E

0x80

Communication and memory fault and R/W Byte

warning status.

N

Y

Reg

NA

STATUS_MFR_ SPECIFIC

Manufacturer specific fault and state

information.

R/W Byte

MFR_PADS

MFR_COMMON

0xE5

0xEF

Digital status of the I/O pads.

Manufacturer status bits that are

common across multiple LTC chips.

R Word

R Byte

N

Reg

NA

CLEAR_FAULTS

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all

status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output

if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain

set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault

occurs within that time frame it may be cleared before the status register is set.

This write-only command has no data bytes.

The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut

down for a fault condition are restarted when:

• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin

and OPERATION command, to turn off and then to turn back on, or

• MFR_RESET command is issued.

• Bias power is removed and reapplied to the integrated circuit

SMBALERT_MASK

The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they

are asserted.

Figure 33 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in

the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code

is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning

Rev. 0

119

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LTM4664A

PMBus COMMAND DETAILS

would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE

bits would continue to assert ALERT if set.

Figure 50 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state

of any supported status register, again without PEC.

SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS. Factory

default masking for applicable status registers is shown below. Providing an unsupported command code to SMBALERT_

MASK will generate a CML for Invalid/Unsupported Data.

SMBALERT_MASK Default Setting: (Refer Also to Figure 2)

STATUS RESISTER

ALERT Mask Value MASKED BITS

STATUS_VOUT

0x00

0x11

None

STATUS_IOUT

None

STATUS_TEMPERATURE

STATUS_CML

None

STATUS_INPUT

None

STATUS_MFR_SPECIFIC

Bit 4 (internal PLL unlocked), bit 0 (FAULT pulled low by external device)

1

7

1

8

1

8

1

8

1

SLAVE

ADDRESS

SMBALERT_MASK

COMMAND CODE

STATUS_x

COMMAND CODE

S

W

A

MASK BYTE

A

P

4664A F56

Figure 53. Example of Writing SMBALERT_MASK

1

7

1

8

1

8

1

8

1

SLAVE

ADDRESS

SMBALERT_MASK

COMMAND CODE

BLOCK COUNT

(= 1)

STATUS_x

COMMAND CODE

S

W

A

…

1

7

1

8

1

8

1

SLAVE

ADDRESS

BLOCK COUNT

(= 1)

Sr

R

A

MASK BYTE

NA

P

4664A F57

Figure 54. Example of Reading SMBALERT_MASK

MFR_CLEAR_PEAKS

The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the

MFR_*_PEAK data values.

This write-only command has no data bytes.

STATUS_BYTE

The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the

lower byte of the status word.

Rev. 0

120

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LTM4664A

PMBus COMMAND DETAILS

STATUS_BYTE Message Contents:

BIT

7*

6

STATUS BIT NAME

MEANING

BUSY

OFF

A fault was declared because the LTM4664A was unable to respond.

This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not

being enabled.

5

4

VOUT_OV

IOUT_OC

VIN_UV

An output overvoltage fault has occurred.

An output overcurrent fault has occurred.

Not supported (LTM4664A returns 0).

3

2

TEMPERATURE

CML

A temperature fault or warning has occurred.

A communications, memory or logic fault has occurred.

1

0*

NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.

*ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_

FAULTS command.

This command has one data byte.

STATUS_WORD

The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the

STATUS_WORD is the same as the STATUS_BYTE command.

STATUS_WORD High Byte Message Contents:

BIT

15

14

13

12

11

10

9

STATUS BIT NAME

MEANING

V

An output voltage fault or warning has occurred.

An output current fault or warning has occurred.

An input voltage fault or warning has occurred.

A fault or warning specific to the LTM4664A has occurred.

The POWER_GOOD state is false if this bit is set.

Not supported (LTM4664A returns 0).

OUT

I

INPUT

MFR_SPECIFIC

POWER_GOOD#

FANS

OTHER

8

UNKNOWN

If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted.

This command has two data bytes.

STATUS_VOUT

The STATUS_VOUT command returns one byte of V

status information.

OUT

STATUS_VOUT Message Contents:

BIT

MEANING

7

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

overvoltage fault.

overvoltage warning.

undervoltage warning.

undervoltage fault.

max warning.

6

5

4

3

2

TON max fault.

1

TOFF max fault.

0

Not supported (LTM4664A returns 0).

Rev. 0

121

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LTM4664A

PMBus COMMAND DETAILS

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

Any supported fault bit in this command will initiate an ALERT event.

This command has one data byte.

STATUS_IOUT

The STATUS_IOUT command returns one byte of I

status information.

OUT

STATUS_IOUT Message Contents:

BIT

MEANING

7

I

overcurrent fault.

OUT

6

Not supported (LTM4664A returns 0).

I overcurrent warning.

OUT

5

4:0

Not supported (LTM4664A returns 0).

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

STATUS_INPUT

The STATUS_INPUT command returns one byte of V (VINS3_C1) status information.

IN

STATUS_INPUT Message Contents:

BIT

MEANING

7

V

IN

overvoltage fault.

6

Not supported (LTM4664A returns 0).

V undervoltage warning.

IN

5

4

Not supported (LTM4664A returns 0).

3

Unit off for insufficient V .

IN

2

Not supported (LTM4664A returns 0).

1

I overcurrent warning.

IN

0

Not supported (LTM4664A returns 0).

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not

generate an ALERT even if it is set. This command has one data byte.

Rev. 0

122

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LTM4664A

PMBus COMMAND DETAILS

STATUS_TEMPERATURE

The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged

command and is related to the respective READ_TEMPERATURE_1 value.

STATUS_TEMPERATURE Message Contents:

BIT

MEANING

7

External overtemperature fault.

External overtemperature warning.

Not supported (LTM4664A returns 0).

External undertemperature fault.

Not supported (LTM4664A returns 0).

6

5

4

3:0

.

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

This command has one data byte.

STATUS_CML

The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.

STATUS_CML Message Contents:

BIT

MEANING

7

Invalid or unsupported command received.

Invalid or unsupported data received.

Packet error check failed.

6

5

4

Memory fault detected.

3

Processor fault detected.

2

Reserved (LTM4664A returns 0).

Other communication fault.

Other memory or logic fault.

1

0

If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued

operation of the part is not recommended if these bits are continuously set.

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

Any supported fault bit in this command will initiate an ALERT event.

This command has one data byte.

Rev. 0

123

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LTM4664A

PMBus COMMAND DETAILS

STATUS_MFR_SPECIFIC

The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.

The format for this byte is:

BIT MEANING

7

6

5

4

3

2

1

0

Internal Temperature Fault Limit Exceeded.

Internal Temperature Warn Limit Exceeded.

Factory Trim Area NVM CRC Fault.

PLL is Unlocked

Fault Log Present

V

DD33

UV or OV Fault

Short-cycle Event Detected

FAULT Pin Asserted Low by External Device

If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted.

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared

by issuing the MFR_FAULT_LOG_CLEAR command.

Any supported fault bit in this command will initiate an ALERT event.

This command has one data byte.

MFR_PADS

This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit

assignments of this command are as follows:

BIT ASSIGNED DIGITAL PIN

15

14

V

OV Fault

UV Fault

DD33

13 Reserved

12 Reserved

11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation

10 SYNC clocked by external device (when LTM4664A configured to drive SYNC pin)

9

8

7

6

5

4

3

2

1

0

Channel 1 Power Good

Channel 0 Power Good

LTM4664A Driving RUN1 Low

LTM4664A Driving RUN0 Low

RUN1 Pin State

RUN0 Pin State

LTM4664A Driving FAULT1 Low

LTM4664A Driving FAULT0 Low

FAULT1 Pin State

FAULT0 Pin State

A 1 indicates the condition is true.

This read-only command has two data bytes.

Rev. 0

124

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LTM4664A

PMBus COMMAND DETAILS

MFR_COMMON

The MFR_COMMON command contains bits that are common to all LTC digital power and telemetry products.

BIT

7

MEANING

Chip Not Driving ALERT Low

LTM4664A Not Busy

Calculations Not Pending

LTM4664A Outputs Not in Transition

NVM Initialized

6

5

4

3

2

Reserved

1

SHARE_CLK Timeout

WP Pin Status

0

This read-only command has one data byte.

MFR_INFO

The MFR_INFO command contains additional status bits that are LTC3884-specific and may be common to multiple

ADI PSM products.

MFR_INFO Data Contents:

BIT

15:5

4

MEANING

Reserved.

EEPROM ECC status.

0: Corrections made in the EEPROM user space.

1: No corrections made in the EEPROM user space.

Reserved

3:0

EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM

bulk read operation. This read-only command has two data bytes.

Rev. 0

125

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LTM4664A

PMBus COMMAND DETAILS

TELEMETRY

CMD

DEFAULT

VALUE

COMMAND NAME

READ_VIN

READ_IIN

READ_VOUT

READ_IOUT

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

0x88 Measured input supply voltage.

0x89 Measured input supply current.

0x8B Measured output voltage.

0x8C Measured output current.

0x8D Power stage diode junction temperature. This

is the value used for all temperature related

processing, including MFR_IOUT_CAL_GAIN.

R Word

N

Y

L11

L16

L11

V

A

V

A

C

NA

READ_TEMPERATURE_1

READ_TEMPERATURE_2

0x8E Power stage junction temperature. Does not

affect any other commands.

R Word

N

L11

C

NA

READ_FREQUENCY

READ_POUT

READ_PIN

MFR_PIN_ACCURACY

MFR_IOUT_PEAK

0x95 Measured PWM switching frequency.

0x96 Calculated output power.

0x97 Calculated input power.

0xAC Returns the accuracy of the READ_PIN command R Byte

0xD7 Report the maximum measured value of

READ_IOUT since last MFR_CLEAR_PEAKS.

0xDD Maximum measured value of READ_VOUT

since last MFR_CLEAR_PEAKS.

0xDE Maximum measured value of READ_VIN since

last MFR_CLEAR_PEAKS.

R Word

Y

N

Y

L11

Hz

W

%

A

NA

5.0%

NA

R Word

L11

L16

L11

MFR_VOUT_PEAK

MFR_VIN_PEAK

Y

N

Y

V

C

NA

MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external

Temperature (READ_TEMPERATURE_1) since

last MFR_CLEAR_PEAKS.

MFR_READ_IIN_PEAK

0xE1 Maximum measured value of READ_IIN

command since last MFR_CLEAR_PEAKS.

R Word

N

L11

A

NA

MFR_READ_ICHIP

0xE4 Measured current used by the LTM4664A.

R Word

N

L11

A

C

NA

MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last

MFR_CLEAR_PEAKS.

MFR_ADC_CONTROL

0xD8 ADC telemetry parameter selected for repeated R/W Byte

fast ADC read back.

N

Reg

NA

Rev. 0

126

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LTM4664A

PMBus COMMAND DETAILS

READ_VIN

The READ_VIN command returns the measured V pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This

IN

compensates for the IR voltage drop across the V filter element due to the supply current of the LTM4664A.

IN

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_VOUT

The READ_VOUT command returns the measured output voltage by the VOUT_MODE command.

This read-only command has two data bytes and is formatted in Linear_16u format.

READ_IIN

The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor

(see also MFR_IIN_CAL_GAIN).

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_IOUT

The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:

a) the differential voltage measured across the I

b) the MFR_IOUT_CAL_GAIN value

pins

SENSE

c) the MFR_IOUT_CAL_GAIN_TC value, and

d) READ_TEMPERATURE_1 value

e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_TEMPERATURE_1

The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the power stage sense element.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_TEMPERATURE_2

The READ_TEMPERATURE_2 command returns the LTM4664A’s die temperature, in degrees Celsius, of the internal

sense element.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_FREQUENCY

The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz.

This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.

READ_POUT

The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on

the most recent correlated output voltage and current reading.

This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.

Rev. 0

127

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LTM4664A

PMBus COMMAND DETAILS

READ_PIN

The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the

most recent input voltage and current reading.

This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.

MFR_PIN_ACCURACY

The MFR_PIN_ACCURACY command returns the accuracy, in percent, of the value returned by the READ_PIN command.

There is one data byte. The value is 0.1% per bit which gives a range of 0.0% to 25.5%.

This read-only command has one data byte and is formatted as an unsigned integer.

MFR_IOUT_PEAK

The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

MFR_VOUT_PEAK

The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_16u format.

MFR_VIN_PEAK

The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

MFR_TEMPERATURE_1_PEAK

The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the

READ_TEMPERATURE_1 measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

MFR_READ_IIN_PEAK

The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This command has two data bytes and is formatted in Linear_5s_11s format.

MFR_READ_ICHIP

The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTM4664A.

This command has two data bytes and is formatted in Linear_5s_11s format.

Rev. 0

128

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LTM4664A

PMBus COMMAND DETAILS

MFR_TEMPERATURE_2_PEAK

The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the

READ_TEMPERATURE_2 measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

MFR_ADC_CONTROL

The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs

the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of t

.

CONVERT

The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms.

This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions

may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard

telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be

commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command

back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all

warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage

servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.

COMMANDED VALUE

TELEMETRY COMMAND NAME

DESCRIPTION

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

Reserved

Channel 1 external temperature

Reserved

Channel 1 measured output current

Channel 1 measured output voltage

Channel 0 external temperature

Reserved

Channel 0 measured output current

Channel 0 measured output voltage

Internal junction temperature

Measured input supply current

READ_TEMPERATURE_1

READ_IOUT

READ_VOUT

READ_TEMPERATURE_1

READ_IOUT

READ_VOUT

READ_TEMPERATURE_2

READ_IIN

MFR_READ_ICHIP

Measured supply current of the

LTM4664A

0x01

0x00

READ_VIN

Measured input supply voltage

Standard ADC Round Robin Telemetry

If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault.

CML faults will continue to be issued by the LTM4664A until a valid command value is entered. The accuracy of the

measured input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round

robin telemetry.

This write-only command has 1 data byte and is formatted in register format.

Rev. 0

129

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LTM4664A

PMBus COMMAND DETAILS

NVM MEMORY COMMANDS

Store/Restore

CMD

DEFAULT

VALUE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGED

FORMAT

UNITS

NVM

STORE_USER_ALL

0x15

0x16

0xF0

Store user operating memory to

EEPROM.

Send Byte

N

NA

RESTORE_USER_ALL

Restore user operating memory from Send Byte

EEPROM.

N

MFR_COMPARE_USER_ALL

Compares current command contents Send Byte

with NVM.

STORE_USER_ALL

The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating

Memory to the matching locations in the non-volatile User NVM memory.

Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data retention

of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled.

The command is re-enabled when the IC temperature drops below 125°C.

Communication with the LTM4664A and programming of the NVM can be initiated when EXTV or VDD33 is available

CC

and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B

followed by 0xC4. The LTM4664A will now communicate normally, and the project file can be updated. To write the

updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be

issued to allow the PWM to be enabled and valid ADCs to be read.

This write-only command has no data bytes.

RESTORE_USER_ALL

The RESTORE_USER_ALL command instructs the LTM4664A to copy the contents of the non-volatile User memory

to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value

retrieved from the User commands. The LTM4664A ensures both channels are off, loads the operating memory from

the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both

PWM channels if applicable.

STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds

130°C and are not re-enabled until the die temperature drops below 125°C.

This write-only command has no data bytes.

MFR_COMPARE_USER_ALL

The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with

what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.

This write-only command has no data bytes.

Rev. 0

130

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LTM4664A

PMBus COMMAND DETAILS

Fault Logging

DATA

PAGED FORMAT UNITS NVM

DEFAULT

VALUE

NA

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

MFR_FAULT_LOG

0xEE

0xEA

Fault log data bytes.

R Block

N

CF

Y

MFR_FAULT_LOG_ STORE

Command a transfer of the fault log from RAM Send Byte

to EEPROM.

NA

MFR_FAULT_LOG_CLEAR

0xEC

Initialize the EEPROM block reserved for fault

logging.

Send Byte

N

NA

MFR_FAULT_LOG

The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occurrence

since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in non-volatile

memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command are listed

in Table 15. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the command will return

a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147 bytes long. If a fault

occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data.

NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.

This read-only command is in block format.

MFR_FAULT_LOG_STORE

The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event

occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in the

MFR_CONFIG_ALL command.

If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature

drops below 125°C.

This write-only command has no data bytes.

Rev. 0

131

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LTM4664A

PMBus COMMAND DETAILS

Table 20. Fault Logging

This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.

Data Format Definitions

LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1

LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only

BYTE = 8 bits interpreted per definition of this command

DATA

FORMAT BYTE NUM BLOCK READ COMMAND

DATA

BITS

Block Length

BYTE

147

The MFR_FAULT_LOG command is a fixed length of 147 bytes

The block length will be zero if a data log event has not been captured

HEADER INFORMATION

Fault Log Preface

[7:0]

[15:8]

[7:0]

ASC

Reg

0

1

2

Returns LTxx beginning at byte 0 if a partial or complete fault log exists.

Word xx is a factory identifier that may vary part to part.

3

Fault Source

MFR_REAL_TIME

[7:0]

Reg

4

5

Refer to Table 16.

48 bit share-clock counter value when fault occurred (200µs resolution).

[15:8]

[23:16]

[31:24]

[39:32]

[47:40]

[15:8]

6

7

8

9

10

11

MFR_VOUT_PEAK (PAGE 0)

MFR_VOUT_PEAK (PAGE 1)

MFR_IOUT_PEAK (PAGE 0)

MFR_IOUT_PEAK (PAGE 1)

L16

L11

Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS

command.

[7:0]

[15:8]

12

13

Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS

command.

[7:0]

[15:8]

14

15

Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS

command.

[7:0]

[15:8]

16

17

Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS

command.

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

18

19

20

21

22

23

24

25

26

MFR_VIN_PEAK

L11

Peak READ_VIN since last power-on or CLEAR_PEAKS command.

External temperature sensor 0 during last event.

READ_TEMPERATURE1 (PAGE 0)

READ_TEMPERATURE1 (PAGE 1)

READ_TEMPERATURE2

External temperature sensor 1 during last event.

LTM4664A die temperature sensor during last event.

Rev. 0

132

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LTM4664A

PMBus COMMAND DETAILS

CYCLICAL DATA

EVENT n

Event “n” represents one complete cycle of ADC reads through the MUX

at time of fault. Example: If the fault occurs when the ADC is processing

step 15, it will continue to take readings through step 25 and then store

the header and all 6 event pages to EEPROM

(Data at Which Fault Occurred; Most Recent Data)

READ_VOUT (PAGE 0)

READ_VOUT (PAGE 1)

READ_IOUT (PAGE 0)

READ_IOUT (PAGE 1)

READ_VIN

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

LIN 16

LIN 11

BYTE

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

READ_IIN

STATUS_VOUT (PAGE 0)

STATUS_VOUT (PAGE 1)

STATUS_WORD (PAGE 0)

BYTE

[15:8]

[7:0]

[15:8]

[7:0]

WORD

BYTE

STATUS_WORD (PAGE 1)

STATUS_MFR_SPECIFIC (PAGE 0)

STATUS_MFR_SPECIFIC (PAGE 1)

BYTE

EVENT n-1

(data measured before fault was detected)

READ_VOUT (PAGE 0)

READ_VOUT (PAGE 1)

READ_IOUT (PAGE 0)

READ_IOUT (PAGE 1)

READ_VIN

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

LIN 16

LIN 11

BYTE

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

READ_IIN

STATUS_VOUT (PAGE 0)

STATUS_VOUT (PAGE 1)

STATUS_WORD (PAGE 0)

BYTE

[15:8]

[7:0]

[15:8]

[7:0]

WORD

BYTE

STATUS_WORD (PAGE 1)

STATUS_MFR_SPECIFIC (PAGE 0)

STATUS_MFR_SPECIFIC (PAGE 1)

BYTE

Rev. 0

133

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LTM4664A

PMBus COMMAND DETAILS

EVENT n-5

(Oldest Recorded Data)

READ_VOUT (PAGE 0)

READ_VOUT (PAGE 1)

READ_IOUT (PAGE 0)

READ_IOUT (PAGE 1)

READ_VIN

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

LIN 16

LIN 11

BYTE

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

READ_IIN

STATUS_VOUT (PAGE 0)

STATUS_VOUT (PAGE 1)

STATUS_WORD (PAGE 0)

BYTE

[15:8]

[7:0]

[15:8]

[7:0]

WORD

BYTE

STATUS_WORD (PAGE 1)

STATUS_MFR_SPECIFIC (PAGE 0)

STATUS_MFR_SPECIFIC (PAGE 1)

BYTE

Table 21. Explanation of Position_Fault Values

POSITION_FAULT VALUE

SOURCE OF FAULT LOG

MFR_FAULT_LOG_STORE

TON_MAX_FAULT

VOUT_OV_FAULT

0xFF

0x00

0x01

0x02

0x03

0x05

0x06

0x07

0x0A

VOUT_UV_FAULT

IOUT_OC_FAULT

TEMP_OT_FAULT

TEMP_UT_FAULT

VIN_OV_FAULT

MFR_TEMP_2_OT_FAULT

Rev. 0

134

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LTM4664A

PMBus COMMAND DETAILS

MFR_INFO

Contact the factory for details.

MFR_IOUT_CAL_GAIN

Contact the factory for details.

MFR_FAULT_LOG_CLEAR

The MFR_FAULT_LOG_CLEAR command will erase the

fault log file stored values. It will also clear bit 3 in the

STATUS_MFR_SPECIFIC command. After a clear is

issued, the status can take up to 8ms to clear.

This write-only command is send bytes.

Block Memory Write/Read

DATA

PAGED FORMAT UNITS NVM

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

MFR_EE_UNLOCK

0xBD

0xBE

0xBF

Unlock user EEPROM for access by MFR_EE_ERASE

R/W Byte

N

Reg

NA

and MFR_EE_DATA commands.

MFR_EE_ERASE

MFR_EE_DATA

Initialize user EEPROM for bulk programming by

MFR_EE_DATA.

R/W Byte

NA

Data transferred to and from EEPROM using

sequential PMBus word reads or writes. Supports bulk

programming.

R/W

Word

All the NVM commands are disabled if the die temperature

exceeds 130°C. NVM commands are re-enabled when the

die temperature drops below 125°C.

MFR_EE_xxxx

The MFR_EE_xxxx commands facilitate bulk program-

ming of the LTM4664A internal EEPROM. Contact the

factory for details.

Rev. 0

135

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LTM4664A

PACKAGE DESCRIPTION

Rev. 0

136

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LTM4664A

PACKAGE DESCRIPTION

Z

/ / b b b

Z

f f f / /

aaa

Z

7 . 5 0 0

6 . 5 0 0

5 . 5 0 0

4 . 5 0 0

3 . 5 0 0

2 . 5 0 0

1 . 5 0 0

0 . 5 0 0

0 . 0 0 0 0

0 . 5 0 0

1 . 5 0 0

2 . 5 0 0

3 . 5 0 0

4 . 5 0 0

5 . 5 0 0

6 . 5 0 0

7 . 5 0 0

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

137

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTM4664A

TYPICAL APPLICATIONS

DESIGN RESOURCES

SUBJECT

DESCRIPTION

µModule Design and Manufacturing Resources Design:

Manufacturing:

• Selector Guides

• Quick Start Guide

• Demo Boards and Gerber Files

• Free Simulation Tools

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

Digital Power System Management

Analog Devices’ family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LTM4664

LTM4681

LTM4700

LTM4680

LTM4678

LTM4686

54V Dual 25A or Single 50A µModule Regulator with PMBus Interface 30V ≤ V ≤ 58V, 0.5V ≤ V ≤ 1.5V. 16mm × 16mm × 7.72mm BGA

IN IN OUT

Quad 31.25A to Single 125A µModule Regulator with PMBus Interface Quad 31.25A to Single 125A µModule Regulator with PMBus Interface

Dual 50A or Single 100A µModule Regulator with PMBus Interface 4.5V ≤ V ≤ 16V, 0.5V ≤ V ≤ 1.8V. 15mm × 22mm × 7.82mm BGA

IN

OUT

Dual 30A or Single 60A µModule Regulator with PMBus Interface

Dual 25A or Single 50A µModule Regulator with PMBus Interface

4.5V ≤ V ≤ 16V, 0.5V ≤ V ≤ 3.3V. 16mm × 16mm × 7.72mm BGA

IN OUT

4.5V ≤ V ≤ 16V, 0.5V ≤ V ≤ 3.3V. 16mm × 16mm × 5.86mm BGA

IN

OUT

Ultrathin Package, Dual 10A or Single 20A µModule Regulator with 4.5V ≤ V ≤ 17V, 0.5V ≤ V

≤ 2.75V. 11.9mm × 16mm ×

IN

OUT

PMBus Interface

1.82mm LGA

LTM4650

Dual 50A or Single 100A µModule Regulator

Dual 50A or Single 100A µModule Regulator with High V

4.5V ≤ V ≤ 15V, 0.6V ≤ V ≤ 1.8V. 16mm × 16mm × 5.01mm BGA

IN

OUT

LTM4650A

Range 4.5V ≤ V ≤ 16V, 0.6V ≤ V

≤ 5.5V. 16mm × 16mm × 5.01mm

OUT

IN

OUT

BGA. 16mm × 16mm × 4.41mm LGA.

LTC^®2977

LTC2974

Octal Digital Power Supply Manager with EEPROM

Quad Digital Power Supply Manager with EEPROM

I²C/PMBus Interface, Configuration EEPROM, Fault Logging,

16-Bit ADC with 0.25% TUE, 3.3V to 15V Operation

I²C/PMBus Interface, Configuration EEPROM, Fault Logging, Per

Channel Voltage, Current and Temperature Measurements

Rev. 0

12/21

www.analog.com

138

 ANALOG DEVICES, INC. 2021

For more information www.analog.com


型号：	LTM4650
厂家：	ADI
描述：	30V to 58V Input, Dual 30A, Single 60A Î¼Module Regulator with Digital Power System Management
文件：	总138页 (文件大小：6976K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4650 [ADI]

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