LTM4655IY [ADI]
EN55022B Compliant 40V, Dual 4A or Single 8A Step-Down or 50W Inverting μModule Regulator;
| 型号： | LTM4655IY |
| 厂家： | 
ADI |
| 描述： | EN55022B Compliant 40V, Dual 4A or Single 8A Step-Down or 50W Inverting μModule Regulator |
| 文件： | 总54页 (文件大小：3380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4655
EN55022B Compliant 40V, Dual 4A or Single 8A Step-
Down or 50W Inverting µModule Regulator
FEATURES
DESCRIPTION
ꢂulꢆ 4AꢃSinꢈꢆe 8A Low EμI Switch μoꢅe Power Suꢁꢁꢆy
EN55011 Cꢆlss B Comꢁꢆilnt
Two Fuꢆꢆy Inꢅeꢁenꢅent Chlnneꢆs, Elch
Confiꢈurlbꢆe for Positive or Neꢈltive ꢀutꢁut
2oꢆtlꢈe Poꢆlrity
ꢀutꢁut 2oꢆtlꢈe ꢇlnꢈe: 0.52 ≤ |2
Wiꢅe Inꢁut 2oꢆtlꢈe ꢇlnꢈe: Uꢁ to 402
The LTM®4655 is an ultralow noise 40V, dual 4A or single
8A DC/DC μModule® regulator designed to meet the radi-
ated emissions requirements of EN55022. Its channels
are fully independent, parallelable and capable of deliver-
ing positive or negative output polarity. Conducted emis-
sion requirements can be met by adding standard filter
components. Included in the package are the switching
controllers, power MOSFETs, inductors, filters and sup-
port components. A 5V, 25mA LDO and clock generator
enable phase interleaving of the power switching stages,
for improved EMC performance.
n
n
n
+
–
n
n
– 2
| ≤ 16.52
ꢀUTn
ꢀUTn
n
3.±2 or 3.62 Stlrt-Uꢁ, Confiꢈurltion-ꢂeꢁenꢅent
±±.6ꢊ7 Totlꢆ ꢂC ꢀutꢁut 2oꢆtlꢈe Error ꢀver Line,
Lolꢅ lnꢅ Temꢁerlture
n
n
n
n
n
n
n
n
Anlꢆoꢈ ꢀutꢁut Current Inꢅicltor (Positive-2
Lꢂꢀ : 52 Fixeꢅ, 15mA Clꢁlbꢆe Lꢂꢀ
ꢀnꢆy)
ꢀUT
+
ꢀUT
The LTM4655 can regulate positive VOUTn voltages
Plrlꢆꢆeꢆlbꢆe with LTμ465±ꢃLTμ4653
between 0.5V and 26.5V from a 3.1V to 40V input. The
Constant-Frequency Current Mode Control
–
LTM4655 can regulate negative V
voltages between
OUTn
Power Good Indicators and Programmable Soft-Start
Overcurrent and Overtemperature Protection
16mm × 16mm × 5.01mm BGA Package
–0.5V and –26.5V from a maximum input range of 3.6V to
–
40V, with the span from V to V
not to exceed 40V. A
switching frequency range of 250OkUHTznto 3MHz is supported.
INn
APPLICATIONS
The LTM4655 is offered in a 16mm × 16mm × 5.01mm
BGA package with SnPb or RoHS compliant terminal finish.
n
Automated Test and Measurement
n
Avionics and Industrial Control Systems
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 5481178, 5705919, 5847554, 6580258.
n
Video, Imaging and Instrumentation
TYPICAL APPLICATION
Concurrent, ±±12 ꢀutꢁut ꢂCꢃꢂC ꢄμoꢅuꢆe ꢇeꢈuꢆltorꢉ
I
OUT1
V
IN
13V TO 28V
12V
OUT
UP TO 4A
+
V
V
OUT1
IN1
4.7μF
4.7μF
ꢀutꢁut 2oꢆtlꢈe Stlrt-Uꢁ Wlveforms
+
SV
V
V
OSNS1
IN1
22µF
×2
–
LOAD1
SV
OUT1
D1
–
Rꢈꢑꢊꢐꢀ
V
OUT1
ꢌꢆꢃꢄꢅꢆ
f
SET1
124k
IMON1a
IMON1b
CHANNEL 1 ANALOG OUTPUT
CURRENT INDICATOR
ꢋ
ꢆ
ꢇꢈꢉꢊ
V
V
= 0.25Ω • I
ꢌꢆꢃꢄꢅꢆ
IN2
IMON1
OUT1
4.7μF
SV
IN2
LDO
OUT
5V
OUT
ꢍ
ꢆ
LTM4655
ꢇꢈꢉꢀ
UP TO 25mA
V
f
D2
ꢌꢆꢃꢄꢅꢆ
4.7μF
+
V
124k
240k
OUT2
+
SET2
V
OSNS2
ꢎꢏꢇꢇꢄꢊꢐꢀ
ꢌꢆꢃꢄꢅꢆ
47µF
×2
–12V
LOAD2
ISET2a
ISET2b
–
ꢀꢁꢂꢂ ꢃꢄ0ꢅꢆ
V
OUT
UP TO 2.9A**
ꢀꢁꢂꢃꢄꢅꢆ
OUT2
I
OUT2
–
SV
OUT2
ISET1a
ISET1b
240k
GND
4655 TA01a
*FOR COMPLETE CIRCUIT, SEE FIGURE 50.
**FOR CHANNELS CONFIGURED TO REGULATE NEGATIVE V
−
:
CURRENT LIMIT FREQUENCY-FOLDBACK INCEPTION IS
OUT
n
A FUNCTION OF V , V
-, AND f
. CONTINUOUS OUTPUT CURRENT CAPABILITY IS SUBJECT TO DETAILS OF
OUT
INn
n
SWn
APPLICATION IMPLEMENTATION. SEE NOTES 2 AND 3 AND THE APPLICATIONS INFORMATION SECTION, FOR DETAILS.
Rev. 0
1
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LTM4655
TABLE OF CONTENTS
Feltures..................................................... ±
Aꢁꢁꢆicltions ................................................ ±
Tyꢁiclꢆ Aꢁꢁꢆicltion ........................................ ±
ꢂescriꢁtion.................................................. ±
Absoꢆute μlximum ꢇltinꢈs.............................. 3
Pin Confiꢈurltion .......................................... 3
ꢀrꢅer Informltion.......................................... 4
Eꢆectriclꢆ Chlrlcteristics................................. 4
Tyꢁiclꢆ Performlnce Chlrlcteristics ..................±0
Pin Functions..............................................±4
Simꢁꢆifieꢅ Bꢆock ꢂilꢈrlm ...............................1±
Test Circuit.................................................11
ꢂecouꢁꢆinꢈ ꢇequirements...............................13
ꢀꢁerltion...................................................14
Power Module Overview.........................................24
Aꢁꢁꢆicltions Informltion ................................18
Power Module Protection .......................................28
RUN Pin Enable.......................................................28
Loop Compensation................................................28
Hot Plugging Safely ................................................29
Input Disconnect/Input Short Considerations.........29
INTV
and EXTV
Connection.........................29
CCn
CCn
Multiphase Operation..............................................30
Negative Output Current Capability Varies as a
–
Function of V to V
Conversion Ratios,
INn
OUTn
–
Negative-V
Operation.......................................31
OUT
–
Input Capacitors, Negative-V
Output Capacitors, Negative-V
Optional Diodes to Guard Against Overstress,
Operation...........32
OUT
–
Operation ........33
OUT
–
Negative-V
Operation.......................................33
OUT
–
V to V
Conversion Ratios................................25
Frequency Adjustment, Negative-V
Operation .34
IN
OUT
OUT
Input Capacitors, Positive-V
Operation .............25
Operation...........26
Radiated EMI Noise ................................................35
OUT
Output Capacitors, Positive-V
Thermal Considerations and Output Current
OUT
Forced Continuous Operation .................................26
Derating..................................................................35
Safety Considerations.............................................46
Layout Checklist/Example ......................................46
Tyꢁiclꢆ Aꢁꢁꢆicltions......................................49
Plcklꢈe ꢂescriꢁtion .....................................51
Plcklꢈe Photoꢈrlꢁh .....................................54
ꢂesiꢈn ꢇesources ........................................54
ꢇeꢆlteꢅ Plrts..............................................54
Output Voltage Programming, Tracking and
Soft-Start................................................................26
Frequency Adjustment............................................27
Rev. 0
2
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LTM4655
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(Note ± lnꢅ Note 5)
ꢕꢧꢍ ꢨꢢꢈꢝ
Channel 1 Terminal Voltages (Aꢆꢆ Chlnneꢆ ± Terminlꢆ
2oꢆtlꢈes ꢇeꢆltive to 2ꢀUT±– Unꢆess ꢀtherwise Inꢅiclteꢅ)
ꢌ
ꢋ
ꢊ
ꢉ
ꢈ
ꢨ
ꢨ
ꢢꢩꢘ
ꢢꢩꢀ
ꢭ
ꢨ
ꢨ
ꢭ
ꢨ
ꢨ
ꢉꢀ
ꢧꢪꢕꢀ
ꢉꢘ
ꢧꢪꢕꢘ
ꢊꢂꢃꢢꢩꢀ ꢊꢂꢃꢧꢪꢕꢀ
ꢊꢂꢃꢢꢩꢘ ꢊꢂꢃꢧꢪꢕꢘ
ꢤꢨ
ꢤꢨ
ꢂꢉꢧ
ꢢꢩ
ꢢꢩꢇꢀ
V
, V , SV , SV , SW1.................... –0.3V to 42V
IN1 D1
GND, EXTV , V
IN1
INF1
+
+
, V
,
ꢢꢁꢧꢩꢀꢡ ꢢꢁꢧꢩꢀꢫ ꢤꢨ
ꢢꢁꢧꢩꢘꢡ ꢢꢁꢧꢩꢘꢫ ꢤꢨ
ꢊꢂꢃꢧꢪꢕꢘ
ꢆꢩꢉ
ꢢꢩꢀ
ꢢꢩꢘ
ꢢꢩꢇꢘ
CC1 OUT1
OSNS1
ISET1a , ISET1b ..................................... –0.3V to 28V
ꢍꢆꢧꢧꢉꢀ ꢍꢆꢉꢇꢋꢀ ꢨꢢꢩRꢈꢆꢀ ꢆꢩꢉ
ꢍꢆꢧꢧꢉꢘ ꢍꢆꢉꢇꢋꢘ ꢨꢢꢩRꢈꢆꢘ ꢆꢩꢉ
INTV , PGDFB1, VINREG1, COMP1a,
CC1
ꢭ
ꢨ
ꢧꢪꢕꢀ
ꢭ
ꢭ
ꢤꢨ
ꢧꢪꢕꢘ
ꢊꢧꢁꢍꢀꢡ ꢊꢧꢁꢍꢀꢫ
ꢬ
ꢤꢨ
ꢧꢪꢕꢀ
ꢊꢧꢁꢍꢘꢡ ꢊꢧꢁꢍꢘꢫ
ꢬ
ꢁꢧꢉ
ꢤꢈꢕꢀ
ꢤꢈꢕꢘ
IMON1a, IMON1b..................................... –0.3V to 4V
ꢨ
ꢭ
f
.................................................... –0.3V to INTV
ꢧꢪꢕꢘ
ꢊꢂꢃꢤꢈꢕ
ꢢꢤꢈꢕꢀꢡ ꢢꢤꢈꢕꢀꢫ ꢈꢖꢕꢨ
Rꢪꢩꢀ
ꢢꢤꢈꢕꢘꢡ ꢢꢤꢈꢕꢘꢫ ꢈꢖꢕꢨ
ꢊꢊꢘ
Rꢪꢩꢘ
ꢤꢝꢘ
SET1
CC1
+ 32V
ꢊꢊꢀ
–
ꢇ
RUN1 ...................................GND–0.3V to V
OUT1
ꢭ
ꢭ
ꢨ
ꢧꢪꢕꢘ
ꢮ
ꢭ
ꢮ
ꢭ
ꢨ
ꢂꢉꢧ
ꢧꢪꢕ
ꢨ
ꢤꢨ
ꢧꢪꢕꢀ
ꢢꢩꢕꢨ
ꢊꢊꢀ
ꢧꢪꢕꢀ
ꢨ
ꢤꢨ
ꢧꢪꢕꢘ
ꢢꢩꢕꢨ
ꢊꢊꢘ
ꢧꢤꢩꢤꢀ
ꢧꢤꢩꢤꢘ
PGOOD1, CLKIN1 (Relative to GND)............. –0.3V to 6V
ꢆ
ꢅ
ꢄ
ꢮ
ꢭ
ꢮ
ꢭ
ꢨ
ꢤꢨ
ꢧꢪꢕꢀ
ꢤꢝꢀ
ꢨ
ꢤꢨ
ꢧꢤꢩꢤꢀ
ꢧꢤꢩꢤꢘ ꢧꢪꢕꢘ
ꢭ
Channel 2 Terminal Voltages (Aꢆꢆ Chlnneꢆ 1 Terminlꢆ
ꢨ
ꢭ
ꢨ
ꢮ
ꢭ
ꢧꢪꢕꢀ
ꢧꢪꢕꢘ
ꢕꢈꢁꢍ ꢕꢈꢁꢍ
ꢩꢊ
ꢩꢊ
ꢩꢊ
ꢩꢊ
2oꢆtlꢈes ꢇeꢆltive to 2ꢀUT1– Unꢆess ꢀtherwise Inꢅiclteꢅ)
ꢭ
ꢨ
ꢧꢪꢕꢀ
ꢃ
ꢂ
V
, V , S
, SV , SW2 ................... –0.3V to 42V
IN2 D2 VIN2 INF2
ꢮ
ꢮ
ꢭ
ꢨ
ꢨ
ꢨ
ꢧꢪꢕꢘ
ꢧꢪꢕꢀ
ꢧꢪꢕꢘ
+
+
GND, EXTV , V
, V
,
CC2 OUT2
OSNS2
ꢭ
ꢨ
ꢧꢪꢕꢀ
ISET2a, ISET2b...................................... –0.3V to 28V
ꢁ
INTV , PGDFB2, VINREG2, COMP2a,
CC2
ꢀ
ꢘ
ꢣ
ꢎ
ꢓ
ꢑ
ꢥ
ꢦ
ꢛ
ꢀ0
ꢀꢀ
ꢀꢘ
IMON2a, IMON2b .................................... –0.3V to 4V
ꢋꢆꢌ ꢍꢌꢊꢃꢌꢆꢈ
ꢀꢎꢎꢏꢂꢈꢌꢉ ꢐꢀꢑꢒꢒ × ꢀꢑꢒꢒ × ꢓ.0ꢀꢒꢒꢔ
f
.................................................... –0.3V to INTV
SET2
CC2
+ 32V
ꢕ
ꢗ ꢀꢘꢓꢙꢊꢚ θ ꢗ ꢀꢀ.ꢛꢙꢊꢜꢝꢚ
–
ꢄꢐꢁꢌꢖꢔ
ꢄꢌ
RUN2 ...................................GND–0.3V to V
θ
ꢗ ꢀ0ꢙꢊꢜꢝꢚ θ
ꢗ ꢘ.ꢑꢙꢊꢜꢝꢚ
ꢄꢊꢡꢟꢞ
OUT2
ꢄꢊꢞꢟꢠ
ꢝꢈꢢꢆꢅꢕ ꢗ ꢣ.ꢣ ꢆRꢌꢁꢤ
PGOOD2, CLKIN2 (Relative to GND) ............ –0.3V to 6V
ꢩꢧꢕꢈꢤꢯ
ꢀꢔ θ ꢨꢌꢂꢪꢈꢤ ꢌRꢈ ꢉꢈꢕꢈRꢁꢢꢩꢈꢉ ꢋꢰ ꢤꢢꢁꢪꢂꢌꢕꢢꢧꢩ ꢍꢈR ꢄꢈꢤꢉꢓꢀ ꢊꢧꢩꢉꢢꢕꢢꢧꢩꢤ.
ꢘꢔ θ ꢨꢌꢂꢪꢈ ꢢꢤ ꢧꢋꢕꢌꢢꢩꢈꢉ ꢝꢢꢕꢅ ꢉꢈꢁꢧ ꢋꢧꢌRꢉ.
ꢄꢌ
ꢣꢔ RꢈꢇꢈR ꢕꢧ ꢌꢍꢍꢂꢢꢊꢌꢕꢢꢧꢩ ꢢꢩꢇꢧRꢁꢌꢕꢢꢧꢩ ꢤꢈꢊꢕꢢꢧꢩ ꢇꢧR ꢂꢌꢋ ꢁꢈꢌꢤꢪRꢈꢁꢈꢩꢕ
ꢌꢩꢉ ꢉꢈRꢌꢕꢢꢩꢆ ꢢꢩꢇꢧRꢁꢌꢕꢢꢧꢩ.
LDO and Clock Generator Voltages (Aꢆꢆ Lꢂꢀ lnꢅ Cꢆock
Generltor Terminlꢆ 2oꢆtlꢈes ꢇeꢆltive to GNꢂ Unꢆess
ꢀtherwise Inꢅiclteꢅ)
LDO ......................................................... –0.3V to 42V
IN
CLKSET, MOD...........................–0.3V to LDO
+ 0.3V
OUT
Terminal Currents
INTV
Peak Output Current (Note 10) ................30mA
CCn
+
TEMP ......................................................–1mA to 10mA
–
TEMP .....................................................–10mA to 1mA
Temperatures Internal Operating Temperature
Range (Note 2 and Note 9)
E- and I-Grade ................................... –40°C to 125°C
MP-Grade .......................................... –55°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Package Body Temperature During Reflow .. 245°C
Rev. 0
3
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LTM4655
ORDER INFORMATION
PAꢇT μAꢇKINGꢉ
PACKAGE
TYPE
μSL
ꢇATING
TEμPEꢇATUꢇE ꢇANGE
(SEE NꢀTE 1)
PAꢇT NUμBEꢇ
LTM4655EY#PBF
LTM4655IY#PBF
LTM4655MPY#PBF
LTM4655IY
PAꢂ ꢀꢇ BALL FINISH
SAC305 (RoHS)
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
ꢂE2ICE
FINISH CꢀꢂE
LTM4655Y
LTM4655Y
LTM4655Y
LTM4655Y
LTM4655Y
e1
e1
e1
e0
e0
BGA
BGA
BGA
BGA
BGA
3
3
3
3
3
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–55°C to 125°C
LTM4655MPY
SnPb (63/37)
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
ELECTRICAL CHARACTERISTICS The l ꢅenotes the sꢁecificltions which lꢁꢁꢆy over the sꢁecifieꢅ internlꢆ
oꢁerltinꢈ temꢁerlture rlnꢈe (Note 1). Sꢁecifieꢅ ls elch inꢅiviꢅulꢆ outꢁut chlnneꢆ (Note 5). TA = 15°C, Test Circuit ± (ꢁositive-2ꢀUT
,
+
noninvertinꢈ steꢁ-ꢅown confiꢈurltion with 2ꢀUTn– = GNꢂ), 2 = S2INn = 362, EXT2CCn = 142, ꢇUNn = 3.32, ꢇISETn = 480k, ꢇfSETn
=
INn
5ꢊ.6kΩ, fSWn = ±.5μHz (CLKINn ꢅriven with ±.5μHz cꢆock siꢈnlꢆ) lnꢅ voꢆtlꢈes referreꢅ to GNꢂ unꢆess otherwise noteꢅ.
SYμBꢀL
PAꢇAμETEꢇ
CꢀNꢂITIꢀNS
μIN
TYP
μAX
UNITS
–
l
l
l
SV
, V
Input DC Voltage in Positive-V
Configuration
V
OUTn
= GND
3.1
40
V
INn(DC) INn(DC)
OUT
+
–
+
V
Range of Positive Output Voltage
Regulation
0.5V ≤ ISETna–SV
(See Note 7)
≤ 26.5V, I = 0A
OUTn
0.5
26.5
24.4
V
V
OUTn(RANGE)
OUTn
+
+
V
Output Voltage Total Variation with Line 29V ≤ V ≤ 40V, 0A ≤ I
≤ 4A, C
INHn
= 2 × 47μF,
23.6
24
0
OUTn(24VDC)
INn
Dn
OUTn
+
and Load at V
= 24V
= 4.7μF, C = 4.7μF, C
CLKINn Driven with 1.5MHz Clock
OUTn
OUTHn
+
+
l
V
Output Voltage Total Variation with Line Measuring V
to ISETna
–15
15
mV
Ω
OUTn(0.5VDC)
OSNSn
+
+
and Load at V
= 0.5V
3.1V ≤ V ≤ 13.2V, 0A ≤ I
≤ 4A, C
OUTn
INn
Dn
OUTn INHn
= 4.7μF, C = 4.7μF, C
= 2 × 47μF,
OUTHn
fSETn
ISETna = 500mV, R
= N/U (Note 6)
R
SVINFn
Resistor Between SV and SV
INFn
1
INn
Inꢁut Sꢁecificltions
l
l
l
V
SV Undervoltage Lockout Threshold SV Rising
2.85
2.6
3.1
2.9
V
V
INn(UVLO)
INRUSH(VINn)
Q(SVINn)
INn
INn
SV Falling
2.4
150
INn
Hysteresis
250
mV
I
I
Input Inrush Current at Start-Up
C
= 4.7μF, C = 4.7μF, C
OUTn
= 2 ×
300
mA
INHn
Dn
OUTHn
+
47μF; I
= 0A, ISETna Electrically
Connected to ISETnb
Input Supply Bias Current
Shutdown, RUNn = GND
RUNn = 3.3V
16
450
30
μA
μA
+
I
I
Input Supply Current
CLKINn Open Circuit, I
= 4A
2.9
4
A
S(VINn)
OUTn
Input Supply Current in Shutdown
Shutdown, RUNn = GND
µA
S(VINn, SHUTDOWN)
ꢀutꢁut Sꢁecificltions
+
+
I
V
Output Continuous Current
(Note 3)
0
4
A
%
%
OUTn
OUTn
Range
+
+
l
l
∆V
V
/
Line Regulation Accuracy
Load Regulation Accuracy
I
= 0A, 29V ≤ V ≤ 40V
0.05
0.05
2
0.1
0.75
OUTn(LINE)
OUTn
INn
+
OUTn
+
+
∆V
V
/
V
= 36V, 0A ≤ I
≤ 4A
OUTn(LOAD)
INn
INn
OUTn
+
OUTn
+
+
V
Output Voltage Ripple, V
V
= 12V, ISETna = 5V
mV
OUTn(AC)
OUTn
P-P
Rev. 0
4
For more information www.analog.com
LTM4655
The l ꢅenotes the sꢁecificltions which lꢁꢁꢆy over the sꢁecifieꢅ internlꢆ
ELECTRICAL CHARACTERISTICS
+
oꢁerltinꢈ temꢁerlture rlnꢈe (Note 1). Sꢁecifieꢅ ls elch inꢅiviꢅulꢆ outꢁut chlnneꢆ (Note 5). TA = 15°C, Test Circuit ± (ꢁositive-2ꢀUTn
,
+
noninvertinꢈ steꢁ-ꢅown confiꢈurltion with 2ꢀUTn– = GNꢂ), 2 = S2INn = 362, EXT2CCn = 142, ꢇUNn = 3.32, ꢇISETn = 480k, ꢇfSETn
=
INn
5ꢊ.6kΩ, fSWn = ±.5μHz (CLKINn ꢅriven with ±.5μHz cꢆock siꢈnlꢆ) lnꢅ voꢆtlꢈes referreꢅ to GNꢂ unꢆess otherwise noteꢅ.
SYμBꢀL
PAꢇAμETEꢇ
CꢀNꢂITIꢀNS
= 57.6k, CLKINn Open Circuit
μIN
TYP
1.95
8
μAX
UNITS
MHz
mV
+
l
l
f
Sn
V
Ripple Frequency
R
fSETn
1.7
2.2
OUTn
+
∆V
Turn-On Overshoot
OUTn(START)
t
Turn-On Start-Up Time
Delay Measured from V Toggling from 0V
4
9
ms
STARTn
INn
to 36V to PGOODn Exceeding 3V; PGOODn.
Having a 100kΩ Pull-Up to 3.3V with Respect
to GND, VPGFBn Resistor Divider Network as
Shown in Test Circuit 1, R
= 480kΩ and
ISETna
ISETna Electrically Connected to ISETnb and
CLKIN Driven with 1.5MHz Clock
+
+
∆V
Peak Output Voltage Deviation for
Dynamic Load Step
I
: 0A to 2A and 2A to 0A Load Steps in
OUTHn
400
50
mV
µs
A
OUTn(LS)
OUTn
1μs, C
= 47µF × 2
+
t
Settling Time for Dynamic Load Step
I
: 0A to 2A and 2A to 0A Load Steps in
SETTLEn
OUTn
1μs, C
= 47µF × 2
OUTHn
+
+
I
I
Output Current Limit
5.5
OUTn(OCL)
OUTn
Controꢆ Section
l
l
I
Reference Current of ISETna Pin
V
V
= 0.5V, 3.1V ≤ V ≤ 13.2V
49.3
49
50
50
50.7
51
µA
µA
ISETna
ISETna
ISETna
INn
= 24V, 29V ≤ V ≤ 40V
INn
+
+
+
I
t
V
Leakage Current
V
= 28V
290
60
μA
ns
VOSNSn
OSNSn
VOSNSn
Minimum On-Time
(Note 4)
ONn(MIN)
l
l
V
RUNn Turn-On/-Off Thresholds
RUNn Input Turn-On Threshold, RUNn Rising
RUNn Hysteresis
1.08
360
1.2
1.32
50
V
RUNn
130
mV
I
RUNn Leakage Current
RUNn = 3.3V
0.1
nA
RUNn
ꢀsciꢆꢆltor lnꢅ Phlse-Lockeꢅ Looꢁ (PLL)
f
Oscillator Frequency Accuracy
V
INn
f
= 12V, ISETna = 5V, and:
OSCn
Open-Circuit
l
400
1.95
440
kHz
MHz
SETn
R
fSETn
= 57.6kΩ (See f Specification)
SN
f
PLL Synchronization Capture Range
V
= 12V, ISETna = 5V, CLKIN Driven with
n
SYNCn
INn
a GND Referred Clock Toggling from 0.4V to
1.2V and Having a Clock Duty Cycle:
From 10% to 90%; f
Open Circuit
= 57.6kΩ
250
1.3
550
3
kHz
MHz
SETn
From 40% to 60%; R
fSETn
V
CLKINn Input Threshold
CLKINn Input Current
V
V
Rising
Falling
1.2
V
V
CLKINn
CLKINn
CLKINn
0.4
I
V
V
= 5V
= 0V
230
–5
500
μA
μA
CLKINn
CLKINn
CLKINn
–20
Power Gooꢅ Feeꢅblck Inꢁut lnꢅ Power Gooꢅ ꢀutꢁut
l
l
OV
UV
∆V
Output Overvoltage PG00Dn Upper
PGDFBn Rising
PGDFBn Falling
PGDFBn Returning
620
525
645
555
675
580
mV
mV
PGDFBn
Threshold
Output Undervoltage PGOODn Lower
Threshold
PGDFBn
PGOODn Hysteresis
8
mV
kΩ
Ω
PGDFBn
PGDFBn
PGOODn
–
R
R
Resistor Between PGDFB1n and SV
PGOODn Pull-Down Resistance
4.94
4.99
700
5.04
OUTn
V
V
= 0.1V, V
> OV
= 3.3V, UV < V
PGDFBn
< UV
or
<
1500
PGOODn
PGDFBn
PGDFBn
PGDFBn
PGDFBn
I
PGOODn Leakage Current
V
0.1
1
μA
PGOODn(LEAK)
PGOODn
PGDFBn
OV
PGDFBn
Rev. 0
5
For more information www.analog.com
LTM4655
The l ꢅenotes the sꢁecificltions which lꢁꢁꢆy over the sꢁecifieꢅ internlꢆ
ELECTRICAL CHARACTERISTICS
+
oꢁerltinꢈ temꢁerlture rlnꢈe (Note 1). Sꢁecifieꢅ ls elch inꢅiviꢅulꢆ outꢁut chlnneꢆ (Note 5). TA = 15°C, Test Circuit ± (ꢁositive-2ꢀUTn
,
+
noninvertinꢈ steꢁ-ꢅown confiꢈurltion with 2ꢀUTn– = GNꢂ), 2 = S2INn = 362, EXT2CCn = 142, ꢇUNn = 3.32, ꢇISETn = 480k, ꢇfSETn
=
INn
5ꢊ.6kΩ, fSWn = ±.5μHz (CLKINn ꢅriven with ±.5μHz cꢆock siꢈnlꢆ) lnꢅ voꢆtlꢈes referreꢅ to GNꢂ unꢆess otherwise noteꢅ.
SYμBꢀL
PAꢇAμETEꢇ
CꢀNꢂITIꢀNS
μIN
TYP
μAX
UNITS
t
PGOODn Delay
PGOODn Low to High (Note 4)
PGOODn High to Low (Note 4)
16/f
s
s
PGOODn(DELAY)
SW(Hz)
SW(Hz)
64/f
Current μonitor lnꢅ Inꢁut 2oꢆtlꢈe ꢇeꢈuꢆltion Pins
+
+
+
l
h
I
/I
Ratio of V
Output Current to I
= 4A
36
40
44
k
IMONna
OUTn IMONna
OUTn
IMONna
Current, I
OUTn
+
I
I
Offset Current
I
at I
= 0A
–5
9.8
1.9
5
μA
kΩ
V
OSn(IMON)
IMONna
IMONna
OUTn
–
IMONnb Resistor
Resistor Between IMONnb and SV
IMONna Servo Voltage
10
10.2
2.1
OUTn
l
l
V
IMONna Voltage During Output Current
2.0
IMONna
VINREGn
VINREGn
Regulation
V
V
V
Servo Voltage
VINREGn Voltage During Output Current
1.8
2.0
1
2.2
V
INREGn
INREGn
Regulation
I
Leakage Current
VINREGn = 2V
nA
INT2
ꢇeꢈuꢆltor
CCn
V
Channel Internal V Voltage, No
3.6V ≤ SV ≤ 40V, EXTV Open Circuit
CCn
3.15
2.85
3.4
3.0
3.65
3.15
V
V
INTVCCn
CC
INn
INTV
Loading (I
= 0mA)
5V ≤ SV ≤ 40V, 3.2V ≤ EXTV
≤ 26.5V
CCn
INTVCCn
INn
CCn
V
EXTV
Switchover Voltage
Load Regulation
(Note 4)
3.15
0.5
V
EXTVCCn(TH)
CCn
CCn
∆V
INTV
0mA ≤ I
≤ 30mA
INTVCCn
–2
2
%
INTVCCn(LOAD)/
INTVCCn
V
ELECTRICAL CHARACTERISTICS The l ꢅenotes the sꢁecificltions which lꢁꢁꢆy over the sꢁecifieꢅ internlꢆ
oꢁerltinꢈ temꢁerlture rlnꢈe (Note 1). Sꢁecifieꢅ ls elch inꢅiviꢅulꢆ outꢁut chlnneꢆ (Note 5). TA = 15°C, Test Circuit 1 (neꢈltive-
2ꢀUTn–, invertinꢈ buck-boost confiꢈurltion with 2ꢀUTn+ = GNꢂ), 2INn = ±12 lnꢅ eꢆectriclꢆꢆy connecteꢅ to S2INn, ꢇUNn–GNꢂ = 3.32,
ISETnl–S2ꢀUTn– = 142, EXT2CCn = GNꢂ, CLKINn oꢁen circuit, ꢇfSETn = 5ꢊ.6kΩ lnꢅ ꢇISETn = 480kΩ lnꢅ voꢆtlꢈes referreꢅ to GNꢂ
unꢆess otherwise noteꢅ.
SYμBꢀL
PAꢇAμETEꢇ
CꢀNꢂITIꢀNS
μIN
TYP
μAX UNITS
+
–
l
l
l
SV
, V
Input DC Voltage in
V
|V | ≤ 40V
OUTn
3.6
40
V
V
V
INn(DC) INn(DC)
INn
–
Negative-V
Configuration
OUT
–
–
V
Range of Negative Output Voltage
Regulation
0.5V ≤ ISETna–SV
≤ 26.5V
–26.5
–0.5
OUTn(RANGE)
OUTn
–
–
V
Output Voltage Total Variation with Line 3.6V ≤ V ≤ 16V, 0A ≤ I
≤ 0.3A, CLKINn
–24.4 –24 –23.6
OUTn(–24VDC)
INn
OUTn
–
and Load at V
= –24V
Driven per Note 8, C
OUTHn
= 4.7μF, C = 4.7μF × 2,
INHn Dn
OUTn
C
= 47μF × 2
–
+
l
V
Output Voltage Total Variation with Line Measuring V
– ISETna, 12V ≤ V ≤ 35V,
–15
0
1
15
mV
Ω
OUTn(–5VDC)
OSNSn
INn
–
–
and Load at V
= –5V
0A ≤ I
≤ 3A, CLKINn Driven by 550kHz Clock,
OUTn
OUT
C
= 4.7μF, C = 4.7μF × 2, C
= 47μF ×
INHn
Dn
OUTHn
–
2, ISETna–SV
= 5V
OUTn
R
Resistor Between SV and SV
INn INFn
SVINFn
Rev. 0
6
For more information www.analog.com
LTM4655
ELECTRICAL CHARACTERISTICS The l ꢅenotes the sꢁecificltions which lꢁꢁꢆy over the sꢁecifieꢅ internlꢆ
oꢁerltinꢈ temꢁerlture rlnꢈe (Note 1). Sꢁecifieꢅ ls elch inꢅiviꢅulꢆ outꢁut chlnneꢆ (Note 5). TA = 15°C, Test Circuit 1 (neꢈltive-
2ꢀUTn–, invertinꢈ buck-boost confiꢈurltion with 2ꢀUTn+ = GNꢂ), 2INn = ±12 lnꢅ eꢆectriclꢆꢆy connecteꢅ to S2INn, ꢇUNn–GNꢂ = 3.32,
ISETnl–S2ꢀUTn– = 142, EXT2CCn = GNꢂ, CLKINn oꢁen circuit, ꢇfSETn = 5ꢊ.6kΩ lnꢅ ꢇISETn = 480kΩ lnꢅ voꢆtlꢈes referreꢅ to GNꢂ
unꢆess otherwise noteꢅ.
SYμBꢀL
PAꢇAμETEꢇ
CꢀNꢂITIꢀNS
μIN
TYP
μAX UNITS
Inꢁut Sꢁecificltions
l
l
l
V
SV Undervoltage Lockout Threshold SV Rising
3.2
2.5
700
3.6
2.8
V
V
INn(UVLO)
INRUSH(VINn)
Q(SVINn)
INn
INn
SV Falling
2.1
400
INn
Hysteresis
mV
I
I
Input Inrush Current at Start-Up
C
= 4.7μF, CDn = 4.7μF × 2, C
OUTn
= 47μF ×
1.1
A
INHn
OUTHn
–
2; I
= 0A, ISETna Electrically Connected to
ISETnb
Input Supply Bias Current
Shutdown, RUNn = GND
RUNn–GND = 3.3V
16
450
30
μA
μA
–
I
I
Input Supply Current
CLKINn Open Circuit, I
= 1.25A
3.0
4
A
S(VINn)
OUTn
Input Supply Current in Shutdown
Shutdown, RUNn = GND
µA
S(VINn, SHUTDOWN)
ꢀutꢁut Sꢁecificltions
–
–
–
I
V
OUTn
Output Continuous Current Range
V
INn
=12V, Regulating V
=–24V at f
=1MHz
0
0
1.25
3
A
A
OUTn
INn
OUTn
SWn
SWn
–
V
= 12V, Regulating V
= –5V at f
= 550kHz
OUTn
(See Note 3. Capable of Up to 4A Output Current
–
for Some Combinations of V , V
and f
)
INn OUTn
SWn
–
–
–
–
–
l
l
∆V
∆V
/V
Line Regulation Accuracy
Load Regulation Accuracy
I
= 0A, 3.6V ≤ V ≤ 16V, ISETna–SV
OUTn
=
0.05 0.25
0.05 0.75
10
%
%
OUTn(LINE)
OUTn
OUTn
INn
24V, CLKINn Driven by 1.8MHz Clock
–
–
/V
V
= 12V, 0A ≤ I
1.5MHz Clock, R
≤ 1.25A, CLKINn Driven by
OUTn(LOAD) OUTn
INn
OUTn
fSETn
= 57.6kΩ, and R
= 480kΩ
ISETn
–
–
–
V
Output Voltage Ripple, V
V
V
= 12V, I
= 12V, I
–SV
= 5V
= 5V
mV
P-P
OUTn(AC)
OUTn
INn
INn
SETna
SETna
OUTn
OUTn
–
–
l
l
f
V
Ripple Frequency
–SV
1.7
1.95
8
2.2
MHz
SN
OUTn
–
∆V
Turn-On Overshoot
mV
ms
OUTn(START)
t
Turn-On Start-Up Time
Delay Measured from V Toggling from 0V
4
9
STARTn
INn
to 12V to PGOODn Exceeding 3V Above GND;
PGOODn Having a 100kΩ Pull-Up to 3.3V with
Respect to GND, V
Resistor Divider Network
PGFBn
as Shown in Test Circuit 2, R
= 480kΩ,
ISETna
ISETna Electrically Connected to ISETnb, and
CLKINn Driven with 1.2MHz Clock
–
–
∆V
Peak Output Voltage Deviation for
Dynamic Load Step
I
: 0A to 1A and 1A to 0A Load Steps in 1μs,
400
50
mV
µs
A
OUTn(LS)
OUTn
C
= 47µF × 2
OUTHn
–
t
I
Settling Time for Dynamic Load Step
I
: 0A to 1A and 1A to 0A Load Steps in 1μs,
SETTLEn
OUTn
C
= 47µF × 2 X5R
OUTH2
–
–
I
Output Current Limit
1.7
OUTn(OCL)
OUTn
Controꢆ Section
–
l
l
I
Reference Current of ISETna Pin
V
–SV
ISETna
= 0.5V, 3.6V ≤ V ≤ 28V
49.3
49
50
50
50.7
51
µA
µA
ISETna
ISETna
OUTn
INn
–
–
0V ≤ V
–SV
≤ V –SV
≤ 40V
OUTn
INn
OUT
+
+
+
–
I
t
V
Leakage Current
V
– SV
= 28V
290
60
μA
ns
VOSNSn
OSNSn
OSNSn
OUTn
Minimum On-Time
(Note 4 )
ONn(MIN)
l
l
V
RUNn Turn-On/-Off Thresholds
RUNn Input Turn-On Threshold, RUNn Rising
RUNn Hysteresis
1.08
1.2
1.32
50
V
RUNn
130
mV
(RUNn Thresholds Measured with Respect to GND)
I
RUNn Leakage Current
V
INn
= 12V, RUNn–GND = 3.3V
0.1
nA
Rev. 0
7
RUNn
For more information www.analog.com
LTM4655
ELECTRICAL CHARACTERISTICS The l ꢅenotes the sꢁecificltions which lꢁꢁꢆy over the sꢁecifieꢅ internlꢆ
oꢁerltinꢈ temꢁerlture rlnꢈe (Note 1). Sꢁecifieꢅ ls elch inꢅiviꢅulꢆ outꢁut chlnneꢆ (Note 5). TA = 15°C, Test Circuit 1 (neꢈltive-
2ꢀUTn–, invertinꢈ buck-boost confiꢈurltion with 2ꢀUTn+ = GNꢂ), 2INn = ±12 lnꢅ eꢆectriclꢆꢆy connecteꢅ to S2INn, ꢇUNn–GNꢂ = 3.32,
ISETnl–S2ꢀUTn– = 142, EXT2CCn = GNꢂ, CLKINn oꢁen circuit, ꢇfSETn = 5ꢊ.6kΩ lnꢅ ꢇISETn = 480kΩ lnꢅ voꢆtlꢈes referreꢅ to GNꢂ
unꢆess otherwise noteꢅ.
SYμBꢀL
PAꢇAμETEꢇ
CꢀNꢂITIꢀNS
μIN
TYP
μAX UNITS
ꢀsciꢆꢆltor lnꢅ Phlse-Lockeꢅ Looꢁ (PLL)
–
f
f
Oscillator Frequency Accuracy
V
= 12V, ISETna–SV
= 5V, and:
OUTn
OSCn
INn
f
Open Circuit
l
360
400
1.95
440
kHz
MHz
SETn
R
fSETn
= 57.6kΩ (See f Specification)
SN
–
PLL Synchronization Capture Range
V
INn
= 12V, ISETna–SV
= 5V, CLKINn Driven
SYNCn
OUTn
with a GND Referred Clock Toggling from 0.4V to
1.2V and Having a Clock Duty Cycle:
From 10% to 90%; f
From 40% to 60%; R
Open Circuit
250
1.3
550
3
kHz
MHz
SETn
= 57.6kΩ
fSETn
V
CLKINn Input Threshold
V
V
Rising with Respect to GND
Falling with Respect to GND
1.2
V
V
CLKINn
CLKINn
CLKINn
0.4
I
CLKINn Input Current
V
V
= 5V with Respect to GND
= 0V with Respect to GND
230
–5
500
μA
μA
CLKINn
CLKINn
CLKINn
–20
Power Gooꢅ Feeꢅblck Inꢁut lnꢅ Power Gooꢅ ꢀutꢁut
l
l
OV
UV
∆V
Output Overvoltage PGOODn
PGDFBn Rising, Differential Voltage from PGDFBn
620
525
645
555
8
675
580
mV
mV
PGDFBn
–
Upper Threshold
to SV
OUTn
Output Undervoltage PGOODn Lower
Threshold
PGDFBn Falling, Differential Voltage from PGDFBn
PGDFBn
–
to SV
OUTn
PGOODn Hysteresis
PGDFBn Returning
mV
kΩ
Ω
PGDFBn
PGDFBn
PGOODn
–
R
R
Resistor Between PGDFBn and SV
PGOODn Pull-Down Resistance
4.94 4.99 5.04
700 1500
OUTn
V
V
V
= 0.1V with Respect to GND,
PGOODn
PGDFBn
PGDFBn
–
–SV
< UV
> OV
or
OUTn
OUTn
PGDFBn
PGDFBn
–
–SV
I
t
PGOODn Leakage Current
PGOODn Delay
V
= 3.3V with Respect to GND,
0.1
1
μA
PGOODn(LEAK)
PGOODn
–
UV
< V
–SV
< OV
PGDFBn
PGDFBn
PGDFBn
OUTn
PGOODn Low to High (Note 4)
PGOODn High to Low (Note 4)
16/f
s
s
PGOODn(DELAY)
SW(Hz)
SW(Hz)
64/f
Inꢁut 2oꢆtlꢈe ꢇeꢈuꢆltion Pin
l
V
V
Servo Voltage
V
Voltage During Output Current Regulation,
1.8
2.0
1
2.2
V
VINREGn
INREGn
INREGn
–
Measured with Respect to SV
OUTn
–
I
V
Leakage Current
V
INREG
–SV
= 2V
nA
VINREGn
INREGn
OUTn
INT2
ꢇeꢈuꢆltor
CCn
–
–
V
Channel Internal V Voltage, No
3.6V ≤ SV –SV
≤ 40V, EXTV = Open Circuit
3.15
2.85
3.4
3.0
3.65
3.15
V
V
V
INTVCCn
CC
INn
OUTn
CCn
–
INTV
Loading (I
= 0mA)
5V ≤ SV –SV
≤ 40V, 3.2V ≤ EXTV
CCn
INTVCCn
INn
≤ 26.5V
OUTn CCn
–
V
OUTn
–
(INTV
Measured with Respect to SV
)
CCn
OUTn
–
V
EXTV
Switchover Voltage
Load Regulation
(EXTV
Measured with Respect to SV )
OUTn
3.15
0.5
V
EXTVCCn(TH)
CCn
CCn
(Note 4)
∆V
/
INTV
0mA ≤ I
≤ 30mA
INTVCCn
–2
2
%
INTVCCn(LOAD)
INTVCCn
CCn
V
Rev. 0
8
For more information www.analog.com
LTM4655
ELECTRICAL CHARACTERISTICS The l ꢅenotes the sꢁecificltions which lꢁꢁꢆy over the sꢁecifieꢅ internlꢆ
oꢁerltinꢈ temꢁerlture rlnꢈe (Note 1). TA = 15°C, Test Circuit 3 lnꢅ voꢆtlꢈes referreꢅ to GNꢂ unꢆess otherwise noteꢅ.
SYμBꢀL
PAꢇAμETEꢇ
CꢀNꢂITIꢀNS
μIN
TYP
μAX UNITS
l
LDO
LDO Input DC Voltage
LDO Output Voltage
4.5
40
V
IN(DC)
l
l
V
V
V
= 36V, 0mA ≤ I
LDOOUT
≤ 25mA
≤ 20mA
4.8
2.7
5.0
4.1
5.2
V
V
LDOOUT(DC)
LDOIN
LDOIN
= 4.5V, 0mA ≤ I
LDOOUT
V
Output Voltage Ripple
2
mV
P-P
LDOOUT(AC)
I
Output Current Limit, 5V LDO
LDO = 36V
140
mA
LDOOUT(OCL)
IN
Cꢆock Generltor
l
l
∆f
Clock-Generator Frequency Accuracy
Frequency Setting Resistor Range
2.7V ≤ LDO
≤ 5.2V, 200kHz ≤ f ≤ 3MHz,
OUT
2.5
2.5
7.5
3
%
%
OUT
OUT
MOD Connected to CLKOUT2
Resistance for Which –7.5% ≤ ∆f ≤
OUT
R
R
33.2
40
499
kΩ
CLKSET(RANGE)
CLKSET
7.5%, Over 2.7V ≤ LDO
≤ 5.2V,
OUT
MOD Electrically Connected to CLKOUT2
Period Variation (Frequency Spreading)
Duty Cycle
LDO = 5V, R = 100kΩ, MOD Open Circuit
10
%
%
OUT
CLKSET
l
2.7V ≤ LDO
MOD Electrically Connected to CLKOUT2
≤ 5.2V, 200kHz ≤ f
≤ 3MHz,
60
OUT
OUT
θ
θ
/
Phase Relationship of CLKOUT2 to
CLKOUT1
2.7V ≤ LDO ≤ 5.2V, 200kHz ≤ f ≤ 3MHz,
180
Deg
V
CLKOUT1
CLKOUT2
OUT
OUT
MOD Electrically Connected to CLKOUT2
CLKOUTn V Measured with Respect to LDO ,
OUT
V
CLKOUTn Output Voltage, Logic High
–0.4
OH_CLKOUTn
OL_CLKOUTn
OH
OUT
2.7V ≤ LDO
≤ 5.2V, I
= –100μA
CLKOUTn
V
CLKOUTn Output Voltage, Logic Low
CLKOUTn V Measured with Respect to GND, 2.7V
0.4
V
OL
≤ 5.2V, I
≤ LDO
= 100μA
OUT
CLKOUTn
Temꢁerlture Sensor
∆V
TEMP
Temperature Sensor Forward Voltage,
+ to V
I
+ = 100µA and I
– = –100μA at T = 25°C
0.598
V
TEMP
TEMP
A
V
–
TEMP
TEMP
TC
∆V
TEMP
Temperature Coefficient
–2.0
mV/°C
∆V(TEMP)
η
Ideality Factor
1.004
+
Note ±: Stresses beyond those listing under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating conditions for extended periods may affect device
reliability and lifetime.
Note 6: To ensure minimum on-time criteria is met, V
(0.5V ) high
OUTn DC
line regulation is tested at 13.2V , with f
and CLKINn open circuit.
IN
SETn
–
V
(–0.5V ) low line regulation is tested at 3.6V , with f
and
OUTn
DC
IN
SETn
CLKINn open circuit.
–
Note 1: The LTM4655 is tested under pulsed load conditions such that T ≈
V
(–0.5V ) high line regulation is tested at 28V , and with CLKINn
J
OUTn
DC
IN
T . The LTM4655E is guaranteed to meet performance specifications over the
driven at 200kHz—so as to ensure minimum on-time criteria is met.
The LTM4655 is not recommended for applications where the minimum
on-time criteria (guardband to 90ns) is continuously violated. The
A
0°C to 125°C internal operating temperature range. Specifications over the full
–40°C to 125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls.
LTM4655 can ride through events (such as V surge) where the on-time
IN
criteria is transiently violated. See the Applications Information section.
The LTM4655I is guaranteed to meet specifications over the full –40°C to
125°C internal operating temperature range. The LTM4655MP is tested and
guaranteed over the full –55°C to 125°C operating temperature range. Note
that the maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board layout,
the rated package thermal resistance and other environmental factors.
Note ꢊ: See the Applications Information section for dropout criteria.
–
Note 8: V
(–24V ) is tested at 3.6V and 16V , with CLKINn
OUTn
DC
IN
IN
–
driven with a 1.8MHz clock, ISETna to SV
= 12V, and R
= 57.6k.
OUTn
fSET
It is also tested at 12V , with CLKINn driven with a 1.5MHz clock, R
IN
fSETn
= 57.6k, and R
= 480k.
ISETn
Note 3: See output current derating curves for different V , V , and T ,
located in the Applications Information section.
IN OUT
A
Note 9: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4: Minimum on-time, PGOOD delay, and EXTV
switchover
CCn
threshold are tested at wafer sort.
Note 5:The two power inputs—V and V —and their respective power
IN1
IN2
+
–
+
–
outputs—V
or V
, and V
or V
, depending on operational
Note ±0: The INTV
Abs Max peak output current is specified as the sum
OUT1
OUT1
OUT2
OUT2
CCn
configuration—are tested independently in production, in both positive-V
of current drawn by circuits internal to the module biased off of INTV
OUT
CCn
–
(noninverting step-down) and negative-V
(inverting buck-boost) configurations.
and current drawn by external circuits biased off of INTV . Specified
OUT
CCn
On occasion, a shorthand notation is used in this document that allows V to refer
independently, for each channel. See the Applications Information section.
INn
to both V and V by virtue of nbeing permitted to take on a value of 1 or 2. This
IN1
IN2
italicized nnotation and convention is extended to all such pin names.
Rev. 0
9
For more information www.analog.com
LTM4655
+
TA = 15°C, sinꢈꢆe chlnneꢆ ꢁositive-2ꢀUTn
oꢁerltion onꢆy, unꢆess otherwise noteꢅ.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Lolꢅ Current lt
52IN, Forceꢅ Continuous μoꢅe
Efficiency vs Lolꢅ Current lt
Efficiency vs Lolꢅ Current lt
±12IN, Forceꢅ Continuous μoꢅe
±52IN, Forceꢅ Continuous μoꢅe
ꢐꢋ
ꢐ0
ꢌꢋ
ꢌ0
ꢏꢋ
ꢏ0
ꢎꢋ
ꢐꢁ
ꢐ0
ꢋꢁ
ꢋ0
ꢏꢁ
ꢏ0
ꢎꢁ
ꢀ00
ꢐꢌ
ꢐ0
ꢁꢌ
ꢁ0
ꢏꢌ
ꢏ0
ꢎꢌ
ꢎ0
ꢍ.ꢍꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀꢋꢂ ꢆ ꢌ00ꢈꢉꢊ
ꢃꢄꢅ
ꢁ.ꢋꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢌ.0ꢂ ꢆ ꢇꢌ0ꢈꢉꢊ
ꢃꢄꢅ
ꢁ.0ꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢌꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢍ.ꢍꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢍ.ꢍꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢋꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢋ.ꢌꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢌ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢋꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.0ꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢌꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.0ꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢋꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.0ꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢌꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
0.ꢋ ꢀ.0 ꢀ.ꢋ ꢁ.0 ꢁ.ꢋ ꢍ.0 ꢍ.ꢋ ꢇ.0
0.ꢁ ꢀ.0 ꢀ.ꢁ ꢌ.0 ꢌ.ꢁ ꢍ.0 ꢍ.ꢁ ꢇ.0
0.ꢌ ꢀ.0 ꢀ.ꢌ ꢋ.0 ꢋ.ꢌ ꢍ.0 ꢍ.ꢌ ꢇ.0
ꢚꢃꢛꢜ ꢔꢄRRꢑꢕꢅ ꢗꢛꢙ
ꢚꢃꢛꢜ ꢔꢄRRꢑꢕꢅ ꢗꢛꢙ
ꢚꢃꢛꢜ ꢔꢄRRꢑꢕꢅ ꢗꢛꢙ
ꢇꢎꢋꢋ ꢝ0ꢀ
ꢇꢎꢌꢌ ꢝ0ꢍ
ꢇꢎꢁꢁ ꢝ0ꢌ
Efficiency vs Lolꢅ Current lt
142IN, Forceꢅ Continuous μoꢅe
Efficiency vs Lolꢅ Current lt
362IN, Forceꢅ Continuous μoꢅe
±2 Trlnsient ꢇesꢁonse, 142IN
ꢌ00
ꢊ00
ꢐꢀ
ꢐ0
ꢎꢀ
ꢎ0
ꢆꢀ
ꢆ0
ꢏꢀ
ꢏ0
ꢀꢀ
ꢐꢁ
ꢐ0
ꢍꢁ
ꢍ0
ꢎꢁ
ꢎ0
ꢏꢁ
ꢏ0
ꢁꢁ
+
V
OUTn
50mV/DIV
AC-COUPLED
+
I
OUTn
2A/DIV
ꢌꢁꢂ ꢆ ꢎꢁ0ꢈꢉꢊ
ꢃꢄꢅ
ꢋꢍꢁ ꢅ ꢊ.ꢋꢌꢈꢉ
ꢂꢃꢄ
ꢑ.ꢑꢁ ꢅ ꢍ00ꢇꢈꢉ
ꢂꢃꢄ
ꢌꢀꢂ ꢆ ꢍ00ꢈꢉꢊ
ꢃꢄꢅ
ꢌ.ꢍꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
4655 G06
ꢊꢀꢁ ꢅ ꢊ.ꢋꢌꢈꢉ
ꢂꢃꢄ
ꢋ.ꢀꢁ ꢅ ꢍ00ꢇꢈꢉ
ꢂꢃꢄ
ꢁ.0ꢂ ꢆ ꢁꢁ0ꢈꢉꢊ
ꢃꢄꢅ
ꢌ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
40µs/DIV
FIGURE 51 CIRCUIT, 24V
ꢊꢋꢁ ꢅ ꢊ.ꢊꢌꢈꢉ
ꢂꢃꢄ
ꢀꢁ ꢅ ꢀꢆꢀꢇꢈꢉ
ꢂꢃꢄ
ꢊ.ꢎꢁ ꢅ ꢍ00ꢇꢈꢉ
ꢂꢃꢄ
ꢊ.ꢀꢁ ꢅ ꢍ00ꢇꢈꢉ
ꢂꢃꢄ
ꢋ.ꢋꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢌ.ꢀꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢌ.0ꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
,
ꢀ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
IN
C
= C = 4.7µF, C
= 3 x 100µF,
INHn
Dn
OUTn
0.ꢁ ꢌ.0 ꢌ.ꢁ ꢀ.0 ꢀ.ꢁ ꢋ.0 ꢋ.ꢁ ꢇ.0
0.ꢀ ꢊ.0 ꢊ.ꢀ ꢋ.0 ꢋ.ꢀ ꢑ.0 ꢑ.ꢀ ꢍ.0
R
= N/A, R
= 20kΩ,
fSETn
ISETn
THn
C
= 6.8nF, R
= 681Ω,
THn
R
ꢚꢃꢛꢜ ꢔꢄRRꢑꢕꢅ ꢗꢛꢙ
ꢛꢂꢜꢝ ꢕꢃRRꢒꢖꢄ ꢘꢜꢚ
= N/A, C
= N/A,
EXTVCCn
EXTVCCn
ꢇꢏꢁꢁ ꢝ0ꢇ
ꢍꢏꢀꢀ ꢞ0ꢀ
2A to 4A LOAD STEP AT 2A/µs
Rev. 0
10
For more information www.analog.com
LTM4655
+
TA = 15°C, sinꢈꢆe chlnneꢆ ꢁositive-2ꢀUTn
oꢁerltion onꢆy, unꢆess otherwise noteꢅ.
TYPICAL PERFORMANCE CHARACTERISTICS
Stlrt-Uꢁ, Pre-Bils
Stlrt-Uꢁ, No Lolꢅ
Stlrt-Uꢁ, 4A Lolꢅ
RUNn
2V/DIV
RUNn
2V/DIV
RUNn
2V/DIV
+
V
OUTn
+
+
V
V
5V/DIV
OUTn
OUTn
5V/DIV
5V/DIV
I
DIODEn
1mA/DIV
PGOODn
2V/DIV
PGOODn
2V/DIV
PGOODn
2V/DIV
4655 G07
4655 G08
4655 G09
2ms/DIV
FIGURE 51 CIRCUIT, 36V
2ms/DIV
FIGURE 51 CIRCUIT, 36V
2ms/DIV
FIGURE 51 CIRCUIT, 36V
,
,
IN
IN
,
IN
C
= C = 4.7µF, C
= 2 x 22µF,
= 240kΩ,
C
= C = 4.7µF, C
= 2 x 22µF,
= 240kΩ,
INHn
Dn OUTn
INHn Dn OUTn
fSETn ISETn
C
= C = 4.7µF, C
= 2 x 22µF,
INHn
fSETn
PGDFBn
Dn
OUTn
R
R
= 124k, R
R
R
C
= 124k, R
fSETn
PGDFBn
ISETn
R
R
= 124k, R
= 240kΩ,
ISETn
= 95.3kΩ,
= 95.3kΩ,
THn
= 49.9Ω, C
PGDFBn
THn
= 95.3kΩ,
C
= 10nF, R
= 562Ω,
EXTVCCn
= 10nF, R
= 562Ω,
THn
THn
C
= 10nF, R
EXTVCCn
= 562Ω,
EXTVCCn
THn
THn
R
= 49.9Ω, C
= 1µF,
R
= 1µF,
EXTVCCn
NO LOAD
EXTVCCn
3Ω RESISTIVE LOAD
EXTVCCn
R
= 49.9Ω, C
PRE-BIASED TO 5V
= 1µF,
+
V
OUTn
THROUGH 1N4148 DIODE
Short Circuit, No Lolꢅ
Short Circuit, 4A Lolꢅ
+
V
+
OUTn
5V/DIV
V
OUTn
5V/DIV
I
INn
1A/DIV
I
INn
1A/DIV
4655 G10
4655 G11
10µs/DIV
10µs/DIV
FIGURE 51 CIRCUIT, 36V
IN
,
FIGURE 51 CIRCUIT, 36V ,
IN
INHn Dn OUTn
C
= C = 4.7µF, C
= 2 x 22µF,
C
= C = 4.7µF, C
= 2 x 22µF,
= 240kΩ,
INHn
fSETn
PGDFBn
Dn OUTn
R
R
= 124k, R
= 240kΩ,
R
= 124k, R
fSETn ISETn
ISETn
= 95.3kΩ,
THn
= 49.9Ω, C
R
= 95.3kΩ,
PGDFBn
C
= 10nF, R
EXTVCCn
= 562Ω,
EXTVCCn
C
= 10nF, R
= 562Ω,
THn
THn
THn
R
= 1µF,
R
= 49.9Ω, C
= 1µF,
EXTVCCn
EXTVCCn
NO LOAD PRIOR TO APPLICATION
OF OUTPUT SHORT-CIRCUIT
4Ω RESISTIVE LOAD PRIOR TO
APPLICATION OF OUTPUT
SHORT-CIRCUIT
Rev. 0
11
For more information www.analog.com
LTM4655
–
TA = 25°C, single channel negative-VOUTn
operation only, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
–3.3V Efficiency vs Load Current
–5V Efficiency vs Load Current
Output Current Capability*
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ ꢄ ꢅ00ꢆꢇꢈ
ꢂꢃ
ꢀꢁꢂ ꢅ ꢆ00ꢇꢈꢉ
ꢃꢄ
ꢀꢁꢂ ꢅ ꢁꢆ0ꢇꢈꢉ
ꢃꢄ
ꢀꢁꢂ ꢅ ꢆ00ꢇꢈꢉ
ꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁ ꢀ0.ꢂꢃ
ꢁ ꢀꢂ.ꢂꢃ
ꢁ ꢀꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢁ ꢀꢂꢃ
ꢀꢁ ꢄ ꢅ00ꢆꢇꢈ
ꢂꢃ
ꢁ ꢀꢂꢃꢄ
ꢁ ꢀꢂꢃꢄ
ꢁ ꢀꢂ0ꢃ
ꢁ ꢀꢂꢃꢄ
ꢀꢁꢂ ꢅ ꢆꢆ0ꢇꢈꢉ
ꢃꢄ
ꢀꢁꢂ ꢅ ꢆ00ꢇꢈꢉ
ꢃꢄ
ꢀꢁꢂ ꢅ ꢁ00ꢆꢇꢈ
ꢃꢄ
0
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢃ ꢄꢃꢀ
–12V Efficiency vs Load Current
–15V Efficiency vs Load Current
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ ꢄ ꢅꢆꢀꢇꢈꢉ
ꢂꢃ
ꢀꢁ ꢄ ꢀ00ꢅꢆꢇ
ꢂꢃ
ꢀꢁꢂ ꢅ ꢆꢁꢇꢈꢉꢊ
ꢃꢄ
ꢀꢁꢂ ꢅ ꢆꢇꢈꢉꢊꢋ
ꢃꢄ
ꢀꢁꢂ ꢅ ꢆ.ꢆꢇꢈꢉ
ꢃꢄ
ꢀꢁꢂ ꢅ ꢆ.ꢀꢇꢈꢉ
ꢃꢄ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃꢄꢃꢂꢅ
ꢀꢁꢂꢂ ꢃꢄꢁ
–24V Efficiency vs Load Current
Rated Operating Output Voltage
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
0
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁ0
ꢀꢁꢂꢃ ꢄꢅꢃRꢁꢆꢇꢈꢉ ꢁRꢃꢁ
ꢀꢁ ꢄ ꢀꢀ0ꢅꢆꢇ
ꢂꢃ
ꢀꢁꢂ ꢅ ꢀꢆꢇꢈ
ꢃꢄ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
*Current limit frequency-foldback activates at load currents higher than indicated curves. Continuous channel output current capability subject to details of
application implementation. Switching frequency set per Table 1. See Notes 2 and 3.
Rev. 0
12
For more information www.analog.com
LTM4655
–
TA = 25°C, single channel negative-VOUTn
operation only, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
–5V Transient Response, 24VIN
–24V Transient Response, 12VIN
Start-Up, No Load
ꢑ
ꢁꢎn
–
–
V
V
OUTn
OUTn
ꢘꢑꢗꢔꢁꢑ
100mV/DIV
AC-COUPLED
100mV/DIV
AC-COUPLED
ꢙ
ꢑ
ꢍꢃꢈn
ꢏ0ꢑꢗꢔꢁꢑ
–
–
I
I
Rꢃꢎn
ꢐꢑꢗꢔꢁꢑ
OUTn
OUTn
1A/DIV
0.4A/DIV
ꢋꢂꢍꢍꢔn
ꢘꢑꢗꢔꢁꢑ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄ0
ꢏꢕꢖꢗꢔꢁꢑ
40μs/DIV
FIGURE 48 CIRCUIT, 24V
20μs/DIV
FIGURE 48 CIRCUIT,
ꢀꢁꢂꢃRꢄ ꢅꢆ ꢇꢁRꢇꢃꢁ ꢉ ꢊꢋꢋꢌꢁꢇꢊꢈꢁꢍꢎ ꢍꢀ ꢏꢐꢑ
ꢒꢈꢊRꢈꢓꢃꢋ ꢁꢎꢈꢍ ꢎꢍ ꢌꢍꢊꢔ
ꢉ
,
ꢁꢎ
IN
C
C
R
R
= C
= C
= C = 4.7μF,
0.625A TO 1.25A LOAD STEP AT 0.625A/μs
INOUTn
= 47μF ×2, R
ISETn
INHn DGNDn
Dn
= 665kΩ,
OUTn
fSETn
= 100kΩ, R
EXTVCCn
= 36.5kΩ,
PGDFBn
= 20Ω, 1.8A TO 3.8A LOAD STEP AT 2A/μs
Start-Up, 1.25A Load
Start-Up, Pre-Bias
ꢌ
V
ꢊ
ꢋꢃꢈn
INn
5V/DIV
–
ꢕ0ꢊꢚꢒꢁꢊ
V
ꢁ
ꢒꢁꢋꢒꢄn
ꢕ00ꢘꢐꢚꢒꢁꢊ
OUTn
10V/DIV
–
I
Rꢃꢖn
ꢛꢊꢚꢒꢁꢊ
OUTn
500mA/DIV
PGOODn
5V/DIV
ꢍꢂꢋꢋꢒn
ꢛꢊꢚꢒꢁꢊ
ꢀꢁꢂꢂ ꢃꢄꢄ
ꢀꢁꢂꢂ ꢃꢄꢅ
1ms/DIV
ꢕꢘꢙꢚꢒꢁꢊ
ꢌ
FIGURE 48 CIRCUIT, APPLICATION OF 12V
START-UP INTO 19.2Ω LOAD
,
IN
ꢀꢁꢂꢃRꢄ ꢅꢆ ꢇꢁRꢇꢃꢁ ꢉ ꢊ
ꢍRꢄꢎꢏꢁꢐꢑꢄꢒ
ꢋꢃꢈn
ꢈꢋ ꢌꢓꢊ ꢈꢔRꢋꢃꢂꢔ ꢐ ꢕꢖꢅꢕꢅꢆ ꢒꢁꢋꢒꢄ ꢍRꢁꢋR
ꢈꢋ Rꢃꢖn ꢈꢋꢂꢂꢗꢁꢖꢂ ꢔꢁꢂꢔ
Short Circuit, No Load
Short Circuit, 1.25A Load
–
–
V
V
OUTn
OUTn
10V/DIV
10V/DIV
I
I
INn
INn
10A/DIV
10A/DIV
ꢀꢁꢂꢂ ꢃꢄꢂ
ꢀꢁꢂꢂ ꢃꢄꢀ
10μs/DIV
FIGURE 48 CIRCUIT,
10μs/DIV
FIGURE 48 CIRCUIT,
19.2Ω LOAD PRIOR TO APPLICATION OF
NO LOAD PRIOR TO APPLICATION OF
–
–
V
SHORT-CIRCUIT
V
SHORT-CIRCUIT
OUTn
OUTn
Rev. 0
13
For more information www.analog.com
LTM4655
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
SV
(C11): Channel 2 Filtered Voltage Supply for Small
INF2
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Signal Circuits. If powering the LTM4655’s 5V LDO from
channel 2’s supply for small signal circuits, electrically
connect SV
carrying up to 25mA.
and LDO with a short trace capable of
IN
INF2
V
(A1–A3, B3): Channel 1 Power Input Pins. Apply
IN1
input voltage and input decoupling capacitance directly
between V and a power ground (PGND) plane. Either
LDO (B12): Input to 5V LDO. Connect LDO to either
IN1
IN
IN
connect PGND to VOUT1– in noninverting step-down appli-
SVINF1 or SVINF2 with a short trace capable of carrying up
to 25mA, depending on which input rail is better suited
for powering the 5V LDO. If LDOIN is being powered from
+
cations, where V
voltage—or, connect PGND to V
is the regulated positive output
OUT1
+
in inverting buck-
OUT1
–
boost applications, where V
output voltage.
is the regulated negative
SV
or SV , no bypass capacitance from LDO to
INF1 INF2 IN
OUT1
GND is needed; otherwise, 0.1μF-to-1μF local bypass
capacitance is recommended.
V
(A6–A8, B8): Channel 2 Power Input Pins. Apply
IN2
–
input voltage and input decoupling capacitance directly
V
(A5, B5, C5, D5, E5, F5, G4–5, H3, H5, J3–5,
OUT1
between V and a power ground (PGND) plane. Either
K4–5, L4–5, M4–5): Negative Power Output of Channel 1.
IN2
connect PGND to VOUT2– in noninverting step-down appli-
Either connect V
to a PGND plane in noninverting
–
OUT1
+
+
cations, where V
voltage—or, connect PGND to V
boost applications, where V
output voltage.
is the regulated positive output
step-down applications, where V
is the regulated
OUT2
OUT1
+
+
in inverting buck-
positive output voltage—or, connect V
to PGND in
OUT2
is the regulated negative
inverting buck-boost applications, whOerUeT1V
regulated negative output voltage.
is the
–
–
OUT2
OUT1
–
–
V
(A4, B4, C4): Drain of Channel 1’s Primary Switching
SV
(E4, G2, H2): Signal Return of Channel 1. The
D1
OUT1
MOSFET. Apply at least one 4.7μF high frequency ceramic
decoupling capacitor directly from VD1 to VOUT1–. Give
this capacitor higher layout priority (closer proximity to
SV
pins are the reference node for channel 1’s con-
troOl UloTo1p. A small island of SVOUT1 copper should be
extended from the module and used to shield sensitive
–
the module) than any V decoupling capacitors.
channel 1 pins and signals from noise—such as those
IN1
–
routing to f
, ISET1a/b, and COMP1a/b. All SV
SET1
OUT1
V
(A9, B9, C9): Drain of Channel 2’s Primary Switching
D2
pins are connected to each other internal to the module.
MOSFET. Apply at least one 4.7μF high frequency ceramic
decoupling capacitor directly from VD2 to VOUT2–. Give
this capacitor higher layout priority (closer proximity to
–
Connect Pin H2 to V
The remaining SV
directly under the LTM4655.
OUT1
–
pins can be used for redundant
connectivity or roOuUteTd1 to an ICT test point for design-
for-test considerations, as desired. See the Applications
Information section for the layout checklist.
the module) than any V decoupling capacitors.
IN2
SV (C3): Channel 1 Input Voltage Supplies for Small
IN1
Signal Circuits. SV is the input to the INTV
LDO.
IN1
CC1
+
V
(K1–3, L1–3, M1–3): Positive Power Output of
COhUanT1nel 1. Bypass V
ule with at least 1μF. The remainder of V
bypass caps should be located near channel 1’sOloUaT1d.
Connect SV directly to V
.
IN1
IN1
+
–
to V
local to the mod-
OUT1
OUT1
OUT1
+
–
SV (C8): Channel 2 Input Voltage Supplies for Small
to V
IN2
Signal Circuits. SV is the input to the INTV
LDO.
IN2
CC2
+
Connect SV directly to V
.
Either connect V
boost applications, where V
to a PGND plane in inverting buck-
IN2
IN2
OUT1
–
is the regulated nega-
OUT1
SV
(B11): Channel 1 Filtered Voltage Supply for Small
INF1
–
tive output voltage—or, connect V
to a PGND plane
OUT1
Signal Circuits. If powering the LTM4655’s 5V LDO from
noninverting step-down applications, where VOUT1+ is the
regulated positive output voltage.
channel 1’s supply for small signal circuits, electrically
connect SV
carrying up to 25mA.
and LDO with a short trace capable of
IN
INF1
Rev. 0
14
For more information www.analog.com
LTM4655
PIN FUNCTIONS
+
+
VOSNS1 (G1, H1): Positive Voltage Sense Input for
VOSNS2 (G6, H6): Positive Voltage Sense Input for
+
+
+
+
Channel 1. Route a signal trace from V
to V
Channel 2. Route a signal trace from V
to V
OSNS1
OUT1
OSNS2 OUT2
at channel 1’s point-of-load (POL). This provides the feed-
at channel 2’s point-of-load (POL). This provides the feed-
back signal to channel 1’s control loop. In noisy environ-
back signal to channel 2’s control loop. In noisy environ-
+
+
ments, shield V
from electrical noise by sandwich-
ments, shield V
from electrical noise by sandwich-
ing the trace beOtwSNeSe1n PGND copper. Pins G1 and H1 are
ing the trace beOtwSNeSe2n PGND copper. Pins G6 and H6 are
electrically connected to each other internal to the mod-
electrically connected to each other internal to the mod-
+
+
ule, and thus it is only necessary to connect one V
ule, and thus it is only necessary to connect one V
OSNS1
OSNS2
+
+
+
+
pin to V
at the POL. The remaining V
pin can
pin to V
at the POL. The remaining V pin can
OSNS2
OUT1
OSNS1
OUT2
be used for redundant connectivity or routed to an ICT
be used for redundant connectivity or routed to an ICT
test point for design-for-test considerations, as desired.
test point for design-for-test considerations, as desired.
–
V
(A10–12, B10, C10, D10–11, E10–11, F10–11,
GND (D4, D9, D12): Ground Pins. The logic thresholds
for RUNn, PGOODn, and CLKINn are electrically referred
to GND. GND is also the reference voltage for the 5V-fixed
LDO and the CLKOUTn clock generator. Connect all GND
pins to a solid ground plane, PGND.
GO9U–T121, H8, H10–12, J8–10, K9–12, L9–12, M9–12):
Negative Power Output of Channel 2. Either connect
–
V
OUT2
to a PGND plane in noninverting step-down appli-
+
cations, where V
voltage—or, connect V
boost applications, where V
output voltage.
is the regulated positive output
OUT2
+
to PGND in inverting buck-
OUT2
RUN1 (F4): Channel 1 Run Control Pin. A voltage above
~1.2V (with respect to GND) commands the module to
regulate its output voltage. Undervoltage lockout (UVLO)
can be implemented by connecting RUN1 to the midpoint
–
is the regulated negative
OUT2
–
–
SV
SV
(E9, G7, H7): Signal Return of Channel 2. The
OUT2
pins are the reference node for channel 2’s con-
node formed by a resistor divider between V and GND.
troOl UloTo2p. A small island of SVOUT2 copper should be
extended from the module and used to shield sensitive
RUN1 features ~130mV of hysteresis.
IN1
–
RUN2 (F9): Channel 2 Run Control Pin. A voltage above
~1.2V (with respect to GND) commands the module to
regulate its output voltage. Undervoltage lockout (UVLO)
can be implemented by connecting RUN2 to the midpoint
channel 2 pins and signals from noise—such as those
–
routing to f
, ISET2a/b, and COMP2a/b. All SV
SET2
OUT2
pins are connected to each other internal to the module.
–
Connect Pin H7 to V
The remaining SV
directly under the LTM4655.
OUT2
node formed by a resistor divider between V and GND.
IN2
–
pins can be used for redundant
connectivity or roOuUteTd2 to an ICT test point for design-
for-test considerations, as desired. See the Applications
Information section for the layout checklist.
RUN2 features ~130mV of hysteresis.
INTV
(G3): Channel 1 Internal Regulator, 3.3V Output
CC1
with Respect to VOUT1–. Channel 1 internal control circuits
and MOSFET drivers derive power from INTVCC1 bias.
+
V
(K6–8, L6–8, M6–8): Positive Power Output of
COhUanT2nel 2. Bypass V
to V
local to the mod-
OUT2
Leave INTV
open circuit. An LDO generates INTV
CC1
CC1
+
–
OUT2
OUT2
from either SV or EXTV , when RUN1 is logic high
IN1
CC1
+
–
ule with at least 1μF. The remainder of V
bypass caps should be located near channel 2’sOloUaT2d.
to V
(RUN1–GND > 1.2V). The INTV LDO is turned off when
CC1
RUN1 is logic low (RUN1–GND < 1.2V). (See EXTV .)
CC1
+
Either connect V
boost applications, where V
to a PGND plane in inverting buck-
OUT2
–
is the regulated nega-
OUT2
–
tive output voltage—or, connect V
to a PGND plane
OUT2
noninverting step-down applications, where VOUT2+ is the
regulated positive output voltage.
Rev. 0
15
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LTM4655
PIN FUNCTIONS
INTV
(G8): Channel 2 Internal Regulator, 3.3V Output
ISET1a (F2): Accurate 50μA Current Source. Positive
CC2
with Respect to VOUT2–. Channel 2 internal control circuits
and MOSFET drivers derive power from INTVCC2 bias.
input to the error amplifier of channel 1. Connect a resis-
+
tor RISET1a = ((VOUT1 – VOUT1–)/50μA) from this pin
–
Leave INTV
open circuit. An LDO generates INTV
to SV
local to the module to program the desired
CC2
CC2
OUT1
+
–
from either SV or EXTV , when RUN2 is logic high
channel 1 output voltage magnitude, V
capacitor can be connected from ISET1a to SV
– V
. A
to
IN2
CC2
OUT1
OUT1
OUT1
–
(RUN2–GND > 1.2V). The INTV LDO is turned off when
CC2
RUN2 is logic low (RUN2–GND < 1.2V). (See EXTV .)
soft-start channel 1’s output voltage, i.e., reduce its start-
up inrush current. Connect ISET1a to ISET1b in order to
achieve default soft-start characteristics if desired. (See
ISET1b.)
CC2
EXTVCC1 (F3): External Bias, Auxiliary Input to the
–
INTVCC1 Regulator. When EXTVCC1–VOUT1 > 3.2V and
SVIN1 > 5V and RUN1–GND > 1.2V, the INTVCC1 LDO
derives power from EXTV
bias instead of SV . This
In addition, the channel 1 output of the LTM4655 can
track a voltage applied to this pin. (See the Applications
Information section.)
CC1
IN1
technique reduces LDO losses considerably, resulting in
a corresponding reduction in module junction tempera-
+
–
ture. For applications in which 4V < V
– V
<
OUT1
OUT1
ISET2a (F7): Accurate 50μA Current Source. Positive
+
28V, connect EXTV
to V
through a 15Ω~110Ω
CC1
OUT1
input to the error amplifier of channel 1. Connect a resis-
–
resistor and locally decouple EXTV
to V
with a
+
tor RISET2a = ((VOUT2 – VOUT2–)/50μA) from this pin
1μF ceramic capacitor. Otherwise, CcCo1nnectOEUXT1TV
to
–
CC1
to SV
local to the module to program the desired
OUT2
VOUT1– or leave EXTVCC1 open circuit. See the Applications
Information section.
+
–
channel 2 output voltage magnitude, V
capacitor can be connected from ISET2a to SV
– V
. A
to
OUT2
OUT2
OUT2
–
EXTVCC2 (F8): External Bias, Auxiliary Input to the
soft-start channel 2’s output voltage, i.e., reduce its start-
up inrush current. Connect ISET2a to ISET2b in order
to achieve default soft-start characteristics if desired.
(See ISET2b.)
–
INTVCC2 Regulator. When EXTVCC2–VOUT2 > 3.2V and
SVIN2 > 5V and RUN2–GND >1.2V, the INTVCC2 LDO
derives power from EXTV
bias instead of SV . This
CC2
IN2
technique reduces LDO losses considerably, resulting in
In addition, the channel 2 output of the LTM4655 can
track a voltage applied to this pin. (See the Applications
Information section.)
a corresponding reduction in module junction tempera-
ture. For applications in which 4V < VOUT2+ – VOUT2
<
–
+
28V, connect EXTV
to V
through a 15Ω~110Ω
CC2
OUT2
–
PGOOD1 (D1): Channel 1 Power Good Indicator, Open-
resistor and locally decouple EXTV
to V
with a
1μF ceramic capacitor. Otherwise, CcCo2nnectOEUXT2TV
to
Drain Output Pin. PGOOD1 is high impedance when
CC2
–
VOUT2– or leave EXTVCC2 open circuit. See the Applications
Information section.
PGDFB1–SVOUT1 is within approximately 7.5% of
0.6V. PGOOD1 is pulled to GND when PGDFB1 is outside
this range.
ISET1b (F1): 1.5nF Soft-Start Capacitor for Channel 1.
Connect ISET1b to ISET1a to achieve default soft-start
characteristics on channel 1, if desired. See ISET1a.
PGOOD2 (D6): Channel 2 Power Good Indicator, Open-
Drain Output Pin. PGOOD2 is high impedance when
–
PGDFB2–SVOUT2 is within approximately 7.5% of
ISET2b (F6): 1.5nF Soft-Start Capacitor for Channel 2.
Connect ISET2b to ISET2a to achieve default soft-start
characteristics on channel 2, if desired. See ISET2a.
0.6V. PGOOD2 is pulled to GND when PGDFB2 is outside
this range.
Rev. 0
16
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LTM4655
PIN FUNCTIONS
PGDFB1 (D2): Channel 1 Power Good Feedback
f
(E8): Channel 2 Oscillator Frequency Programming
SET2
+
Programming Pin. Connect PGDFB1 to V
through a
Pin. The default switching frequency of channel 2 is
resistor, R
. R
OUT1
configures thOeSvNoSlt1age thresh-
) for which PGOOD1 toggles its
400kHz. If needed, the programmed frequency can be
PGDFB1 PGDFB1
+
–
old of (V
– V
increased by connecting a resistor between fSET2 and
OUT1
–
state. If the PGOOD1 feature is used, set R
to:
SV
. Keep f -related trace lengths short. (See the
SET2
PGDFB1
OUT2
Applications Information section.) Note the synchroniza-
tion range of CLKIN2 is approximately 40% of the oscil-
ꢆꢇꢈꢉꢅ+ ꢊ ꢆꢇꢈꢉꢅ
ꢊ
(1)
Rꢀꢁꢂꢃꢄꢅ
=
ꢊ ꢅ ꢌ ꢍ.ꢎꢎꢏ
0.ꢋꢆ
lator frequency programmed by this f
pin.
SET2
CLKIN1 (B1): Channel 1 Mode Select and Oscillator
Synchronization Input. Referred to GND. Leave CLKIN1
open circuit for forced continuous mode operation.
Otherwise, leave PGDFB1 open circuit.
A small filter capacitor (220pF) internal to the LTM4655
on this pin provides high frequency noise immunity for
the PGOOD1 output indicator.
Alternatively, this pin can be driven so as to synchronize
the switching frequency of channel 1 to a clock signal.
In this condition, channel 1 operates in forced continu-
ous mode and the cycle-by-cycle turn-on of its primary
MOSFET is coincident with the rising edge of the clock
applied to CLKIN1. Note the synchronization range of
CLKIN1 is approximately 40% of the oscillator frequency
programmed by the fSET1 pin. (See the Applications
Information section.) The LTM4655 contains a built-in
dual 180° out-of-phase clock generator. Electrically con-
nect CLKIN1 to CLKOUT1 with a short trace, if desired,
to synchronize the switching frequency of channel 1
to CLKOUT1. If 0° phase interleaving is desired, connect
CLKOUT1 to both CLKIN1 and CLKIN2.
PGDFB2 (D7): Channel 2 Power Good Feedback
+
Programming Pin. Connect PGDFB2 to V
through a
resistor, R
. R
OUT2
configures thOeSvNoSlt2age thresh-
) for which PGOOD2 toggles its
PGDFB2 PGDFB2
+
–
old of (V
– V
OUT2
state. If the PGOOD2 feature is used, set R
ing to Equation 2.
accord-
PGDFB2
–
VOUT2+ – VOUT2
0.6V
⎡
⎢
⎤
RPGDFB2
=
– 1 • 4.99k
⎥
(2)
⎢
⎥
⎦
⎣
Otherwise, leave PGDFB2 open circuit.
A small filter capacitor (220pF) internal to the LTM4655
on this pin provides high frequency noise immunity for
the PGOOD2 output indicator.
CLKIN2 (B6): Channel 2 Mode Select and Oscillator
Synchronization Input. Referred to GND. Leave CLKIN2
open circuit for forced continuous mode operation.
f
(E3): Channel 1 Oscillator Frequency Programming
SET1
Alternatively, this pin can be driven so as to synchronize
the switching frequency of channel 2 to a clock signal. In
this condition, channel 2 operates in forced continuous
mode and the cycle-by-cycle turn-on of its primary
MOSFET is coincident with the rising edge of the clock
applied to CLKIN2. Note the synchronization range of
CLKIN2 is approximately 40% of the oscillator frequency
programmed by the fSET2 pin. (See the Applications
Information section.) The LTM4655 contains a built-in
dual 180° out-of-phase clock generator. Electrically
connect CLKIN2 to CLKOUT2 with a short trace, if desired,
to synchronize the switching frequency of channel 2
to CLKOUT2. If 0° phase interleaving is desired, connect
CLKOUT1 to both CLKIN1 and CLKIN2.
Pin. The default switching frequency of channel 1 is
400kHz. If needed, the programmed frequency can be
increased by connecting a resistor between fSET1 and
–
SV
. Keep f -related trace lengths short. (See the
SET1
OUT1
Applications Information section.) Note the synchroniza-
tion range of CLKIN1 is approximately 40% of the oscil-
lator frequency programmed by this f
pin.
SET1
Rev. 0
17
For more information www.analog.com
LTM4655
PIN FUNCTIONS
COMP1a (E2): Current Control Threshold and Error
Amplifier Compensation Node for Channel 1. The trip
threshold of channel 1’s current comparator increases
with a respective rise in COMP1a voltage. A small filter
cap (10pF) internal to the LTM4655 on this pin introduces
a high frequency roll-off of the error amplifier response,
yielding good noise rejection in the control loop. Often,
COMP1a is electrically connected to COMP1b in one’s
application, thus applying default loop compensation.
COMP2b (E6): Channel 2 Internal Loop Compensation
Network. For a majority of applications, the internal,
default loop compensation of the LTM4655 is suitable to
apply “as is”, and yields very satisfactory results: apply
the default loop compensation to channel 2’s control loop
by simply connecting COMP2a to COMP2b. When more
specialized applications require a personal touch to the
optimization of control loop response, this can be easily
accomplished by connecting a series resistor-capacitor
–
Loop compensation (a series resistor capacitor) can be
applied externally from COMP1a to SV
needed, instead. (See COMP1b.)
network from COMP2a to SV
open circuit.
and leaving COMP2b
OUT2
–
, if desired or
OUT1
IMON1a (C2): Channel 1 Power Inductor Current Analog
Indicator Pin and Current Limit Programming Pin. In
positive-VOUT step-down applications, only, the current
flowing out of this pin is equal to 1/40,000 of the average
channel 1 power inductor current. Optionally apply a par-
COMP2a (E7): Current Control Threshold and Error
Amplifier Compensation Node for Channel 2. The trip
threshold of channel 2’s current comparator increases
with a respective rise in COMP2a voltage. A small filter
cap (10pF) internal to the LTM4655 on this pin introduces
a high frequency roll-off of the error amplifier response,
yielding good noise rejection in the control loop. Often,
COMP2a is electrically connected to COMP2b in one’s
application, thus applying default loop compensation.
allel resistor-capacitor network to this pin and terminate
–
it to SV
torOcUuTr1rent.
in order to construct a voltage (V
–
OUT1
IMON1a
–
SV
) that is proportional to channel 1’s power induc-
IMON1a can be connected to IMON1b if the default resis-
tor capacitor termination network provided by IMON1b is
desired. If this analog indicator feature is not desired—
Loop compensation (a series resistor capacitor) can be
applied externally from COMP2a to SV
needed, instead. (See COMP2b.)
–
, if desired or
OUT2
–
or, in negative-VOUT buck-boost applications: connect
–
COMP1b (E1): Channel 1 Internal Loop Compensation
Network. For a majority of applications, the internal,
default loop compensation of the LTM4655 is suitable to
apply “as is”, and yields very satisfactory results: apply
the default loop compensation to channel 1’s control loop
by simply connecting COMP1a to COMP1b. When more
specialized applications require a personal touch to the
optimization of control loop response, this can be easily
IMON1a to SV
.
OUT1
–
If IMON1a–SV
exceeds a trip threshold of approxi-
OUT1
mately 2V, an IMON1 control loop servos channel 1
power inductor current accordingly and thus regulates
–
IMON1a–SV
at 2V. In this manner, the current limit
OUT1
inception threshold of channel 1 can be configured. (See
the Applications Information section.)
IMON1b (C1): Channel 1 Power Inductor Analog Indicator
accomplished by connecting a series resistor-capacitor
network from COMP1a to SV
open circuit.
–
Current Default Termination R-C Network. A 10k resis-
and leaving COMP1b
OUT1
tor in parallel with a 10nF capacitor and terminating to
–
SV
connect to this pin. Connect IMON1b to IMON1a
OUT1
to achieve default power inductor analog indicator current
–
characteristics: 1V (with respect to SV
) at full-scale
OUT1
(4A) load current in positive-VOUT, noninverting step-
down applications. (See IMON1a.) If unused, IMON1b
–
can be left open circuit or connected to SV
.
OUT1
Rev. 0
18
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LTM4655
PIN FUNCTIONS
VINREG2 (D8): Channel 2 Input Voltage Regulation
IMON2a (C7): Channel 2 Power Inductor Current Analog
Indicator Pin and Current Limit Programming Pin. In
positive-VOUT step-down applications, only, the current
flowing out of this pin is equal to 1/40,000 of the average
channel 2 power inductor current. Optionally apply a par-
Programming Pin. Optionally connect this pin to the mid-
point node formed by a resistor divider between V and
D2
–
–
V
. If VINREG2–SV
falls below approximately
OUT2
OUT2
2V, a VINREG2 control loop servos the power inductor
current accordingly and thus regulates VINREG2 at 2V
with respect to SVOUT2–. (See the Applications Information
section.)
allel resistor-capacitor network to this pin and terminate
–
it to SV
torOcUuTr2rent.
in order to construct a voltage (V
–
OUT2
IMON2a
–
SV
) that is proportional to channel 2’s power induc-
If this input voltage regulation feature is not desired on
channel 2, connect VINREG2 to INTV
.
CC2
IMON2a can be connected to IMON2b if the default resis-
tor capacitor termination network provided by IMON2b is
desired. If this analog indicator feature is not desired—
+
TEMP (J6): Temperature Sensor, Positive Input. Emitter
of a 2N3906-genre PNP bipolar junction transistor (BJT).
Optionally interface to temperature monitoring circuitry
such as LTC®2997, LTC2990, LTC2974 or LTC2975.
Otherwise leave electrically open.
–
or, in negative-VOUT buck-boost applications: connect
–
IMON2a to SV
.
OUT2
–
If IMON2a–SV
exceeds a trip threshold of approxi-
OUT2
TEMP– (J7): Temperature Sensor, Negative Input. Collector
and base of a 2N3906-genre PNP bipolar junction tran-
sistor (BJT). Optionally interface to temperature moni-
toring circuitry such as LTC2997, LTC2990, LTC2974 or
LTC2975. Otherwise leave electrically open.
mately 2V, an IMON2 control loop servos channel 2
power inductor current accordingly and thus regulates
–
IMON2a–SV
at 2V. In this manner, the current limit
OUT2
inception threshold of channel 2 can be configured. (See
the Applications Information section.)
IMON2b (C6): Channel 2 Power Inductor Analog Indicator
SW1 (H4): Switching Node of Channel 1 Switching
Converter Stage. Used for test purposes. May be routed
a short distance with a thin trace to a local test point to
monitor switching action of the converter, if desired, but
do not route near any sensitive signals; otherwise, leave
electrically open circuit.
Current Default Termination R-C Network. A 10k resis-
tor in parallel with a 10nF capacitor and terminating to
–
SV
connect to this pin. Connect IMON2b to IMON2a
OUT2
to achieve default power inductor analog indicator current
–
characteristics: 1V (with respect to SV
) at full-scale
OUT2
(4A) load current in positive-VOUT, noninverting step-
SW2 (H9): Switching Node of Channel 2 Switching
Converter Stage. Used for test purposes. May be routed
a short distance with a thin trace to a local test point to
monitor switching action of the converter, if desired, but
do not route near any sensitive signals; otherwise, leave
electrically open circuit.
down applications. (See IMON2a.) If unused, IMON2b
–
can be left open circuit or connected to SV
.
OUT2
VINREG1 (D3): Channel 1 Input Voltage Regulation
Programming Pin. Optionally connect this pin to the
midpoint node formed by a resistor divider between V
D1
–
and VOUT1–. If VINREG1–SVOUT1 falls below approxi-
mately 2V, a VINREG1 control loop servos the power
inductor current accordingly and thus regulates VINREG1
at 2V with respect to SVOUT1–. (See the Applications
Information section.)
LDOOUT (G12): Output of the LTM4655’s GND Referenced
5V-Fixed LDO. No bypass capacitance is needed. Powers
the clock generator internal to the LTM4655. Can deliver
up to 25mA of current.
If this input voltage regulation feature is not desired on
channel 1, connect VINREG1 to INTV
.
CC1
Rev. 0
19
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LTM4655
PIN FUNCTIONS
CLKSET (F12): Clock Generator Frequency Setting
Resistor Input. Apply a resistor, RCLKSET, between
LDOOUT and CLKSET. The clock frequency of CLKOUT1
The CLKOUT2 pins at locations B7 and C12 are electri-
cally connected together by a signal trace internal to the
module. It is pinned out as described purely to facilitate
routing of short traces to CLKIN2 and MOD. CLKOUT2
should be routed with minimal trace lengths. Minimize
stray capacitance to these pins.
and CLKOUT2 is set by R
according Equation 3.
CLKSET,
10kΩ
(3)
f
= 10MHz•
(CLKOUT1, CLKOUT2)
RCLKSET(kΩ)
MOD (E12): Modulation Setting Input. This three-state
Resistor values between 32.2k and 400k are supported,
corresponding to oscillator frequency settings of 3MHz
to 250kHz, respectively. Minimize stray capacitance to
this pin.
input selects among four modulation rate settings. The
MOD pin should be tied to GND for the f /16 modulation
OUT
rate. Leaving the MOD pin open circuit selects the f /32
OUT
modulation rate. The MOD pin should be electrically
connected to LDOOUT for the fOUT/64 modulation rate.
Electrically connecting CLKOUT2 (pin C12, only) to the
MOD pin (pin E12) turns the modulation off. Do not route
high speed digital logic or signals with fast edges near
CLKOUT1 (B2): Squarewave Output of Clock Generator for
Channel 1. 180° out-of-phase from CLKOUT2. Minimize
stray capacitance to this pin. Connect CLKOUT1 to
CLKIN1, if desired, to synchronize channel 1 to CLKOUT1.
If 0° phase interleaving is desired, connect CLKOUT1 to
both CLKIN1 and CLKIN2.
MOD. Be advised that the f /16, f /32 and f /64
OUT
OUT
OUT
modulation rates are not explicitly tested in factory ATE
to demonstrate their stated typical modulation rates; the
modulation off setting, however, is.
CLKOUT2 (B7, C12): Squarewave Output of Clock
Generator for Channel 2. 180° out-of-phase from
CLKOUT1. Minimize stray capacitance to these pins.
Connect CLKOUT2 (pin B7, only) to CLKIN2, if desired,
to synchronize channel 2 to CLKOUT2. If 0° phase inter-
leaving is desired, connect CLKOUT1 to both CLKIN1 and
CLKIN2.
NC (J1–2, J11–12): No Connect Pins, i.e., Pins with No
Internal Connection. The NC pins predominantly serve to
provide improved mounting of the module to the board.
For drop-in compatibility of the LTM4651/LTM4653 into
either half of a LTM4655 layout, these NC are recom-
mended to be left electrically open circuit.
To disable spread spectrum frequency modulation
(SFFM), connect CLKOUT2 (pin C12, only) to the MOD
pin (pin E12) with a short trace.
Rev. 0
20
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LTM4655
(Only One Channel Shown Within Dotted Outlines)
SIMPLIFIED BLOCK DIAGRAM
Rev. 0
21
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LTM4655
TEST CIRCUIT
V
24V
UP TO 4A
,
+
+
IN
OUT
NC
SW
V
V
INn
OUTn
C
4.7μF
29V TO 40V
INHn
V
OSNSn
SV
SV
INFn
INn
+
C
68µF
C
27µF
OUTLn
OUTHn
LOADn
RUNn
RUNn
GND
RUN – GND:
–
–
SV
OUTn
>1.2V
<1.07V
= ON
TYP
TYP
CLKINn
V
LTM4655
= OFF
OUTn
V
R
PGDFBn
196k
Dn
C
4.7μF
x2
Dn
INTV
CCn
PGDFBn
PGOODn
VINREGn
COMPna
EXTV
CCn
C
0.1μF
THn
COMPnb
IMONna
IMONnb
4655 TC01
R
499Ω
THn
f
SETn
ISETna ISETnb
PINS NOT SHOWN AND NOT TESTED
IN THIS TEST CIRCUIT:
R
57.6k
R
ISETn
480k
fSETn
LDO , LDO , CLKOUTn, CLKSET,
OUT
IN
+
–
MOD, TEMP , TEMP
Test Circuit 1. Positive-VOUT Configuration, Regulating VOUTn+, One Channel Shown
V
IN
V
PGOODn
PGDFBn
NC
SW
INn
3.6V
C
4.7μF
INHn
SV
SV
INFn
INn
TO 16V
R
PGDFB
196k
–
SV
RUNn
GND
RUNn
RUN – GND:
>1.2V = ON
OUTn
+
V
OUTn
+
TYP
TYP
CLKINn
C
C
*
OUTL
OUTH
LOAD
<1.07V
= OFF
27µF
68µF
–
–
V
LTM4655
Dn
V
V
–
OUTn
OUT
C
Dn
4.7μF
2x
–24V
SV
INTV
OUT
CCn
UP TO 1.25A
IMONna
IMONnb
AT V = 12V
IN
VINREGn
COMPna
COMPnb
R
**
EXTVCCn
0Ω
C
THn
f
SETn
0.1μF
EXTV
CCn
ISETna ISETnb
4655 TC02
PINS NOT SHOWN AND NOT TESTED
IN THIS TEST CIRCUIT:
R
499Ω
C
EXTVCCn
1μF
THn
R
57.6k
fSETn
R
480k
ISETn
LDO , LDO , CLKOUTn, CLKSET,
OUT
IN
+
–
MOD, TEMP , TEMP
*Polarized output capacitors C
, if used, must be rated to withstand ~0.3V typical reverse polarity prior to LTM4655 start-up,
OUTL
stemming from a weakly forward-biased body diode. In such cases, a Schottky diode should be connected between PGND and
VOUT– to limit the voltage. See the Applications Information section and Figures 49a and 49b.
**Outside the ATE Test environment, R
, if used, should not be 0Ω. See the Applications Information section.
EXTVCC
Test Circuit 2. Negative-VOUT– Configuration, Regulating VOUTn–, One Channel Shown
Rev. 0
22
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LTM4655
TEST CIRCUIT
V
IN
LDO
LDO
OUT
IN
4.5V
0.1μF
TO 40V
R
CLKSET
CLKSET
CLKOUT1
LTM4655
GND
PINS NOT SHOWN AND NOT TESTED
IN THIS TEST CIRCUIT:
CLKOUT2
MOD
+
V
V
, SV , SV
, V , RUNn, V
,
OUTn
INn
INn
INFn Dn
+
+
–
–
TEMP
TEMP
, V
OUTn
, SV
, CLKINn,
OSNSn
OUTn
–
INTV , EXTV , VINREGn, COMPna,
CCn
CCn
COMPnb, f
, ISETna, ISETnb, IMONna,
SETn
4655 TC03
IMONnb, PGDFBn, PGOODn, NC
Test Circuit 3. Clock-Generator, 5V LDO and Temperature-Sensor
TA = 25°C. Refer to Test Circuit 1 and Test Circuit 2.
DECOUPLING REQUIREMENTS
APPLICATION
SYMBOL
PARAMETER
CONDITIONS MIN
TYP MAX
UNITS
+
Positive-V
Operation
C
C
C
C
, C
External High Frequency Input Capacitor Requirement,
I
I
I
I
= 4A
= 4A
= 2A
= 2A
9.4
μF
OUT
INHn Dn
OUT
OUT
OUT
OUT
+
(Noninverting Step-Down)
(Test Circuit 1)
27V ≤ V –GND1 ≤40V, V
= 24V
IN1
OUT
+
–
–
External High Frequency Output Capacitor Requirement
22
9.4
22
μF
μF
μF
OUTHn
+
27V ≤ V –GND1 ≤ 40V, V
= 24V
IN1
OUT
–
Negative-V
(Inverting Output Buck-Boost)
(Test Circuit 2)
Operation
, C
INHn Dn
External High Frequency Input Capacitor Requirement,
OUT
–
3.6V ≤V –GND2 ≤ 16V, V
= –24V
IN2
OUT
External High Frequency Output Capacitor Requirement
OUTHn
–
3.6V ≤ V –GND2 ≤ 16V, V
= –24V
IN2
OUT
Rev. 0
23
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LTM4655
OPERATION
Power Module Overview
Each channel of the LTM4655 contains an independent,
integrated constant-frequency current mode regulator,
power MOSFETs, power inductor, EMI filter and other
supporting discrete components. The nominal switching
frequency range is from 400kHz to 3MHz, and the default
operating frequency is 400kHz. Each channel can optionally
be synchronized to its built-in clock oscillator CLKOUTn
pins or to an externally applied clock, from 250kHz to
3MHz. See the Applications Information section. Each
channel of the LTM4655 supports internal and external
control loop compensation. Internal loop compensation
is selected by connecting the COMPna and COMPnb pins.
Using internal loop compensation, the LTM4655 has suf-
ficient stability margins and good transient performance
with a wide range of output capacitors—even ceramic-
only output capacitors. For external loop compensation,
see the Applications Information section. LTpowerCAD®
is available for transient load step and stability analysis.
Input filter and noise cancellation circuitry reduces noise-
coupling to the module’s inputs and outputs, ensuring the
module’s electromagnetic interference (EMI) meets the
limits of EN55022 Class B (see Figure 7 through Figure 9).
The LTM4655 is a dual-channel non-isolated switch mode
DC/DC power supply. Each channel is fully independent
of the other. Each output can be configured for positive
or negative polarity. A channel configured for positive-
VOUT operation performs step-down DC/DC conversion
+
and regulates a positive output voltage, V
. A chan-
OUTn
–
nel configured for negative-VOUT operation performs
two-switch buck-boost DC/DC conversion and regulates
–
a negative output voltage, V
known as a ground-referred buck converter).
(this topology is also
OUTn
An integrated LDO provides up to 25mA of output current
at +5V (LDO ) with respect to GND. This LDO powers
OUT
an internal 2-phase clock oscillator, yielding flexibility to
operate the switching channels 180° out-of-phase from
each other.
A channel in positive-VOUT configuration (see Test
Circuit 1) can deliver up to 4A output current with a few
external input and output capacitors. Set by a single resis-
tor, R
, an LTM4655 channel regulates a positive out-
ISETn
put voltage, V
+
+ V
can be set to as low as 0.5V
OUTn
OUTn
to as high as 26.5V of V . Channels in this positive-V
Pulling the RUNn pin below 1.2V (with respect to GND)
forces the corresponding LTM4655 channel into a shut-
down state. A capacitor can be applied from ISETna to
INn
OUT
configuration can operate from a positive input supply
rail, V , between 3.1V and 40V. The typical application
INn
–
schematic is shown in Figure 45.
SVOUTn to program the output voltage ramp rate; or,
–
the default LTM4655 ramp rate can be set by connect-
ing ISETna to ISETnb; or, voltage tracking can be imple-
mented by interfacing rail voltages to the ISETna pin. See
the Applications Information section.
A channel in negative-VOUT configuration (see Test
Circuit 2) can deliver up to 4A output current with a few
external input and output capacitors. The output current
capability of the LTM4655 channel in this configuration is
dependent on its V and V
, as indicated in Figure 6.
, the LTM4655 channel
Multiphase operation can be employed by connecting the
CLKOUTn pins to their respective CLKINn pins—or, by
connecting an external clock source to the LTM4655’s
CLKINn pins. See the Typical Applications section.
INn
OUTn
ISETn
Set by a single resistor, R
–
–
regulates a negative output voltage, V
. V
can
OUTn
OUTn
be set to as low as –26.5V to as high as –0.5V. In this
negative-VOUT configuration, an LTM4655 channel can
LDO losses within the module incurred primarily due to
MOSFET driver power are optionally reduced by connect-
ing EXTVCCn to VOUTn+ through an RC filter or by connect-
operate from a positive input supply rail, V , between
INn
3.6V and 40V. The LTM4655 channel’s safe operating
area is defined by: VINn + |VOUTn–| ≤ 40V. The typical
ing EXTV
to a suitable voltage source.
CCn
application schematic is shown in Figure 48. Though
–
an LTM4655 channel configured to regulate V
is
For channels configured for positive-V
operation, the
OUTn
a ground-referred buck topology, built-in level-shift cir-
IMONna pin is an analog output currOeUnTt indicator that
sources a current proportional to its channel’s load current.
(For channels configured for negative-VOUT– operation, the
cuitry on the RUNn, CLKINn, and PGOODn pins result
in these pins being conveniently referred to GND (not
–
SV
).
OUTn
Rev. 0
24
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LTM4655
OPERATION
where D (unitless) is the duty-cycle of M , given by
n
Tn
IMONna pin does not support such a feature and must be
Equation 5:
connected to V –.) When IMONna is electrically con-
OUTn
nected to IMONnb, the voltage on the IMONna/IMONnb
node is proportional to load current—with 1V correspond-
ing to 4A load. If desired, IMONna can be interfaced to an
external parallel RC network instead of the one provided by
IMONnb. If IMONna ever exceeds 2V, a servo loop reduces
the LTM4655’s output current in order to keep IMONna
at or below 2V. Through this servo mechanism, a parallel
RC network can be connected to IMONna to implement an
average current limit function—if desired. When the feature
−
VOUTn+ − VOUTn
(5)
Dn =
−
V
− − VOUTn
INn
In rare cases where the minimum on-time restriction
is violated, the channel n frequency of the LTM4655
automatically and gradually folds back down to approxi-
mately one-fifth of its programmed switching frequency
to allow V
to remain in regulation. See the Frequency
OUT
Adjustment section. Be reminded of Notes 2 and 3 in
the Electrical Characteristics section regarding output
current guidelines.
is not needed, connect IMONna to V
–.
OUTn
The LTM4655 features an additional control pin called
VINREGn, which has a 2V servo threshold. This pin can be
used to as an extra control pin, e.g., to reduce channel input
current draw during input line sag (“brownout”) conditions.
Connect VINREGnto INTVCCn when this feature is not needed.
TEMP+ and TEMP– pins give access to a diode-con-
nected PNP transistor, making it possible to monitor the
LTM4655’s internal temperature—if desired.
Input Capacitors, Positive-V
Operation
OUT
The LTM4655 achieves low input conducted EMI noise
due to tight layout and high frequency bypassing of
MOSFETs M and M within the module itself. A small
Tn
Bn
filter inductor (400nH) is integrated in the input line (from
to V ), providing further noise attenuation—again,
V
INn
Dn
local to the switching MOSFETs. The V and V pins
External component selection is primarily determined by
the maximum load current and output voltage. Refer to
Table 11 and Table 12 and the Test Circuits for recom-
mended external component values.
Dn
INn
are available for external input capacitors—CDn and
C
—to form a high-frequency π filter. As shown in
INHn
the Simplified Block Diagram, the ceramic capacitor C
Dn
on the LTM4655’s V pins handles the majority of the
Dn
V to V
Conversion Ratios
RMS current into the DC/DC converter power stage and
IN
OUT
requires careful selection, for that reason.
There are restrictions on the V to V
conversion ratios
that the LTM4655 can achieve. The OmUaTximum duty cycle
of the LTM4655 is 96% typical. The VIN to VOUT mini-
mum dropout voltage is a function of load current when
operating in high duty cycle applications. As an example,
VOUTn(24VDC) from the Electrical Characteristics table
IN
See Figure 7 through Figure 9 for demonstration of
LTM4655’s EMI performance, meeting the radiated emis-
sions requirements of EN55022B.
The input capacitance, C , is needed to filter the pulsed
Dn
current drawn by M . To prevent excessive voltage sag
Tn
highlights the LTM4655’s ability to regulate 24V
at up
OUT
on V , a low-effective series resistance (low-ESR, such
Dn
to 4A from 29V , when running at a switching frequency,
IN
as an X7R ceramic) input capacitor should be used, sized
f
, of 1.5MHz.
SW
appropriately for the maximum C RMS ripple current
Dn
At very low duty cycles, the LTM4655’s on-time of MT
each switching cycle should be designed to exceed the
LTM4655 control loop’s specified minimum on-time of
(Equation 6)
IOUTn(MAX)
(6)
ICDn(RMS)
=
• Dn •(1–Dn)
ηn%
60ns, t , (guardband to 90ns) see Equation 4.
ON(MIN)
Dn
fSWn
where ηn% is the estimated efficiency of the chan-
nel n power module. (See Typical Performance
> TON(MIN)n
(4)
Characteristics graphs.)
Rev. 0
25
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LTM4655
OPERATION
Several capacitors may be paralleled to meet the appli-
External loop compensation can be applied from COMPna
–
cation’s target size, height, and C RMS ripple current
to SV
, if needed, for transient response optimization.
Dn
OUTn
rating. For lower input voltage applications, sufficient bulk
input capacitance is needed to counteract line sag and
transient effects during output load changes. The bulk
capacitor can be a switcher-rated aluminum electrolytic
capacitor or a Polymer capacitor. Suggested values for
Forced Continuous Operation
Leave the CLKINn pin open circuit to command chan-
nel n of the LTM4655 for forced continuous operation.
In this mode, the control loop is allowed to command the
inductor peak current to approximately –1A, allowing for
significant negative average current. Clocking the CLKINn
pin at a frequency within 40% of the target switching fre-
C
and C
are found in Table 11.
Dn
INHn
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM4655’s VINn
,
quency commanded by the f
pin synchronizes M ’s
SVINn, and VDn pins. A ceramic input capacitor combined
with trace or cable inductance forms a high Q (under-
damped) tank circuit. If the LTM4655 circuit is plugged
into a live supply, the input voltage can ring to twice its
nominal value, possibly exceeding the device’s rating.
This situation is easily avoided; see the Hot Plugging
Safely section.
SETn
Tn
turn-on to the rising edge of the CLKINn pin.
Output Voltage Programming, Tracking and Soft-Start
+
–
The LTM4655 regulates its output voltage, V
– V
,
OUTn
OUTn
according to the differential voltage present from ISETna to
–
SV
. In most applications, the output voltage is set by
OUTn
–
simply connecting a resistor, R
according to Equation 7.
, from ISETna to SV
,
ISETn
OUTn
Output Capacitors, Positive-V
Operation
OUT
Output capacitors C
the LTM4655’s V
Sufficient capacitance and low ESR are called for, to
meet the output voltage ripple, loop stability, and tran-
sient requirements. C
or polymer capacitor. C
typical output capacitance is 22μF (type X5R material, or
better), if ceramic-only output capacitors are used.
and C
are applied across
OUTLn
−
VOUTn+ − VOUTn
OUTHn
OUTn
–
+/VOUTn power output pins.
(7)
RISETn
=
50µA
Since the LTM4655 control loop servos its output voltage
–
can be a low ESR tantalum
is a ceramic capacitor. The
OUTLn
according to the voltage between ISETna and SV
:
OUTn
OUTHn
placing a capacitor, C , parallel to R
configures the
ramp-up rate of ISETna and thus theISoEuTtnput. In the time
domain, the output voltage ramp-up after the RUNn pin is
toggled from low to high (t = 0s) is given by Equation 8.
SSn
Table 11 shows a matrix of suggested output capacitors
optimized for 2A transient step-loads applied at 2A/μs.
Additional output filtering may be required by the system
designer, if further reduction of output ripple or dynamic
transient spike is required. The LTpowerCAD design tool is
available for transient and stability analysis. Stability crite-
ria are considered in the Table 11 matrix, and LTpowerCAD
is available for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the num-
ber of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as a
function of stability and transient response. LTpowerCAD
can be used to calculate the output ripple reduction as the
number of implemented phases increases by N times.
t
⎛
⎞
⎟
–
RISETn• CSSn
VOUTn(t)+ VOUTn(t)− =IISETna •RISETn • 1–e
⎜
(8)
⎜
⎟
⎝
⎠
The soft-start time, t , is defined as the time it takes for
SS
channel n’s output voltage to ramp from 0V to 90% of its
final value (Equation 9 or Equation 10)
tSSn = –RISETn •CSSn •In(1–0.9)
(9)
or
tSSn =2.3 •RISETn •CSSn
(10)
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26
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LTM4655
OPERATION
A default value of C
= 1.5nF can be implemented by
The LTM4655’s minimum on-time, t
, is specified
SSn
connecting ISETna to ISETnb. For other ramp-up rates,
as 60ns. For a practical design, it OisNnr(eMcIoNm) mended to
guardband to 90ns.
connect an external C capacitor parallel to R
.
SS
ISET
When starting up into a pre-biased V , the LTM4655
To configure channel n of the LTM4655 for a higher
OUT
stays in a sleep mode, keeping MTn and MBn off until
switching frequency than its default of 400kHz, apply
VISETna equals VOSNSn+—after which, the DC/DC con-
a resistor, RfSETn, between the fSETn pin and SVOUTn
fSETn
.
+
verter commences switching action and V
is ramped
R
is given (in MΩ) by Equation 13.
OUT
according to the voltage commanded by ISETna.
1
RfSETn(MΩ)=
(13)
+
Since the LTM4655 control loop servos its V
volt-
10pF •[fSWn(MHz)–0.4(MHz)]
age to match that of ISETna’s, the LTM465O5S’sNScnhannel
The relationship of R to programmed f
is shown
SWn
n output can be configured to track any voltage applied
fSETn
–
in Figure 1. See Table 11 and Table 12 for recommended
to ISETna, referenced to SV
. See Figure 52 for an
OUTn
f
and corresponding R
values for various com-
example of the LTM4655 configured as a DAC-controlled
bipolar-output programmable power supply.
SWn
fSETn
and V
+
–
binations of V , V
.
INn OUTn
OUTn
The LTM4655 can track the mirror-image of a posi-
tive rail to generate the negative half of a split-sup-
ply, as seen in Figure 50 (note the use of RTRACK and
ꢀ0
R
= R
|| R
).
ISET2
ISET1
TRACK
Frequency Adjustment
The default switching frequency (f
Rꢀ
ꢄꢅꢃ ꢆꢁꢂꢇ
ꢀ
ꢁꢂꢃn
) of channel n of the
SWn
LTM4655 is 400kHz. This is suitable for low-V (V
≤
IN INn
+
–
5V) applications and low-V
(V
– V
≤ 3.3V)
OUT OUTn
OUTn
applications. For a practical design, the LTM4655’s induc-
tor ripple current (∆I
) is suggested to be less than
0.ꢀ
nPK-PK
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0ꢁ
~2A
. Choose f
according to Equation 11.
PK-PK
SWn
Rf
(kΩ)
SETn
ꢀꢁꢂꢂ ꢃ0ꢄ
−
VOUTn+ − VOUTn • 1−D
(
)
n
(11)
Figure 1. Relationship Between RfSETn and Target fSWn
fSWn
=
Ln • ∆InPK-PK
where the value of LTM4655’s power inductor, Ln, is 4μH.
To avoid cycle-skipping, impose restrictions on f
, to
SWn
ensure minimum on-time criteria is met (Equation 12).
Dn
TONn(MIN)
(12)
fSWn
<
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LTM4655
APPLICATIONS INFORMATION
Power Module Protection
UVLO. Resistors are chosen by first selecting R (refer
Bn
to Figure 2 and Equation 14). Then:
The LTM4655’s current mode control architecture pro-
vides fast cycle-by-cycle current limit in an overcur-
rent condition, as shown in the Typical Performance
Characteristics section. If the output voltage collapses
sufficiently due to an overload or short-circuit condition,
minimum on-time will be violated and the internal oscil-
lator will then fold-back automatically to one-fifth of the
LTM4655’s programmed switching frequency—thereby
reducing the output current and affording the load a
chance to recover.
ꢆ
ꢇꢀꢂꢂꢈꢉ
R
ꢄn
Rꢀꢁn ꢂꢃꢁ
R
ꢅn
ꢊꢋꢌꢌ ꢍ0ꢎ
Figure 2. Undervoltage Lockout Resistive Divider
The LTM4655 ceases channel n switching action if the
channel’s internal temperatures exceed 165°C. The chan-
nel’s control IC resumes operation after a 10°C cool-down
hysteresis. Note that these typical parameters are based
on measurements in a lab oven and are not production
tested. This overtemperature protection is intended to
protect the device during momentary overload condi-
tions. The maximum rated junction temperature will be
exceeded when this overtemperature protection is active.
Continuous operation above the specified absolute maxi-
mum operating junction temperature may impair device
reliability or permanently damage the device. See Note 1
of the Electrical Characteristics table.
V
⎛
⎞
(14)
RAn =RBn
•
INn(ON) –1
⎜
⎟
1.2V
⎝
⎠
where V
is the input voltage at which the under-
voltage lockout is overcome and the supply turns on. The
turn-off voltage, V is given by Equation 15.
INn(ON)
V
INn
INn(OFF)
⎛
⎞
R
(15)
V
INn(OFF) =1.07V • An +1
⎜ ⎟
R n
⎝
⎠
B
If UVLO is not needed, RUNn can be connected to
LTM4655’s LDO pin.
OUT
When RUNn is below its threshold, UVLO of channel n
is engaged, M and M are turned off, INTV
ceases
The LTM4655 does not feature any specialized output
overvoltage protection beyond what is inherent to the
control loop’s servo mechanism.
Tn
Bn
CCn
–
to be regulated, and ISETna is discharged to SV
by
OUTn
internal circuitry.
Loop Compensation
RUN Pin Enable
External loop compensation may be preferred for some
applications and can be implemented easily, as follows:
The RUNn pin is used to enable the power module or
sequence the power module. The threshold is 1.2V. The
RUNn pin can be used to provide an undervoltage lockout
(UVLO) function by connecting a resistor divider from
the input supply to the RUNn pin, as shown in Figure 2.
Undervoltage lockout keeps channel n of the LTM4655
in shutdown until the supply input voltage is above a
certain voltage programmed by the user. The RUNn pin
hysteresis voltage prevents noise from falsely tripping
leave COMPnb open circuit; connect a series-RC net-
–
work R
and C
from COMPnb to SV
; in some
THn
THn
OUTn
instances, connect a capacitor (C
) from COMPna to
series-RC network).
THPn
THn THn
–
SV
(paralleling the R –C
OUTn
See Table 10 for suggested input and output capaci-
tances for a variety of operating conditions. Additionally,
the LTpowerCAD design tool is available for transient and
stability analysis.
Rev. 0
28
For more information www.analog.com
LTM4655
APPLICATIONS INFORMATION
(Figure 4). Applications with loads that experience large
load-step release, load dump or other mechanisms that
invoke reverse energy flow in the Figure 3 circuit may
need a suitably-rated Zener diode protection clamp, to
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitors (CDn and CINHn) of the LTM4655.
However, these capacitors can cause problems if the
LTM4655 is plugged into a live supply (see Analog Devices
Application Note 88 for a complete discussion). The low
loss ceramic capacitor combined with stray inductance in
series with the power source forms an under damped tank
limit the resulting transient voltage rise on SV /V
INn INn
and C
.
INHn
ꢀ
ꢀꢁn
ꢀ
ꢀꢁn
ꢀꢁ
ꢀꢁn
circuit, and the voltage at the V pin of the LTM4655 can
INn
ꢀꢁ
ꢂꢃꢄ
n
ꢀꢁꢂꢃꢄꢅꢅ
ring to twice the nominal input voltage, possibly exceed-
ing the LTM4655’s rating and damaging the part. If the
input supply is poorly controlled or the user will be plug-
ging the LTM4655 into an energized supply, the input
network should be designed to prevent this overshoot by
introducing a damping element into the path of current
flow. This is often done by adding an inexpensive elec-
ꢀ
ꢀꢁꢂn
ꢀ.ꢁꢂꢃ
ꢀꢁꢂꢂ ꢃ0ꢄ
Figure 3. Schottky Diode in Series with the Supply
trolytic bulk capacitor (C
of the LTM4655. The selection criteria for C
) across the input terminals
INLn
calls for:
INLn
ꢃ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂn
ꢀ
ꢀꢁꢂn
ꢀꢁn
ꢀꢁn
an ESR high enough to damp the ringing; a capacitance
value several times larger than CINHn; a suitable ripple cur-
ꢀꢁ
ꢀꢁn
rent rating. C
does not need to be located physically
ꢀꢁꢂꢃꢄꢅꢅ
ꢀ
ꢀ
ꢀꢁꢂn
ꢀꢁꢂꢃ
INLn
ꢀꢁꢂn
ꢀ.ꢁꢂꢃ
close to the LTM4655; it should be located close to the
application board’s input connector, instead.
ꢀꢁꢂꢂ ꢃ0ꢀ
Input Disconnect/Input Short Considerations
Figure 4. Schottky Diode from VOUTn+ to VINn
If at any point the input supply is removed with the output
voltage still held high through its capacitor, power will be
drawn from the output capacitor to power the module,
INTV
and EXTV
Connection
CCn
CCn
When RUNn is logic high, an internal low dropout regula-
tor regulates an internal supply, INTVCCn, that powers the
control circuitry for driving LTM4655’s channel n internal
MOSFETs. INTV
the LTM4655’s INTV
by default. The gate driver current through the INTV
LDO is about 20mA for a typical 1MHz application. The
internal LDO power dissipation can be calculated as
shown in Equation 16.
until the output voltage drops below the minimum SV
/
INn
V
INn
requirements of the module.
is regulated at 3.3V. In this manner,
However, if the SV /V pins are grounded while the
CCn
INn INn
is directly powered from SV
,
output is held high, regardless of the RUNn state, para-
CCn
INn
sitic body diodes inside the LTM4655 will pull current
CCn
+
from the output through the V
pins. Depending on
OUTn
the size of the output capacitor and the resistivity of the
short, high currents may flow through the internal body
diode, and cause damage to the part. If discharge of
−
−
P
= 20mA •(SV
− V
–3V)
(16)
INn
LDO_LOSSn(INTVCC)
OUTn
SV /V by the input source is possible, preventative
INn INn
measures should be taken to prevent current flow through
the internal body diode. Simple solutions would be plac-
The LDO draws current off of EXTV
instead of SV
CCn
INn
–
–
when EXTV –V
exceeds 3.2V and SV –SV
CCn OUTn
INn OUTn
ing a Schottky diode in series with the supply (Figure 3),
exceeds 5V. For output voltages of 4V and higher, EXTVCCn
+
or placing a Schottky diode from V
to SV /V
OUTn
INn INn
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LTM4655
APPLICATIONS INFORMATION
+
can be connected to V
through an RC-filter. When
OUTn
Note that for parallel applications, VOUT can be set by a single,
the internal LDO derives power from EXTV
SV , the internal LDO power dissipation is shown in
instead of
CCn
common resistor on the ISETna net (see Equation 18).
INn
−
VOUTn+ − VOUTn
Equation 17.
(18)
RISETn
=
50µA •N
−
(17)
P
= 20mA •(V
− V
−3V)
LDO_LOSSn(EXTVCC)
OUTn
OUTn
where N is the number of LTM4655 channels in parallel
configuration.
+
The recommended value of the resistor between V
OUTn
+
–
and EXTV
is roughly (V
– V ) • 4Ω/V. This
CCn
OUTn
OUTn
Depending on the duty cycle of operation, the output
voltage ripple achieved by paralleled, synchronized
LTM4655 modules may be considerably smaller than
what is yielded by a single-phase solution. Application
Note 77 provides a detailed explanation of multiphase
operation (relevant to parallel LTM4655 applications)
pertaining to noise reduction and output and input ripple
current cancellation. Regardless of ripple current cancel-
lation, it remains important for the output capacitance of
paralleled LTM4655 applications to be designed for loop
stability and transient response. LTpowerCAD is available
for such analysis.
resistor, R
, must be rated to continually dissipate
EXTVCCn
(0.02A) • R
²
. The primary purpose of this resistor
EXTVCCn
is to prevent EXTV
overstress under a fault condition.
CCn
For example, when an inductive short-circuit is applied
+
to the module’s output, VOUT may be briefly dragged
–
–
below V
—forward biasing the V
-to-EXTV
OUTn
OUTn CCn
body diode. This resistor limits the magnitude of current
flow in EXTV . If the application requires a low resistive
CCn
path to EXTV , apply a protective Schottky diode across
CCn
–
EXTV
OUTn
and V
; see Figure 52. Bypass EXTV
to
CCn
OUTn
CCn
–
V
with 1μF of X5R (or better) MLCC.
Multiphase Operation
Figure 5 illustrates the RMS ripple current reduction as a
function of the number of interleaved (paralleled and syn-
chronized) LTM4655 modules—derived from Application
Note 77.
Multiple LTM4655 channels and modules can be paralleled
for higher output current applications. For lowest input
and output voltage and current ripples, it is advisable to
synchronize paralleled LTM4655s to a clock (within 40%
0.ꢄ0
ꢈꢝꢜꢞꢙꢛꢐ
ꢇꢝꢜꢞꢙꢛꢐ
of the target switching frequency set by f
.
SETn
0.ꢁꢁ
ꢆꢝꢜꢞꢙꢛꢐ
ꢃꢝꢜꢞꢙꢛꢐ
ꢄꢝꢜꢞꢙꢛꢐ
LTM4655 channels and modules can be paralleled with-
out synchronizing circuits: just be aware that some beat-
frequency ripple will be present in the output voltage and
reflected input current by virtue of the fact that such mod-
ules are not operating at identical, synchronized switching
frequencies.
0.ꢁ0
0.ꢃꢁ
0.ꢃ0
0.ꢆꢁ
0.ꢆ0
0.ꢇꢁ
0.ꢇ0
0.ꢈꢁ
0.ꢈ0
0.0ꢁ
The LTM4655 device is an inherently current mode con-
trolled device, so parallel channels and modules will have
good current sharing as shown in Figure 45 and Figure 47.
To parallel LTM4655 channels and/or modules, con-
+
nect the respective COMPna, ISETna, and V
pins
of each LTM4655 together to share the curOreSnNtSnevenly.
In addition, tie the respective RUNn pins of paralleled
LTM4655 channels and/or modules together, to ensure
proper start-up and shutdown behavior.
0
0.ꢈ 0.ꢈꢁ 0.ꢇ 0.ꢇꢁ 0.ꢆ 0.ꢆꢁ 0.ꢃ 0.ꢃꢁ 0.ꢁ 0.ꢁꢁ 0.ꢄ 0.ꢄꢁ 0.ꢀ 0.ꢀꢁ 0.ꢂ 0.ꢂꢁ 0.ꢉ
ꢒ
ꢒ
ꢊꢋꢌꢍ ꢎꢍꢎꢏꢐ ꢑꢒꢓ
ꢕ ꢓ ꢒ ꢓ ꢘ
ꢖꢗ ꢔꢋꢌ
ꢔꢋꢌ
ꢃꢄꢁꢁ ꢅ0ꢁ
Figure 5. Normalized Input RMS Ripple Current vs Duty Cycle for
One to Six LTM4655 Channels (Phases)
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LTM4655
APPLICATIONS INFORMATION
Negative Output Current Capability Varies as a
these effects is shown the plots in Figure 6 and described
by Equation 19.
–
Function of V to V
Conversion Ratios,
INn
OUTn
–
Negative-V
Operation
OUT
ΔInPK–PK
⎛
⎝
⎞
V
• I
–
•η
n
⎜
⎟
⎠
INn
nPK
2
In negative-VOUT operation, the output current capability of
(19)
IOUTn(CAPABILITY)
where:
=
–
the LTM4655 has a strong dependency on the operating
V
INn – VOUTn
–
input (V ) and output (V
) voltages. See Figure 6.
INn
OUTn
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
∆InPK-PK is the channel n inductor ripple current, in
amps, and η (unitless) is the channel efficiency of the
n
LTM4655.
For completeness, ∆I
is given by Equation 20.
nPK-PK
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁ ꢀ0.ꢂꢃ
ꢁ ꢀꢂ.ꢂꢃ
ꢁ ꢀꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ΔInPK–PK
=
⎛
⎞
1
1
ꢁ ꢀꢂꢃ
(20)
Ln •fSWn
•
–
ꢁ ꢀꢂꢃꢄ
ꢁ ꢀꢂꢃꢄ
ꢁ ꢀꢂ0ꢃ
ꢁ ꢀꢂꢃꢄ
⎜
⎟
–
V
VOUTn
⎝
⎠
INn
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
where:
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢂ ꢃ0ꢁ
L is 4μH, the LTM4655 channel’s power inductor value,
and fSWn is the switching frequency of the LTM4655’s
channel, in MHz.
n
Figure 6. Channel Output Current Capability*,
Negative-VOUT Operation
*Current limit frequency-foldback activates at load cur-
rents higher than indicated curves. Continuous channel
output current capability subject to details of appli-
cation implementation. Switching frequency set per
Table 1. See Notes 2 and 3.
For a practical design, ∆InPK-PK is designed to be less
than ~2A
.
PK-PK
For a practical design, the LTM4655’s on-time of M
Tn
each switching cycle should be designed to exceed the
LTM4655 control loop’s specified minimum on-time
of 60ns, tON(MIN), (guardband to 90ns). For example,
Equation 21.
The reason for this is inherent in the two-switch buck-boost
topology employed by the LTM4655 when so-configured
for negative-VOUT operation. To protect the primary power
MOSFET (MTn) from overstress (see Simplified Block
Diagram), its peak current (InPK) is limited by control
circuitry to 6A. When M is on, observe that no current
flows to LTM4655’s ouTtnput; furthermore, observe that
Dn
fSWn
> TONn(MIN)
(21)
where D (unitless) is the duty-cycle of M , given by
n
Tn
Equation 22.
only when M is off does current flow to the output of
Tn
–
VOUTn+ – VOUTn
the LTM4655. As a consequence of this arrangement: for
a given output voltage, current limit inception activates
sooner at low line (higher, larger duty cycle) than at high
line (lower, smaller duty cycle). A further consequence
D=
(22)
–
VINn – VOUTn
Combining Equation 22 with Equation 19, it can be illus-
trative to see Equation 23.
is: for a given input voltage, the output power capability
–
of the LTM4655 is higher for lower-magnitude V
OUTn
ΔInPK–PK
⎛
⎝
⎞
⎟
⎠
(lower, smaller duty cycle) than for higher-magnitude
VOUTn (higher, larger duty cycle). The combination of
IOUTn(CAPABILITY) =(1–Dn)• I
–
• η
n
(23)
⎜
nPK
–
2
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LTM4655
APPLICATIONS INFORMATION
In rare cases where the minimum on-time restric-
tion is violated, the frequency of the affected LTM4655
channel(s) automatically and gradually folds back down to
filter inductor (400nH) is integrated in the input line (from
to V ) provides further noise attenuation—again,
V
INn
Dn
local to the switching MOSFETs. The V and V pins
Dn
INn
one-fifth of its programmed switching frequency to allow
are available for external input capacitors—CDn and
C —to form a high-frequency � filter. As shown in
INHn
–
V
to remain in regulation.
OUTn
the Simplified Block Diagram, the ceramic capacitor C
Dn
Be reminded of Notes 2, and 3 in the Electrical
Characteristics section regarding output current
guidelines.
on the LTM4655’s V pins handles the majority of the
Dn
RMS current into the DC/DC converter power stage and
requires careful selection, for that reason.
–
Input Capacitors, Negative-V
Operation
OUT
To meet the radiated emissions requirements of
EN55022B, an additional filter capacitor, CINOUTn, is
The LTM4655 achieves low input conducted EMI noise
due to tight layout and high-frequency bypassing of
needed—connecting from V to V
–. See Figure 7
OUTn
INn
through Figure 9 for EMI performance.
MOSFETs M and M within the module itself. A small
Tn
Bn
ꢓ0
ꢒ0
ꢑ0
ꢔ0
ꢕ0
ꢖ0
ꢗ0
0
ꢓ0
ꢢꢗꢣ ꢞꢤRꢄꢥꢤꢛꢅꢀꢃ
ꢢꢖꢣ ꢍꢈRꢅꢄꢜꢀꢃ
ꢚꢂꢦ ꢃꢄꢁꢄꢅ
ꢁꢈꢀꢧ ꢇꢄꢧꢅ ꢗ0ꢏ
ꢧꢂꢈꢜ ꢇꢄꢧꢅ ꢗ0ꢏ
ꢁꢈꢀꢧ ꢇꢄꢧꢅ ꢗ0ꢏ
ꢒ0
ꢑ0
ꢔ0
ꢕ0
ꢖ0
ꢗ0
0
ꢧꢂꢈꢜ ꢇꢄꢧꢅ ꢗ0ꢏ
ꢨ
ꢙꢤRꢁꢀꢃ
ꢢꢗꢣ ꢞꢤRꢄꢥꢤꢛꢅꢀꢃ
ꢢꢖꢣ ꢍꢈRꢅꢄꢜꢀꢃ
ꢚꢂꢦ ꢃꢄꢁꢄꢅ
ꢨ
ꢙꢤRꢁꢀꢃ
ꢘꢗ0
ꢘꢗ0
ꢕ0
ꢗꢕ0 ꢖꢕ0 ꢕꢕ0 ꢔꢕ0 ꢑꢕ0 ꢒꢕ0 ꢓꢕ0 ꢠꢕ0 ꢡꢕ0 ꢗ000
ꢕ0
ꢗꢕ0 ꢖꢕ0 ꢕꢕ0 ꢔꢕ0 ꢑꢕ0 ꢒꢕ0 ꢓꢕ0 ꢠꢕ0 ꢡꢕ0 ꢗ000
ꢔꢒꢑꢑ ꢙ0ꢠ
ꢔꢒꢑꢑ ꢙ0ꢒ
ꢙRꢈꢚꢆꢈꢛꢜꢝ ꢉꢁꢞꢟꢐ
ꢙRꢈꢚꢆꢈꢛꢜꢝ ꢉꢁꢞꢟꢐ
Figure 7. Radiated Emissions Scan of the LTM4655. Producing
24VOUT at 7A, from 36VIN. DC2898A Hardware. fSW = 1.2MHz.
Measured in a 10m Chamber. Peak Detect Method
Figure 8. Radiated Emissions Scan of the LTM4655. Producing
–24VOUT at 2A, from 12VIN , DC2899A Hardware. fSW = 1.2MHz.
Measured in a 10m Chamber. Peak Detect Method
ꢓ0
ꢁꢈꢀꢧ ꢇꢄꢧꢅ ꢗ0ꢏ
ꢧꢂꢈꢜ ꢇꢄꢧꢅ ꢗ0ꢏ
ꢒ0
ꢑ0
ꢔ0
ꢕ0
ꢖ0
ꢗ0
0
ꢢꢗꢣ ꢞꢤRꢄꢥꢤꢛꢅꢀꢃ
ꢢꢖꢣ ꢍꢈRꢅꢄꢜꢀꢃ
ꢚꢂꢦ ꢃꢄꢁꢄꢅ
ꢨ
ꢙꢤRꢁꢀꢃ
ꢘꢗ0
ꢕ0
ꢗꢕ0 ꢖꢕ0 ꢕꢕ0 ꢔꢕ0 ꢑꢕ0 ꢒꢕ0 ꢓꢕ0 ꢠꢕ0 ꢡꢕ0 ꢗ000
ꢔꢒꢑꢑ ꢙ0ꢡ
ꢙRꢈꢚꢆꢈꢛꢜꢝ ꢉꢁꢞꢟꢐ
Figure 9. Radiated Emissions Scan of the LTM4655. Producing
–12VOUT at 4A, from 12VIN. DC2899A Hardware. fSW = 700kHz.
Measured in a 10m Chamber. Peak Detect Method
Rev. 0
32
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LTM4655
APPLICATIONS INFORMATION
The input capacitance, C , is needed to filter the pulsed
capacitor. C
is a ceramic capacitor. The typical out-
Dn
OUTHn
current drawn by M . To prevent excessive voltage sag
put capacitance is 22μF (type X5R material, or better), if
ceramic-only output capacitors are used.
Tn
on V , a low-effective series resistance (low-ESR) input
capaDcnitor should be used, sized appropriately for the
For highest reliability designs, polarized output capaci
-
maximum C RMS ripple current (see Equation 24).
Dn
tors (C
) are not recommended, as there is a pos-
OUTLn
(24)
sibility of a diode-drop of reverse voltage appearing tran-
ICDn(RMS) =InPK • Dn •(1–Dn)
–
siently on V
during rapid application of input volt-
OUTn
age or when RUNn is toggled logic high (see Figure 49).
I
I
is maximum for D = 1/2. For D = 1/2,
CDn(RMS)
CDn(RMS)
n
n
–
When polarized capacitors are used on V
, contact
= 1/2 • I
or 3A. This simplification of the
OUTn
nPK
the capacitor vendor to understand what reverse volt-
age their polarized capacitor can withstand. Be advised,
polarized capacitor reverse voltage rating is sometimes
temperature-dependent.
worst-case condition is commonly used for design pur-
poses because even significant deviations in D do not
n
offer much relief, in practice. Furthermore: note that ripple
current ratings from capacitor manufacturers are often
based on 2000 hours of life; therefore, it is advisable to
significantly over-design C , and/or choose a capacitor
rated at a higher temperatDunre than required. Err on the
side of caution and contact the capacitor manufacturer to
understand the capacitor vendor’s derating methodology.
Output voltage ripple (∆VOUTn(PK-PK)–) is governed by
charge lost in COUTHn and COUTLn while MTn is on, in
addition to the contribution of a resistive drop across
the ESR of the output capacitors. This is expressed by
Equation 25.
Several capacitors may be paralleled to meet the appli-
ILOADn •D ILOADn •ESRn
(25)
ΔVOUTn(PK–PK)
≈
+
cation’s target size, height, and C RMS ripple current
Dn
COUTn •fSWn
Dn
rating. For lower input voltage applications, sufficient bulk
input capacitance is needed for C
to counteract line
sag and transient effects during IoNuLntput load changes.
Table 12 shows a matrix of suggested output capacitors
optimized for transient step-loads that are 50% of the full
Suggested values for C and C
are found in Table 12.
–
INHn
Take note that CDn isDcnonnected from VDn to VOUTn–,
whereas CINHn and CINLn are connected from VINn to
power ground; this is deliberate.
load capability for that combination of V , V
, and
INn OUTn
f
. The table optimizes total equivalent ESR and total
SW
bulk capacitance to yield the stated transient-load per-
formance. Additional output filtering may be required by
the system designer, if further reduction of output ripple
or dynamic transient spike is required. The LTpowerCAD
design tool is available for transient and stability analysis.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM4655’s VINn
,
SVINn, and VDn pins. A ceramic input capacitor combined
with trace or cable inductance forms a high Q (under-
damped) tank circuit. If the LTM4655 circuit is plugged
into a live supply, the input voltage can ring to twice its
nominal value, possibly exceeding the device’s rating.
This situation is easily avoided; see the Hot Plugging
Safely section.
Optional Diodes to Guard Against Overstress,
–
Negative-V
Operation
OUT
Just prior to output voltage start-up, a mechanism exists
whereby a diode-drop of reverse polarity can appear on
–
V
. See the Simplified Block Diagram and observe:
OUTn
just prior to output voltage start-up, SV bias current
INn
–
Output Capacitors, Negative-V
Operation
–
OUT
(ISVINn) flows through the module’s control IC, to SVOUTn
;
–
from there, the bias current (now I
) flows into
Output capacitors C
the LTM4655’s V
and C
OUTn
are applied across
SVOUTn
OUTHn
OUTLn
–
+
–
V
and through M ’s body diode, to SW . This cur-
/V
power output pins: suffi-
OUTn
Bn n
OUTn
rent (now I ) continues to flow—though the 4μH power
cient capacitance and low ESR are called for, to meet the
output voltage ripple, loop stability, and transient require-
Ln
+
inductor—to V
and thus ground, closing the con-
OUTn
trol IC bias circuit’s path. It is this current through M ’s
ments. C
can be a low ESR tantalum or polymer
Bn
Rev. 0
OUTLn
33
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LTM4655
APPLICATIONS INFORMATION
body diode that creates a diode-drop of reverse polarity
–
Frequency Adjustment, Negative-V
Operation
OUT
–
(positive voltage) on V
, as shown in Figure 49. The
OUTn
The default switching frequency (f
) of channel n of the
LTM4655 is 400kHz. This is suitable for mainly low-V or
SWn
voltage excursion is highest when RUNn toggles high
IN
because that is the instant when INTV
powers-up, with
–
–
a corresponding increase in ISVINn/ICSCVnOUTn–/ILn current
flow. With higher current flow, the forward voltage drop
low-V
applications (V < 5V or |V
| < 5V). For
OUT
INn
OUTn
a practical design, the LTM4655’s inductor ripple current
(∆
) is suggested to be less than ~2A
. From
PK–PK
nPK–PK
(V ) of M ’s body diode—and thus, the positive voltage
F
Bn
Equation 20, it follows that f should be chosen such
SW
–
excursion on V
is higher.
OUTn
that Equation 26).
If this transient voltage excursion is unwelcome for the
load or polarized output capacitors, minimize it with a
1
fSWn
=
⎛
⎞
1
1
–
+
(26)
Ln • ∆InPK-PK
•
–
low V Schottky diode that straddles V
and V
F
OUTn
(see Figure 48 circuit and Figure 4O9UTpnerformance).
Additionally, the voltage excursion can be empirically
reduced by increasing output capacitance.
⎜
⎟
–
V
VOUTn
⎝
⎠
INn
In some cases, the value of f
violates the supported minimum on-time of the LTM4655
(see Equation 21). If this occurs, choose f
according to Equation 12.
yielded by Equation 26
SWn
Lastly: in applications where it is anticipated that VINn
may be rapidly applied (e.g., <10μs) and CINOUTn is
instead
SWn
used, the resulting capacitor-divider network formed by
The primary consequence of using a lower switching fre-
quency than that dictated by Equation 26 is that the output
current capability of the LTM4655 is reduced, according
to Equation 23.
–
C
and C
||C
may transiently drag V
INOUTn
INLn INHn OUTn
positive. It is recommended to apply a low V Schottky
F
–
+
diode from V
to V
in such applications. The
OUTn
OUTn
reverse mechanism applies, as well: in applications where
it is anticipated that V may be rapidly discharged and
To configure the channel n of the LTM4655 for a higher
INn
switching frequency than 400kHz default, apply a resistor,
C
is used, the resulting capacitor-divider network
INOUTn
formed by C
–
R
, between the f
pin and SV
. R
is given
and C
||C
may transiently drag
fSETn
OUTn
fSETn
(in MΩ) by EquationS1ET3n.
INOUTn
INLn INHn
VOUTn– excessively negative. It is recommended to strad-
–
+
dle V
and V
with a TVS diode, if output voltage
excursions durinOgUVTn -discharge are anticipated.
OUTn
The relationship of R
in Figure 1.
to programmed f
is shown
SWn
fSETn
INn
See Table 1 and Table 12 for Recommended fSWn and
associated R
values for various combinations of V
fSETn
INn
–
and V
.
OUTn
–
Table 1. Recommended Channel n Switching Frequency (fSWn) and RfSETn for Common Combinations of VINn and VOUTn
,
Negative-VOUTn– Operation
–
V
(V)
OUTn
–0.5
–3.3
–5
–8
–12
–15
–20
–24
3.6
400kHz,
400kHz,
425kHz,
4.3MΩ
450kHz,
2.2MΩ
400kHz,
No R
No R
No R
fSETn
fSETn
400kHz,
fSETn
No R
400kHz,
400kHz,
fSETn
5
450kHz,
2.2MΩ
475kHz,
1.3MΩ
500kHz,
1MΩ
525kHz,
806kΩ
550kHz,
665kΩ
No R
No R
fSETn
fSETn
12
550kHz,
665kΩ
700kHz,
332kΩ
825kHz,
237kΩ
875kHz,
210kΩ
900kHz,
200kΩ
1MHz,
165kΩ
24 Drive CLKIN with a 200kHz
450kHz,
2.2MΩ
600kHz,
499kΩ
800kHz,
249kΩ
1.1MHz,
143kΩ
1.2MHz,
124kΩ
N/A
N/A
n
Clock, No R
fSETn
36
Not Recommended Due to
On-Time Criteria Violation
500kHz,
1MΩ
N/A Due to SOA Criteria Violation
Rev. 0
34
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LTM4655
APPLICATIONS INFORMATION
Radiated EMI Noise
1. θ , the thermal resistance from junction-to-ambient,
JA
is the natural convection junction-to-ambient air ther-
mal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD51-9 defined test board, which
does not reflect an actual application or viable operat-
ing condition.
The generation of radiated EMI noise is an inherent
disadvantage of switching regulators. Fast switching
turn-on and turn-off of the power MOSFETs—necessary
for achieving high efficiency—create high-frequency
(~30MHz+) ∆ /∆ changes within DC/DC converters. This
l
t
activity tends to be the dominant source of high-frequency
EMI radiation in such systems. The high level of device
integration within LTM4655—including optimized gate-
driver and critical front-end � filter inductor—delivers
low radiated EMI noise performance. Figure 7 through
Figure 9 show typical examples of LTM4655 meeting the
radiated emission limits established by EN55022 Class B.
2. θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section are consistent with those parameters defined by
JESD51-12 and are intended for use with finite element
analysis (FEA) software modeling tools that leverage the
outcome of thermal modeling, simulation, and correlation
to hardware evaluation performed on a µModule package
mounted to a hardware test board. The motivation for pro-
viding these thermal coefficients is found in JESD51-12
(“Guidelines for Reporting and Using Electronic Package
Thermal Information”).
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule regulator are on the bottom of the
package, it is rare for an application to operate such
that most of the heat flows from the junction to the top
of the part. As in the case of θ
, this value may
JCbottom
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to predict the
µModule regulator’s thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are, in and of themselves, not
relevant to providing guidance of thermal performance;
instead, the derating curves provided in this data sheet
can be used in a manner that yields insight and guid-
ance pertaining to one’s application-usage, and can be
adapted to correlate thermal performance to one’s own
application.
be useful for comparing packages but the test condi-
tions don’t generally match the user’s application.
4. θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resis-
tance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
and is really the sum of the θ
and the thermal
JCbottom
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from the
package, using a two sided, two layer board. This board
is described in JESD51-9.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD51-12; these coefficients
are quoted or paraphrased below:
A graphical representation of the aforementioned thermal
resistances is given in Figure 10; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
Rev. 0
35
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LTM4655
APPLICATIONS INFORMATION
ꢅꢆꢇꢈꢉꢊe ꢋꢌꢍꢎꢏꢌ
θ
ꢐꢓꢔꢏꢕꢎꢖꢔꢗꢕꢖꢗꢘꢆꢝꢎꢌꢔꢕ Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
ꢐꢘ
θ
ꢐꢓꢔꢏꢕꢎꢖꢔꢗꢕꢖꢗꢏꢘꢙꢌ
ꢏꢘꢙꢌ ꢚꢕꢖꢛꢜꢗꢕꢖꢗꢘꢆꢝꢎꢌꢔꢕ
ꢐꢏꢑꢇꢒ
ꢚꢕꢖꢛꢜ Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
ꢐꢓꢔꢏꢕꢎꢖꢔ
ꢘꢆꢝꢎꢌꢔꢕ
θ
ꢐꢏꢞꢇꢑ
ꢐꢓꢔꢏꢕꢎꢖꢔꢗꢕꢖꢗꢏꢘꢙꢌ
ꢏꢘꢙꢌ ꢚꢝꢖꢕꢕꢖꢆꢜꢗꢕꢖꢗꢝꢖꢘRꢋ
Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
ꢝꢖꢘRꢋꢗꢕꢖꢗꢘꢆꢝꢎꢌꢔꢕ
Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
ꢚꢝꢖꢕꢕꢖꢆꢜ Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
ꢀꢁꢂꢂ ꢃꢄ0
Figure 10. Graphical Representation of JESD51-12 Thermal Coefficients
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal oper-
ating conditions of a µModule regulator. For example, in
normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
temperature readings at different interfaces that enable
the calculation of the JEDEC-defined thermal resistance
values; (3) the model and FEA software is used to evaluate
the LTM4655 with heat sink and airflow; (4) having solved
for and analyzed these thermal resistance values and
simulated various operating conditions in the software
model, a thorough laboratory evaluation replicates the
simulated conditions with thermocouples within a con-
trolled environment chamber while operating the device
at the same power loss as that which was simulated. The
outcome of this process and due diligence yields the set
of derating curves provided in later sections of this data
sheet, along with well-correlated JESD51-12-defined θ
values provided in the Pin Configuration section.
for θ
and θ
, respectively. In practice, power
JCtop
JCbottom
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4655, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to differ-
ent junctions of components or die are not exactly linear
with respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also not ignoring practical realities—an approach has
been taken using FEA software modeling along with labo-
ratory testing in a controlled-environment chamber to rea-
sonably define and correlate the thermal resistance values
supplied in this data sheet: (1) Initially, FEA software is
used to accurately build the mechanical geometry of the
LTM4655 and the specified PCB with all of the correct
material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD51-9 and
JESD51-12 to predict power loss heat flow and
For positive-VOUT applications, the 12VIN and 24VIN power
loss curves in Figure 11 and Figure 12, respectively, can
be used with the load current derating curves in Figure 13
to Figure 24 for calculating an approximate θ thermal
JA
resistance for the LTM4655 with various heat sinking
and air flow conditions. For negative-V
applications:
use instead the –5VOUT, –12VOUT andO–U2T4VOUT power
loss curves in Figure 25 to Figure 27, respectively, in
combination with the load current derating curves in
Figure 28 to Figure 43. For split-supply applications,
total power loss within the module will dictate the thermal
derating; interpolate the relevant derating curves. These
thermal resistances represent demonstrated performance
of the LTM4655 on DC2898A and DC2899A hardware;
4-layer FR4 PCB measuring 97mm × 116mm × 1.6mm
using outer and inner copper weights of 2oz and 1oz,
Rev. 0
36
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LTM4655
APPLICATIONS INFORMATION
respectively. The power loss curves are taken at room
temperature, and are increased with multiplicative factors
with ambient temperature. These approximate factors are
listed in Table 1. (Compute the factor by interpolation,
for intermediate temperatures.) The derating curves
are plotted with the LTM4655’s outputs paralleled and
inteleaved, sourcing its maximum output capability, in
an environment with temperature-controlled ambient.
power loss curve at 4.9W (Figure 25), with the 1.1
multiplying factor at 60°C ambient (from Table 2). If the
60°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 60°C divided
by 5.39W yields a thermal resistance, θ , of 11.1°C/W—
JA
in good agreement with Table 6. Table 3 to Table 5 provide
equivalent thermal resistances for 1V, 5V, and 15V outputs
with and without airflow and heatsinking. Table 6 to
Table 8 provide equivalent thermal resistances for –5V,
–15V and –24V outputs with and without airflow and
heatsinking. The derived thermal resistances in Table 3
to Table 8 for the various conditions can be multiplied
by the calculated power loss as a function of ambient
temperature to derive temperature rise above ambient,
thus maximum junction temperature. Room temperature
power loss can be derived from the efficiency curves
in the Typical Performance Characteristics section and
adjusted with ambient temperature multiplicative factors
from Table 2.
The output voltages are 1V , 5V , 15V , –5V ,
OUT
OUT
OUT
OUT
–15V
and –24V . These are chosen to include the
OUT
OUT
lower and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived
from several temperature measurements in a controlled
temperature chamber along with thermal modeling
analysis. The junction temperatures are monitored while
ambient temperature is increased with and without air
flow, and with and without a heat sink attached with
thermally conductive adhesive tape. The power loss
increase with ambient temperature change is factored
into the derating curves. The junctions are maintained at
120°C maximum while lowering output current or power
while increasing ambient temperature. The decreased
output current decreases the internal module loss as
ambient temperature is increased. The monitored junction
temperature of 120°C minus the ambient operating
temperature specifies how much module temperature
rise can be allowed. As an example in Figure 30, the load
current is derated to 3.05A per channel (6.1A, combined)
at 60°C ambient with no airflow and no heat sink and the
room temperature (25°C) per channel power loss for this
Table 2. Power Loss Multiplicative Factors vs Ambient
Temperature
POWER LOSS MULTIPLICATIVE
AMBIENT TEMPERATURE
FACTOR
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
Up to 40°C
50°C
60°C
70°C
80°C
90°C
100°C
110°C
120°C
24V to –5V
at 3.05A out condition is 2.45W; 4.9W,
IN
OUT
combined. A 5.39W loss is calculated by multiplying the
4.9W room temperature loss from the 24V to –5V
IN
OUT
Rev. 0
37
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LTM4655
APPLICATIONS INFORMATION
Table 3. 1V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 11, Figure 12
Figure 11, Figure 12
Figure 11, Figure 12
Figure 11, Figure 12
Figure 11, Figure 12
Figure 11, Figure 12
AIRFLOW (LFM)
HEAT SINK
None
θ
JA
(°C/W)
IN
Figure 13, Figure 14, Figure 15
Figure 13, Figure 14, Figure 15
Figure 13, Figure 14, Figure 15
Figure 16, Figure 17, Figure 18
Figure 16, Figure 17, Figure 18
Figure 17, Figure 17, Figure 18
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
0
11.9
10.9
10.0
11.2
10.1
9.1
200
400
0
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
200
400
Table 4. 5V Output
DERATING CURVE
Figure 19, Figure 20
Figure 19, Figure 20
Figure 19, Figure 20
Figure 21, Figure 22
Figure 21, Figure 22
Figure 21, Figure 22
V
(V)
POWER LOSS CURVE
Figure 11, Figure 12
Figure 11, Figure 12
Figure 11, Figure 12
Figure 11, Figure 12
Figure 11, Figure 12
Figure 11, Figure 12
AIRFLOW (LFM)
HEAT SINK
None
θ
(°C/W)
JA
IN
12, 24
12, 24
12, 24
12, 24
12, 24
12, 24
0
11.9
10.9
10.0
11.2
10.1
9.1
200
400
0
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
200
400
Table 5. 15V Output
DERATING CURVE
Figure 23
V
IN
(V)
POWER LOSS CURVE
Figure 12
AIRFLOW (LFM)
HEAT SINK
None
θ
JA
(°C/W)
24
0
11.9
10.9
10.0
11.2
10.1
9.1
Figure 23
24
24
24
24
24
Figure 12
200
400
0
None
Figure 23
Figure 12
None
Figure 24
Figure 12
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 24
Figure 12
200
400
Figure 24
Figure 12
Rev. 0
38
For more information www.analog.com
LTM4655
APPLICATIONS INFORMATION
Table 6. –5V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 25
AIRFLOW (LFM)
HEAT SINK
None
θ
(°C/W)
JA
IN
Figure 28, Figure 29, Figure 30
Figure 28, Figure 29, Figure 30
Figure 28, Figure 29, Figure 30
Figure 31, Figure 32, Figure 33
Figure 31, Figure 32, Figure 33
Figure 31, Figure 32, Figure 33
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
0
11.9
10.9
10.0
11.2
10.1
9.1
Figure 25
200
400
0
None
Figure 25
None
Figure 25
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 25
200
400
Figure 25
Table 7. –15V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 26
AIRFLOW (LFM)
HEAT SINK
None
θ
(°C/W)
JA
IN
Figure 34, Figure 35, Figure 36
Figure 34, Figure 35, Figure 36
Figure 34, Figure 35, Figure 36
Figure 37, Figure 38, Figure 39
Figure 37, Figure 38, Figure 39
Figure 37, Figure 38, Figure 39
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
0
11.9
10.9
10.0
11.2
10.1
9.1
Figure 26
200
400
0
None
Figure 26
None
Figure 26
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 26
200
400
Figure 26
Table 8. –24V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 27
AIRFLOW (LFM)
HEAT SINK
None
θ
(°C/W)
JA
IN
Figure 40, Figure 41
Figure 40, Figure 41
Figure 40, Figure 41
Figure 42, Figure 43
Figure 42, Figure 43
Figure 42, Figure 43
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
0
11.9
10.9
10.0
11.2
10.1
9.1
Figure 27
200
400
0
None
Figure 27
None
Figure 27
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 27
200
400
Figure 27
Table 9. Heat Sink Manufacturer (Thermally Conductive Adhesive Tape Pre-Attached)
HEAT SINK MANUFACTURER
PART NUMBER
WEBSITE
Aavid Thermalloy
Cool Innovations
375424B00034G
4-050503PT411
LTN20069
www.aavid.com
www.coolinnovations.com
www.wakefield.com
Wakefield Engineering
Table 10. Thermally Conductive Adhesive Tape Vendor
THERMALLY CONDUCTIVE ADHESIVE
TAPE MANUFACTURER
PART NUMBER
WEBSITE
Chomerics
T411
www.chomerics.com
Rev. 0
39
For more information www.analog.com
LTM4655
APPLICATIONS INFORMATION
Table 11. Positive Output Voltage Response vs Component Matrix. Performance of a Channel of LTM4655 in Figure 51 Circuit, with
Values Here Indicated. Load-Stepping from 2A to 4A Load Current, at 2A/μs. Typical Measured Values
C
VENDORS
PART NUMBER
C
VENDORS
PART NUMBER
OUTHn
OUTHn
AVX
12066D107MAT2A (100μF, 6.3V, 1206 Case Size)
GRM31CR60J107M (100μF, 6.3V, 1206 Case Size)
JMK316BBJ107MLHT (100μF, 6.3V, 1206 Case Size)
C3216X5R0J107M (100μF, 6.3V, 1206 Case Size)
1210YD476MAT2A (47μF, 16V, 1210 Case Size)
GRM32ER61C476M (47μF, 16V, 1210 Case Size)
EMK325BJ476MM (47μF, 16V, 1210 Case Size)
12103D226MAT2A (22μF, 25V, 1210 Case Size)
TMK325BJ226MM (22μF, 25V, 1210 Case Size)
C3225X5R1E226M (22μF, 25V, 1210 Case Size)
AVX
12105D106MAT2A (10μF, 50V, 1210 Case Size)
GRM32ER61H106M (10μF, 50V, 1210 Case Size)
UMK325BJ106M (10μF, 50V, 1210 Case Size)
C3225X5R1H106M (10μF, 50V, 1210 Case Size)
PART NUMBER
Murata
Murata
Taiyo Yuden
TDK
Taiyo Yuden
TDK
AVX
C
/C VENDORS
INHn Dn
Murata
Taiyo Yuden
AVX
Murata
AVX
GRM32ER71K475M (4.7μF, 80V, 1210 Case Size)
12065C475MAT2A (4.7μF, 50V, 1206 Case Size)
GRM31CR71H475M (4.7μF, 50V, 1206 Case Size)
UMK316AB7475ML (4.7μF, 50V, 1206 Case Size)
C3216X5R1H475M (4.7μF, 50V, 1206 Case Size)
Murata
Taiyo Yuden
TDK
Taiyo Yuden
TDK
LOAD STEP LOAD STEP
TRANSIENT
DROOP
(mV)
PK-PK
DEVIATION
(mV)
RECOVERY
TIME
(μs)
V
V
R
C
R
R
f
R
R
EXTVCCn
OUTn
(V)
INn
(V)
THn
THn
ISETn
(kΩ)
PGDFBn
(kΩ)
SWn
fSETn
C
C
C
OUTHn
(Ω)
681
681
681
665
665
665
665
665
665
665
665
665
665
665
649
649
649
649
604
604
604
604
499
499
499
499
499
499
499
499
499
(nF)
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
8.2
8.2
8.2
8.2
8.2
8.2
8.2
8.2
10
(kHz)
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
550
575
500
800
1100
750
1200
1200
(kΩ)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
665
576
1000
249
143
287
124
124
(Ω)
INHn
Dn
1
5
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
4.7μF
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 3
100μF x 2
100μF x 2
100μF x 2
100μF x 2
47μF x 2
20
3.32
3.32
3.32
4.99
4.99
4.99
7.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
20
70
70
145
145
145
145
145
145
145
145
145
145
145
145
145
145
145
145
145
145
190
190
185
180
260
260
260
350
350
350
350
350
430
55
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
45
45
45
40
40
40
40
40
35
1
12
24
5
20
1
20
70
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
5
24
70
12
24
5
24
70
24
70
30.1
30.1
30.1
30.1
36
70
12
24
36
5
7.5
70
7.5
70
7.5
70
10
70
12
24
36
5
36
10
70
36
10
70
36
10
70
50
15.8
15.8
15.8
15.8
22.6
22.6
22.6
22.6
36.5
36.5
36.5
95.3
95.3
95.3
121
121
196
70
12
24
36
5
50
70
50
70
50
70
66.5
66.5
66.5
66.5
100
100
100
240
240
240
301
301
481
90
12
24
36
12
24
36
15
24
36
24
36
36
10
90
10
90
10
90
10
130
130
130
170
170
170
170
170
220
5
47μF x 2
10
20
5
47μF x 2
10
20
12
12
12
15
15
24
22μF x 2
10
49.9
49.9
49.9
60.4
60.4
100
22μF x 2
10
22μF x 2
10
22μF x 2
10
22μF x 2
10
10μF x 2
10
Rev. 0
40
For more information www.analog.com
LTM4655
APPLICATIONS INFORMATION
Table 12. Negative Output Voltage Response vs Component Matrix. Performance of Figure 48 Circuit with Values Here Indicated.
Load-Stepping from 50% of Full Scale (F.S.) to 100% of F.S. Load Current, in 1μs. Typical Measured Values.
C
VENDORS
PART NUMBER
C /C VENDORS
INHn Dn
PART NUMBER
OUTHn
AVX
12066D107MAT2A (100µF, 6.3V, 1206 Case Size)
GRM31CR60J107M (100µF, 6.3V, 1206 Case Size)
JMK316BBJ107MLHT (100µF, 6.3V, 1206 Case Size)
C3216X5R0J107M (100µF, 6.3V, 1206 Case Size)
1210YD476MAT2A (47µF, 16V, 1210 Case Size)
GRM32ER61C476M (47µF, 16V, 1210 Case Size)
EMK325BJ476MM (47µF, 16V, 1210 Case Size)
12103D226MAT2A (22µF, 25V, 1210 Case Size)
TMK325BJ226MM (22µF, 25V, 1210 Case Size)
C3225X5R1E226M (22µF, 25V, 1210 Case Size)
12105D106MAT2A (10µF, 50V, 1210 Case Size)
GRM32ER61H106M (10µF, 50V, 1210 Case Size)
UMK325BJ106M (10µF, 50V, 1210 Case Size)
C3225X5R1H106M (10µF, 50V, 1210 Case Size)
Murata
AVX
GRM32ER71K475M (4.7µF, 80V, 1210 Case Size)
12065C475MAT2A (4.7µF, 50V, 1206 Case Size)
GRM31CR71H475M (4.7µF, 50V, 1206 Case Size)
UMK316AB7475ML (4.7µF, 50V, 1206 Case Size)
C3216X5R1H475M (4.7µF, 50V, 1206 Case Size)
Murata
Taiyo Yuden
TDK
Murata
Taiyo Yuden
TDK
AVX
Murata
Taiyo Yuden
AVX
Taiyo Yuden
TDK
AVX
Murata
Taiyo Yuden
TDK
LOAD STEP LOAD STEP
C
C
C
Dn
(V TO V
BYPASS CAP)
CDGNDn
INHn
INOUTn
F. S.
C
TRANSIENT
DROOP
(mV)
PK-PK
DEVIATION
(mV)
RECOVERY
TIME
(μs)
OUTHn
–
–
–
–
–
–
–
V
V
LOAD (V
TO GND (V
TO V
(V TO GND
(CERAMIC
OUTPUT CAP)
R
R
f
R
R
EXTVCCn
(Ω)
OUTn
(V)
INn
INn
INn
OUTn
Dn
OUTn
Dn
ISETn
(kΩ)
PGDFBn
(kΩ)
SWn
fSETn
(kΩ)
(V) (A)
BYPASS CAP)
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
BYPASS CAP)
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
4.7µF
BYPASS CAP)
(kHz)
400
400
200**
400
400
450
500
400
550
600
450
700
800
475
825
1100
500
875
1200
550
1000
–0.5
–0.5
5
3.2
4
4.7µF
4.7µF
100µF × 4
100µF × 4
100µF × 4
100µF
10
N/A
N/A
2.2
75
150
190
190
130
330
355
310
235
340
380
235
340
330
270
290
325
170
380
400
220
275
55
60
60
25
50
50
40
45
60
55
30
30
27
32
25
25
25
32
28
45
30
12
4.7µF
4.7µF
10
N/A
N/A
2.2
90
–0.5* 24
4
4.7µF
4.7µF
10
N/A
N/A
2.2
90
–3.3
–3.3
–3.3
–3.3
–5
5
2.2
4.7µF
4.7µF
66.5
66.5
66.5
66.5
100
100
100
160
160
160
240
240
240
301
301
301
481
481
22.6
22.6
22.6
22.6
36.5
36.5
36.5
61.9
61.9
61.9
95.3
95.3
95.3
121
N/A
15
65
12 3.5
4.7µF
4.7µF
100µF × 2
100µF × 2
100µF × 2
47µF × 2
47µF × 2
47µF × 2
47µF
N/A
15
165
175
160
125
175
185
125
185
180
140
157
170
90
24
36
5
4
4
4.7µF
4.7µF
2200
1000
N/A
15
4.7µF
4.7µF
15
1.75
4.7µF
4.7µF
20
–5
12 3.2
24 3.85
4.7µF
4.7µF
665
499
2200
332
249
1300
237
143
1000
210
124
665
165
20
–5
4.7µF
4.7µF
20
–8
5
1.2
4.7µF
4.7µF
32.4
32.4
32.4
49.9
49.9
49.9
60.4
60.4
60.4
100
100
–8
12 2.3
24 3.1
4.7µF
4.7µF
47µF
–8
4.7µF
4.7µF
47µF
–12
–12
–12
–15
–15
–15
–24
–24
5
0.9
4.7µF
4.7µF
22µF
12 1.9
24 2.75
4.7µF
4.7µF
22µF
4.7µF
4.7µF
22µF
5
0.75
4.7µF
4.7µF
22µF
12 1.75
24 2.5
4.7µF
4.7µF
22µF
121
200
205
105
140
4.7µF
4.7µF
22µF
121
5
0.55
4.7µF × 2
4.7µF × 2
4.7µF × 2
4.7µF × 2
10µF × 2
10µF × 2
196
12 1.25
196
*Internal loop compensation is used with Table 12 settings. COMPna connects to COMPnb in Figure 48.
**To avoid violating minimum on-time criteria, drive CLKIN with a 200kHz, 50% duty cycle clock.
Rev. 0
41
For more information www.analog.com
LTM4655
Settings per Table 11 and Table 12.
APPLICATIONS INFORMATION—DERATING CURVES
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀꢁꢂ ꢀ ꢁꢂ0ꢃꢄꢅ
ꢀ.0ꢁ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ ꢀ ꢁ00ꢂꢃꢄ
ꢀ.ꢀꢁ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.0ꢁ ꢀ ꢁꢁ0ꢂꢃꢄ
ꢀ.ꢁꢂ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢀꢁ ꢀ ꢁ00ꢂꢃꢄ
ꢀ.ꢁꢂ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢁꢂ ꢀ ꢁ00ꢂꢃꢄ
ꢀ.ꢁꢂ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢁꢂ ꢀ ꢁ00ꢂꢃꢄ
ꢀ.ꢁꢂ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢁꢂ ꢀ ꢁ00ꢂꢃꢄ
ꢀ.0ꢁ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢁꢂ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
ꢀ.0ꢁ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢂ ꢃꢄ0
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢄ
Figure 11. 12VIN Power Loss
Curve
Figure 12. 24VIN Power Loss Curve
Figure 13. 5V to 1VOUT Derating
Curve, No Heat Sink
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢄꢀ
ꢀꢁꢂꢂ ꢃꢄꢂ
ꢀꢁꢂꢂ ꢃꢄꢁ
Figure 14. 12V to 1VOUT
Derating Curve, No Heat Sink
Figure 15. 24V to 1VOUT
Derating Curve, No Heat Sink
Figure 16. 5V to 1VOUT Derating
Curve, with BGA Heat Sink
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
Figure 19. 12V to 5VOUT
Derating Curve, No Heat Sink
Figure 17. 12V to 1VOUT Derating
Curve, with BGA Heat Sink
Figure 18. 24V to 1VOUT Derating
Curve, with BGA Heat Sink
Rev. 0
42
For more information www.analog.com
LTM4655
Settings per Table 11 and Table 12.
APPLICATIONS INFORMATION—DERATING CURVES
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢄꢄ
ꢀꢁꢂꢂ ꢃꢄ0
ꢀꢁꢂꢂ ꢃꢄꢅ
Figure 20. 24V to 5VOUT
Derating Curve, No Heat Sink
Figure 21. 12V to 5VOUT Derating
Curve, with BGA Heat Sink
Figure 22. 24V to 5VOUT Derating
Curve, with BGA Heat Sink
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀꢁ ꢄ ꢅ00ꢆꢇꢈ
ꢂꢃ
ꢀꢁꢂ ꢅ ꢆꢆ0ꢇꢈꢉ
ꢃꢄ
ꢀꢁꢂ ꢅ ꢆ00ꢇꢈꢉ
ꢃꢄ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢃꢄꢅ ꢆꢇꢈꢉꢇꢈ ꢀꢇRRꢄꢃꢈꢊꢂꢋ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢄꢂ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢂ
Figure 25. –5VOUT Power
Loss Curve
Figure 23. 24V to 15VOUT Derating
Curve, No Heat Sink
Figure 24. 24V to 15VOUT Derating
Curve, with BGA Heat Sink
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
0.ꢀ0
0
ꢀꢁ ꢄ ꢀ00ꢅꢆꢇ
ꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀꢁꢂ ꢅ ꢆꢇꢈꢉꢊ
ꢃꢄ
ꢀꢁ ꢄ ꢀꢀ0ꢅꢆꢇ
ꢂꢃ
ꢀꢁꢂ ꢅ ꢆ.ꢀꢇꢈꢉ
ꢃꢄ
ꢀꢁꢂ ꢅ ꢀꢆꢇꢈ
ꢃꢄ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢃꢄꢅ ꢆꢇꢈꢉꢇꢈ ꢀꢇRRꢄꢃꢈꢊꢂꢋ
ꢀꢁꢂꢃꢃꢄꢅ ꢆꢇꢈꢉꢇꢈ ꢀꢇRRꢄꢃꢈꢊꢂꢋ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢁ
ꢀꢁꢂꢂ ꢃꢄꢅ
Figure 28. 5V to –5VOUT Derating
Curve, No Heat Sink
Figure 26. –15VOUT Power Loss
Curve
Figure 27. –24VOUT Power
Loss Curve
Rev. 0
43
For more information www.analog.com
LTM4655
Settings per Table 11 and Table 12.
APPLICATIONS INFORMATION—DERATING CURVES
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.ꢁ0
0.ꢀ0
0
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
0.ꢀ0
0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄ0
Figure 31. 5V to –5VOUT Derating
Curve, with BGA Heat Sink
Figure 29. 12V to –5VOUT
Derating Curve, No Heat Sink
Figure 30. 24V to –5VOUT
Derating Curve, No Heat Sink
ꢀ.ꢁ0
ꢀ.ꢁꢂ
ꢀ.00
0.ꢀꢁ
0.ꢀ0
0.ꢀꢁ
0
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.ꢁ0
ꢀ.ꢁ0
0.ꢀ0
0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
ꢀ.ꢀ0
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢄꢀ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢄ
Figure 34. 5V to –15VOUT
Derating Curve, No Heat Sink
Figure 32. 12V to –5VOUT Derating
Curve, with BGA Heat Sink
Figure 33. 24V to –5VOUT Derating
Curve, with BGA Heat Sink
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
0.ꢀ0
0
ꢀ.ꢁ0
ꢀ.ꢁꢂ
ꢀ.00
0.ꢀꢁ
0.ꢀ0
0.ꢀꢁ
0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
0.ꢀ0
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢄꢂ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢁ
Figure 35. 12V to –15VOUT
Derating Curve, No Heat Sink
Figure 36. 24V to –15VOUT
Derating Curve, No Heat Sink
Figure 37. 5V to –15VOUT Derating
Curve, with BGA Heat Sink
Rev. 0
44
For more information www.analog.com
LTM4655
Settings per Table 11 and Table 12.
APPLICATIONS INFORMATION—DERATING CURVES
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
0.ꢀ0
0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
ꢀ.ꢁ0
ꢀ.00
0.ꢀ0
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢂꢂ ꢃꢄꢅ
Figure 39. 24V to –15VOUT Derating
Curve, with BGA Heat Sink
Figure 38. 12V to –15VOUT Derating
Curve, with BGA Heat Sink
ꢀ.ꢀ0
ꢀ.00
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0
ꢀ.ꢁ0
ꢀ.ꢀꢁ
ꢀ.00
ꢀ.ꢁꢂ
ꢀ.ꢁ0
ꢀ.ꢁꢂ
ꢀ.00
0.ꢀꢁ
0.ꢀ0
0.ꢀꢁ
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢀ0
ꢀꢁꢂꢂ ꢃꢀꢄ
Figure 41. 12V to –24VOUT Derating
Curve, No Heat Sink
Figure 40. 5V to –24VOUT Derating
Curve, No Heat Sink
ꢀ.ꢀ0
ꢀ.00
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0.ꢀ0
0
ꢀ.ꢁ0
ꢀ.ꢀꢁ
ꢀ.00
ꢀ.ꢁꢂ
ꢀ.ꢁ0
ꢀ.ꢁꢂ
ꢀ.00
0.ꢀꢁ
0.ꢀ0
0.ꢀꢁ
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢂ ꢃꢀꢄ
ꢀꢁꢂꢂ ꢃꢀꢄ
Figure 43. 12V to –24VOUT Derating
Curve, with BGA Heat Sink
Figure 42. 5V to –24VOUT Derating
Curve, with BGA Heat Sink
Rev. 0
45
For more information www.analog.com
LTM4655
APPLICATIONS INFORMATION
Safety Considerations
• Use large PCB copper areas for high current paths,
+
–
including V , V
and V
. Doing so helps to
INn OUTn
OUTn
The LTM4655 does not provide galvanic isolation from
VINn to VOUTn+/VOUTn–. There is no internal fuse. If
required, a slow blow fuse with a rating twice the maxi-
mum input current needs to be provided to protect the
unit from catastrophic failure.
minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output (and, if
used, input-to-output) capacitors next to the V , V ,
INn Dn
+
–
V
/V
pins to minimize high frequency noise.
OUTn
OUTn
The fuse or circuit breaker, if used, should be selected to
limit the current to the regulator in case of a MTn MOSFET
• Place a dedicated power ground layer underneath the
LTM4655.
fault. If M fails, the system’s input supply will source
Tn
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
very large currents to VOUTn+ through MTn. This can cause
excessive heat and board damage depending on how
much power the input voltage can deliver to this system.
A fuse or circuit breaker can be used as a secondary fault
protector in this situation. Each channel of the LTM4655
features its own, independent overcurrent and overtem-
perature protection.
• Do not put vias directly on pads, unless they are capped
or plated over.
• For each channel, use a separate SVOUTn– copper plane
for components connected to signal pins. Connect
–
–
SV
to V
directly under the module.
OUTn
OUTn
Layout Checklist/Example
+
• For parallel applications, connect the respective VOUTn
,
The high integration of LTM4655 makes the PCB board
layout straightforward. However, to optimize its electrical
and thermal performance, some layout considerations
are still necessary.
–
+
V
, V
, RUNn, ISETna, COMPna, PGOODn
OUTn
OSNSn
and IMONna pins, accordingly (see Figure 45).
• Bring out test points on the signal pins for monitoring.
Figure 44 gives a good example of the recommended
LTM4655 layout.
ꢅ
ꢀ
ꢁꢂꢃꢄ
ꢇ
ꢀ
ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢈꢉꢄ
ꢅ
ꢀ
ꢁꢂꢃꢆ
ꢈꢉꢆ
ꢅ
ꢀ
ꢁꢂꢃꢆ
ꢇ
ꢀ
ꢁꢂꢃꢆ
ꢅ
ꢀ
ꢁꢂꢃꢆ
ꢊꢋꢌꢌ ꢍꢊꢊ
Figure 44. Recommended PCB Layout, Package Top View
Rev. 0
46
For more information www.analog.com
LTM4655
TYPICAL APPLICATIONS
+
24V
,
OUT
UP TO 8A
SW1
SW2
NC
V
V
V
OUT1
IN
29V TO 40V
IN1
47µF
×4
4.7μF
4.7μF
90.9k
+
V
OSNS1
SV
IN1
–
LOAD
SV
OUT1
V
D1
–
V
OUT1
f
196k
SET1
PGDFB1
INTV
CC1
VINREG1
100Ω
1μF
EXTV
CC1
+
SV
SV
INF1
INF2
V
OSNS2
196k
LDO
IN
PGDFB2
100Ω
1μF
CLKOUT1
CLKIN1
EXTV
CC2
V
IN2
+
4.7μF
4.7μF
V
OUT2
SV
INF2
–
SV
OUT2
LTM4655
V
D2
–
V
OUT2
INTV
CC2
f
SET2
PGOOD1
PGOOD2
100k
90.9k
RUN1
PGOOD
5V
,
OUT
LDO
OUT
RUN
RUN2
INTV
UP TO 25mA
>1.2V = ON
TYP
66.5k
CC2
<1.07V = OFF
TYP
INTV
CC2
VINREG2
COMP1a
COMP1b
CLKSET
IMON1a
IMON1b
IMON2a
IMON2b
COMP2a
COMP2b
CLKOUT2
0.1µF
+
–
V
+
CC
V
D
D
TEMP
REF
470pF
LTC2997*
CLKIN2
MOD
>1k
4mV/K
–
V
V
PTAT
TEMP
GND
PTAT(FILTER)
C
FILTER
GND ISET1a ISET1b ISET2b ISET2a
4655 F45
OPTIONAL ANALOG OUTPUT
TEMPERATURE INDICATOR
240k
+
–
* PLACE 470pF DIRECTLY ACROSS THE LTC2997'S D /D PINS.
+
–
+
–
ROUTE TEMP /TEMP DIFFERENTIALLY TO D /D AND PROTECT FROM NOISE WITH GROUND SHIELDING.
•
+
–
TERMINATE (CONNECT) THE D /D GROUND SHIELD AT THE LTC2997 GND PIN, ONLY.
FOR BEST V PERFORMANCE, THE V PIN OF THE LTC2997 MUST BE LOCALLY BYPASSED AND QUIET.
PTAT CC
SEE LTC2997 DATA SHEET AND APRIL 2017 LT JOURNAL TECHNICAL ARTICLES.
Figure 45. Single 8A, 24V Output DC/DC μModule Regulator with Optional Analog Temperature Indicator
Rev. 0
47
For more information www.analog.com
LTM4655
TYPICAL APPLICATIONS
Rꢈꢍ
ꢌꢆꢃꢄꢅꢆ
ꢆ
ꢇꢈꢉ
ꢀ0ꢆꢃꢄꢅꢆ
ꢊꢋꢇꢇꢄ
ꢌꢆꢃꢄꢅꢆ
ꢀꢁꢂꢂ ꢃꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
Figure 46. Start-Up Waveforms at 36VIN, Figure 45 Circuit
ꢄ
ꢃ
ꢂ
ꢁ
ꢀ
0
ꢎꢗꢊꢐꢐꢏꢋ ꢀ
ꢎꢗꢊꢐꢐꢏꢋ ꢁ
ꢔꢀ
0
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈꢉꢈꢊꢋ ꢉꢌꢈꢍꢌꢈ ꢎꢌRRꢏꢐꢈ ꢑꢊꢒ
ꢃꢅꢄꢄ ꢓꢃꢆ
Figure 47. Current Sharing Performance of LTM4655 Channels in Figure 45 Circuit
Rev. 0
48
For more information www.analog.com
LTM4655
TYPICAL APPLICATIONS
R
PGOODn
100k
V
IN
3.3V
V
PGOODn
INn
12V
C
4.7μF
+
C
4.7μF
INHn
INOUTn
SV
V
INn
OSNSn
GND
+
V
Dn
C
10µF
×2
V
OUTn
OUTn
D1*
RUNn
RUNn
LOAD
LTM4655**
C
4.7μF
DGNDn
–
–24V
UP TO 1.25A
OUT
V
OUTn
C
–
Dn
INTV
SV
CCn
OUTn
4.7μF
R
PGDFBn
196k
VINREGn
COMPna
COMPnb
PGDFBn
R
100Ω
EXTVCCn
EXTV
CCn
f
IMONna
SETn
ISETna ISETnb
C
1µF
EXTVCCn
4655 F48
R
165k
fSETn
R
ISETn
481k
*D1 OPTIONAL (SEE EFFECT IN FIGURE 49): CENTRAL SEMICONDUCTOR P/N CMMSH1-40L
**ONE CHANNEL SHOWN. PINS NOT USED AND NOT SHOWN IN THIS CIRCUIT: NC, SV , IMONnb,
INFn
+
–
LDO , LDO , CLKSET, MOD, CLKOUTn, CLKINn, TEMP , TEMP
IN
OUT
Figure 48. 1.25A, –24V Output DC/DC μModule Regulator
Rꢈꢌnꢍ ꢎꢆꢃꢄꢅꢆ
Rꢈꢌnꢍ ꢎꢆꢃꢄꢅꢆ
ꢏꢐꢇꢇꢄnꢍ ꢎꢆꢃꢄꢅꢆ
ꢏꢐꢇꢇꢄnꢍ ꢎꢆꢃꢄꢅꢆ
ꢊ
ꢊ
ꢆ
ꢆ
ꢇꢈꢉn
ꢇꢈꢉn
ꢀ0ꢆꢃꢄꢅꢆ
ꢀ0ꢆꢃꢄꢅꢆ
ꢊ
ꢊ
ꢆ
ꢆ
ꢇꢈꢉn
ꢇꢈꢉn
ꢋ00ꢁꢆꢃꢄꢅꢆ
ꢋ00ꢁꢆꢃꢄꢅꢆ
ꢀꢁꢂꢂ ꢃꢀꢄꢅ
ꢀꢁꢂꢂ ꢃꢀꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
(b) Start-up Performance with D1 Installed.
(a) Start-up Performance with D1 Not Installed.
–
–
V
Reverse-Polarity at Start-Up is Transiently
V
Reverse-Polarity at Start-Up Transiently
OUTn
Limited to 360mV
OUTn
Reaches 500mV
Figure 49. Start-Up Waveforms at 12VIN, Figure 48 Circuit
Rev. 0
49
For more information www.analog.com
LTM4655
TYPICAL APPLICATIONS
+
12V
,
SW1
SW2
NC
OUT
UP TO 4A
V
V
OUT1
V
IN1
SV
IN
C
4.7μF
+
13V TO 28V
INH1
C
22µF
×2
V
OUTH1
IN1
OSNS1
–
LOAD1
V
D1
RUN1
SV
OUT1
–
C
4.7μF
D1
LDO
V
OUT
OUT1
R
PGDFB1
95.3k
f
SET1
INTV
INTV
CC1
PGDFB1
PGOOD1
EXTV
CC1
IMON1a
IMON1b
CC1
R
fSET1
124k
100k
VINREG1
COMP1a
COMP1b
SV
SV
INF2
LDO
CLKOUT1
CLKIN1
V
IN2
SV
V
D2
RUN2
R
EXTVCC1
49.9Ω
INTV
CC1
C
1μF
EXTVCC1
R
TH1
499Ω
INF1
5V
,
LDO
OUT
UP TO 25mA
IN
OUT
C
TH1
10nF
R
CLKSET
84.5k
CLKSET
+
LTM4655
V
OUT2
+
C
47µF
×2
C
OUTH2
INH2
4.7μF
V
SV
V
OSNS2
IN2
–
LOAD2
PGDFB2
OUT2
–
–12V
,
OUT2
OUT
UP TO 2.9A
C
D2
4.7μF
C
R
DGND2
4.7μF
LDO
OUT
95.3k
f
SET2
INTV
PGDFB2
PGOOD2
INTV
CC2
100k
R
CC2
EXTVCC2
49.9Ω
INTV
CC2
VINREG2
COMP2a
COMP2b
CLKOUT2
CLKIN2
MOD
R
fSET2
124k
EXTV
CC2
IMON2a
IMON2b
R
TRACK
10k
C
1μF
EXTVCC2
+
TEMP
–
TEMP
GND ISET1a ISET1b ISET2b ISET2a
4655 F50
R
ISET1
240k
R
ISET2
240k || 10k
(R = R
ISET2
|| R
)
TRACK
ISET1
Figure 50. Concurrent ±12V Output DC/DC μModule Regulator
+
12V
,
SW1
SW2
NC
OUT
UP TO 4A
V
V
V
IN1
SV
OUT1
IN
13V TO 40V
C
+
INH1
4.7μF
C
22µF
×2
V
OUTH1
IN1
OSNS1
–
LOAD1
V
D1
RUN1
SV
OUT1
–
C
4.7μF
D1
V
LDO
OUT1
OUT
R
PGDFB1
95.3k
f
SET1
INTV
INTV
CC1
PGDFB1
PGOOD1
EXTV
CC1
IMON1a
IMON1b
CC1
R
fSET1
124k
100k
VINREG1
COMP1a
COMP1b
SV
SV
INF2
LDO
R
EXTVCC1
49.9Ω
INTV
CC1
C
1μF
EXTVCC1
R
TH1
499Ω
INF1
5V
OUT
UP TO 25mA
,
LDO
IN
OUT
C
TH1
10nF
R
CLKOUT1
CLKIN1
CLKSET
84.5k
CLKSET
+
LTM4655
5V
OUT
UP TO 4A
,
V
IN2
V
V
SV
V
OUT2
+
C
INH2
4.7μF
OSNS2
C
47µF
×2
SV
IN2
V
D2
RUN2
OUTH2
–
LOAD2
PGDFB2
OUT2
–
C
OUT2
D2
4.7μF
R
LDO
OUT
36.5k
f
SET2
INTV
PGDFB2
PGOOD2
R
fSET2
INTV
CC2
100k
R
CC2
EXTVCC2
20Ω
124k
INTV
CC2
VINREG2
COMP2a
COMP2b
CLKOUT2
CLKIN2
MOD
EXTV
CC2
C
1μF
EXTVCC2
IMON2a
IMON2b
R
TH2
499Ω
+
TEMP
–
TEMP
C
TH2
10nF
GND ISET1a ISET1b ISET2b ISET2a
4655 F51
R
ISET2
100k
R
ISET1
240k
Figure 51. Dual 4A, 12V and 5V Output DC/DC μModule Regulator
Rev. 0
50
For more information www.analog.com
LTM4655
TYPICAL APPLICATIONS
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁ
ꢀ
ꢀꢀꢁ
ꢀ
ꢀ
ꢀꢁꢂꢁꢃ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂ ꢃꢄ ꢅꢆꢂ
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢀꢆꢇꢈꢉ
ꢀꢁ ꢂꢃ ꢄꢅ ꢆ
ꢀꢁ ꢂꢃ ꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁ
ꢀ.ꢁꢂꢃ
Rꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ00ꢅꢆꢂꢇ
1Ω
R
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂꢃꢄ
ꢀꢀꢁ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢀꢁ
ꢀꢁꢂ
R
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ0ꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
R
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢅ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢁꢃ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀ.ꢁꢂꢃ
ꢀ.ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢀꢃ
ꢀꢁ
ꢀ.ꢁꢂꢃ ꢀꢁꢂ
ꢀ
ꢁ
ꢀ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
Rꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢀꢆꢇꢈꢉ
ꢀꢁꢂ ꢃꢄ ꢀꢅꢆ ꢇ
ꢀꢁ ꢂꢃ ꢄꢅꢆ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ00ꢅꢆꢂꢇ
ꢀꢁꢂꢃ
ꢀꢀꢁ
ꢀꢁꢂꢂꢃꢄ
R
ꢀ
1Ω
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢄ
ꢀꢁꢂꢃ
ꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂ ꢀꢁꢂꢃꢄꢅ ꢀꢁꢂꢃꢄꢅ ꢀꢁꢂꢃꢄꢅ ꢀꢁꢂꢃꢄꢅ
10Ω
ꢀꢁ.ꢂꢃ
0.ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ ꢁ ꢂ.ꢃꢄ ꢅ ꢆ
ꢀꢁRꢂꢃꢀꢄꢁꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆꢁꢇꢈꢉ
0.ꢀꢁꢂ
ꢁ
ꢀ
ꢀ0ꢁ
0.ꢀꢁ
ꢀꢁꢂ ꢃꢄꢅ0ꢀꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢁ
ꢀ
ꢀ
0.ꢀꢁꢂ
ꢀꢁ.ꢂꢃ
0.ꢀꢁ
0.ꢀꢁꢂ
ꢀ
ꢀꢀ
10Ω
ꢀꢁꢂ
Rꢀꢁ
ꢀꢁꢂ
ꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
0.ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
0.ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢈ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢁ
ꢀꢁRꢂꢃꢄ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢀ
ꢀ0ꢁ
0.ꢀꢁ
ꢀꢁꢂ ꢃꢄꢅ0ꢀꢅꢆꢆ
ꢀ
ꢀꢁꢂꢃ
ꢁ
CSꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃꢃꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
Rꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢀ
0.ꢀꢁꢂ
ꢀꢁꢂꢂ ꢃꢄꢅꢆꢂ ꢇ ꢄꢈꢉ ꢄꢊꢊꢆꢋꢌꢄꢃꢋꢍꢈꢁ ꢋꢈꢎꢍRꢏꢄꢃꢋꢍꢈ ꢁꢂꢌꢃꢋꢍꢈ ꢎꢍR ꢈꢂꢐꢄꢃꢋꢑꢂ ꢍꢒꢃꢊꢒꢃ ꢌꢒRRꢂꢈꢃ ꢌꢄꢊꢄꢅꢋꢆꢋꢃꢓ
ꢀꢀꢁꢂꢃꢄ ꢄꢅꢆꢇꢈꢉ ꢂꢊ ꢆꢃꢋ0ꢌꢋ ꢂꢍ ꢉꢅꢎꢈ ꢉꢏꢐꢐꢆꢑ
Figure 52. A DAC-Controlled Bipolar-Output Programmable Power Supply
Rev. 0
51
For more information www.analog.com
LTM4655
PACKAGE DESCRIPTION
Table 13. LTM4655 Component BGA Pinout
PIN ID
A1
FUNCTION
PIN ID
B1
FUNCTION
CLKIN1
PIN ID
C1
FUNCTION
IMON1b
IMON1a
PIN ID
D1
FUNCTION
PGOOD1
PGDFB1
PIN ID
E1
FUNCTION
COMP1b
COMP1a
PIN ID
F1
FUNCTION
ISET1b
V
IN1
V
IN1
V
IN1
A2
B2
CLKOUT1
C2
D2
E2
F2
ISET1a
A3
B3
V
IN1
C3
SV
D3
VINREG1
E3
f
F3
EXTV
CC1
IN1
D1
SET1
–
A4
V
B4
V
C4
V
D4
GND
E4
SV
OUT1
F4
RUN1
D1
D1
–
–
–
–
–
–
A5
V
B5
V
C5
V
OUT1
D5
V
OUT1
E5
V
F5
V
OUT1
OUT1
OUT1
OUT1
A6
V
V
V
B6
CLKIN2
C6
IMON2b
IMON2a
D6
PGOOD2
PGDFB2
VINREG2
E6
COMP2b
COMP2a
F6
ISET2b
IN2
IN2
IN2
A7
B7
CLKOUT2
C7
D7
E7
F7
ISET2a
A8
B8
V
IN2
C8
SV
D8
E8
f
F8
EXTV
CC2
IN2
D2
SET2
–
A9
V
B9
V
C9
V
D9
GND
E9
SV
OUT2
F9
RUN2
D2
D2
–
–
–
–
–
–
–
–
A10
A11
A12
V
V
V
B10
B11
B12
V
C10
C11
C12
V
OUT2
D10
D11
D12
V
OUT2
V
OUT2
E10
E11
E12
V
V
F10
F11
F12
V
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
–
–
–
SV
SV
V
INF1
INF2
LDO
CLKOUT2
GND
MOD
CLKSET
IN
PIN ID
G1
FUNCTION
PIN ID
H1
FUNCTION
PIN ID
J1
FUNCTION
PIN ID
K1
FUNCTION
PIN ID
L1
FUNCTION
PIN ID
M1
FUNCTION
+
+
+
+
+
V
V
NC
V
OUT1
V
OUT1
V
OUT1
V
OUT1
V
OUT1
V
OUT2
V
OUT2
V
OUT2
V
OUT2
V
OUT2
V
OUT2
V
OUT2
V
V
V
V
V
V
V
V
V
V
V
V
V
OUT1
V
OUT1
V
OUT1
V
OUT1
V
OUT1
V
OUT2
V
OUT2
V
OUT2
V
OUT2
V
OUT2
V
OUT2
V
OUT2
OSNS1
OSNS1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
–
–
+
+
–
–
+
+
+
–
–
–
–
+
+
–
–
+
+
+
–
–
–
–
+
+
–
–
+
+
+
–
–
–
–
G2
SV
H2
SV
J2
NC
K2
L2
M2
OUT1
OUT1
–
–
G3
INTV
H3
V
J3
V
V
V
K3
L3
M3
CC1
–
OUT1
OUT1
OUT1
OUT1
–
–
+
–
–
–
–
G4
V
V
H4
SW1
J4
K4
L4
M4
OUT1
–
–
G5
H5
V
J5
K5
L5
M5
OUT1
OUT1
+
–
+
–
G6
V
H6
V
J6
TEMP
TEMP
K6
L6
M6
OSNS2
OSNS2
G7
SV
H7
SV
J7
K7
L7
M7
OUT2
OUT2
–
G8
INTV
H8
V
J8
V
V
V
K8
L8
M8
CC2
–
OUT2
OUT2
OUT2
G9
V
V
V
H9
SW2
J9
K9
L9
M9
OUT2
–
–
–
–
–
G10
G11
G12
H10
H11
H12
V
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
V
V
NC
LDO
NC
OUT
Rev. 0
52
For more information www.analog.com
LTM4655
PACKAGE DESCRIPTION
ꢠ
ꢵ ꢵ ꢥ ꢥ ꢥ
ꢠ
ꢧ . ꢭ ꢎ ꢌ 0
ꢌ . ꢮ ꢏ ꢌ 0
ꢙ . ꢙ ꢙ ꢌ 0
ꢣ . ꢏ ꢮ ꢌ 0
ꢏ . ꢭ 0 ꢌ 0
0 . ꢧ ꢣ ꢌ 0
0 . 0 0 0 0
0 . ꢧ ꢣ ꢌ 0
ꢏ . ꢭ 0 ꢌ 0
ꢣ . ꢏ ꢮ ꢌ 0
ꢙ . ꢙ ꢙ ꢌ 0
ꢌ . ꢮ ꢏ ꢌ 0
ꢧ . ꢭ ꢎ ꢌ 0
ꢟ ꢟ ꢟ
ꢠ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
53
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTM4655
PACKAGE PHOTOGRAPH
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
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9mm × 11.25mm × 3.32mm BGA
2.6V ≤ V ≤ 20V, 2.5V ≤ V
≤ 24V. I
≤ 15V,
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9mm × 15mm × 2.42mm BGA
3.6V ≤ V ≤ 60V, 0.97V ≤ V
IN
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Rev. 0
04/21
www.analog.com
ANALOG DEVICES, INC. 2021
54
相关型号：
LTM4655MPY
EN55022B Compliant 40V, Dual 4A or Single 8A Step-Down or 50W Inverting μModule Regulator
ADI
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