LTM4656EY_技术文档

LTM4656/LTM4656-1

Synchronous Boost µModule Regulator

with Input-Output Short Protection

FEATURES

DESCRIPTION

The LTM^®4656 is a complete high efficiency boost

µModule^®(power module) regulator with the switch-

ing controller, power FETs, inductor, and all supporting

components. Only a few input and output capacitors are

needed. Operating over an input voltage range of 4.5V to

28V, the LTM4656 supports an output voltage range of 6V

to 36V, set by a single external resistor. Its high efficiency

design delivers up to 5A continuous output current. An

in-line protection circuit sets the maximum input current,

and will trip off the input power if exceeded and retry (see

Typical Applications section).

n

Complete Boost Switch Mode Power Supply

Wide Input Voltage Range: 4.5V to 28V

Output Voltage Range: 6V to 36V

n

4A Continuous Output Current (12V , 24V

)

IN

OUT

2% Maximum Total Output Voltage Regulation

Over Load, Line and Temperature

Input Disconnect in Shutdown

n

Inrush Current Limit

External Frequency Synchronization

Programmable Frequency (350kHz to 780kHz)

Parallel Current Sharing

Up to 98% Efficiency

The high density boost design can convert up to 180W

of output power.

Selectable Burst Mode^®Operation

In-Line Overcurrent Protection

Fault protection features include overtemperature pro-

tection, and overcurrent protection input referred with

auto-retry. The µmodule is offered in a space saving

and thermally enhanced 16mm × 16mm × 7.07mm BGA

package. The LTM4656 is Pb-free and RoHS compliant.

Overtemperature Protection

LTM4656-1 Adjustable Compensation Version

16mm × 16mm × 7.07mm BGA Package

APPLICATIONS

All registered trademarks and trademarks are the property of their respective owners. Protected

by U. S. Patents, including 5408150, 5481178, 5705919, 5929620, 6177787, 6498466,

6580258, 6611131.

n

Telecom and Networking Equipment

Electronic Test Equipment

n

TYPICAL APPLICATION

12V_IN, 24V_OUTat 4A

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈ

24V Output Efficiency at 550kHz

ꢀ00

ꢀꢁ

ꢀ0

ꢀꢀ

ꢀꢁ

ꢀ0

ꢀ.ꢁ

ꢀ.0

ꢀ.ꢁ

ꢀ.0

ꢀ.ꢁ

ꢀ.0

ꢀ.ꢁ

ꢀ.0

0.ꢀ

0

ꢀ

ꢃꢄꢀ

ꢁꢂ

ꢀ

ꢁꢂꢃꢄ

ꢀ

ꢀꢁꢂꢃ

ꢁꢂ

ꢄꢄ

ꢀꢁꢂꢃ

ꢄꢄ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

SHDN

ꢀ.ꢁꢂꢃ

ꢀ.ꢁꢂ

ꢀꢁ

ꢀ ꢁ

ꢂꢃRꢄ ꢅꢄ

ꢀꢁꢂꢂꢃ

ꢀ0ꢁ

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈ

ꢀꢁ

ꢂꢃ

ꢀꢀ

ꢀꢁꢂꢃR ꢄꢁꢅꢅ

ꢀꢀꢁꢂ

0.ꢀꢁꢂ

ꢀꢁ ꢂꢃꢄꢁꢀꢅꢀ

ꢀ00ꢁꢂ

ꢀꢁꢂꢃꢄꢅꢄ

FLT

ꢀꢁꢂ ꢃꢄ ꢁꢃ

ꢀ

ꢄꢅꢀ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢆꢇꢈ

ꢄꢄ

ꢀ

ꢁꢂ

ꢀ0ꢁꢂ

ꢀꢁ0ꢂꢃ

Rꢀ

ꢁꢁ.ꢂꢃ

ꢀRꢁꢂ

ꢀ0.ꢁꢂ

ꢀꢁꢂꢃ

0

0.ꢀ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢀ.ꢁ

ꢀ

ꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ

ꢀꢁꢂꢁ ꢃꢄ0ꢅꢆ

PINS UNUSED IN THIS APPLICATION:

ꢀꢁ ꢀꢂꢃꢄ ꢃꢁꢅꢆꢀꢁR

ꢃꢇRꢈ Rꢉꢊꢈ ꢋꢌꢇꢍꢈ ꢎꢏꢊꢎꢏꢅꢈ ꢎꢐ

Rev. 0

1

Document Feedback

For more information www.analog.com

LTM4656/LTM4656-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

(See Capacitor Matrix, Pin Configuration Table)

V , SENSE1, BV , SW, V ,

OUT

IN

ꢆꢄꢙ ꢀꢁꢋꢚ

SHDN, UV, FLT, V

................................. –0.3V to 36V

ꢇ

ꢓ

ꢔ

ꢕ

ꢖ

ꢗ

ꢘ

ꢛ

ꢜ

ꢇ0

ꢇꢇ

ꢇꢓ

BIAS

INTV , MODE_PLLIN, PGOOD ................... –0.3V to 6V

CC

ꢈ

ꢃ

ꢉ

ꢊ

ꢫꢋꢂꢫꢋꢇ

FREQ, SS, COMP, V ...........................–0.3V to INTV

FB

CC

RUN ............................................................. –0.3V to 5V

ꢀ

ꢍꢂꢊ

ꢃꢀ

ꢁꢂ

TMR......................................................................0.5mA

+

–

TEMP , TEMP ................... <0.7V Across Pins, No More

than 5mA (Current Source)

ꢀ

ꢌꢃ

ꢍꢂꢊ

ꢂꢉ

ꢋ

ꢌ

Operating Junction Temperature (Note 2)..–40 to 125°C

Storage Temperature Range ...................... –55 to 125°C

Peak Solder Reflow Body Temperature................. 245°C

ꢀ

ꢍꢂꢊ

ꢉꢄꢒꢙ ꢫꢫ ꢙꢍꢄꢄꢊ

ꢃꢁꢈꢫ

SHDN

ꢒꢄꢊꢋꢯꢙꢑꢑꢁꢂ

ꢍꢂꢊ

ꢅꢀ

ꢁꢂꢆꢀ

ꢆꢒR

ꢉꢉ

ꢍ

ꢭ

ꢬ

ꢆꢋꢒꢙ

ꢌRꢋꢮ Rꢅꢂ

FLT

ꢆꢋꢒꢙ

Note: Not recommended for upside-down reflow.

ꢎ

ꢏ

ꢫꢚ

ꢍꢂꢊ

ꢐ

ꢀ

ꢄꢅꢆ

ꢑ

ꢍꢂꢊ

ꢒ

ꢃꢍꢈ ꢙꢈꢉꢐꢈꢍꢋ

ꢇꢕꢕꢝꢑꢋꢈꢊ ꢞꢇꢗꢟꢟ × ꢇꢗꢟꢟ × ꢘ.0ꢘꢟꢟꢠ

ꢢ ꢇꢓꢖꢣꢉꢤ θ ꢢ ꢇꢇ.ꢛꢣꢉꢥꢚꢤ

ꢆ

ꢏꢒꢈꢡ

ꢏꢈ

θ

ꢢ ꢘ.ꢇꢣꢉꢥꢚꢤ θ

ꢢ ꢕ.ꢕꢣꢉꢥꢚ ꢞꢂꢧꢦe ꢘꢠ

ꢏꢉꢦꢧꢨ

ꢏꢉꢩꢧꢦ

ꢚꢋꢁꢍꢎꢆ ꢢ ꢕ.ꢓꢓꢪ

ORDER INFORMATION

PART MARKING*

TEMPERATURE

MSL RATING RANGE (Note 2)

PART NUMBER

LTM4656EY#PBF

LTM4656IY#PBF

LTM4656IY

PAD OR BALL FINISH

SAC305 (RoHS)

SnPb (63/37)

DEVICE

FINISH CODE

PACKAGE TYPE

e1

e0

e1

e0

−40°C to 125°C

LTM4656Y

BGA

4

LTM4656EY-1#PBF

LTM4656IY-1#PBF

LTM4656IY-1

SAC305 (RoHS)

SnPb (63/37)

−40°C to 125°C

• Contact the factory for parts specified with wider operating temperature

ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Recommended LGA and BGA PCB Assembly and Manufacturing

Procedures

• LGA and BGA Package and Tray Drawings

Rev. 0

2

For more information www.analog.com

LTM4656/LTM4656-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 2), V_IN= 12, V_BIAS= BV_IN, SHDN = V_INper the typical application.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Input/Output Section

l

V

Input DC Voltage

Note 4

4.5

6

28

36

V

IN

Output Voltage Range

Note 4, V = 5V for 6V output

IN

OUT(RANGE)

OUT(DC)

Output Voltage, Total Variation

with Line and Load

R

= 11.5k, MODE_PLLIN = INTV

= 12V, I

23.52

24

24.48

FB

IN

CC

V

= 0A to 4A

OUT

I

Input Supply Bias Current

V

= 12V, V

= 24V, MODE_PLLIN = INTV

CC

1.7

76

230

mA

µA

Q(VIN)

IN

OUT

= 12V, V

= 24V, MODE/PLLIN = GND

Shutdown, SDHN = 0, V = 12V

IN

I

Input Supply Current

V

= 12V, V

= 24V, I = 4A

OUT

8

A

S(VIN)

IN

OUT

Input Inrush Current at Startup

C

IN

V

IN

= 10µF × 2, 150µF; C

= 10µF × 2 Ceramic, 150µF

INRUSH(VIN)

OUT

= 12V, V

= 24V, TRACK/SS = 0.1µF

0.5

A

OUT

I

Output Continuous Current Range

Note 4

V

= 5V, V

OUT

= 12V (Note 4)

= 24V

0

3.5

4

A

OUT(DC)

IN

=12V, V

OUT

Limit Range

Input Current Limit

See Typical Applications

Based on Internal 0.004 R

IN

and 50mV Trip Typical

10.6

12.5

0.1

14

0.2

0.6

A

%/V

%

SENSE

l

∆V

/V

Line Regulation Accuracy

Load Regulation Accuracy

Output Ripple Voltage

V

= 24V, V = 5 to 12V, I

= 0A

OUT(LINE) OUT

OUT

IN

OUT

/V

= 12V, V

= 24V, I = 0A to 4.0A

OUT

0.3

OUT(LOAD) OUT

IN

OUT

V

I

= 0A, C = 10µF Ceramic × 2, 150µF Aluminum,

OUT

200

mV

OUT(AC)

OUT

IN

V

= 12V, V

= 24V

OUT

∆V

)

Turn-On Overshoot

I

= 0A, C = 10µF Ceramic × 2, 150µF Aluminum,

OUT

100

1

mV

ms

mV

OUT(START

OUT

SS = 0.1µF, V = 12V, V

= 24V

IN

OUT

t

Turn-On Time

I

= 0A, C

= 10µF Ceramic × 2, 150µF Aluminum,

START

OUT

SS = 0.01µF, V = 12V, V

= 24V

IN

OUT

∆V

OUTLS

Peak Deviation for Dynamic Load

Load: 0% to 50% to 0% of Full Load

C

V

200

= 10µF Ceramic × 2, 150µF Aluminum,

OUT

= 12V, V

= 24V

IN

OUT

t

Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load

200

µs

SETTLE

C

V

= 10µF Ceramic × 2, 150µF Aluminum,

OUT

= 12V, V

= 24V

IN

OUT

Regulator Specifics

l

V

Voltage at V Pin

I

= 0A, V = 12V, V = 24V

OUT

1.180 1.200 1.220

V

nA

kΩ

µA

%

FB

OUT

IN

I

FB

Current at V Pin

(Note 6)

5

221

10

50

FB

R

Resistor Between V

and V Pins

FBHI

OUT FB

SS (I)

Track Pin Soft-Start Pull-Up Current

Maximum Duty Cycle

V

= 0V

7

13

96

5.6

2

SS

DC

FB = 1.0V (Note 6)

6V < V < 20V

MAX

V

Internal V Voltage

5.2

5.4

0.5

V

INTVCC

CC

IN

I

Load Regulation

I = 0mA to 50mA

CC

%

INTVCC(LOAD)

NTVCC

UVLO

INTV UVLO Thresholds

V

Ramping Up

4.3

3.8

4.5

V

CC

INTVCC

Ramping Down (Note 6)

3.6

350

f

t

Typical Output Ripple Voltage Frequency

SYNC Frequency Range

Lowest Frequency

V

= 12V, V

= 24V, R = Selectable

500

780

kHz

ns

S

IN

OUT

fSET

SYNC

LOW

NOM

HIGH

ON(MIN)

R

= 47.5k

350

500

750

110

fSET

Nominal Frequency

=68.1k

= 95.3k

Highest Frequency

Minimum On-Time

Note 3

Rev. 0

3

For more information www.analog.com

LTM4656/LTM4656-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 2), V_IN= 12, V_BIAS= BV_IN, SHDN = V_INper the typical application,

or otherwise specified in the table.

SYMBOL

PARAMETER

CONDITIONS

Rising

MIN

TYP

1.28

100

MAX UNITS

V

RUN Pin ON Threshold

RUN Pin ON Hysteresis

V

1.18

1.38

V

RUN

mV

RUNHYS

In-Line Protection Control Section

SHDN

Active Low Shutdown

4V to 36V Input

Threshold

0.6

1.4

1.7

2.1

V

l

0.385

SHDN Reset

UV Threshold

UV Hysteresis

SHDN Reset Time

SHDN = 0.4V (Note 6)

100

µs

V

Undervoltage Lockout

UV Input Hysteresis

UV Lockout Threshold, V =12V

1.24 1.275 1.31

12

IN

V

IN

> 4.5V, Nominal 12V (Note 6)

mV

µA

V

UV

UV Input Current

UV =1 .275V (Note 6)

TMR Rising (Note 6)

TMR Rising

0.3

1.275

1.375

4.3

1

IN

V

TMR Fault Threshold

TMR Gate Off Threshold

TMR Cooldown High Threshold

TMR(F)

)

V

TMR(G

V

IN

= 12V to 24V, TMR Rising

V

TMR(H)

TMR OVER I (5V)

TMR OVER I (12V)

TMR OVER I (24V)

TMR Overcurrent t

FLT Pin Leak

= 5V

V , SHDN, UV = 5V, V = 24.3k, 12V V

Shorted

800

220

150

2.5

µs

µA

V

VDS

IN

FB

OUT

= 12V

= 24V

V , SHDN, UV =12V, V = 11.5k, 24V V

IN FB

OUT

V , SHDN, UV = 24V, V = 7.5k, 36V V

Shorted

IN

FB

OUT

l

I

FLT = 36V

LEAK(FLT)

V

IN

– BV Rising Delta Path Fully Enhanced

Delta V – BV Enhancing, Boost RUN Pin Enabled

0.25

0.5

0.75

IN

V

IN

– BV Falling Delta Path Being Opened

Delta V – BV Opening, Boost RUN Pin Pulled Low

2.7

V

IN

DC

Retry Duty Cycle, Shorted Output

V

= 12V, V

= 0V, Referenced to BV

IN

1

%

µs

V

IN

OUT

l

t

Undervoltage Turn-Off Propagation Delay UV Steps from 1.5V to 1V (Note 6)

2

5

OFF(UV)

V

FLT Output Low

I

=100µA

0.3

0.8

OL(FLT)

SINK

PGOOD Output

V

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 6V

0.3

1

V

PGL

PGOOD

I

V

μA

PGOOD(LEAK)

PGOOD

V

PG

with Respect to Set Regulated Voltage

Ramping Negative

Ramping Positive

FB

V

FB

V

FB

–12

8

–10

10

–8

12

%

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: The minimum on-time condition is specified for a peak-to-

peak inductor ripple current of ~40% of I

Information section)

Load. (See Applications

MAX

Note 4: See output current derating curves for different V , V

and T .

A

IN OUT

Note 2: The LTM4656 is tested under pulsed load conditions such

Note 5: Guaranteed by design.

Note 6: 100% tested at wafer level.

that T ≈ T . The LTM4656E is guaranteed to meet performance

J

A

specifications over the 0°C to 125°C internal operating temperature

range. Specifications over the full –40°C to 125°C internal operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTM4656I is guaranteed to meet

specifications over the full –40°C to 125°C internal operating temperature

range. Note that the maximum ambient temperature consistent with

these specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal resistance and

other environmental factors.

Note 7: JEDEC board θ values are determined by simulation per JESD51

conditions. Demo board θ values are obtained with demo board. Refer

to Figure 9 to Figure 17 and Table 2 to Table 5 for lab ameasurement and

derating information.

Rev. 0

4

For more information www.analog.com

LTM4656/LTM4656-1

TYPICAL PERFORMANCE CHARACTERISTICS

5V_INEfficiency

12V_INEfficiency

24V_INEfficiency

ꢀ00

ꢀꢁ

ꢀ0

ꢀꢀ

ꢀꢁ

ꢀ0

ꢀ00

ꢀꢁ

ꢀ0

ꢀꢀ

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ0

ꢀꢀ

ꢀꢁ

ꢅꢆꢆꢇ ꢈꢉ0ꢊꢋꢌ

ꢂꢃꢄ

ꢀ0ꢁ

ꢀꢁꢂ

ꢅꢆꢆ ꢇꢇ0ꢈꢉꢊ

ꢆꢇꢇ ꢈꢈ0ꢉꢊꢋ

ꢆꢇꢇ ꢁꢈ0ꢉꢊꢋ

ꢀꢁꢂ

ꢆꢇꢇꢈ ꢉ00ꢊꢋꢌ

ꢂꢃꢄ

ꢃꢄꢅ

ꢀꢁꢂ

ꢆꢇꢇꢈ ꢉꢊ0ꢋꢌꢍ

ꢆꢇꢇꢈ ꢁꢉ0ꢊꢋꢌ

ꢃꢄꢅ

ꢆꢇꢇꢈ ꢁꢉ0ꢊꢋꢌ

ꢆꢇꢇꢈ ꢉ00ꢊꢋꢌ

ꢀꢁ

ꢀ0

0

ꢀ

0

ꢀ

0

ꢀ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀꢁꢂꢁ ꢃ0ꢄ

12V to 24V at 4A Switch and Ripple

5V to 12V Boost Load Step

5V to 24V Boost Load Step

ꢇ0ꢆꢃꢄꢅꢆ

200mV/DIV

0.5A/DIV

200mV/DIV

0.5A/DIV

ꢀ00ꢈꢆꢃꢄꢅꢆ

ꢉꢊꢋꢊ ꢌ0ꢉ

4656 G05

4656 G06

ꢀꢁꢂꢃꢄꢅꢆ

200µs/DIV

ꢇꢀꢆ ꢍꢎ ꢀꢉꢆ ꢏꢍ ꢉꢏ

C

= 100µF ×2, 6.8µF ×2 CERAMIC,

C

= 100µF ×2, 6.8µF ×2 CERAMIC

OUT

ꢐ

ꢒ ꢇ00ꢁꢓ ꢔꢀꢕ ꢊ.ꢖꢁꢓ ꢔꢀ ꢐꢗRꢏꢘꢅꢐ

ꢎꢑꢍ

28mΩ ESR

12V to 24V Boost Load Step

12V to 36V Boost Load Step

24V to 36V Boost Load Step

200mV/DIV

0.5A/DIV

200mV/DIV

0.5A/DIV

200mV/DIV

0.5A/DIV

4656 G07

4656 G08

4656 G09

500µs/DIV

C

= 100µF ×2, 6.8µF ×2 CERAMIC

C

= 100µF ×2, 6.8µF ×2 CERAMIC

C

= 100µF ×2, 6.8µF ×2 CERAMIC

OUT

28mΩ ESR

OUT

28mΩ ESR

OUT

28mΩ ESR

Rev. 0

5

For more information www.analog.com

LTM4656/LTM4656-1

TYPICAL PERFORMANCE CHARACTERISTICS

5V to 12V Boost HOT Plugged

12V to 24V Boost HOT Plugged

Start-Up Into 4A Load

24V to 36V Boost HOT Plugged

Start-Up Into 5A Load

Start-Up Into 3.5A Load,

ꢆ

ꢅꢇ

ꢀꢆꢃꢄꢅꢆ

ꢆ

ꢅꢇ

ꢀꢆꢃꢄꢅꢆ

ꢅꢌ

ꢀꢆꢃꢄꢅꢆ

ꢆ

ꢍꢎꢏ

ꢊ0ꢆꢃꢄꢅꢆ

ꢆ

ꢈꢉꢊ

ꢋ0ꢆꢃꢄꢅꢆ

ꢆ

ꢈꢉꢊ

ꢋ0ꢆꢃꢄꢅꢆ

ꢅ

ꢅꢌ

ꢀꢐꢃꢄꢅꢆ

ꢅ

ꢅꢇ

ꢀꢌꢃꢄꢅꢆ

ꢏꢅꢑꢒR ꢓꢅꢌ

0.ꢀꢆꢃꢄꢅꢆ

ꢊꢅꢍꢎR ꢏꢅꢇ

0.ꢀꢆꢃꢄꢅꢆ

ꢊꢅꢍꢎR ꢏꢅꢇ

0.ꢀꢆꢃꢄꢅꢆ

ꢇꢈꢀꢈ ꢉꢊꢋ

ꢀꢁꢂꢃꢄꢅꢆ

ꢐꢑꢀꢑ ꢒꢋ0

ꢐꢑꢀꢑ ꢒꢋꢋ

ꢀꢁꢂꢃꢄꢅꢆ

PIN FUNCTIONS

V (A9–A12, B9–B12, C9–C12, D10–D12): Power Input

operation when the pin is floated. Tying this pin to less

IN

Pins to Protection Path. Apply main input voltage between

than INTV –1.3V selects pulse-skipping operation.

CC

these pins and GND pins. Recommend placing minimum

This can be done by adding a 100k resistor between the

1µF input decoupling capacitance directly between V

pins and GND pins.

MODE_PLLIN pin and INTV . Forced continuous opera-

IN

CC

tion can be selected by tying this pin to INTV .

CC

BV (A1–A4, B1–B4, C1–C4, D1–D3):BoostPowerInput

FREQ (H6): The Frequency Control Pin for the Internal

IN

Pins. Recommend placing input decoupling capacitance

VCO. Connecting the pin to GND forces the VCO to a fixed

directly between BV pins and GND pins.

low frequency of 350kHz. Connecting the pin to INTV

IN

CC

forces the VCO to a fixed high frequency of 535kHz. The

frequency can be programmed from 300kHz to 780kHz

by connecting a resistor from the FREQ pin to GND. The

resistor and an internal 20µA source current create a volt-

age used by the internal oscillator to set the frequency.

Alternatively, this pin can be driven with a DC voltage to

vary the frequency of the internal oscillator. See Typical

Applications section.

V

(J1–J6, K1–K6, L1–L6, M1–M6): Power Output

OUT

Pins. Apply output load between these pins and GND

pins. Recommend placing output decoupling capacitance

directly between these pins and GND pins.

GND (A5–A6, B5–B6, C5–C6, D4–D9, E1–E7, E9–E12,

F2–F5, F10–F12, G1–G3, G5, G7–G8, G10–G12, H1,

H8–H12, J7–J11, K7–K11, L7–L12, M7–M12): Ground

Pins for the Input and Output Capacitors and Small Signal

Component Connection.

SS (F7): Output Soft-Start Input. A capacitor to ground

at this pin sets the ramp rate of the output voltage during

start-up.

SW (J12, K12): Switching node that is used for testing

purposes.

V

(E8): The Negative Input of the Error Amplifier for

FB

MODE_PLLIN (G6): External Synchronization Input to

Phase Detector and Mode Operation Input. When an ex-

ternal clock is applied to this pin, it will force the converter

into forced continuous mode of operation and the phase-

locked loop will force the rising boost switch signal to be

synchronized with the rising edge of the external clock.

When not synchronizing to an external clock, this input

determineshowtheLTM4656operatesatlightloads.Pull-

ing this pin to ground selects Burst Mode operation. An

internal 100k resistor to ground also invokes Burst Mode

Each Channel. Internally, this pin is connected to V

OUT

with a 221k precision resistor. Different output voltages

can be programmed with an additional resistor between

V and GND pins. In PolyPhase^®operation, tying the V

FB

pins together allows for parallel operation. See Typical

Applications section for details.

COMP(F6):CurrentControlThresholdandErrorAmplifier

Compensation Point for the Regulator. The current com-

parator threshold increases with this control voltage. Tie

Rev. 0

6

For more information www.analog.com

LTM4656/LTM4656-1

PIN FUNCTIONS

allCOMPpinstogetherforparalleloperation. Thedeviceis

internal compensated. The LTM4656-1 offers an External

Compensation option.

turnsoffwhenTMRreachesthethresholdof1.375V.A2µA

current source then continues to pull the TMR up. When

TMR reaches 4.3V, the 2µA current reverses direction and

startstopulltheTMRpinlow. WhenTMRreachestheretry

threshold of 0.5V, the GATE pin pulls high turning back

on the pass transistor. See Typical Applications section.

SENSE1 (A7–A8, B7–B8, C7–C8): These pins are the

output side of the input protection power MOSFET, and

the input to the onboard 4mΩ current sense resistor that

sets maximum input current limit to trip off and retry

in a output short. Measuring the voltage drop between

NC (E3): Float Pin.

SHDN(F1):TheLTM4656canbeshutdowntoalowcurrent

modewhenthevoltageattheSHDNpinispulledbelowthe

shutdown threshold of 0.4V. The quiescent current drops

downto40µAwithinternalcircuitryturnedoff.Thispinwill

shut down the in-line protection and the boost converter.

SENSE1 and BV , and dividing by the 4mΩ resistance

IN

gives the input current for a given operating condition in

the boost converter.

RUN (H7): RUN Pin Monitor. The threshold level of 1.28V

The SHDN pin can be pulled up to V MAX or below GND

IN

will turn on the boost converter. An internal 75k resistor is

by up to V MAX without damage. The SHDN pin is pulled

IN

connected from this pin to BV , and a 5.1V Zener diode to

IN

up to V with an internal 100k resistor for active on. An

IN

GNDisinternaltothemoduleforlimitingthevoltageonthe

RUN pin to 5V. The RUN pin is allowed to turn on from an

open-collector control coming from the in-line protection

V rated open collector can be used to controlled this pin

IN

for enabling the in-line protection and the boost converter,

or a Zener diode can be placed from this pin to ground to

interface to lower voltage rated pull downs.

control when the voltage at the BV pin is within 0.5V of

IN

V and 3V above GND, indicating the protection MOSFET

IN

is fully on. The state of the pin stays on until the BV pin

UV (H2): Undervoltage Comparator Input. When UV falls

below its threshold of1.275V, the GATEpin is pulled down

with a 1mA current. When UV rises above 1.275V plus

the hysteresis, the pull-down current disappears and the

GATE pin is pulled up by the internal charge pump. This is

used to set up an undervoltage lockout to limit the input

current during startup. There is an internal 100k resistor

IN

voltage drops below 2V. See Block Diagram.

INTV (G9): Output of Internal 5.4V LDO. Power supply

CC

for internal control circuits and gate drivers. There is an

internal 4.7µF low ESR ceramic capacitor from this pin to

ground for decoupling.

V

(F9): Main Control Supply Pin. It is normally tied

from this pin to V to set up with an external resistor an

BIAS

IN

to the input supply BV or to the output of the boost

under voltage trip point. If unused, connect to V . See

IN

CC

converter. A bypass capacitor should be tied between this

pin and the GND pin. The operating voltage range on this

pin is 4.5V to 36V.

Typical Applications section.

FLT (H3): Open Collector Fault Output. This pin pulls low

after the voltage at the TMR pin has reached the fault

threshold of 1.275V. It indicates the pass transistor is

about to turn off because the device is in an overcurrent

condition (current fault). The internal NPN is capable of

sinking up to 100µA of current while maintaining a low

level of 0.8V max.

PGOOD (F8): Power Good Indicator. Open-drain logic

output that is pulled to ground when the output voltage is

more than 10% away from the regulated output voltage.

To avoid false trips, the output voltage must be outside of

the range for 25µs before this output is activated.

+

TEMP (H4): Onboard temperature diode for monitoring

TMR (G4): Fault Timer Input. An internal 0.01µF capacitor

to ground sets the times for early fault warning, fault turn-

off, and cooldown periods. The current charging up this

pin during fault conditions depends on the voltage differ-

each channel with differential connections for noise im-

munity. See Block Diagram.

–

TEMP (H5): Onboard temperature diode for monitoring

ence between the V and BV pins. When TMR reaches

IN

each channel with differential connections for noise im-

munity. See Block Diagram.

1.275V, the FLT pin pulls low to indicate the detection of a

faultcondition.Iftheconditionpersists,thepasstransistor

Rev. 0

7

For more information www.analog.com

LTM4656/LTM4656-1

BLOCK DIAGRAM

ꢀꢁꢂꢀꢁꢃ

ꢀꢁꢂꢃꢁꢂꢄ ꢅ ꢆꢇ ꢉꢊR

ꢋ ꢈꢃꢌꢍꢎ ꢈ

ꢈꢃ ꢁꢂꢃꢁꢂ

ꢀꢁꢂ

R

ꢀꢁꢂꢀꢁ

ꢀ

ꢁꢂ

0.004Ω

ꢀ

ꢁꢂ

47Ω

R

+

ꢀ0ꢁꢂꢃꢄꢀꢁꢂ

–

ꢀ00ꢁ

SHDN

ꢀ

ꢁꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢂꢄꢉ

ꢊꢋꢁ ꢌꢀRꢍ ꢃꢍ ꢎ ꢌꢏꢆꢍ

ꢐ.ꢑꢒꢓꢁ ꢔ ꢃꢍ

ꢀꢁ

ꢀꢁꢂRꢃꢄ

ꢀꢁꢂꢀ

ꢀꢁꢂꢃ ꢄꢅꢆꢁ

ꢀꢁ

FLT

ꢀ0ꢁ

ꢀ00ꢁ

ꢀꢁꢂꢃꢄꢅꢂꢆ

SHDN

FLT

ꢀ.ꢁꢂꢃꢄ

ꢀ

ꢁꢂ

ꢀꢁ

CONTROL LOGIC

RꢀꢁRꢂ

ꢀ

ꢁꢁ

ꢀꢁꢂꢃꢄꢅꢅ FLT RꢀꢁRꢂ ꢀꢁꢂꢃꢄꢀ

ꢀ.ꢁꢂꢃꢄ

ꢀ

ꢁꢂR

0.ꢀꢁ

ꢀꢁꢂ

ꢀ.ꢁꢂꢃꢄ

ꢀ.ꢁꢂ

ꢀꢁR

IN-LINE PROTECTION BLOCK

0.0ꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢂꢃ

ꢀ

ꢁꢂꢃ

0.ꢀꢁꢂ

ꢀ0ꢁ

ꢀ

ꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢃꢄ

ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

ꢀꢁꢂ

NTSA545

ꢀ0ꢁꢂ

ꢃꢄꢅ

ꢆꢃ

ꢀꢁ0ꢂꢃ

ꢄꢁꢅ

ꢀ.ꢁꢂ

ꢃꢄꢅꢄR

0.ꢀꢁꢂ

ꢀ0ꢁ

ꢀꢀꢁꢂ

Rꢀꢁ

POWER CONTROL

ꢀ

ꢀꢁꢂꢃ

ꢁꢂ

ꢀꢁꢂꢃ ꢄRꢅꢆꢇ

ꢀꢀ

*BV NEEDS ≥100μF

IN

ꢀꢁ

ꢀ.ꢁꢂꢃ

INPUT CAPACITOR

TO SERVICE CURRENT

DURING SHORT FOR

PROPER CURRENT

LIMIT TIMEOUT.

ꢀꢁꢂꢂꢃ

ꢄ

ꢀꢁꢂꢃ

ꢀꢁRRꢂꢃꢄ ꢅꢂꢃꢅꢂ

ꢀꢁꢂꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃ ꢀꢁꢂꢃꢄ

ꢀꢁ0ꢂꢃ

ꢀꢁꢂꢂꢃꢄ ꢅRꢆꢇꢈ

ꢄ

ꢀꢁꢂꢃ

ꢀ

ꢁꢂ

ꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢀLLꢁN ꢀꢁꢂ ꢀRꢁꢂ

ꢄꢄ

ꢀꢁꢂ

0.ꢀꢁꢂ

ꢀ.ꢁꢂꢃ

ꢀ

ꢁꢂ

ꢀ

Rꢀꢁ ꢀꢀ

ꢀꢁꢂꢂꢃ ꢀꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢀLLꢁN ꢀRꢁꢂ

ꢀ

ꢁꢂꢃꢄ

ꢄꢄ

ꢁꢂ

4656 BD

0.ꢀꢁꢂ

ꢀꢀ.ꢁꢂ

ꢀ0.ꢁꢂ

ꢀꢁꢂꢂꢃ

ꢀꢁ

ꢂꢃ

ꢀ0ꢁ

*LTM4656-1 Optional External Compensation

Rev. 0

8

For more information www.analog.com

LTM4656/LTM4656-1

OPERATION

The LTM4656 contains an integrated fixed frequency,

current mode boost controller, power MOSFETs, induc-

tor, in-line protect circuitry and other supporting discrete

components. The default switching frequency is 500kHz.

For noise-sensitive applications, the switching frequency

can be adjusted by an external resistor and the µModule

regulator can be externally synchronized to a clock.

The LTM4656 is a single output standalone non-isolated

step-up switching mode DC/DC power supply with input

currentlimitprotectionduringanoutputshort.Thismodule

provides a precisely regulated output voltage program-

mable via one external resistor from 6V to 36V and deliv-

ers up to 5A output current with few external input and

output capacitors. During normal operation the LTM4656

sensesinputcurrentthroughaninputprotectedfrontend.

The LTM4656 softly turns on with a controlled inrush and

will perform a low duty cycle auto-retry during an output

short circuit. The output short trip time is controlled by

how much short-circuit current is applied and the amount

of voltage across the in-line protection switch. The typical

application schematic is shown in Figure 17. See Typical

Applications section for explanation and curves.

With current mode control and internal feedback loop

compensation, the LTM4656 module has sufficient stabil-

ity margins and good transient performance with a wide

range of output capacitors, even with all ceramic output

capacitors.

Current mode control allows the LTM4656 to parallel for

increase power delivery.

Rev. 0

9

For more information www.analog.com

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

IN-LINE PROTECTION SECTION

assure the MOSFET can handle this power dissipation for

that period of time. When TMR reaches 1.275V, the FLT

pin pulls low to indicate the detection of a fault condition.

Iftheconditionpersists, thepasstransistorturnsoffwhen

TMRreachesthethresholdof1.375V.A2µAcurrentsource

then continues to pull the TMR up. When TMR reaches

4.3V, the 2µA current reverses direction and starts to pull

the TMR pin low. When TMR reaches the retry threshold

of 0.5V, the GATE pin pulls high turning back on the pass

transistor. See overcurrent fault diagram in Figure 2.

ReferringtotheBlockDiagram,theinputvoltageisapplied

to V . The power MOSFET MIN is controlled by a charge

IN

pump high side drive that is slowly turned on after the

SHDN pin is either pulled up to V or driven from an open

IN

collectordriveratedtoV .TheUVpinhasaninternal100k

IN

resistor to V that can be used with an external resistor

IN

to ground to set a UVLO trip point for V . This is valuable

IN

to limit turn-on to a specific input voltage level. When

both the SHDN and UV pin thresholds are met, then the

gate voltage begins to ramp up at a control rate and the

MIN source pin will follow. Gate turn-on time is ~10ms.

ꢃꢒꢓ0

ꢉꢊR ꢚ ꢆꢀ

The R

in series with this path monitors the current

SENSE

ꢃꢒꢒ0

ꢃꢆꢓ0

ꢃꢆꢒ0

ꢃꢔ0

ꢃꢕ0

0

going to the boost converter. The LTM4656 monitors the

voltagedropbetweentheSENSE1andBV pinstoprotect

IN

against overcurrent faults. An internal amplifier limits the

voltage across the internal 4mΩ current sense resistor

to 50mV. This is reduced to 25mV in a severe fault when

BV is below 2V. In this fault condition, a timer is started

IN

inversely proportional to MOSFET stress. Before the timer

expires,theFLT pinpullslowtowarnofanimpendingpower

down. If the condition persists, the MOSFET is turned off,

0

ꢆ0 ꢒ0 ꢙ0 ꢕ0 ꢖ0 ꢓ0 ꢘ0 ꢔ0

ꢃ ꢄꢅꢂꢄꢅꢆ ꢇꢀꢈ

ꢀ

ꢁꢂ

ꢕꢓꢖꢓ ꢗ0ꢆ

and restarts after a cooldown period. BV needs at least

IN

Figure 1. Overcurrent TMR Current

vs V_IN– SENSE1 Voltage

100µF capacitance to service proper current limit level to

eliminate any overtemperature timeout oscillations.

ꢕ

ꢃꢌRꢖꢕꢗ

FAULT TIMER SECTION

ꢓ.ꢚꢝꢛ

ꢓ.ꢒꢝꢛ

A 0.01µF capacitor is connected internal to the TMR pin

and ground to set the times for early fault warning, fault

turn-off, and cooldown periods. This capacitor is selected

to assure the MIN MOSFET is turn-off fast enough. The

ꢕ

ꢃꢌR

ꢄ ꢒꢔꢕ

ꢄ ꢓꢒ0ꢆꢉ

ꢄ 0.0ꢓꢆꢁ

ꢘꢙ

ꢕ

ꢃꢌR

ꢄ ꢓꢒꢕ

ꢄ ꢚꢛꢆꢉ

ꢄ 0.0ꢓꢆꢁ

ꢋ

ꢜ

ꢘꢙ

ꢋ

ꢜ

TMRchargingcurrentincreaseslinearlyfrom8µAwithV

DS

< 0.5V to 120µA with V = 40V. V is inferred from the

DS

drop across V and SENSE1. See Figure 1. The current

IN

0.ꢛ0

ꢃꢋꢌꢍ

ꢀ

ꢏꢉRꢐꢋꢐꢑ

ꢄ ꢔꢆꢇ

charging up this TMR pin during fault conditions depends

ꢀ

ꢁꢂꢃ

ꢄ ꢅ0ꢆꢇ

on the voltage difference across MIN MOSFET between

ꢀ

ꢄ ꢒꢒꢓꢆꢇ

ꢁꢂꢃ

ꢀ

the V and SENSE1 pins. This increase in TMR current is

ꢏꢉRꢐꢋꢐꢑ

ꢄ ꢒ0ꢆꢇ

IN

ꢞꢟꢛꢟ ꢁ0ꢒ

ꢃꢈꢃꢉꢂ ꢁꢉꢊꢂꢃ ꢃꢋꢌꢍR ꢄ ꢀ

ꢎ ꢀ

ꢁꢂꢃ

ꢏꢉRꢐꢋꢐꢑ

to assure a faster turn off during an overcurrent fault with

substantial voltage across the MIN MOSFET. This turn-off

time is correlated with the MIN MOSFET SOA capability to

Figure 2. Overcurrent Fault Time with 0.01µF

Rev. 0

10

For more information www.analog.com

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

When the TMR pin reaches 1.275V, the FLT pin is latched

low as an early warning of impending shutdown, then it

continues unabated until the TMR reaches 1.375V, pro-

ducing an early warning period given by:

Brief overcurrent conditions interrupt the operation of

the timer. If the TMR pin has not yet reached 1.275V

when fault drops out of current limit, the timer capacitor

is discharged back to 0.5V with a 2µA current sink. If the

TMR voltage crosses 1.275V, then FLT is set low. If the

overcurrent abates before reaching 1.375V, the timer

capacitor discharges with 2µA back to 0.5V, whereupon

FLT resets high. If several short overcurrent events occur

in rapid succession, the timer capacitor will integrate the

charging and discharging currents. Figure 20 shows an

overcurrent fault wave from and a retry cycle.

1.275V – 0.5V

t_FLT= 0.01µF •

I_TMR

1.375V – 1.275V

t_WARN= 0.01µF •

I_TMR

I

taken from Figure 1.

TMR

Because I

is a function of V –SENSE1, the exact time

IN

TMR

in current limit depends upon the input waveform and the

time required for the output current to come into regula-

tion. Testing of the overall solution should be verified, and

compared to the MOSFET SOA curves.

MIN MOSFET SOA CURVE

Figure 3 shows the MIN MOSFET SOA curve. This curve

can be compared to the period of time the MIN Power

MOSFET stays on during a fault condition with an over-

current flowing through MIN, and the worse-case voltage

across the MIN MOSFET.

COOLDOWN PHASE

Cooldown behavior is initiated by overcurrent. During

the cooldown phase, the timer continues to charge from

1.375V to 4.3V with 2µA, and then discharges back down

to 0.5V with 2µA, for a total equivalent voltage swing of

6.725V. The cooldown time is given by:

ꢀ00

ꢀ0

ꢀꢁꢂ

ꢀ0ꢁꢂ

6.725V

2µA

ꢀꢁꢂꢃ ꢄRꢅꢄ ꢂꢃ

ꢀ

t_COOL= 0.01µF •

= 33.6ms

ꢀ00ꢁꢂ

ꢆꢂꢇꢂꢀꢅꢈ ꢉꢊ

R

ꢈꢃꢋꢌꢍꢎ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢄꢀꢅ

0.ꢀ

ꢀ0ꢁ

ꢀ ꢂ ꢃꢄꢅ Rꢄꢀꢆꢇ

This long cool time assures that during retry the MOSFET

does not overheat.

ꢁ

ꢀ

ꢀ ꢁꢂꢃꢄ

ꢀꢁ

R

θꢀꢁ

ꢂ ꢃꢄꢅꢆꢇꢈꢉ

0.0ꢀ

0.ꢀ

ꢀ

ꢀ0

ꢀ00 ꢀ00

The LTM4656 will auto-retry at the end of the cooldown

phase.Retryisautomaticallyinitiated.Thecooldownphase

may be interrupted in the LTM4656 by pulling SHDN low

for at least 10ms.

ꢀ

ꢀ ꢁRꢂꢃꢄ ꢅꢆ ꢇꢆꢈRꢉꢊ ꢋꢆꢌꢅꢂꢍꢊ ꢎꢋꢏ

ꢀꢁ

ꢀꢁꢂꢁ ꢃ0ꢄ

Figure 3. MIN Internal MOSFET SOA Curves

The FLT pin goes high in shutdown and is cleared high

when power is first applied to V .

IN

Rev. 0

11

For more information www.analog.com

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

Figure 4 and Figure 5 show the overcurrent fault wave-

forms, and the timer pin timeout period as a function of the

amount of voltage across the MIN power MOSFET during

an overcurrent fault. Figure 4 shows a 10V to 36V boost

in short-circuit, and Figure 5 shows a 28V to 36V boost in

a short-circuit. Figure 2 shows that the over current timer

(TIMER pin) will expire at ~240µs in a short-circuit at the

1.375V threshold with 10V input, will expire at 73µs at 40V

input. Figure4timeoutwith10VinputandFigure5timeout

with 28V input are very close to Figure 2 time out period

relative to input voltage. These timeout periods across the

full input range can be checked against the Figure 3 MIN

MOSFET SOA curves to ensure adequate margin relative

to voltage across the input protection MOSFET and the

current flowing through. Adequate guard band is to ensure

that these conditions are OK overtemperature.

TURN-ON INRUSH CURRENT CONTROL AND

POWER-UP INTO LOAD

TheLTM4656turnsontheMINpowerMOSFETwithatime

control ramp of 10ms. When the voltage at the SENSE1

pin is within 0.5V of V and 3V above GND, indicating

IN

the external MOSFET is fully on, then the internal ENABLE

signal goes high impedance to allow the RUN pin to acti-

vate the boost converter. The state of the internal ENABLE

signal is latched until the SENSE1 pin voltage drops below

2V, resetting the latch. Utilizing the UV pin to set a UVLO

voltage before turn on, then having the boost converter

turn on after the MIN MOSFET is fully enhanced, and the a

0.1µF soft-start capacitor will assure no false overcurrent

trips at start-up.

SYNCHRONOUS BOOST CONVERTER SECTION

The LTM4656 has a high power synchronous converter

downstream of the input protection. A synchronous boost

converterinherentlyhasdifficultywithoutputshort-circuit

due to the MOUT output power MOSFET body diode

conducting.

V

IN

5V/DIV

V

SHORTED

OUT

V

OUT

5V/DIV

~240μSEC TIME OUT

INPUT CURRENT FOLDBACK TO 5A

TIMER PIN

1V/DIV

I

The input protection path will control the input current to

boost converter and auto-retry during an output short.

IN

5A/DIV

4656 F04

200µs/DIV

*25mV SENSE IN FOLDBACK

TIMER (78μs)

The LTM4656 uses a constant-frequency, current mode

step-upcontrolarchitecture.Duringnormaloperation,the

MBOTbottomMOSFETisturnedonwhentheclocksetsthe

internal RS latch, and is turned off when the main (ICMP)

current comparator resets the RS latch. The peak induc-

tor current at which ICMP trips and resets the latch is

controlled by the voltage on the COMP pin, which is the

output of the error amplifier. The error amplifier compares

Figure 4. 10V Input to 36V Output Short Input Current

Trip Waveform

V

IN

20V/DIV

V

OUT

SHORTED

V

OUT

the output voltage feedback signal at the V pin.

20V/DIV

FB

~100μSEC TIME OUT

INPUT CURRENT FOLDBACK TO 5A

TIMER PIN

1V/DIV

The LTM4656-1 provides optional External Compensation.

I

In a boost converter, the required inductor current is de-

IN

5A/DIV

termined by the load current, V and V . When the load

IN

OUT

4656 F05

100µs/DIV

currentincreases,itcausesaslightdecreaseinV relative

FB

*25mV SENSE IN FOLDBACK

TIMER (218μs)

to the reference, which causes the error amp to increase

the COMP voltage until the average inductor current in

the channel matches the new requirement based on the

new load current. After the bottom MOSFET is turned off

Figure 5. 28V Input to 36V Output Short Input Current

Trip Waveform

Rev. 0

12

For more information www.analog.com

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

each cycle, the top MOSFET is turned on until either the

inductor current starts to reverse, as indicated by the cur-

rent comparator or the beginning of the next clock cycle.

Although ceramic capacitors can be relatively tolerant of

overvoltage conditions, aluminum electrolytic capacitors

are not. Be sure to characterize the input voltage for any

possible overvoltage transients that could apply excess

stress to the input capacitors.

In a step-up boost converter, the duty cycle can be cal-

culated at:

The value of the C is a function of the source impedance,

IN

V

V_OUT

IN

D = 1 –

andingeneral,thehigherthesourceimpedance,thehigher

the required input capacitance. The required amount of

inputcapacitanceisalsogreatlyaffectedbythedutycycle.

High output current applications that also experience high

duty cycles can place great demands on the input supply,

both in terms of DC current and ripple current.

Note that at low input voltages, small voltage drops due

to series resistance become critical and greatly limit the

power delivery capability of the converter.

Theboostcontrollerhasaninternal1.2Vreferencevoltage,

The input I

current in boost is fairly low since the

RMS

and a 221k 1% internal feedback resistor connects V

OUT

input current is continuous. Primary input capacitance is

and V pins together. Adding a resistor R from V pin

FB

to maintain low input ripple voltage.

to GND programs the output voltage:

The input I

current equation:

RMS

1.2V

V_OUT– 1.2V

R_FB

=

• 221k

I_O²+(∆I)²

I_RMS

=

12

Table 1. V_FBResistor Value vs Various Output Voltages

(V) 6V 8V 10V 12V 20V 24V 30V

54.9k 39.2k 30.9k 24.3k 14k 11.5k 9.31k

V

36V

7.5k

OUT

Where I is output current, and

O

R

FB

V

•D

IN

∆I =

ForparalleloperationofN-pieceofLTM4656modules,the

following equation can be used to solve for R :

4.7µH • FREQ

FB

The output capacitor will see discontinuous current, thus

1.2V

V_OUT– 1.2V

221k

N

the peak current can be high, and the C is signifi-

I

R_FB

=

•

OUT RMS

current is:

cant. The equation for the C

I

OUT RMS

The V , COMP, SS, RUN and SDHN pins should be con-

V_OUT– V

FB

IN

I_RMS= I_OUT

nected together.

V

IN

The UV pins can be tied together taking into account the

The output ripple has two components, one that is related

to output capacitance minimum:

internal 100k resistor to V will reduce N times when

IN

selecting a single resistor to set an UVLO operating point

for the paralleled modules.

I_OUT• D

FREQ • ∆V_OUT

C_OUT

=

INPUT DECOUPLING CAPACITORS

Where ∆V

is the output ripple based on total output

OUT

The LTM4656 module should be connected to a low

AC-impedance DC source. The input ripple current in a

boostconverterisrelativelylow(comparedwiththeoutput

ripplecurrent)becausethiscurrentiscontinuous.Theinput

capacitance.Thesecondisbasedontotalequivalentoutput

capacitance ESR:

I

∆I

2

⎛

⎞

OUT

∆V_OUTESR= ESR •

+

⎜

⎝

⎟

⎠

capacitor, C , voltage rating should comfortably exceed

1– D

IN

the maximum input voltage, and placed on the BV pins.

IN

Rev. 0

13

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LTM4656/LTM4656-1

APPLICATIONS INFORMATION

Theoutputcapacitorrecommendationsandinternalcontrol

loop compensation assure stability over the operating

ranges. The Analog Devices LTpowerCAD^®design tool

is available to download online for RMS current, output

ripple, stability and transient response analysis.

internal1.2Vreference,theLTM4656regulatestheV pin

FB

voltage to the voltage on the SS pin instead of 1.2V. Soft-

start is enabled by simply connecting a capacitor from the

SSpintoground. Aninternal10µAcurrentsourcecharges

the capacitor, providing a linear ramping voltage at the SS

pin. The LTM4656 will regulate the V pin (and hence,

FB

V

) according to the voltage on the SS pin, allowing

OUT

LOW VOLTAGE OPERATION

to rise smoothly from V to its final regulated value.

IN

The LTM4656 is designed to allow start-up from input

voltages as low as 4.5V. The limiting factors for the low

voltage applications become the availability of the power

source to supply sufficient power to the output at the

low input voltage, and the maximum duty cycle, which is

clamped at 96%. Note that at low input voltages, small

voltage drops due to series resistance become critical and

greatly limit the power delivery capability of the converter.

The input current can get large at high boost ratios. The

input is limited to a minimum of 9A. The below equation

can be used to calculate the input current need to support

a particular design.

The total soft-start time will be approximately:

1.2V

10µA

T_SS= C_SS

•

A0.1µFisagoodvaluetouseforC . Thisprovidesaslow

SS

12msrampthatwillslowlyturnontheboostregulatorinto

load, and eliminate false overcurrent tripping at start-up.

INTV Power

CC

The LTM4656 boost control section features an internal

P-channellowdropoutlinearregulator(LDO)thatsupplies

power at the INTV pin from the V

supply pin. INTV

CC

BIAS

CC

V_OUT•I_OUT

I_IN=

powers the gate drivers and much of the boost control’s

V

IN

internal circuitry. The V LDO regulates INTV to 5.4V.

BIAS

CC

It can supply at least 50mA and is bypassed to ground

For example, 5V to 12V at 3.5A output current would

equate to an input current of ~8.5A.

with an internal 4.7µF ceramic capacitor.

Power Good

SHDN AND RUN PINS

The PGOOD pin is connected to an open-drain of an

N-channel MOSFET. The MOSFET turns on and pulls the

The SHDN pin controls the complete shutdown of the

LTM4656. When this pin is below 0.4V, the LTM4656

will be in complete shutdown drawing only 40µA. When

SHDN goes above 2.1V then the LTM4656 will enable.

The LTM4656 boost converter can be shut down using

the RUN pin while the inline overcurrent protection is

still powered. Pulling this pin below 1.28V shuts down

the main boost control loop. Pulling this pin below 0.7V

disables the boost controller and most internal circuits,

PGOODpinlowwhentheV pinvoltageisnotwithin 10%

FB

ofthe1.2Vreferencevoltage.ThePGOODpinisalsopulled

low when the corresponding RUN pin is low (shutdown).

When the V pin voltage is within the 10% require-

FB

ment, the MOSFET is turned off and the pin is allowed to

be pulled up by an external resistor to a source of up to

6V (ABS max).

including the INTV LDOs. In this state, total current

Loop Compensation

CC

draw is about 50µA.

The LTM4656 has internal compensation while the

LTM4656-1 provides for optimized external compen-

sation. LTpowerCAD can be used to optimize External

Compensation.

SOFT-START (SS PIN)

The start-up of the V

is controlled by the voltage on the

OUT

SS pin. When the voltage on the SS pin is less than the

Rev. 0

14

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LTM4656/LTM4656-1

APPLICATIONS INFORMATION

Light Load Current Operation—Burst Mode Operation,

Pulse-Skipping or Continuous Conduction

(MODE_PLLIN Pin)

In forced continuous operation or when clocked by an

external clock source to use the phase-locked loop. See

the Frequency Selection and Phase-Locked Loop (FREQ

and MODE_PLLIN Pins) section, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

the voltage on the COMP pin, just as in normal operation.

In this mode, the efficiency at light loads is lower than in

BurstModeoperation.However,continuousoperationhas

the advantages of lower output voltage ripple and less

interference to audio circuitry, as it maintains constant-

frequency operation independent of load current.

The LTM4656 boost converter can be enabled to enter

high efficiencyBurstModeoperation, constant-frequency

pulse-skipping mode or forced continuous conduction

mode at low load currents. To select Burst Mode opera-

tion, tie the MODE_PLLIN pin to ground. To select forced

continuous operation, tie the MODE_PLLIN pin to INTV .

CC

Toselectpulse-skippingmode,tietheMODE_PLLINpinto

aDCvoltagegreaterthan1.2VandlessthanINTV –1.3V.

CC

When the controller is enabled for Burst Mode operation,

theminimumpeakcurrentintheinductorissettoapproxi-

mately 30% of the maximum sense voltage even though

the voltage on the COMP pin indicates a lower value.

When the MODE_PLLIN pin is connected for pulse-

skipping mode, the LTM4656 boost converter operates

in PWM pulse-skipping mode at light loads. In this mode,

constant-frequency operation is maintained down to ap-

proximately 1% of designed maximum output current.

At very light loads, the internal current comparator may

remain tripped for several cycles and force the external

bottom MOSFET to stay off for the same number of cycles

(i.e., skipping pulses). The inductor current is not allowed

to reverse (discontinuous operation). This mode, like

forced continuous operation, exhibits low output ripple

as well as low audio noise and reduced RF interference

as compared to Burst Mode operation. It provides higher

low current efficiency than forced continuous mode, but

not nearly as high as Burst Mode operation.

If the average inductor current is higher than the required

current,theinternalerroramplifierwilldecreasethevoltage

on the COMP pin. When the COMP voltage drops below

0.425V, an internal sleep signal goes high (enabling sleep

mode) and both external MOSFETs are turned off. The

COMP pin is then disconnected from the output of the

EA and parked at 0.450V.

In sleep mode, much of the internal boost controller

circuitry is turned off and the LTM4656 draws only 50µA

of quiescent current. In sleep mode, the load current is

supplied by the output capacitor. As the output voltage

decreases,theinternalerroramplifieroutputbeginstorise.

When the output voltage drops enough, the COMP pin is

reconnectedtotheoutputoftheinternalerroramplifier,the

sleep signal goes low, and the controller resumes normal

operation by turning on the bottom external MOSFET on

thenextcycleoftheinternaloscillator. Whenthecontroller

is enabled for Burst Mode operation, the inductor current

is not allowed to reverse. The internal reverse current

comparator (IR) turns off the top external MOSFET just

before the inductor current reaches zero, preventing it

from reversing and going negative. Thus, the controller

operates in discontinuous current operation.

Frequency Selection and Phase-Locked Loop (FREQ

and MODE_PLLIN Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency operation

increasesefficiencybyreducingMOSFETswitchinglosses,

butrequireslargerinductanceand/orcapacitancetomain-

tain low output ripple voltage. The switching frequency

of the LTM4656 boost controllers can be selected using

the FREQ pin. If the MODE_PLLIN pin is not being driven

by an external clock source, the FREQ pin can be tied to

Rev. 0

15

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LTM4656/LTM4656-1

APPLICATIONS INFORMATION

GND, tied to INTV , or programmed through an external

The typical input clock thresholds on the MODE_PLLIN

pin are 1.6V (rising) and 1.2V (falling).

CC

resistor. Tying FREQ to GND selects 350kHz while tying

FREQtoINTV selects535kHz.Placingaresistorbetween

CC

Overtemperature Protection

FREQ and GND allows the frequency to be programmed

between 50kHz and 900kHz, as shown in Figure 6. The

recommendedoperatingrangefortheLTM4656is300kHz

to 780kHz based on the internal 4.7µH inductor.

At higher temperatures, or in cases where the internal

power dissipation causes excessive self-heating of the

boost controller (such as an INTV short to ground),

CC

the overtemperature shutdown circuitry will shut down

the boost converter. When the junction temperature ex-

ceedsapproximately170°C,theovertemperaturecircuitry

disables the INTV LDO, causing the INTV supply to

1000

900

800

700

600

500

400

300

200

100

CC

collapse and effectively shut down the entire boost con-

troller chip. Once the junction temperature drops back

to approximately 155°C, the INTV LDO turns back on.

CC

Long-term overstress (T > 125°C) should be avoided as

J

it can degrade the performance or shorten life. As explain

aboveintheinlineprotection,ifanovercurrentshortoccurs

in the boost converter section, then the inline protection

will operate in a low duty cycle retry mode.

0

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kΩ)

4656 F06

Figure 6. Relationship Between Oscillator

Frequencies and Resistor Value at the FREQ Pin

Thermal Performance

The LTM4656 provides adequate heat sinking utilizing the

inductor on top of package, and can either be cooled with

airflow or other heat sinking methods. Figure 7 shows a

12V to 24V boost at 96W conversion with only ~ 36°C

rise with 200LFM.

A phase-locked loop (PLL) is available on the LTM4656’s

boostconvertertosynchronizetheinternaloscillatortoan

externalclocksourcethatisconnectedtotheMODE_PLLIN

pin.TheLTM4656’sboostconverterphasedetectoradjusts

the voltage (through an internal low pass filter) of the VCO

input to align the turn-on of the external bottom MOSFET

to the rising edge of the synchronizing signal.

The VCO input voltage is pre-biased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If pre-biased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of BG. The ability to

pre-bias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

Figure 7. 12V_INto 24V_OUTat 4A (96W),

200LFM Air Flow Thermal Plot

TheMODE_PLLINisguaranteedtolocktoanexternalclock

source whose frequency is between 75kHz and 850kHz.

Rev. 0

16

For more information www.analog.com

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

Thermal Considerations and Output Current Derating

This environment is sometimes referred to as “still air”

although natural convection causes the air to move.

This value is determined with the part mounted to a

JESD 51-9 defined test board, which does not reflect an

actual application or viable operating condition.

The thermal resistances reported in the Pin Configura-

tion section of the data sheet are consistent with those

parameters defined by JESD51-9 and are intended for

use with finite element analysis (FEA) software modeling

tools that leverage the outcome of thermal modeling,

simulation, and correlation to hardware evaluation per-

formedonaµModulepackagemountedtoahardwaretest

board—also defined by JESD51-9 (Test Boards for Area

Array Surface Mount Package Thermal Measurements).

The motivation for providing these thermal coefficients is

found in JESD51-12 (Guidelines for Reporting and Using

Electronic Package Thermal Information).

θ ,thethermalresistancefromjunction-to-ambient,

JCbottom

is the natural convection junction-to-ambient air thermal

resistance measured in a one cubic foot sealed enclosure.

This environment is sometimes referred to as “still air”

although natural convection causes the air to move. This

value is determined with the part mounted to a JESD 51-9

defined test board, which does not reflect an actual ap-

plication or viable operating condition.

Many designers may opt to use laboratory equipment

and a test vehicle such as the demo board to anticipate

the µModule regulator’s thermal performance in their ap-

plicationatvariouselectricalandenvironmentaloperating

conditions to compliment any FEA activities. Without FEA

software, the thermal resistances reported in the Pin Con-

figuration section are in-and-of themselves not relevant to

providing guidance of thermal performance; instead, the

derating curves provided in the data sheet can be used in

a manner that yields insight and guidance pertaining to

one’s application usage, and can be adapted to correlate

thermal performance to one’s own application.

θ

, the thermal resistance from junction-to-top of the

JCtop

productcase,isdeterminedwithnearlyallofthecomponent

power dissipation flowing through the top of the package.

As the electrical connections of the typical µModule are

on the bottom of the package, it is rare for an application

to operate such that most of the heat flows from the junc-

tion to the top of the part. As in the case of θ

value may be useful for comparing packages but the test

conditions don’t generally match the user’s application.

, this

JCbottom

θ , the thermal resistance from junction to the printed

JB

circuit board, is the junction-to-board thermal resistance

where almost all of the heat flows through the bottom of

the µModule and into the board, and is really the sum of

The Pin Configuration section typically gives four thermal

coefficients explicitly defined in JESD 51-12; these coef-

ficients are quoted or paraphrased below:

the θ

and the thermal resistance of the bottom of

JCbottom

the part through the solder joints and through a portion

of the board. The board temperature is measured at a

specified distance from the package, using a two-sided,

two-layer board. This board is described in JESD 51-9.

θ , the thermal resistance from junction-to-ambient, is

JA

the natural convection junction-to-ambient air thermal

resistancemeasuredinaonecubicfootsealedenclosure.

ꢐꢑꢒꢏꢓꢎꢔꢒꢕꢓꢔꢕꢖꢆꢛꢎꢌꢒꢓ Rꢌꢗꢎꢗꢓꢖꢒꢏꢌ ꢘꢐꢌꢗꢋ ꢂꢜꢕꢝ ꢋꢌꢃꢎꢒꢌꢋ ꢛꢔꢖRꢋꢚ

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Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients

Rev. 0

17

For more information www.analog.com

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 8; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule.

loss as that which was simulated. An outcome of this

process and due-diligence yields a set of derating curves

provided in other sections of this data sheet. After these

laboratorytestshavebeenperformedandcorrelatedtothe

µModulemodel,thentheθ andθ aresummedtogether

JB

BA

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD 51-12 or provided in the

Pin Configuration section replicates or conveys normal

operatingconditionsofaµModule.Forexample,innormal

board-mounted applications, never does 100% of the

device’s total power loss (heat) thermally conduct exclu-

sivelythroughthetoporexclusivelythroughbottomofthe

to correlate quite well with the µModule model with no

airflow or heat sinking in a properly define chamber. This

θ

+ θ value is shown in the Pin Configuration section

BA

JB

and should accurately equal the θ value because ap-

JA

proximately 100% of power loss flows from the junction

through the board into ambient with no airflow or top

mounted heat sink.

µModule—asthestandarddefinesforθ

andθ

,

The 5V, 12V and 24V input power loss curves in Figure 9

toFigure11canbeusedincoordinationwiththeloadcurrent

derating curves in Figure 12 to Figure 17 for calculating

JCtop

JCbottom

respectively.Inpractice,powerlossisthermallydissipated

in bothdirectionsawayfromthepackage—granted, in the

absence of a heat sink and airflow, a majority of the heat

flow is into the board.

an approximate θ thermal resistance for the LTM4656

JA

with various heat sinking and airflow conditions. The

power loss curves are taken at room temperature, and

are increased with multiplicative factors according to the

ambient temperature. These approximate factors is 1.4

assuming the junction temperature at 120°C. The output

voltages are chosen to include the lower and higher out-

put voltage ranges for correlating the thermal resistance.

Thermal models are derived from several temperature

measurementsinacontrolledtemperaturechamberalong

withthermalmodelinganalysis.Thejunctiontemperatures

are monitored while ambient temperature is increased

with and without airflow. The power loss increase with

ambient temperature change is factored into the derating

curves. The junctions are maintained at 120°C maximum

while lowering output current or power with increasing

ambient temperature. The decreased output current will

decrease the internal module loss as ambient temperature

isincreased.Themonitoredjunctiontemperatureof120°C

minus the ambient operating temperature specifies how

much module temperature rise can be allowed. As an

example in Figure 15, the load current is derated to ~3.2A

at ~ 80°C with no air or heat sink and the power loss for

the 12V to 24V at 3.2A output is about 3W. The 4.48W

loss is calculated with the ~ 3W room temperature loss

from the 12V to 24V power loss curve at 3.2A, and the

1.4 multiplying factor. If the 80°C ambient temperature

is subtracted from the 120°C junction temperature, then

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-9topredictpowerlossheatflowandtemperature

readingsatdifferentinterfacesthatenablethecalculationof

theJEDEC-definedthermalresistancevalues;(3)themodel

and FEA software is used to evaluate the µModule with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

Rev. 0

18

For more information www.analog.com

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

ꢀ

ꢁ

ꢂ

ꢃ

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ꢁ

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Figure 9. Power Loss vs Load

Current 5V_INBased on LTM4656

Figure 10. Power Loss vs Load

Current 12V_INBased on LTM4656

Figure 11. Power Loss vs Load

Current 24V_INBased on LTM4656

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ꢑ0

ꢋ00

ꢋꢃ0

0

ꢋ0

ꢂ0

ꢁ0

ꢃ0

ꢀ00

ꢀꢋ0

0

ꢉ0

ꢋ0

ꢊ0

ꢀ0

ꢈ00

ꢈꢉ0

ꢇ

ꢈꢐꢊ

ꢇ

ꢈꢑꢊ

ꢄ

ꢅꢐꢇ

ꢆꢎꢏ

ꢉꢎꢏ

ꢉꢏꢐ

ꢀꢌꢂꢌ ꢍꢋꢃ

ꢂꢁꢌꢁ ꢍꢀꢎ

ꢋꢊꢌꢊ ꢍꢈꢋ

Figure 12. LTM4656 5V_IN12V_OUT

400kHz no HS

Figure 13. LTM4656 5V_IN24V_OUT

500kHz no HS

Figure 14. LTM4656 5V_IN36V_OUT

500kHz no HS

ꢀ.ꢁ

ꢀ.0

ꢂ.ꢁ

ꢂ.0

ꢃ.ꢁ

ꢃ.0

ꢋ.ꢁ

ꢋ.0

0.ꢁ

0

ꢉ.0

ꢀ.ꢈ

ꢀ.0

ꢊ.ꢈ

ꢊ.0

0.ꢈ

0

ꢉ

ꢈ

ꢀ

ꢊ

ꢋ

ꢌ

0

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

0

ꢃ0

ꢀ0

ꢌ0

ꢑ0

ꢋ00

ꢋꢃ0

0

ꢀ0

ꢋ0

ꢌ0

ꢑ0

ꢊ00

ꢊꢀ0

0

ꢋ0

ꢀ0

ꢉ0

ꢒ0

ꢌ00

ꢌꢋ0

ꢇ

ꢈꢐꢊ

ꢄ

ꢅꢐꢇ

ꢄ

ꢅꢑꢇ

ꢆꢏꢐ

ꢉꢎꢏ

ꢆꢎꢏ

ꢀꢌꢁꢌ ꢍꢋꢁ

ꢋꢌꢈꢌ ꢍꢊꢌ

ꢀꢉꢈꢉ ꢍꢌꢎ

Figure 17. LTM4656 24V_IN36V_OUT

650kHz no HS

Figure 15. LTM4656 12V_IN24V_OUT

550kHz no HS

Figure 16. LTM4656 12V_IN36V_OUT

650kHz no HS

Rev. 0

19

For more information www.analog.com

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

Table 2. 12V Output

DERATING CURVE

Figure 12

V (V)

POWER LOSS CURVE AIRFLOW (LFM)

HEAT SINK

None

θ (°C/W)

IN

JA

5

Figure 9

0

200

400

10

8

7.5

Figure 12

None

Table 3. 24V Output

DERATING CURVE

Figures 13, 15

V (V)

POWER LOSS CURVE AIRFLOW (LFM)

HEAT SINK

None

θ (°C/W)

IN

JA

5, 12

Figure 10

0

200

400

10

8

7.5

None

Table 4. 36V Output

DERATING CURVE

Figures 14, 16, 17

V (V)

POWER LOSS CURVE AIRFLOW (LFM)

HEAT SINK

None

θ (°C/W)

IN

JA

5, 12, 24

Figure 11

0

200

400

10

8

7.5

None

Table 5. Capacitor Matrix

BV

MAX IN 8.5A

C

OUT

IN

(CER)

(μF)

(BULK)

(μF)

V

FREQ

(kHz)

OUT

(W)

(CER)

(μF)

C

OUT

V

(V)

LOAD

5

I

IN

DC

(Bulk)

IN

100

22

10

5

8

300

400

500

550

650

500

650

8.65

9.34

7.18

7.83

8.68

8.42

7.95

8.02

5.94

7.70

0.38

0.58

0.79

0.86

0.40

0.50

0.67

0.57

0.14

0.33

40

43.2

32.4

36

10 ×2

100µF, 30mΩ ×2

5

12

24

36.

20

24

36

28

36

3.6

1.35

1

5

12

24.

24

5

100

96

4

2.5

3.25

5

90

91

140

180

5

BV BULK

Suncon HVA Series

100µF, 10V

100µF, 16V

100µF, 25V

V

BULK

Suncon HVA Series

100µF, 16V

100µF, 25V

150µF, 35V

82µF, 50V

10µF, 25V

10µF, 50V

IN

OUT

Suncon HVPF Series

Suncon HVT Series

Suncon HVP Series

BV CER

IN

Murata GRM31CR71A226K

22µF, 16V

10µF, 25V

10µF, 50V

CER

Murata GRM32DR71E106KA12L

Murata GRM32ER71H106KA12L

OUT

Murata GRM32ER61C226ME20

Murata GRM31CR71E106KA12L

Murata GRM32ER71H106KA12L

Rev. 0

20

For more information www.analog.com

LTM4656/LTM4656-1

APPLICATIONS INFORMATION

the difference of 40°C divided by 4.48W equals a 9°C/W

JA

•

Do not put via directly on the pad, unless they are

capped or plated over.

θ

thermal resistance. Table 2 specifies a 10°C/W value

which is very close. Table 2, Table 3, and Table 4 provide

equivalent thermal resistances for 12V, 24V and 36V out-

putswithandwithoutairflowandheatsinking.Thederived

thermal resistances in Table 2 to Table 4 for the various

conditions can be multiplied by the calculated power loss

asafunctionofambienttemperaturetoderivetemperature

rise above ambient, thus maximum junction temperature.

Room temperature power loss can be derived from the ef-

ficiencycurvesintheTypicalPerformanceCharacteristics

section and adjusted with the above ambient temperature

multiplicativefactors.Theprintedcircuitboardisa1.6mm

thick four-layer board with two-ounce copper for the two

outer layers and one-ounce copper for the two inner lay-

ers. The PCB dimensions are 95mm × 76mm.

Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

•

Forparallelmodules, tietheV , COMP, SS, andSDHN

FB

pins together. Use an internal layer to closely connect

these pins together. The TRACK pin can be tied a com-

mon capacitor for regulator soft-start.

•

Bringouttestpointsonthesignalpinsformonitoring.

Figure18givesagoodexampleoftherecommendedlayout.

ꢆꢇꢈꢉꢆꢊꢋꢌ ꢉꢊꢇꢍꢈ ꢎꢋꢇ

ꢒꢊꢓ

ꢏ

ꢉꢊ

SAFETY CONSIDERATIONS

ꢐꢑꢊꢐꢑ

ꢒꢊꢓ

The LTM4656 modules do not provide galvanic isolation

from V to V . There is no internal fuse. The device

IN

OUT

does support thermal shutdown and overcurrent protec-

tion with retry. If required, a slow blow fuse with a rating

twice the maximum input current needs to be provided to

protect each unit from catastrophic failure.

ꢔꢏ

ꢉꢊ

ꢏ

ꢆꢍꢈ

ꢔꢏ ꢎꢋꢇꢐ

ꢉꢊ

LAYOUT CHECKLIST/EXAMPLE

ꢒꢊꢓ

The high integration of LTM4656 makes the PCB board

layoutverysimpleandeasy.However,tooptimizeitselectri-

cal and thermal performance, some layout considerations

are still necessary.

ꢀꢁꢂꢁ ꢃꢄꢅ

ꢕꢖꢗ ꢈꢆꢇ ꢌꢋꢘꢑRꢙ ꢌꢈꢚꢀꢁꢂꢁ ꢄꢁꢛꢛ ꢜ ꢄꢁꢛꢛ

ꢋꢈꢌ

ꢆ

ꢇꢈ

•

Use large PCB copper areas for high current paths,

includingV ,BV GNDandV .Ithelpstominimize

IN

OUT

ꢉꢊꢈꢉꢊ

ꢋꢈꢌ

the PCB conduction loss and thermal stress.

•

Placehighfrequencyceramicinputandoutputcapaci-

torsnexttotheBV , PGNDandV

pinstominimize

IN

OUT

ꢐꢆ

ꢆ

ꢍꢎꢏ

ꢇꢈ

high frequency noise.

•

Place a dedicated power ground layer underneath

the unit.

ꢐꢆ ꢛꢖꢜꢉ

ꢇꢈ

ꢋꢈꢌ

Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

ꢀꢁꢂꢁ ꢃꢄꢅ

ꢑꢒꢓ ꢐꢍꢏꢏꢍꢔ ꢕꢖꢗꢊRꢘ ꢕꢏꢔꢀꢁꢂꢁ ꢄꢁꢙꢙ ꢚ ꢄꢁꢙꢙ

Figure 18. Recommended PCB Layout

Rev. 0

21

For more information www.analog.com

LTM4656/LTM4656-1

TYPICAL APPLICATIONS

ꢀꢁ ꢂRꢃꢄꢅꢆꢄꢅꢇ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃ

ꢁꢂ

ꢄꢄ

ꢀꢁꢂꢃ

ꢄꢄ

SHDN

ꢀ.ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢂꢃ

ꢀꢁ

ꢀ.ꢁꢂꢃ

ꢄꢅRꢆ ꢇꢆ

ꢀꢁ.ꢂꢃ

ꢀꢁ ꢂRꢃꢄꢅꢆꢄꢅꢇ

ꢂꢃ

ꢀꢀ

ꢀꢀꢁꢂ

ꢀꢁꢂ

0.ꢀꢁꢂ

ꢀꢁ

ꢀ00ꢁꢂ

ꢀꢁꢂꢃꢄꢅꢄ

ꢀꢁꢂ

FLT

FꢀꢁLT

ꢀꢁꢂ ꢃꢄ ꢅ.ꢁꢆꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢆꢇꢈ

ꢄꢄ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀ0ꢁꢂ

ꢀꢁꢂ

ꢀ0ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢁꢂ

Rꢀ

ꢁꢀ.ꢂꢃ

ꢀRꢁꢂ

ꢀꢁꢂ

ꢀ0.ꢁꢂ

ꢀꢁꢂꢃ

ꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢁ ꢃꢄꢅ

PINS UNUSED IN THIS APPLICATION:

ꢀꢁ ꢀꢂꢃꢄ ꢃꢁꢅꢆꢀꢁR

ꢆꢇRꢈ Rꢉꢊꢈ ꢋꢌꢇꢍꢈ ꢎꢏꢊꢎꢏꢄꢈ ꢎꢐ

Figure 19. 5V Input to 12V_OUTat 3.25A Design

ꢀꢁ ꢂRꢃꢄꢅꢆꢄꢅꢇ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃ

ꢁꢂ

ꢄꢄ

ꢀꢁꢂꢃ

ꢄꢄ

SHDN

ꢀ.ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢂꢃ

ꢀꢁ

ꢀ.ꢁꢂꢃ

ꢄꢅRꢆ ꢇꢆ

ꢀꢁ.ꢂꢃ

ꢀꢁ ꢂRꢃꢄꢅꢆꢄꢅꢇ

ꢂꢃ

ꢀꢀ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀꢀꢁꢂ

ꢀꢁꢂ

0.ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢄ

ꢀꢁꢂ

FLT

FꢀꢁLT

ꢀꢁꢂ ꢃꢄ ꢅ.ꢆꢇꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢆꢇꢈ

ꢄꢄ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀꢁ0ꢂꢃ

ꢀꢁꢂ

ꢀ0ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢁꢂ

Rꢀ

ꢁꢁ.ꢂꢃ

ꢀRꢁꢂ

ꢀꢁꢂ

ꢀ0.ꢁꢂ

ꢀꢁꢂꢃ

ꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢁ ꢃꢄ0ꢅ

PINS UNUSED IN THIS APPLICATION:

ꢀꢁ ꢀꢂꢃꢄ ꢃꢁꢅꢆꢀꢁR

ꢆꢇRꢈ Rꢉꢊꢈ ꢋꢌꢇꢍꢈ ꢎꢏꢊꢎꢏꢐꢈ ꢎꢑ

Retry Cycle

Short Circuit Trip

V

ꢆ

ꢅꢇ

ꢀꢆꢃꢄꢅꢆ

IN

5V/DIV

V

ꢆ

ꢈꢉꢊ

ꢋ0ꢆꢃꢄꢅꢆ

OUT

10V/DIV

I

IN

ꢊꢅꢗꢘR ꢙꢅꢇ ꢋꢆꢃꢄꢅꢆ

ꢀꢁꢂꢃꢄꢅꢆ

5A/DIV*

ꢊ

ꢌꢈꢈꢍ

ꢎꢏꢐꢀꢁꢂꢑ

TIMER PIN

1V/DIV

4656 F20b

ꢒꢓꢀꢓ ꢔꢕ0ꢖ

200ms/DIV

*25mV SENSE IN FOLDBACK

TIMER (218μs)

Figure 20. 5V Input to 24V_OUTat 1.35A Design

Rev. 0

22

For more information www.analog.com

LTM4656/LTM4656-1

TYPICAL APPLICATIONS

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂ

ꢀꢁꢂꢃ

ꢄꢄ

SHDN

ꢀ.ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢂꢃ

ꢀꢁ

ꢀ0ꢁ

ꢂꢃRꢄ ꢅꢄ

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈ

ꢂꢃ

ꢀꢀ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀꢀꢁꢂ

ꢀꢁꢂ

0.ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢄꢆꢇ

ꢀꢁꢂ

FLT

FꢀꢁLT

ꢀꢁꢂ ꢃꢄ ꢁꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢆꢇꢈ

ꢄꢄ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀ0ꢁꢂ

ꢀꢁꢂ

ꢀ

ꢁꢂ

ꢀꢁꢂꢃ

ꢀRꢁꢂ

Rꢀ

ꢁꢁ.ꢂꢃ

ꢀ0.ꢁꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢄ

ꢀꢁꢂꢃ

PINS UNUSED IN THIS APPLICATION:

R R

ꢀꢁꢂ

0.0ꢀꢁꢂ

ꢀꢁ ꢀꢂꢃꢄ ꢃꢁꢅꢆꢀꢁR

ꢀ00ꢁꢂ

Figure 21. 12V Input to 24V_OUTat 4A Design

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈꢉꢀ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂ

ꢀꢁꢂꢃ

ꢄꢄꢅ

SHDN

ꢀ.ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢂꢃ

ꢀ0ꢁ

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈꢉꢀ

ꢀꢀ

ꢀꢁ

ꢂꢃ

ꢀꢀ

ꢀꢀꢁꢂ

ꢀꢁꢂ

0.ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀ00ꢁꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢄ

FLT

FꢀꢁLT

ꢀꢁꢂ ꢃꢄ ꢁꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢆꢇꢈ

ꢀ

ꢁꢂ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀ0ꢁꢂ

ꢀꢁꢂ

ꢀ0ꢁꢂ

ꢀ

ꢁꢂ

ꢀꢁꢂꢃ

Rꢀ

ꢁꢁ.ꢂꢃ

ꢀꢁꢂꢃ

ꢀRꢁꢂ

ꢀꢁꢂ

ꢄ

ꢀꢁ.ꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢀꢃ ꢄꢅꢆꢀ

0ꢇꢈꢉꢊꢄꢋ

ꢀꢁꢂꢃ

ꢄꢄꢅ

ꢁ

ꢀꢁ ꢀꢂꢃꢄ ꢃꢁꢅꢆꢀꢁR

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈꢉꢁ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂ ꢃꢄ ꢅꢃ

ꢀꢁꢂꢀꢃ ꢄꢅꢆꢀ

ꢇꢈ0ꢉꢊꢋꢌꢄꢍ

0.ꢀꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ0ꢅꢆꢇ

ꢀ

ꢁꢂꢃꢄ

ꢀ00ꢁ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢁꢂ

ꢄꢄ

ꢀꢁꢂꢃ

ꢄꢄꢅ

ꢀꢁꢂ

SHDN

ꢀ.ꢁꢂꢃ

ꢀ00ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢂꢃ

ꢀ0ꢁ

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈꢉꢁ

ꢀꢀ

ꢀꢁ

ꢂꢃ

ꢀꢀ

ꢀꢀꢁꢂ

0.ꢀꢀꢁꢂ

ꢀꢁꢂ

ꢀ00ꢁꢂ

ꢀꢁꢂꢃꢄꢅꢄ

ꢀꢁꢂ

FLT

FꢀꢁLT

ꢀꢁꢂ ꢃꢄ ꢁꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢆꢇꢈ

ꢀ

ꢁꢂ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀ0ꢁꢂ

ꢀ

ꢁꢂ

ꢀꢁꢂꢃ

Rꢀ

ꢁꢁ.ꢂꢃ

ꢀꢁꢂꢃ

ꢀRꢁꢂ

ꢀꢁꢂ

ꢄ

ꢀꢁ.ꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢅ

PINS UNUSED IN THIS APPLICATION:

ꢀꢁ ꢀꢂꢃꢄ ꢃꢁꢅꢆꢀꢁR

R R

Figure 22. 2-Phase 12V Input to 24V_OUTat 8A Design

Rev. 0

23

For more information www.analog.com

LTM4656/LTM4656-1

TYPICAL APPLICATIONS

ꢀꢁ ꢂRꢃꢄꢅꢆꢄꢅꢇ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁ

ꢀ

ꢀꢁꢂꢃ

ꢄꢄ

ꢁꢂ

ꢀꢁꢂꢃ

ꢄꢄ

SHDN

ꢀ.ꢁꢂꢃ

ꢀꢁ

ꢀ.ꢁꢂꢃ

ꢄꢅRꢆ ꢇꢆ

ꢀꢁꢂꢂꢃ

ꢀꢁ.ꢂꢃ

ꢀꢁ ꢂRꢃꢄꢅꢆꢄꢅꢇ

ꢀꢁ

ꢂꢃ

ꢀꢀ

ꢀꢀꢁꢂ

ꢀꢁꢂ

0.ꢀꢁꢂ

ꢀꢁꢂ

ꢀ00ꢁꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢄ

FLT

FꢀꢁLT

ꢀꢁꢂ ꢃꢄ 0.ꢅꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢆꢇꢈ

ꢄꢄ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀ0ꢁꢂ

ꢀ0ꢁ

ꢀ

ꢁꢂ

Rꢀ

ꢁ.ꢂꢃ

ꢀRꢁꢂ

ꢀ0ꢁ

ꢀꢁ.ꢂꢃ

ꢀꢁꢂꢃ

ꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢁ ꢃꢄꢅ

PINS UNUSED IN THIS APPLICATION:

ꢆꢇRꢈ Rꢉꢊꢈ ꢋꢌꢇꢍꢈ ꢎꢏꢊꢎꢏꢐꢈ ꢎꢑ

ꢀꢁ ꢀꢂꢃꢄ ꢃꢁꢅꢆꢀꢁR

ꢀꢁꢂꢃꢄꢅꢆꢅ

Figure 23. 5V Input to 36V_OUTat 0.8A Design

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀ

ꢁꢂ

ꢀꢁꢂꢃ

ꢄꢄ

ꢀꢁꢂꢃ

ꢄꢄ

SHDN

ꢀ.ꢁꢂꢃ

ꢀꢁ

ꢂꢃRꢄ ꢅꢄ

ꢀꢁꢂꢂꢃ

ꢀꢁ.ꢂꢃ

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈ

ꢀꢁ

ꢂꢃ

ꢀꢀ

ꢀꢀꢁꢂ

ꢀꢁꢂ

0.ꢀꢁꢂ

ꢀꢁꢂ

ꢀ00ꢁꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢄ

FLT

FꢀꢁLT

ꢀꢁꢂ ꢃꢄ ꢅ.ꢆꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢆꢇꢈ

ꢄꢄ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀ0ꢁꢂ

ꢀ0ꢁ

ꢀ

ꢁꢂ

Rꢀ

ꢁꢀ.ꢂꢃ

ꢀRꢁꢂ

ꢀ0ꢁ

ꢀꢁ.ꢂꢃ

ꢀꢁꢂꢃ

ꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢁ ꢃꢄꢀ

PINS UNUSED IN THIS APPLICATION:

ꢅꢆRꢇ Rꢈꢉꢇ ꢊꢋꢆꢌꢇ ꢍꢎꢉꢍꢎꢏꢇ ꢍꢐ

ꢀꢁ ꢀꢂꢃꢄ ꢃꢁꢅꢆꢀꢁR

ꢀꢁꢂꢃꢄꢅꢆꢅ

Figure 24. 12V Input to 36V_OUTat 2.5A Design

Rev. 0

24

For more information www.analog.com

LTM4656/LTM4656-1

TYPICAL APPLICATIONS

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢁꢂ

ꢄꢄ

ꢀꢁꢂꢃ

ꢄꢄ

SHDN

ꢀ.ꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢂꢃ

ꢀꢁꢂ

ꢃꢄRꢅ ꢆꢅ

ꢀ.0ꢁꢂ

ꢀꢁꢂ ꢃRꢄꢅꢆꢇꢅꢆꢈ

ꢀꢁ

ꢂꢃ

ꢀꢀ

ꢀꢀꢁꢂ

ꢀꢁꢂ

0.ꢀꢁꢂ

ꢀꢁꢂ

ꢀ00ꢁꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢄ

FLT

FꢀꢁLT

ꢀꢁꢂ ꢃꢄ ꢅꢃ

ꢀ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢆꢇꢈ

ꢄꢄ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀ0ꢁꢂ

ꢀ0ꢁ

ꢀ

ꢁꢂ

Rꢀ

ꢁ.ꢂꢃ

ꢀRꢁꢂ

ꢀ0ꢁ

ꢀꢁ.ꢂꢃ

ꢀꢁꢂꢃ

ꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢁ ꢃꢄꢂ

PINS UNUSED IN THIS APPLICATION:

ꢅꢆRꢇ Rꢈꢉꢇ ꢊꢋꢆꢌꢇ ꢍꢎꢉꢍꢎꢏꢇ ꢍꢐ

ꢀꢁ ꢀꢂꢃꢄ ꢃꢁꢅꢆꢀꢁR

ꢀꢁꢂꢃꢄꢅꢆꢅ

Figure 25. 24V Input to 36V_OUTat 5A Design

Rev. 0

25

For more information www.analog.com

LTM4656/LTM4656-1

PIN CONFIGURATION TABLE

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

LTM4656Y Component BGA Pinout

PIN ID

A1

FUNCTION

PIN ID

B1

FUNCTION

PIN ID

C1

FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID

FUNCTION

SHDN

GND

BV

IN

BV

IN

BV

IN

BV

IN

BV

D1

D2

BV

E1

E2

GND

NC

F1

F2

IN

A2

B2

C2

A3

B3

C3

D3

E3

F3

GND

A4

B4

C4

D4

GND

E4

GND

F4

GND

A5

GND

B5

GND

C5

GND

D5

E5

F5

GND

A6

B6

C6

D6

E6

F6

COMP

SS

A7

SENSE1

B7

SENSE1

C7

SENSE1

D7

E7

F7

A8

B8

C8

D8

E8

V

F8

PGOOD

FB

A9

V

IN

V

IN

V

IN

V

IN

B9

V

C9

V

D9

E9

GND

F9

V

BIAS

IN

A10

A11

A12

B10

B11

B12

C10

C11

C12

D10

D11

D12

V

IN

V

IN

V

IN

E10

E11

E12

F10

F11

F12

GND

PIN ID

G1

FUNCTION

GND

PIN ID

H1

FUNCTION

GND

PIN ID

J1

FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID

FUNCTION

V

K1

K2

V

L1

L2

V

M1

M2

V

OUT

G2

GND

H2

UV

J2

G3

GND

H3

FLT

J3

K3

L3

M3

+

G4

TMR

H4

TEMP

J4

K4

L4

M4

–

G5

GND

H5

TEMP

J5

K5

L5

M5

G6

MODE_PLLIN

GND

H6

FREQ

RUN

GND

J6

K6

L6

M6

G7

H7

J7

GND

SW

K7

GND

SW

L7

GND

M7

GND

G8

GND

H8

J8

K8

L8

M8

G9

INTV

H9

J9

K9

L9

M9

CC

G10

G11

G12

GND

H10

H11

H12

J10

J11

J12

K10

K11

K12

L10

L11

L12

M10

M11

M12

Rev. 0

26

For more information www.analog.com

LTM4656/LTM4656-1

PACKAGE DESCRIPTION

ꢰ ꢰ ꢣ ꢣ ꢣ

ꢝ

ꢧ . ꢓ ꢮ ꢑ 0

ꢑ . ꢯ ꢄ ꢑ 0

ꢀ . ꢀ ꢀ ꢑ 0

ꢘ . ꢄ ꢯ ꢑ 0

ꢄ . ꢓ 0 ꢑ 0

0 . ꢧ ꢘ ꢑ 0

0 . 0 0 0 0

0 . ꢧ ꢘ ꢑ 0

ꢄ . ꢓ 0 ꢑ 0

ꢘ . ꢄ ꢯ ꢑ 0

ꢀ . ꢀ ꢀ ꢑ 0

ꢑ . ꢯ ꢄ ꢑ 0

ꢧ . ꢓ ꢮ ꢑ 0

ꢡ ꢡ ꢡ

ꢝ

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

27

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTM4656/LTM4656-1

PACKAGE PHOTO

DESIGN RESOURCES

SUBJECT

DESCRIPTION

µModule Design and Manufacturing Resources Design:

Manufacturing:

• Selector Guides

• Quick Start Guide

• Demo Boards and Gerber Files

• Free Simulation Tools

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

Digital Power System Management

Analog Devices’ family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTM4661

5.5V , 15V , 4A Boost µModule

1.8V ≤ V ≤ 5.5V, 2.5V ≤ V

≤ 15V. 6.25mm × 6.25mm × 2.42mm BGA.

≤ 16V. 15mm × 15mm × 2.82mm LGA.

≤ 24V. 15mm × 15mm × 2.82mm LGA.

≤ 34V. 15mm × 15mm × 2.82mm LGA.

IN

OUT

IN

OUT

Regulator.

LTM4605

LTM4607

LTM4609

LTM8054

LTM8055

LTM8056

20V , 20V , 12A Buck-Boost

4.5V ≤ V ≤ 20V, 0.8V ≤ V

IN

OUT

µModule Regulator. External Inductor.

36V , 24V , 10A Buck-Boost

4.5V ≤ V ≤ 36V, 0.8V ≤ V

IN

OUT

IN

µModule Regulator. External Inductor.

36V , 34V , 10A Buck-Boost

4.5V ≤ V ≤ 36V, 0.8V ≤ V

IN

OUT

IN

µModule Regulator. External Inductor.

15mm × 15mm × 3.42mm BGA.

36V , 36V , 5.4A Buck-Boost

5V ≤ Vin ≤ 36V, 1.2V ≤ V

≤ 36V. 11.25mm × 15mm × 3.42mm BGA.

≤ 36V. 15mm × 15mm × 4.92mm BGA.

≤ 48V. 15mm × 15mm × 4.92mm BGA.

IN

OUT

uModule Regulator. Integrated Inductor.

36V , 36V , 8.5A Buck-Boost

5V ≤ V ≤ 36V, 1.2V ≤ V

IN

OUT

IN

uModule Regulator. Integrated Inductor.

58V , 48V , 5.4A Buck-Boost

5V ≤ V ≤ 58V, 1.2V ≤ V

IN

OUT

IN

uModule Regulator. Integrated Inductor.

Rev. 0

09/20

www.analog.com

28

For more information www.analog.com


型号：	LTM4656EY
厂家：	ADI
描述：	Synchronous Boost Î¼Module Regulator with Input-Output Short Protection
文件：	总28页 (文件大小：2696K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4656EY [ADI]

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