LTM4680 [ADI]
Quad 31.25A or Single 125A μModule Regulator with Digital Power System Management;型号: | LTM4680 |
厂家: | ADI |
描述: | Quad 31.25A or Single 125A μModule Regulator with Digital Power System Management |
文件: | 总132页 (文件大小:3781K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM4681
Quad 31.25A or Single 125A µModule Regulator
with Digital Power System Management
FEATURES
DESCRIPTION
The LTM®4681 is a quad 31.25A or single 125A step-
down µModule® (power module) DC/DC regulator fea-
turing remote configurability and telemetry-monitoring
of power management parameters over PMBus. The
LTM4681 is comprised of digitally programmable analog
control loops, precision mixed-signal circuitry, EEPROM,
power MOSFETs, inductors and supporting components.
n
Quad Digitally Adjustable Analog Loops with Digital
Interface for Control and Monitoring
n
n
n
n
n
n
n
n
n
n
Wide Input Voltage Range: 4.5V to 16V
Output Voltage Range: 0.5V to 3.3V
0.5ꢀ Maꢁiꢂuꢂ DC Output ꢃrror Oꢄer ꢅeꢂperature
4ꢀ Current Readbacꢆ Accuracy: 0ꢇC to 1ꢈ5ꢇC
Integrated Input Current Sense Aꢂplifier
400ꢆHz PMBus-Coꢂpliant I C Serial Interface
Supports ꢅeleꢂetry Polling Rates Up to 1ꢈ5Hz
Integrated 16-Bit ∆Σ ADC
Parallel and Current Share Multiple Modules
15mm × 22mm × 8.17mm BGA Package
ꢈ
The LTM4681’s 2-wire serial interface allows outputs
to be margined, tuned and ramped up and down at pro-
grammable slew rates with sequencing delay times. True
input current sense, output currents and voltages, output
power, temperatures, uptime and peak values are read-
able. Custom configuration of the EEPROM contents is not
required. At start-up, output voltages, switching frequency,
and channel phase angle assignments can be set by pin-
strapping resistors. The LTpowerPlay® GUI and DC1613
USB-to-PMBus converter and demo kits are available.
Readable Data:
n
Input and Output Voltages, Currents, and Temperatures
n
Running Peak Values, Uptime, Faults and Warnings
n
Onboard EEPROM Fault Log Record
Writable Data and Configurable Paraꢂeters:
n
Output Voltage, Voltage Sequencing and Margining
Digital Soft-Start/Stop Ramp, Program Analog Loop
OV/UV/OT, UVLO, Frequency and Phasing
n
n
The LTM4681 is offered in a 15mm × 22mm × 8.17mm
BGA package available with SnPb or RoHS compliant
terminal finish.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258,
7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.
APPLICATIONS
n
Multi-Rail Processor Power, Configurable Core Power
TYPICAL APPLICATION
Channel ꢃfficiency ꢄs Load Current
ꢎꢏ
Quad 31.ꢈ5A µModule Regulator with Digital Interface for Control and Monitoring
ꢎꢒ
ꢎꢔ
ꢎꢓ
ꢎꢕ
ꢎ0
ꢐꢎ
ꢐꢐ
ꢐꢖ
ꢐꢑ
ꢐꢏ
ꢑ.ꢒꢓ ꢉꢁ ꢔꢕꢓ
0.ꢜꢓ ꢌꢉ ꢛꢔ.ꢘꢒꢌ
ꢐꢃR
ꢤ
ꢓ
ꢈꢇꢠ0ꢔ
ꢁꢍꢉ0
ꢘꢘꢙꢋ
ꢚꢕ
ꢤ
ꢓ
ꢓ
ꢁꢊꢇꢊ0
R
ꢊꢃꢇꢊꢃꢔ
ꢊꢃꢇꢊꢃꢘ
ꢤ
ꢣ
ꢎꢁꢌꢅ
ꢎꢁꢌꢅ
ꢎꢁꢌꢅ
ꢎꢁꢌꢅ
ꢈꢇꢠ0ꢔ
ꢐ
ꢖꢍꢎꢗ
ꢣ
ꢁꢊꢇꢊ0
ꢓ
ꢈꢇ0ꢔ
ꢊꢓ
ꢔꢓ ꢌꢉ ꢛꢔ.ꢘꢒꢌ
ꢐꢃR
ꢤ
ꢑ.ꢒꢓ ꢉꢁ ꢔꢕꢓ
ꢈꢇꢠ0ꢔ
ꢤ
ꢓ
ꢁꢍꢉꢔ
ꢤ
ꢈꢇꢠꢘꢛ
ꢓ
ꢓ
ꢁꢊꢇꢊꢔ
ꢘꢘꢙꢋ
ꢚꢕ
R
ꢐ
ꢖꢍꢎꢗ
ꢣ
ꢣ
ꢈꢇꢠꢘꢛ
ꢁꢊꢇꢊꢔ
ꢓ
ꢓ
ꢈꢇꢘꢛ
ꢔ.ꢘꢓ ꢌꢉ ꢛꢔ.ꢘꢒꢌ
ꢐꢃR
ꢤ
ꢎꢉꢆꢑꢕꢝꢔ
ꢁꢍꢉꢘ
ꢤ
ꢕꢓꢘ ꢙ 0.ꢎꢘ ꢙ ꢓꢏ0ꢚꢛꢜ
ꢋꢆ ꢀꢁꢂ
ꢊꢓ
ꢈꢇꢠꢘꢛ
ꢓ
ꢓ
ꢁꢊꢇꢊꢘ
ꢕꢓꢘ ꢙ ꢕ.0ꢘ ꢙ ꢓꢏ0ꢚꢛꢜ
ꢓ
ꢈꢇꢠꢓꢖꢈꢌꢊ
ꢋꢆ
ꢋꢆ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢕꢓꢘ ꢙ ꢕ.ꢓꢘ ꢙ ꢔꢏ0ꢚꢛꢜ
Rꢍꢇꢀ
ꢐ
ꢖꢍꢎꢗ
ꢣ
ꢁꢊꢇꢊꢘ
ꢕꢓꢘ ꢙ ꢕ.ꢏꢘ ꢙ ꢒꢓꢏꢚꢛꢜ
ꢁꢇꢏꢁꢋꢋ ꢐꢁꢇꢉRꢁꢎ
ꢋꢌꢍꢎꢉ ꢈꢇꢉꢃRRꢍꢀꢉꢊ
Rꢍꢇ0ꢟꢔꢟꢘꢟꢛ
FAULT0,1,2,3
ꢀꢄꢁꢁꢅ0ꢟꢔꢟꢘꢟꢛ
ꢋꢆ
ꢔ.ꢒꢓ ꢌꢉ ꢛꢔ.ꢘꢒꢌ
ꢐꢃR
ꢤ
ꢓ
ꢁꢍꢉꢛ
0
ꢏ
ꢕ0
ꢕꢏ
ꢓ0
ꢓꢏ
ꢔ0
ꢔꢏ
ꢤ
ꢀꢁꢂꢃR ꢄꢁꢁꢅ ꢆꢁꢇꢈꢉꢁRꢊ
ꢓ
ꢓ
ꢁꢊꢇꢊꢛ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢒꢑꢐꢕ ꢂꢈ0ꢕꢗ
ꢐ
ꢖꢍꢎꢗ
ꢣ
ꢀꢁRꢂꢃ ꢄ.ꢅꢆ ꢇꢂ ꢅ.ꢅꢆ
ꢁꢊꢇꢊꢛ
Configurable Output Array
ꢈꢂꢉꢉꢊꢈꢇ ꢆ ꢌ ꢍꢆ
ꢌ
ꢋꢉ
ꢋꢉ
ꢎꢉꢏ ꢋꢉꢇꢆ ꢇꢂꢐꢊꢇꢑꢊRꢒ
ꢈꢈ
31.25A
ꢑꢕꢝꢔ ꢉꢌ0ꢔꢞ
62.5A
62.5A
62.5A
31.25A
31.25A
31.25A
93.75A
125A
Rev. 0
1
ꢁ
31.25A
ꢀꢁR ꢂꢁꢃꢄꢅꢆꢇꢆ ꢂꢈRꢂꢉꢈꢇ
ꢊꢆꢆ ꢀꢈꢋꢉRꢆ ꢌꢍ
ꢀꢁꢂꢃꢄRꢅꢂꢆꢇꢈꢉꢆꢅꢂ ꢉꢆꢊꢋ
ꢌꢈꢀꢋ RꢋꢍꢆꢀꢉꢋR ꢎRꢆꢉꢋ
ꢏRꢅꢉꢋꢃꢉꢆꢅꢂ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR
ꢆꢎꢏRꢑ ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
31.25A
31.25A
Document Feedback
For more information www.analog.com
LTM4681
TABLE OF CONTENTS
Features..................................................... 1
Applications ................................................ 1
ꢅypical Application ........................................ 1
Description.................................................. 1
ꢅable of Contents .......................................... ꢈ
Absolute Maꢁiꢂuꢂ Ratings.............................. 4
Order Inforꢂation.......................................... 4
Pin Configuration .......................................... 4
ꢃlectrical Characteristics................................. 5
ꢅypical Perforꢂance Characteristics ..................1ꢈ
Pin Functions..............................................16
Siꢂplified Blocꢆ Diagraꢂ ...............................ꢈ4
Decoupling Requireꢂents...............................ꢈ4
Functional Diagraꢂ ......................................ꢈ5
ꢅest Circuits ...............................................ꢈ6
ꢅest Circuits ...............................................ꢈ7
Operation...................................................ꢈ8
Power Module Introduction ....................................28
Power Module Overview, Major Features................28
EEPROM with ECC..................................................29
Power-Up and Initialization .....................................30
Soft-Start................................................................31
Time-Based Sequencing.........................................31
Voltage-Based Sequencing.....................................32
Shutdown ...............................................................32
Light-Load Current Operation .................................32
Switching Frequency and Phase.............................33
PWM Loop Compensation......................................33
Output Voltage Sensing ..........................................33
Table 3. FSWPH_nn_CFG Pin Strapping Look-Up
Table to Set the LTM4681’s Switching Frequency
and Channel Phase-Interleaving Angle (Not
Applicable if MFR_CONFIG_ALL[6] = 1b), nn = 0,1
or 2,3 Channels, set top resistor to 14.3k...........37
Table 4. ASEL_nn Pin Strapping Look-Up Table
to Set the LTM4681’s Slave Address (Applicable
Regardless of MFR_CONFIG_ALL[6] Setting) ....38
Table 5. LTM4681 MFR_ADDRESS Command
Examples Expressed in 7- and 8-Bit Addressing 38
Fault Detection and Handling..................................38
Status Registers and ALERT Masking...................39
Figure 5. LTM4681 Status Register Summary per
Controller............................................................40
Mapping Faults to FAULTn Pins............................. 41
Power Good Pins.................................................. 41
CRC Protection..................................................... 41
Serial Interface ....................................................... 41
Communication Protection................................... 41
Device Addressing.................................................. 41
Responses to V
and I /I
Faults ...................42
OUT
IN OUT
Output Overvoltage Fault Response .....................42
Output Undervoltage Response............................43
Peak Output Overcurrent Fault Response.............43
Responses to Timing Faults....................................43
Responses to V OV Faults....................................43
IN
Responses to OT/UT Faults.....................................43
Internal Overtemperature Fault Response.............43
Overtemperature and Undertemperature
INTV /V
Power...............................................33
Fault Response...................................................44
Responses to Input Overcurrent and Output
CC BIAS
Output Current Sensing and Sub Milliohm DCR
Current Sensing......................................................34
Input Current Sensing.............................................34
PolyPhase Load Sharing.........................................34
Internal Temperature Sense....................................35
RCONFIG (Resistor Configuration) Pins..................35
Table 1. VOUTn _CFG Pin Strapping Look-Up Table
for the LTM4681’s Output Voltage, Coarse Setting
(Not Applicable if MFR_CONFIG_ALL[6] = 1b) Top
Resistor = 14.3k..................................................36
Table 2. VTRIMn_CFG Pin Strapping Look-Up
Undercurrent Faults................................................44
Responses to External Faults..................................44
Fault Logging..........................................................44
Bus Timeout Protection..........................................44
2
Similarity Between PMBus, SMBus and I C 2-Wire
Interface .................................................................45
PMBus Serial Digital Interface................................45
Table 6. Abbreviations of Supported Data Formats ... 46
Figure 6. PMBus Timing Diagram.........................46
Figure 7 to Figure 24 PMBus Protocols ..................47
PMBus Coꢂꢂand Suꢂꢂary ............................50
PMBus Commands.................................................50
Table for the LTM4681’s Output Voltage, Fine
Adjustment Setting (Not Applicable if MFR_
CONFIG_ALL[6] = 1b) Top Resistor = 14.3k........36
Rev. 0
2
For more information www.analog.com
LTM4681
TABLE OF CONTENTS
Table 7. PMBus Commands Summary (Note: The Data
Format Abbreviations Are Detailed in Table 8)......... 50
Table 8. Data Format Abbreviations......................55
Applications Inforꢂation ................................56
Safety Considerations.............................................77
Layout Checklist/Example ......................................77
ꢅypical Applications......................................79
PMBus Coꢂꢂand Details ...............................84
Addressing and Write Protect.................................84
General Configuration Commands..........................86
On/Off/Margin ........................................................87
PWM Configuration ................................................89
Voltage....................................................................92
Input Voltage and Limits.......................................92
Output Voltage and Limits ....................................93
Output Current and Limits ......................................96
Input Current and Limits.......................................98
Temperature............................................................99
Power Stage DCR Temperature Calibration...........99
Power Stage Temperature Limits..........................99
Timing ..................................................................100
Timing—On Sequence/Ramp............................. 100
Timing—Off Sequence/Ramp ............................ 101
Precondition for Restart ..................................... 102
Fault Response ..................................................... 102
Fault Responses All Faults.................................. 102
Fault Responses Input Voltage ........................... 103
Fault Responses Output Voltage......................... 103
Fault Responses Output Current.........................106
Fault Responses IC Temperature ........................ 107
Fault Responses External Temperature............... 108
Fault Sharing......................................................... 109
Fault Sharing Propagation .................................. 109
Fault Sharing Response.......................................111
Scratchpad ............................................................111
Identification......................................................... 112
Fault Warning and Status...................................... 113
Telemetry.............................................................. 119
NVM Memory Commands .................................... 123
Store/Restore ..................................................... 123
Fault Logging...................................................... 124
Block Memory Write/Read.................................. 128
Pacꢆage Description ................................... 1ꢈ9
Table 25. LTM4681 BGA Pinout.......................... 129
Pacꢆage Description ................................... 130
Pacꢆage Photograph ................................... 13ꢈ
Design Resources ...................................... 13ꢈ
Related Parts............................................ 13ꢈ
V to V
Step-Down Ratios................................56
IN
OUT
Input Capacitors .....................................................56
Output Capacitors...................................................56
Light Load Current Operation .................................56
Switching Frequency and Phase.............................57
Output Current Limit Programming ........................58
Minimum On-Time Considerations..........................59
Variable Delay Time, Soft-Start and Output Voltage
Ramping .................................................................59
Digital Servo Mode.................................................59
Soft Off (Sequenced Off)........................................60
Undervoltage Lockout.............................................61
Fault Detection and Handling..................................61
Open-Drain Pins .....................................................61
Phase-Locked Loop and Frequency Synchronization .. 62
Input Current Sense Amplifier.................................63
Programmable Loop Compensation .......................63
Checking Transient Response.................................64
PolyPhase Configuration ......................................65
2
Connecting The USB to I C/SMBus/PMBus
Controller to the LTM4681 In System.....................65
LTpowerPlay: An Interactive GUI for Digital Power .66
PMBus Communication and Command Processing66
Thermal Considerations and Output Current Derating. 68
Table 10 through Table 12:Output Current Derating......... 71
Table 13. Single Channel Output Voltage vs
Capacitor Selection, 10A to 20A Load Step with
10A/µs Slew Rate ...............................................72
Table 14. Single Channel Output Voltage vs
Capacitor Selection, All Ceramic Configuration,
10A to 20A Load Step with 10A/µs Slew Rate ....73
Table 15. Dual Connected Channels Output Voltage
vs Capacitor Selection, Bulk and Ceramic Cap
Configuration, 10A to 30A Load Step with 20A/µs
Slew Rate ........................................................... 74
Table 16. Quad Connected Channels Output Voltage
vs Capacitor Selection, Bulk and Ceramic Cap
Configuration, 10A to 40A Load Step with 15A/µs
Slew Rate ........................................................... 74
Derating Curves......................................................75
EMI Performance....................................................77
Rev. 0
3
For more information www.analog.com
LTM4681
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ꢔꢜꢕ ꢛꢟꢍꢚ
ꢅerꢂinal Voltages:
+
−
V
(Note 4), SV
, I
, I
,
INnn
IN_nn IN_nn IN_nn
V
, RUNP.................................... –0.3V to 18V
IN_VBIAS
+
+
−
(SV
– I
), (I
– I
) ....... –0.3V to 0.3V
IN_nn
IN_nn
IN_nn
IN_nn
SWn............................ −1V to 18V, −5V to 18V Transient
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ0 ꢅꢅ ꢅꢆ ꢅꢇ ꢅꢈ ꢅꢀ
INTV
, V
......................................... –0.3V to 6V
........................................................ –0.3V to 3.6V
........................................................ –0.3V to 6V
..................................................... –0.3V to 0.3V
CC_nn BIAS
ꢉ
ꢛ
ꢏꢖꢌ
ꢜꢘꢔ0
V
V
V
OUTn
OSNSn
OSNSn
ꢊ
ꢛꢔRꢟꢗꢅꢞꢋꢎꢏ
ꢝꢌꢉꢞ0ꢅ
ꢝꢋꢓꢞ0ꢅ
ꢛ
ALERTꢞ0ꢅ
+
−
ꢌꢌꢆꢀꢞ0ꢅ
ꢋ
ꢛ
ꢟꢖ0ꢅ
ꢝꢙꢖꢋꢞ0ꢅ
ꢔꢝꢖꢝꢅ
ꢝꢚ0
ꢌ
ꢍ
ꢝꢐꢉRꢍꢞꢋꢓꢑꢞ0ꢅ
ꢚꢕꢞ0ꢅ
ꢛꢔRꢟꢗ0ꢞꢋꢎꢏ
ꢔꢝꢖꢝ0
ꢛ
ꢛ
ꢝꢏꢖꢌ0ꢅ
ꢌꢌꢇꢇꢞ0ꢅ
ꢮ
ꢎ
ꢜꢝꢖꢝꢅ
ꢰ
RUNn, SDA_nn, SCL_nn, ALERT_nn ......... –0.3V to 5.5V
FSWPH_nn_CFG, VOUTn_CFG,
VTRIMn_CFG, ASEL_nn ..................... –0.3V to 2.75V
FAULTn, SYNC_nn, SHARE_CLK_nn,
ꢛ
ꢋꢜꢗꢕꢅꢭ
ꢜꢘꢔꢅ
ꢏ
ꢐ
ꢒ
ꢛ
ꢋꢜꢗꢕ0ꢯ
ꢮ
ꢜꢝꢖꢝꢅ
ꢋꢜꢗꢕꢅꢯ
ꢕꢏꢜꢜꢌ0
ꢋꢜꢗꢕ0ꢭ
ꢝꢚꢅ
ꢕꢏꢜꢜꢌꢅ
ꢛ
ꢛ
ꢜꢝꢖꢝ0
ꢜꢝꢖꢝ0
ꢰ
ꢟꢖꢞ0ꢅ
ꢰ
ꢝꢛ
ꢟꢖꢞ0ꢅ
ꢮ
ꢟꢖꢔꢛ
ꢋꢋꢞ0ꢅ
ꢟꢖꢞ0ꢅ
ꢑ
ꢏꢖꢌ
ꢛ
ꢓ
ꢏꢖꢌ
ꢗ
ꢖ
ꢕ
ꢛ
ꢟꢖꢞꢛꢊꢟꢉꢝ
ꢊꢟꢉꢝ Rꢘꢖꢕ
ꢮ
WP_nn, PGOODn .................................. −0.3V to 3.6V
COMPna, COMPnb, .................................. –0.3V to 2.7V
TSNSn....................................................... –0.3V to 0.8V
n = 0, 1, 2, 3 and nn = 01, 23
ꢰ
ꢟꢖꢔꢛ
ꢋꢋꢞꢆꢇ
ꢟꢖꢞꢆꢇ
ꢛ
ꢛ
ꢜꢝꢖꢝꢆ
ꢝꢛ
ꢟꢖꢞꢆꢇ
ꢰ
ꢛ
ꢛ
ꢟꢖꢆꢇ
ꢟꢖꢞꢆꢇ
ꢜꢘꢔꢆ
ꢝꢚꢆ
ꢮ
R
ꢔ
ꢰ
ꢛ
ꢛ
ꢜꢝꢖꢝꢆ
ꢜꢝꢖꢝꢇ
ꢕꢏꢜꢜꢌꢆ
ꢕꢏꢜꢜꢌꢇ
ꢮ
ꢋꢜꢗꢕꢆꢯ
ꢜꢝꢖꢝꢇ
ꢔꢝꢖꢝꢇ
Rꢘꢖꢆ
ꢋꢜꢗꢕꢆꢭ
ꢘ
ꢛ
ꢔꢝꢖꢝꢆ
ꢝꢏꢖꢌꢆꢇ
ꢝꢌꢉꢞꢆꢇ
ꢋꢜꢗꢕꢇꢯ
ꢋꢜꢗꢕꢇꢭ
ꢚꢕꢞꢆꢇ
ꢝꢙꢖꢋꢞꢆꢇ
ꢝꢋꢓꢞꢆꢇ
FAULT2
FAULT3
V
and V
are outputs not to be driven.
DD25_nn
ꢝꢚꢇ
ꢚ
ꢙ
DD33_nn
ALERTꢞꢆꢇ
Rꢘꢖꢇ
ꢛ
ꢅeꢂperatures
Internal Operating Temperature Range
ꢌꢌꢇꢇꢞꢆꢇ
ꢉꢉ
ꢉꢊ
ꢛ
ꢜꢘꢔꢇ
ꢏꢖꢌ
(Notes 2, 13, 16, 17) .......................... –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Package Body Temperature... 245°C
ꢊꢏꢉ ꢕꢉꢋꢑꢉꢏꢍ
ꢇꢇ0ꢠꢓꢍꢉꢌ ꢡꢅꢀꢢꢢ ꢣ ꢆꢆꢢꢢ ꢣ ꢃ.ꢅꢂꢢꢢꢤ
ꢔ
ꢦ ꢅꢆꢀꢧꢋꢨ θ
ꢦ ꢆ.ꢃꢧꢋꢬꢚꢨ θ ꢦ ꢅ.ꢈꢧꢋꢬꢚꢨ θ ꢦ ꢈ.ꢂꢇꢧꢋꢬꢚ
ꢒꢋꢭꢪꢩꢩꢪꢢ ꢒꢉ
ꢒꢗꢉꢥ
ꢒꢋꢩꢪꢫ
ꢖꢜꢔꢍꢱ
ꢅꢤ θ ꢛꢉꢓꢘꢍꢝ ꢉRꢍ ꢌꢍꢔꢍRꢗꢟꢖꢍꢌ ꢊꢙ ꢝꢟꢗꢘꢓꢉꢔꢟꢜꢖ ꢕꢍR ꢒꢍꢝꢌꢀꢅ ꢋꢜꢖꢌꢟꢔꢟꢜꢖꢝꢨ ꢚꢍꢟꢏꢐꢔ ꢦ ꢅ0ꢲ.
ꢆꢤ θ ꢛꢉꢓꢘꢍ ꢟꢝ ꢜꢊꢔꢉꢟꢖꢍꢌ ꢚꢟꢔꢐ ꢌꢍꢗꢜ ꢊꢜꢉRꢌ.
ꢒꢉ
ꢇꢤ RꢍꢎꢍR ꢔꢜ ꢕꢉꢏꢍꢝ ꢂꢅꢨ ꢂꢀꢨ ꢂꢁ ꢎꢜR ꢓꢉꢊ ꢗꢍꢉꢝꢘRꢍꢗꢍꢖꢔ ꢉꢖꢌ ꢌꢍRꢉꢔꢟꢖꢏ ꢟꢖꢎꢜRꢗꢉꢔꢟꢜꢖ.
ORDER INFORMATION
PARꢅ MARKING*
PACKAGꢃ
ꢅYPꢃ
MSL
RAꢅING
ꢅꢃMPꢃRAꢅURꢃ RANGꢃ
(Sꢃꢃ NOꢅꢃ ꢈ)
PARꢅ NUMBꢃR
LTM4681EY#PBF
LTM4681IY#PBF
LTM4681IY
PAD OR BALL FINISH
SAC305 (RoHS)
SnPb (63/37)
DꢃVICꢃ
FINISH CODꢃ
LTM4681Y
LTM4681Y
LTM4681Y
e1
BGA
4
–40°C to 125°C
e0
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
Rev. 0
4
For more information www.analog.com
LTM4681
ELECTRICAL CHARACTERISTICS ꢅhe ldenotes the specifications which apply oꢄer the specified internal
operating teꢂperature range (Note ꢈ). Specified as each indiꢄidual output channel (Note 4). ꢅA = ꢈ5ꢇC, VIN = 1ꢈV, RUNn = 3.3V,
RUNP = 0, FRꢃQUꢃNCY_SWIꢅCH = 350ꢆHz and VOUꢅn coꢂꢂanded to 1.000V unless otherwise noted. Configured with factory-default
ꢃꢃPROM settings and per ꢅest Circuit 1, unless otherwise noted.
SYMBOL
PARAMꢃꢅꢃR
CONDIꢅIONS
MIN
ꢅYP
MAX
UNIꢅS
l
l
V
Input DC Voltage
Test Circuit 1
Test Circuit 2; VIN_OFF < VIN_ON = 4V
5.75
4.5
16
5.75
V
V
INnn
+
–
l
V
Range of Output Voltage Regulation
for Each Channel
V
Differentially Sensed on V
/V Pin-Pair;
OSNSn
0.5
3.34
V
V
OUTn
OUTn
OSNSn
Commanded by Serial Bus or with Resistors Present at
Start-Up on V
OUTn_CFG
l
V
V
Output Voltage, Total Variation with
Line and Load for Each Channel
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
0.995 1.000 1.005
0.985 1.000 1.015
V
V
OUTn(DC)
V
Commanded to 1.000V, V
Low Range
OUTn
OUTn
(MFR_PWM_MODEn[1] = 1b) (Notes 5, 6)
Undervoltage Lockout Threshold,
V
V
Falling
Rising
3.55
3.90
V
V
UVLO
INTVCC_nn
INTVCC_nn
When V < 4.3V
IN
Input Specifications
I
Input Inrush Current at
Start-Up
Test Circuit 1, V
=1V, V = 12V; No Load Besides
n
400
mA
INRUSH(VINn)
OUTn
IN
Capacitors; TON_RISE = 3ms
I
Input Supply Bias Current
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
RUNn = 3.3V
Shutdown, RUN0 = RUN1 = 0V
Q(SVIN)
25
23
mA
mA
I
I
Input Supply Current in Pulse-
Skipping Mode Operation
Pulse-Skipping Mode, MFR_PWM_MODEn[0] = 0b,
OUTn
20
mA
S(VINn,PSM)
S(VINn,FCM)
I
= 100mA
Input Supply Current in Forced-
Continuous Mode Operation
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
12V to 1V
2.89
50
A
I
= 31.25A
OUTn
I
Input Supply Current in Shutdown
Shutdown, RUNn = 0V
µA
S(VINn,SHUTDOWN)
Output Specifications
I
Output Continuous Current Range
Each Channel
(Note 6) Utilizing MFR_PWM_MODE[7] = 1 and Using
OUT
0
31.25
0.2
A
OUTn
~I
= 40 for IOUT_OC_FAULT_LIMIT, Page 97
∆V
Line Regulation Accuracy Each
Channel
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
0.03
0.03
%/V
%/V
OUTn(LINE)
l
V
OUTn
SV and V Electrically Shorted Together and INTV
IN
INn
CC
Open Circuit; I
= 0A, 5.75V ≤ V ≤ 16V, V
Low Range
OUTn
IN
OUT
(MFR_PWM_MODEn[1] = 1b), FREQUENCY_SWITCH =
350kHz (Note 5)
∆V
Load Regulation Accuracy Each
Channel
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
0.03
0.2
%
%
OUTn(LOAD)
l
l
0.5
V
OUTn
0A ≤ I
≤ 31.25A, V
Low Range, (MFR_PWM_
OUT
OUTn
MODEn[1] = 1b) (Notes 5, 6)
V
Output Voltage Ripple
10
350
8
mV
P-P
OUTn(AC)
f (Each Channel)
S
V
OUTn
Ripple Frequency
FREQUENCY_SWITCH Set to 350kHz (0xFABC)
320
370
kHz
mV
ms
∆V
OUTn(START)
Turn-On Overshoot
TON_RISEn = 3ms (Note 12)
l
l
t
Turn-On Start-Up Time
Time from V Toggling from 0V to 12V to Rising Edge
30
START
IN
PGOODn. TON_DELAYn = 0ms, TON_RISEn = 3ms
t
Turn-On Delay Time
Time from First Rising Edge of RUNn to Rising Edge of
PGOODn . TON_DELAYn = 0ms, TON_RISEn = 3ms,
2.75
3.3
50
3.8
ms
mV
DELAY(0ms)
V
Having Been Established for at Least 70ms
IN
∆V
Peak Output Voltage Deviation for
Dynamic Load Step
Load: 10A to 20A and 20A to 10A at 10A/µs,
= 1.2V, V = 12V (Note 12) See Transient Graph
OUTn(LS)
V
OUTn
IN
Rev. 0
5
For more information www.analog.com
LTM4681
ELECTRICAL CHARACTERISTICS ꢅhe ldenotes the specifications which apply oꢄer the specified internal
operating teꢂperature range (Note ꢈ). Specified as each indiꢄidual output channel (Note 4). ꢅA = ꢈ5ꢇC, VIN = 1ꢈV, RUNn = 3.3V,
RUNP = 0, FRꢃQUꢃNCY_SWIꢅCH = 350ꢆHz and VOUꢅn coꢂꢂanded to 1.000V unless otherwise noted. Configured with factory-default
ꢃꢃPROM settings and per ꢅest Circuit 1, unless otherwise noted.
SYMBOL
PARAMꢃꢅꢃR
CONDIꢅIONS
MIN
ꢅYP
MAX
UNIꢅS
t
Settling Time for Dynamic Load Step Load: 10A to 20A and 20A to 10A at 10A/µs,
25
µs
SETTLE
per Channel
V
= 1.2V, V = 12V (Note 12) See Transient Graphs
OUTn IN
I
Output Current Limit, Peak High
Range per Channel
Cycle-by-Cycle Inductor Peak Current Limit Inception,
46
A
OUTn(OCL_PK)
Utilizing MFR_PWM_MODE[7] = 1, Using ~I
IOUT_OC_FAULT_LIMIT, Page 97
= 34A for
OUT
I
Output Current Limit, Time Averaged Time-Averaged Output Inductor Current Limit Inception
40; See I
OUTn(OCL_AVG)
O-RB-ACC
Specification (Output Current
Readback Accuracy)
per Channel
Threshold, Commanded by IOUT_OC_FAULT_LIMIT
(Note 12)
n
Utilizing MFR_PWM_MODE[7] = 1, Using ~I
Page 97
= 40A,
OUT
Control Section
–
+
l
l
V
Channel 0 - 3 Feedback Input
Common Mode Range
V
V
Valid Input Range (Referred to SGND)
–0.1
−0.5
0.3
3.6
V
V
FBCMn
OSNSn
OSNSn
Valid Input Range (Referred to SGND)
V
Full-Scale Command Voltage, Range
Low (0.5V to 2.75V, Note 15) per
Channel
V
Commanded to 2.750V, MFR_PWM_MODEn[1] = 1b
OUTn
2.75
V
%
Bits
mV
OUT-RNGL
Set Point Accuracy
Resolution
LSB Step Size
+0.5
12
0.688
V
Full-Scale Command Voltage, Range
High (0.5V to 3.6V, Note 15) per
Channel
V
Commanded to 3.6V, MFR_PWM_MODEn[0] = 1b
OUTn
3.6
V
OUT-RNGH
Limit Design to 3.6V Operating for Module
Set Point Accuracy
−0.5
+0.5
%
Bits
mV
Resolution
LSB Step Size
12
1.375
+
+
+
R
V
Impedance to SGND
0.05V ≤ V
– V ≤ 3.3V
SGND
50
60
kΩ
ns
VSNSn
OSNSn
VOSNSn
t
Minimum On-Time
(Note 8 ) per Channel
ON(MIN)
R
Resolution
MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1, Note
Section)
5
Bits
kΩ
kΩ
COMPn
mn
Compensation Resistor R
Compensation Resistor R
62
0.5
TH(MAX)
TH(MIN)
g
Resolution
COMPn = 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7
3
Bits
mmho
mmho
mmho
Error Amplifier g
Error Amplifier g
LSB Step Size
5.76
1
m(MAX)
m(MIN)
0.68
Analog OV/UV (Oꢄerꢄoltage/Underꢄoltage) Output Voltage Superꢄisor Coꢂparators (VOUꢅ_OV/UV_FAULꢅ_LIMIꢅ and VOUꢅ_OV/UV_WARN_LIMIꢅ Monitors)
N
Resolution, Output Voltage
Supervisors
(Notes 14, 15)
9
Bits
OV/UV_COMP
V
V
Output OV Comparator Threshold
Detection Range
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
1
0.5
3.6
2.7
V
V
OV-RNG
Output OV and UV Comparator
Threshold Programming LSB Step
Size
(Note 15)
OUSTP
High Range Scale, MFR_PWM_MODEn[1] = 0b
11.2
5.6
mV
mV
Low Range Scale, MFR_PWM_MODEn[1] = 1b
+
–
l
l
l
V
Output OV Comparator Threshold
Accuracy Channel 0 - 3
(See Note 14)
1V ≤ V
– V
≤ 2.7V, MFR_PWM_MODE[1] = 1b
1.5
2.5
1.5
%
%
%
OV-ACC-n
VOSNSn
VOSNSn
+
–
0.5V ≤ V
2.0V ≤ V
– V
≤ 1V, MFR_PWM_MODE[1] = 1b
VOSNSn
VOSNSn
– V
≤ 3.6V, MFR_PWM_MODE[0] = 0b
VSNS
SNG
V
V
Output UV Comparator Threshold
Detection Range
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
1
0.5
3.6
2.7
V
V
UV-RNGn
UV-ACCn
+
–
l
l
l
Output UV Comparator Threshold
Accuracy (Note 14)
1V ≤V
–V
≤ 2.7V, MFR_PWM_MODE[1] =1b
1.5
2.5
1.5
%
%
%
VOSNSn
VOSNSn
+
–
0.5V ≤ V
–V
≤ 1V, MFR_PWM_MODE[1]=1b
VOSNSn
VOSNSn
2.0V ≤ V
– V
≤ 3.6V, MFR_PWM_MODE[0] = 0b
VSNS
SNG
Rev. 0
6
For more information www.analog.com
LTM4681
ELECTRICAL CHARACTERISTICS ꢅhe ldenotes the specifications which apply oꢄer the specified internal
operating teꢂperature range (Note ꢈ). Specified as each indiꢄidual output channel (Note 4). ꢅA = ꢈ5ꢇC, VIN = 1ꢈV, RUNn = 3.3V,
RUNP = 0, FRꢃQUꢃNCY_SWIꢅCH = 350ꢆHz and VOUꢅn coꢂꢂanded to 1.000V unless otherwise noted. Configured with factory-default
ꢃꢃPROM settings and per ꢅest Circuit 1, unless otherwise noted.
SYMBOL
PARAMꢃꢅꢃR
CONDIꢅIONS
MIN
ꢅYP
MAX
UNIꢅS
t
Output OV Comparator Response
Times
Overdrive to 10% Above Programmed Threshold
100
µs
PROP-OV
t
Output UV Comparator Response
Times
Under Drive to 10% Below Programmed Threshold
100
18
µs
PROP-UV
Analog OV/UV SV
Input Voltage Superꢄisor Coꢂparators (ꢅhreshold Detectors for VIN_ON and VIN_OFF)
IN_nn
N
SV
OV/UV Comparator
IN_nn
(Notes 14, 15)
9
Bits
V
SVIN-OV/UV-COMP
Threshold-Programming Resolution
l
SV
SV
SV
SV
OV/UV Comparator
IN_nn
Limited to Abs Max = 18V for LTM4681 Module
4.5
IN-OU-RANGE
IN-OU-STP
Threshold-Programming Range
SV OV/UV Comparator Threshold- (Note 15)
76
mV
IN_nn
Programming LSB Step Size
l
l
SV OV/UV Comparator
9V < SV ≤ 16V
3
270
%
mV
IN-OU-ACC
IN_nn
IN
Threshold Accuracy
4.5V ≤ SV ≤ 9V
IN
t
SV
OV/UV Comparator
IN_nn
Test Circuit 1, and:
PROP-SVIN-HIGH-VIN
l
l
Response Time, High V Operating
VIN_ON = 9V; SV Driven from 8.775V to 9.225V
100
100
µs
µs
IN
IN
Configuration
VIN_OFF = 9V; SV Driven from 9.225V to 8.775V
IN
t
SV
OV/UV Comparator
IN_nn
Test Circuit 2, and:
PROP-SVIN-LOW-VIN
l
l
Response Time, Low V Operating
VIN_ON = 4.5V; SV Driven from 4.225V to 4.725V
100
100
µs
µs
IN
IN
Configuration
VIN_OFF = 4.5V; SV Driven from 4.725V to 4.225V
IN
Channeln Output Voltage Readbacꢆ (RꢃAD_VOUꢅn)
N
Output Voltage Readback Resolution (Note 15)
and LSB Step Size
16
244
Bits
µV
VO-RB
V
Output Voltage Full-Scale Digitizable
Range
V
= 0V (Note 15), Limited to 3.6V Max Operating
RUNn
8
V
O-F/S
+
–
l
l
V
Output Voltage Readback Accuracy
Channel n: 1V ≤ V
– V
≤ 3.3V
Within 0.5%ofReading
Within 5mVofReading
O-RB-ACC
CONVERT-VO-RB
VOSNS
VOSNS
+
–
Channel n: 0.5V ≤ V
– V
< 1V
VOSNS
VOSNS
t
Output Voltage Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x01 through 0x0C (Notes 9, 15)
MFR_ADC_CONTROL Section
90
8
ms
ms
ms
Input Voltage (SV
) Readbacꢆ (RꢃAD_VIN)
IN_nn
N
Input Voltage Readback Resolution
and LSB Step Size
(Notes 10, 15) Limited to Abs Max = 18V for
LTM4681 Module
10
15.625
Bits
mV
SVIN-RB
SV
Input Voltage Full-Scale Digitizable
Range
(Notes 11, 15)
43
V
IN-F/S
l
SV
Input Voltage Readback Accuracy
READ_VIN, 4.5V ≤ SV ≤ 16V
Within 2% of Reading
IN-RB-ACC
IN
t
Input Voltage Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x01 (Notes 9, 15)
90
8
ms
ms
CONVERT-SVIN-RB
Channeln OutputCurrent(RꢃAD_IOUꢅn),DutyCycle(RꢃAD_DUꢅY_CYCLꢃ ),andCoꢂputedInputCurrent(MFR_RꢃAD_IINn)Readbacꢆ
n
N
Output Current Readback Resolution (Notes 10, 15)
and LSB Step Size
10
34.1
Bits
mA
IO-RB
Rev. 0
7
For more information www.analog.com
LTM4681
ELECTRICAL CHARACTERISTICS ꢅhe ldenotes the specifications which apply oꢄer the specified internal
operating teꢂperature range (Note ꢈ). Specified as each indiꢄidual output channel (Note 4). ꢅA = ꢈ5ꢇC, VIN = 1ꢈV, RUNn = 3.3V,
RUNP = 0, FRꢃQUꢃNCY_SWIꢅCH = 350ꢆHz and VOUꢅn coꢂꢂanded to 1.000V unless otherwise noted. Configured with factory-default
ꢃꢃPROM settings and per ꢅest Circuit 1, unless otherwise noted.
SYMBOL
PARAMꢃꢅꢃR
Output Current Full-Scale Digitizable (Note 15)
Range Utilizing MFR_PWM_MODE[7] = 1, Using IOUT_OC_
FAULT_LIMIT = 61A, Page 97
CONDIꢅIONS
MIN
ꢅYP
MAX
UNIꢅS
I
I
54
A
O-F/S
Output Current, Readback Accuracy READ_IOUTn, Channels 0–3, 0 ≤ I
≤ 30A,
OUTn
O-RB-ACC
Forced-Continuous Mode, MFR_PWM_MODEn[0] = 1b
0°C to 125°C
–40°C to 125°C
Within 1.25A of Reading
Within 1.5A of Reading
l
See Histograms in Typical Performance Characteristics
(Note 12)
I
t
Full Load Output Current Readback
(Note 12). See Histograms in Typical Performance
Characteristics
31.25
A
O-RB(31.25A)
Output Current Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
90
8
ms
ms
CONVERT-IO-RB
MFR_ADC_CONTROL =0x06 (CH0,2 I ) or 0x01 (CH1,3 I
)
OUT
OUT
(Notes 9, 15) See MFR_ADC_CONTROL SECTION
Input Current Readbacꢆ
Resolution
N
(Note 10)
10
Bits
+
+
+
–
V
LSB Step Size Full-Scale Range = 16mV Gain = 8, 0V ≤ |V
LSB Step Size Full-Scale Range = 32mV Gain = 4, 0V ≤ |V
LSB Step Size Full-Scale Range = 64mV Gain = 2, 0V ≤ |V
– V | ≤ 5mV
15.26
30.52
61
µV
µV
µV
IINSTP
IIN
IIN
IIN
IIN
–
–
– V | ≤ 20mV
IIN
– V | ≤ 50mV
IIN
+
–
l
l
l
I
Total Unadjusted Error
Gain = 8, 2.5mV ≤ |V
– V | (Note 7)
2
1.3
1.2
%
%
%
IN_TUE
IIN
+
+
IIN
–
Gain = 4, 4mV ≤ |V
Gain = 2, 6mV ≤ |V
– V | (Note 7)
– V | (Note 7)
IIN
IIN
IIN
–
IIN
V
Zero-Code Offset Voltage
Update Rate
(Note 15)
50
µV
OS
t
(Notes 9,15) See MFR_ADC_CONTROL SECTION for
Faster Update Rates
90
ms
CONVERT
Supply Current Readbacꢆ
Resolution
N
(Note 10)
10
Bits
µV
V
LSB Step Size Full-Scale Range =
256mV
Onboard 1Ω Resistor
244
ICHIPSTP
I
t
I
Readback
SV Current
IN_nn
50
90
mA
ms
CHIP_RB
CHIP
Update Rate
(Notes 9,15) See MFR_ADC_CONTROL SECTION for
Faster Update Rates
CONVERT
ꢅeꢂperature Readbacꢆ (ꢅ0, ꢅ1)
T
Temperature Readback Resolution
Channel n, and Controller (Note 15)
0.25
°C
RES-RB
T0_TUE
External Temperature Total
Unadjusted Readback Error
Supporting Only ∆V Sensing
BE
2.5
1
°C
°C
T1_TUE
Internal TSNS TUE
Update Rate
V
= 0.0, f
= 0kHz (Note 7)
SYNC
RUNn
t
(Note 9)
MFR_ADC_CONTROL = 0x04 or 0x0C (Notes 9, 15)
90
8
ms
ms
CONVERT
INꢅV
Regulator/V
BIAS
CC_nn
INTVCC_nn
LDO_INT
l
V
V
V
Internal V Voltage No Load
6V ≤ SV
≤ 16V
5.25
4.5
5.5
0.5
5.75
2
V
%
V
CC
IN_nn
INTV Load Regulation
I
CC
= 0mA to 20mA, 6V ≤ SV
≤ 16V
IN_nn
CC
Input Range for V
16
IN_VBIAS
IN_VBIAS
RUNP
V
Enable
RUNP Rising
7 ≤ V
0.8
5.5
0.85
5.75
V
BIAS
V
BIAS
5.5V Internal Regulator
≤ 16
IN_VBIAS
5.25
V
Rev. 0
8
For more information www.analog.com
LTM4681
ELECTRICAL CHARACTERISTICS ꢅhe ldenotes the specifications which apply oꢄer the specified internal
operating teꢂperature range (Note ꢈ). Specified as each indiꢄidual output channel (Note 4). ꢅA = ꢈ5ꢇC, VIN = 1ꢈV, RUNn = 3.3V,
RUNP = 0, FRꢃQUꢃNCY_SWIꢅCH = 350ꢆHz and VOUꢅn coꢂꢂanded to 1.000V unless otherwise noted. Configured with factory-default
ꢃꢃPROM settings and per ꢅest Circuit 1, unless otherwise noted.
SYMBOL
PARAMꢃꢅꢃR
Threshold to Enable V
CONDIꢅIONS
MIN
ꢅYP
MAX
UNIꢅS
SV
V
SV
IN_nn
Rising
7
7.5
V
IN_THR
SVIN_nn
BIAS
Switchover
SV
IN_THF
V
Threshold to Disable V
SV
Falling
6.5
V
SVIN_nn
BIAS
IN_nn
Switchover
V
Regulator
DD33_nn
VDD33nn
LIM
V
Internal V
Voltage
4.5V < V
3.2
3.3
100
3.5
3.1
3.4
V
mA
V
DD33
INTVCC_nn
I
V
V
V
Current Limit
V
= GND, V
= INTV
= INTV
= 4.5V
= 4.5V
DD33
DD33
DD33
DD33_nn
IN_nn
IN_nn
CC_nn
V
V
V
V
Overvoltage Threshold
Undervoltage Threshold
VDD33_OV
V
VDD33_UV
Regulator
DDꢈ5_nn
VDD25nn
LIM
Internal V
Voltage
2.5
80
V
DD25
I
V
DD25
Current Limit
V
= GND, V
mA
DD25_nn
CC_nn
Oscillator and Phase-Locꢆed Loop (PLL)
l
l
f
f
PLL SYNC Range
Synchronized with Falling Edge of SYNC
250
1000
7.5
kHz
%
RANGE
OSC
Oscillator Frequency Accuracy
SYNC Input Threshold
Frequency Switch = 250kHz to 1000kHz (Note 15)
V
V
SYNC
V
SYNC
Falling
Rising
1
1.5
V
V
TH(SYNC_nn)
V
SYNC Low Output Voltage
I
= 3mA
0.2
0.4
5
V
OL(SYNC_nn)
LOAD
I
SYNC Leakage Current in Slave Mode 0V ≤ V ≤ 3.6V
µA
LEAK(SYNC_nn)
PIN
θSYNC-θ0,-θ2
SYNC to Ch0, Ch2 Phase
Relationship Based on the Falling
Edge of Sync and Rising Edge of
SW0, SW2
MFR_PWM_CONFIG[2:0] = 0,2,3
0
Deg
Deg
Deg
Deg
MFR_PWM_CONFIG[2:0] = 5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0]= 4,6
60
90
120
θSYNC-θ1,-θ3
SYNC to Ch1, Ch3 Phase
Relationship Based on the Falling
Edge of Sync and Rising Edge of
SW1, SW3
MFR_PWM_CONFIG[2:0] = 3
MFR_PWM_CONFIG[2:0] = 0
MFR_PWM_CONFIG[2:0] = 2,4,5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0] = 6
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
ꢃꢃPROM Characteristics
l
l
Endurance
Retention
(Note 13)
0°C ≤ T ≤ 85°C During EEPROM Write Operations
10,000
10
Cycles
Years
ms
J
(Note 13)
T < 125°C
J
Mass_Write
Mass Write Operation Time
STORE_USER_ALL, 0°C < T < 85°C
440
4100
J
During EEPROM Write Operation
Leaꢆage Current SDA_nn, SCL_nn, ALERT_nn, RUNn
Input Leakage Current
Leaꢆage Current FAULTn, PGOODn
Input Leakage Current
Digital Inputs SCL_nn, SDA_nn, RUNn
l
l
I
OV ≤ V ≤ 5.5V
5
2
µA
µA
OL
PIN
I
OV ≤ V ≤ 3.6V
GL
PIN
l
l
V
V
V
C
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
1.35
V
V
IH
0.8
IL
SCL, SDA
0.08
V
HYST
PIN
Input Capacitance
10
pF
Rev. 0
9
For more information www.analog.com
LTM4681
ELECTRICAL CHARACTERISTICS ꢅhe ldenotes the specifications which apply oꢄer the specified internal
operating teꢂperature range (Note ꢈ). Specified as each indiꢄidual output channel (Note 4). ꢅA = ꢈ5ꢇC, VIN = 1ꢈV, RUNn = 3.3V,
RUNP = 0, FRꢃQUꢃNCY_SWIꢅCH = 350ꢆHz and VOUꢅn coꢂꢂanded to 1.000V unless otherwise noted. Configured with factory-default
ꢃꢃPROM settings and per ꢅest Circuit 1, unless otherwise noted.
SYMBOL
Digital Input WP_nn
Input Pull-Up Current
PARAMꢃꢅꢃR
CONDIꢅIONS
MIN
ꢅYP
MAX
UNIꢅS
I
WP
10
µA
PUWP
Open-Drain Outputs SCL_nn, SDA_nn, FAULT_nn, ALERT_nn, RUNn, SHARꢃ_CLK_nn, PGOODn
Output Low Voltage = 3mA
Digital Inputs SHARꢃ_CLK_nn, WP_nn
V
I
0.4
1.8
V
OL
SINK
l
l
V
V
Input High Threshold Voltage
Input Low Threshold Voltage
1.5
1
V
V
IH
IL
0.6
Digital Filtering of FAULTn
Input Digital Filtering FAULTn
Digital Filtering of PGOODn
Output Digital Filtering PGOODn
Digital Filtering of RUNn
Input Digital Filtering RUN
PMBus Interface ꢅiꢂing Characteristics
I
3
µs
µs
µs
FLTG
I
100
10
FLTG
I
FLTG
l
l
f
t
Serial Bus Operating Frequency
10
400
kHz
µs
SCL
BUF
Bus Free Time Between Stop and
Start
1.3
l
t
Hold Time After Repeated Start
Condition After This Period, the First
Clock is Generated
0.6
µs
HD(STA)
l
l
t
t
t
Repeated Start Condition Setup Time
Stop Condition Setup Time
0.6
0.6
10000
0.9
µs
µs
SU(STA)
SU(ST0)
HD(DAT)
Date Hold Time
Receiving Data
Transmitting Data
l
l
0
0.3
µs
µs
t
t
Data Setup Time
Receiving Data
SU(DAT)
0.1
µs
Stuck PMBus Timer Non-Block Reads Measured from the Last PMBus Start Event
Stuck PMBus Timer Block Reads
32
255
ms
TIMEOUT_SMB
l
l
t
t
Serial Clock Low Period
Serial Clock High Period
1.3
0.6
10000
µs
µs
LOW
HIGH
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4681I is guaranteed to meet specifications over the full
–40°C to 125°C internal operating temperature range. T is calculated from
J
the ambient temperature T and the power dissipation PD according the
A
Note ꢈ: The LTM4681 is tested under pulsed-load conditions such that
formula:
T ≈ T . The LTM4681E is guaranteed to meet performance specifications
J
A
over the 0°C to 125°C internal operating temperature range. Specifications
T = T + (P • θ )
J A D JA
Rev. 0
10
For more information www.analog.com
LTM4681
ELECTRICAL CHARACTERISTICS
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 11: The absolute maximum rating for the SV
pin is 18V. Input
IN_nn
voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled
down from the SV pin.
IN_nn
Note 1ꢈ: These typical parameters are based on bench measurements and
are not production tested.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified
Note 13: EEPROM endurance and retention are guaranteed by wafer-level
testing for data retention. The minimum retention specification applies
for devices whose EEPROM has been cycled less than the minimum
endurance specification, and whose EEPROM data was written to at 0°C
Note 4: The two power inputs—V
and V
—and their respective
IN01
IN23
power outputs—V
and V
—are tested independently in
OUT0,1
OUT2,3
≤ T ≤ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over
production. A shorthand notation is used in this document that allows
these parameters to be referred to by “V ” and “V ”, where n is
J
the entire operating temperature range and does not influence EEPROM
characteristics.
Note 14: Channel 0 OV/UV comparator threshold accuracy for
MFR_PWM_MODEn[1] = 1b tested in ATE at V
0.5V and 3.6V. 1V condition tested at IC-Level, only. Channel 1 OV/UV
INnn
OUTn
permitted to take on a value of 0–3. This italicized, subscripted “n”
notation and convention is extended to encompass all such pin names, as
well as register names with channel-specific, i.e., paged data. For example,
VOUT_COMMANDn refers to the VOUT_COMMAND command code data
+
–
– V
=
VOSNSn
VOSNSn
located in Pages 0 and 1, which in turn relate to channel 0,2 (V
)
comparator threshold accuracy for MFR_PWM_MODEn[1] = 1b tested
OUT0,2
and channel 1,3 (V ). Registers containing non-page-specific data,
OUT1,3
in ATE with V
-V
= 0.5V and 3.6V. 1.5V condition tested at
VOSNSn SGND
i.e., whose data is “global” to the module or applies to all of the module’s
channels lack the italicized, subscripted “n”, e.g., FREQUENCY_SWITCH.
IC-level, only. MFR_PWM_MODEn[1] = 1b is the Low Range.
Note 15: Tested at IC-level ATE.
Note 5: V
(DC) and line and load regulation tests are performed in
OUTn
Note 16: The LTM4681’s EEPROM temperature range for valid write
commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention,
execution of the “STORE_USER_ALL” command—i.e., uploading RAM
contents to NVM—outside this temperature range is not recommended.
However, as long as the LTM4681’s EEPROM temperature is less than
130°C, the LTM4681 will obey the STORE_USER_ALL command. Only
when EEPROM temperature exceeds 130°C, the LTM4681 will not act
on any STORE_USER_ALL transactions: instead, the LTM4681 NACKs
the serial command and asserts its relevant CML (communications,
memory, logic) fault bits. EEPROM temperature can be queried prior
to commanding STORE_USER_ALL; see the Applications Information
section.
production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b)
and low V range selected MFR_PWM_MODEn[1] = 1b. The digital
OUTn
servo control loop is exercised in production (setting MFR_PWM_
MODEn[6] = 1b), but convergence of the output voltage to its final settling
value is not necessarily observed in final test—due to potentially long
time constants involved—and is instead guaranteed by the output voltage
readback accuracy specification. Evaluation in application demonstrates
capability; see the Typical Performance Characteristics section.
Note 6: See output current derating curves for different V , V , and T ,
IN OUT
A
located in the Applications Information section.
Note 7: Part tested with PWM disabled. Evalution in appliction
demonstrates capability. TUE(%) = ADC Gain Error (%) + 100 (zero code
offset + ADC Linearity Error)/Actual Value.
Note 8: Minimum on-time is tested at wafer sort.
Note 17: The LTM4681 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 9: The data conversion is done by default in round robin fashion. All
inputs signals are continuously converted for a typical latency of 90ms.
Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4681 can do fast
data conversion with only 8ms to 10ms. See section PMBus Command
for details.
Note 10: The following telemetry parameters are formatted in PMBus-
defined “Linear Data Format”, in which each register contains a word
comprised of 5 most significant bits—representing a signed exponent, to
be raised to the power of 2—and 11 least significant bits—representing a
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
signed mantissa: input voltage (on SV
), accessed via the READ_VIN
), accessed via the READ_IOUTn
IN_nn
command code; output currents (I
OUTn
command codes; module input current (I
+ I
+ I
SVIN_nn
),
VIN_nn
VIN_nn
accessed via the READ_IIN command code; channel input currents (I
VIN_nn
+ 1/2 • I
), accessed via the MFR_READ_IINn command codes;and
SVIN_nn
duty cycles of channel 0 and channel 1 switching power stages, accessed
0
via the READ_DUTY_CYCLE command codes. This data format limits the
n
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
resolution of telemetry readback data to 10 bits even though the internal
ADC is 16 bits and the LTM4681’s internal calculations use 32-bit words.
ꢀꢁꢂꢃ
ꢀꢁꢂ0 ꢃ0ꢄ
Figure 1. Prograꢂꢂable RCOMPn
Rev. 0
11
For more information www.analog.com
LTM4681
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Single Channel Efficiency, 5VIN,
VIN = SVIN = INTVCC = 5V,
RUNP = 0V, CCM Mode
Single Channel Efficiency, 8VIN,
VIN = SVIN = VIN_VBIAS = 8V,
RUNP = 8V,CCM Mode
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
0.ꢀꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
0.ꢀꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
ꢀ.0ꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
ꢀ.0ꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
ꢀ.ꢁꢂ ꢆ ꢇꢈ0ꢉꢊꢋ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇꢈ0ꢉꢊꢋ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇꢈꢁꢉꢊꢋ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇꢈꢁꢉꢊꢋ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢁꢇꢁꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢁꢇꢁꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢀꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢀ.ꢀꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
ꢂꢃꢄ
0
ꢀ
ꢀ0 ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
0
ꢀ
ꢀ0 ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄ0ꢃ
ꢀꢁꢂꢃ ꢄ0ꢅ
Quad Channel Single
Output Efficiency
Single Channel Efficiency, 12VIN
VIN = SVIN = VIN_VBIAS = RUNP =
12V, CCM Mode
VIN = SVIN = 12V, RUNP = 0V,
VBIAS = 5.5V External, CCM Mode
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
0.ꢀꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
ꢀ.0ꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
0.ꢀꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
ꢀ.0ꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
ꢀ.ꢁꢂ ꢆ ꢇꢈ0ꢉꢊꢋ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇꢈ0ꢉꢊꢋ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇꢈꢁꢉꢊꢋ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇꢈꢁꢉꢊꢋ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢇ00ꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢁꢇꢁꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢁꢂ ꢆ ꢁꢇꢁꢈꢉꢊ
ꢃꢄꢅ
ꢀ.ꢀꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
ꢀ.ꢀꢁ ꢅ ꢆꢇ0ꢈꢉꢊ
ꢂꢃꢄ
0
ꢀ
ꢀ0 ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢀ
Rev. 0
12
For more information www.analog.com
LTM4681
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Single Channel Load Transient
Response (10A) to (20A)
Load Step, 10A/µs VIN = 12V,
VOUT = 1.2V, fSW = 350kHz
Single Channel Load Transient
Response (10A) to (20A)
Load Step, 10A/µs VIN = 12V,
VOUT = 1.5V, fSW = 350kHz
Single Channel Load Transient
Response (10A) to (20A) Load Step,
10A/µs 12VIN to 0.9VOUT
50mV/DIV
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢆꢇꢈꢄ ꢉꢊꢋꢌ
ꢍꢈꢃꢄꢅꢂ
LOAD STEP
10A/DIV
ꢆꢇꢈꢄ ꢉꢊꢋꢌ
ꢀ0ꢈꢃꢄꢅꢂ
4681 G04
ꢓꢢꢔꢀ ꢑ0ꢢ
ꢔꢢꢕꢀ ꢒ0ꢞ
200μS/DIV
ꢍ00ꢎꢏꢃꢄꢅꢂ
ꢎ00ꢏꢐꢃꢄꢅꢂ
FIGURE 48 CIRCUIT, 12V TO 0.9V, FREQ = 350kHz
ꢐꢅꢑꢒRꢋ ꢓꢔ ꢕꢅRꢕꢒꢅꢊꢖ ꢀꢍꢂ ꢊꢇ ꢀ.ꢍꢂꢖ ꢐRꢋꢗ ꢘ ꢙꢚ0ꢛꢜꢝ
ꢑꢅꢒꢓRꢋ ꢔꢕ ꢖꢅRꢖꢓꢅꢊꢗ ꢀꢎꢂ ꢊꢇ ꢀ.ꢍꢂꢗ ꢑRꢋꢘ ꢙ ꢚꢍ0ꢛꢜꢝ
C
R
= 470µF ×3 POSCAP, 100µF ×5 CERAMIC
ꢕ
R
ꢘ ꢓꢞ0ꢎꢐ ꢟꢍ ꢌꢇꢉꢕꢈꢌꢖ ꢀ00ꢎꢐ ꢟꢍ ꢕꢋRꢈꢠꢅꢕ
ꢖ
R
ꢙ ꢔꢞ0ꢏꢑ ꢟꢎ ꢌꢇꢉꢖꢈꢌꢗ ꢀ00ꢏꢑ ꢟꢎ ꢖꢋRꢈꢠꢅꢖ
OUT
COMP
ꢇꢒꢊ
ꢕꢇꢠꢌ
ꢇꢓꢊ
ꢖꢇꢠꢌ
= 11k, EA-GM = 4.36ms
ꢘ ꢞꢛꢖ ꢋꢈꢡꢑꢠ ꢘ ꢓ.ꢙꢢꢁꢏ
ꢙ ꢞꢛꢗ ꢋꢈꢡꢒꢠ ꢙ ꢚ.ꢢꢣꢁꢐ
COMPna = 2.2nF, COMPnb = 150pF
ꢕꢇꢠꢌꢣꢤ ꢘ ꢍ.ꢍꢣꢐꢖ ꢕꢇꢠꢌꢣꢥ ꢘ ꢀꢚ0ꢦꢐ
ꢖꢇꢠꢌꢤꢥ ꢙ ꢎ.ꢎꢤꢑꢗ ꢖꢇꢠꢌꢤꢦ ꢙ ꢀꢍ0ꢧꢑ
ILIM RANGE HIGH, V
RANGE LOW
OUT
ꢅꢆꢅꢠ Rꢈꢧꢑꢋ ꢜꢅꢑꢜꢖ ꢂ
Rꢈꢧꢑꢋ ꢆꢇꢨ
ꢅꢆꢅꢠ Rꢈꢨꢒꢋ ꢜꢅꢒꢜꢗ ꢂ
Rꢈꢨꢒꢋ ꢆꢇꢩ
ꢇꢒꢊ
ꢇꢓꢊ
Single Channel Load Transient
Response (10A) to (20A)
Load Step, 10A/µs VIN = 12V,
VOUT = 2.5V, fSW = 500kHz
Single Channel Load Transient
Response (10A) to 1 (20A)
Load Step, 10A/µs VIN = 12V,
VOUT = 3.3V, fSW = 500kHz
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢀ00ꢁꢂꢃꢄꢅꢂ
ꢆꢇꢈꢄ ꢉꢊꢋꢌ
ꢀ0ꢈꢃꢄꢅꢂ
ꢆꢇꢈꢄ ꢉꢊꢋꢌ
ꢍꢈꢃꢄꢅꢂ
ꢓꢢꢔꢗ ꢑ0ꢨ
ꢓꢠꢔꢀ ꢑ0ꢔ
ꢀ00ꢎꢏꢃꢄꢅꢂ
ꢍ00ꢎꢏꢃꢄꢅꢂ
ꢐꢅꢑꢒRꢋ ꢓꢔ ꢕꢅRꢕꢒꢅꢊꢖ ꢗꢀꢂ ꢊꢇ ꢘ.ꢘꢂꢖ ꢐRꢋꢙ ꢚ ꢍ00ꢛꢜꢝ
ꢐꢅꢑꢒRꢋ ꢓꢔ ꢕꢅRꢕꢒꢅꢊꢖ ꢀꢍꢂ ꢊꢇ ꢍ.ꢗꢂꢖ ꢐRꢋꢘ ꢙ ꢗ00ꢚꢛꢜ
ꢕ
R
ꢚ ꢓꢞ0ꢎꢐ ꢟꢗ ꢌꢇꢉꢕꢈꢌꢖ ꢗ00ꢎꢐ ꢟꢗ ꢕꢋRꢈꢠꢅꢕ
ꢚ ꢗꢗꢛꢖ ꢋꢈꢡꢑꢠ ꢚ ꢗ.ꢢꢔꢁꢏꢖ
ꢕ
R
ꢙ ꢓꢝ0ꢎꢐ ꢞꢀ ꢌꢇꢉꢕꢈꢌꢖ ꢀ00ꢎꢐ ꢞꢀ ꢕꢋRꢈꢟꢅꢕ
ꢙ ꢠꢚꢖ ꢋꢈꢡꢑꢟ ꢙ ꢍ.ꢢꢗꢁꢏꢖ
ꢇꢒꢊ
ꢕꢇꢠꢌ
ꢇꢒꢊ
ꢕꢇꢟꢌ
ꢕꢇꢠꢌꢣꢤ ꢚ ꢀ.ꢀꢣꢐꢖ ꢕꢇꢠꢌꢣꢥ ꢚ ꢗ00ꢦꢐ
ꢅꢆꢅꢠ Rꢈꢧꢑꢋ ꢜꢅꢑꢜꢖ ꢂ Rꢈꢧꢑꢋ ꢜꢅꢑꢜ
ꢕꢇꢟꢌꢣꢤ ꢙ ꢍ.ꢍꢣꢐꢖ ꢕꢇꢟꢌꢣꢥ ꢙ ꢍꢍ0ꢦꢐ
ꢅꢆꢅꢟ Rꢈꢧꢑꢋ ꢛꢅꢑꢛꢖ ꢂ Rꢈꢧꢑꢋ ꢆꢇꢨ
ꢇꢒꢊ
ꢇꢒꢊ
Rev. 0
13
For more information www.analog.com
LTM4681
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Quad Output Concurrent Rail,
Quad Output Concurrent Rail,
ꢏ ꢓ.ꢓꢆ Start-Up/Shut Down
ꢐꢆꢃꢄꢅꢆ
ꢏ ꢑ.ꢀꢆ
ꢅ ꢌ.ꢌꢀ Start-Up/Shut Down, Pre-Bias
ꢄꢀꢇꢈꢉꢀ
ꢅ ꢊ.ꢋꢀ
ꢄꢀꢇꢈꢉꢀ
ꢅ ꢄ.ꢆꢀ
ꢆ
ꢆ
ꢆ
ꢀ
ꢀ
ꢀ
ꢕꢉꢎꢓ
ꢁꢂꢃꢌ
ꢕꢉꢎꢑ
ꢁꢂꢃꢊ
ꢐꢆꢃꢄꢅꢆ
ꢏ ꢐ.ꢌꢆ
ꢕꢉꢎꢐ
ꢁꢂꢃꢄ
ꢐꢆꢃꢄꢅꢆ
ꢏ ꢓ0ꢔ
ꢄꢀꢇꢈꢉꢀ
ꢅ ꢌ0ꢍ
ꢆ
ꢀ
ꢕꢉꢎ0
ꢁꢂꢃ0
ꢐꢆꢃꢄꢅꢆ
ꢄꢀꢇꢈꢉꢀ
ꢅ
ꢉ
ꢕꢉꢎ0
ꢁꢂꢃ0
ꢑ0ꢔꢃꢄꢅꢆ
ꢊ0ꢍꢇꢈꢉꢀ
Rꢉꢒ0ꢏ Rꢉꢒꢐꢏ
Rꢉꢒꢑꢏ Rꢉꢒꢓ
ꢀꢆꢃꢄꢅꢆ
Rꢂꢎ0ꢅ Rꢂꢎꢄꢅ
Rꢂꢎꢊꢅ Rꢂꢎꢌ
ꢋꢀꢇꢈꢉꢀ
ꢋꢚꢌꢐ ꢈꢐ0
ꢑꢒꢆꢄ ꢓꢄꢄ
ꢀꢁꢂꢃꢄꢅꢆ
ꢋꢏꢐꢇꢈꢉꢀ
ꢇꢅꢈꢉRꢊ ꢋꢌ ꢍꢅRꢍꢉꢅꢎꢏ ꢐꢑꢆ ꢏ ꢓ0ꢔ ꢕꢒ ꢆ
ꢔꢉꢓꢂRꢕ ꢑꢆ ꢖꢉRꢖꢂꢉꢃꢅ ꢄꢊꢀ ꢅ ꢌ0ꢍ ꢁꢎ ꢀ
ꢅꢒ
ꢕꢉꢎ0
ꢉꢎ
ꢁꢂꢃ0
ꢒꢕ ꢖꢕꢔꢄ ꢕꢒ ꢕꢎꢗꢊR ꢕꢉꢎꢘꢉꢎꢙ
ꢎꢁ ꢗꢁꢍꢈ ꢁꢎ ꢁꢃꢘꢕR ꢁꢂꢃꢙꢂꢃꢚ ꢍꢎꢈ
0.ꢋꢀ ꢙRꢕꢛꢉꢍꢚ ꢁꢎ ꢀ
ꢁꢂꢃꢄ
Single Phase Single Output
Short-Circuit Protection, No Load
Single Phase Single Output
Short-Circuit Protection, 30A Load
V
, 1V
OUT0
0.5V/DIV
ꢀ
ꢄ ꢅꢀ
ꢁꢂꢃ0
0.ꢆꢀꢇꢈꢉꢀ
I
IN
2A/DIV
ꢉ
ꢉꢊ
ꢋꢌꢇꢈꢉꢀ
4681 G12
ꢒꢠꢓꢅ ꢐꢅꢕ
50μs/DIV
ꢆ0ꢍꢎꢇꢈꢉꢀ
FIGURE 48 CIRCUIT, 12V , NO LOAD ON V
IN
ꢏꢉꢐꢂRꢑ ꢒꢓ ꢔꢉRꢔꢂꢉꢃꢄ ꢅꢋꢀ ꢄ ꢕ0ꢌ ꢖꢁꢌꢈ ꢁꢊ ꢀ
OUT0
ꢉꢊ
ꢁꢂꢃ0
PRIOR TO APPLICATION OF SHORT-CIRCUIT
USE HIGH RANGE OF I LIMIT SYSTEM
SHORT-CIRCUIT USING LOW IMPEDANCE
COPPER ACROSS OUTPUT (HARD SHORT)
ꢗRꢉꢁR ꢃꢁ ꢌꢗꢗꢖꢉꢔꢌꢃꢉꢁꢊ ꢁꢏ ꢘꢙꢁRꢃꢚꢔꢉRꢔꢂꢉꢃ
ꢂꢘꢑ ꢙꢉꢐꢙ Rꢌꢊꢐꢑ ꢁꢏ ꢉ ꢖꢉꢛꢉꢃ ꢘꢜꢘꢃꢑꢛ
ꢘꢙꢁRꢃꢚꢔꢉRꢔꢂꢉꢃ ꢂꢘꢉꢊꢐ ꢖꢁꢝ ꢉꢛꢗꢑꢈꢌꢊꢔꢑ
ꢔꢁꢗꢗꢑR ꢌꢔRꢁꢘꢘ ꢁꢂꢃꢗꢂꢃ ꢞꢙꢌRꢈ ꢘꢙꢁRꢃꢟ
Rev. 0
14
For more information www.analog.com
LTM4681
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Load Current
Comparison, RSENSE = 2mΩ,
12V to 1.0VOUT, 250kHz
Supply Current vs Load Current
Supply Current vs Load Current
Comparison, RSENSE = 2mΩ,
12V to 3.3VOUT, 650kHz
Comparison, RSENSE = 2mΩ,
12V to 1.8VOUT, 500kHz
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ
0
ꢀ
ꢀ
R
R
ꢀ
R
R
R
R
0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
RR
ꢀ0
ꢀ0
ꢀ0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ꢀꢁꢂꢃ ꢄꢃꢁ
RR
RR
READ_IOUT of 12 LTM4681 Channels
12VIN, 1VOUT, TJ = –40°C, IOUTn = 30A,
System Having Reached Thermally
Steady-State Condition, No Airflow
READ_IOUT of 12 LTM4681 Channels
12VIN, 1VOUT, TJ = 25°C, IOUTn = 30A,
System Having Reached Thermally
Steady-State Condition, No Airflow
READ_IOUT of 12 LTM4681 Channels
12VIN, 1VOUT, TJ = 125°C, IOUTn =30A,
System Having Reached Thermally
Steady-State Condition, No Airflow
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.0
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.0
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.0
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.0
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢀ
ꢀꢁ.0
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.0
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢂ
ꢀꢁ.ꢀ
ꢀꢁ.0
ꢀꢁ.ꢁ
0
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ0 ꢀꢀ ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0 ꢀꢀ ꢀꢁ
0 ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ0 ꢀꢀ ꢀꢁ
ꢀꢁꢂꢃꢃꢄꢅ ꢃꢆꢇꢈꢄR
ꢀꢁꢂꢃꢃꢄꢅ ꢃꢆꢇꢈꢄR
ꢀꢁꢂꢃꢃꢄꢅ ꢃꢆꢇꢈꢄR
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢂ
ꢀꢁꢂꢃ ꢄꢃꢅ
Rev. 0
15
For more information www.analog.com
LTM4681
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
memory) contents (factory default: 1.000V)—or, option-
ally, may be set by configuration resistors; see VOUT1_
CFG, VTRIM1_CFG and the Applications Information
section.
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
GND (A1-A4, A7, A12, B1-B4, B7, B12, C3-C4, C7,
C12, D3-D4, D7, D12, E3-E4, E7, E12, F1-F4, F7,
F12, G3-G4, G7, G12, H3-H4, H7, H12, J3-J4, J7,
J12, K1-K4, K7-K12, L1-L15, M1-M15, N1-N4, N7-N8,
N12, P3-P4, P7, P12, R3-R4, R7, R12, T3-T4, T7, T12,
U1-U4, U7, U12, V3-V4, V7, V12, W3-W4, W7, W12,
Y3-Y4, Y7, Y12, AA1-AA4, AA7, AA12, AB1-AB4, AB7,
AB12): Power Ground of the LTM4681. Power return for
–
VOSNS1 (F8): Channel 1 Negative Differential Voltage
+
Sense Input. See V
.
OSNS1
VOUT2 (N13-N15, P13-P15, R13-R15, T13-T15, U13-
U15): Channel 2 Output Voltage. Place recommended
output capacitors from this shape to GND. See recom-
mended layout.
+
V
V
V
and V
. Return input and output
OUT2,3
VOSNS2 (P8): Channel 2 Positive Differential Voltage
IN01 IN23 OUT0,1
capacitors to this point.
+
–
Sense Input. Together, VOSNS2 and VOSNS2 serve to
Kelvin-sense the VOUT2 output voltage at VOUT1’s point
of load (POL) and provide the differential feedback signal
VOUT0 (A13-A15, B13-B15, C13-C15, D13-D15, E13-
E15): Channel 0 Output Voltage. Place recommended
output capacitors from this shape to GND. See recom-
mended layout.
directly to channel 2’s feedback loop. Command V
’s
OUT2
target regulation voltage by serial bus. Its initial command
value at SVIN_23 power-up is dictated by NVM (non-volatile
memory) contents (factory default: 1.000V)—or, option-
ally, may be set by configuration resistors; see VOUT2_
CFG, VTRIM2_CFG and the Applications Information
section.
+
VOSNS0 (J11): Channel 0 Positive Differential Voltage
+
–
Sense Input. Together, VOSNS0 and VOSNS0 serve to
Kelvin-sense the VOUT0 output voltage at VOUT0’s point
of load (POL) and provide the differential feedback signal
directly to channel 0’s feedback loop. Command V
’s
OUT0
–
VOSNS2 (R8): Channel 2 Negative Differential Voltage
target regulation voltage by serial bus. Its initial command
value at SVIN_01 power-up is dictated by NVM (non-volatile
memory) contents (factory default: 1.000V)—or, option-
ally, may be set by configuration resistors; see VOUT0_
CFG, VTRIM0_CFG and the Applications Information
section.
+
Sense Input. See V
.
OSNS2
VOUT3 (V13-V15, W13-W15, Y13-Y15, AA13-AA15,
AB13-AB15): Channel 3 Output Voltage. Place recom-
mended output capacitors from this shape to GND See
recommended layout.
–
+
V
(H11): Channel 0 Negative Differential Voltage
VOSNS3 (R11): Channel 3 Positive Differential Voltage
OSNS0
+
+
–
Sense Input. See V
.
Sense Input. Together, VOSNS3 and VOSNS3 serve to
Kelvin-sense the VOUT3 output voltage at VOUT3’s point
of load (POL) and provide the differential feedback signal
OSNS0
VOUT1 (F13-F15, G13-G15, H13-H15, J13-J15, K13-
K15): Channel 1 Output Voltage. Place recommended
output capacitors from this shape to GND. See recom-
mended layout.
directly to channel 3’s feedback loop. Command V
’s
OUT3
target regulation voltage by serial bus. Its initial command
value at SVIN_23 power-up is dictated by NVM (non-volatile
memory) contents (factory default: 1.000V)—or, option-
ally, may be set by configuration resistors; see VOUT3_
CFG, VTRIM3_CFG and the Applications Information
section.
+
VOSNS1 (G8): Channel 1 Positive Differential Voltage
+
–
Sense Input. Together, VOSNS1 and VOSNS1 serve to
Kelvin-sense the VOUT1 output voltage at VOUT1’s point
of load (POL) and provide the differential feedback signal
directly to channel 1’s feedback loop. Command V
target regulation voltage by serial bus. Its initial command
value at SVIN_01 power-up is dictated by NVM (non-volatile
’s
OUT1
–
VOSNS3 (T11): Channel 3 Negative Differential Voltage
+
Sense Input. See V
.
OSNS3
Rev. 0
16
For more information www.analog.com
LTM4681
PIN FUNCTIONS
SGND01, SGND23 (F10-F11, U10-U11): SGND is the sig-
nal ground return path of the LTM4681 internal control-
lers. SGND is not internally connected to GND. Connect
SGND to GND local to the LTM4681. See recommended
layout.
SW3 (V1-V2, W1-W2, Y1-Y2): Switching Node of Channel
3 Step-Down Converter Stage. Used for test purposes or
EMI-snubbing. May be routed a short distance to a local
test point to monitor switching action of channel 3, if
desired, but do not route near any sensitive signals; oth-
erwise, leave open.
VIN01 (A5-A6, B5-B6, C5-C6, D5-D6, E5-E6, F5-F6,
G5-G6, H5-H6, J5-J6, K5-K6): Positive Power Input to
Channel 0 and 1 Switching Stages. Provide sufficient
decoupling capacitance in the form of multilayer ceramic
capacitors (MLCCs) and low ESR electrolytic (or equiv-
alent) to handle reflected input current ripple from the
step-down switching stage. MLCCs should be placed as
close to the LTM4681 as physically possible. See Layout
Recommendations in the Applications Information
section.
SV
(J8): Input Supply for LTM4681’s Internal Control
IN_01
IC for channel 0 and 1. In most applications, SV
con-
IN_01
nects to V
supply separate from V
a lower supply like 3.3V. The SV
. SV
can be operated from an auxiliary
IN01
IN_01
for powering the V
from
IN01
IN01
pin has an onboard
IN_01
1Ω and 1µF decoupling capacitor. The 1Ω resistor is used
to measure the actual control chip current. See MFR_
READ_ICHIP and MFR_ADC_CONTROL COMMAND sec-
tion. When operating from 4.5V to 5.75V with no auxiliary
bias supply, then the main input supply should connect to
SVIN_01 and INTVCC_01. See Test Circuit 2 for an example.
In this configuration, the ICHIP current will not be relevant
VIN23 (N5-N6, P5-P6, R5-R6, T5-T6, U5-U6, V5-V6,
W5-W6, Y5-Y6, AA5-AA6, AB5-AB6): Positive Power
Input to Channel 2 and 3 Switching Stages. Provide suf-
ficient decoupling capacitance in the form of MLCCs and
low ESR electrolytic (or equivalent) to handle reflected
input current ripple from the step-down switching stage.
MLCCs should be placed as close to the LTM4681 as
physically possible. See Layout Recommendations in the
Applications Information section.
since INTV
is connected to SV
.
CC_01
IN_01
SVIN_23 (P11): Input Supply for LTM4681’s Internal
Control IC for channel 2 and 3. In most applications,
SV
connects to V
. SV
can be operated from
IN_23
an IaNu_x2i3liary supply seIpNa_r2a3te from V
for powering the
IN23
V
from a lower supply like 3.3V. The SV
pin has
IN23
IN_23
an onboard 1Ω and 1µF decoupling capacitor. The 1Ω
resistor is used to measure the actual control chip cur-
rent. See MFR_READ_ICHIP and MFR_ADC_CONTROL
COMMAND section. When operating from 4.5V to 5.75V
with no auxiliary bias supply, then the main input sup-
SW0 (C1-C2, D1-D2, E1-E2): Switching Node of Channel
0 Step-Down Converter Stage. Used for test purposes
or EMI-snubbing. May be routed a short distance to a
local test point to monitor switching action of channel
0, if desired, but do not route near any sensitive signals;
otherwise, leave electrically isolated (open).
ply should connect to SV
and INTV
. See Test
IN_23
CC_23
Circuit 2 for an example. In this configuration, the I
CHIP
is connected
SW1 (G1-G2, H1-H2, J1-J2): Switching Node of Channel
1 Step-Down Converter Stage. Used for test purposes
or EMI-snubbing. May be routed a short distance to a
local test point to monitor switching action of channel
1, if desired, but do not route near any sensitive signals;
otherwise, leave open.
current will not be relevant since INTV
CC_23
to SV
.
IN_23
V
(N9): Input pin to the internal step down regula-
IN_VBIAS
tor that produces 5.5V (V
pin) to power both internal
BIAS
controllers to reduce power dissipation after power up.
Each internal controller has an INTV or INTV
CC_01
CC_23
SW2 (P1-P2, R1-R2, T1-T2): Switching Node of Channel
2 Step-Down Converter Stage. Used for test purposes
or EMI-snubbing. May be routed a short distance to a
local test point to monitor switching action of channel
2, if desired, but do not route near any sensitive signals;
otherwise, leave open.
regulator that is powered from SVIN_01 or SVIN_23. To
eliminate this power loss through these linear regulators,
the V
powers both at very high efficiency.
BIAS
Rev. 0
17
For more information www.analog.com
LTM4681
PIN FUNCTIONS
INTV
(J9): Internal Regulator, 5.5V Output. When
RUNP (N11): This pin enables the Internal 5.5V VBIAS Step
CC_01
operating the LTM4681 from 5.75V ≤ SV
≤ 16V, an
to bias
Down Regulator. Pulling this pin above 0.85V will enable
IN_01
from SV
internal LDO generates INTV
internal control circuits and the MOSFET dIrNiv_e0r1s of the
LTM4681’s channel 0 and 1. An external 4.7µF ceramic
decoupling capacitor is required. INTV
lated regardless of the RUNn pin state. When operating
the LTM4681 with 4.5V ≤ SV < 5.75V, INTV
must be electrically shorted to SV
pin must be pulled to GND. V
when the input voltage is greater than 7V.
the Internal regulator. The pin is rated to V , so tie to
CC_01
IN
V to enable, and tie to GND to disable. When the input
IN
voltage is between 4.5V to 5.75V, pull the RUNP pin to
is on regu-
GND, and connect SV
and SV
to INTV
and
CC_01
IN_01
respectively.
IN_23
CC_01
INTV
CC_23
IN_01
CC_01
, and the RUNP
V
(N10): 5.5V step down output that powers both
BIAS
IN_01
internal controllers to reduce power loss. Provide a 22µF
ceramic bypass capacitor on this pin to GND. SVIN_01
and SVIN_23 must be higher than 7V for this VBIAS to
supply the controllers. When the input voltage is between
4.5V to 5.75V, pull the RUNP pin to GND, and connect
SVIN_01 and SVIN_23 to INTVCC_01 and INTVCC_23, respec-
takes over after startup
BIAS
INTV (P10): Internal Regulator, 5.5V Output. When
CC_23
operating the LTM4681 from 5.75V ≤ SV
≤ 16V, an
to bias
IN_23
from SV
internal LDO generates INTV
internal control circuits and the MOSFET dIrNiv_e2r3s of the
CC_23
tively. Powering up the V
and SVIN_23 greater thanBI7AVS will power the INTVCC_01
regulator with the SV
IN_01
LTM4681’s channel 2 and 3. An external 4.7µF ceramic
decoupling i capacitor s required. INTV
lated regardless of the RUNn pin state. When operating
the LTM4681 with 4.5V ≤ SV < 5.75V, INTV
must be electrically shorted to SV
pin must be pulled to GND. V
when the input voltage is greater than 7V.
,
is on regu-
INTVCC_02, the VDD33_01, VDD33_23, VDD25_01, and
from V . Otherwise these sources will get
CC_23
V
DD25_23
BIAS
their power from SVIN_01 and SVIN_23. This will allow pro-
gramming each internal controller’s EEPROM with the
power regulator channels in the off position.
IN_23
CC_23
, and the RUNP
IN_23
takes over after startup
BIAS
+
IIN_01 (H10): Positive Current Sense Amplifier Input.
V
(E8): Internally Generated 3.3V Power Supply
If the input current sense amplifier is not used, this pin
DD33_01
–
Output Pin for Channel 0 and 1 Circuits. This pin should
only be used to provide external current for the pull-up
resistors required for FAULT_nn, SHARE_CLK_nn, and
SYNC_nn, and may be used to provide external current for
pull-up resistors on RUNn, SDA_nn, SCL_nn, ALERT_nn
and PGOODn. Where nn is either 0,1 or 2,3 channels, and
n is the actual channel. No external decoupling is required.
must be shorted to the IIN_01 and SVIN_01 pin. See
Applications Information section for detail about the
input current sensing.
–
IIN_01 (J10): Negative Current Sense Amplifier Input. If
the input current sense amplifier is not used, this pin must
+
be shorted to the I
and SV
pin. See Applications
IN_01
IN_01
Information section for detail about the input current sensing.
V
can be powered from V
, such that this con-
DD33_01
BIAS
+
I
(R9): Positive Current Sense Amplifier Input. If
troller 1 can be programmed with RUNn low.
tIhNe_2in3put current sense amplifier is not used, this pin
V
(Y10): Internally Generated 3.3V Power Supply
DD33_23
–
must be shorted to the IIN_23 and SVIN_23 pin. See
Output Pin for Channel 2 and 3 Circuits. This pin should
only be used to provide external current for the pull-up
resistors required for FAULT_nn, SHARE_CLK_nn, and
SYNC_nn, and may be used to provide external current for
pull-up resistors on RUNn, SDA_nn, SCL_nn, ALERT_nn
and PGOODn. Where nn is either 0,1 or 2,3 channels, and
n is the actual channel. No external decoupling is required.
Applications Information section for detail about the
input current sensing.
–
I
(P9): Negative Current Sense Amplifier Input. If
tIhNe_2in3put current sense amplifier is not used, this pin
+
must be shorted to the IIN_23 and SVIN_23 pin. See
Applications Information section for detail about the
input current sensing.
V
can be powered from V
, such that this con-
DD33_23
BIAS
troller 2 can be programmed with RUNn low.
Rev. 0
18
For more information www.analog.com
LTM4681
PIN FUNCTIONS
V
(C8): Internally Generated 2.5V Power Supply
of the pin state. It is recommended to use a resistor
to set the address. The ASEL_23 address will be used
to address channels 2 and 3, and a different ASEL_01
address will be used to address channels 1 and 2. For
addressed ASEL_23, Page 0x00 corresponds to channel
2 and Page 0x01 corresponds to Channel 3. See PAGE
description section. The GUI will represent Channel 2 as
U1:B0 and Channel 3 as U1:B1. See Page 66.
DD25_01
Output Pin for Channel 0 and 1 Circuits. Do not load this
pin with external current; it is used strictly to bias internal
logic and provides current for the internal pull-up resis-
tors connected to the configuration-programming pins.
No external decoupling is required.
VDD25_23 (AB11): Internally Generated 2.5V Power Supply
Output Pin for Channel 2 and 3 Circuits. Do not load this
pin with external current; it is used strictly to bias internal
logic and provides current for the internal pull-up resis-
tors connected to the configuration-programming pins.
No external decoupling is required.
FSWPH_01_CFG (A9): Switching Frequency, Channel
Phase-Interleaving Angle and Phase Relationship to SYNC
Configuration Pin for Channel 0 and 1. If this pin is left
open—or, if the LTM4681 is configured to ignore pin-
strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] =
1b—then LTM4681’s switching frequency (FREQUENCY_
SWITCH) and channel phase relationships (with respect
to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dictated
ASEL_01 (B9): Serial Bus Address Configuration Pin for
Channel 0 and 1 Controller. On any given I C/SMBus serial
2
bus segment, every device must have its own unique slave
address. If this pin is left open, the LTM4681 powers up
to its default slave address of 0x4E (hexadecimal), i.e.,
1001110b (industry-standard convention is used through-
out this document: 7-bit slave addressing). The lower four
bits of the LTM4681’s slave address can be altered from
this default value by connecting a resistor from this pin to
SGND. Minimize capacitance—especially when the pin is
left open—to assure accurate detection of the pin state.
It is recommended to use a resistor to set the address.
The ASEL_01 address will be used to address channels
0 and 1, and a different ASEL_23 address will be used
to address channels 2 and 3. For addressed ASEL_01,
Page 0x00 corresponds to channel 0 and Page 0x01 cor-
responds to Channel 1. See PAGE description section. The
GUI will represent Channel 0 as U0:B0 and Channel 1 as
U0:B1. See Page 66.
at SV
power-up according to the LTM4681’s NVM
IN_01
contents for channel 0 and 1. Default factory values are:
350kHz operation; channel 0 at 0°; and channel 1 at 180°C
(convention throughout this document: a phase angle of
0° means the channel’s switch node rises coincident with
the falling edge of the SYNC pulse). Connecting a resistor
divider from 2.5V to SGND (and using the factory-default
NVM setting of MFR_CONFIG_ALL[6] = 0b) allows a con-
venient way to configure multiple LTM4681s with identi-
cal NVM contents for different switching frequencies of
operation and phase interleaving angle settings of intra-
and extra-module-paralleled channels—all, without GUI
intervention or the need to custom pre-program module
NVM contents. (See the Applications Information sec-
tion.) Minimize capacitance—especially when the pin is
left open—to assure accurate detection of the pin state.
ASEL_23 (AA10): Serial Bus Address Configuration Pin
for Channel 2 and 3 Controller. On any given I C/SMBus
FSWPH_23_CFG (AA9): Switching Frequency, Channel
Phase-Interleaving Angle and Phase Relationship to SYNC
Configuration Pin for Channel 2 and 3. If this pin is left
open—or, if the LTM4681 is configured to ignore pin-
strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] =
1b—then LTM4681’s switching frequency (FREQUENCY_
SWITCH) and channel phase relationships (with respect
to the SYNC clock; MFR_PWM_CONFIG[2:0]) are dic-
tated at SVIN_23 power-up according to the LTM4681’s
NVM contents for channel 2 and 3. Default factory values
2
serial bus segment, every device must have its own
unique slave address. If this pin is left open, the LTM4681
powers up to its default slave address of 0x4F (hexa-
decimal), i.e., 1001111b (industry-standard convention is
used throughout this document: 7-bit slave addressing).
The lower four bits of the LTM4681’s slave address can
be altered from this default value by connecting a resistor
from this pin to SGND. Minimize capacitance—especially
when the pin is left open—to assure accurate detection
Rev. 0
19
For more information www.analog.com
LTM4681
PIN FUNCTIONS
are: 350kHz operation; channel 2 at 0°; and channel 3 at
180°C (convention throughout this document: a phase
angle of 0° means the channel’s switch node rises coinci-
dent with the falling edge of the SYNC pulse). Connecting a
resistor divider from 2.5V to SGND (and using the factory-
default NVM setting of MFR_CONFIG_ALL[6] = 0b) allows
a convenient way to configure multiple LTM4681s with
identical NVM contents for different switching frequencies
of operation and phase interleaving angle settings of intra-
and extra-module-paralleled channels—all, without GUI
intervention or the need to custom pre-program module
NVM contents. (See the Applications Information sec-
tion.) Minimize capacitance—especially when the pin is
left open—to assure accurate detection of the pin state.
VTRIM0_CFG (D9): Output Voltage Select Pin for V
,
OUT0
Fine Setting. Works in combination with VOUT0_CFG to
affect the VOUT_COMMAND (and associated output volt-
age monitoring and protection/fault-detection thresholds)
of channel 0, at SV
power-up. (See VOUT0_CFG and
IN_01
the Applications Information section.) A resistor divider
from 2.5V to SGND connected to the pin will set the
TRIM value. See Table 2. Minimize capacitance especially
when the pin is left open to assure accurate detection
of the pin state. Note that use of RCONFIGs on VOUT0_
CFG/VTRIM0_CFG can affect the VOUT0 range setting
(MFR_PWM_MODE0[1]) and loop gain. For addressed
ASEL_01, Page 0x00 corresponds to channel 0 and Page
0x01 corresponds to Channel 1. See PAGE command
description section.
VOUT0_CFG (A8): Output Voltage Select Pin for V
,
OUT0
Coarse Setting. If the VOUT0_CFG and VTRIM0_CFG pins
are both left open—or, if the LTM4681 is configured to
VOUT1_CFG (B8): Output Voltage Select Pin for V
,
OUT1
Coarse Setting. If the VOUT1_CFG and VTRIM1_CFG pins
are both left open—or, if the LTM4681 is configured to
ignore pin-strap (R
) resistors, i.e., MFR_CONFIG_
CONFIG
ALL[6] = 1b—then the LTM4681s target V
output
ignore pin-strap (R
) resistors, i.e., MFR_CONFIG_
voltage setting (VOUT_COMMAND0) andOaUsTs0ociated
power-good and OV/UV warning and fault thresholds are
dictated at SVIN_01 power-up according to the LTM4681’s
NVM contents. A resistor divider connected to 2.5V and
to SGND (see Table 1)—in combination with resistor pin
settings on VTRIM0_CFG, and using the factory-default
NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used
to configure the LTM4681’s channel 0 output to power-
up to a VOUT_COMMAND value (and associated output
voltage monitoring and protection/fault-detection thresh-
olds) different from those of NVM contents. (See the
Applications Information section.) Connecting resistor(s)
from VOUT0_CFG to SGND and/or VTRIM0_CFG to SGND
in this manner allows a convenient way to configure mul-
tiple LTM4681s with identical NVM contents for different
output voltage settings all without GUI intervention or
the need to custom-preprogram module NVM contents.
Minimize capacitance especially when the pin is left open
to assure accurate detection of the pin state. Note that use
ALL[6] = 1b—then the LTM4681s target V
output
CONFIG
voltage setting (VOUT_COMMAND1) andOaUsTs1ociated
power-good and OV/UV warning and fault thresholds are
dictated at SVIN_01 power-up according to the LTM4681’s
NVM contents. A resistor divider connected to 2.5V and
to SGND to this pin—in combination with resistor pin
settings on VTRIM1_CFG, and using the factory-default
NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used
to configure the LTM4681’s channel 1 output to power-
up to a VOUT_COMMAND value (and associated output
voltage monitoring and protection/fault-detection thresh-
olds) different from those of NVM contents. (See the
Applications Information section.) Connecting resistor(s)
from VOUT1_CFG to SGND and/or VTRIM1_CFG to SGND
in this manner allows a convenient way to configure mul-
tiple LTM4681s with identical NVM contents for different
output voltage settings all without GUI intervention or
the need to custom-preprogram module NVM contents.
Minimize capacitance especially when the pin is left open
to assure accurate detection of the pin state. Note that use
of R
s on VOUT0_CFG/VTRIM0_CFG can affect the
CONFIG
VOUT0 range setting (MFR_PWM_MODE0[1]) and loop
gain. For addressed ASEL_01, Page 0x00 corresponds to
channel 0 and Page 0x01 corresponds to Channel 1. See
PAGE description section.
of R
s on VOUT1_CFG/VTRIM1_CFG can affect the
CONFIG
VOUT1 range setting (MFR_PWM_MODE1[1]) and loop
gain. For addressed ASEL_01, Page 0x00 corresponds to
channel 0 and Page 0x01 corresponds to Channel 1. See
PAGE description section.
Rev. 0
20
For more information www.analog.com
LTM4681
PIN FUNCTIONS
VTRIM1_CFG (C9): Output Voltage Select Pin for V
,
VTRIM2_CFG (AB10): Output Voltage Select Pin for VOUT2,
OUT1
Fine Setting. Works in combination with VOUT1_CFG to
affect the VOUT_COMMAND (and associated output volt-
age monitoring and protection/fault-detection thresholds)
Fine Setting. Works in combination with VOUT2_CFG to
affect the VOUT_COMMAND (and associated output volt-
age monitoring and protection/fault-detection thresholds)
of channel 1, at SV
power-up. (See VOUT1_CFG and
of channel 2, at SV
power-up. (See VOUT2_CFG and
IN_01
IN_23
the Applications Information section.) A resistor divider
from 2.5V to SGND connected to the pin will set the TRIM
value. See Table 2. Minimize capacitance especially when
the pin is left open to assure accurate detection of the
pin state. Note that use of RCONFIGs on VOUT1_CFG/
the Applications Information section.) A resistor divider
from 2.5V to SGND connected to the pin will set the TRIM
value. See Table 2. Minimize capacitance especially when
the pin is left open to assure accurate detection of the
pin state. Note that use of RCONFIGs on VOUT2_CFG/
VTRIM1_CFG can affect the V
range setting (MFR_
VTRIM2_CFG can affect the V
range setting (MFR_
OUT1
OUT2
PWM_MODE1[1]) and loop gain. For addressed ASEL_01,
Page 0x00 corresponds to channel 0 and Page 0x01 cor-
responds to Channel 1. See PAGE description section.
PWM_MODE0[1]) and loop gain. For addressed ASEL_23,
Page 0x00 corresponds to channel 2 and Page 0x01 cor-
responds to Channel 3. See PAGE description section.
VOUT2_CFG (AA8): Output Voltage Select Pin for V
Coarse Setting. If the VOUT2_CFG and VTRIM2_CFG pins
are both left open—or, if the LTM4681 is configured to
,
VOUT3_CFG (AB8): Output Voltage Select Pin for V
Coarse Setting. If the VOUT3_CFG and VTRIM3_CFG pins
are both left open—or, if the LTM4681 is configured to
,
OUT2
OUT3
ignore pin-strap (R
) resistors, i.e., MFR_CONFIG_
ignore pin-strap (R
) resistors, i.e., MFR_CONFIG_
CONFIG
CONFIG
ALL[6] = 1b—then the LTM4681s target V
output
ALL[6] = 1b—then the LTM4681s target V
output
voltage setting (VOUT_COMMAND0) andOaUsTs2ociated
power-good and OV/UV warning and fault thresholds are
dictated at SVIN_23 power-up according to the LTM4681’s
NVM contents. A resistor divider connected to 2.5V and
to SGND to this pin—in combination with resistor pin
settings on VTRIM2_CFG, and using the factory-default
NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used
to configure the LTM4681’s channel 2 output to power-
up to a VOUT_COMMAND value (and associated output
voltage monitoring and protection/fault-detection thresh-
olds) different from those of NVM contents. (See the
Applications Information section.) Connecting resistor(s)
from VOUT2_CFG to SGND and/or VTRIM2_CFG to SGND
in this manner allows a convenient way to configure mul-
tiple LTM4681s with identical NVM contents for different
output voltage settings all without GUI intervention or
the need to custom-preprogram module NVM contents.
Minimize capacitance especially when the pin is left open
to assure accurate detection of the pin state. Note that use
voltage setting (VOUT_COMMAND3) andOaUsTs3ociated
power-good and OV/UV warning and fault thresholds are
dictated at SVIN_23 power-up according to the LTM4681’s
NVM contents. A resistor divider connected to 2.5V and
to SGND to this pin—in combination with resistor pin
settings on VTRIM3_CFG, and using the factory-default
NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used
to configure the LTM4681’s channel 3 output to power-
up to a VOUT_COMMAND value (and associated output
voltage monitoring and protection/fault-detection thresh-
olds) different from those of NVM contents. (See the
Applications Information section.) Connecting resistor(s)
from VOUT3_CFG to SGND and/or VTRIM3_CFG to SGND
in this manner allows a convenient way to configure mul-
tiple LTM4681s with identical NVM contents for different
output voltage settings all without GUI intervention or
the need to custom-preprogram module NVM contents.
Minimize capacitance especially when the pin is left open
to assure accurate detection of the pin state. Note that use
of R
s on VOUT2_CFG/VTRIM2_CFG can affect the
of R
s on VOUT3_CFG/VTRIM3_CFG can affect the
CONFIG
CONFIG
VOUT2 range setting (MFR_PWM_MODE0[1]) and loop
gain.For addressed ASEL_23, Page 0x00 corresponds to
channel 2 and Page 0x01 corresponds to Channel 3. See
PAGE description section.
VOUT3 range setting (MFR_PWM_MODE1[1]) and loop
gain. For addressed ASEL_23, Page 0x00 corresponds to
channel 2 and Page 0x01 corresponds to Channel 3. See
PAGE description section.
Rev. 0
21
For more information www.analog.com
LTM4681
PIN FUNCTIONS
VTRIM3_CFG (AB9): Output Voltage Select Pin for VOUT3
,
logic high with a low impedance source. INTV is active
CC
Fine Setting. Works in combination with VOUT3_CFG to
affect the VOUT_COMMAND (and associated output volt-
age monitoring and protection/fault-detection thresholds)
when SVIN_23 is above UVLO. This provides power to the
VDD33 and VDD25 to allow programming the EEPROM.
PGOOD0, PGOOD1, PGOOD2, PGOOD3 (H9, H8, R10,
T10): Power Good Indicator Outputs. Open-drain logic
output that is pulled to ground when the output exceeds
the UV and OV regulation window. The output is de-
glitched by an internal 100µs filter. A pull-up resistor to
3.3V is required in the application.
of channel 3, at SV
power-up. (See VOUT3_CFG and
IN_23
the Applications Information section.) A resistor divider
from 2.5V to SGND connected to the pin will set the TRIM
value. See Table 2. Minimize capacitance especially when
the pin is left open to assure accurate detection of the
pin state. Note that use of RCONFIGs on VOUT3_CFG/
FAULT0, FAULT1, FAULT2, FAULT3 (A11, A10, V10,
W10): Digital Programmable FAULT Inputs and Outputs.
Open-drain output. A pull-up resistor to 3.3V is required
in the application.
VTRIM3_CFG can affect the V
range setting (MFR_
OUT3
PWM_MODE0[1]) and loop gain. For addressed ASEL_23,
Page 0x00 corresponds to channel 2 and Page 0x01 cor-
responds to Channel 3. See PAGE description section.
COMP0b, COMP1b, COMP2b, COMP3b (G10, F9, T9,
W11): Current Control Threshold and Error Amplifier
Compensation Nodes. Each associated channel’s current
comparator tripping threshold increases with its compen-
sation voltage. Each channel has a 22pF to SGND.
RUN0, RUN1 (B10, B11 Respectively): Enable Run Input
for Channels 0 and 1, respectively. Open-drain input and
output. Logic high on these pins enables the respective
outputs of the LTM4681. These open-drain output pins
hold the pin low until the LTM4681 is out of reset and
SV
is detected to exceed V
. A pull-up resistor
IN_01
IN_ON
COMP0a, COMP1a, COMP2a, COMP3a (G11, G9, T8,
V11): Loop Compensation Nodes. The internal PWM
loop compensation resistors RCOMPn of the LTM4681
can be adjusted using bit[4:0] of the MFR_PWM_COMP
command. The transconductance of the LTM4681 PWM
error amplifier can be adjusted using bit[7:5] of the MFR_
PWM_COMP command. These two loop compensation
parameters can be programmed when device is in opera-
tion. Refer to the Programmable Loop Compensation sub-
section in the Applications Information section for further
details. See Figure 1.
to 3.3V is required in the application. The LTM4681 pulls
RUN0 and/or RUN1 low, as appropriate, when a global
fault and/or channel-specific fault occurs whose fault
response is configured to latch off and cease regulation;
issuing a CLEAR_FAULTS command via I2C or power-
cycling SV
is necessary to restart the module, in such
cases. Do InNo_0t1pull RUN logic high with a low impedance
source. INTV is active when SVIN_01 is above UVLO.
CC
This provides power to the VDD33 and VDD25 to allow
programming the EERROM.
RUN2, RUN3 (Y9, Y8): Enable Run Input for Channels 2
and 3, respectively. Open-drain input and output. Logic
high on these pins enables the respective outputs of the
LTM4681. These open-drain output pins hold the pin low
SYNC_01, SYNC_23 (D11,V9): External Clock
Synchronization Input and Open-Drain Output Pin. If
an external clock is present at this pin, the switching
frequency will be synchronized to the external clock. If
clock master mode is enabled, this pin will pull low at
the switching frequency with a 500ns pulse to ground.
A resistor pull-up to 3.3V is required in the application if
the LTM4681 is the master.
until the LTM4681 is out of reset and SV
is detected
IN_23
to exceed V
. A pull-up resistor to 3.3V is required in
IN_ON
the application. The LTM4681 pulls RUN2 and/or RUN3
low, as appropriate, when a global fault and/or channel-
specific fault occurs whose fault response is configured to
SCL_01, SCL_23 (D10, W9): Serial Bus Clock Open-Drain
Input (Can Be an Input and Output, if Clock Stretching
is Enabled). A pull-up resistor to 3.3V is required in the
latch off and cease regulation; issuing a CLEAR_FAULTS
2
command via I C or power-cycling SV
is necessary
to restart the module, in such cases.IND_o23not pull RUN
Rev. 0
22
For more information www.analog.com
LTM4681
PIN FUNCTIONS
application only if SMBALERT interrupt detection is imple-
mented in one’s SMBus system.
application for digital communication to the SMBus
master(s) that nominally drive this clock. The LTM4681
will never encounter scenarios where it would need to
engage clock stretching unless SCL communication
speeds exceed 100kHz—and even then, LTM4681 will not
clock stretch unless clock stretching is enabled by means
of setting MFR_CONFIG_ALL[1] = 1b. The factory-default
NVM configuration setting has MFR_CONFIG_ALL[1] =
0b: clock stretching disabled. If communication on the
bus at clock speeds above 100kHz is required, the user’s
SMBus master(s) needs to implement clock stretching
support to assure solid serial bus communications, and
only then should MFR_CONFIG_ALL[1] be set to 1b.
When clock stretching is enabled, SCL becomes a bidi-
rectional, open-drain output pin on LTM4681.
SHARE_CLK_01, SHARE_CLK_23 (D8, AA11): Share
Clock, Bidirectional Open-Drain Clock Sharing Pin.
Nominally 100kHz. Used for synchronizing the time
base between multiple LTM4681s (and any other Analog
Devices products with a SHARE_CLK pin)—to realize
well-defined rail sequencing and rail tracking. Tie the
SHARE_CLK pins of all such devices together; all devices
with a SHARE_CLK pin will synchronize to the fastest
clock. A pull-up resistor to 3.3V is only required when
synchronizing the time base between devices.
TSNS0, TSNS1, TSNS2, TSNS3 (E11, E10, U8, U9):
Power stage temperature monitors for the 4channels.
See Applications Information section.
SDA_01, SDA_23 (C10, V8): Serial Bus Data Open-Drain
Input and Output. A pull-up resistor to 3.3V is required
in the application. SDA_01 is for Channel 0 and 1, and
SDA_23 is for Channel 2 and 3.
WP_01, WP_23 (E9, Y11): Write Protect Pin, Active High.
An internal 10µA current source pulls this pin to V
. If
DD33
2
WP is open circuit or logic high, only I C writes to PAGE,
OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and
MFR_EE_UNLOCK are supported. Additionally, Individual
faults can be cleared by writing 1b’s to bits of interest in
ALERT_01, ALERT_23 (C11, W8): Open-Drain Digital
Output. A pull-up resistor to 3.3V is required in the
2
registers prefixed with STATUS. If WP is low, I C writes
are unrestricted.
Rev. 0
23
For more information www.analog.com
LTM4681
SIMPLIFIED BLOCK DIAGRAM
1Ω
ꢀꢁꢂ
Channel #
GUI
ꢀꢁꢁ ꢂꢃꢄꢅ ꢅꢆꢇꢈꢄ ꢃꢅ ꢉꢊꢄꢋꢌꢃꢇꢄ ꢍꢎ
ꢌꢇ ꢅꢊꢂꢂꢇRꢌ ꢋꢆꢀꢄꢄꢏꢁꢅ 0 ꢀꢄꢐ ꢑꢒ
ꢀꢄꢐ ꢋꢆꢀꢄꢄꢏꢁꢅ ꢎ ꢀꢄꢐ ꢓ.
R
ꢀꢁꢂꢀꢁ
Identity
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀꢀꢁꢂ
ꢀ.ꢁꢂꢃ
0
1
2
3
U0:A0
U0:A1
U0:B0
U0:B1
ꢄ
ꢄ
ꢀꢁ
ꢀꢁ
ꢆ
ꢀꢁꢂ0ꢃ ꢅ
ꢀꢁꢂ0ꢃ ꢅ
ꢀ
ꢁꢂ0ꢃ
ꢀ
ꢁꢂꢅꢆ
ꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢇ
ꢀ
ꢀ
ꢀ
ꢅ
ꢀ
ꢁꢂ0ꢃ
ꢀ
ꢁꢂꢅꢆ
ꢄ
ꢂꢃꢄ0ꢅ
ꢂꢃꢄꢇꢈ
ꢄꢄꢅ0ꢆ
ꢁꢂꢃꢄ
ꢁꢁꢂꢂꢃ0ꢄ
ꢁꢁꢂꢂꢃꢆꢂ
ꢄ
ꢄ
ꢀꢁꢂꢆꢇ
ꢀꢁꢂꢆꢇ
ꢄꢄꢅꢈꢉ
0.ꢀꢀꢁꢂ
ꢀ.ꢀꢁꢂ
0.ꢀꢁꢂ
0.ꢀꢀꢁꢂ
ꢀ ꢁ ꢂ
ꢀ
ꢀ
ꢁꢂꢃꢀꢄꢁꢅꢆ
ꢁꢂꢃꢄ
ꢀ.ꢀꢁ
ꢀ
ꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂꢃꢄ ꢅꢃRRꢆꢁꢄꢇꢀꢅꢈꢀꢂ ꢉRꢆꢊꢋꢌꢀꢀꢁꢍ
ꢎꢏRꢌRꢆꢊꢋꢌꢀꢀꢁꢌꢂꢆꢊꢐ ꢄꢑ ꢊꢁꢊꢒꢑꢓ
Rꢆꢊꢋꢔꢊꢅꢐꢕ
ꢀꢁ0ꢂ ꢀꢁꢃ
ꢀꢁꢂꢃ ꢀꢁꢄ
ꢀ
ꢄ ꢀ
ꢃꢁ ꢉ.ꢉꢀ
ꢂꢊ ꢃꢁ ꢉꢋ.ꢅꢌꢆ
ꢆꢇꢈ
ꢀꢁ
ꢁꢂꢃ0 ꢁꢂꢃꢅ
ꢀ
ꢅ ꢀ
ꢃꢁ ꢆ.ꢆꢀ
ꢂꢊ ꢃꢁ ꢆꢄ.ꢋꢌꢇ
ꢇꢈꢉ
ꢀꢁ
ꢁꢂꢃꢄ ꢁꢂꢃꢆ
ꢀꢁ0ꢂꢃ
ꢀꢁ0ꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃ0
ꢁꢂꢃꢄ
ꢀꢁꢂꢃR ꢄꢁꢅꢆRꢁꢇ
ꢈꢅꢈꢇꢁꢉ ꢊꢃꢄꢆꢋꢁꢅ
ꢀ
ꢁꢂꢃꢄ
ꢀ.ꢀꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ0ꢅꢆ ꢀꢁꢂꢃꢄꢇꢈ
0.0ꢀꢁꢂ
ꢀꢁꢂ ꢃꢂꢄꢅ ꢆꢂꢇꢆꢂ
0.0ꢀꢁꢂ
ꢀꢁꢂꢁ0
ꢀꢁꢂꢁꢃ
ꢀꢁ ꢂꢃꢂꢄꢁꢅ
Rꢆꢂꢇꢈꢂꢉꢊ
ꢀꢁ ꢂꢃꢂꢄꢁꢅ
Rꢆꢂꢇꢈꢂꢉꢊ
ꢀ ꢄꢂRRꢅꢆꢃ ꢇꢅꢆꢇꢅ
ꢁꢂꢃ
ꢀ
ꢄꢂRRꢅꢆꢃ ꢇꢅꢆꢇꢅ
ꢁꢂꢃ
ꢀꢁꢂꢁ0ꢃ ꢀꢁꢂꢁꢄ
ꢀꢁꢂꢁꢃꢄ ꢀꢁꢂꢁꢅ
ꢀꢁꢂꢃ ꢂꢄꢅ
ꢄ
ꢄ
ꢅ
ꢅ
ꢀ
ꢅ ꢀ
ꢁꢂꢃꢂꢆ
ꢀ
ꢆ ꢀ
ꢁꢂꢃꢂ0
ꢁꢂꢃꢂꢄ
ꢁꢂꢃꢂꢇ
Rꢀꢁꢂꢃꢀ ꢄꢀꢅꢄꢀ
Rꢀꢁꢂꢃꢀ ꢄꢀꢅꢄꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀ
ꢁꢂꢃꢄ
ꢀꢁ
ꢁꢂꢃꢄ
ꢀꢁꢁ ꢀꢂꢀꢁꢃꢄ
Rꢅꢀꢆꢇꢀꢈꢉ ꢊꢋꢄꢂꢀꢁꢊ
ꢅ
ꢅ
ꢄ
ꢄ
ꢀ
ꢆ ꢀ
ꢁꢂꢃꢂꢄ
ꢁꢂꢃꢂꢇ
ꢀ
ꢅ ꢀ
ꢁꢂꢃꢂꢆ
ꢁꢂꢃꢂ0
ꢀRꢁꢂ ꢂꢃ
ꢀꢁ0ꢂꢃ
ꢀRꢁꢂ ꢂꢃ
ꢀ0ꢁꢀ ꢂꢃꢄ
ꢀꢁꢂꢃꢄꢅꢆ ꢀꢁꢂꢃꢇꢅ
ꢀꢀꢁꢂ
ꢀꢁꢂꢃ0ꢄꢅ ꢀꢁꢂꢃꢆꢄ
ꢀꢁꢂꢃꢄ
ꢀRꢁꢂ R
ꢀꢀꢁꢂ
ꢀRꢁꢂ R
ꢀ
ꢃꢁꢄꢀ
ꢃꢁꢄꢀ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃ0ꢄꢅ ꢀꢁꢂꢃꢆꢄ
ꢀꢁꢂꢃꢄꢅꢆ ꢀꢁꢂꢃꢇꢅ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢂꢃ0ꢄ ꢀꢁꢂꢂꢃꢅ
ꢀꢁꢂꢂꢃꢄꢅ ꢀꢁꢂꢂꢃꢆ
ꢀ.ꢀꢁ
ꢀꢁꢂ ꢀꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄ0ꢅꢆ ꢀꢁꢂꢃꢄꢇꢈ
ꢂꢃꢄꢅRꢆꢇꢂ ꢈꢉꢄꢄꢊꢉꢈ
ꢇꢃꢂ ꢋꢌꢃꢍꢇ
ꢀꢁꢂ ꢃꢄꢅꢅꢆRꢆꢇꢀ ꢈꢉꢊ
ꢋꢂꢇꢀRꢂꢌꢌꢆRꢉ
ꢍꢉꢀ ꢋꢂꢇꢀRꢂꢌꢌꢆR
ꢀꢁꢂꢃR ꢄꢁꢅꢆRꢁꢇ ꢈꢉꢊꢉꢆꢋꢇ ꢌꢃꢄꢆꢉꢁꢅ
ꢀ
ꢆ ꢀ
ꢁꢁꢂꢃꢄ0ꢅ ꢁꢁꢂꢃꢄꢂꢇ
ꢀ.ꢁꢂ
ꢎꢈꢏꢐꢆ 0ꢑ00ꢒ ꢓ ꢋꢔꢏꢇꢇꢆꢌ 0
ꢎꢈꢏꢐꢆ 0ꢑ0ꢍꢒ ꢓ ꢋꢔꢏꢇꢇꢆꢌ ꢍ
ꢕꢇꢃ ꢋꢂꢇꢀRꢂꢌꢌꢆR
ꢎꢈꢏꢐꢆ 0ꢑ00ꢒ ꢓ ꢋꢔꢏꢇꢇꢆꢌ ꢕ
ꢎꢈꢏꢐꢆ 0ꢑ0ꢍꢒ ꢓ ꢋꢔꢏꢇꢇꢆꢌ ꢖ
ꢀ.ꢀꢁꢂ
ꢀꢁ.ꢂꢃ
ꢄꢅꢆꢇ ꢈꢉꢊ
ꢀꢁꢂꢃ0ꢄꢅ ꢀꢁꢂꢃꢆꢇ
ꢀꢁꢂ ꢃꢄꢀꢅꢆR
Rꢀꢁ
ꢀꢁꢂꢃ ꢄRꢅꢆꢇR
ꢀꢁꢂꢃ0ꢄꢅ ꢀꢁꢂꢃꢆꢇ
ꢀꢁꢂꢃꢄ0ꢅꢆ ꢀꢁꢂꢃꢄꢇꢈ
ALERTꢀ0ꢁꢂ ALERTꢀꢃꢄ
ꢀꢁꢂꢃꢄꢅ0ꢆꢅꢇꢀꢈꢉ ꢀꢁꢂꢃꢄꢅꢊꢋꢅꢇꢀꢈ
ꢀ.ꢀꢁꢂꢃꢄꢅꢆRꢇꢈꢃ
ꢉꢊꢅꢅꢂꢊꢉ ꢈꢄꢃ
ꢋꢌꢄꢍꢈ
ꢀꢁꢂꢁꢃꢄꢅ ꢆꢇꢂꢁꢇꢆ
Rꢀꢁ
ꢀꢁꢂ0ꢃꢄ ꢀꢁꢂꢅꢆ
ꢀꢁꢂꢃꢄ ꢅꢆꢇ
ꢀꢁRꢂꢃ0ꢄꢅꢆꢇ
ꢀꢁꢂꢀRꢃꢄꢅ Rꢀꢆꢇꢆꢂꢇꢈꢀ
ꢉꢇꢈꢇꢉꢀRꢆ ꢊꢀꢂꢋꢀꢀꢃ
ꢀꢁRꢂꢃꢄꢅꢆꢇꢈ
ꢀꢁRꢂꢃꢄꢅꢆꢇꢈꢉ ꢀꢁRꢂꢃꢊꢅꢆꢇꢈ
ꢀꢁꢂꢃ0ꢄꢅꢆꢇ
Rꢀꢁ0ꢂ Rꢀꢁꢃ
ꢀꢀꢁRꢂꢃ
ꢈ
ꢄꢃꢉ
ꢉꢉꢌꢍꢎnn
Rꢀꢁꢂꢃ Rꢀꢁꢄ
ꢆꢏꢃꢉꢎnn ꢄRꢀ
ꢃꢐꢂ ꢆꢑꢐꢋꢃ.
RꢀꢒꢀR ꢂꢐ
FAULT0ꢀ FAULT1
ꢀ.ꢀꢁꢂꢃꢄꢅꢆRꢇꢈꢃ
ꢉꢊꢅꢅꢂꢊꢉ ꢈꢄꢃ
ꢋꢌꢄꢍꢈ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
FAULT2ꢀ FAULT3
ꢂꢄꢊꢅꢀꢆ ꢓꢔ ꢌ ꢄꢃꢉ ꢕ.
ꢀꢁꢂRꢃꢄꢅꢆꢇꢄ0ꢈꢉ ꢀꢁꢂRꢃꢄꢅꢆꢇꢄꢊꢋ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉ ꢀꢁꢂꢃꢊꢅꢆꢇꢈ
0
Figure 2. Simplified LTM4681 Block Diagram of the 1/2 Function
TA = 25°C. Using Figure 1 configuration.
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
External High Frequency Input Capacitor Requirement
I
I
= 31.25A
= 31.25A
100
100
µF
µF
INH
OUT0
OUT1
(5.75V ≤ V ≤ 16V, V
Commanded to 1.000V)
IN
OUTn
C
External High Frequency Output Capacitor Requirement
(5.75V ≤ V ≤ 16V, V Commanded to 1.000V)
I
I
= 31.25A
= 31.25A
800
800
µF
µF
OUTn
OUT0
OUT1
IN
OUTn
Rev. 0
24
For more information www.analog.com
LTM4681
FUNCTIONAL DIAGRAM
Channel #
GUI
Identity
0
1
2
3
U0:A0
U0:A1
U0:B0
U0:B1
ꢁ ꢀ
ꢁ ꢀ
ꢀ
ꢁ
ꢀ
ꢁ
ꢀ
ꢁ ꢂ
ꢀ
ꢁ ꢂ
ꢀ
ꢁ ꢂ
ꢀ
ꢁ
ꢀ
ꢀ ꢁ
ꢀ
Figure 3. Functional LTM4681 Block Diagram
Rev. 0
25
For more information www.analog.com
LTM4681
TEST CIRCUITS
V
DD33_01
4.7µF
22µF
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
10k
4.99k
10k
10k
10k
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
4.7µF
SW0
1V AT 31.25A
ADJUSTABLE TO 3.3V
V
OUT0
+
100µF
×5
V
V
OSNS0
V
IN
, 5.75V TO 16V
+
IN_01
LOAD
+
–
22µF
×6
150µF
1mΩ
1mΩ
OSNS0
–
1Ω
IN_01
V
IN01
SW1
1V AT 31.25A
ADJUSTABLE TO 3.3V
SV
IN_01
V
OUT1
+
1µF
100µF
×5
V
V
OSNS1
LOAD
V
IN
+
–
IN_23
OSNS1
–
1Ω
IN_23
SW2
1V AT 31.25A
V
SV
ADJUSTABLE TO 3.3V
IN23
V
OUT2
+
IN_23
100µF
V
V
1µF
10k
OSNS2
V
IN_VBIAS
LTM4681
×5
V
IN
LOAD
RUNP
V
DD33_01
–
OSNS2
RUN0
RUN1
RUN2
RUN3
SW3
1V AT 31.25A
ADJUSTABLE TO 3.3V
ON_OFF_CONFIG
V
OUT3
+
100µF
10k
FAULT0
FAULT1
FAULT2
FAULT3
V
V
OSNS3
×5
LOAD
–
OSNS3
FAULT INTERRUPTS
GND
PGOOD0
PGOOD1
PGOOD2
PGOOD3
10k
SGND_23
SGND_01
POWER GOOD
4681TC01
2200pF
2200pF
2200pF
100pF
2200pF
32.4k
22.6k
100pF
100pF
100pF
14.3k
14.3k
14.3k
14.3k
14.3k
14.3k
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢈꢁ ꢊꢆ ꢋꢌꢍ ꢎ0ꢏꢏꢐ
ꢇꢑꢉꢒꢆ ꢉꢓꢓRꢆꢇꢇꢔꢋ00ꢕꢋꢋꢋ0ꢕRꢖꢗ
ꢃꢁR ꢘꢍꢙ ꢓꢆꢒꢄꢀꢆ
1.65k
22.6k
2.43k
2.43k
2.43k
2.43k
ꢀꢁRꢂꢃꢄꢅꢁꢆꢇꢂꢈꢉꢉ ꢊꢋꢌꢍꢎꢏ ꢐꢑ
ꢁꢄR 0ꢒꢑ ꢓꢔꢕꢆꢃꢔ
ꢖꢉꢈꢕꢔ ꢈꢓꢓRꢔꢖꢖꢗꢑ00ꢂꢑꢑꢑꢑꢂRꢘꢙ
Test Circuit 1.
Rev. 0
26
For more information www.analog.com
LTM4681
TEST CIRCUITS
SV
IN_01
4.7µF
SV
V
DD33_01
22µF
IN_23
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
10k
4.99k
10k
10k
10k
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
4.7µF
SW0
1V AT 31.25A
ADJUSTABLE TO 3.3V
V
OUT0
+
100µF
×5
V
V
V
IN
, 4.5V TO 5.75V
OSNS0
+
IN_01
LOAD
+
22µF
×6
–
150µF
1mΩ
OSNS0
–
1Ω
IN_01
V
IN01
SW1
1V AT 31.25A
SV
IN_01
ADJUSTABLE TO 3.3V
SV
IN_01
V
OUT1
+
1µF
100µF
V
V
OSNS1
×5
LOAD
V
IN
+
IN_23
–
OSNS1
1mΩ
–
1Ω
SV
IN_23
SW2
1V AT 31.25A
ADJUSTABLE TO 3.3V
V
IN23
IN_23
V
OUT2
+
SV
V
IN_23
100µF
V
V
OSNS2
1µF
10k
V
LTM4681
×5
IN
IN_VBIAS
RUNP
LOAD
V
DD33_01
–
OSNS2
RUN0
RUN1
RUN2
RUN3
SW3
1V AT 31.25A
ADJUSTABLE TO 3.3V
ON_OFF_CONFIG
V
OUT3
+
100µF
10k
V
V
FAULT0
FAULT1
FAULT2
FAULT3
OSNS3
×5
LOAD
–
OSNS3
FAULT INTERRUPTS
GND
PGOOD0
PGOOD1
PGOOD2
PGOOD3
10k
SGND_23
SGND_01
POWER GOOD
4681TC02
2200pF
2200pF
2200pF
100pF
2200pF
32.4k
22.6k
100pF
100pF
100pF
14.3k
14.3k
14.3k
14.3k
14.3k
14.3k
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢈꢁ ꢊꢆ ꢋꢌꢍ ꢎ0ꢏꢏꢐ
ꢇꢑꢉꢒꢆ ꢉꢓꢓRꢆꢇꢇꢔꢋ00ꢕꢋꢋꢋ0ꢕRꢖꢗ
ꢃꢁR ꢘꢍꢙ ꢓꢆꢒꢄꢀꢆ
1.65k
22.6k
2.43k
2.43k
2.43k
2.43k
ꢀꢁRꢂꢃꢄꢅꢁꢆꢇꢂꢈꢉꢉ ꢊꢋꢌꢍꢎꢏ ꢐꢑ
ꢁꢄR 0ꢒꢑ ꢓꢔꢕꢆꢃꢔ
ꢖꢉꢈꢕꢔ ꢈꢓꢓRꢔꢖꢖꢗꢑ00ꢂꢑꢑꢑꢑꢂRꢘꢙ
Test Circuit 2.
Rev. 0
27
For more information www.analog.com
LTM4681
OPERATION
POWER MODULE INTRODUCTION
n
n
n
Fault Logging
The LTM4681 is a highly configurable quad 31.25A out-
put standalone nonisolated switching mode step-down
DC/DC power supply with built-in EEPROM NVM (non-
volatile memory) with ECC and I2C-based PMBus/ SMBus
2-wire serial communication interface capable of 400kHz
SCL bus speed. Four output voltages can be regulated
Programmable Output Voltage
Programmable Input Voltage On and Off Threshold
Voltage
n
n
n
n
n
n
Programmable Current Limit
Programmable Switching Frequency
Programmable OV and UV Threshold voltage
Programmable ON and Off Delay Times
Programmable Output Rise/Fall Times
(V
, V
, V
, V
) with a few external input
OUT1 OUT2 OUT3
anOdUoT0utput capacitors and pull-up resistors. Readback
telemetry data of input and output voltages and input and
output currents, and module temperatures are continually
digitized cyclically by an integrated 16-bit ADC (analog-to-
digital converter). Many fault thresholds and responses
are customizable. Data can be autonomously saved to
EEPROM when a fault occurs, and the resulting fault log
Phase-Locked Loop for Synchronous PolyPhase
Operation (2, 3, 4 or 6 Phases)
n
n
Nonvolatile Configuration Memory with ECC
2
can be retrieved over I C at a later time, for analysis. See
Optional External Configuration Resistors for Key
Operating Parameters
Figure 2 and Figure 3 for Block Diagrams. One controller
for channels 0 and 1, 2nd controller for channels 2 and 3.
n
Optional Time Base Interconnect for Synchronization
Between Multiple Controllers
POWER MODULE OVERVIEW, MAJOR FEATURES
n
n
Major Features Include:
WP Pin to Protect Internal Configuration
n
Dedicated Power Good Indicators
Stand Along Operation After User Factory
Configuration
n
Direct Input and Chip Current Sensing
n
PMBus, Version 1.2, 400kHz Compliant Interface
n
Programmable Loop Compensation Parameters
The PMBus interface provides access to important power
management data during system operation including:
n
T
Start-Up Time: 30ms
INIT
n
n
PWM Synchronization Circuit, (See Frequency and
Phasing Section for Details)
n
Internal Controller Temperature
n
Internal Power Channel Temperature
MFR_ADC_CONTROL for Fast ADC Sampling of One
Parameter (as Fast as 8ms) (See PMBus Command
for Details)
n
Average Output Current
n
Average Output Voltage
n
Fully Differential Output Sensing for All Four Channels;
V
3.3V
n
Average Input Voltage
/V
/V
/V
All Programmable Up to
OUT0 OUT1 OUT2 OUT3
n
Average Input Current
n
n
n
n
n
Average Chip Input Current from V
Power-Up and Program EEPROM with V
Input Voltage Up to 16V
IN
BIAS
n
Configurable, Latched and Unlatched Individual Fault
and Warning Status
∆V Temperature Sensing
BE
Individual channels are accessed through the PMBus
using the PAGE command, i.e., PAGE 0 or 1.
SYNC Contention Circuit (Refer to Frequency and
Phase Section for Details)
Rev. 0
28
For more information www.analog.com
LTM4681
OPERATION
Fault reporting and shutdown behavior are fully configu-
rable. Four individual FAULT0, FAULT1, FAULT2, FAULT3,
outputs are provided, both of which can be masked
independently.
EEPROM write operations. All EEPROM write operations
will be re-enabled when the die temperature drops below
125°C. (The controller will also disable all the switching
when the die temperature exceeds the internal overtem-
perature fault limit 160°C with a 10°C hysteresis).
Six dedicated pins for ALERT_01, ALERT_23, PGOOD0,
PGOOD1, PGOOD2, PGOOD3 functions are provided. The
shutdown operation also allows all faults to be individually
masked and can be operated in either unlatched (hiccup)
or latched modes.
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimen-
sionless acceleration factor using the following equation:
⎡
⎤
⎥
⎦
⎛
⎞
Ea
k
1
1
⎛
⎞
•
–
⎢
⎜
⎟
⎠
⎜
⎟
AF = e⎣⎝
where:
Individual status commands enable fault reporting over
the serial bus to identify the specific fault event. Fault or
warning detection includes the following:
TUSE+273 TSTRESS+273
⎝
⎠
n
AF = acceleration factor
Output Undervoltage/Overvoltage
Ea = activation energy = 1.4eV
k = 8.617 • 10 eV/K
n
Input Undervoltage/Overvoltage
–5
n
Input and Output Overcurrent
T
T
= 125°C specified junction temperature
USE
n
Internal Overtemperature
= actual junction temperature in °C
STRESS
n
Communication, Memory or Logic (CML) Fault
Example: Calculate the effect on retention when operating
at a junction temperature of 130°C for 10 hours.
EEPROM WITH ECC
T
T
= 130°C
STRESS
The LTM4681 contains internal EEPROM with ECC
(Error Correction Coding) to store user configuration
settings and fault log information for channels 0 and 1,
and channels 2 and 3. EEPROM endurance retention and
mass write operation time are specified in the Electrical
Characteristics and Absolute Maximum Ratings sections.
= 125°C,
–5
([(1.4/8.617 • 10 ) • (1/398 – 1/403)] )
USE
AF = e
= 1.66
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded
by 6.6 hours as a result of operating at a junction tempera-
ture of 130°C for 10 hours. The effect of the overstress is
negligible when compared to the overall EEPROM reten-
tion rating of 87,600 hours at a maximum junction tem-
perature of 125°C.
Write operations above T = 85°C are possible although
J
the Electrical Characteristics are not guaranteed and the
EEPROM will be degraded. Read operations performed at
temperatures between –40°C and 125°C will not degrade
the EEPROM. Writing to the EEPROM above 85°C will
result in a degradation of retention characteristics. The
fault logging function, which is useful in debugging sys-
tem problems that may occur at high temperatures, only
writes to fault log EEPROM locations. If occasional writes
to these registers occur above 85°C, the slight degrada-
tion in the data retention characteristics of the fault log
will not take away from the usefulness of the function.
The integrity of the entire onboard EEPROM is checked with
a CRC calculation each time its data is to be read, such as
after a power-on reset or execution of a RESTORE_USER_
ALL command. If a CRC error occurs, the CML bit is set in
the STATUS_BYTE and STATUS_WORD commands, the
EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC
command is set, and the ALERT and RUN pins pulled
low (PWM channels off). At that point the device will only
respond at special address 0x7C, which is activated only
after an invalid CRC has been detected. The chip will also
It is recommended that the EEPROM not be written when
the die temperature is greater than 85°C. If the die tem-
perature exceeds 130°C, the LTM4681 will disable all
Rev. 0
29
For more information www.analog.com
LTM4681
OPERATION
respond at the global addresses 0x5A and 0x5B, but use
of these addresses when attempting to recover from a
CRC issue is not recommended. All power supply rails
associated with either PWM channel of a device reporting
an invalid CRC should remain disabled until the issue is
resolved. See the Applications Information section or con-
tact the factory for details on efficient in-system EEPROM
programming, including bulk EEPROM Programming,
which the LTM4681 also supports.
pin has the programmable resistor range along with a
capacitor to SGND that sets the frequency compensa-
tion. See Programmable Loop Compensation section.
The LTM4681 module has sufficient stability margins and
good transient performance with a wide range of output
capacitors—even all-ceramic MLCCs. Table 13 provides
guidance on input and output capacitors recommended
for many common operating conditions along with
the programmable compensation settings. The Analog
Devices LTpowerCAD tool is available for transient and
stability analysis, and experienced users who prefer to
adjust the module’s feedback loop compensation param-
eters can use this tool.
The LTM4681 contains two dual internal constant fre-
quency current mode control buck regulators (channel 0
and channel 1, and channel 2 and 3) and whose power
MOSFETs are capable of fast switching speed. Reference to
the signal pins will be Name_nn, where n is either 01 or 23,
or with namen when referring to signal pins that are related
to the actual channel. The factory NVM-default switching
frequency clocks SYNC_nn at 350kHz, to which the regu-
lators synchronize their switching frequency. The default
phase-interleaving angle between the channels is 180°. A
pin-strapping resistor on FSWPH_nn_CFG configures the
frequency of the SYNC_nn clock (switching frequency) and
the channel phase relationship of the channels to each other
and with respect to the falling edge of the SYNC_nn sig-
nal. (Most possible combinations of switching frequency
and phase-angle assignments are settleable by resistor
pin programming; see Table 3. Configure the LTM4681’s
NVM to implement settings not available by resistor-pin
strapping.) When a FSWPH_nn_CFG pin-strap resistor
sets the channel phase relationship of the LTM4681’s
channels, the SYNC_nn clock is not driven by the module;
instead, SYNC_nn becomes strictly a high impedance input
and channel switching frequency is then synchronized to
SYNC_nn provided by an externally-generated clock or sib-
POWER-UP AND INITIALIZATION
The LTM4681 is designed to provide standalone supply
sequencing and controlled turn-on and turn-off operation.
It operates from a single input supply (4.5V to 16V) while
three on-chip linear regulators generate internal 2.5V, 3.3V
and 5.5V per controller. If V
does not exceed 6V, and
INnn
the V
pin is turned off, the INTV , V
and SV
BIAS
CC INnn IN_nn
pins must be tied together. The controller configuration
is initialized by an internal threshold based UVLO where
V
INnn
must be approximately 4V and the 5.5V, 3.3V and
2.5V linear regulators must be within approximately 20%
of the regulated values. In addition to the power supply, a
PMBus RESTORE_USER_ALL or MFR_RESET command
can initialize the part too.
The V
pin is the output of an internal 5.5V buck regu-
BIAS
lator to improve efficiency of the circuit and minimize
power loss on the LTM4681. The V pin must exceed
BIAS
approximately 4.8V, and V must exceed 7V before the
IN
INTV LDO operates from the V
pin. The V
regu-
CC
BIAS
BIAS
ling LTM4681 with pull-up resistor to V
. Switching
frequency and phase relationship canDbDe33a_lntnered via the
lator is powered from V
and enabled with RUNP.
IN_VBIAS
2
I C interface, but only when switching action is off, i.e.,
During initialization, the external configuration resistors
are identified and/or contents of the NVM are read into the
controller’s commands and the power train is held off. The
RUNn and FAULTn and PGOODn are held low. The LTM4681
will use the contents of Table 1 thru Table 5 to determine the
resistor defined parameters. See the Resistor Configuration
section for more details. The resistor configuration pins
only control some of the preset values of the controller.
when the module is not regulating the outputs. See the
Applications Information section for details.
Programmable analog feedback loop compensation for
channel 0 to channel 3 is accomplished with a capaci-
tor connection from COMPna to SGND, and a capacitor
from COMPnb to SGND.) The COMPnb pin is for the
high frequency gain roll off and is the g amplifier out-
put that has a programmable range, and the COMPna
m
Rev. 0
30
For more information www.analog.com
LTM4681
OPERATION
The remaining values are programmed in NVM either at the
factory or by the user.
After the RUNn pins release and prior to entering a constant
output voltage regulation state, the LTM4681 performs a
monotonic initial ramp or “soft-start”. Soft-start is per-
formed by actively regulating the load voltage while digi-
tally ramping the target voltage from 0V to the commanded
voltage set-point. Once the LTM4681 is commanded to turn
on (after power up and initialization), the controller waits for
the user specified turn-on delay (TON_DELAY) prior to ini-
tiating this output voltage ramp. The rise time of the voltage
ramp can be programmed using the TON_RISE command
to minimize inrush currents associated with the start-up
voltage ramp. The soft-start feature is disabled by setting
the value of TON_RISE to any value less than 0.25ms. The
LTM4681 PWM always uses discontinuous mode during
the TON_RISE operation. In discontinuous mode, the bot-
tom MOSFET is turned off as soon as reverse current is
detected in the inductor. This will allow the regulator to start
up into a pre-biased load. When the TON_MAX_FAULT_
LIMIT is reached, the part transitions to continuous mode, if
so programmed. If TON_MAX_FAULT_LIMIT is set to zero,
there is no time limit and the part transitions to the desired
If the configuration resistors are not inserted or if the
ignore RCONFIG bit is asserted (bit 6 of the MFR_
CONFIG_ALL configuration command), the LTM4681
will use only the contents of NVM to determine the DC/
DC characteristics. The ASEL_nn value read at power-up
or reset is always respected unless the pin is open. The
ASEL_nn will set the bottom 4LSBs and the MSBs are
set by NVM. See the Applications Information section for
more details.
After the part has initialized, an additional comparator
monitors VIN through the SVIN_nn pins. The VIN_ON
threshold must be exceeded before the output power
sequencing can begin. After VIN is initially applied, the
part will typically require 30ms to initialize and begin the
TON_DELAY timer. The readback of voltages and currents
may require an additional 0ms to 90ms.
SOFT-START
conduction mode after TON_RISE completes and V
OUTn
The method of start-up sequencing described below is
time-based. The part must enter the run state prior to soft-
start. The run pins are released by the LTM4681 after the
has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC
is not present. However, setting TON_MAX_FAULT_LIMIT
to a value of 0 is not recommended.
part is initialized and SV
is greater than the VIN_ON
IN_nn
threshold. If multiple LTM4681s are used in an application,
they all hold their respective run pins low until all devices
TIME-BASED SEQUENCING
are initialized and SV
exceeds the VIN_ON threshold
The default mode for sequencing the outputs on and off
is time-based. Each output is enabled after waiting TON_
DELAY amount of time following either a RUN pin going
high, a PMBus command to turn on or the VIN rising above
a preprogrammed voltage. Off sequencing is handled in a
similar way. To assure proper sequencing, make sure all
ICs connect the SHARE_CLK_nn pin together and RUNn
pins together. If the RUNn pins cannot be connected
together for some reasons, set bit 2 of MFR_CHAN_
CONFIG to 1. This bit requires the SHARE_CLK_nn pin
to be clocking before the power supply output can start.
When the RUNn pin is pulled low, the LTM4681 will hold
the pin low for the MFR_ RESTART_DELAY. The minimum
MFR_RESTART_ DELAY is TOFF_DELAY + TOFF_FALL +
136ms. This delay assures proper sequencing of all rails.
The LTM4681 calculates this delay internally and will not
IN_nn
for every device. The SHARE_CLK_nn pin assures all the
devices connected to the signal use the same time base.
The SHARE_CLK_nn pin is held low until the part has been
initialized after V is applied. The LTM4681 can be set to
IN
turn-off (or remain off) if SHARE_CLK_nn is low (set bit
2 of MFR_CHAN_CONFIG to 1). This allows the user to
assure synchronization across numerous LTC® devices
even if the RUNn pins cannot be connected together due
to board constraints. In general, if the user cares about
synchronization between chips it is best not only to con-
nect all the respective RUNn pins together but also to
connect all the respective SHARE_CLK_nn pins together
and pulled up to VDD33_nn with a 10k resistor. This assures
all chips begin sequencing at the same time and use the
same time base.
process a shorter delay. However, a longer commanded
Rev. 0
31
For more information www.analog.com
LTM4681
OPERATION
MFR_RESTART_DELAY can be used by the part. The maxi-
mum allowed value is 65.52 seconds.
or FAULT pulled low externally (if the MFR_FAULT_
RESPONSE is set to inhibit). Under these conditions, the
power stage is disabled in order to stop the transfer of
energy to the load as quickly as possible. The shutdown
state can be entered from the soft-start or active regula-
tion states or through user intervention.
VOLTAGE-BASED SEQUENCING
The sequence can also be voltage-based. As shown
in Figure 4, The PGOODn pin is asserted when the UV
threshold is exceeded for each output. It is possible to
feed the PGOODn pin from one LTM4681 channel into the
RUNn pin of the next LTM4681 channel in the sequence,
especially across multiple LTM4681s. The PGOODn has
There are two ways to respond to faults; which are retry
mode and latched off mode. In retry mode, the controller
responds to a fault by shutting down and entering the inac
-
tive state for a programmable delay time (MFR_RETRY_
DELAY). This delay minimizes the duty cycle associated
with autonomous retries if the fault that causes the shut-
down disappears once the output is disabled. The retry
delay time is determined by the longer of the MFR_RETRY_
DELAY command or the time required for the regulated
output to decay below 12.5% of the programmed value.
If multiple outputs are controlled by the same FAULTn
pin, the decay time of the faulted output determines the
retry delay. If the natural decay time of the output is too
long, it is possible to remove the voltage requirement of
the MFR_RETRY_DELAY command by asserting bit 0
of MFR_CHAN_CONFIG. Alternatively, latched off mode
means the controller remains latched-off following a fault
and clearing requires user intervention such as toggling
RUNn or commanding the part OFF then ON.
a 100µs filter. If the V
voltage bounces around the UV
threshold for a longOpUeTrniod of time it is possible for the
PGOODn output to toggle more than once. To minimize
this problem, set the TON_RISE time under 100ms.
If a fault in the string of rails is detected, only the faulted
rail and downstream rails will fault off. The rails in the
string of devices in front of the faulted rail will remain on
unless commanded off.
Rꢉꢊ0
ꢋꢌꢍꢍꢎ0
ꢐꢁꢑRꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢆꢇꢈ
Rꢉꢊꢆ
ꢋꢌꢍꢍꢎꢆ
Rꢉꢊꢈ
Rꢉꢊꢏ
ꢋꢌꢍꢍꢎꢈ
ꢋꢌꢍꢍꢎꢏ
ꢀꢁꢂꢃꢄꢅꢆ
ꢆꢇꢈ
LIGHT-LOAD CURRENT OPERATION
ꢃꢄꢅꢆ ꢒ0ꢃ
ꢁꢍ ꢊꢓꢔꢁ ꢕꢖꢑꢊꢊꢓꢀ
ꢗꢊ ꢁꢖꢓ ꢐꢓꢘꢉꢓꢊꢕꢓ
The LTM4681 has two modes of operation: high efficiency
discontinuous conduction mode or forced continuous
conduction mode. Mode selection is done using the
MFR_PWM _MODE command (discontinuous conduc-
tion is always the start-up mode, forced continuous is the
default running mode).
Figure 4. Event (Voltage) Based Sequencing
SHUTDOWN
The LTM4681 supports two shutdown modes. The first
mode is closed-loop shutdown response, with user
defined turn-off delay (TOFF_DELAY) and ramp down rate
(TOFF_FALL). The controller will maintain the mode of
operation for TOFF_FALL. The second mode is discontinu-
ous conduction mode, the controller will not draw current
from the load and the fall time will be set by the output
capacitance and load current, instead of TOFF_FALL.
If a controller is enabled for discontinuous operation, the
inductor current is not allowed to reverse. The reverse
current comparator’s output turns off the bottom MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative.
In forced continuous operation, the inductor current
is allowed to reverse at light loads or under large tran-
sient conditions. The peak inductor current is determined
solely by the voltage on the COMPn pins. In this mode,
The shutdown occurs in response to a fault condition or
loss of SHARE_CLK_nn (if bit 2 of MFR_CHAN_ CONFIG
is set to a 1) or VINnn falling below the VIN_OFF threshold
Rev. 0
32
For more information www.analog.com
LTM4681
OPERATION
the efficiency at light loads is lower than in discontinuous
mode operation. However, continuous mode exhibits lower
output ripple and less interference with audio circuitry, but
may result in reverse inductor current, which can cause
the input supply to boost. The VIN_OV_FAULT_LIMIT can
detect this and turn off the offending channel. However,
be set from EEPROM or external configuration resistors
as outlined in Table 3. Designated phase is the relation-
ship between the falling edge of SYNC and the internal
clock edge that sets the PWM latch to turn on the top
power switch. Additional small propagation delays to the
PWM control pins will also apply. Both channels must be
off before the FREQUENCY_SWITCH and MFR_PWM_
CONFIG commands can be written to the LTM4681.
this fault is based on an ADC read and can take up to t
CON-
to detect. If there is a concern about the input supply
VERT
boosting, keep the part in discontinuous conduction mode.
The phase relationships and frequency options provide for
numerous application options. Multiple LTM4681 mod-
ules can be synchronized to realize a PolyPhase array.
In this case the phases should be separated by 360/n
degrees, where n is the number of phases driving the
output voltage rail.
If the part is set to discontinuous mode operation, as
the inductor average current increases, the controller will
automatically modify the operation from discontinuous
mode to continuous mode.
SWITCHING FREQUENCY AND PHASE
PWM LOOP COMPENSATION
The switching frequency of the PWM can be established
with an internal oscillator or an external time base. The
internal phase-locked loop (PLL) synchronizes the PWM
control to this timing reference with proper phase relation,
whether the clock is provided internally or externally. The
device can also be configured to provide the master clock
to other devices through PMBus command, NVM setting,
or external configuration resistors as outlined in Table 3.
The internal PWM loop compensation resistors R
of the LTM4681 can be adjusted using bit[4:0]CoOfMtPhnea
MFR_PWM_COMP command for each controller.
The transconductance (gm) of the LTM4681 PWM error
amplifier can be adjusted using bit[7:5] of the MFR_
PWM_COMP command. These two loop compensation
parameters can be programmed when device is in opera-
tion. Refer to the Programmable Loop Compensation sub-
section in the Applications Information section for further
details.
As clock master, the LTM4681 will drive its open-drain
SYNC_nn pin at the selected rate with a pulse width of
500ns. An external pull-up resistor between SYNC_nn
and V
is required in this case. Only one device
DD33_nn
connected to SYNC_nn should be designated to drive the
pin. The LTM4681 will automatically revert to an external
SYNC_nn input, disabling its own SYNC_nn, as long as
the external SYNC_nn frequency is greater than 80% of
the programmed SYNC_nn frequency. The external SYNC
input shall have a duty cycle between 20% and 80%.
OUTPUT VOLTAGE SENSING
All four channels in LTM4681 have differential amplifi-
ers, which allow the remote sensing of the load voltage
+
–
between V and V pins. The telemetry ADC is also fully
+
–
differential and makes measurements between V
OSNSn
+
and V
-voltages for both channels at the V and V
OSNSn
Whether configured to drive SYNC_nn or not, the LTM4681
can continue PWM operation using its own internal oscil-
lator if an external clock signal is subsequently lost.
pins, respectively. The maximum allowed 3.6V, but the
LTM4681 design is limited to 3.3V.
The device can also be programmed to always require an
external oscillator for PWM operation by setting bit 4 of
MFR_CONFIG_ALL. The status of the SYNC driver circuit
is indicated by bit 10 of MFR_PADS.
INTV /V
POWER
CC BIAS
Power for the internal top and bottom MOSFET drivers and
most other internal circuitry is derived from the INTV
CC
BIAS
CC
pin. When the RUNP pin is shorted to GND and the V
The MFR_PWM_CONFIG command can be used to con-
figure the phase of each channel. Desired phase can also
is off, an internal 5.5V linear regulator supplies INTV
Rev. 0
33
For more information www.analog.com
LTM4681
OPERATION
power from SV . If V
IN_nn
is on at 5.5V output and V
limit circuit to maintain an essentially constant current
limit with temperature. The current sensed is then digitized
by the LTM4681’s telemetry ADC with an input range of
BIAS IN
is higher than 7.0V, the 5.5V regulator is turned off and
an internal switch is turned on, connecting V . Using
BIAS
the V
allows the INTV power to be derived from a
128mV, a noise floor of 7µV
, and a peak-peak noise of
BIAS
CC
RMS
high efficiency internal source. V
can provide power
approximately 46.5µV. The LTM4681 computes the induc-
tor current using the DCR value stored in the IOUT_CAL_
GAIN command and the temperature coefficient stored in
command MFR_IOUT_CAL_GAIN_TC. The resulting cur-
rent value is returned by the READ_IOUT command.
BIAS
to the internal 3.3V linear regulators when V is present,
IN
which allows the LTM4681 controllers to be initialized and
programmed even with channels off.
The INTV
regulator is powered from the SV
pin,
.
the poweCrCt_hnrnough the IC is equal to SV
• I
IN_nn
IN_nn INTVCCnn
INPUT CURRENT SENSING
The gate charge current is dependent on operating fre-
quency. The INTV
regulator can supply up to 100mA,
and the typical ICNCT_VnnCC_nn current for the LTM4681 is
~50mA. A 12V input voltage would equate to a difference
of 7V per controller drop across the internal controller,
when multiplied by 50mA equals a 350mW power loss.
This loss can be eliminated by ultilizing the VBIAS regulator.
To sense the total input current consumed by the
LTM4681’s power stages , a sense resistor is placed
between the supply voltage and the drain of the top
+
–
N-channel MOSFET. The I
and I
pins are con-
IN_nn
IN_nn
nected to the sense resistor. The filtered voltage is ampli-
fied by the internal high side current sense amplifier and
digitized by the LTM4681’s telemetry ADC. The input cur-
rent sense amplifier has three gain settings of 2x, 4x, and
8x set by the bit[3:2] of the MFR_PWM_CONFIG com-
mand. The maximum input sense voltage for the three
gain settings is 50mV, 25mV, and 10mV respectively. The
LTM4681 computes the input current using the internal
Do not tie INTV
on the LTM4681 to an external sup-
ply because INCTCV_nn will attempt to pull the external
CC_nn
supply high and hit current limit, significantly increasing
the die temperature.
For applications where VIN is 5V, tie the SVIN_nn and
INTVCC_nn pins together to the 5V input through a 1Ω
resistor as shown in Test Circuit 2.
R
value stored in the IIN_CAL_GAIN command. The
SENSE
resulting measured power stage current is returned by
+
–
the READ_IIN command. I
1 (channel 0 and 1), and I
(channel 2 and 3).
, I
for controller
IN_01
IN_01
+
–
OUTPUT CURRENT SENSING AND SUB MILLIOHM
DCR CURRENT SENSING
, I
for controller 2
IN_23
IN_23
The LTM4681 use a unique sub-milliohm inductor cur-
rent sensing technique that provides a high level signal
to noise ratio while sensing very low signals in current
mode operation. This enables higher conversion efficien-
cies with the use of the internal sub-milliohm inductors in
heavy load applications. The current limit threshold can
be accurately set with the MFR_PWM_MODE[7] for High
and Low range (see page 97).
The LTM4681 uses a 1Ω resistor to measure the SV
IN_nn
pin supply current being consumed by each LTM4681
internal controller. This value is returned by the MFR_
READ_ICHIP command. The chip current is calculated by
using the 1Ω value stored in the MFR_ICHIP_CAL_GAIN
command. Refer to the subsection titled Input Current
Sense Amplifier in the Applications Information section
for further details.
The internal DCR sensing network, thus current limit are
calculated based on the DCR of the inductor at room tem-
perature. The DCR of the inductor has a large temperature
coefficient, approximately 3900ppm/°C. The temperature
coefficient of the inductor is written to the MFR_IOUT_
CAL_GAIN_TC register. The external temperature is sensed
near the inductor and used to modify the internal current
PolyPhase LOAD SHARING
Multiple LTM4681s can be arrayed in order to provide a
balanced load-share solution by bussing the necessary
pins. Figure 50 illustrates a 8-Phase design sharing con-
nections required for load sharing.
Rev. 0
34
For more information www.analog.com
LTM4681
OPERATION
If an external oscillator is not provided, the SYNC_nn pins
should only be enabled on one of the LTM4681s con-
trollers. The other(s) should be programmed to disable
SYNC_nn controllers using bit 4 of MFR_CONFIG_ALL. If
an external oscillator is present, the chip with the SYNC_
nn pin enabled will detect the presence of the external
clock and disable its output.
The VOUTn_CFG pin settings are described in Table 1.
These pins set the LTM4681 VOUT0 to VOUT3 output voltage
coarse settings. If the pin is open, the VOUT_COMMAND
command is loaded from NVM to determine the output
voltage. The default setting is to have the switcher off
unless the voltage configuration pins are installed. The
VTRIMn_CFG pins in Table 2 are used to set the output
voltage fine adjustment setting. Both combine to offer
several distinct output voltages.
+
Multiple channels need to tie all the V
pins together,
and all the V
– pins together, OCSNSn and C
pins togetheOrSaNsSnwell. Do not assert bit[4] of MFR_
The following parameters are set as a percentage of the
output voltage if the RCONFIG pins are used to determine
the output voltage:
OMPna
OMPnb
CONFIG_ALL except in a PolyPhase® application.
The user must share the SYNC_nn, SHARE_CLK_nn,
FAULTn, and ALERTn pins of these parts. Be sure to use
pull-up resistors on SYNC_nn, FAULTn, SHARE_CLK_nn
and ALERTn. See Application figures.
n
VOUT_OV_FAULT_LIMIT....................................+10%
n
VOUT_OV_WARN_LIMIT....................................+7.5%
n
VOUT_MAX.........................................................+7.5%
n
VOUT_MARGIN_HIGH........................................+5%
n
VOUT_MARGIN_LOW.........................................–5%
INTERNAL TEMPERATURE SENSE
n
VOUT_UV_FAULT_LIMIT....................................–7%
Temperature is measured using the internal diode-con-
nected PNP transistors, and the outputs are connected to
TSNS0 to TSNS3 pins corresponding to channel 0 to 3.
These outputs are used for testing. Two different currents
are applied to the diode (nominally 2µA and 32µA) and
The FSWPH_CFG_nn pin settings are described in Table 3.
This pin selects the switching frequency and phase of each
channel. The phase relationships between the two channels
and SYNC_nn pin are determined in Table 3. To synchronize
to an external clock, the part should be put into external
clock mode (SYNC_nn output disabled but frequency set to
the nominal value). If no external clock is supplied, the part
will clock at the programmed frequency. If the application
is multiphase and the SYNC_nn signal between chips is
lost, the parts will not operate at the designed phase even if
they are programmed and trimmed to the same frequency.
the temperature is calculated from a ∆V measurement
BE
made with the internal 16-bit monitor ADC (see Figure 2
Block Diagram).
The LTM4681 will only implement ∆VBE temperature
sensing, therefore MFR_PWM_MODE bit[5] is reserved.
RCONFIG (RESISTOR CONFIGURATION) PINS
This may increase the ripple voltage on the output, possi-
bly produce undesirable operation. If the external SYNC_nn
signal is being generated internally and external SYNC_nn
is not selected, bit 10 of MFR_PADS will be asserted. If no
frequency is selected and the external SYNC_nn frequency
is not present, a PLL_FAULT will occur. If the user does not
wish to see the ALERT from a PLL_FAULT even if there is not
a valid synchronization signal at power-up, the ALERT mask
for PLL_FAULT must be written. See the description on
SMBALERT_MASK for more details. If the SYNC_nn pin is
connected between multiple ICs only one of the ICs should
have the SYNC_nn pin enabled using the MFR_CONFIG_
ALL[4] = 0, and all other ICs should be configured to have
There are twelve input pins utilizing 1% resistors between
these pins to select key operating parameters. The pins are
ASEL_01, ASEL_23, FSWPH_01_CFG, FSWPH_23_CFG,
VOUT0_CFG, VOUT1_CFG, VOUT2_CFG, VOUT3_CFG,
VTRIM0_CFG, VTRIM1_CFG, VTRIM2_CFG, VTRIM3_CFG.
If pins are floated, the value stored in the corresponding
NVM command is used. If bit 6 of the MFR_CONFIG_ALL
configuration command is asserted in NVM, the resistor
input is ignored upon power-up except for ASEL which is
always respected. The resistor configuration pins are only
measured during a power-up reset or after a MFR_RESET
or after a RESTORE_USER_ALL command is executed.
the SYNC pin disabled with MFR_CONFIG_ALL[4] = 1.
Rev. 0
35
For more information www.analog.com
LTM4681
OPERATION
The ASEL_nn pin settings are described in Table 4. ASEL_
nn selects slave address for the LTM4681 internal control-
ler. For more detail, refer to Table 5.
Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the
LTM4681’s Output Voltage, Fine Adjustment Setting (Not
Applicable if MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k
R
*
V
TRIM
(mV) FINE ADJUSTMENT TO V
SETTING WHEN RESPECTIVE
VTRIMn_CFG
(kΩ)
OUTn
NOTE: Per the PMBus specification, pin programmed
parameters can be overridden by commands from the
digital interface with the exception of ASEL_nn which is
always honored. Do not set any part address to 0x5A or
0x5B because these are global addresses and all parts
will respond to them.
Open
32.4
22.6
18.0
15.4
12.7
10.7
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
0
99
86.625
74.25
61.875
49.5
Table 1. VOUTn _CFG Pin Strapping Look-Up Table for the
LTM4681’s Output Voltage, Coarse Setting (Not Applicable if
MFR_CONFIG_ALL[6] = 1b) Top Resistor = 14.3k
37.125
24.75
12.375
–12.375
–24.75
–37.125
–49.5
R
*
V
(V)
MFR_PWM_
MODEn[1] BIT
VOUTn_CFG
(kΩ)
OUTn
SETTING COARSE
Open
32.4
22.6
18.0
15.4
12.7
10.7
NVM
NVM
3.3
NVM
NVM
0
0
0
0
3.1
–61.875
–74.25
–86.625
–99
2.9
2.7
2.5
0, if V
1, if V
> 0mV
≤ 0mV
TRIMn
TRIMn
*R
value indicated is nominal. Select R
from a
VTRIMn_CFG
VTRIMn_CFG
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
1
1
1
1
1
1
1
1
1
1
resistor vendor such that its value is always within 3% of the value
indicated in the table. Take into account resistor initial tolerance, T.C.R. and
resistor operating temperatures, soldering heat/IR reflow, and endurance
of the resistor over its lifetime. Thermal shock/cycling, moisture (humidity)
and other effects (depending on one’s specific application) could also
affect R ’s value over time. All such effects must be taken into
VTRIMn_CFG
account in order for resistor pin strapping to yield the expected result
at every SV power-up and/or every execution of MFR_RESET, or
IN_nn
RESTORE_USER_ALL over the lifetime of one’s product. R = 14.3k is
TOP
external to the part.
Example:
*R
VOUTn_CFG
value indicated is nominal. Select R
from a resistor
VOUTn_CFG
ꢐ
ꢏꢏꢑꢒ
vendor such that its value is always within 3% of the value indicated in the
table. Take into account resistor initial tolerance, T.C.R. and resistor operating
temperatures, soldering heat/IR reflow, and endurance of the resistor over its
lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending
ꢀꢁ.ꢂꢃ
ꢐ
ꢇꢈꢉꢊ
ꢄRꢅꢆn
R
ꢇꢈꢉꢊ ꢋꢌꢄ
ꢄRꢅꢆ
on one’s specific application) could also affect R ’s value over time.
VOUTn_CFG
All such effects must be taken into account in order for resistor pin strapping
ꢍꢊꢎꢏꢇnn
to yield the expected result at every SV power-up and/or every execution of
IN
MFR_RESET or RESTORE_ USER_ALL, over the lifetime of one’s product.
R
TOP
= 14.3k is external to the part. Example:
ꢇ
ꢏꢏꢐꢑꢉnn
R
ꢀꢁꢂ
ꢃꢄ.ꢅꢆ
ꢇ
ꢁꢈꢀn
ꢉꢊꢋꢌ
R ꢉꢊꢋꢌ
ꢇꢁꢈꢀn
ꢍꢌꢎꢏꢉnn
Rev. 0
36
For more information www.analog.com
LTM4681
OPERATION
Table 3. FSWPH_nn_CFG Pin Strapping Look-Up Table to Set the LTM4681’s Switching Frequency and Channel Phase-Interleaving
Angle (Not Applicable if MFR_CONFIG_ALL[6] = 1b), nn = 0,1 or 2,3 Channels, set top resistor to 14.3k.
R
*
SWITCHING
FREQUENCY (kHz)
bits [2:0] of
MFR_PWM_CONFIG
bit [4] of
MFR_CONFIG_ALL
FSWPH_CFG
(kΩ)
θSYNC TO θ0
θSYNC TO θ1
NVM; LTM4681
Default = 500
NVM; LTM4681
Default = 0°
NVM; LTM4681
Default = 180°
NVM; LTM4681
Default = 000b
NVM; LTM4681
Default = 0b
Open
32.4
22.6
18.0
15.4
12.7
10.7
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
250
350
0°
0°
180°
180°
180°
180°
180°
180°
240°
270°
240°
120°
240°
300°
270°
180°
240°
000b
000b
000b
000b
000b
000b
100b
001b
010b
011b
101b
110b
001b
000b
100b
0b
0b
0b
0b
0b
0b
0b
0b
1b
1b
1b
1b
1b
1b
1b
425
0°
575
0°
650
0°
750
0°
500
120°
90°
0°
500
External**
External**
External**
External**
External**
External**
External**
0°
60°
120°
90°
0°
120°
*R
value indicated is nominal. Select R
from a resistor vendor such that its value is always within 3% of the value indicated in
FSWPH_nn_CFG
FSWPH_nn_CFG
the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor
over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect R
’s
FSWPH_nn_CFG
value over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every SV power-up and/or
IN
every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.
**External setting corresponds to FREQUENCY_SWITCH (Register 0x33) value set to 0x0000; the device synchronizes its switching frequency to that of
the clock provided on the SYNC_nn pin, provided MFR_CONFIG_ALL[4] = 1b. R = 14.3k is external to the part.
TOP
Example:
ꢄ
ꢅꢅꢆꢇ
ꢀꢁ.ꢂꢃ
ꢈꢉꢊꢋꢌꢍnnꢍꢎꢈꢏ ꢋꢓꢔ
ꢎꢈꢏ ꢐꢑꢒ
R
ꢈꢉꢊꢋꢌꢍ
Rev. 0
37
For more information www.analog.com
LTM4681
OPERATION
Table 4. ASEL_nn Pin Strapping Look-Up Table to Set the
LTM4681’s Slave Address (Applicable Regardless of
MFR_CONFIG_ALL[6] Setting)
Table 5. LTM4681 MFR_ADDRESS Command Examples
Expressed in 7- and 8-Bit Addressing
HEX DEVICE
ADDRESS
BIT
R * (kΩ)
ASEL
SLAVE ADDRESS
100_1111_R/W
100_1111_R/W
100_1110_R/W
100_1101_R/W
100_1100_R/W
100_1011_R/W
100_1010_R/W
100_1001_R/W
100_1000_R/W
100_0111_R/W
100_0110_R/W
100_0101_R/W
100_0100_R/W
100_0011_R/W
100_0010_R/W
100_0001_R/W
100_0000_R/W
DESCRIPTION
7-BIT
8-BIT
0xB4
0xB6
0x9E
0x80
0x82
7
0
0
0
0
0
1
6
1
1
1
1
1
0
5
0
0
0
0
0
0
4
1
1
0
0
0
0
3
2
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
R/W
0
Open
4
Rail
0x5A
0x5B
0x4F
0x40
0x41
1
1
1
0
0
0
32.4
22.6
18.0
15.4
12.7
10.7
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
4
Global
0
Default
0
Example 1
Example 2
0
0
2,3
Disabled
0
Note 1: This table can be applied to the MFR_RAIL_ADDRESSn
commands, but not the MFR_ADDRESS command.
Note 2: A disabled value in one command does not disable the device,
nor does it disable the global address.
Note 3: A disabled value in one command does not inhibit the device
from responding to device addresses specified in other commands.
Note 4: It is not recommended to write the value 0x00, 0x0C (7-bit), 0x5A
(7-bit), 0x5B (7-bit) or 0x7C(7-bit) to the MFR_CHANNEL_ADDRESSn or
the MFR_RAIL_ADDRESSn commands.
FAULT DETECTION AND HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
Where:
R/W = Read/Write bit in control byte
All PMBus device addresses listed in the specification are 7 bits wide
unless otherwise noted.
n
Input OV FAULT Protection and UV Warning
Note: The LTM4681 will always respond to slave address 0x5A and 0x5B
regardless of the NVM or ASEL resistor configuration values.
n
Average Input OC Warn
*R
value indicated is nominal. Select R
from a resistor vendor
CFG
CFG
n
such that its value is always within 3% of the value indicated in the table.
Take into account resistor initial tolerance, T.C.R. and resistor operating
temperatures, soldering heat/IR reflow, and endurance of the resistor
over its lifetime. Thermal shock cycling, moisture (humidity) and other
Output OV/UV Fault and Warn Protection
n
Output OC Fault and Warn Protection
n
Internal control Die and Internal Module
Overtemperature Fault and Warn Protection
effects (depending on one’s specific application) could also affect R ’s
value over time. All such effects must be taken into account in order for
resistor pin-strapping to yield the expected result at every SV power-up
and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the
lifetime of one’s product.
CFG
IN
n
Internal Undertemperature Fault and Warn Protection
n
CML Fault (Communication, Memory or Logic)
Example:
n
External Fault Detection via the Bidirectional FAULTn
Pins
ꢇꢀꢈꢉꢄnn ꢊꢋꢂ
R
ꢇꢀꢈꢉ
In addition, the LTM4681 can map any combination of
fault indicators to their respective FAULTn pin using the
propagate FAULTn response commands, MFR_FAULT_
PROPAGATE. Typical usage of a FAULTn pin is as a
driver for an external crowbar device, overtemperature
alert, overvoltage alert or as an interrupt to cause a
ꢀꢁꢂꢃꢄꢅ0ꢄꢅꢆ
Rev. 0
38
For more information www.analog.com
LTM4681
OPERATION
microcontroller to poll the fault commands. Alternatively,
the FAULTn pins can be used as inputs to detect external
faults downstream of the controller that require an imme-
diate response.
In general, any asserted bit in a STATUS_x register also
pulls the ALERT_nn pin low. Once set, ALERT_nn will
remain low until one of the following occurs.
n
A CLEAR_FAULTS or MFR_RESET Command Is
Issued
Any fault or warning event will always cause the ALERT_nn
pin to assert low unless the fault or warning is masked by
the SMBALERT_MASK. The pin will remain asserted low
until the CLEAR_FAULTS command is issued, the fault bit
is written to a 1 or bias power is cycled or a MFR_RESET
command is issued, or the RUNn pins are toggled OFF/
ON or the part is commanded OFF/ON via PMBus or an
ARA command operation is performed. The MFR_FAULT_
PROPAGATE command determines if the FAULTn pins are
pulled low when a fault is detected.
n
The Related Status Bit Is Written to a One
n
The Faulted Channel Is Properly Commanded Off and
Back On
n
The LTM4681 Successfully Transmits Its Address
During a PMBus ARA
n
Bias Power Is Cycled
With some exceptions, the SMBALERT_MASK command
can be used to prevent the LTM4681 from asserting
ALERT_nn for bits in these registers on a bit-by-bit basis.
These mask settings are promoted to STATUS_WORD
and STATUS_BYTE in the same fashion as the status bits
themselves. For example, if ALERT_nn is masked for all
bits in channel n STATUS_VOUT, then ALERT_nn is effec-
tively masked for the VOUT bit in STATUS_WORD for PAGE
n. The BUSY bit in STATUS_BYTE also asserts ALERT_nn
low and cannot be masked. This bit can be set as a result
of various internal interactions with PMBus communi-
cation. This fault occurs when a command is received
that cannot be safely executed with one or both channels
enabled. As discussed in the Application Information,
BUSY faults can be avoided by polling MFR_COMMON
before executing some commands.
Output and input fault event handling is controlled by the
corresponding fault response byte as specified in Table 14
thru Table 18. Shutdown recovery from these types of
faults can either be autonomous or latched. For autono-
mous recovery, the faults are not latched, so if the fault
conditions not present after the retry interval has elapsed,
a new soft-start is attempted.
If the fault persists, the controller will continue to retry.
The retry interval is specified by the MFR_RETRY_DELAY
command and prevents damage to the regulator com-
ponents by repetitive power cycling, assuming the fault
condition itself is not immediately destructive. The MFR_
RETRY_DELAY must be greater than 120ms. It can not
exceed 83.88 seconds.
If masked faults occur immediately after power up,
ALERT_nn may still be pulled low because there has not
been time to retrieve all of the programmed masking
information from EEPROM.
Status Registers and ALERT Masking
Figure 5 summarizes the internal LTM4681 status regis-
ters accessible by PMBus command. These contain indi-
cation of various faults, warnings and other important
operating conditions. As shown, the STATUS_BYTE and
STATUS_WORD commands also summarize contents of
other status registers. Refer to PMBus Command Details
for specific information.
Status information contained in MFR_COMMON and
MFR_PADS can be used to further debug or clarify the
contents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the ALERT_nn pin and may not directly influence bits
in STATUS_BYTE or STATUS_WORD.
NONE OF THE ABOVE in the STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
Rev. 0
39
For more information www.analog.com
LTM4681
OPERATION
STATUS_VOUT*
STATUS_WORD
ꢇꢈ ꢐꢑꢗꢬ
ꢇꢉ ꢛꢑꢗꢬ
ꢇꢊ ꢛꢡꢁꢗꢬ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢐꢑꢗꢬꢪꢑꢐ ꢒꢓꢔꢕꢖ
ꢐꢑꢗꢬꢪꢑꢐ ꢩꢓꢘꢜꢝꢜꢮ
ꢐꢑꢗꢬꢪꢗꢐ ꢩꢓꢘꢜꢝꢜꢮ
ꢐꢑꢗꢬꢪꢗꢐ ꢒꢓꢔꢕꢖ
ꢐꢑꢗꢬꢪꢭꢂꢵ ꢩꢓꢘꢜꢝꢜꢮ
ꢬꢑꢡꢪꢭꢂꢵ ꢒꢓꢔꢕꢖ
ꢬꢑꢒꢒꢪꢭꢂꢵ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
STATUS_INPUT
ꢐꢛꢡꢪꢑꢐ ꢒꢓꢔꢕꢖ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢐꢛꢡꢪꢗꢐ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢗꢜꢝꢖ ꢑꢹꢹ ꢹꢢꢘ ꢛꢜꢚꢔꢹꢹꢣꢝeꢜꢖ ꢐꢛꢡ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢇꢋ ꢭꢒRꢪꢟꢁꢄꢞꢛꢒꢛꢞ
ꢇꢇ ꢁꢑꢩꢄRꢪꢃꢑꢑꢅꢸ
ꢇ0 ꢀꢘeꢓꢙꢚ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢌ
ꢍ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
STATUS_BYTE
ꢀꢁꢂꢃꢄꢅꢆ
ꢛꢛꢡꢪꢑꢞ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢱꢗꢟꢠ
ꢑꢒꢒ
ꢐꢑꢗꢬꢪꢑꢐ
ꢛꢑꢗꢬꢪꢑꢞ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢬꢄꢭꢁꢄRꢂꢬꢗRꢄ
ꢞꢭꢫ
ꢡꢑꢡꢄ ꢑꢒ ꢬꢳꢄ ꢂꢱꢑꢐꢄ
STATUS_IOUT
STATUS_MFR_SPECIFIC
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢛꢑꢗꢬꢪꢑꢞ ꢒꢓꢔꢕꢖ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢛꢑꢗꢬꢪꢑꢞ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢛꢜꢖeꢘꢜꢓꢕ ꢬeꢷꢰeꢘꢓꢖꢔꢘe ꢒꢓꢔꢕꢖ
ꢛꢜꢖeꢘꢜꢓꢕ ꢬeꢷꢰeꢘꢓꢖꢔꢘe ꢩꢓꢘꢜꢝꢜꢮ
ꢄꢄꢁRꢑꢭ ꢞRꢞ ꢄꢘꢘꢢꢘ
ꢛꢜꢖeꢘꢜꢓꢕ ꢁꢫꢫ ꢗꢜꢕꢢꢣꢤeꢙ
ꢒꢓꢔꢕꢖ ꢫꢢꢮ ꢁꢘeꢚeꢜꢖ
ꢐꢅꢅꢊꢊ ꢗꢐ ꢢꢘ ꢑꢐ ꢒꢓꢔꢕꢖ
ꢐꢑꢗꢬ ꢟꢨꢢꢘꢖ ꢞꢦꢣꢕeꢙ
FAULT ꢁꢔꢕꢕeꢙ ꢫꢢꢯ ꢱꢦ ꢄꢧꢖeꢘꢜꢓꢕ ꢅevꢝꢣe
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
MFR_COMMON
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢞꢨꢝꢰ ꢡꢢꢖ ꢅꢘꢝvꢝꢜꢮ ALERT ꢫꢢꢯ
ꢞꢨꢝꢰ ꢡꢢꢖ ꢱꢔꢚꢦ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢛꢜꢖeꢘꢜꢓꢕ ꢞꢓꢕꢣꢔꢕꢓꢖꢝꢢꢜꢚ ꢡꢢꢖ ꢁeꢜꢙꢝꢜꢮ
ꢑꢔꢖꢰꢔꢖ ꢡꢢꢖ ꢛꢜ ꢬꢘꢓꢜꢚꢝꢖꢝꢢꢜ
ꢄꢄꢁRꢑꢭ ꢛꢜꢝꢖꢝꢓꢕꢝꢲeꢙ
ꢀꢘeꢓꢙꢚ 0ꢆ
STATUS_TEMPERATURE
MFR_PADS
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢑꢬ ꢒꢓꢔꢕꢖ
ꢇꢈ ꢐꢅꢅꢊꢊ ꢑꢐ ꢒꢓꢔꢕꢖ
ꢇꢉ ꢐꢅꢅꢊꢊ ꢗꢐ ꢒꢓꢔꢕꢖ
ꢇꢊ ꢀꢘeꢓꢙꢚ 0ꢆ
ꢇꢋ ꢀꢘeꢓꢙꢚ 0ꢆ
ꢇꢇ ꢛꢜvꢓꢕꢝꢙ ꢂꢅꢞ Reꢚꢔꢕꢖꢀꢚꢆ
ꢇ0 ꢟꢠꢡꢞ ꢞꢕꢢꢣꢤeꢙ ꢥꢦ ꢄꢧꢖeꢘꢜꢓꢕ ꢟꢢꢔꢘꢣe
ꢑꢬ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢗꢬ ꢒꢓꢔꢕꢖ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢟꢳꢂRꢄꢪꢞꢫꢴꢪꢫꢑꢩ
ꢩꢁ ꢁꢝꢜ ꢳꢝꢮꢨ
MFR_INFO
ꢌ
ꢍ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢞꢨꢓꢜꢜeꢕ ꢇ ꢝꢚ ꢁꢑꢩꢄRꢪꢃꢑꢑꢅ
ꢞꢨꢓꢜꢜeꢕ 0 ꢝꢚ ꢁꢑꢩꢄRꢪꢃꢑꢑꢅ
ꢫꢬꢭꢉꢏꢍꢇ ꢒꢢꢘꢣꢝꢜꢮ Rꢗꢡꢇ ꢫꢢꢯ
ꢫꢬꢭꢉꢏꢍꢇ ꢒꢢꢘꢣꢝꢜꢮ Rꢗꢡ0 ꢫꢢꢯ
Rꢗꢡꢇ ꢁꢝꢜ ꢟꢖꢓꢖe
ꢇꢈ Reꢚeꢘveꢙ
ꢇꢉ Reꢚeꢘveꢙ
ꢇꢊ Reꢚeꢘveꢙ
ꢇꢋ Reꢚeꢘveꢙ
ꢇꢇ Reꢚeꢘveꢙ
ꢇ0 Reꢚeꢘveꢙ
ꢀꢁꢂꢃꢄꢅꢆ
STATUS_CML
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢛꢜvꢓꢕꢝꢙꢶꢗꢜꢚꢔꢰꢰꢢꢘꢖeꢙ ꢞꢢꢷꢷꢓꢜꢙ
ꢛꢜvꢓꢕꢝꢙꢶꢗꢜꢚꢔꢰꢰꢢꢘꢖeꢙ ꢅꢓꢖꢓ
ꢁꢓꢣꢤeꢖ ꢄꢘꢘꢢꢘ ꢞꢨeꢣꢤ ꢒꢓꢝꢕeꢙ
ꢭeꢷꢢꢘꢦ ꢒꢓꢔꢕꢖ ꢅeꢖeꢣꢖeꢙ
ꢁꢘꢢꢣeꢚꢚꢢꢘ ꢒꢓꢔꢕꢖ ꢅeꢖeꢣꢖeꢙ
ꢀꢘeꢓꢙꢚ 0ꢆ
Rꢗꢡ0 ꢁꢝꢜ ꢟꢖꢓꢖe
ꢫꢬꢭꢉꢏꢍꢇ ꢒꢢꢘꢣꢝꢜꢮ FAULTn ꢫꢢꢯ
ꢫꢬꢭꢉꢏꢍꢇ ꢒꢢꢘꢣꢝꢜꢮ FAULTn ꢫꢢꢯ
FAULTn ꢁꢝꢜ ꢟꢖꢓꢖe
ꢌ
ꢍ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
ꢄꢄꢁRꢑꢭ ꢄꢞꢞ ꢟꢖꢓꢖꢔꢚ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
FAULTn ꢁꢝꢜ ꢟꢖꢓꢖe
ꢉꢏꢍꢇ ꢒ0ꢈ
ꢑꢖꢨeꢘ ꢞꢢꢷꢷꢔꢜꢝꢣꢓꢖꢝꢢꢜ ꢒꢓꢔꢕꢖ
ꢑꢖꢨeꢘ ꢭeꢷꢢꢘꢦ ꢢꢘ ꢫꢢꢮꢝꢣ ꢒꢓꢔꢕꢖ
Reꢚeꢘveꢙ
DESCRIPTION
MASKABLE GENERATES ALERT BIT CLEARABLE
ꢃeꢜeꢘꢓꢕ ꢒꢓꢔꢕꢖ ꢢꢘ ꢩꢓꢘꢜꢝꢜꢮ ꢄveꢜꢖ
ꢃeꢜeꢘꢓꢕ ꢡꢢꢜꢺꢭꢓꢚꢤꢓꢥꢕe ꢄveꢜꢖ
ꢅꢦꢜꢓꢷꢝꢣ
ꢠeꢚ
ꢡꢢ
ꢡꢢ
ꢡꢢ
ꢠeꢚ
ꢠeꢚ
ꢡꢢ
ꢠeꢚ
ꢠeꢚ
ꢡꢢ
ꢟꢖꢓꢖꢔꢚ ꢅeꢘꢝveꢙ ꢹꢘꢢꢷ ꢑꢖꢨeꢘ ꢱꢝꢖꢚ
ꢡꢢꢖ ꢅꢝꢘeꢣꢖꢕꢦ
ꢡꢢ
Figure 5. LTM4681 Status Register Summary per Controller
Rev. 0
40
For more information www.analog.com
LTM4681
OPERATION
Mapping Faults to FAULTn Pins
repair can be attempted by writing the desired configura-
tion to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
Channel-to-channel fault (including channels from mul-
tiple LTM4681s) dependencies can be created by con-
necting FAULTn pins together. In the event of an internal
fault, one or more of the channels is configured to pull
the bussed FAULTn pins low. The other channels are then
configured to shut down when the FAULTn pins are pulled
low. For autonomous group retry, the faulted channel is
configured to let go of the FAULTn pin(s) after a retry
interval, assuming the original fault has cleared. All the
channels in the group then begin a soft-start sequence. If
the fault response is LATCH_OFF, the FAULTn pin remains
asserted low until either the RUNn pin is toggled OFF/ON
or the part is commanded OFF/ON. The toggling of the
RUNn either by the pin or OFF/ON command will clear
faults associated with the channel. If it is desired to have
all faults cleared when either RUNn pin is toggled or, set
bit 0 of MFR_CONFIG_ALL to a 1.
The LTM4681 manufacturing section of the NVM is mir-
rored. If both copies are corrupted, the “NVM CRC Fault”
in the STATUS_MFR_SPECIFIC command is set. If this
bit remains set after being cleared by issuing a CLEAR_
FAULTS or writing a 1 to this bit, an irrecoverable internal
fault has occurred. The user is cautioned to disable both
output power supply rails associated with this specific
part. There are no provisions for field repair of NVM faults
in the manufacturing section.
SERIAL INTERFACE
The LTM4681 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
NVM or an external resistor. In addition the LTM4681
always responds to the global broadcast address of 0x5A
(7-bit) or 0x5B (7-bit).
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
The serial interface supports the following protocols
defined in the PMBus specifications: 1) send command,
2) write byte, 3) write word, 4) group, 5) read byte, 6) read
word and 7) read block. 8) write block. All read operations
will return a valid PEC if the PMBus master requests it. If
the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL
command, the PMBus write operations will not be acted
upon until a valid PEC has been received by the LTM4681.
Power Good Pins
The PGOODn pins of the LTM4681 are connected to the
open drains of internal MOSFETs. The MOSFETs turn on
and pull the PGOODn pins low when the channel output
voltage is not within the channel’s UV and OV voltage
thresholds. During TON_DELAY and TON_RISE sequenc-
ing, the PGOODn pin is held low. The PGOODn pin is
also pulled low when the respective RUNn pin is low. The
PGOODn pin response is deglitched by an internal 100µs
digital filter. The PGOODn pin and PGOOD status may be
different at times due to communication latency of up to
10µs.
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
CRC Protection
The integrity of the NVM memory is checked after a power
on reset. A CRC error will prevent the controller from leav-
ing the inactive state. If a CRC error occurs, the CML bit is
set in the STATUS_BYTE and STATUS_WORD commands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT_nn pin will be pulled low. NVM
DEVICE ADDRESSING
The LTM4681 offers five different types of addressing
over the PMBus interface, specifically: 1) global, 2) device,
3) rail addressing and 4) alert response address (ARA).
Rev. 0
41
For more information www.analog.com
LTM4681
OPERATION
Global addressing provides a means of the PMBus master
to address all LTM4681 devices on the bus. The LTM4681
global address is fixed 0x5A (7-bit) or 0xB4 (8-bit) and
cannot be disabled. Commands sent to the global address
act the same as if PAGE is set to a value of 0xFF. Commands
sent are written to both channels simultaneously. Global
command 0x5B (7-bit) or 0xB6 (8-bit) is paged and allows
channel specific command of all LTM4681 devices on the
bus. Other ADI device types may respond at one or both
of these global addresses. Reading from global addresses
is strongly discouraged.
The I and I
overcurrent monitors are performed by
ADC IrNeadingOsUaTnd calculations. Thus these values are
based on average currents and can have a time latency
of up to t
. The I
calculation accounts for the
CONVERT
OUT
DCR and their temperature coefficient. The input current
is equal to the voltage measured across the R resis-
SENSEn
tor divided by the resistors value as set with the MFR_
IIN_CAL_GAIN command. If this calculated input current
exceeds the IN_OC_WARN_LIMIT the ALERT_nn pin is
pulled low and the IIN_OC_WARN bit is asserted in the
STATUS_INPUT command.
Device addressing provides the standard means of the
PMBus master communicating with a single instance of
an LTM4681. The value of the device address is set by
a combination of the ASEL_nn configuration pin and the
MFR_ ADDRESS command. When this addressing means
is used, the PAGE command determines the channel being
acted upon. Device addressing can be disabled by writing
a value of 0x80 to the MFR_ADDRESS.
The digital processor within the LTM4681 provides the
ability to ignore the fault, shut down and latch off or shut
down and retry indefinitely (hiccup). The retry interval
is set in MFR_RETRY_ DELAY and can be from 120ms
to 83.88 seconds in 1ms increments. The shutdown for
OV/UV and OC can be done immediately or after a user
selectable deglitch time.
Output Overvoltage Fault Response
Rail addressing provides a means for the bus master to
simultaneously communicate with all channels connected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_
ADDRESS command, allowing for any logical grouping
of channels that might be required for reliable system
control. Reading from rail addresses is also strongly
discouraged.
A programmable overvoltage comparator (OV) guards
against transient overshoots as well as long-term over-
voltages at the output. In such cases, the top MOSFET
is turned off and the bottom MOSFET is turned on.
However, the reverse output current is monitored while
device is in OV fault. When it reaches the limit, both top
and bottom MOSFETs are turned off. The top and bot-
tom MOSFETs will keep their state until the overvoltage
condition is cleared regardless of the PMBus VOUT_OV_
FAULT_RESPONSE command byte value. This hardware
level fault response delay is typically 2µs from the over-
voltage condition to BG asserted high. Using the VOUT_
OV_FAULT_RESPONSE command, the user can select
any of the following behaviors:
All four means of PMBus addressing require the user to
employ disciplined planning to avoid addressing conflicts.
Communication to LTM4681 devices at global and rail
addresses should be limited to command write operations.
RESPONSES TO V
AND I /I
FAULTS
OUT
IN OUT
n
OV Pull-Down Only (OV Cannot Be Ignored)
V
OV and UV conditions are monitored by compara-
OUT
n
Shut Down (Stop Switching) Immediately—Latch Off
tors. The OV and UV limits are set in three ways:
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
n
As a Percentage of the VOUT if Using the Resistor
Configuration Pins
Either the Latch Off or Retry fault responses can be de-
glitched in increments of (0-7) • 10µs. See Table 14.
n
In NVM if Either Programmed at the Factory or
Through the GUI
n
By PMBus Command
Rev. 0
42
For more information www.analog.com
LTM4681
OPERATION
Output Undervoltage Response
FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT _LIMIT
is not reached within the TON_MAX_FAULT_LIMIT time,
the response of this fault is determined by the value of
the TON_MAX_FAULT_RESPONSE command value. This
response may be one of the following:
The response to an undervoltage comparator output can
be the following:
n
Ignore
n
Shut Down Immediately—Latch Off
n
n
n
Ignore
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
Shut Down (Stop Switching) Immediately—Latch Off
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
The UV responses can be deglitched. See Table 15.
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMIT means the fault is ignored. The
TON_MAX_FAULT_LIMIT should be set longer than the
TON_RISE time. It is recommended TON_MAX_FAULT_
LIMIT always be set to a non-zero value, otherwise the
output may never come up and no flag will be set to the
user. See Table 18.
Peak Output Overcurrent Fault Response
Due to the current mode control algorithm, peak output
current across the inductor is always limited on a cycle-
by-cycle basis. The value of the peak current limit is speci-
fied in Electrical Characteristics table. The current limit
circuit operates by limiting the COMPn maximum voltage.
Since internal DCR sensing is used, the COMPn maximum
voltage has a temperature dependency directly propor-
tional to the TC of the DCR of the inductor. The LTM4681
automatically monitors the external temperature sensors
and modifies the maximum allowed COMPn to compen-
sate for this term. The IOUT_OC_FAULT_LIMIT section
RESPONSES TO V OV FAULTS
IN
V overvoltage is measured with the ADC. The response
IN
is naturally deglitched by the 100ms typical response time
of the ADC. The fault responses are:
provides data points for I
Limiting on page 97.
OUT
n
Ignore
The overcurrent fault processing circuitry can execute the
following behaviors:
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY. See
Table 18.
n
Current Limit Indefinitely
n
n
Shut Down Immediately—Latch Off
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
RESPONSES TO OT/UT FAULTS
Internal Overtemperature Fault Response
The overcurrent responses can be deglitched in incre-
ments of (0-7) • 16ms. See Table 16.
An internal temperature sensor protects against NVM
damage. Above 85°C, no writes to NVM are recom-
mended. Above 130°C, the internal overtemperature warn
threshold is exceeded and the part disables the NVM and
does not re-enable until the temperature has dropped to
125°C. When the die temperature exceed 160°C the inter-
nal temperature fault response is enabled and the PWM
is disabled until the die temperature drops below 150°C.
Temperature is measured by the ADC. Internal tempera-
ture faults cannot be ignored. Internal temperature limits
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMIT is the time allowed for V
to
OUT
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMIT as the output is undergoing a SOFT_START
sequence. The TON_MAX_ FAULT_LIMIT time is started
after TON_DELAY has been reached and a SOFT_START
sequence is started. The resolution of the TON_MAX_
cannot be adjusted by the user. See Table 17.
Rev. 0
43
For more information www.analog.com
LTM4681
OPERATION
Overtemperature and Undertemperature
Fault Response
FAULT LOGGING
The LTM4681 has fault logging capability. Data is logged
into memory in the order shown in Table 19. The data is
stored in a continuously updated buffer in RAM. When a
fault event occurs, the fault log buffer is copied from the
RAM buffer into NVM. Fault logging is allowed at tem-
peratures above 85°C; however, retention of 10 years is
not guaranteed. When the die temperature exceeds 130°C
the fault logging is delayed until the die temperature drops
below 125°C. The fault log data remains in NVM until a
MFR_FAULT _LOG_CLEAR command is issued. Issuing
this command re-enables the fault log feature. Before re-
enabling fault log, be sure no faults are present and a
CLEAR_FAULTS command has been issued.
Four internal temperature sensors are used to sense the
temperature of critical circuit elements like inductors
and power MOSFETs on each channel. The OT_FAULT_
RESPONSE and UT_FAULT_ RESPONSE commands are
used to determine the appropriate response to an over-
temperature and under temperature condition, respec-
tively. If no external sense elements are used (not recom-
mended) set the UT_FAULT_ RESPONSE to ignore—and
set the UT_FAULT_LIMIT to 275°C. The fault responses
are:
n
Ignore
n
Shut Down Immediately—Latch Off
When the LTM4681 powers-up or exits its reset state, it
checks the NVM for a valid fault log. If a valid fault log
exists in NVM, the “Valid Fault Log” bit in the STATUS_
MFR_SPECIFIC command will be set and an ALERT event
will be generated. Also, fault logging will be blocked until
the LTM4681 has received a MFR_FAULT_LOG_CLEAR
command before fault logging will be re-enabled.
n
Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAY. See Table 18.
RESPONSES TO INPUT OVERCURRENT AND OUTPUT
UNDERCURRENT FAULTS
Input overcurrent and output undercurrent are measured
with the ADC. The fault responses are:
The information is stored in EEPROM in the event of
any fault that disables the controller on either channel. A
FAULTn being externally pulled low will not trigger a fault
logging event.
n
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
BUS TIMEOUT PROTECTION
The LTM4681 implements a timeout feature to avoid
persistent faults on the serial interface. The data packet
timer begins at the first START event before the device
address write byte. Data packet information must be
completed within 30ms or the LTM4681 will three-state
the bus and ignore the given data packet. If more time
is required, assert bit 3 of MFR_CONFIG_ALL to allow
typical bus timeouts of 255ms. Data packet information
includes the device address byte write, command byte,
repeat start event (if a read operation), device address
byte read (if a read operation), all data bytes and the PEC
byte if applicable.
RESPONSES TO EXTERNAL FAULTS
When either FAULTn pin is pulled low, the OTHER bit is
set in the STATUS_WORD command, the appropriate bit
is set in the STATUS_MFR_SPECIFIC command, and the
ALERT_nn pin is pulled low. Responses are not deglitched.
Each channel can be configured to ignore or shut down
then retry in response to its FAULTn pin going low by
modifying the MFR_FAULT_RESPONSE command. To
avoid the ALERT_nn pin asserting low when FAULTn is
pulled low, assert bit 1 of MFR_CHAN_CONFIG, or mask
the ALERT using the SMBALERT_MASK command.
The LTM4681 allows longer PMBus timeouts for block
read data packets. This timeout is proportional to the
length of the block read. The additional block read timeout
Rev. 0
44
For more information www.analog.com
LTM4681
OPERATION
applies primarily to the MFR_FAULT_LOG command. The
timeout period defaults to 32ms.
PMBus SERIAL DIGITAL INTERFACE
The LTM4681 communicates with a host (master) using
the standard PMBus serial bus interface. The Timing
Diagram, Figure 6, shows the timing relationship of the
signals on the bus. The two-bus lines, SDA and SCL, must
be high when the bus is not in use. External pull-up resis-
tors or current sources are required on these lines. The
LTM4681 is a slave device. The master can communicate
with the LTM4681 using the following formats:
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTM4681
supports the full PMBus frequency range from 10kHz
to 400kHz.
2
SIMILARITY BETWEEN PMBus, SMBus AND I C
2-WIRE INTERFACE
n
Master Transmitter, Slave Receiver
Master Receiver, Slave Transmitter
The PMBus 2-wire interface is an incremental extension
n
2
of the SMBus. SMBus is built upon I C with some minor
The following PMBus protocols are supported:
differences in timing, DC parameters and protocol. The
2
n
PMBus/SMBus protocols are more robust than simple I C
Write Byte, Write Word, Send Byte
byte commands because PMBus/SMBus provide time-
outs to prevent persistent bus errors and optional packet
error checking (PEC) to ensure data integrity. In general, a
master device that can be configured for I2C communica-
tion can be used for PMBus communication with little or
no change to hardware or firmware. Repeat start (restart)
n
Read Byte, Read Word, Block Read, Block Write
n
Alert Response Address
Figure 7 to Figure 24 illustrate the aforementioned PMBus
protocols. All transactions support PEC and GCP (group
command protocol). The Block Read supports 255 bytes
of returned data. For this reason, the PMBus timeout may
be extended when reading the fault log.
2
is not supported by all I C controllers but is required for
2
SMBus/PMBus reads. If a general purpose I C controller
is used, check that repeat start is supported.
Figure 7 is a key to the protocol diagrams in this section.
PEC is optional.
The LTM4681 supports the maximum SMBus clock speed
of 100kHz and is compatible with the higher speed PMBus
specification (between 100kHz and 400kHz) if MFR_
COMMON polling or clock stretching is enabled. For
robust communication and operation refer to the Note
section in the PMBus command summary. Clock stretch-
ing is enabled by asserting bit 1 of MFR_CONFIG_ALL.
A value shown below a field in the following figures is
mandatory value for that field.
The data formats implemented by PMBus are:
n
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.2: Paragraph 5: Transport.
n
Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes
a master receiver and the slave receiver becomes a
slave transmitter.
For a description of the differences between SMBus
and I2C, refer to System Management Bus (SMBus)
Specification Version 2.0: Appendix B—Differences
n
Combined format. During a change of direction within
2
Between SMBus and I C.
a transfer, the master repeats both a start condition
and the slave address but with the R/W bit reversed.
In this case, the master receiver terminates the trans-
fer by generating a NACK on the last byte of the trans-
fer and a STOP condition.
Rev. 0
45
For more information www.analog.com
LTM4681
OPERATION
Refer to Figure 7 for a legend.
Handshaking features are included to ensure robust system communication. Please refer to the PMBus Communication
and Command Processing subsection of the Applications Information section for further details.
ꢀꢁꢂ
ꢅ
ꢓ
ꢅ
ꢀꢊꢇꢁꢂꢈꢉ
ꢅ
ꢅ
ꢀꢍ
ꢅ
ꢓ
ꢆꢁꢇꢀꢁꢂꢉ
ꢅ
ꢔ
ꢅ
ꢅ
ꢅ
ꢎꢊꢏ
ꢔ
ꢄꢋꢌ
ꢀꢃꢄ
ꢅ
ꢅ
ꢅ
ꢀꢊꢇꢀꢈꢋꢉ
ꢆꢁꢇꢀꢈꢂꢉ
ꢀꢊꢇꢀꢈꢂꢉ
ꢅ
ꢅ
ꢆꢑꢕꢆ
ꢆꢁꢇꢁꢂꢈꢉ
ꢖꢗꢘꢙ ꢏ0ꢗ
ꢀꢈꢂRꢈ
ꢃꢋꢐꢁꢑꢈꢑꢋꢐ
Rꢒꢍꢒꢂꢈꢒꢁ ꢀꢈꢂRꢈ
ꢃꢋꢐꢁꢑꢈꢑꢋꢐ
ꢀꢈꢋꢍ
ꢀꢈꢂRꢈ
ꢃꢋꢐꢁꢑꢈꢑꢋꢐ ꢃꢋꢐꢁꢑꢈꢑꢋꢐ
Figure 6. PMBus Timing Diagram
Table 6. Abbreviations of Supported Data Formats
PMBus
SPECIFICATION
REFERENCE
ADI
TERMINOLOGY DEFINITION
TERMINOLOGY
EXAMPLE
N
L11
Linear
Part II ¶7.1
Linear_5s_1s Floating point 16-bit data: value = Y • 2 ,
where N = b[15:11] and Y = b[10:0], both
two’s compliment binary integers
b[15:0] = 0x9807 = 10011_000_0000_0111
–13
value = 7 • 2 = 854E-6
–12
L16
CF
Linear
Part II ¶8.2
Part II ¶7.2
Part II ¶10.3
Linear_16u
Varies
Reg
Floating point 16-bit data: value = Y • 2
where Y = b[15:0], an unsigned integer
,
b[15:0] = 0x4C00 = 0100_1100_0000_0000
–12
VOUT_MODE
value = 19456 • 2 = 4.75
DIRECT
16-bit data with a custom format defined in Often an unsigned or two’s compliment
the detailed PMBus command description integer
Reg
ASC
Register Bits
Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command
command description
Text Characters Part II ¶22.2.1
ASCII
ISO/IEC 8859-1 [A05]
LTC (0x4C5443)
Rev. 0
46
For more information www.analog.com
LTM4681
OPERATION
FIGURE 7 TO FIGURE 24 PMBus PROTOCOLS
ꢆ
ꢆꢇꢈRꢇ ꢉꢊꢋꢌꢍꢇꢍꢊꢋ
Rꢏꢐꢏꢈꢇꢏꢌ ꢆꢇꢈRꢇ ꢉꢊꢋꢌꢍꢇꢍꢊꢋ
ꢆꢎ
Rꢑ Rꢏꢈꢌ ꢒꢓꢍꢇ ꢔꢈꢕꢖꢏ ꢊꢄ ꢃꢗ
ꢘꢎ ꢘRꢍꢇꢏ ꢒꢓꢍꢇ ꢔꢈꢕꢖꢏ ꢊꢄ 0ꢗ
ꢈ
ꢈꢉꢙꢋꢊꢘꢕꢏꢌꢚꢏ ꢒꢇꢛꢍꢆ ꢓꢍꢇ ꢐꢊꢆꢍꢇꢍꢊꢋ ꢜꢈꢝ ꢓꢏ 0
ꢄꢊR ꢈꢋ ꢈꢉꢙ ꢊR ꢃ ꢄꢊR ꢈ ꢋꢈꢉꢙꢗ
ꢐ
ꢆꢇꢊꢐ ꢉꢊꢋꢌꢍꢇꢍꢊꢋ
ꢐꢏꢉ ꢐꢈꢉꢙꢏꢇ ꢏRRꢊR ꢉꢊꢌꢏ
ꢜꢈꢆꢇꢏR ꢇꢊ ꢆꢕꢈꢔꢏ
ꢆꢕꢈꢔꢏ ꢇꢊ ꢜꢈꢆꢇꢏR
...
ꢉꢊꢋꢇꢍꢋꢖꢈꢇꢍꢊꢋ ꢊꢄ ꢐRꢊꢇꢊꢉꢊꢕ
ꢀꢁꢂꢃ ꢄ0ꢅ
Figure 7. PMBus Packet Protocol Diagram Element Key
ꢎ
ꢐ
ꢎ
ꢎ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢆꢇꢈꢉ
ꢂ
ꢊ
ꢋꢌꢍꢎ ꢏ0ꢍ
Figure 8. Quick Command Protocol
ꢐ
ꢓ
ꢐ
ꢐ
ꢏ
ꢐ
ꢐ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑ0ꢒ
Figure 9. Send Byte Protocol
ꢐ
ꢒ
ꢐ
ꢐ
ꢏ
ꢐ
ꢏ
ꢐ
ꢐ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢋꢌ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢄꢆ
ꢂ
ꢊ
ꢍꢎꢏꢐ ꢑꢐ0
Figure 10. Send Byte Protocol with PEC
ꢒ
ꢐ
ꢒ
ꢒ
ꢑ
ꢒ
ꢑ
ꢒ
ꢒ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ
ꢂ
ꢏ
ꢓꢔꢑꢒ ꢕꢒꢒ
Figure 11. Write Byte Protocol
ꢓ
ꢖ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ
ꢂ
ꢏꢄꢆ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢓꢕ
Figure 12. Write Byte Protocol with PEC
ꢓ
ꢖ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢁꢇꢍ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢗꢘꢙꢗ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢓꢕ
Figure 13. Write Word Protocol
ꢓ
ꢕ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢁꢇꢍ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢖꢗꢘꢖ
ꢂ
ꢏꢄꢆ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢓꢐ
Figure 14. Write Word Protocol with PEC
Rev. 0
47
For more information www.analog.com
LTM4681
OPERATION
ꢐ
ꢓ
ꢐ
ꢐ
ꢏ
ꢐ
ꢐ
ꢓ
ꢐ
ꢐ
ꢏ
ꢐ
ꢐ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢗ
ꢂ
ꢅꢂꢔꢂ ꢕꢖꢔꢄ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢐꢒ
Figure 15. Read Byte Protocol
ꢐ
ꢒ
ꢐ
ꢐ
ꢏ
ꢐ
ꢐ
ꢒ
ꢐ
ꢐ
ꢏ
ꢐ
ꢐ
ꢐ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ
ꢂ
ꢌꢄꢆ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢐꢎ
Figure 16. Read Byte Protocol with PEC
ꢐ
ꢒ
ꢐ
ꢐ
ꢏ
ꢐ
ꢐ
ꢒ
ꢐ
ꢐ
ꢏ
ꢐ
ꢏ
ꢐ
ꢐ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢙ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢁꢇꢊ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢖꢗꢘꢖ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢐꢒ
Figure 17. Read Word Protocol
ꢐ
ꢒ
ꢐ
ꢐ
ꢏ
ꢐ
ꢐ
ꢒ
ꢐ
ꢐ
ꢏ
ꢐ
ꢏ
ꢐ
ꢏ
ꢐ
ꢐ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢙ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢁꢇꢊ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢖꢗꢘꢖ
ꢂ
ꢌꢄꢆ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢐꢏ
Figure 18. Read Word Protocol with PEC
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢔ
ꢂ
ꢏꢐꢑꢄ ꢆꢇꢒꢉꢑ ꢓ ꢉ
ꢂ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢕ
ꢕ
ꢍ
ꢎ
ꢎ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢛ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢉ
ꢂ
ꢖ
ꢗꢘꢍꢎ ꢙꢎꢚ
Figure 19. Block Read Protocol
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢔ
ꢂ
ꢏꢐꢑꢄ ꢆꢇꢒꢉꢑ ꢓ ꢉ
ꢂ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢕ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢎ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢖ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢉ
ꢂ
ꢗꢄꢆ
ꢂ
ꢗ
ꢘꢙꢍꢎ ꢚꢖ0
Figure 20. Block Read Protocol with PEC
Rev. 0
48
For more information www.analog.com
LTM4681
OPERATION
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢏꢐ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢈ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢈ
ꢂ
ꢔ
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢀꢐ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢉ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢔ
ꢔ
ꢒ
ꢓ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢉ
ꢂ
ꢗ
ꢘꢙꢒꢓ ꢚꢕꢓ
Figure 21. Block Write – Block Read Process Call
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢏꢐ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢈ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢈ
ꢂ
ꢔ
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢀꢐ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢉ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢔ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢉ
ꢂ
ꢗꢄꢆ
ꢂ
ꢗ
ꢘꢙꢒꢓ ꢚꢕꢕ
Figure 22. Block Write – Block Read Process Call with PEC
ꢍ
ꢑ
ꢍ
ꢍ
ꢌ
ꢍ
ꢍ
ꢀꢁꢂRꢃ Rꢂꢄꢅꢆꢇꢄꢂ
ꢀꢈꢈRꢂꢄꢄ
ꢄ
Rꢉ
ꢀ
ꢈꢂꢒꢓꢔꢂ ꢀꢈꢈRꢂꢄꢄ
ꢀ
ꢅ
ꢊꢋꢌꢍ ꢎꢏꢐ
Figure 23. Alert Response Address Protocol
ꢌ
ꢊ
ꢌ
ꢌ
ꢋ
ꢌ
ꢋ
ꢌ
ꢌ
ꢀꢁꢂRꢃ Rꢂꢄꢅꢆꢇꢄꢂ
ꢀꢈꢈRꢂꢄꢄ
ꢄ
Rꢉ
ꢀ
ꢈꢂꢍꢎꢏꢂ ꢀꢈꢈRꢂꢄꢄ
ꢀ
ꢅꢂꢏ
ꢀ
ꢅ
ꢐꢑꢋꢌ ꢒꢓꢐ
Figure 24. Alert Response Address Protocol with PEC
Rev. 0
49
For more information www.analog.com
LTM4681
PMBus COMMAND SUMMARY
PMBus COMMANDS
not supported by the manufacturer. Attempting to access
non-supported or reserved commands may result in a
CML command fault event. All output voltage settings and
Table 7 lists supported PMBus commands and manu-
facturer specific commands. A complete description of
these commands can be found in the “PMBus Power
System Mgt Protocol Specification – Part II – Revision
1.2”. Users are encouraged to reference this specifica-
tion. Exceptions or manufacturer specific implementa-
tions are listed in Table 7. Floating point values listed in
the “DEFAULT VALUE” column are either Linear 16-bit
Signed (PMBus Section 8.3.1) or Linear_5s_11s (PMBus
Section 7.1) format, whichever is appropriate for the com-
mand. All commands from 0xD0 through 0xFF not listed in
Table 7 are implicitly reserved by the manufacturer. Users
should avoid blind writes within this range of commands
to avoid undesired operation of the part. All commands
from 0x00 through 0xCF not listed in Table 7 are implicitly
measurements are based on the VOUT_MODE setting of
–12
0x14. This translates to an exponent of 2
.
If PMBus commands are received faster than they are
being processed, the part may become too busy to handle
new commands. In these circumstances the part follows
the protocols defined in the PMBus Specification v1.2,
Part II, Section 10.8.7, to communicate that it is busy.
The part includes handshaking features to eliminate busy
errors and simplify error handling software while ensur-
ing robust communication and system behavior. Please
refer to the subsection titled PMBus Communication and
Command Processing in the Applications Information
section for further details.
Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations Are Detailed in Table 8)
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
PAGE
0x00 Provides integration with multi-page
PMBus devices.
R/W Byte
N
Y
Y
Reg
Reg
Reg
0x00
0x80
0x1E
NA
84
OPERATION
0x01 Operating mode control. On/off, margin
high and margin low.
R/W Byte
R/W Byte
Y
Y
88
88
ON_OFF_CONFIG
0x02 RUN pin and PMBus bus on/off command
configuration.
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Send Byte
W Block
N
N
113
84
PAGE_PLUS_WRITE
0x05 Write a command directly to a
specified page.
PAGE_PLUS_READ
WRITE_PROTECT
0x06 Read a command directly from a
specified page.
Block R/W
R/W Byte
N
N
84
85
0x10 Level of protection provided by the device
against accidental changes.
Reg
Reg
Y
Y
0x00
STORE_USER_ALL
0x15 Store user operating memory to EEPROM. Send Byte
N
N
NA
NA
123
123
RESTORE_USER_ALL
0x16 Restore user operating memory from
EEPROM.
Send Byte
CAPABILITY
0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
0xB0
112
SMBALERT_MASK
VOUT_MODE
0x1B Mask ALERT activity
Block R/W
R Byte
Y
Y
Reg
Reg
See CMD
113
94
–12
–12
0x20 Output voltage format and exponent (2 ).
2
0x14
VOUT_COMMAND
VOUT_MAX
0x21 Nominal output voltage set point.
R/W Word
R/W Word
Y
Y
L16
L16
V
V
Y
Y
1.0
95
94
0x1000
0x24 Upper limit on the commanded output
voltage including VOUT_MARGIN_HI.
3.6
0xC399
Rev. 0
50
For more information www.analog.com
LTM4681
PMBus COMMAND SUMMARY
CMD
DATA
PAGED FORMAT UNITS NVM
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGE
VOUT_MARGIN_HIGH
0x25 Margin high output voltage set point. Must R/W Word
be greater than VOUT_COMMAND.
Y
Y
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
L16
L16
L11
L11
L11
L11
L16
Reg
L16
L16
L16
Reg
L11
Reg
L11
L11
Reg
L11
L11
Reg
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1.05
95
0x10CD
VOUT_MARGIN_LOW
VOUT_TRANSITION_ RATE
FREQUENCY_SWITCH
VIN_ON
0x26 Margin low output voltage set point. Must R/W Word
be less than VOUT_COMMAND.
V
0.95
0x0F33
95
101
92
0X27 Rate the output changes when V
commanded to a new value.
R/W Word
V/ms
kHz
V
0.25
0xD010
OUT
0x33 Switching frequency of the controller.
R/W Word
350kHz
0x2016
0x35 Input voltage at which the unit should start R/W Word
power conversion.
4.75
0xD130
93
VIN_OFF
0x36 Input voltage at which the unit should stop R/W Word
power conversion.
V
4.5
0xD120
93
VOUT_OV_FAULT_LIMIT
0x40 Output overvoltage fault limit.
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Byte
V
1.1
0x119A
94
VOUT_OV_FAULT_
RESPONSE
0x41 Action to be taken by the device when an
output overvoltage fault is detected.
0xB8
103
94
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
0x42 Output overvoltage warning limit.
0x43 Output undervoltage warning limit.
0x44 Output undervoltage fault limit.
V
V
V
1.075
0x1133
0.925
0x0ECD
95
0.9
0x0E66
95
VOUT_UV_FAULT_
RESPONSE
0x45 Action to be taken by the device when an
output undervoltage fault is detected.
0xB8
104
97
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
A
40.00
0xE280
IOUT_OC_FAULT_ RESPONSE 0x47 Action to be taken by the device when an
output overcurrent fault is detected.
0x00
106
98
IOUT_OC_WARN_LIMIT
0x4A Output overcurrent warning limit.
A
C
34.0
0xE230
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
128.0
0xF200
99
OT_FAULT_RESPONSE
OT_WARN_LIMIT
0x50 Action to be taken by the device when an
external overtemperature fault is detected,
0xB8
108
99
0x51 External overtemperature warning limit.
C
C
125.0
0xEBE8
UT_FAULT_LIMIT
0x53 External undertemperature fault limit.
–45.0
0xE530
100
108
UT_FAULT_RESPONSE
0x54 Action to be taken by the device when
an external undertemperature fault is
detected.
0xB8
VIN_OV_FAULT_LIMIT
0x55 Input supply overvoltage fault limit.
R/W Word
R/W Byte
R/W Word
R/W Word
N
Y
N
N
L11
Reg
L11
L11
V
Y
Y
Y
Y
15.5
92
103
93
0xD3E0
VIN_OV_FAULT_ RESPONSE 0x56 Action to be taken by the device when an
input overvoltage fault is detected.
0x80
VIN_UV_WARN_LIMIT
0x58 Input supply undervoltage warning limit.
V
A
4.65
0xD12A
IIN_OC_WARN_LIMIT
0x5D Input supply overcurrent warning limit.
10.0
0xD280
98
Rev. 0
51
For more information www.analog.com
LTM4681
PMBus COMMAND SUMMARY
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
TON_DELAY
0x60 Time from RUN and/or Operation on to
output rail turn-on.
R/W Word
Y
L11
L11
ms
Y
0.0
100
0x8000
TON_RISE
0x61 Time from when the output starts to rise
R/W Word
R/W Word
R/W Byte
Y
ms
Y
3.0
0xC300
100
101
until the output voltage reaches the V
commanded value.
OUT
TON_MAX_FAULT_LIMIT
0x62 Maximum time from the start of
Y
L11
ms
Y
5.0
0xCA80
TON_RISE for V
to cross the
OUT
VOUT_UV_FAULT_LIMIT.
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a
TON_ MAX_FAULT event is detected.
Y
Y
Y
Y
Reg
L11
L11
L11
Y
Y
Y
Y
0xB8
106
101
101
102
TOFF_DELAY
0x64 Time from RUN and/or Operation off to the R/W Word
start of TOFF_FALL ramp.
ms
ms
ms
0.0
0x8000
TOFF_FALL
0x65 Time from when the output starts to fall
until the output reaches zero volts.
R/W Word
3.0
0xC300
TOFF_MAX_WARN_ LIMIT
0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below
12.5%.
R/W Word
0
0x8000
STATUS_BYTE
STATUS_WORD
0x78 One byte summary of the unit’s fault
condition.
R/W Byte
Y
Y
Reg
Reg
NA
NA
114
115
0x79 Two byte summary of the unit’s fault
condition.
R/W Word
STATUS_VOUT
0x7A Output voltage fault and warning status.
0x7B Output current fault and warning status.
0x7C Input supply fault and warning status.
R/W Byte
R/W Byte
R/W Byte
R/W Byte
Y
Y
N
Y
Reg
Reg
Reg
Reg
NA
NA
NA
NA
115
116
116
117
STATUS_IOUT
STATUS_INPUT
STATUS_TEMPERATURE
0x7D External temperature fault and warning
status for READ_TEMERATURE_1.
STATUS_CML
0x7E Communication and memory fault and
warning status.
R/W Byte
R/W Byte
N
Y
Reg
Reg
NA
NA
117
118
STATUS_MFR_SPECIFIC
0x80 Manufacturer specific fault and state
information.
READ_VIN
0x88 Measured input supply voltage.
0x89 Measured input supply current.
0x8B Measured output voltage.
0x8C Measured output current.
R Word
R Word
R Word
R Word
R Word
N
N
Y
Y
Y
L11
L11
L16
L11
L11
V
A
V
A
C
NA
NA
NA
NA
NA
120
120
120
120
120
READ_IIN
READ_VOUT
READ_IOUT
READ_TEMPERATURE_1
0x8D External temperature sensor temperature.
This is the value used for all temperature
related processing, including
IOUT_CAL_GAIN.
READ_TEMPERATURE_2
0x8E Internal die junction temperature. Does
not affect any other commands.
R Word
N
L11
C
NA
120
READ_FREQUENCY
READ_POUT
0x95 Measured PWM switching frequency.
0x96 Measured output power
R Word
R Word
R Word
R Byte
Y
Y
Y
N
L11
L11
L11
Reg
Hz
W
W
NA
N/A
120
120
121
112
READ_PIN
0x97 Calculated input power
N/A
PMBus_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.2.
0x22
MFR_ID
0x99 The manufacturer ID of the LTM4681 in
ASCII.
R String
R String
N
N
ASC
ASC
LTC
112
112
MFR_MODEL
0x9A Manufacturer part number in ASCII.
Rev. 0
52
For more information www.analog.com
LTM4681
PMBus COMMAND SUMMARY
CMD
DATA
PAGED FORMAT UNITS NVM
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGE
MFR_VOUT_MAX
0xA5 Maximum allowed output voltage
including VOUT_OV_FAULT_LIMIT.
R Word
Y
N
N
L16
V
3.6
96
0x0399
MFR_PIN_ACCURACY
USER_DATA_00
0xAC Returns the accuracy of the READ_PIN
command
R Byte
%
5.0%
NA
121
112
0xB0 OEM RESERVED. Typically used for part
serialization.
R/W Word
Reg
Y
USER_DATA_01
USER_DATA_02
0xB1 Manufacturer reserved for LTpowerPlay.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
NA
NA
112
112
0xB2 OEM RESERVED. Typically used for part
serialization
USER_DATA_03
USER_DATA_04
MFR_EE_UNLOCK
MFR_EE_ERASE
MFR_EE_DATA
0xB3 An NVM word available for the user.
0xB4 An NVM word available for the user.
0xBD Contact factory.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
0x0000
0x0000
112
112
128
128
128
86
0xBE Contact factory.
0xBF Contact factory.
MFR_CHAN_CONFIG
0xD0 Configuration bits that are channel
specific.
R/W Byte
R/W Byte
Y
Reg
Y
0x1D
MFR_CONFIG_ALL
0xD1 General configuration bits.
N
Y
Reg
Reg
Y
Y
0x21
87
MFR_FAULT_ PROPAGATE
0xD2 Configuration that determines which faults R/W Word
0x6993
109
are propagated to the FAULT pin.
MFR_PWM_COMP
0xD3 PWM loop compensation configuration
0xD4 Configuration for the PWM engine.
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
Reg
Reg
Reg
Y
Y
Y
0x28
0xC7
0xC0
90
89
MFR_PWM_MODE
MFR_FAULT_RESPONSE
0xD5 Action to be taken by the device when the
111
FAULT pin is externally asserted low.
MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte
N
Y
Reg
L11
0xC0
NA
107
121
MFR_IOUT_PEAK
0xD7 Report the maximum measured
value of READ_ IOUT since last
MFR_CLEAR_PEAKS.
R Word
A
MFR_ADC_CONTROL
MFR_RETRY_DELAY
MFR_RESTART_DELAY
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xD8 ADC telemetry parameter selected for
repeated fast ADC read back
R/W Byte
N
Y
Y
Y
N
Y
Reg
L11
L11
L16
L11
L11
0x00
122
102
102
121
121
121
0xDB Retry interval during FAULT retry mode.
R/W Word
ms
ms
V
Y
Y
250.0
0xF3E8
0xDC Minimum time the RUN pin is held low by R/W Word
the LTM4681.
150.0
0xF258
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
R Word
R Word
R Word
NA
NA
NA
0xDE Maximum measured value of READ_VIN
since last MFR_CLEAR_PEAKS.
V
MFR_TEMPERATURE_1_ PEAK 0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1)
C
since last MFR_CLEAR_PEAKS.
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS
R Word
N
L11
A
A
NA
121
MFR_CLEAR_PEAKS
MFR_READ_ICHIP
MFR_PADS
0xE3 Clears all peak values.
Send Byte
R Word
N
N
N
NA
NA
NA
114
122
118
0xE4 Measured supply current of the SV pin
L11
Reg
IN
0xE5 Digital status of the I/O pads.
R Word
Rev. 0
53
For more information www.analog.com
LTM4681
PMBus COMMAND SUMMARY
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
MFR_ADDRESS
MFR_ADDRESS
MFR_SPECIAL_ID
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
86
2
0xE6 Sets the 7-bit I C address byte, Ch 0 and 1 R/W Byte
N
N
N
Reg
Reg
Reg
Y
Y
0x4F
0x4E
2
0xE6 Sets the 7-bit I C address byte, Ch 2 and 3 R/W Byte
86
0xE7 Manufacturer code representing the
LTM4681 and revision
R Word
R/W Word
Send Byte
0x414X
112
MFR_IIN_CAL_GAIN
0xE8 The resistance value of the input current
sense element in mΩ.
N
N
L11
mΩ
mΩ
Y
2.0
0xC200
98
MFR_FAULT_LOG_ STORE
0xEA Command a transfer of the fault log from
RAM to EEPROM.
NA
124
MFR_INFO
0x
Contact factory.
128
96
MFR_IOUT_CAL_GAIN
0xDA SET AT FACTORY. Typical 0.4mΩ
R Word
Y
N
L11
0.4 typical
0xD01A
MFR_FAULT_LOG_ CLEAR
0xEC Initialize the EEPROM block reserved for
fault logging.
Send Byte
NA
128
MFR_FAULT_LOG
MFR_COMMON
0xEE Fault log data bytes.
R Block
R Byte
N
N
Reg
Reg
Y
NA
NA
124
119
0xEF Manufacturer status bits that are common
across multiple ADI chips.
MFR_COMPARE_USER_ ALL
0xF0 Compares current command contents
with NVM.
Send Byte
R Word
N
N
N
Y
N
Y
Y
Y
NA
NA
123
122
91
MFR_TEMPERATURE_2_ PEAK 0xF4 Peak internal die temperature since last
MFR_ CLEAR_PEAKS.
L11
Reg
CF
C
MFR_PWM_CONFIG
0xF5 Set numerous parameters for the DC/DC
controller including phasing.
R/W Byte
R/W Word
R/W Word
Y
Y
Y
Y
Y
Y
0x10
MFR_IOUT_CAL_GAIN_ TC
MFR_ICHIP_CAL_GAIN
MFR_TEMP_1_GAIN
0xF6 Temperature coefficient of the current
sensing element.
ppm/
˚C
3900
0x0F3C
96
0xF7 The resistance value of the V pin filter
L11
CF
mΩ
1000
0x03E8
93
IN
element in mΩ.
0xF8 Sets the slope of the external temperature R/W Word
sensor.
0.995
0x3FAE
99
MFR_TEMP_1_OFFSET
MFR_RAIL_ADDRESS
0xF9 Sets the offset of the external temperature R/W Word
sensor with respect to –273.1°C
L11
Reg
CF
C
0.0
0x8000
99
0xFA Common address for PolyPhase outputs
to adjust common parameters.
R/W Byte
0x80
86
MFR_REAL_TIME
MFR_RESET
0xFB 48-bit share-clock counter value.
R Block
N
N
NA
NA
71
88
0xFD Commanded reset without requiring a
power down.
Send Byte
Note 1: Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and
RESTORE_USER_ALL commands, respectively.
Note 2: Commands with a default value of NA indicate “not applicable”. Commands with a default value of FS indicate “factory set on a per part basis”.
Note 3: The LTM4681 contains additional commands not listed in Table 7. Reading these commands is harmless to the operation of the IC; however, the
contents and meaning of these commands can change without notice.
Note 4: Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in Table 7 is not permitted.
Note 6: The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s
data sheet for each part for a complete definition of a command’s function. ADI strives to keep command functionality compatible between all ADI
devices. Differences may occur to address specific product requirements.
Rev. 0
54
For more information www.analog.com
LTM4681
PMBus COMMAND SUMMARY
Table 8. Data Format Abbreviations
L11
Linear_5s_11s
PMBus data field b[15:0]
N
Value = Y • 2
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer
Example:
For b[15:0] = 0x9807 = ‘b10011_000_0000_0111
–13
–6
Value = 7 • 2 = 854 • 10
From “PMBus Spec Part II: Paragraph 7.1”
L16
Linear_16u
PMBus data field b[15:0]
N
Value = Y • 2
where Y = b[15:0] is an unsigned integer and N = VOUT_MODE_PARAMETER is a 5-bit two’s complement exponent that is
hardwired to –12 decimal
Example:
For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000
–12
Value = 19456 • 2 = 4.75 From “PMBus Spec Part II: Paragraph 8.2”
Reg
L16
Register
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Description.
Integer Word
PMBus data field b[15:0]
Value = Y
where Y = b[15:0] is a 16-bit unsigned integer
Example:
For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111
Value = 38919 (decimal)
CF
Custom Format
ASCII Format
Value is defined in detailed PMBus Command Description.
This is often an unsigned or two’s complement integer scaled by an MFR specific constant.
ASC
A variable length string of text characters conforming to ISO/IEC 8859-1 standard.
Rev. 0
55
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
V TO V
STEP-DOWN RATIOS
OUTPUT CAPACITORS
IN
OUT
There are restrictions in the maximum V and V
step-
The LTM4681 is designed for low output voltage ripple
noise and good transient response. The bulk output
IN
OUT
down ratio that can be achieved for a given input voltage.
Each output of the LTM4681 is capable of 95% duty cycle
capacitors defined as C
are chosen with low enough
OUT
at 500kHz, but the V to V
minimum dropout is still
effective series resistance (ESR) to meet the output volt-
age ripple and transient requirements. C can be a low
IN
OUT
a function of its load current and will limit output current
capability related to high duty cycle on the topside switch.
OUT
ESR tantalum capacitor, a low ESR polymer capacitor or
ceramic capacitor. The typical output capacitance range
for each output is from 400µF to 1000µF. Additional out-
put filtering may be required by the system designer, if
further reduction of output ripple or dynamic transient
spikes is required. Table 13 shows a matrix of different
output voltages and output capacitors to minimize the
voltage droop and overshoot during a 15A to 30A step,
15A/µs transient each channel. Table 13 optimizes total
equivalent ESR and total bulk capacitance to optimize the
transient performance. Stability criteria are considered in
the Table 13 matrix, and the LTPowerCAD Design Tool will
be provided for stability analysis. Multiphase operation
reduces effective output ripple as a function of the number
of phases. Application Note 77 discusses this noise reduc-
tion versus output ripple current cancellation, but the out-
put capacitance should be considered carefully as a func-
tion of stability and transient response. The LTPowerCAD
Design Tool can calculate the output ripple reduction as
the number of implemented phases increases by N times.
Minimum on-time t
is another consideration in
ON(MIN)
operating at a specified duty cycle while operating at a
certain frequency due to the fact that tON(MIN) < D/fSW
where D is duty cycle and f is the switching frequency.
,
SW
t
is specified in the electrical parameters as 60ns.
ON(MIN)
See Note 6 in the Electrical Characteristics section for
output current guideline.
INPUT CAPACITORS
The LTM4681 module should be connected to a low AC
impedance DC source. For the regulator input, four 22µF
input ceramic capacitors are used to handle the RMS
ripple current. A 47µF to 150µF surface mount aluminum
electrolytic bulk capacitor can be used for more input
bulk capacitance. This bulk input capacitor is only needed
if the input source impedance is compromised by long
inductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
A small value 10Ω resistor can be placed in series from
+
V
OUTn
to the V
pin to allow for a bode plot analyzer
to inject a sigOnSaNl Sin0to the control loop and validate the
regulator stability. The LTM4681’s stability compensation
can be adjusted using two external capacitors (COMPna ,
COMPnb), and the MFR_PWM_COMP commands.
For a buck converter, the switching duty-cycle can be
estimated as:
VOUTn
Dn =
V
INn
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
LIGHT LOAD CURRENT OPERATION
The LTM4681 has two modes of operation including high
efficiency, discontinuous conduction mode or forced
continuous conduction mode. The mode of operation is
configured by bit 0 of the MFR_PWM_MODEn command
(discontinuous conduction is always the start-up mode,
forced continuous is the default running mode).
IOUTn(MAX)
ICIN (RMS)
=
• D • 1−D
n n
(
)
n
η%
In the above equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcher-
rated electrolytic aluminum capacitor, or a polymer capac-
itor. Application Note 77 can be utilized to help calculate
ripple current cancellation for multiphase applications.
If a channel is enabled for discontinuous mode opera-
tion, the inductor current is not allowed to reverse. The
reverse current comparator, IREV, turns off the bottom
Rev. 0
56
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
MOSFET (MBn) just before the inductor current reaches
zero, preventing it from reversing and going negative.
Thus, the controller can operate in discontinuous (pulse-
skipping) operation. In forced continuous operation, the
inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined solely by the voltage on the COMPn
pin. In this mode, the efficiency at light loads is lower than
in discontinuous mode operation. However, continuous
mode exhibits lower output ripple and less interference
with audio circuitry. Forced continuous conduction mode
may result in reverse inductor current, which can cause
the input supply to boost. The VIN_OV_FAULT_LIMIT
ALL[4] = 1b. This can be easily implemented with resis-
tor pin-strap settings on the FSWPH_nn_CFG pin (see
Table 3). Using MFR_CONFIG_ALL[4] = 1b, the LTM4681s
SYNC pin becomes a high impedance input, only—i.e.,
it does not drive SYNC low. The module synchronizes its
frequency to that of the clock applied to its SYNC pin.
The only shortcoming of this approach is: in the absence
of an externally applied clock, the switching frequency of
the module will default to the low end of its frequency-
synchronization capture range (~225kHz).
If fault-tolerance to the loss of an externally applied SYNC
clock is desired, the FREQUENCY_SWITCH command of
a “sync slave” can be left at the nominal target switching
frequency of the application, and not 0x0000 However,
it is then still necessary to configure MFR_CONFIG_
ALL[4] = 1b. With this combination of configurations,
the LTM4681’s SYNC_nn pins becomes a high imped-
ance input and the module synchronizes its frequency
to that of the externally applied clock, provided that the
frequency of the externally applied clock exceeds ~½.
of the target frequency (FREQUENCY_SWITCH). If the
SYNC clock is absent, the module responds by operating
at its target frequency, indefinitely. If and when the SYNC
clock is restored, the module automatically phase-locks
to the SYNC clock as normal. The only shortcoming of
this approach is: the EEPROM must be configured per
above guidance; resistor pin-strapping options on the
FSWPH_nn_CFG pin alone cannot provide fault-tolerance
to the absence of the SYNC clock.
can detect this (if SV
IN23
is connected to V
and/or
IN_nn
IN01
V
) and turn off the offending channel. However, this
fault is based on an ADC read and can nominally take up
to 100ms to detect. If there is a concern about the input
supply boosting, keep the part in discontinuous conduc-
tion operation.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the LTM4681’s channels is
established by its analog phase-locked-loop (PLL) locking
on to the clock present at the module’s SYNC_nn pin. The
clock waveform on the SYNC_nn pin can be generated by
the LTM4681’s internal circuitry when an external pull-up
resistor to 3.3V (e.g., V ) is provided, in combination
DD33
with the LTM4681 control IC’s FREQUENCY_SWITCH
command being set to one of the following supported val-
ues: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz, 650kHz,
750kHz. In this configuration, the module is called a
“sync master”: (using the factory-default setting of MFR_
CONFIG_ALL[4] = 0b), SYNC_nn becomes a bidirectional
open-drain pin, and the LTM4681 pulls SYNC logic low
for nominally 500ns at a time, at the prescribed clock
rate. The SYNC signal can be bused to other LTM4681
modules (configured as “sync slaves”), for purposes of
synchronizing switching frequencies of multiple modules
within a system—but only one LTM4681 internal control-
lers should be configured as a “sync master”; the other
LTM4681(s) should be configured as “sync slaves”.
2
The FREQUENCY_SWITCH register can be altered via I C
commands, but only when switching action is disengaged,
i.e., the module’s outputs are turned off. The FREQUENCY_
SWITCH command takes on the value stored in NVM at
SV power-up, but is overridden according to a resistor
IN
pin-strap applied between the FSWPH_nn_CFG pin and
SGND only if the module is configured to respect resistor
pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3
highlights available resistor pin-strap and corresponding
FREQUENCY_SWITCH settings.
The relative phasing of all active channels in a PolyPhase
rail should be optimally phased. The relative phasing of
each rail is 360°/n, where n is the number of phases in the
rail. MFR_PWM_CONFIG[2:0] configures channel relative
The most straightforward way is to set its FREQUENCY_
SWITCH command to 0x0000 and MFR_CONFIG_
Rev. 0
57
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
phasing with respect to the SYNC_nn pin. Phase relation-
ship values are indicated with 0° corresponding to the
falling edge of SYNC being coincident with the turn-on of
the top MOSFETs.
Table 9. Recommended Switching Frequency for Various VIN-
to-VOUT Step-Down Scenarios
5V
IN
8V
IN
12V
IN
0.9V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
250kHz to 350kHz
The MFR_PWM_CONFIG command can be altered via
2
I C commands, but only when switching action is dis-
engaged, i.e., the module’s outputs are turned off. The
MFR_PWM_CONFIG command takes on the value stored
425kHz, 500kHz
500kHz, 575kHz
in NVM at SV
power-up, but is overridden according
IN_nn
to a resistor pin-strap applied between the FSWPH_nn_
CFG pin and SGND only if the module is configured to
respect resistor pin-strap settings (MFR_CONFIG_ALL[6]
= 0b). Table 3 highlights available resistor pin-strap and
corresponding MFR_PWM_CONFIG[2:0] settings.
OUTPUT CURRENT LIMIT PROGRAMMING
The cycle-by-cycle current limit (= VISENSE/DCR) is propor-
tional to COMPnb, which can be programmed from 1.45V
to 2.2V using the PMBus command IOUT_OC_FAULT_
LIMIT. The LTM4681 uses only the sub-milliohm sensing
to detect current levels. See page 97. The LTM4681
has two ranges of current limit programming. The value
of MFR_PWM_MODE[2] is reserved and the MFR_PWM_
MODE[7], and IOUT_OC_FAULT_LIMIT are used to set
the current limit level, see the section of the PMBus com-
mands, the device can regulate output voltage with the
peak current under the value of IOUT_OC_FAULT_LIMIT
in normal operation. In case of output current exceeding
that current limit, a OC fault will be issued. Each of the
IOUT_OC_FAULT_LIMIT ranges will affect the loop gain,
and subsequently affect the loop stability, so setting the
range of current limiting is a part of loop design.
Some combinations of FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] are not available by resistor
pin-strapping the FSWPH_nn_CFG pin. All combinations
of supported values for FREQUENCY_SWITCH and MFR_
PWM_CONFIG[2:0] can be configured by NVM program-
2
ming—or, I C transactions, provided switching action is
disengaged, i.e., the module’s outputs are turned off.
Care must be taken to minimize capacitance on SYNC
to assure that the pull-up resistor versus the capacitor
load has a low enough time constant for the application
to form a “clean” clock. (See “Open-Drain Pins”, later in
this section.)
When an LTM4681 is configured as a sync slave, it is
permissible for external circuitry to drive the SYNC_nn
pin from a current-limited source (less than 10mA), rather
than using a pull-up resistor. Any external circuitry must
The LTPowerCAD Design Tool can be used to look at the
loop stability changes if current limit range is adjusted.
The LTM4681 will automatically update the current limit
as the inductor temperature changes. Keep in mind this
operation is on a cycle-by-cycle basis and is only a func-
tion of the peak inductor current. The average inductor
current is monitored by the ADC converter and can provide
a warning if too much average output current is detected.
The overcurrent fault is detected when the COMPnb volt-
age hits the maximum value. The digital processor within
the LTM4681 provides the ability to either ignore the fault,
shut down and latch off or shut down and retry indefinitely
(hiccup). Refer to the overcurrent portion of the Operation
section for more detail. The Read_POUT can be used to
readback calculated output power.
not drive high with arbitrarily low impedance at SV
IN_nn
power-up, because the SYNC_nn output can be low imped-
ance until NVM contents have been downloaded to RAM.
Recommended LTM4681 switching frequencies of oper-
ation for many common VIN-to-VOUT applications are
indicated below. When the two channels of an LTM4681
are stepping input voltage(s) down to output voltages
whose recommended switching frequencies below are
significantly different, operation at the higher of the two
recommended switching frequencies is preferable, but
minimum on-time must be considered. (See Minimum
On-Time Considerations section.)
Rev. 0
58
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
MINIMUM ON-TIME CONSIDERATIONS
in frequency, thus the actual time delays will have some
variance.
Minimum on-time, t
, is the smallest time dura-
ON(MIN)
tion that the LTM4681 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from 0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISEn
command to minimize inrush currents associated with the
start-up voltage ramp. The soft-start feature is disabled
by setting TON_RISEn to any value less than 0.250ms.
The LTM4681 performs the necessary math internally to
assure the voltage ramp is controlled to the desired slope.
However, the voltage slope can not be any faster than the
VOUTn
INn •fOSC
tON(MIN)
<
V
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
V
fundamental limits of the power stage. The number
OUTn
of tON(MIN) steps in the ramp is equal to TON_RISE/0.1ms.
Therefore, the shorter the TON_RISEn time setting, the
more discrete steps in the soft-start ramp appear.
The minimum on-time for the LTM4681 is 60ns.
The LTM4681 PWM always operates in discontinuous
mode during the TON_RISEn operation. In discontinuous
mode, the bottom MOSFET (MBn) is turned off as soon
as reverse current is detected in the inductor. This allows
the regulator to start up into a pre-biased load.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTM4681 must enter its run state prior to soft-start.
The RUNn pins are released after the part initializes and
SV
is greater than the VIN_ON threshold. If multiple
IN_nn
There is no analog tracking feature in the LTM4681; how
-
LTM4681s are used in an application, they should be con-
figured to share the same RUNn pins. They all hold their
respective RUNn pins low until all devices initialize and
ever, two outputs can be given the same TON_RISEn and
TON_DELAYn times to achieve ratiometric rail tracking.
Because the RUNn pins are released at the same time and
both units use the same time base (SHARE_CLK), the
outputs track very closely. If the circuit is in a PolyPhase
configuration, all timing parameters must be the same.
SV exceeds the VIN_ON threshold for all devices. The
IN
SHARE_CLK_nn pin assures all the devices connected to
the signal use the same time base.
After the RUNn pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAYn) prior to ini-
tiating an output voltage ramp. Multiple LTM4681s and
other ADI parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUNn pin.
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE command. In digital servo mode, the
LTM4681 will adjust the regulated output voltage based
on the ADC voltage reading. Every 90ms the digital servo
loop will step the LSB of the DAC (nominally 1.375mV or
0.6875mV depending on the voltage range bit) until the
output is at the correct ADC reading. At power-up this
mode engages after TON_MAX_FAULT_LIMIT unless the
limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is
set to 0 (infinite), the servo begins after TON_RISE is com-
plete and VOUT has exceeded the VOUT_UV_FAULT_LIMIT.
This allows the relative delay of all parts to be synchro-
nized. The actual variation in the delay will be dependent
on the highest clock rate of the devices connected to the
SHARE_CLK pin (all Analog Devices ICs are configured
to allow the fastest SHARE_CLK signal to control the tim-
ing of all devices). The SHARE_CLK signal can be 10%
Rev. 0
59
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
This same point in time is when the output changes from
discontinuous to the programmed mode as indicated in
MFR_PWM_MODE bit 0. Refer to Figure 25 for details on
SOFT OFF (SEQUENCED OFF)
In addition to a controlled start-up, the LTM4681 also
supports controlled turn-off. The TOFF_DELAY and TOFF_
FALL functions are shown in Figure 26. TOFF_FALL is
processed when the RUNn pin goes low or if the part is
commanded off. If the part faults off or FAULTn is pulled
low externally and the part is programmed to respond
to this, the output will three-state rather than exhibiting
a controlled ramp. The output will decay as a function
of the load. The output voltage will operate as shown
in Figure 26 as long as the part is in forced continu-
ous mode and the TOFF_FALL time is sufficiently slow
that the power stage can achieve the desired slope. The
TOFF_FALL time can only be met if the power stage and
controller can sink sufficient current to assure the output
is at zero volts by the end of the fall time interval. If the
TOFF_FALL time is set shorter than the time required to
discharge the load capacitance, the output will not reach
the desired zero volt state. At the end of TOFF_FALL, the
the V
waveform under time-based sequencing. If the
OUT
TON_MAX_FAULT_LIMIT is set to a value greater than 0
and the TON_MAX_FAULT_RESPONSE is set to ignore
0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time is reached;
and
3. After the VOUT_UV_FAULT_LIMIT has been exceed
or the IOUT_OC_FAULT_LIMIT is no longer active.
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is not set
to ignore 0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time has expired
and both VOUT_UV_FAULT and IOUT_OC_FAULT are
not present.
controller will cease to sink current and V
will decay
OUT
at the natural rate determined by the load impedance. If
the controller is in discontinuous mode, the controller will
not pull negative current and the output will be pulled low
by the load, not the power stage. The maximum fall time
is limited to 1.3 seconds. The shorter TOFF_FALL time is
set, the larger the discrete steps in the TOFF_FALL ramp
will appear. The number of steps in the ramp is equal to
TOFF_FALL/0.1ms.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one
of the control loops have the digital servo mode enabled.
This will assure the various loops do not work against each
other due to slight differences in the reference circuits.
ꢀꢍꢇꢍꢆꢁꢅ ꢋꢈRꢃꢄ
ꢎꢄꢀꢈ ꢈꢊꢁꢖꢅꢈꢀ
ꢐꢍꢊꢁꢅ ꢄꢗꢆꢘꢗꢆ
ꢃꢄꢅꢆꢁꢇꢈ Rꢈꢁꢂꢙꢈꢀ
ꢆꢄꢊꢚꢎꢁꢛꢚꢐꢁꢗꢅꢆꢚꢅꢍꢎꢍꢆ
ꢆꢍꢎꢈ ꢀꢈꢅꢁꢏ ꢄꢐ
ꢑ00ꢒꢓ00ꢔꢕ
ꢀꢁꢂ ꢃꢄꢅꢆꢁꢇꢈ
ꢈRRꢄR ꢉꢊꢄꢆ
ꢆꢄ ꢋꢂꢁꢅꢈꢌ
ꢐ
ꢁꢑꢀ
ꢃ
ꢄꢗꢆ
ꢋꢌꢍꢎ ꢂꢏꢌ
ꢀꢉꢊꢇ
ꢀꢁꢂꢂꢃꢆꢇꢅꢄꢈ
ꢀꢁꢂꢂꢃꢂꢄꢅꢅ
ꢓꢜꢝꢞ ꢐꢑꢟ
ꢆꢍꢎꢈ
ꢆꢄꢊꢚRꢍꢋꢈ
ꢆꢄꢊꢚꢀꢈꢅꢁꢏ
Figure 26. TOFF_DELAY and TOFF_FALL
Figure 25. Timing Controlled VOUT Rise
Rev. 0
60
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
UNDERVOLTAGE LOCKOUT
can be pulled low by external sources indicating a fault in
some other portion of the system. The fault response is
configurable and allows the following options:
The LTM4681 is initialized by an internal threshold-based
UVLO where V must be approximately 4V and INTV
IN
CC_
n
, V
nn
, and V
must be within approximately
Ignore
20%DoDf3t3h_eninr regulated values. In addition, V
must
DD25_nn
be within approximately 7% of the targetedDvDa3l3u_ennbefore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
the RUNn pin is released. After the part has initialized, an
additional comparator monitors V . The VIN_ON thresh-
IN
old must be exceeded before the power sequencing can
Refer to the PMBus section of the data sheet and the
PMBus specification for more details.
begin. When VIN drops below the VIN_OFF threshold,
the SHARE_CLK_nn pin will be pulled low and V must
IN
The OV response is automatic. If an OV condition is
detected, TGn goes low and BGn is asserted.
increase above the VIN_ON threshold before the con-
troller will restart. The normal start-up sequence will be
allowed after the VIN_ON threshold is crossed. If FAULTn
Fault logging is available on the LTM4681. The fault log-
ging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
is held low when V is applied, ALERTnn will be asserted
IN
low even if the part is programmed to not assert ALERTnn
2
when FAULTn is held low. If I C communication occurs
before the LTM4681 is out of reset and only a portion of
the command is seen by the part, this can be interpreted
as a CML fault. If a CML fault is detected, ALERTnn is
asserted low.
If the LTM4681 internal temperature is in excess of 85°C,
writes into the NVM (other than fault logging) are not
recommended. The data will still be held in RAM, unless
the 3.3V supply UVLO threshold is reached. If the die
temperature exceeds 130°C all NVM communication is
disabled until the die temperature drops below 120°C.
It is possible to program the contents of the NVM in the
application if the VDD33_nn supply is externally driven
directly to V
or through V . This will activate the
BIAS
DD33_nn
digital portion of the LTM4681 without engaging the high
voltage sections. PMBus communications are valid in this
supply configuration. If V has not been applied to the
IN
OPEN-DRAIN PINS
LTM4681, bit 3 (NVM Not Initialized) in MFR_COMMON
will be asserted low. If this condition is detected, the part
will only respond to addresses 5A and 5B. To initialize
the part issue the following set of commands: global
address 0x5B command 0xBD data 0x2B followed by
global address 5B command 0xBD and data 0xC4. The
part will now respond to the correct address. Configure
the part as desired then issue a STORE_USER_ALL. When
The LTM4681 has the following open-drain pins:
3.3V Pins
1. FAULTn
2. SYNC_nn
3. SHARE_CLK_nn
V is applied a MFR_RESET command must be issued to
4. PGOODn
IN
allow the PWM to be enabled and valid ADC conversions
5V Pins (5V pins operate correctly when pulled to 3.3V.)
to be read.
1. RUNn
2. ALERT_nn
3. SCL_nn
4. SDA_nn
Rev. 0
FAULT DETECTION AND HANDLING
The LTM4681 FAULTn pins are configurable to indicate
a variety of faults including OV, UV, OC, OT, timing faults,
and peak over current faults. In addition, the FAULTn pins
61
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
All the above pins have on-chip pull-down transistors that
can sink 3mA at 0.4V. The low threshold on the pins is
0.8V; thus, there is plenty of margin on the digital signals
with 3mA of current. For 3.3V pins, 3mA of current is
a 1.1k resistor. Unless there are transient speed issues
associated with the RC time constant of the resistor pull-
up and parasitic capacitance to ground, a 10k resistor or
larger is generally recommended.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTM4681 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of the
SYNC_nn pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by
the lower 3 bits of the MFR_PWM_ CONFIG command.
For PolyPhase applications, it is recommended that all
the phases be spaced evenly. Thus for a 2-phase system
the signals should be 180° out of phase and a 4-phase
system should be spaced 90°.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA_nn and SCL_
nn pins with the time constant set to 1/3 the rise time is:
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
tRISE
3•100pF
RPULLUP
=
=1k
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
200kHz and 1MHz. Nominal parts will have a range beyond
this; however, operation to a wider frequency range is not
guaranteed.
The closest 1% resistor value is 1k. Be careful to minimize
parasitic capacitance on the SDA and SCL pins to avoid
communication problems. To estimate the loading capaci-
tance, monitor the signal in question and measure how
long it takes for the desired signal to reach approximately
63% of the output value. This is a one time constant. The
SYNC_nn pin has an on-chip pull-down transistor with the
output held low for nominally 500ns. If the internal oscil-
lator is set for 500kHz and the load is 100pF and a 3x time
constant is required, the resistor calculation is as follows:
The PLL has a lock detection circuit. If the PLL should
lose lock during operation, bit 4 of the STATUS_MFR_
SPECIFIC command is asserted and the ALERT_nn pin
is pulled low. The fault can be cleared by writing a 1 to
the bit. If the user does not wish to see the ALERT_nn
pin assert if a PLL_FAULT occurs, the SMBALERT_MASK
command can be used to prevent the alert.
2µs–500ns
3•100pF
RPULLUP
=
= 5k
If the SYNC signal is not clocking in the application, the
nominal programmed frequency will control the PWM
circuitry. However, if multiple parts share the SYNC_nn
pins and the signal is not clocking, the parts will not be
synchronized and excess voltage ripple on the output may
be present. Bit 10 of MFR_PADS will be asserted low if
this condition exists.
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and deter-
mine if the RC time constant is too long for the applica-
tion. If possible reduce the parasitic capacitance. If not,
reduce the pull-up resistor sufficiently to assure proper
timing. The SHARE_CLK_nn pull-up resistor has a similar
equation with a period of 10µs and a pull-down time of
1µs. The RC time constant should be approximately 3µs
or faster.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC_nn pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
Rev. 0
62
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
to avoid this problem. Multiple LTM4681s are required
to share one SYNC_nn pin in PolyPhase configurations.
For other configurations, connecting the SYNC_nn pins
to form a single SYNC signal is optional. If the SYNC_nn
pin is shared between LTM4681s, only one LTM4681 con-
trollers can be programmed with a frequency output. All
the other LTM4681s should be programmed to disable
the SYNC_nn output. However their frequency should be
programmed to the nominal desired value.
change. The error amplifier gain g varies from 1.0mS
m
to 5.76mS, and the compensation resistor RCOMPn varies
from 0kΩ to 62kΩ inside the controller. Two compensa-
tion capacitors, COMPna and COMPnb, are required in
the design and the typical ratio between COMPna and
COMPnb is 10. Also see Figure 2 Block Diagram and
Figure 27.
By adjusting the g and R
only, the LTM4681 can
m
COMPn
provide a flexible Type II compensation network to opti-
mize the loop over a wide range of output capacitors.
Adjusting the gm will change the gain of the compensation
over the whole frequency range without moving the pole
and zero location, as shown in Figure 28.
INPUT CURRENT SENSE AMPLIFIER
The LTM4681 input current sense amplifier can sense the
supply current into the V
and V
power stages pins
IN01
IN23
using an external sense resistor as shown in the Figure 2
Adjusting the R
will change the pole and zero loca-
COMP
Block Diagram. The R value can be programmed
tion, as shown in Figure 29. It is recommended that the
user determines the appropriate value for the gm and
SENSEn
using the MFR_IIN_CAL_GAIN command. Kelvin sensing
is recommended across the R resistor to eliminate
R
COMPn
using the LTPowerCAD tool.
SENSE
errors. The MFR_PWM_CONFIG [6:5] sets the input cur-
rent sense amplifier gain. See the MFR_PWM_CONFIG
section. The IIN_OC_WARN_LIMIT command sets the
value of the input current measured by the ADC, in
amperes, that causes a warning indicating the input cur-
rent is high. The READ_IIN value will be used to determine
if this limit has been exceeded. The READ_IIN command
returns the input current, in Amperes, as measured across
the input current sense resistor.
ꢂ
ꢁ
ꢀ
Rꢃꢄ
ꢐ
ꢑ
ꢄꢅ
R
ꢌꢍꢎꢏn
ꢌꢍꢎꢏna
ꢌꢍꢎꢏnb
ꢆꢇꢈꢉ ꢄꢊꢋ
ꢌ
ꢌ
ꢌꢍꢎꢏL
ꢌꢍꢎꢏH
There is an IR voltage drop from the supply to the SVIN_nn
Figure 27. Programmable Loop Compensation
pin due to the current flowing into the SV
pin. To
IN_nn
compensate for this voltage drop, the MFR_RVIN will
be automatically set to the 1Ω internal sense resistor in
the Figure 2 Block Diagram. The LTM4681 will multiply
the MFR_READ_ICHIP measurement value by this 1Ω
resistor and add this voltage to the measured voltage at
ꢒꢋꢓꢃ ꢀꢀ ꢂꢔꢕꢓꢃꢁꢅꢄꢒꢀꢔꢁ
ꢑꢄꢀꢁ
the SV
pin. Therefore, READ_VIN = VSVIN_PIN +
IN_nn
(MFR_READ_ICHIP • 1Ω) The MFR_READ_ICHIP com-
mand is used to measure the internal controller current.
Using the READ_PIN command allows for reading calcu-
lated input power.
ꢀꢁꢂRꢃꢄꢅꢃ ꢆ
ꢇ
ꢈRꢃꢉꢊꢃꢁꢂꢋ
PROGRAMMABLE LOOP COMPENSATION
ꢌꢍꢎꢏ ꢈꢐꢎ
The LTM4681 offers programmable loop compensation
to optimize the transient response without any hardware
Figure 28. Error Amp gm Adjust
Rev. 0
63
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
ꢔꢌꢈꢃ ꢀꢀ ꢂꢆꢇꢈꢃꢁꢅꢄꢔꢀꢆꢁ
ꢓꢄꢀꢁ
The COMPna series internal R
and external C
COMPn
filter sets the dominant pole-zero loop compenCsOaMtioPnna.
The internal R
value can be modified (from 0Ω to
COMPn
62kΩ) using bits[4:0] of the MFR_PWM_ COMP com-
mand. Adjust the value of RCOMPn to optimize transient
response once the final PCB layout is done and the par-
ticular C
filter capacitor and output capacitor type
COMPbn
ꢀꢁꢂRꢃꢄꢅꢃ R
ꢂꢆꢇꢈn
and value have been determined. The output capacitors
need to be selected because the various types and val-
ues determine the loop gain and phase. An output cur-
rent pulse of 20% to 80% of full-load current having a
rise time of 1µs to 10µs will produce output voltage and
COMP pin waveforms that will give a sense of the overall
loop stability without breaking the feedback loop. Placing
a power MOSFET with a resistor to ground directly across
the output capacitor and driving the gate with an appropri-
ate signal generator is a practical way to produce to a load
ꢉRꢃꢊꢋꢃꢁꢂꢌ
ꢍꢎꢏꢐ ꢉꢑꢒ
Figure 29. RCOMP Adjust
CHECKING TRANSIENT RESPONSE
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
step. The MOSFET + R
will produce output currents
SERIES
load current. When a load step occurs, V
shifts by an
OUT
approximately equal to V /R
. R
values from
OUT SERIES SERIES
amount equal to ∆I
• ESR, where ESR is the effective
LOAD
0.1Ω to 2Ω are valid depending on the current limit set-
tings and the programmed output voltage. The initial out-
put voltage step resulting from the step change in output
current may not be within the bandwidth of the feedback
loop, so this signal cannot be used to determine phase
margin. This is why it is better to look at the COMP pin
signal which is in the feedback loop and is the filtered and
compensated control loop response. The gain of the loop
will be increased by increasing RCOMP and the bandwidth of
the loop will be increased by decreasing CCOMPna. If RCOMP
series resistance of C . ∆I
also begins to charge or
OUT
discharge C
generating tLhOeAfDeedback error signal that
OUT
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recov-
OUT
ery time V
can be monitored for excessive overshoot
OUT
or ringing, which would indicate a stability problem. The
availability of the COMP pin not only allows optimization
of control loop behavior but also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly
second order system, phase margin and/or damping fac-
tor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated by
examining the rise time at the pin. The COMPna external
capacitor shown in the Typical Application circuit will pro-
vide an adequate starting point for most applications. The
programmable parameters that affect loop gain are the
voltage range, bit[1] of the MFR_PWM_MODE command,
the current range bit[7] of the MFR_PWM_MODE com-
is increased by the same factor that C is decreased, the
TH
zero frequency will be kept the same, thereby keeping the
phase shift the same in the most critical frequency range of
the feedback loop. The gain of the loop will be proportional
to the transconductance of the error amplifier which is set
using bits[7:5] of the MFR_PWM_COMP command. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. A second, more severe tran-
sient is caused by switching in loads with large (>1µF)
supply bypass capacitors. The discharged bypass capaci-
tors are effectively put in parallel with COUT, causing a
mand, the g of the PWM channel amplifier bits [7:5] of
m
MFR_PWM_COMP, and the internal R
compensation
COMP
rapid drop in V . No regulator can alter its delivery of
OUT
resistor, bits[4:0] of MFR_PWM_COMP. Be sure to estab-
current quickly enough to prevent this sudden step change
in output voltage if the load switch resistance is low and
lish these settings prior to compensation calculation.
Rev. 0
64
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
2
it is driven quickly. If the ratio of C
to C
is greater
CONNECTING THE USB TO I C/SMBUS/PMBUS
CONTROLLER TO THE LTM4681 IN SYSTEM
LOAD
OUT
than 1:50, the switch rise time should be controlled so that
the load rise time is limited to approximately 25 • C
.
The ADI USB-to-I2C/SMBus/PMBus adapter (DC1613A
or equivalent) can be interfaced to the LTM4681 on
the user’s board for programming, telemetry and sys
LOAD
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
-
tem debug. The adapter, when used in conjunction with
LTpowerPlay, provides a powerful way to debug an entire
power system. Faults are quickly diagnosed using telem-
etry, fault status commands and the fault log. The final
configuration can be quickly developed and stored to the
LTM4681 EEPROM. Figure 30 illustrates the application
schematic for powering, programming and communica-
PolyPhase Configuration
When configuring a PolyPhase rail with multiple LTM4681s,
the user must share the SYNC, COMP, SHARE_CLK, FAULT,
and ALERT pins of these parts. Be sure to use pull-up resis-
tors on FAULT, SHARE_CLK and ALERT. One of the part’s
SYNC pins must be set to the desired switching frequency,
and all other FREQUENCY_SWITCH commands must be set
to External Clock. If an external oscillator is provided, set
the FREQUENCY_SWITCH command to External Clock for
all parts. The relative phasing of all the channels should be
spaced equally. The MFR_RAIL_ADDRESS of all the devices
should be set to the same value.
2
tion with one or more LTM4681s via the ADI I C/SMBus/
PMBus adapter regardless of whether or not system
power is present. If system power is not present, the
dongle will power the LTM4681 through the VDD33_nn
supply pin. To initialize the part when V
is not applied
INnn
and the V
pin is powered, use global address 0x5B
DD33_nn
command 0xBD data 0x2B followed by address 0x5B
command 0xBD data 0xC4. The LTM4681 can now com-
municate with the internal EEPROM and read the project
file. To write the updated project file to the NVM issue
+
Multiple channels need to tie all the VSENSEn pins
–
together, and all the V
pins together, COMPna and
COMPnb pins togethSeErNaSsEnwell. Do not assert bit[4] of
MFR_CONFIG_ALL except in a PolyPhase application. See
application example Figure 50.
a STORE_USER_ALL command. When V is applied, a
IN
MFR_RESET must be issued to allow the PWM POWER
to be enabled and valid ADCs to be read.
ꢀ
ꢁꢂ
ꢚꢑꢙ
ꢙꢐꢂꢑRꢐꢚꢚꢓR
ꢒꢓꢉꢃꢓR
ꢊ00ꢝ
ꢊ00ꢝ
ꢀ
ꢀ
ꢁꢂnn
ꢁꢈꢐꢚꢉꢑꢓꢃ
ꢄ.ꢄꢀ
ꢈꢃꢉ
ꢈꢙꢚ
ꢀ
ꢃꢃꢄꢄꢅnn
ꢃꢃꢆꢇꢅnn
ꢑꢔ0ꢊ0ꢊꢕ
ꢊꢋꢌ
ꢚꢑꢎꢛꢘꢖꢊ
ꢊꢠꢆ
ꢊ0ꢝ
ꢊ0ꢝ
ꢈꢃꢉꢅnn
ꢈꢙꢚꢅnn
ꢜꢔꢅnn ꢔꢍꢂꢃꢠꢈꢍꢂꢃꢅnn
ꢑꢐ ꢚꢑꢙ ꢃꢙꢊꢘꢊꢄ
ꢆ
ꢞꢈꢟ ꢑꢐ ꢁ ꢙꢠꢈꢎꢟꢡꢢꢠꢔꢎꢟꢡꢢ
ꢙꢐꢂꢑRꢐꢚꢚꢓR
ꢀ
ꢀ
ꢁꢂnn
ꢀ
ꢃꢃꢄꢄꢅnn
ꢃꢃꢆꢇ
ꢑꢔ0ꢊ0ꢊꢕ
ꢊꢋꢌ
ꢚꢑꢎꢛꢘꢖꢊ
ꢊꢠꢆ
ꢈꢃꢉꢅnn
ꢈꢙꢚꢅnn
ꢀꢍꢈ ꢎꢉꢏ ꢐꢂ ꢑꢒꢓ ꢑꢔ0ꢊ0ꢊꢕ ꢁꢈ ꢖꢀ ꢁꢌ ꢀ ꢗ ꢊꢘꢀ
ꢙꢒꢉꢂꢍꢓ ꢑꢒꢓ RꢓꢈꢁꢈꢑꢐR ꢃꢁꢀꢁꢃꢓR ꢐꢂ ꢑꢒꢓ ꢔꢌꢓꢑ ꢍꢉꢑꢓ
ꢚꢑꢎꢛꢘꢖꢊ ꢒꢉꢈ ꢑꢜꢐ ꢁꢂꢑꢓRꢂꢉꢚ ꢙꢐꢂꢑRꢐꢚꢚꢓRꢈ
ꢁꢂ
ꢜꢔꢅnn ꢔꢍꢂꢃꢠꢈꢍꢂꢃꢅnn
ꢛꢘꢖꢊ ꢌꢄ0
Figure 30. Controller Connection
Rev. 0
65
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
Because of the adapter’s limited current sourcing capabil-
ity, only the LTM4681s, their associated pull-up resistors
and the I2C pull-up resistors should be powered from
the VDD33 3.3V supply. In addition any device sharing
demo boards, or a customer target system. The software
also provides an automatic update feature to keep the
revisions current with the latest set of device drivers and
documentation.
2
the I C bus connections with the LTM4681 should not
A great deal of context sensitive help is available with
LTpowerPlay along with several tutorial demos. :
have body diodes between the SDA/SCL pins and their
respective V node because this will interfere with bus
DD
communication in the absence of system power. If V is
applied, the DC1613A will not supply the power toINthe
LTM4681s on the board. It is recommended the RUNn
pins be held low or no voltage configuration resistors
inserted to avoid providing power to the load until the
part is fully configured.
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTM4681 internal controllers have one deep buffer
to hold the last data written for each supported com-
mand prior to processing as shown in Figure 32, Write
Command Data Processing. When the part receives a new
command from the bus, it copies the data into the Write
Command Data Buffer, indicates to the internal processor
that this command data needs to be fetched, and con-
verts the command to its internal format so that it can be
executed. Two distinct parallel blocks manage command
buffering and command processing (fetch, convert, and
execute) to ensure the last data written to any command
is never lost. Command data buffering handles incoming
PMBus writes by storing the command data to the Write
Command Data Buffer and marking these commands for
future processing. The internal processor runs in parallel
and handles the sometimes slower task of fetching, con-
verting and executing commands marked for processing.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long rela-
tive to PMBus timing. If the part is busy processing a
command, and new command(s) arrive, execution may
be delayed or processed in a different order than received.
The part indicates when internal calculations are in pro-
cess via bit 5 of MFR_COMMON (“calculations not pend-
ing”). When the part is busy calculating, bit 5 is cleared.
When this bit is set, the part is ready for another com-
mand. An example polling loop is provided in Figure 33
which ensures that commands are processed in order
while simplifying error handling routines.
The LTM4681 is fully isolated from the host PC’s ground
by the DC1613A.The 3.3V from the adapter and the
LTM4681 V
pin must be driven to each LTM4681
DD33_nn
internal controllers with a separate PFET. If both V and
VBIAS are not on, the VDD33_nn pins can be in pIaNrallel
because the on-chip LDO is off. The controller’s 3.3V
current limit is 100mA but typical V
currents are
DD33_nn
does back drive the INTV /
under 15mA. The V
DD33_nn
CC
V
pin. Normally this is not an issue if V is open.
BIAS
IN
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
LTpowerPlay (Figure 31) is a powerful Windows-based
development environment that supports Analog Devices
digital power system management ICs including the
LTM4681. The software supports a variety of differ-
ent tasks. LTpowerPlay can be used to evaluate Analog
Devices ICs by connecting to a demo board or the user
application. LTpowerPlay can also be used in an offline
mode (with no hardware present) in order to build mul-
tiple IC configuration files that can be saved and reloaded
at a later time. LTpowerPlay provides unprecedented diag-
nostic and debug features. It becomes a valuable diagnos-
tic tool during board bring-up to program or tweak the
power system or to diagnose power issues when bring up
2
rails. LTpowerPlay utilizes Analog Devices’s USB-to-I C/
SMBus/PMBus adapter to communication with one of the
many potential targets including the DC2924A, DC3082A
Rev. 0
66
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
Figure 31. LTpowerPlay Screen Shot
ꢂꢄꢀ
ꢌRꢅꢇꢁ ꢂꢃꢄꢄꢈꢆꢀ
ꢀꢈꢇꢈ ꢍꢎꢏꢏꢁR
ꢊꢄꢍꢛꢜ
ꢌRꢅꢇꢁ
Channel #
GUI
ꢀꢁꢂꢃꢀꢁR
ꢅꢆꢇꢁRꢆꢈꢉ
Identity
ꢊꢈꢐꢁ
ꢘ
ꢘ
ꢘ
0ꢑ00
0ꢑꢒꢓ
ꢊRꢃꢂꢁꢋꢋꢃR
ꢂꢄꢀꢋ
0
1
2
3
U0:A0
U0:A1
U0:B0
U0:B1
ꢏꢁꢇꢂꢝꢞ
ꢂꢃꢆꢚꢁRꢇ
ꢀꢈꢇꢈ
ꢈꢆꢀ
ꢁꢟꢁꢂꢎꢇꢁ
ꢀꢈꢇꢈ
ꢄꢎꢟ
ꢚꢃꢎꢇꢙꢂꢃꢄꢄꢈꢆꢀ
ꢘ
ꢘ
ꢘ
ꢄꢏRꢙRꢁꢋꢁꢇ
ꢑꢓ
0ꢑꢏꢀ
ꢋ
R
ꢂꢈꢉꢂꢎꢉꢈꢇꢅꢃꢆꢋ
ꢊꢁꢆꢀꢅꢆꢐ
ꢔꢕꢖꢓ ꢏꢗꢒ
Figure 32. Write Command Data Processing
Rev. 0
67
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads.
It may also generate a BUSY fault and ALERT notifica-
tion, or stretch the SCL clock low. For more information
refer to PMBus Specification v1.1, Part II, Section 10.8.7
and SMBus v2.0 section 4.3.3. Clock stretching can be
enabled by asserting bit 1 of MFR_CONFIG_ ALL. Clock
stretching will only occur if enabled and the bus com-
munication speed exceeds 100kHz.
or data). An example of a robust command write algo-
rithm for the VOUT_COMMAND register is provided in
Figure 33.
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERT notification. A simple way to achieve this
is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD() subroutine. The above polling mechanism allows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to the
Application Note section.
// wait until chip is not busy
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simple solution that ensures robust communication with-
out clock stretching. At bus speeds in excess of 100kHz,
it is strongly recommended that the part be configured to
enable clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults as described in the PMBus Specification v1.1,
Par II, Section 10.8.7 is required to communicate The
LTM4681 is not recommended in applications with bus
speeds in excess of 400kHz.
// now the part is ready to receive the next
command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_
COMMAND to 2V
Figure 33. Example of a Command Write of VOUT_COMMAND
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat com-
plex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_
COMMON register. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON
(‘chip not busy’). When the part is busy specifically
THERMAL CONSIDERATIONS AND OUTPUT
CURRENT DERATING
The thermal resistances reported in the Pin Configuration
section of this data sheet are consistent with those
parameters defined by JESD51-12 and are intended for
use with finite element analysis (FEA) software model-
ing tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formed on a µModule package mounted to a hardware
test board defined by JESD51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
because it is in a transitional V
state (margining hi/lo,
OUT
power off/on, moving to a new output voltage set point,
etc.) it will clear bit 4 of MFR_COMMON (‘output not in
transition’). When internal calculations are in process, the
part will clear bit 5 of MFR_COMMON (‘calculations not
pending’). These three status bits can be polled with a
PMBus read byte of the MFR_COMMON register until all
three bits are set. A command immediately following the
status bits being set will be accepted without NACKing or
generating a BUSY fault/ALERT notification. The part can
NACK commands for other reasons, however, as required
by the PMBus spec (for instance, an invalid command
Rev. 0
68
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
Many designers may opt to use laboratory equipment
of the package, but there is always heat flow out into
the ambient environment. As a result, this thermal
resistance value may be useful for comparing pack-
ages but the test conditions don’t generally match the
user’s application.
and a test vehicle such as the demo board to predict the
µModule regulator’s thermal performance in their appli
-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the Pin
Configuration section are in-and-of themselves not relevant
to providing guidance of thermal performance; instead, the
derating curves provided later in this data sheet can be
used in a manner that yields insight and guidance per-
taining to one’s application-usage, and can be adapted to
correlate thermal performance to one’s own application.
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule regulator are on the bottom of the
package, it is rare for an application to operate such
that most of the heat flows from the junction to the top
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD51-12; these coefficients
are quoted or paraphrased below:
of the part. As in the case of θ
, this value may
JCbottom
be useful for comparing packages but the test condi-
tions don’t generally match the user’s application.
1. θ , the thermal resistance from junction to ambient,
4
θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resis-
tance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
JA
is the natural convection junction-to-ambient air ther-
mal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD51-9 defined test board, which
does not reflect an actual application or viable operat-
ing condition.
and is really the sum of the θ
and the thermal
JCbottom
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD51-9.
2. θ , the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all
of the component power dissipation flowing through
the bottom of the package. In the typical µModule
regulator, the bulk of the heat flows out the bottom
A graphical representation of the aforementioned thermal
resistances is given in Figure 34; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
ꢑꢒꢓꢐꢔꢏꢕꢓꢖꢔꢕꢖꢗꢇꢜꢏꢍꢓꢔ ꢔꢝꢍRꢇꢗꢞ Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ ꢐꢕꢇꢚꢕꢓꢍꢓꢔꢘ
ꢑꢒꢓꢐꢔꢏꢕꢓꢖꢔꢕꢖꢐꢗꢘꢍ ꢙꢔꢕꢚꢛ
Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ
ꢐꢗꢘꢍ ꢙꢔꢕꢚꢛꢖꢔꢕꢖꢗꢇꢜꢏꢍꢓꢔ
Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ
ꢑꢒꢓꢐꢔꢏꢕꢓꢖꢔꢕꢖꢜꢕꢗRꢌ Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ
ꢑꢒꢓꢐꢔꢏꢕꢓ
ꢗꢇꢜꢏꢍꢓꢔ
ꢑꢒꢓꢐꢔꢏꢕꢓꢖꢔꢕꢖꢐꢗꢘꢍ
ꢙꢜꢕꢔꢔꢕꢇꢛ Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ
ꢐꢗꢘꢍ ꢙꢜꢕꢔꢔꢕꢇꢛꢖꢔꢕꢖꢜꢕꢗRꢌ
Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ
ꢜꢕꢗRꢌꢖꢔꢕꢖꢗꢇꢜꢏꢍꢓꢔ
Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ
ꢀꢁꢂꢃ ꢄꢅꢅ
ꢆꢇꢈꢉꢊꢋe ꢌꢍꢎꢏꢐꢍ
Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients
Rev. 0
69
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal oper-
ating conditions of a µModule regulator. For example, in
normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
of derating curves provided in later sections of this data
sheet, along with well-correlated JESD51-12-defined θ
values provided in the Pin Configuration section of this
data sheet.
The 5V, 8V, and 12V power loss curves in Figure 35,
Figure 36 and Figure 37, respectively, can be used in coor
-
dination with the load current derating curves in Figure 41
to Figure 46 for calculating an approximate θ thermal
JA
resistance for the LTM4681 with various airflow condi-
tions and without heat sinks. These thermal resistances
represent demonstrated performance of the LTM4681
on hardware; a 8-layer FR4 PCB measuring 215mm ×
160mm × 1.6mm using 2oz copper on all layers. The
power loss curves are taken at room temperature, and
are increased with multiplicative factors of 1.35 when the
junction temperature reaches 125°C. The derating curves
are plotted with the LTM4681’s paralleled outputs initially
sourcing up to 120A and the ambient temperature at 25°C.
The output voltages are 0.9V, 1.5V and 3.3V. These are
chosen to include the lower and higher output voltage
ranges for correlating the thermal resistance. Thermal
models are derived from several temperature measure-
ments in a controlled temperature chamber along with
thermal modeling analysis. The junction temperatures are
monitored while ambient temperature is increased with
and without airflow.
for θ
and θ , respectively. In practice, power
JCbottom
JCtop
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4681, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to differ-
ent junctions of components or die are not exactly linear
with respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet: (1) Initially, FEA soft-
ware is used to accurately build the mechanical geometry
of the LTM4681 and the specified PCB with all of the cor-
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD51-9
and JESD51-12 to predict power loss heat flow and
temperature readings at different interfaces that enable
the calculation of the JEDEC-defined thermal resistance
values; (3) the model and FEA software is used to evaluate
the LTM4681 with heat sink and airflow; (4) having solved
for and analyzed these thermal resistance values and
simulated various operating conditions in the software
model, a thorough laboratory evaluation replicates the
simulated conditions with thermocouples within a con-
trolled environment chamber while operating the device
at the same power loss as that which was simulated. The
outcome of this process and due diligence yields the set
The power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at 125°C maximum while lowering output cur-
rent or power while increasing ambient temperature. The
decreased output current decreases the internal module
loss as ambient temperature is increased. The monitored
junction temperature of 125°C minus the ambient operat-
ing temperature specifies how much module temperature
rise can be allowed. As an example in Figure 43, the load
current is derated to ~90A at ~65°C ambient with no air
or heat sink and the room temperature (25°C) power loss
for this 12V to 1.5V
at 90A
condition is ~9.5W. A
OUT
12.8W lossIiNs calculated by muOltUipTlying the ~9.5W room
temperature loss from the 12V to 1.5V
curve at 90A (Figure 37), with the 1.35 multiplying factor.
power loss
IN
OUT
Rev. 0
70
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
If the 60°C ambient temperature is subtracted from the
125°C junction temperature, then the difference of 65°C
divided by 12.8W yields a thermal resistance, θJA, of
5°C/W—in good agreement with the value derived from
thermal simulation shown in the Pin Configuration sec-
tion. Table 10, Table 11 and Table 12 provide equivalent
thermal resistances for 0.9V, 1.5V, and 3.3V outputs with
and without airflow. The derived thermal resistances in
Table 10 through Table 12 for the various conditions can
be multiplied by the calculated power loss as a function
of ambient temperature to derive temperature rise above
ambient, thus maximum junction temperature. Room
temperature power loss can be derived from the efficiency
curves in the Typical Performance Characteristics sec-
tion and adjusted with the above ambient temperature
multiplicative factors.
Table 10 through Table 12: Output Current Derating
Table 10. 0.9V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 35 to Figure 37
Figure 35 to Figure 37
Figure 35 to Figure 37
AIRFLOW (LFM)
HEAT SINK
None
θ
JA
θ
JA
θ
JA
(°C/W)
IN
Figure 38 to Figure 40
Figure 38 to Figure 40
Figure 38 to Figure 40
5, 8, 12
5, 8, 12
5, 8, 12
0
5
4
3
200
400
None
None
Table 11. 1.5V Output
DERATING CURVE
V
IN
(V)
POWER LOSS CURVE
Figure 35 to Figure 37
Figure 35 to Figure 37
Figure 35 to Figure 37
AIRFLOW (LFM)
HEAT SINK
None
(°C/W)
Figure 41 to Figure 43
Figure 41 to Figure 43
Figure 41 to Figure 43
5, 8, 12
5, 8, 12
5, 8, 12
0
5
4
3
200
400
None
None
Table 12. 3.3V Output
DERATING CURVE
V
(V)
POWER LOSS CURVE
Figure 35 to Figure 37
Figure 35 to Figure 37
Figure 35 to Figure 37
AIRFLOW (LFM)
HEAT SINK
None
(°C/W)
IN
Figure 44 to Figure 46
Figure 44 to Figure 46
Figure 44 to Figure 46
5, 8, 12
5, 8, 12
5, 8, 12
0
5
4
3
200
400
None
None
Rev. 0
71
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
Rev. 0
72
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
Rev. 0
73
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
Rev. 0
74
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION-DERATING CURVES
DERATING CURVES
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
0.
.0
.
.
.
.
.
0
0
0
0.
.0
.
.
.
.
.
0
0
0
0.
.0
.
.
.
.
.
0
0
0
00
0
00
0
00
0
0
0
0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ00 ꢀꢀ0 ꢀꢁ0 ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ00 ꢀꢀ0 ꢀꢁ0 ꢀꢁ0
0
ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ0 ꢀ00 ꢀꢀ0 ꢀꢁ0 ꢀꢁ0
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢁ
ꢀꢁꢂꢃ ꢄꢅꢆ
Figure 35. 5VIN Power Loss Curve
Figure 36. 8VIN Power Loss Curve
Figure 37. 12VIN Power Loss Curve
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
0
0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢀ0
ꢀꢁꢂꢃ ꢄꢅꢂ
Figure 38. 5VIN to 0.9VOUT
Derating Curve, No Heatsink
Figure 39. 8VIN to 0.9VOUT Derating
Curve, No Heatsink
Figure 40. 12VIN to 0.9VOUT Derating
Curve, No Heatsink
Rev. 0
75
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
DERATING CURVES
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
ꢀ0
0
0
0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃ ꢄꢀꢃ
ꢀꢁꢂꢃ ꢄꢀꢅ
ꢀꢁꢂꢃ ꢄꢀꢅ
Figure 41. 5VIN to 1.5VOUT
Derating Curve, No Heat Sink
Figure 42. 8VIN to 1.5VOUT Derating
Curve, No Heat Sink
Figure 43. 12VIN to 1.5VOUT
Derating Curve, No Heat Sink
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀꢁ0
ꢀꢁ0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
ꢀ0
ꢀ0
0
0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃ ꢄꢀꢀ
ꢀꢁꢂꢃ ꢄꢀꢅ
ꢀꢁꢂꢃ ꢄꢀꢁ
Figure 46. 12VIN to 3.3VOUT
Derating Curve, No Heat Sink
Figure 44. 5VIN to 3.3VOUT
Derating Curve, No Heat Sink
Figure 45. 8VIN to 3.3VOUT
Derating Curve, No Heat Sink
Rev. 0
76
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
EMI PERFORMANCE
SAFETY CONSIDERATIONS
The LTM4681 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
The SWn pin provides access to the midpoint of the power
MOSFETs in LTM4681’s power stages.
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
Connecting an optional series RC network from SWn to
GND can dampen high frequency (~30MHz+) switch node
ringing caused by parasitic inductances and capacitances
in the switched-current paths. The RC network is called a
snubber circuit because it dampens (or “snubs”) the reso-
nance of the parasitics, at the expense of higher power
loss. To use a snubber, choose first how much power to
allocate to the task and how much PCB real estate is avail-
able to implement the snubber. For example, if PCB space
allows a low inductance 0.5W resistor to be used then the
capacitor in the snubber network (CSW) is computed by:
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET
fails, then turning it off will not resolve the overvoltage,
thus the internal bottom MOSFET will turn on indefinitely
trying to protect the load. Under this fault condition, the
input voltage will source very large currents to ground
through the failed internal top MOSFET and enabled
internal bottom MOSFET. This can cause excessive heat
and board damage depending on how much power the
input voltage can deliver to this system. A fuse or circuit
breaker can be used as a secondary fault protector in
this situation. The device does support over current and
overtemperature protection.
PSNUB
CSW
=
V
2 • fSW
INn(MAX)
where V
is the maximum input voltage that the
INn(MAX)
input to the power stage (V ) will see in the application,
INn
and f is the DC/DC converter’s switching frequency
SW
of operation. C should be NPO, C0G or X7R-type (or
SW
LAYOUT CHECKLIST/EXAMPLE
better) material.
The high integration of LTM4681 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
The snubber resistor (R ) value is then given by:
SW
5nH
CSW
RSW
=
n
Use large PCB copper areas for high current paths,
The snubber resistor should be low ESL and capable of
withstanding the pulsed currents present in snubber cir-
cuits. A value between 0.7Ω and 4.2Ω is normal.
including V , GND and V
. It helps to minimize
INn
OUTn
the PCB conduction loss and thermal stress.
n
Place high frequency ceramic input and output capac-
A 2.2nF snubber capacitor is a good value to start with in
series with the snubber resistor to ground. The no load
input quiescent current can be monitored while selecting
different RC series snubber components to get a increased
power loss versus switch node ringing attenuation.
itors next to the V , GND and V
pins to minimize
INn
OUTn
high frequency noise.
n
n
Place a dedicated power ground layer underneath the
module.
To minimize the via conduction loss and reduce mod-
ule thermal stress, use multiple vias for interconnec-
tion between top layer and other power layers.
Rev. 0
77
For more information www.analog.com
LTM4681
APPLICATIONS INFORMATION
–
For parallel modules, tie the VOUTn, ,VOSNSn+/VOSNSn
voltage-sense differential pair lines, RUNn, , COMPna,
n
Do not put vias directly on pads, unless they are
capped or plated over.
n
n
Use a separate SGND copper plane for components
connected to signal pins. Connect SGND to GND local
to the LTM4681.
COMPnb pin together. The user must share the
SYNC_nn, SHARE_CLK_nn, FAULTn, and ALERT_nn
pins of these parts. Be sure to use pull-up resistors
on FAULTn, SHARE_CLK_nn and ALERT_nn.
n
Use Kelvin sense connections across the input R
resistor if input current monitoring is used.
SENSE
n
Bring out test points on the signal pins for monitoring.
Figure 47 gives a good example of the recommended
layout.
ꢀ
ꢀ
ꢆꢂꢇ
ꢀ
ꢀ
ꢀ
ꢀ
ꢆꢂꢇ
ꢀ ꢀ
ꢃꢄꢅꢉ ꢃꢄꢅꢊ
ꢃꢄꢅ0 ꢃꢄꢅꢈ
ꢃꢄꢅꢉ ꢃꢄꢅꢊ
ꢃꢄꢅ0 ꢃꢄꢅꢈ
ꢆꢂꢇ
ꢆꢂꢇ
ꢆꢂꢇ
ꢆꢂꢇ
ꢀ
ꢁꢂ
ꢀ
ꢀ
ꢁꢂ
ꢀ
ꢁꢂ
ꢁꢂ
ꢆꢂꢇ
ꢆꢂꢇ
ꢋꢌꢍꢈ ꢎꢋꢏꢐ
ꢋꢌꢍꢈ ꢎꢋꢏꢐ
(a) LTM4681 TOP LAYER
(b) LTM4681 BOTTOM LAYER
Figure 47. Recommended PCB Layout Package Top View
Rev. 0
78
For more information www.analog.com
LTM4681
TYPICAL APPLICATIONS
V
DD33_01
4.7µF
22µF
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
10k
10k 4.99k
10k
10k
10k
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
4.7µF
SW0
0.9V AT 31.25A
V
OUT0
+
+
100µF
×5
470µF
×2
V
V
V
, 6V TO 16V
OSNS0
IN
+
–
IN_01
LOAD
+
22µF
×6
–
1mΩ
1mΩ
150µF
OSNS0
1Ω
IN_01
V
IN01
SW1
SV
IN_01
1V AT 31.25A
V
1µF
OUT1
+
+
100µF
×5
470µF
×2
V
V
OSNS1
+
IN_23
IN_23
LOAD
–
OSNS1
–
1Ω
V
SW2
IN23
SV
IN_23
1.2V AT 31.25A
V
OUT2
+
1µF
+
100µF
×5
470µF
×2
V
V
OSNS2
LTM4681
LOAD
V
IN_VBIAS
V
–
DD33_01
OSNS2
RUNP
RUN0
RUN1
RUN2
RUN3
10k
SW3
10k
1.8V AT 31.25A
V
OUT3
+
ON_OFF_CONFIG
+
100µF
×5
V
V
OSNS3
470µF
×2
10k
FAULT0
FAULT1
FAULT2
FAULT3
LOAD
–
OSNS3
FAULT INTERRUPTS
10k
GND
PGOOD0
PGOOD1
PGOOD2
PGOOD3
10k
10k
SGND_23
SGND_01
SGND
10k
POWER GOOD
4681 F48
2200pF
2200pF
100pF
2200pF
100pF
2200pF
32.4k
22.6k
100pF
100pF
14.3k
14.3k
14.3k
14.3k
14.3k
14.3k
1.65k
22.6k
1.65k
2.43k
3.24k
6.34k
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢈꢁ ꢊꢆ ꢋꢌꢍ ꢎ0ꢏꢏꢐ
ꢇꢑꢉꢒꢆ ꢉꢓꢓRꢆꢇꢇꢔꢋ00ꢕꢋꢋꢋ0ꢕRꢖꢗ ꢃꢁR ꢘꢍꢙ ꢓꢆꢒꢄꢀꢆ
ꢀꢁRꢂꢃꢄꢅꢁꢆꢇꢂꢈꢉꢉ ꢊꢋꢌꢍꢎꢏ ꢐꢑ
ꢒꢉꢈꢓꢔ ꢈꢕꢕRꢔꢒꢒꢖꢑ00ꢂꢑꢑꢑꢑꢂRꢗꢘ ꢁꢄR 0ꢙꢑ ꢕꢔꢓꢆꢃꢔ
Figure 48. Quad 31.25A DC/DC µModule Regulator with I2C/SMBus/PMBus Serial Interface
Rev. 0
79
For more information www.analog.com
LTM4681
TYPICAL APPLICATIONS
V
DD33_01
4.7µF
22µF
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
10k
10k 4.99k
10k
10k
10k
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
4.7µF
SW0
OUT0
0.75V AT 60A
V
V
, 6V TO 16V
IN
100µF
+
–
IN_01
×3
+
+
22µF
×6
1mΩ
1mΩ
150µF
+
V
V
OSNS0
V
V
OSNS0
OSNS0
1Ω
IN_01
+
470µF
×3
LOAD
–
V
IN01
OSNS0
–
SV
IN_01
1µF
SW1
OUT1
V
+
IN_23
IN_23
100µF
×3
+
+
–
V
V
V
V
OSNS1
OSNS1
OSNS0
OSNS0
1Ω
–
–
V
IN23
SV
IN_23
SW2
OUT2
1V AT 60A
1µF
V
100µF
×3
LTM4681
V
V
IN_VBIAS
RUNP
DD33_01
+
V
V
OSNS2
OSNS2
10k
RUN0
RUN1
RUN2
RUN3
+
470µF
×3
LOAD
10k
–
10k
ON_OFF_CONFIG
10k
SW3
OUT3
FAULT0
FAULT1
FAULT2
FAULT3
V
100µF
×3
+
+
–
V
V
V
V
OSNS3
OSNS3
OSNS2
OSNS2
FAULT INTERRUPTS
–
10k
PGOOD0
PGOOD1
PGOOD2
PGOOD3
GND
PGOOD_0.75V
PGOOD_1V
SGND_23
SGND_01
10k
SGND
4681 F49
32.4k
2200pF
2200pF
2200pF
100pF
2200pF
100pF
22.6k
14.3k
100pF
100pF
f = 250kHz
14.3k
14.3k
14.3k
32.4k
787Ω
12.7k
2.43k
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢈꢁ ꢊꢆ ꢋꢌꢍ ꢎ0ꢏꢏꢐ
ꢇꢑꢉꢒꢆ ꢉꢓꢓRꢆꢇꢇꢔꢋ00ꢕꢋꢋꢋ0ꢕRꢖꢗ ꢃꢁR ꢘꢍꢙ ꢓꢆꢒꢄꢀꢆ
ꢀꢁRꢂꢃꢄꢅꢁꢆꢇꢂꢈꢉꢉ ꢊꢋꢌꢍꢎꢏ ꢐꢑ
ꢒꢉꢈꢓꢔ ꢈꢕꢕRꢔꢒꢒꢖꢑ00ꢂꢑꢑꢑꢑꢂRꢗꢘ ꢁꢄR 0ꢙꢑ ꢕꢔꢓꢆꢃꢔ
Figure 49. 0.75V and 1V Outputs at 60A with Providing I2C/SMBus/PMBus Serial Interface
Rev. 0
80
For more information www.analog.com
LTM4681
TYPICAL APPLICATIONS
V
ꢁ
DD33A_01
ꢀ
ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
4.7µF
22µF
4.99k
4.99k
SYNC
4.99k
SDA
4.99k
SCL
4.99k
ALERT
SHARE_CLK
4.7µF
V
IN
, 6V TO 16V
+
SW0
OUT0
IN_01
+
22µF
×6
V
150µF
1mΩ
1mΩ
100µF
×3
–
1Ω
1Ω
IN_01
+
470µF
×2
V
IN01
+
+
–
V
V
V
V
OSNS0
OSNS0
OSNS
OSNS
SV
IN_01
–
1µF
SW1
OUT1
+
IN_23
IN_23
V
100µF
×3
–
+
+
V
IN23
V
V
V
V
OSNS1
OSNS1
OSNS
OSNS
–
–
SV
IN_23
1µF
SW2
OUT2
V
100µF
×3
LTM4681
V
IN_VBIAS
RUNP
V
+
470µF
×2
DD33A_01
+
+
RUN0
RUN1
RUN2
RUN3
V
V
V
V
OSNS2
OSNS2
OSNS
OSNS
–
–
4.99k
SW3
OUT3
ON_OFF_CONFIG
4.99k
V
100µF
×3
FAULT0
FAULT1
FAULT2
FAULT3
+
+
V
V
V
V
OSNS3
OSNS3
OSNS
OSNS
FAULT INTERRUPTS
4.99k
–
–
PGOOD0
PGOOD1
PGOOD2
PGOOD3
GND
SGND_23
SGND_01
SGND
PGOOD_0.9V
COMPb
COMPa
32.4k
22.6k
4700pF
100pF
14.3k
14.3k
14.3k
32.4k
14.3k
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢈꢁ ꢊꢆ ꢋꢌꢍ ꢎ0ꢏꢏꢐ
ꢇꢑꢉꢒꢆ ꢉꢓꢓRꢆꢇꢇꢔꢋ00ꢕꢋꢋꢋ0ꢕRꢖꢗ ꢃꢁR ꢘꢍꢙ ꢓꢆꢒꢄꢀꢆ
1.65k
1.65k
1.65k
ꢀꢁRꢂꢃꢄꢅꢁꢆꢇꢂꢈꢉꢉ ꢊꢋꢌꢍꢎꢏ ꢐꢑ
ꢒꢉꢈꢓꢔ ꢈꢕꢕRꢔꢒꢒꢖꢑ00ꢂꢑꢑꢑꢑꢂRꢗꢘ ꢁꢄR 0ꢙꢑ ꢕꢔꢓꢆꢃꢔ
ꢁ
ꢀ
ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
+
V
OSNS
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
4.7µF
22µF
0.9V AT 250A
LOAD
ALERT SHARE_CLK SYNC
SDA
SCL
4.7µF
–
V
IN
, 6V TO 16V
V
OSNS
+
SW0
OUT0
IN_01
+
22µF
×6
V
150µF
1mΩ
1mΩ
100µF
×3
–
1Ω
1Ω
IN_01
+
470µF
×2
V
IN01
+
+
V
V
V
V
OSNS0
OSNS0
OSNS
OSNS
SV
IN_01
–
–
1µF
1µF
SW1
OUT1
+
IN_23
IN_23
V
100µF
×3
–
+
+
V
IN23
V
V
V
V
OSNS1
OSNS1
OSNS
OSNS
–
–
SV
IN_23
SW2
OUT2
V
100µF
×3
LTM4681
V
IN_VBIAS
+
470µF
×2
RUNP
+
+
RUN0
RUN1
RUN2
RUN3
V
V
V
V
OSNS2
OSNS2
OSNS
OSNS
–
–
SW3
OUT3
ON_OFF_CONFIG
V
100µF
×3
FAULT0
FAULT1
FAULT2
FAULT3
+
+
V
V
V
V
OSNS3
OSNS3
OSNS
OSNS
FAULT INTERRUPTS
PGOOD_0.9V
–
–
PGOOD0
PGOOD1
PGOOD2
PGOOD3
GND
SGND_23
SGND_01
4681 F50
COMPb
COMPa
18k
15.4k
14.3k
14.3k
14.3k
32.4k
14.3k
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢈꢁ ꢊꢆ ꢋꢌꢍ ꢎ0ꢏꢏꢐ
ꢇꢑꢉꢒꢆ ꢉꢓꢓRꢆꢇꢇꢔꢋ00ꢕꢋꢋꢋ0ꢕRꢖꢗ ꢃꢁR ꢘꢍꢙ ꢓꢆꢒꢄꢀꢆ
1.65k
1.65k
1.65k
ꢀꢁRꢂꢃꢄꢅꢁꢆꢇꢂꢈꢉꢉ ꢊꢋꢌꢍꢎꢏ ꢐꢑ
ꢒꢉꢈꢓꢔ ꢈꢕꢕRꢔꢒꢒꢖꢑ00ꢂꢑꢑ0ꢑꢂRꢗꢘ ꢁꢄR 0ꢙꢑ ꢕꢔꢓꢆꢃꢔ
Figure 50. Two Paralleled LTM4681 Producing 0.9VOUT at 250A. Integrated Power System Management Features Accessible
Over 2-Wire I2C/SMBus/PMBus Serial Interface
Rev. 0
81
For more information www.analog.com
LTM4681
TYPICAL APPLICATIONS
V
DD33_01
5V
5V
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
10k 4.99k
10k
10k
10k
10k
4.7µF
4.7µF
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
SW0
OUT0
5V
0.75V AT 60A
+
IN_01
V
+
100µF
×3
22µF
×6
150µF
×3
1mΩ
1mΩ
–
+
–
1Ω
IN_01
V
V
OSNS0
OSNS0
+
V
V
OSNS0
OSNS0
V
IN01
+
LOAD
470µF
×3
SV
IN_01
–
1µF
3.3V
SW1
OUT1
+
IN_23
IN_23
V
5V
22µF
×6
100µF
×3
–
+
+
V
V
V
V
1Ω
OSNS1
OSNS1
OSNS0
OSNS0
V
IN23
–
–
ENABLE
SV
IN_23
5V
1µF
SW2
OUT2
1V AT 60A
LTM4681
V
V
IN_VBIAS
RUNP
V
100µF
×3
DD33_01
+
–
V
V
OSNS2
OSNS2
RUN0
RUN1
RUN2
RUN3
+
10k
V
V
OSNS2
OSNS2
10k
10k
+
470µF
×3
LOAD
–
ENABLE
SW3
OUT3
FAULT0
FAULT1
FAULT2
FAULT3
V
10k
100µF
×3
+
+
OSNS2
–
V
V
V
OSNS3
OSNS3
FAULT INTERRUPTS
–
V
OSNS2
10k
PGOOD0
PGOOD1
PGOOD2
PGOOD3
GND
PGOOD_1V
10k
SGND_23
SGND_01
SGND
PGOOD_0.75V
4681 F51
32.4k
2200pF
2200pF
2200pF
2200pF
100pF
22.6k
14.3k
100pF
100pF
100pF
14.3k
14.3k
14.3k
32.4k
787Ω
12.7k
2.43k
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢈꢁ ꢊꢆ ꢋꢌꢍ ꢎ0ꢏꢏꢐ
ꢇꢑꢉꢒꢆ ꢉꢓꢓRꢆꢇꢇꢔꢋ00ꢕꢋꢋꢋ0ꢕRꢖꢗ ꢃꢁR ꢘꢍꢙ ꢓꢆꢒꢄꢀꢆ
ꢀꢁRꢂꢃꢄꢅꢁꢆꢇꢂꢈꢉꢉ ꢊꢋꢌꢍꢎꢏ ꢐꢑ
ꢒꢉꢈꢓꢔ ꢈꢕꢕRꢔꢒꢒꢖꢑ00ꢂꢑꢑꢑꢑꢂRꢗꢘ ꢁꢄR 0ꢙꢑ ꢕꢔꢓꢆꢃꢔ
Figure 51. 1V/60A and 0.75V/60A Outputs Generated from 3.3V and 5V Power Input and Providing I2C/SMBus/PMBus Serial Interface
Rev. 0
82
For more information www.analog.com
LTM4681
TYPICAL APPLICATIONS
V
ꢁ
DD33A_01
ꢀ
ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
4.7µF
22µF
4.99k
4.99k
SYNC
4.99k
SDA
4.99k
SCL
4.99k
ALERT
SHARE_CLK
4.7µF
V
IN
, 6V TO 16V
+
SW0
OUT0
IN_01
+
22µF
×6
V
150µF
×2
1mΩ
1mΩ
100µF
×3
–
1Ω
1Ω
IN_01
+
470µF
×2
V
IN01
+
+
–
V
V
V
V
OSNS0
OSNS0
OSNS
OSNS
SV
IN_01
–
1µF
SW1
OUT1
+
IN_23
IN_23
V
100µF
×3
–
+
+
V
IN23
V
V
V
V
OSNS1
OSNS1
OSNS
OSNS
–
–
SV
IN_23
1µF
SW2
OUT2
V
100µF
×3
LTM4681
V
IN_VBIAS
RUNP
V
+
470µF
×2
DD33A_01
+
+
RUN0
RUN1
RUN2
RUN3
V
V
V
V
OSNS2
OSNS2
OSNS
OSNS
–
–
4.99k
SW3
OUT3
ON_OFF_CONFIG
4.99k
V
100µF
×3
FAULT0
FAULT1
FAULT2
FAULT3
+
+
V
V
V
V
OSNS3
OSNS3
OSNS
OSNS
FAULT INTERRUPTS
4.99k
–
–
PGOOD0
PGOOD1
PGOOD2
PGOOD3
GND
SGND_23
SGND_01
SGND
PGOOD_0.9V
COMPb
COMPa
32.4k
22.6k
4700pF
100pF
14.3k
14.3k
14.3k
32.4k
14.3k
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢈꢁ ꢊꢆ ꢋꢌꢍ ꢎ0ꢏꢏꢐ
ꢇꢑꢉꢒꢆ ꢉꢓꢓRꢆꢇꢇꢔꢋ00ꢕꢋꢋꢋ0ꢕRꢖꢗ ꢃꢁR ꢘꢍꢙ ꢓꢆꢒꢄꢀꢆ
1.65k
1.65k
1.65k
ꢀꢁRꢂꢃꢄꢅꢁꢆꢇꢂꢈꢉꢉ ꢊꢋꢌꢍꢎꢏ ꢐꢑ
ꢒꢉꢈꢓꢔ ꢈꢕꢕRꢔꢒꢒꢖꢑ00ꢂꢑꢑꢑꢑꢂRꢗꢘ ꢁꢄR 0ꢙꢑ ꢕꢔꢓꢆꢃꢔ
ꢁ
ꢀ
ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
+
V
OSNS
ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
4.7µF
22µF
0.9V AT 187A
LOAD
ALERT SHARE_CLK SYNC
SDA
SCL
4.7µF
–
V
IN
, 6V TO 16V
V
OSNS
+
SW0
OUT0
IN_01
+
22µF
×6
V
150µF
×2
1mΩ
1mΩ
100µF
×3
–
1Ω
1Ω
IN_01
+
470µF
×2
V
IN01
+
+
V
V
V
V
OSNS0
OSNS0
OSNS
OSNS
SV
IN_01
–
–
1µF
1µF
SW1
OUT1
+
IN_23
IN_23
V
100µF
×3
–
+
+
V
IN23
V
V
V
V
OSNS1
OSNS1
OSNS
OSNS
–
–
SV
IN_23
SW2
V
LTM4681
1V AT 30A
IN_VBIAS
RUNP
V
OUT2
+
+
+
V
V
OSNS1V
100µF
×4
470µF
×2
V
V
OSNS2
OSNS2
RUN0
RUN1
RUN2
RUN3
–
OSNS1V
–
ON_OFF_CONFIG
SW3
1.2V AT 30A
V
FAULT0
FAULT1
FAULT2
FAULT3
OUT3
+
+
+
V
OSNS1V2
100µF
×4
470µF
×2
V
OSNS3
–
V
OSNS1V2
–
V
OSNS3
FAULT INTERRUPTS
V
DD33B_01
10k
PGOOD0
PGOOD1
PGOOD2
PGOOD3
GND
PGOOD_0.9V
PGOOD_1V
SGND_23
SGND_01
10k
SGND
PGOOD_1.2V
4681 F52
100pF
100pF
COMPb
COMPa
18k
15.4k
2200pF
2200pF
14.3k
14.3k
14.3k 14.3k
14.3k
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢈꢁ ꢊꢆ ꢋꢌꢍ ꢎ0ꢏꢏꢐ
ꢇꢑꢉꢒꢆ ꢉꢓꢓRꢆꢇꢇꢔꢋ00ꢕꢋꢋ00ꢕRꢖꢗ ꢃꢁR ꢘꢍꢙ ꢓꢆꢒꢄꢀꢆ
1.65k
2.43k
1.65k
32.4k
32.4k
ꢀꢁRꢂꢃꢄꢅꢁꢆꢇꢂꢈꢉꢉ ꢊꢋꢌꢍꢎꢏ ꢐꢑ
ꢒꢉꢈꢓꢔ ꢈꢕꢕRꢔꢒꢒꢖꢑ00ꢂꢑꢑ0ꢑꢂRꢗꢘ ꢁꢄR 0ꢙꢑ ꢕꢔꢓꢆꢃꢔ
Figure 52. 6-Phase Operation Producing 0.9V at 187A, 2 Phase for 1V at 30A, and 1.2V at 30A. Power System Management
Features Accessible Through LTM4681 Over 2-Wire I2C/SMBus/PMBus Serial Interface
Rev. 0
83
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
ADDRESSING AND WRITE PROTECT
CMD
DATA
DEFAULT
COMMAND NAME
PAGE
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
0x00 Provides integration with multi-page PMBus devices.
R/W Byte
N
N
N
Reg
Reg
0x00
PAGE_PLUS_WRITE
PAGE_PLUS_READ
0x05 Write a supported command directly to a PWM channel. W Block
0x06 Read a supported command directly from a PWM
channel.
Block
R/W
WRITE_PROTECT
0x10 Level of protection provided by the device against
accidental changes.
R/W Byte
N
Y
0x00
2
MFR_ADDRESS
0xE6 Sets the 7-bit I C address byte.
R/W Byte
R/W Byte
N
Y
Reg
Reg
Y
Y
0x4F
0x80
MFR_RAIL_ADDRESS
0xFA Common address for PolyPhase outputs to adjust
common parameters.
PAGE
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physi-
cal address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for
one PWM channel.
Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.
ASEL_01 sets the address for Channel 0 and 1, ASEL_23 sets the address for Channel 2 and 3. Each of the ASEL pins
will have a different programmed address.
Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTM4681
will respond to read commands as if PAGE were set to 0x00 (Channel 0 results).
This command has one data byte.
PAGE_PLUS_WRITE
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send
the data for the command, all in one communication packet. Commands allowed by the present write protection level
may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send
a non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a com-
mand that has two data bytes is shown in Figure 53.
ꢘ
ꢖ
ꢘ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢆꢂꢇꢄꢈꢆꢁꢉꢀ
ꢊꢋꢌꢌꢂꢍꢅ ꢊꢋꢅꢄ
ꢎꢁꢋꢊꢏ ꢊꢋꢉꢍꢐ
ꢑꢒ ꢓꢔ
ꢆꢂꢇꢄ
ꢍꢉꢌꢎꢄR
ꢊꢋꢌꢌꢂꢍꢅ
ꢊꢋꢅꢄ
ꢀ
ꢕ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢙ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢘ
ꢁꢋꢕꢄR ꢅꢂꢐꢂ
ꢎꢚꢐꢄ
ꢉꢆꢆꢄR ꢅꢂꢐꢂ
ꢎꢚꢐꢄ
ꢂ
ꢂ
ꢆꢄꢊ ꢎꢚꢐꢄ
ꢂ
ꢆ
ꢓꢛꢗꢘ ꢜꢝꢞ
Figure 53. Example of PAGE_PLUS_WRITE
PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read
the data returned by the command, all in one communication packet .
Rev. 0
84
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access
data from a non-paged command, the Page Number byte is ignored.
This command uses the Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown
in Figure 54.
ꢁ
ꢗ
ꢁ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢀꢄꢈꢆꢉꢀꢃꢊꢂ
ꢋꢌꢍꢍꢄꢎꢇ ꢋꢌꢇꢆ
ꢏꢃꢌꢋꢐ ꢋꢌꢊꢎꢑ
ꢒꢓ ꢔꢕ
ꢀꢄꢈꢆ
ꢎꢊꢍꢏꢆR
ꢋꢌꢍꢍꢄꢎꢇ
ꢋꢌꢇꢆ
ꢂ
ꢖ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢙ
ꢁ
ꢗ
ꢁ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢏꢃꢌꢋꢐ ꢋꢌꢊꢎꢑ
ꢃꢌꢖꢆR ꢇꢄꢑꢄ
ꢏꢚꢑꢆ
ꢊꢀꢀꢆR ꢇꢄꢑꢄ
ꢏꢚꢑꢆ
ꢂꢛ
R
ꢄ
ꢄ
ꢄ
ꢄ
ꢀꢆꢋ ꢏꢚꢑꢆ
ꢎꢄ
ꢀ
ꢒꢓ ꢔꢕ
ꢜꢝꢘꢁ ꢞꢟꢜ
Figure 54. Example of PAGE_PLUS_READ
Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another
PAGE_PLUS command. If this is attempted, the LTM4681 will NACK the entire PAGE_PLUS packet and issue a CML
fault for Invalid/Unsupported Data.
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTM4681 device. This command does not indicate
the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the
value of this command.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_
EE_UNLOCK, and STORE_USER_ALL commands.
0x40 Disable all writes except to the WRITE_PROTECT, PAGE,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,
OPERATION and CLEAR_FAULTS command. Individual fault
bits can be cleared by writing a 1 to the respective bits in the
STATUS commands.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,
PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_
ALL. Individual fault bits can be cleared by writing a 1 to the
respective bits in the STATUS commands.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
Enable writes to all commands when WRITE_PROTECT is set to 0x00.
If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT and CLEAR_
FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the
STATUS commands.
Rev. 0
85
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore, the ASEL_nn pins are still used to determine the LSB of the chan-
nel address. If the ASEL_01 and ASEL_23 pins are both open, the LTM4681 will use the address value stored in NVM.
If the ASEL_nn pins are open, the LTM4681 will use the lower 4 bits of the MFR_ADDRESS value stored in NVM to
construct the effective address of the part.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTM4681 will detect bus contention and may set a CML
communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
GENERAL CONFIGURATION COMMANDS
DATA
DEFAULT
VALUE
COMMAND NAME
MFR_CHAN_CONFIG
MFR_CONFIG_ALL
CMD CODE DESCRIPTION
TYPE
Configuration bits that are channel specific. R/W Byte
General configuration bits. R/W Byte
PAGED FORMAT UNITS NVM
0xD0
0xD1
Y
N
Reg
Reg
Y
Y
0x1D
0x21
MFR_CHAN_CONFIG
General purpose configuration command common to multiple ADI products.
BIT MEANING
7
6
5
4
3
2
1
Reserved
Reserved
Reserved
Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF.
Enable Short Cycle recognition if this bit is set to a 1.
SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled.
No FAULT ALERT, ALERT is not pulled low if FAULT is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are
propagated on FAULT.
0
Disables the V
decay value requirement for MFR_RETRY_TIME and t
processing. When this bit is set to a 0, the output must decay to
OUT
OFF(MIN)
less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from
high to low to high.
This command has one data byte.
Rev. 0
86
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
A ShortCycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been
commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned
ON and OFF through either the RUN pin and or the PMBus OPERATION command.
If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following:
1. Immediately tri-state the PWM channel output;
2. Start the retry delay timer as specified by the t
.
OFF(MIN)
3. After the t
value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_
OFF(MIN)
MFR_SPECIFIC bit #1 will assert.
If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following:
1. Stop ramping down the PWM channel output;
2. Immediately tri-state the PWM channel output;
3. Start the retry delay timer as specified by the t
.
OFF(MIN)
4. After the t
value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_
OFF(MIN)
MFR_SPEFIFIC bit #1 will assert.
If the ShortCycle event occurs and the ShortCycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine
will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user.
MFR_CONFIG_ALL
General purpose configuration command common to multiple ADI products.
BIT MEANING
7
6
5
4
3
2
Enable Fault Logging
Ignore Resistor Configuration Pins
Mask PMBus, Part II, Section 10.9.1 Violations
Disable SYNC output
Enable 255ms PMBus timeout
A valid PEC required for PMBus writes to be accepted. If this bit is not
set, the part will accept commands with invalid PEC.
1
0
Enable the use of PMBus clock stretching
Execute CLEAR_FAULTS on rising edge of either RUN pin.
This command has one data byte.
ON/OFF/MARGIN
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
ON_OFF_CONFIG
OPERATION
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte
Y
Y
Reg
Reg
Y
Y
0x1E
0x80
0x01 Operating mode control. On/off, margin high and margin R/W Byte
low.
MFR_RESET
0xFD Commanded reset without requiring a power-down.
Send Byte
N
NA
Rev. 0
87
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
ON_OFF_CONFIG
The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to
turn the PWM channel on and off.
Supported Values:
VALUE
MEANING
0x1F
OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.
OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off.
RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.
RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.
0x1E
0x17
0x16
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It
is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in
the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin
instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET
or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed
to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation
command is sequence off. If V is applied to a part with factory default programming and the VOUT_CONFIG resistor
IN
configuration pins are not installed, the outputs will be commanded off.
The part defaults to the Sequence Off state.
This command has one data byte.
Supported Values:
VALUE
MEANING
0xA8
Margin high.
Margin low.
0x98
0x80
On (V
back to nominal even if bit 3 of ON_OFF_CONFIG is not set).
OUT
0x40*
0x00*
Soft off (with sequencing).
Immediate off (no sequencing).
*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.
Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored.
This command has one data byte.
MFR_RESET
This command provides a means to reset the LTM4681 from the serial bus. This forces the LTM4681 to turn off both
PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of
both PWM channels, if enabled.
This write-only command has no data bytes.
Rev. 0
88
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
PWM CONFIGURATION
DATA
DEFAULT
COMMAND NAME
MFR_PWM_COMP
MFR_PWM_MODE
MFR_PWM_CONFIG
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
0xD3
0xD4
0xF5
PWM loop compensation configuration
R/W Byte
R/W Byte
R/W Byte
Y
Y
N
Reg
Reg
Reg
Y
Y
Y
0x28
0xC3
0x10
Configuration for the PWM engine.
Set numerous parameters for the DC/DC controller
including phasing.
FREQUENCY_SWITCH
0x33
Switching frequency of the controller.
R/W
Word
N
L11
kHz
Y
250
0xF3E8
MFR_PWM_MODE
The MFR_PWM_MODE command sets important PWM controls for each channel.
The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping
mode), or forced continuous conduction mode.
BIT
7
0b
1b
6
MEANING
Use High Range of I
Low Current Range
High Current Range
Enable Servo Mode
LIMIT
5
External temperature sense:
0: ∆V measurement.
BE
Now reserved, ∆V only supported.
BE
4
Page 0 Only: Use of TSNS -Sensed Temperature Telemetry
1a
0 - Temperature sensed via TSNS is used to temperature-correct the current-sense information digitized by Channel 1’s current sense input,
1a
ISNS +/ISNS –.
1a
1a
1 - Temperature sensed via TSNS is used to temperature-correct the current-sense information digitized by Channel 1’s current sense input,
0a
ISNS +/ISNS –. Telemetry obtained from the thermal sensor connected to TSNS can be external to the module, if desired.
1a
1a
1a
3
Reserved
2
1
Reserved
V
OUT
Range
1b
0b
The maximum output voltage is 2.75V
The maximum output voltage is 3.6V
Bit[0] Mode
0b
1b
Discontinuous
Forced Continuous
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.
Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the
channel output is active. Writing this bit when the channel is active will generate a CML fault.
Bit [6] The LTM4681 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo
is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC
and the VOUT_COMMAND (or the appropriate margined value).
The LTM4681 computes temperature in °C from ∆V measured by the ADC at the TSNSn pin as
BE
T = (G • ∆V • q/(K • ln(16))) – 273.15 + O
BE
Rev. 0
89
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
For both equations,
–14
G = MFR_TEMP_1_GAIN • 2 , and
O = MFR_TEMP_1_OFFSET
Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes
the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing
this bit when the channel is active will generate a CML fault.
B
it[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous con-
duction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of
this bit. This command has one data byte.
MFR_PWM_COMP
The MFR_PWM_COMP command sets the g of the PWM channel error amplifiers and the value of the internal R
m
ITHn
compensation resistors. This command affects the loop gain of the PWM output which may require modifications to
the external compensation network.
BIT
MEANING
BIT [7:5]
000b
Error Amplifier GM Adjust (mS)
1.00
1.68
2.35
3.02
3.69
4.36
5.04
5.76
001b
010b
011b
100b
101b
110b
111b
BIT [4:0]
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
R
ITH
(kΩ)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.5
3
3.5
4
4.5
5
5.5
Rev. 0
90
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
10000b
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
6
7
8
9
11
13
15
17
20
24
28
32
38
46
54
62
This command has one data byte.
MFR_PWM_CONFIG
The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the
SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the
channels must be commanded off. If either channel is in the RUN state and this command is written, the command
will be NACK’d and a BUSY fault will be asserted.
BIT
MEANING
7
Reserved
[6:5]
00b
01b
10b
11b
Input current sense gain.
2x gain. 0mV to 50mV range.
4x gain. 0mV to 25mV range.
8x gain. 0mV to 12.5mV range.
Reserved
4
Share Clock Enable : If this bit is 1, the
SHARE_CLK pin will not be released until
IN
V
> VIN_ON. The SHARE_CLK pin will be
pulled low when V < VIN_OFF. If this bit is 0, the SHARE_
IN
CLK pin will not be pulled low when VIN < VIN_OFF except
for the initial application of VIN.
3
BIT [2:0]
000b
001b
010b
011b
100b
101b
110b
Reserved
CHANNEL 0 (DEGREES)
CHANNEL 1 (DEGREES)
0
90
0
180
270
240
120
240
240
300
0
120
60
120
Rev. 0
91
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTM4681.
Supported Frequencies:
VALUE [15:0]
0x0000
0xF3E8
RESULTING FREQUENCY (TYP)
External Oscillator
250kHz
0xFABC
0xFB52
0xFBE8
0x023F
350kHz
425kHz
500kHz
575kHz
0x028A
0x02EE
0x03E8
650kHz
750kHz
1000kHz
The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be
commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY
fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be
detected as the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOLTAGE
Input Voltage and Limits
DATA
PAGED FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
UNITS
NVM
VIN_OV_FAULT_LIMIT
0x55
0x58
0x35
0x36
0xF7
Input supply overvoltage fault limit.
R/W
N
N
N
N
N
L11
L11
L11
L11
L11
V
Y
15.5
Word
0xD3E0
VIN_UV_WARN_LIMIT
VIN_ON
Input supply undervoltage warning limit.
R/W
Word
V
V
Y
Y
Y
Y
4.65
0xD12A
Input voltage at which the unit should start
power conversion.
R/W
Word
4.75
0xD130
VIN_OFF
Input voltage at which the unit should stop
power conversion.
R/W
Word
V
4.5
0xD120
MFR_ICHIP_CAL_GAIN
The resistance value of the V pin filter
R/W
Word
mΩ
1000
0x03E8
IN
element in milliohms
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes
an input overvoltage fault.
This command has two data bytes in Linear_5s_11s format.
Rev. 0
92
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under
voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON
command and the unit has been enabled. If the V Voltage drops below the VIN_OV_WARN_LIMIT the device:
-
IN
•
•
•
Sets the INPUT Bit Is the STATUS_WORD
Sets the V Undervoltage Warning Bit in the STATUS_INPUT Command
IN
Notifies the Host by Asserting ALERT, unless Masked
VIN_ON
The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_OFF
The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_ICHIP_CAL_GAIN
The MFR_ICHIP_CAL_GAIN command is used to set the resistance value of the V pin filter element in milliohms.
IN
(See also READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used.
This command has two data bytes and is formatted in Linear_5s_11s format.
Output Voltage and Limits
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT
UNITS
NVM
–12
VOUT_MODE
0x20
Output voltage format and exponent
R Byte
Y
Reg
L16
2
0x14
–12
(2 ).
VOUT_MAX
0x24
Upper limit on the output voltage
the unit can command regardless of
any other commands.
R/W
Word
Y
V
Y
3.6
0xC399
VOUT_OV_FAULT_ LIMIT
VOUT_OV_WARN_ LIMIT
VOUT_MARGIN_HIGH
0x40
0x42
0x25
Output overvoltage fault limit.
R/W
Y
Y
Y
L16
L16
L16
V
V
V
Y
Y
Y
1.1
Word
0x119A
Output overvoltage warning limit.
R/W
Word
1.075
0x1133
Margin high output voltage set
point. Must be greater than
VOUT_COMMAND.
R/W
Word
1.05
0x10CD
VOUT_COMMAND
0x21
0x26
Nominal output voltage set point.
R/W
Y
Y
L16
L16
V
V
Y
Y
1.0
Word
0x1000
VOUT_MARGIN_LOW
Margin low output voltage
set point. Must be less than
VOUT_COMMAND.
R/W
Word
0.95
0x0F33
VOUT_UV_WARN_ LIMIT
VOUT_UV_FAULT_ LIMIT
MFR_VOUT_MAX
0x43
0x44
0xA5
Output undervoltage warning limit.
Output undervoltage fault limit.
Maximum allowed output voltage.
R/W
Y
Y
Y
L16
L16
L16
V
V
V
Y
Y
0.925
Word
0x0ECD
R/W
Word
0.9
0x0E66
R Word
3.6
0xC399
Rev. 0
93
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
VOUT_MODE
The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode
(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write
commands.
This read-only command has one data byte.
VOUT_MAX
The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com-
mand regardless of any other commands or combinations. The maximum allowed value of this command is 3.6V.
The maximum output voltage the LTM4681 can produce is 3.3V including VOUT_MARGIN_HIGH. However, the
VOUT_OV_FAULT_LIMIT can be commanded as high as 3.6V.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor compara-
tor at the sense pins, in volts, which causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modi-
fied to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and
6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND
is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable
behavior and possible damage to the switcher.
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if VOUT_OV_FAULT is
propagated. The LTM4681 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins,
in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this
limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC so the response time may be up to t
This command has two data bytes and is formatted in Linear_16u format.
.
CONVERT
Rev. 0
94
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts,
when the OPERATION command is set to “Margin High”. The value should be greater than VOUT_COMMAND. The
maximum guaranteed value on VOUT_MARGIN_HIGH is 3.6V.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_
RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_COMMAND
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed
value on VOUT is 3.6V.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_
RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_
RATE will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_WARN_LIMIT
The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins,
in volts, which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor com-
parator at the sense pins, in volts, which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
Rev. 0
95
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
MFR_VOUT_MAX
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_
LIMIT. If the output voltages are set to high range (Bit 6 of MFR_PWM_CONFIG set to a 0) MFR_VOUT_MAX is 3.6V. If
the output voltage is set to low range (Bit 6 of MFR_PWM_CONFIG set to a 1) the MFR_VOUT_MAX is 2.75V. Entering
a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped
to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set.
This read only command has 2 data bytes and is formatted in Linear_16u format.
OUTPUT CURRENT AND LIMITS
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
MFR_IOUT_CAL_GAIN
0xDA
The ratio of the voltage at the current
R Word
Y
L11
mΩ
Factory
Only
NVM
0.4
0xD01A
sense pins to the sensed current. For
devices using a fixed current sense
resistor, it is the resistance value in
mΩ.
MFR_IOUT_CAL_GAIN_TC
IOUT_OC_FAULT_LIMIT
IOUT_OC_WARN_LIMIT
0xF6
0x46
0x4A
Temperature coefficient of the current R/W Word
sensing element.
Y
Y
Y
CF
Y
Y
Y
3900
0x0F3C
Output overcurrent fault limit.
R/W Word
L11
L11
A
A
40.0
0xE940
Output overcurrent warning limit.
R/W Word
35.0
0xE231
MFR_IOUT_CAL_GAIN
The MFR_IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms.
(see also MFR_IOUT_CAL_GAIN_TC).
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_
GAIN sense resistor or inductor DCR in ppm/°C.
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •
–6
10 . Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)].
DCR sensing will have a typical value of 3900.
The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT,
MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.
Rev. 0
96
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the control-
ler is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the
+
–
progammable peak output current limit value in mV between I
and I
. The actual value of current limit is
SENSE
SENSE
+
–
(I
– I
)/IOUT_CAL_GAIN in Amperes.
SENSE
SENSE
BASED ON PEAK-TO-PEAK INDUCTOR CURRENT = 50% OF 30A FOR WORSE CASE, THESE ARE APPROXIMATES, SO USE GUARDBAND AND CHECK
MFR_PWM_MODE[7] = 1
High Current Range (mV)
MFR_PWM_MODE[7] = 0
Low Current Range (mV)
~ILPeak (A)
44.33
~IOUT (A)
36.83
39.65
43.55
45.35
48.18
51.03
53.88
~ ILPeak (A)
24.63
~ IOUT (A)
17.13
17.73
18.86
20.42
21.14
22.27
23.41
24.55
9.85
47.15
10.48
11.34
11.74
12.37
13.01
13.64
26.20
18.70
51.05
28.35
20.85
52.85
29.35
21.85
55.68
30.93
23.43
58.53
32.53
25.03
61.38
34.10
26.60
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output
current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
Peak Current Limit = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
The LTM4681 automatically convert currents to the appropriate internal bit value.
The I
range is set with bit 7 of the MFR_PWM_MODE command.
OUT
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
If the IOUT_OC_FAULT_LIMIT is exceeded, the device:
• Sets the IOUT bit in the STATUS word
• Sets the IOUT Overcurrent fault bit in the STATUS_IOUT
• Notifies the host by asserting ALERT, unless masked
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
97
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
IOUT_OC_WARN_LIMIT
This command sets the value of the output current measured by the ADC that causes an output overcurrent warning
in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format
Input Current and Limits
CMD
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
UNITS
NVM
MFR_IIN_CAL_GAIN
0xE8 The resistance value of the input current sense
element in mΩ.
R/W Word
L11
mΩ
Y
1.000
0xE010
MFR_IIN_CAL_GAIN
The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms.
(see also READ_IIN).
This command has two data bytes and is formatted in Linear_5s_11s format.
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0x5D Input overcurrent warning
limit.
TYPE
PAGED
FORMAT
UNITS
NVM
IIN_OC_WARN_LIMIT
R/W Word
N
L11
A
Y
10.0
0xD280
IIN_OC_WARN_LIMIT
The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes
a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been
exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
• Sets the OTHER bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
• Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
98
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
TEMPERATURE
Power Stage DCR Temperature Calibration
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
MFR_TEMP_1_GAIN
0xF8
Sets the slope of the external temperature
sensor.
R/W Word
Y
CF
Y
0.995
0x3FAE
MFR_TEMP_1_OFFSET
0xF9
Sets the offset of the external temperature R/W Word
sensor.
Y
L11
C
Y
0.0
0x8000
MFR_TEMP_1_GAIN
The MFR_TEMP_1_GAIN command will modify the slope of the power stage sensor to account for non-idealities in
the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. The effective gain adjustment is
–14
N • 2 . The nominal value is 1. N = 8192 to 32767
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command will modify the offset of the power stage temperature sensor to account for
non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calibration with a
–273.15 so the default adjustment is zero.
Power Stage Temperature Limits
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
UNITS
NVM
OT_FAULT_LIMIT
0x4F
0x51
0x53
Power stage overtemperature fault
R/W Word
Y
L11
L11
L11
C
Y
128.0
limit.
0xF200
OT_WARN_LIMIT
UT_FAULT_LIMIT
Power stage overtemperature
warning limit.
R/W Word
R/W Word
Y
Y
C
C
Y
Y
125.0
0xEBE8
Power stage undertemperature fault
limit.
–45.0
0xE530
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees
Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this
limit has been exceeded.
This command has two data bytes and is formatted in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees
Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if
this limit has been exceeded.
Rev. 0
99
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
In response to the OT_WARN_LIMIT being exceeded, the device:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_5s_11s format.
UT_FAULT_LIMIT
The UT_FAULT_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees Celsius,
which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been
exceeded.
Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response
set to ignore to avoid ALERT being asserted.
This command has two data bytes and is formatted in Linear_5s_11s format.
TIMING
Timing—On Sequence/Ramp
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
TON_DELAY
0x60
Time from RUN and/or Operation on to
R/W Word
Y
L11
L11
ms
Y
0.0
output rail turn-on.
0x8000
TON_RISE
0x61
Time from when the output starts to
rise until the output voltage reaches the
VOUT commanded value.
Maximum time from the start of
TON_RISE for VOUT to cross the
VOUT_UV_FAULT_LIMIT.
R/W Word
R/W Word
R/W Word
Y
ms
Y
Y
Y
3.0
0xC300
TON_MAX_FAULT_LIMIT
VOUT_TRANSITION_RATE
0x62
0x27
Y
Y
L11
L11
ms
5.0
0xCA80
Rate the output changes when VOUT
commanded to a new value.
V/ms
0.001
0x8042
TON_DELAY
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output
voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of
270µs for TON_DELAY = 0 and an uncertainty of 50µs for all values of TON_DELAY.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_RISE
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output
enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during
TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4681 digital slope will be bypassed and the output voltage
transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE
is equal to TON_RISE (in ms)/0.1ms with an uncertainty of 0.1ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
100
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power
up the output without reaching the output undervoltage fault limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.
The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOUT_TRANSITION_RATE
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the
output voltage to change this command set the rate in V/ms at which the output voltage changes. The commanded
rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Timing—Off Sequence/Ramp
CMD
DATA
FORMAT UNITS
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED
NVM
TOFF_DELAY
0x64 Time from RUN and/or Operation off to the
start of TOFF_FALL ramp.
0x65 Time from when the output starts to fall until
the output reaches zero volts.
0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below 12.5%.
R/W Word
Y
L11
L11
L11
ms
ms
ms
Y
0.0
0x8000
TOFF_FALL
R/W Word
R/W Word
Y
Y
Y
Y
3.0
0xC300
TOFF_MAX_WARN_LIMIT
0
0x8000
TOFF_DELAY
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output
voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of
270µs for TOFF_DELAY = 0 and an uncertainty of 50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied
when a fault event occurs
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt-
age is commanded to zero. It is the ramp time of the V
set to high impedance state.
DAC. When the V
DAC is zero, the PWM output will be
OUT
OUT
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part
to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.
The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum
fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty
of 0.1ms.
In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by
the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
101
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds
12.5% of the programmed voltage before a warning is asserted. The output is considered off when the V
voltage
OUT
is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete.
A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage
indefinitely. Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
Precondition for Restart
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xDC Minimum time the RUN pin is held
low by the LTM4681.
TYPE
PAGED
FORMAT
UNITS
NVM
MFR_RESTART_ DELAY
R/W Word
Y
L11
ms
Y
150
0xF258
MFR_RESTART_DELAY
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length
of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after
which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_
FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time,
set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_
RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the
output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
FAULT RESPONSE
Fault Responses All Faults
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
UNITS
NVM
MFR_RETRY_ DELAY
0xDB
Retry interval during FAULT retry R/W Word
mode.
Y
L11
ms
Y
250
0xF3E8
MFR_RETRY_DELAY
This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified
intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has
been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required
for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is
too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
102
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
Fault Responses Input Voltage
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
VIN_OV_FAULT_RESPONSE
0x56
Action to be taken by the device when an R/W Byte
input supply overvoltage fault is detected.
Y
Reg
Y
0x80
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over-
voltage fault. The data byte is in the format given in Table 18.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Fault Responses Output Voltage
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
VOUT_OV_FAULT_RESPONSE
0x41 Action to be taken by the device when an
output overvoltage fault is detected.
R/W Byte
Y
Y
Y
Reg
Reg
Reg
Y
0xB8
0xB8
0xB8
VOUT_UV_FAULT_RESPONSE
TON_MAX_FAULT_ RESPONSE
0x45 Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte
R/W Byte
Y
Y
0x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overvoltage fault. The data byte is in the format given in Table 17.
The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
The only values recognized for this command are:
0x00
0x80
Part performs OV pull down only, or OV_PULLDOWN.
The device shuts down (disables the output) and the unit does not attempt to retry.
(PMBus, Part II, Section 10.7).
Rev. 0
103
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
0xB8
The device shuts down (disables the output) and device attempts to retry continuously, without limitation,
until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down.
0x4n
The device shuts down and the unit does not attempt to retry. The output remains disabled until the part
is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or
removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
0x78n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or
the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command
or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.
Table 17. VOUT_OV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
Part performs OV pull down only or OV_PULLDOWN
(i.e., turns off the top MOSFET and turns on lower MOSFET
while V is > VOUT_OV_FAULT).
For all values of bits [7:6], the LTM4681:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
OUT
01
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for that
particular fault. If the fault condition is still present at the end of
the delay time, the unit responds as programmed in the Retry
Setting (bits [5:3]).
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
10
11
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
Not supported. Writing this value will generate a CML fault.
• Bias power is removed and reapplied to the LTM4681.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or another
fault condition causes the unit to shut down without retry. Note: The
retry interval is set by the MFR_RETRY_DELAY command.
Delay Time
000-111 The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The data byte is in the format given in Table 8.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
Rev. 0
104
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
The UV fault and warn are masked until the following criteria are achieved:
1) The TON_MAX_FAULT_LIMIT has been reached
2) The TON_DELAY sequence has completed
3) The TON_RISE sequence has completed
4) The VOUT_UV_FAULT_LIMIT threshold has been reached
5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
Table 18. VOUT_UV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The PMBus device continues operation without interruption.
(Ignores the fault functionally)
For all values of bits [7:6], the LTM4681:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
01
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for
that particular fault. If the fault condition is still present at the
end of the delay time, the unit responds as programmed in the
Retry Setting (bits [5:3]).
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
10
11
The device shuts down (disables the output) and responds
according to the retry setting in bits [5:3].
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
Not supported. Writing this value will generate a CML fault.
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
000-111 The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
Rev. 0
105
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The data byte is in the format given in Table 15.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded.
This command has one data byte.
Fault Responses Output Current
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
IOUT_OC_FAULT_RESPONSE
0x47
Action to be taken by the device when an R/W Byte
output overcurrent fault is detected.
Y
Reg
Y
0x00
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The data byte is in the format given in Table 9.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Rev. 0
106
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
Table 19. IOUT_OC_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The LTM4681 continues to operate indefinitely while
maintaining the output current at the value set by
For all values of bits [7:6], the LTM4681:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
IOUT_OC_FAULT_LIMIT without regard to the output
voltage (known as constant-current or brick-wall limiting).
01
10
Not supported.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
The LTM4681 continues to operate, maintaining the output
current at the value set by IOUT_OC_FAULT_LIMIT without
regard to the output voltage, for the delay time set by bits [2:0].
If the device is still operating in current limit at the end of the
delay time, the device responds as programmed by the Retry
Setting in bits [5:3].
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
11
The LTM4681 shuts down immediately and responds as
programmed by the Retry Setting in bits [5:3].
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared by cycling the RUN pin or
removing bias power.
The device attempts to restart continuously, without limitation,
until it is commanded OFF (by the RUN pin or OPERATION
command or both), bias power is removed, or another fault
condition causes the unit to shut down. Note: The retry interval
is set by the MFR_RETRY_DELAY command.
Delay Time
000-111 The number of delay time units in 16ms increments. This
delay time is used to determine the amount of time a unit is
to continue operating after a fault is detected before shutting
down. Only valid for deglitched off response.
Fault Responses IC Temperature
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
MFR_OT_FAULT_RESPONSE
0xD6
Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte
N
Reg
0xC0
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal
overtemperature fault. The data byte is in the format given in Table 13.
The LTM4681 also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Rev. 0
107
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
Table 20. Data Byte Contents MFR_OT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
Not supported. Writing this value will generate a CML fault.
For all values of bits [7:6], the LTM4681:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
Not supported. Writing this value will generate a CML fault
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
The device’s output is disabled while the fault is present.
Operation resumes and the output is enabled when the fault
condition no longer exists.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4681.
Retry Setting
5:3
2:0
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001-111 Not supported. Writing this value will generate CML fault.
Delay Time
XXX
Not supported. Value ignored
Fault Responses External Temperature
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
OT_FAULT_ RESPONSE
0x50
Action to be taken by the device when an
external overtemperature fault is detected,
R/W Byte
Y
Reg
Reg
Y
0xB8
UT_FAULT_ RESPONSE
0x54
Action to be taken by the device when an
external undertemperature fault is detected.
R/W Byte
Y
Y
0xB8
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtem-
perature fault on the external temp sensors. The data byte is in the format given in Table 15.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
UT_FAULT_RESPONSE
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under-
temperature fault on the external temp sensors. The data byte is in the format given in Table 15.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
Rev. 0
108
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
This condition is detected by the ADC so the response time may be up to t
.
CONVERT
This command has one data byte.
Table 21. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
The PMBus device continues operation without interruption.
Not supported. Writing this value will generate a CML fault.
For all values of bits [7:6], the LTM4681:
• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin, unless masked.
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
Not supported. Writing this value will generate a CML fault.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
XXX
Not supported. Values ignored
FAULT SHARING
Fault Sharing Propagation
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xD2 Configuration that determines which faults
are propagated to the FAULT pins.
TYPE
PAGED FORMAT UNITS
NVM
MFR_FAULT_
PROPAGATE
R/W Word
Y
Reg
Y
0x6993
MFR_FAULT_PROPAGATE
The MFR_FAULT_PROPAGATE command enables the faults that can cause the FAULTn pin to assert low. The com-
mand is formatted as shown in Table 22. Faults can only be propagated to the FAULTn pin if they are programmed to
respond to faults.
This command has two data bytes.
Rev. 0
109
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
Table 22. FAULTn Propagate Fault Configuration
The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output
channels. Others are specific to an output channel. They can also be used to share faults between channels.
BIT(S)
SYMBOL
OPERATION
B[15]
VOUT disabled while not decayed.
This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTM4681 is a
zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then
the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT
will not restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition
if bit 15 is asserted.
B[14]
b[13]
Mfr_fault_propagate_short_CMD_cycle 0: No action
1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high
after sequence off.
t
OFF(MIN)
Mfr_fault_propagate_ton_max_fault
0: No action if a TON_MAX_FAULT fault is asserted
1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted
FAULT0 is associated with page 0 TON_MAX_FAULT faults
FAULT1 is associated with page 1 TON_MAX_FAULT faults
b[12]
b[11]
Reserved
Mfr_fault0_propagate_int_ot,
Mfr_fault1_propagate_int_ot
Reserved
0: No action if the MFR_OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted
b[10]
b[9]
Reserved
b[8]
Mfr_fault0_propagate_ut,
Mfr_fault1_propagate_ut
0: No action if the UT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 UT faults
FAULT1 is associated with page 1 UT faults
b[7]
Mfr_fault0_propagate_ot,
Mfr_fault1_propagate_ot
0: No action if the OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OT faults
FAULT1 is associated with page 1 OT faults
b[6]
b[5]
b[4]
Reserved
Reserved
Mfr_fault0_propagate_input_ov,
Mfr_fault1_propagate_input_ov
Reserved
0: No action if the VIN_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted
b[3]
b[2]
Mfr_fault0_propagate_iout_oc,
Mfr_fault1_propagate_iout_oc
0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OC faults
FAULT1 is associated with page 1 OC faults
b[1]
b[0]
Mfr_fault0_propagate_vout_uv,
Mfr_fault1_propagate_vout_uv
0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 UV faults
FAULT1 is associated with page 1 UV faults
Mfr_fault0_propagate_vout_ov,
Mfr_fault1_propagate_vout_ov
0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OV faults
FAULT1 is associated with page 1 OV faults
Rev. 0
110
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
Fault Sharing Response
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
0xD5 Action to be taken by the device when the
FAULT pin is asserted low.
TYPE
R/W Byte
PAGED FORMAT UNITS
Y
NVM
Y
VALUE
MFR_FAULT_RESPONSE
Reg
0xC0
MFR_FAULT_RESPONSE
The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAULTn pin
being pulled low by an external source.
Supported Values:
VALUE
MEANING
0xC0
FAULT_INHIBIT The LTM4681 will three-state the output in response to the FAULT pin pulled low.
FAULT_IGNORE The LTM4681 continues operation without interruption.
0x00
The device also:
•
•
•
Sets the MFR Bit in the STATUS_WORD.
Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULTn Is Being Pulled Low
Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
SCRATCHPAD
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
USER_DATA_00
0xB0
OEM reserved. Typically used for part
serialization.
R/W Word
N
Reg
Y
NA
USER_DATA_01
USER_DATA_02
0xB1
0xB2
Manufacturer reserved for LTpowerPlay.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
NA
NA
OEM reserved. Typically used for part
serialization.
USER_DATA_03
USER_DATA_04
0xB3
0xB4
A NVM word available for the user.
A NVM word available for the user.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
0x0000
0x0000
Rev. 0
111
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
USER_DATA_00 through USER_DATA_04
These commands are non-volatile memory locations for customer storage. The customer has the option to write any
value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of
these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable
inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.
IDENTIFICATION
DATA
FORMAT UNITS
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
NVM
PMBus_REVISION
0x98
PMBus revision supported by this device.
R Byte
N
Reg
Reg
FS
0x22
Current revision is 1.2.
CAPABILITY
0x19
Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
0xB0
MFR_ID
0x99
0x9A
0xE7
The manufacturer ID of the LTM4681 in ASCII.
Manufacturer part number in ASCII.
R String
R String
R Word
N
N
N
ASC
ASC
Reg
LTC
MFR_MODEL
MFR_SPECIAL_ID
LTM4681
0x500X
Manufacturer code representing the LTM4681.
PMBus_REVISION
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4681
is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
This command provides a way for a host system to determine some key capabilities of a PMBus device.
The LTM4681 supports packet error checking, 400kHz bus speeds, and ALERT pin.
This read-only command has one data byte.
MFR_ID
The MFR_ID command indicates the manufacturer ID of the LTM4681 using ASCII characters.
This read-only command is in block format.
MFR_MODEL
The MFR_MODEL command indicates the manufacturer’s part number of the LTM4681 using ASCII characters.
This read-only command is in block format.
MFR_SPECIAL_ID
The 16-bit word representing the part name and revision. 0x414 denotes the part is an LTM4681, X is adjustable by
the manufacturer.
This read-only command has two data bytes.
Rev. 0
112
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
FAULT WARNING AND STATUS
DEFAULT
COMMAND NAME
CLEAR_FAULTS
CMD CODE DESCRIPTION
TYPE
PAGED
N
Y
FORMAT UNITS
NVM
VALUE
0x03
0x1B
Clear any fault bits that have been set. Send Byte
NA
See CMD
Details
SMBALERT_MASK
Mask activity.
Block R/W
Reg
Y
MFR_CLEAR_PEAKS
STATUS_BYTE
0xE3
0x78
Clears all peak values.
One byte summary of the unit’s fault
condition.
Two byte summary of the unit’s fault
condition.
Output voltage fault and warning
status.
Output current fault and warning
status.
Input supply fault and warning status.
External temperature fault and warning R/W Byte
status for READ_TEMERATURE_1.
Send Byte
R/W Byte
Y
Y
NA
NA
Reg
Reg
Reg
Reg
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
0x79
0x7A
0x7B
R/W Word
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
NA
NA
NA
STATUS_INPUT
STATUS_ TEMPERATURE
0x7C
0x7D
N
Y
Reg
Reg
NA
NA
STATUS_CML
0x7E
0x80
Communication and memory fault and R/W Byte
warning status.
N
Y
Reg
Reg
NA
NA
STATUS_MFR_ SPECIFIC
Manufacturer specific fault and state
information.
R/W Byte
MFR_PADS
MFR_COMMON
0xE5
0xEF
Digital status of the I/O pads.
Manufacturer status bits that are
common across multiple ADI chips.
R Word
R Byte
N
N
Reg
Reg
NA
NA
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all
status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output
if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain
set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault
occurs within that time frame it may be cleared before the status register is set.
This write-only command has no data bytes.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut
down for a fault condition are restarted when:
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin
and OPERATION command, to turn off and then to turn back on, or
• MFR_RESET command is issued.
• Bias power is removed and reapplied to the integrated circuit
SMBALERT_MASK
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they
are asserted.
Figure 33 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in
the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command code
is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning
Rev. 0
113
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE
bits would continue to assert ALERT if set.
Figure 53 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state
of any supported status register, again without PEC.
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTM4681.
Factory default masking for applicable status registers is shown below. Providing an unsupported command code to
SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.
SMBALERT_MASK Default Setting: (Refer Also to Figure 2)
STATUS RESISTER
ALERT Mask Value MASKED BITS
STATUS_VOUT
0x00
0x00
0x00
0x00
0x00
0x11
None
STATUS_IOUT
None
STATUS_TEMPERATURE
STATUS_CML
None
None
STATUS_INPUT
None
STATUS_MFR_SPECIFIC
Bit 4 (internal PLL unlocked), bit 0 (FAULT pulled low by external device)
ꢁ
ꢓ
ꢁ
ꢁ
ꢔ
ꢁ
ꢔ
ꢁ
ꢔ
ꢁ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢂꢈꢉꢄꢃꢆRꢊꢋꢈꢄꢂꢌ
ꢍꢎꢈꢈꢄꢏꢇ ꢍꢎꢇꢆ
ꢂꢊꢄꢊꢐꢂꢋꢑ
ꢍꢎꢈꢈꢄꢏꢇ ꢍꢎꢇꢆ
ꢂ
ꢒ
ꢄ
ꢄ
ꢄ
ꢈꢄꢂꢌ ꢉꢕꢊꢆ
ꢄ
ꢀ
ꢖꢗꢔꢁ ꢘꢙꢙ
Figure 55. Example of Writing SMBALERT_MASK
ꢑ
ꢔ
ꢑ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢀꢆꢇꢂꢁꢄRꢈꢉꢆꢂꢀꢊ
ꢋꢌꢆꢆꢂꢍꢅ ꢋꢌꢅꢄ
ꢇꢁꢌꢋꢊ ꢋꢌꢎꢍꢈ
ꢏꢐ ꢑꢒ
ꢀꢈꢂꢈꢎꢀꢉꢖ
ꢋꢌꢆꢆꢂꢍꢅ ꢋꢌꢅꢄ
ꢀ
ꢓ
ꢂ
ꢂ
ꢂ
ꢂ
ꢗ
ꢑ
ꢔ
ꢑ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢑ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢇꢁꢌꢋꢊ ꢋꢌꢎꢍꢈ
ꢏꢐ ꢑꢒ
ꢀꢘ
R
ꢂ
ꢂ
ꢆꢂꢀꢊ ꢇꢞꢈꢄ
ꢍꢂ
ꢙ
ꢚꢛꢕꢑ ꢜꢝꢛ
Figure 56. Example of Reading SMBALERT_MASK
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the
MFR_*_PEAK data values.
This write-only command has no data bytes.
STATUS_BYTE
The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the
lower byte of the status word.
Rev. 0
114
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
STATUS_BYTE Message Contents:
BIT
7*
6
STATUS BIT NAME
MEANING
BUSY
OFF
A fault was declared because the LTM4681 was unable to respond.
This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not
being enabled.
5
4
VOUT_OV
IOUT_OC
VIN_UV
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
Not supported (LTM4681 returns 0).
3
2
TEMPERATURE
CML
A temperature fault or warning has occurred.
A communications, memory or logic fault has occurred.
1
0*
NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.
*ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_
FAULTS command.
This command has one data byte.
STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the
STATUS_WORD is the same as the STATUS_BYTE command.
STATUS_WORD High Byte Message Contents:
BIT
15
14
13
12
11
10
9
STATUS BIT NAME
MEANING
V
An output voltage fault or warning has occurred.
An output current fault or warning has occurred.
An input voltage fault or warning has occurred.
A fault or warning specific to the LTM4681 has occurred.
The POWER_GOOD state is false if this bit is set.
Not supported (LTM4681 returns 0).
OUT
OUT
I
INPUT
MFR_SPECIFIC
POWER_GOOD#
FANS
OTHER
Not supported (LTM4681 returns 0).
8
UNKNOWN
Not supported (LTM4681 returns 0).
If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted.
This command has two data bytes.
STATUS_VOUT
The STATUS_VOUT command returns one byte of V
status information.
OUT
STATUS_VOUT Message Contents:
BIT
MEANING
7
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
overvoltage fault.
overvoltage warning.
undervoltage warning.
undervoltage fault.
max warning.
6
5
4
3
2
TON max fault.
1
TOFF max fault.
0
Not supported (LTM4681 returns 0).
Rev. 0
115
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_IOUT
The STATUS_IOUT command returns one byte of I
status information.
OUT
STATUS_IOUT Message Contents:
BIT
MEANING
7
I
overcurrent fault.
OUT
6
Not supported (LTM4681 returns 0).
I overcurrent warning.
OUT
5
4:0
Not supported (LTM4681 returns 0).
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.
STATUS_INPUT
The STATUS_INPUT command returns one byte of V (VINSNS) status information.
IN
STATUS_INPUT Message Contents:
BIT
MEANING
7
V
IN
overvoltage fault.
6
Not supported (LTM4681 returns 0).
V undervoltage warning.
IN
5
4
Not supported (LTM4681 returns 0).
3
Unit off for insufficient V .
IN
2
Not supported (LTM4681 returns 0).
1
I overcurrent warning.
IN
0
Not supported (LTM4681 returns 0).
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not
generate an ALERT even if it is set. This command has one data byte.
Rev. 0
116
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
STATUS_TEMPERATURE
The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged
command and is related to the respective READ_TEMPERATURE_1 value.
STATUS_TEMPERATURE Message Contents:
BIT
MEANING
7
External overtemperature fault.
External overtemperature warning.
Not supported (LTM4681 returns 0).
External undertemperature fault.
Not supported (LTM4681 returns 0).
6
5
4
3:0
.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
This command has one data byte.
STATUS_CML
The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.
STATUS_CML Message Contents:
BIT
MEANING
7
Invalid or unsupported command received.
Invalid or unsupported data received.
Packet error check failed.
6
5
4
Memory fault detected.
3
Processor fault detected.
2
Reserved (LTM4681 returns 0).
Other communication fault.
Other memory or logic fault.
1
0
If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued
operation of the part is not recommended if these bits are continuously set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
Rev. 0
117
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.
The format for this byte is:
BIT MEANING
7
6
5
4
3
2
1
0
Internal Temperature Fault Limit Exceeded.
Internal Temperature Warn Limit Exceeded.
Factory Trim Area NVM CRC Fault.
PLL is Unlocked
Fault Log Present
V
DD33
UV or OV Fault
ShortCycle Event Detected
FAULT Pin Asserted Low by External Device
If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared
by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
MFR_PADS
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit
assignments of this command are as follows:
BIT ASSIGNED DIGITAL PIN
15
14
V
V
OV Fault
UV Fault
DD33
DD33
13 Reserved
12 Reserved
11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation
10 SYNC clocked by external device (when LTM4681 configured to drive SYNC pin)
9
8
7
6
5
4
3
2
1
0
Channel 1 Power Good
Channel 0 Power Good
LTM4681 Driving RUN1 Low
LTM4681 Driving RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTM4681 Driving FAULT1 Low
LTM4681 Driving FAULT0 Low
FAULT1 Pin State
FAULT0 Pin State
A 1 indicates the condition is true.
This read-only command has two data bytes.
Rev. 0
118
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
MFR_COMMON
The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products.
BIT
MEANING
7
Module Not Driving ALERT Low
LTM4681 Not Busy
Calculations Not Pending
LTM4681 Outputs Not in Transition
NVM Initialized
6
5
4
3
2
Reserved
1
SHARE_CLK Timeout
WP Pin Status
0
This read-only command has one data byte.
TELEMETRY
CMD
DEFAULT
VALUE
COMMAND NAME
READ_VIN
READ_IIN
READ_VOUT
READ_IOUT
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
0x88 Measured input supply voltage.
0x89 Measured input supply current.
0x8B Measured output voltage.
0x8C Measured output current.
0x8D Power stage temperature sensor. This is
the value used for all temperature related
processing, including IOUT_CAL_GAIN.
R Word
R Word
R Word
R Word
R Word
N
N
Y
Y
Y
L11
L11
L16
L11
L11
V
A
V
A
C
NA
NA
NA
NA
NA
READ_TEMPERATURE_1
READ_TEMPERATURE_2
0x8E Internal junction temperature. Does not affect
any other controller commands.
R Word
N
L11
C
NA
READ_FREQUENCY
READ_POUT
READ_PIN
MFR_PIN_ACCURACY
MFR_IOUT_PEAK
0x95 Measured PWM switching frequency.
0x96 Calculated output power.
0x97 Calculated input power.
0xAC Returns the accuracy of the READ_PIN command R Byte
0xD7 Report the maximum measured value of
READ_IOUT since last MFR_CLEAR_PEAKS.
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
R Word
R Word
R Word
Y
Y
N
N
Y
L11
L11
L11
Hz
W
W
%
A
NA
NA
NA
5.0%
NA
R Word
R Word
R Word
R Word
L11
L16
L11
L11
MFR_VOUT_PEAK
MFR_VIN_PEAK
Y
N
Y
V
V
C
NA
NA
NA
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1) since
last MFR_CLEAR_PEAKS.
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS.
R Word
N
L11
A
NA
MFR_READ_ICHIP
0xE4 Measured current used by the LTM4681.
R Word
R Word
N
N
L11
L11
A
C
NA
NA
MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last
MFR_CLEAR_PEAKS.
MFR_ADC_CONTROL
0xD8 ADC telemetry parameter selected for repeated R/W Byte
fast ADC read back.
N
N
Reg
NA
Rev. 0
119
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
READ_VIN
The READ_VIN command returns the measured V pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This
IN
compensates for the IR voltage drop across the V filter element due to the supply current of the LTM4681.
IN
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the measured output voltage by the VOUT_MODE command.
This read-only command has two data bytes and is formatted in Linear_16u format.
READ_IIN
The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor
(see also MFR_IIN_CAL_GAIN).
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_IOUT
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage measured across the I
b) the IOUT_CAL_GAIN value
pins
SENSE
c) the MFR_IOUT_CAL_GAIN_TC value, and
d) READ_TEMPERATURE_1 value
e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the power stage sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the LTM4681’s die temperature, in degrees Celsius, of the internal
sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_FREQUENCY
The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_POUT
The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on
the most recent correlated output voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
Rev. 0
120
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
READ_PIN
The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the
most recent input voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
MFR_PIN_ACCURACY
The MFR_PIN_ACCURACY command returns the accuracy, in percent, of the value returned by the READ_PIN command.
There is one data byte. The value is 0.1% per bit which gives a range of 0.0% to 25.5%.
This read-only command has one data byte and is formatted as an unsigned integer.
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_IIN_PEAK
The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev. 0
121
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
MFR_READ_ICHIP
The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTM4681.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_ADC_CONTROL
The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs
the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of t
.
CONVERT
The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms.
This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions
may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard
telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be
commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command
back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all
warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage
servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.
COMMANDED VALUE
TELEMETRY COMMAND NAME
DESCRIPTION
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
Reserved
Reserved
Reserved
Channel 1 external temperature
Reserved
Channel 1 measured output current
Channel 1 measured output voltage
Channel 0 external temperature
Reserved
Channel 0 measured output current
Channel 0 measured output voltage
Internal junction temperature
Measured input supply current
READ_TEMPERATURE_1
READ_IOUT
READ_VOUT
READ_TEMPERATURE_1
READ_IOUT
READ_VOUT
READ_TEMPERATURE_2
READ_IIN
MFR_READ_ICHIP
Measured supply current of the
LTM4681
0x01
0x00
READ_VIN
Measured input supply voltage
Standard ADC Round Robin Telemetry
If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML
faults will continue to be issued by the LTM4681 until a valid command value is entered. The accuracy of the measured
input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry.
This write-only command has 1 data byte and is formatted in register format.
Rev. 0
122
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
NVM MEMORY COMMANDS
Store/Restore
CMD
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED
FORMAT
UNITS
NVM
STORE_USER_ALL
0x15
0x16
0xF0
Store user operating memory to
EEPROM.
Send Byte
N
NA
RESTORE_USER_ALL
Restore user operating memory from Send Byte
EEPROM.
N
N
NA
NA
MFR_COMPARE_USER_ALL
Compares current command contents Send Byte
with NVM.
STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating
Memory to the matching locations in the non-volatile User NVM memory.
Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data reten-
tion of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is
disabled. The command is re-enabled when the IC temperature drops below 125°C.
Communication with the LTM4681 and programming of the NVM can be initiated when EXTV or VDD33 is available
CC
and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B
followed by 0xC4. The LTM4681 will now communicate normally, and the project file can be updated. To write the
updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be
issued to allow the PWM to be enabled and valid ADCs to be read.
This write-only command has no data bytes.
RESTORE_USER_ALL
The RESTORE_USER_ALL command instructs the LTM4681 to copy the contents of the non-volatile User memory
to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value
retrieved from the User commands. The LTM4681 ensures both channels are off, loads the operating memory from
the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both
PWM channels if applicable.
STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds
130°C and are not re-enabled until the die temperature drops below 125°C.
This write-only command has no data bytes.
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with
what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.
This write-only command has no data bytes.
Rev. 0
123
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
Fault Logging
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_FAULT_LOG
0xEE
0xEA
Fault log data bytes.
R Block
N
N
CF
Y
NA
NA
MFR_FAULT_LOG_ STORE
Command a transfer of the fault log from RAM Send Byte
to EEPROM.
MFR_FAULT_LOG_CLEAR
0xEC
Initialize the EEPROM block reserved for fault
logging.
Send Byte
N
NA
MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occur-
rence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in
non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this
command are listed in Table 15. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the
command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147
bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may
not contain valid data.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
MFR_FAULT_LOG_STORE
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event
occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in
the MFR_CONFIG_ALL command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature
drops below 125°C.
This write-only command has no data bytes.
Rev. 0
124
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
Table 23. Fault Logging
This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
Data Format Definitions
LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1
LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only
BYTE = 8 bits interpreted per definition of this command
DATA
FORMAT BYTE NUM BLOCK READ COMMAND
DATA
BITS
Block Length
BYTE
147
The MFR_FAULT_LOG command is a fixed length of 147 bytes
The block length will be zero if a data log event has not been captured
HEADER INFORMATION
Fault Log Preface
[7:0]
[7:0]
[15:8]
[7:0]
ASC
Reg
0
1
2
Returns LTxx beginning at byte 0 if a partial or complete fault log exists.
Word xx is a factory identifier that may vary part to part.
3
Fault Source
MFR_REAL_TIME
[7:0]
[7:0]
Reg
Reg
4
5
Refer to Table 19.
48 bit share-clock counter value when fault occurred (200µs resolution).
[15:8]
[23:16]
[31:24]
[39:32]
[47:40]
[15:8]
6
7
8
9
10
11
MFR_VOUT_PEAK (PAGE 0)
MFR_VOUT_PEAK (PAGE 1)
MFR_IOUT_PEAK (PAGE 0)
MFR_IOUT_PEAK (PAGE 1)
L16
L16
L11
L11
Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
12
13
Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
14
15
Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
16
17
Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
18
19
20
21
22
23
24
25
26
MFR_VIN_PEAK
L11
L11
L11
L11
Peak READ_VIN since last power-on or CLEAR_PEAKS command.
Power stage temperature sensor 0 during last event.
Power stage temperature sensor 1 during last event.
LTM4681 die temperature sensor during last event.
READ_TEMPERATURE1 (PAGE 0)
READ_TEMPERATURE1 (PAGE 1)
READ_TEMPERATURE2
Rev. 0
125
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
CYCLICAL DATA
EVENT n
Event “n” represents one complete cycle of ADC reads through the MUX
at time of fault. Example: If the fault occurs when the ADC is processing
step 15, it will continue to take readings through step 25 and then store
the header and all 6 event pages to EEPROM
(Data at Which Fault Occurred; Most Recent Data)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
READ_IIN
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
Rev. 0
126
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
EVENT n-1
(data measured before fault was detected)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
READ_IIN
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
EVENT n-5
BYTE
(Oldest Recorded Data)
READ_VOUT (PAGE 0)
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
READ_IIN
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
Rev. 0
127
For more information www.analog.com
LTM4681
PMBus COMMAND DETAILS
Table 24. Explanation of Position_Fault Values
POSITION_FAULT VALUE
SOURCE OF FAULT LOG
0xFF
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x0A
MFR_FAULT_LOG_STORE
TON_MAX_FAULT
VOUT_OV_FAULT
VOUT_UV_FAULT
IOUT_OC_FAULT
TEMP_OT_FAULT
TEMP_UT_FAULT
VIN_OV_FAULT
MFR_TEMP_2_OT_FAULT
MFR_INFO
Contact the factory for details.
MFR_IOUT_CAL_GAIN
Contact the factory for details.
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the
STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is send bytes.
Block Memory Write/Read
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_EE_UNLOCK
0xBD
0xBE
0xBF
Unlock user EEPROM for access by MFR_EE_ERASE
R/W Byte
N
N
N
Reg
Reg
Reg
NA
NA
NA
and MFR_EE_DATA commands.
MFR_EE_ERASE
MFR_EE_DATA
Initialize user EEPROM for bulk programming by
MFR_EE_DATA.
R/W Byte
Data transferred to and from EEPROM using
sequential PMBus word reads or writes. Supports bulk
programming.
R/W
Word
All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the
die temperature drops below 125°C.
MFR_EE_xxxx
The MFR_EE_xxxx commands facilitate bulk programming of the LTM4681 internal EEPROM. Contact the factory for
details.
Rev. 0
128
For more information www.analog.com
LTM4681
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Table 25. LTM4681 BGA Pinout
PIN ID
A1
FUNCTION
GND
PIN ID
B1
FUNCTION
GND
PIN ID
C1
FUNCTION
SW0
PIN ID
D1
FUNCTION
SW0
PIN ID
E1
FUNCTION
SW0
PIN ID
FUNCTION
GND
F1
F2
A2
GND
B2
GND
C2
SW0
D2
SW0
E2
SW0
GND
A3
GND
B3
GND
C3
GND
D3
GND
E3
GND
F3
GND
A4
GND
B4
GND
C4
GND
D4
GND
E4
GND
F4
GND
A5
V
V
B5
V
V
C5
V
V
D5
V
IN01
V
IN01
E5
V
V
F5
V
V
IN01
IN01
IN01
IN01
IN01
IN01
IN01
IN01
IN01
IN01
A6
B6
C6
D6
E6
F6
A7
GND
B7
GND
VOUT1_CFG
ASEL_01
RUN0
C7
GND
D7
GND
E7
GND
F7
GND
–
A8
VOUT0_CFG
B8
C8
V
D8 SHARE_CLK_01 E8
V
F8
V
OSNS1
DD25_01
DD33_01
A9 FSWPH_01_CFG B9
C9
VTRIM1_CFG
SDA_01
D9
VTRIM0_CFG
SCL_01
E9
WP_01
TSNS1
TSNS0
GND
F9
COMP1b
SGND01
SGND01
GND
A10
A11
A12
A13
A14
A15
FAULT1
FAULT0
GND
B10
B11
B12
B13
B14
B15
C10
C11
C12
C13
C14
C15
D10
D11
D12
D13
D14
D15
E10
E11
E12
E13
E14
E15
F10
F11
F12
F13
F14
F15
RUN1
ALERT_01
GND
SYNC_01
GND
GND
V
OUT0
V
OUT0
V
OUT0
V
OUT0
V
OUT0
V
OUT0
V
OUT0
V
OUT0
V
OUT0
V
V
V
V
OUT0
V
OUT0
V
OUT0
V
OUT1
V
OUT1
V
OUT1
OUT0
OUT0
OUT0
PIN ID
G1
FUNCTION
SW1
PIN ID
H1
FUNCTION
SW1
PIN ID
J1
FUNCTION
SW1
PIN ID
K1
FUNCTION
GND
PIN ID
L1
FUNCTION
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PIN ID
M1
FUNCTION
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
G2
SW1
H2
SW1
J2
SW1
K2
GND
L2
M2
G3
GND
H3
GND
J3
GND
K3
GND
L3
M3
G4
GND
H4
GND
J4
GND
K4
GND
L4
M4
G5
V
V
H5
V
IN01
V
IN01
J5
V
V
K5
V
V
L5
M5
IN01
IN01
IN01
IN01
IN01
IN01
G6
H6
J6
K6
L6
M6
G7
GND
H7
GND
J7
GND
SV
K7
GND
GND
GND
GND
GND
GND
L7
M7
+
G8
V
H8
PGOOD1
J8
K8
L8
M8
OSNS1
IN_01
G9
COMP1a
COMP0b
COMP0a
GND
H9
PGOOD0
J9
INTV
K9
L9
M9
CC_01
+
G10
G11
G12
G13
G14
G15
H10
H11
H12
H13
H14
H15
I
J10
J11
J12
J13
J14
J15
I
–
IN_01
K10
K11
K12
K13
K14
K15
L10
L11
L12
L13
L14
L15
M10
M11
M12
M13
M14
M15
IN_01
–
+
V
V
OSNS0
OSNS0
GND
GND
V
V
V
V
V
V
V
OUT1
V
OUT1
V
OUT1
V
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
V
V
Rev. 0
129
For more information www.analog.com
LTM4681
PACKAGE DESCRIPTION
PIN ID
FUNCTION
PIN ID
FUNCTION
PIN ID
R1
FUNCTION
SW2
PIN ID
T1
FUNCTION
SW2
PIN ID
U1
FUNCTION
GND
PIN ID
V1
FUNCTION
SW3
N1
GND
P1
SW2
N2
GND
P2
SW2
R2
SW2
T2
SW2
U2
GND
V2
SW3
N3
GND
P3
GND
R3
GND
T3
GND
U3
GND
V3
GND
N4
GND
P4
GND
R4
GND
T4
GND
U4
GND
V4
GND
N5
V
IN23
V
IN23
P5
V
V
R5
V
IN23
V
IN23
T5
V
V
U5
V
IN23
V
IN23
V5
V
V
IN23
IN23
IN23
IN23
IN23
IN23
N6
P6
R6
T6
U6
V6
N7
GND
GND
P7
GND
R7
GND
T7
GND
U7
GND
TSNS2
TSNS3
SGND23
SGND23
GND
V7
GND
SDA_23
SYNC_23
FAULT2
COMP3a
GND
+
–
N8
P8
V
I
R8
V
I
T8
COMP2a
COMP2b
U8
V8
OSNS2
OSNS2
–
+
N9
V
P9
R9
T9
U9
V9
IN_VBIAS
IN_23
IN_23
N10
N11
N12
N13
N14
N15
V
P10
P11
P12
P13
P14
P15
INTV
R10
R11
R12
R13
R14
R15
PGOOD2
T10
T11
T12
T13
T14
T15
PGOOD3
U10
U11
U12
U13
U14
U15
V10
V11
V12
V13
V14
V15
BIAS
CC_23
IN_23
+
–
RUNP
GND
SV
V
V
OSNS3
OSNS3
GND
GND
GND
V
V
V
V
OUT2
V
OUT2
V
OUT2
V
V
V
V
OUT2
V
OUT2
V
OUT2
V
V
V
V
OUT3
V
OUT3
V
OUT3
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
PIN ID
W1
FUNCTION
SW3
PIN ID
Y1
FUNCTION
SW3
PIN ID
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
FUNCTION
GND
PIN ID
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
FUNCTION
GND
W2
SW3
Y2
SW3
GND
GND
W3
GND
Y3
GND
GND
GND
W4
GND
Y4
GND
GND
GND
W5
V
IN23
V
IN23
Y5
V
V
V
V
V
V
IN23
IN23
IN23
IN23
IN23
IN23
W6
Y6
W7
GND
ALERT_23
SCL_23
FAULT3
COMP3b
GND
Y7
GND
RUN3
RUN2
GND
GND
W8
Y8
VOUT2_CFG
VOUT3_CFG
VTRIM3_CFG
W9
Y9
AA9 FSWPH_23_CFG AB9
AA10 ASEL_23
AA11 SHARE_CLK_23 AB11
W10
W11
W12
W13
W14
W15
Y10
Y11
Y12
Y13
Y14
Y15
V
AB10 VTRIM2_CFG
DD33_23
WP_23
GND
V
DD25_23
AA12
AA13
AA14
AA15
GND
AB12
AB13
AB14
AB15
GND
V
V
V
V
OUT3
V
OUT3
V
OUT3
V
V
OUT3
V
OUT3
V
OUT3
OUT3
OUT3
OUT3
OUT3
OUT3
OUT3
V
V
Rev. 0
130
For more information www.analog.com
LTM4681
PACKAGE DESCRIPTION
ꢲ ꢨ ꢳ ꢢ ꢴ ꢵ e
ꢃ ꢅ ꢨ ꢬ ꢬ ꢬ ꢬ
ꢭ
ꢭ
ꢶ ꢶ ꢝ ꢝ ꢝ
ꢭ
ꢭ
ꢐ ꢐ ꢐ ꢶ ꢶ
ꢡꢡꢡ
ꢭ
ꢣ . 0 0
ꢙ . 0 0
ꢕ . 0 0
ꢚ . 0 0
ꢠ . 0 0
ꢎ . 0 0
ꢘ . 0 0
0 . 0 0
ꢘ . 0 0
ꢎ . 0 0
ꢠ . 0 0
ꢚ . 0 0
ꢕ . 0 0
ꢙ . 0 0
ꢣ . 0 0
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
131
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTM4681
PACKAGE PHOTOGRAPH
DESIGN RESOURCES
SUBJECT
DESCRIPTION
Design:
• Selector Guides
µModule Design and Manufacturing Resources
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4675
Dual 9A or Single 18A Step-Down μModule Regulator with
Digital Power System Management
4.5V ≤ V ≤ 17V, 0.5V ≤ V
≤ 5.5V,
IN
OUT
11.9mm × 16mm × 3.51mm BGA
LTM4686/
LTM4686-1
Ultrathin Dual 10A or Single 20A μModule Regulator with
Digital Power System Management
4.5V ≤ V ≤ 17V, 0.5V ≤ V ≤ 3.6V (LTM4686),
IN
OUT
2.375V ≤ V ≤ 17V (LTM4686-1) 11.9mm × 16mm × 1.82mm LGA
IN
LTM4676A
LTM4677
LTM4678
LTM4664
LTM4680
LTM4700
Dual 13A or Single 26A Step-Down μModule Regulator with 4.5V ≤ V ≤ 26.5V, 0.5V ≤ V
≤ 5.5V,
IN
OUT
Digital Power System Management
16mm × 16mm × 5.01mm BGA
Dual 18A or Single 36A Step-Down μModule Regulator with 4.5V ≤ V ≤ 16V, 0.5V ≤ V
≤ 1.8V, 16mm × 16mm × 5.01mm BGA
≤ 3.4V, 16mm × 16mm × 5.86mm BGA
≤ 1.5V, 16mm × 16mm × 7.72mm BGA
≤ 3.3V, 16mm × 16mm × 7.82mm BGA
≤ 1.8V, 15mm × 22mm × 7.87mm BGA
IN
OUT
OUT
OUT
Digital Power System Management
Dual 25A or Single 50A μModule Regulator with Digital
Power System Management
4.5V ≤ V ≤ 16V, 0.5V ≤ V
IN
54 VIN, Dual 25A or Single 50A μModule Regulator with
Digital Power System Management
30V ≤ V ≤ 58V, 0.5V ≤ V
IN
Dual 30A or Single 60A μModule Regulator with Digital
Power System Management
4.5V ≤ V ≤ 16V, 0.5V ≤ V
IN
OUT
Dual 50A or Single 100A μModule Regulator with Digital
Power System Management
4.5V ≤ V ≤ 16V, 0.5V ≤ V
IN
OUT
Rev. 0
03/21
www.analog.com
132
ANALOG DEVICES, INC. 2021
相关型号:
©2020 ICPDF网 联系我们和版权申明