LTM8060IY_技术文档

LTM8060

Quad 40V , Silent Switcher μModule Regulator

IN

with Configurable 3A Output Array

FEATURES

DESCRIPTION

The LTM^®8060 is quad 40V_IN, 3A step-down Silent

n

Four Complete Step-Down Switching Power Supplies

Low Noise Silent Switcher^®Architecture

CISPR22 Class B Compliant

Switcher μModule^®regulator. The Silent Switcher archi-

tecture minimizes EMI while delivering high efficiency at

frequencies up to 3MHz. Included in the package are the

controllers, power switches, inductors, and support com-

ponents. Operating over a wide input voltage range, the

LTM8060 supports output voltages from 0.8V to 8V, and

a switching frequency range of 200kHz to 3MHz, each set

by a single resistor. Only the bulk input and output filter

capacitors, are needed to finish the design. The LTM8060

product video is available on website.

n

CISPR25 Class 5 Compliant

Wide Input Voltage Range: 3V to 40V

Wide Output Voltage Range: 0.8V to 8V

3A Continuous Output Current per Channel at 12V ,

IN

3.3V , T = 80°C

OUT

A

n

4A Continuous Output Current per Channel at 12V ,

IN

3.3V , f = 2MHz, T = 60°C

OUT SW

A

Multiphase or Multi-μModule Parallelable for

Increased Output Current

The LTM8060 is packaged in a compact (11.9mm ×

16mm × 3.32mm) over-molded Ball Grid Array (BGA)

package suitable for automated assembly by standard

surface mount equipment. The LTM8060 is available with

SnPb (BGA) or RoHS compliant.

Low Thermal Resistance, θ = 9°C/W,

JA

θ

= 4.2°C/W, θ

= 1.6°C/W

JCtop

JCbot

n

Selectable Switching Frequency: 200kHz to 3MHz

Compact Package

Configurable Output Array

APPLICATIONS

The LTM8060 outputs can be paralleled in an array for up

to 12A capability.

n

Automated Test Equipment

n

Industrial Supplies

Medical Equipment

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ꢂꢁ

ꢃꢁ

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ꢄꢅꢁ

All registered trademarks and trademarks are the property of their respective owners.

ꢂꢁ

ꢀꢁ

Click to view associated Video Design Idea.

TYPICAL APPLICATION

Quad 3A Output from 8.5V to 40V Input

Efficiency, V_IN= 24V, BIAS = 5V

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PINS NOT USED:

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ꢇꢊꢀRꢋꢉꢄ ꢌꢍꢈꢄ

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ꢀꢁ.ꢂꢃ

ꢀ ꢁ00ꢂꢃꢄ

ꢀ00ꢁꢂ

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Rꢀꢁꢂ

ꢀꢁꢂꢃ

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0

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ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢎꢏꢐꢑꢁꢆꢅꢉ

ꢀ

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ꢀ0ꢁ0 ꢂꢃ0ꢄꢅ

ꢀꢁꢂꢃ

ꢀ

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ꢀ0ꢁ0 ꢂꢃ0ꢄꢅ

Rev. 0

1

Document Feedback

For more information www.analog.com

LTM8060

ABSOLUTE MAXIMUM RATINGS

(Note 1)

SYNCn .......................................................................6V

Maximum Internal Temperature (Note 2).............. 125°C

Storage Temperature ............................. –55°C to 125°C

Peak Solder Reflow Package Body Temperature .. 245°C

V

, RUNn, PGn ......................................................42V

OUTn

INn

, BIASn, AUXn ................................................10V

FBn, TRSSn, SHAREn, RTn .......................................4V

PIN CONFIGURATION

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ꢧꢭꢨꢄꢇꢑ Rꢦꢨꢑ Rꢦꢨꢇ

ꢬꢀꢇ

ꢬꢀꢑ ꢂꢦꢖꢑ ꢀꢡꢂꢧꢇꢑ ꢂꢦꢖꢇ

ꢧꢢꢂRꢆꢑ

ꢧꢢꢂRꢆꢇ

Rꢓꢇꢑ ꢓRꢧꢧꢑ ꢓRꢧꢧꢇ

ꢇꢇ

ꢇ0

ꢎ

ꢀꢂꢨꢅꢟ

ꢡꢨꢑ

ꢀꢂꢨꢅꢈ

ꢡꢨꢇ

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ꢌꢨꢄ

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ꢥ

ꢀꢂꢨꢅꢐ

ꢩꢦꢓꢑ

ꢀꢂꢨꢅꢣ

ꢩꢦꢓꢇ

ꢥ

ꢣ

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ꢀꢂꢨꢅꢑ

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ꢧꢢꢂRꢆꢐ

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ꢩꢦꢓꢐ

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ꢃꢁꢟ ꢄꢋꢅꢩꢦꢓꢐꢟ

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Rꢦꢨꢐ Rꢦꢨꢟ ꢧꢭꢨꢄꢐꢟ

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ꢗ ꢇꢑꢉꢘꢄꢙ θ ꢗ ꢎꢘꢄꢚꢛꢙ θ

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ꢗ ꢇ.ꢈꢘꢄꢚꢛꢙ ꢛꢆꢡꢁꢢꢓ ꢗ ꢇ.ꢎꢣꢤ

θ

θ ꢥꢂꢋꢦꢆꢧ ꢌꢆꢓꢆRꢕꢡꢨꢆꢌ ꢃꢆR ꢔꢆꢌꢆꢄ ꢉꢇ ꢄꢩꢨꢌꢡꢓꢡꢩꢨꢧꢪ

θ

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ORDER INFORMATION

PART MARKING*

PACKAGE

TYPE

MSL

RATING

TEMPERATURE RANGE

(SEE NOTE 2)

PART NUMBER

LTM8060IY#PBF

LTM8060IY

BALL FINISH

SAC305 (RoHS)

SnPb (63/37)

DEVICE

FINISH CODE

e1

e0

–40°C to 125°C

LTM8060Y

BGA

3

• Device temperature grade is indicated by a label on the shipping container. • This product is not recommended for second side reflow.

This product is moisture sensitive. For more information, go to

Recommended BGA PCB Assembly and Manufacturing Procedures.

• Pad code is per IPC/JEDEC J-STD-609.

• BGA Package and Tray Drawings

Rev. 0

2

For more information www.analog.com

LTM8060

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

internal temperature range, otherwise specifications are at T_A= 25°C. V_INn= 12V, RUNn = 2V unless otherwise noted (Notes 2, 3).

PARAMETER

Minimum V Input Voltage

CONDITIONS

MIN

TYP

MAX

UNITS

l

3.0

2.0

V

IN1

Minimum V

Input Voltage

IN34

Minimum V Input Voltage

V

IN1

= 3V

IN2

Output DC Voltage

FBn open

FBn = 21.5kΩ

0.8

10

V

Maximum Output DC Current

(Note 4)

6

8

A

Quiescent Current into V

RUNn = 0

BIASn = 5V, SYNCn = 3.3V, No load

μA

mA

INn

7

Current into BIAS

RUNn = 0, BIASn = 5V

0.5

μA

n

BIASn = 5V, SYNCn = 3.3V, No load

18

0.05

0.1

10

mA

Line Regulation

Load Regulation

Output RMS Ripple

FBn Voltage

5V < V < 40V, I

= 1A

OUTn

%

INn

12V , 0.1A < I

< 4A

INn

OUTn

3.3V

, I

= 4A

mV

OUTn OUTn

792

784

800

808

816

mV

l

Current out of FBn

V _n= 1V, FBn = 0V

OUT

4

μA

V

Minimum BIASn for Proper Operation

3.2

Switching Frequency

RTn = 200kΩ

RTn = 35.7kΩ

RTn = 8.06kΩ

200

1

3

kHz

MHz

RUNn Threshold

0.74

V

RUNn Input Current

PGn Threshold at FBn

RUNn = 0V

100

nA

Lower Threshold

Upper Threshold

740

860

mV

PGn Output Sink Current

PGn = 0.1V

100

μA

V

CLKOUTn V

0.2

3.2

OL

OH

V

SYNCn Input High Threshold

SYNCn Input Low Threshold

SYNCn Threshold to Enable Spread Spectrum

SYNCn Current

1.5

2.8

V

0.8

4.0

V

SYNCn = 6V

TRSSn = 0V

60

2

μA

Ω

TRSSn Source Current

TRSSn Pull-Down Resistance

Fault Condition, TRSSn = 0.1V

200

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTM8060E is guaranteed to meet performance specifications

from 0°C to 125°C internal. Specifications over the full –40°C to

125°C internal operating temperature range are assured by design,

characterization and correlation with statistical process controls.

The LTM8060I is guaranteed to meet specifications over the full –40°C

to 125°C internal operating temperature range. Note that the maximum

internal temperature is determined by specific operating conditions in

conjunction with board layout, the rated package thermal resistance and

other environmental factors.

Note 3: n Represents each individual channel. Four outputs are tested

separately and the same testing condition is applied to each output.

Note 4: The maximum current out of any channel may be limited by the

internal temperature of the LTM8060. See output current derating curves

for different V , V

and T .

IN OUT

A

Rev. 0

3

For more information www.analog.com

LTM8060

T_A= 25°C, operating per Table 1,unless otherwise noted.

Efficiency and Power Loss

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency and Power Loss

V_OUT= 0.8V, BIAS = 5V, Burst Mode

V_OUT= 1V, BIAS = 5V, Burst Mode

V_OUT= 1.2V, BIAS = 5V, Burst Mode

ꢀ0

ꢀ

ꢀ0

ꢀ

0

ꢀ0

ꢀ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃR ꢄꢁꢅꢅ

0

ꢀ

0

ꢀ

0

ꢀ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀ0ꢁ0 ꢂ0ꢃ

Efficiency and Power Loss

V_OUT= 1.8V, BIAS = 5V, Burst Mode

Efficiency and Power Loss

V

_OUT= 1.5V, BIAS = 5V, Burst Mode

V_OUT= 2V, BIAS = 5V, Burst Mode

ꢀꢁ

ꢀꢀ

ꢀ

ꢀꢁ

ꢀꢀ

ꢀ

ꢀꢁ

ꢀꢀ

ꢀ

0

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀ

0

ꢀ

0

ꢀꢁꢂ

ꢀꢁꢂꢃR ꢄꢁꢅꢅ

0

ꢀ

0

ꢀ

0

ꢀ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀ0ꢁ0 ꢂ0ꢃ

ꢀ0ꢁ0 ꢂ0ꢁ

Efficiency and Power Loss

V_OUT= 2.5V, BIAS = 5V, Burst Mode

Efficiency and Power Loss

V_OUT= 3.3V, BIAS = 5V, Burst Mode

V_OUT= 5V, BIAS = 5V, Burst Mode

ꢀꢁ

ꢀꢀ

ꢀ

ꢀ00

ꢀ

ꢀ00

ꢀ0

ꢀ

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀ

0

ꢀ0

ꢀ

0

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃR ꢄꢁꢅꢅ

0

ꢀ

0

ꢀ

0

ꢀ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀ0ꢁ0 ꢂ0ꢃ

ꢀ0ꢁ0 ꢂ0ꢀ

ꢀ0ꢁ0 ꢂ0ꢃ

Rev. 0

4

For more information www.analog.com

LTM8060

T_A= 25°C, operating per Table 1,unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency and Power Loss

V_OUT= 8V, BIAS = 5V, Burst Mode

Input vs Load Current, V_OUT= 0.8V

BIAS = 5V Burst Mode

Input vs Load Current, V_OUT= 1V

BIAS = 5V, Burst Mode

0.ꢀ

0

ꢀ00

ꢀ0

ꢀ

0

0.ꢀ

0

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃR ꢄꢁꢅꢅ

0

ꢀ

0

ꢀ

0

ꢀ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀ0ꢁ0 ꢂꢃ0

ꢀ0ꢁ0 ꢂꢃꢃ

Input vs Load Current, V_OUT= 1.2V

BIAS = 5V, Burst Mode

Input vs Load Current, V_OUT= 1.5V

BIAS = 5V, Burst Mode

Input vs Load Current, V_OUT= 1.8V

BIAS = 5V, Burst Mode

0.ꢀ

0

0.ꢀ

0

0.ꢀ

0

ꢀꢁꢂ

ꢀꢁ

0

ꢀ

0

ꢀ

0

ꢀ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀ0ꢁ0 ꢂꢃꢄ

Input vs Load Current, V_OUT= 2V

BIAS = 5V, Burst Mode

Input vs Load Current, V_OUT= 2.5V

BIAS = 5V, Burst Mode

Input vs Load Current, V_OUT= 3.3V

BIAS = 5V, Burst Mode

ꢀ.ꢁ

0.ꢀ

0

0.ꢀ

0

ꢀ.ꢁ

0.ꢀ

0

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

0

ꢀ

0

ꢀ

0

ꢀ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀ0ꢁ0 ꢂꢃꢁ

ꢀ0ꢁ0 ꢂꢃꢀ

Rev. 0

5

For more information www.analog.com

LTM8060

T_A= 25°C, operating per Table 1,unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Derating, V_OUT= 0.8V

BIAS = 5V, DC2820A Demo Board

Input vs Load Current, V_OUT= 5V

BIAS = 5V, Burst Mode

T_J= 120°C, Burst Mode

Input vs Load Current, V_OUT= 8V

BIAS = 5V, Burst Mode

All Channels at Same Load

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀ.ꢁ

ꢀ.0

0.ꢀ

0

ꢀ.ꢁ

0.ꢀ

0

0 ꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁ

ꢀ.0

ꢀꢁꢂ

ꢀꢁ

ꢀ.0

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀ

0

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀ0ꢁ0 ꢂꢃ0

Derating, V_OUT= 1V

Derating, V_OUT= 1.2V

Derating, V_OUT= 1.5V

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

All Channels at Same Load

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

0 ꢀꢁꢂ

ꢀ.0

ꢀꢁꢂ

ꢀꢁ

ꢀ.0

ꢀꢁꢂ

ꢀ.0

ꢀꢁ

ꢀꢁꢂ

ꢀꢁ

ꢀ.0

ꢀꢁꢂ

ꢀ.0

ꢀꢁꢂ

ꢀ.0

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢃ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

Derating, V_OUT= 2V

Derating, V_OUT= 2.5V

Derating, V_OUT= 1.8V

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

All Channels at Same Load

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

0 ꢀꢁꢂ

ꢀ.0

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀ.0

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

Rev. 0

6

For more information www.analog.com

LTM8060

T_A= 25°C, operating per Table 1,unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Derating, V_OUT= 3.3V

Derating, V_OUT= 3.3V, f_SW= 2MHz

Derating, V_OUT= 5V

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

All Channels at Same Load

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

0 ꢀꢁꢂ

ꢀ.0

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀ.0

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀ0ꢁ0 ꢂꢃ0

ꢀ0ꢁ0 ꢂꢃꢀ

Derating with Airflow

Derating, V_OUT= 5V, f_SW= 2MHz

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

Derating, V_OUT= 8V

12V_INto 1.5V_OUT, T_J= 120°C

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

BIAS = 5V, DC2820A Demo Board

Forced Continuous Mode

All Channels at Same Load

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

0 ꢀꢁꢂ

ꢀ.0

ꢀꢁꢂ

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀ.0

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀ0ꢁ0 ꢂꢃꢃ

ꢀ0ꢁ0 ꢂꢃꢄ

Derating with Airflow

12V_INto 1.5V_OUT, T_J= 120°C

BIAS = 5V, DC2820A Demo Board

Forced Continuous Mode

36V_INto 1.5V_OUT, T_J= 120°C

12V_INto 3.3V_OUT, T_J= 120°C

BIAS = 5V, DC2820A Demo Board

Forced Continuous Mode

BIAS = 5V, DC2820A Demo Board

Forced Continuous Mode

All Channels at Same Load

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

ꢀ.0

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀ0ꢁ0 ꢂꢃꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

Rev. 0

7

For more information www.analog.com

LTM8060

T_A= 25°C, operating per Table 1,unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Derating with Airflow

24V_INto 3.3V_OUT, T_J= 120°C

BIAS = 5V, DC2820A Demo Board

Forced Continuous Mode

All Channels at Same Load

36V_INto 3.3V_OUT, T_J= 120°C

12V_INto 5V_OUT, T_J= 120°C

BIAS = 5V, DC2820A Demo Board

Forced Continuous Mode

BIAS = 5V, DC2820A Demo Board

Forced Continuous Mode

All Channels at Same Load

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

ꢀ.0

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀ0ꢁ0 ꢂꢃꢀ

ꢀ0ꢁ0 ꢂꢃꢄ

Derating with Airflow

36V_INto 5V_OUT, T_J= 120°C

24V_INto 5V_OUT, T_J= 120°C

CISPR22 Class B Emissions

DC2820A Demo Board

BIAS = 5V, DC2820A Demo Board

Forced Continuous Mode

All Channels at Same Load

BIAS = 5V, DC2820A Demo Board

Forced Continuous Mode

V

_IN= 24V, V_OUT= 5V, f_SW= 1.2MHz

All Channels at Same Load

All Channels Paralleled, I_OUT= 10A

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢁ.0

ꢀ0.0

ꢀ.0

ꢀꢀ

ꢀꢁ

ꢀ

ꢀ.0

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

0ꢀꢁꢂ

ꢀ00ꢁꢂꢃ

ꢀꢁꢂꢃe ꢄꢅꢁꢁꢆ

ꢀ.0

ꢀꢁꢂeꢃ ꢀꢄeꢅꢆeꢇꢈꢉ

ꢀꢁꢂeꢃꢄ ꢀꢁeꢅꢆꢂꢇꢈ

ꢀꢁꢂꢃꢃ ꢄ ꢅeꢂꢆ ꢇꢈꢉꢈꢊ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀꢁ

ꢀ

0

ꢀ00

ꢀ000

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃ0

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀ0ꢁ0 ꢂꢃꢄ

Output Voltage Ripple

DC2820A Demo Board

V_IN= 12V, V_OUT= 3.3V

I_OUT= 3A, f_SW= 1MHz

CISPR25 Radiated Emission with Class 5

Peak Limit DC2820A Demo Board

Output Noise Spectrum

DC2820A Demo Board

V_IN= 24V, V_OUT= 5V

V

_IN= 14V, V_OUT= 5V, f_SW= 1.2MHz

All Channels Paralleled, I_OUT= 12A

I_OUT= 3A, f_SW= 1.2MHz

ꢀ0

0

ꢀ0

ꢀꢁꢂꢃꢄ ꢅꢆꢁꢁR

ꢀꢁRꢂꢃꢄꢅꢆꢇꢈ ꢁꢉꢊꢋꢉꢊ ꢀꢁꢅꢌꢇ

ꢀ0

ꢀꢁꢂꢃꢄꢅꢂ

ꢀꢁꢂꢁꢃꢄꢅꢆꢇꢈ

0

ꢀꢁ0

ꢀ0ꢁ0 ꢂꢃꢃ

ꢀꢁꢂꢃꢃ ꢄ ꢅꢆꢂꢇ ꢁꢈꢉꢈꢊ

ꢀꢁꢂeꢃꢄ ꢀꢁeꢅꢆꢂꢇꢈ

ꢀꢁꢂeꢃ ꢀꢄeꢅꢆeꢇꢈꢉ

ꢀ00ꢁꢂꢃꢄꢅꢆ

0

ꢀ00

ꢀ000

0

ꢀ00

ꢀ000

ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ

ꢀ0ꢁ0 ꢂꢃꢄ

Rev. 0

8

For more information www.analog.com

LTM8060

T_A= 25°C, operating per Table 1,unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

BIAS Current vs Frequency

12V_INto 3.3V_OUT

Forced Continuous Mode

Input Current vs V_IN

V_OUTShort Circuited

Dropout Voltage vs Load Current

ꢀ000

ꢀꢁ00

ꢀ000

ꢀ00

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ0

ꢀ

ꢀ.ꢁ

0.ꢀ

0

ꢀꢁꢂꢃꢄ ꢅꢆꢇe

ꢀꢁꢂꢃeꢄ ꢅꢁꢆꢇꢈꢆꢉꢁꢉꢊ ꢋꢁꢄe

0

ꢀ

ꢀ0

ꢀꢁ

ꢀ0

ꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀ0

ꢀꢁ

ꢀ0

0

ꢀ

0

ꢀ

ꢀꢁꢂꢃꢄꢅꢂꢆꢇ ꢈRꢉꢊꢋꢉꢆꢄꢌ ꢍꢎꢅꢏꢐ

ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ

ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢀ

ꢀ0ꢁ0 ꢂꢃꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

Single Channel Derating, V_OUT

=

Single Channel Derating, V_OUT

=

Single Channel Derating, V_OUT

5V CH1 ON, CH2/CH3/CH4 OFF

=

1.5V CH1 ON, CH2/CH3/CH4 OFF

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

3.3V CH1 ON, CH2/CH3/CH4 OFF

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

ꢀ

0

ꢀ

0

ꢀ

0

0 ꢀꢁꢂ

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

ꢀ0ꢁ0 ꢂꢃ0

ꢀ0ꢁ0 ꢂꢃꢄ

Dual Channel Derating, V_OUT

=

Dual Channel Derating, V_OUT

=

Dual Channel Derating, V_OUT= 5V

CH1/CH3 ON, CH2/CH4 OFF

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

3.3V CH1/CH3 ON, CH2/CH4 OFF

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

1.5V CH1/CH3 ON, CH2/CH4 OFF

BIAS = 5V, DC2820A Demo Board

T_J= 120°C, Burst Mode

ꢀ

0

ꢀ

0

ꢀ

0

0 ꢀꢁꢂ

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

0

ꢀꢁ

ꢀ0

ꢀꢁ

ꢀ00

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ

ꢀ0ꢁ0 ꢂꢃꢄ

Rev. 0

9

For more information www.analog.com

LTM8060

PIN FUNCTIONS

V

(Bank 6): Input power for the channel 1 regulator. The

voltages of 3.3V and above these pins should be tied to

V . If these pins are tied to a supply other than V

OUTn

V^IN1powers the internal control circuitry for channel 1/2

IN1

OUTn

and is monitored by undervoltage lockout circuitry. The

V_IN1voltage must be greater than 3V for either chan-

nel 1/2 of the LTM8060 to operate. Decouple V_IN1to

ground with an external, low ESR capacitor. See Table 1

for recommended values.

use a local bypass capacitor on these pins.

SYNC12/34 (Pins C11/N1): External Clock Synchronization

Input. Ground these pins for low ripple Burst Mode^®

operation at low output loads; this will also disable the

CLKOUT function. Apply a DC voltage between 2.8V and

4V for forced continuous mode operation with spread

spectrum modulation. Float the SYNC_npin for forced

continuous mode operation without spread spectrum

V

(Bank 4): Input power for the channel 2 regulator.

IN2

Decouple V_IN2to ground with an external, low ESR capaci-

tor. See Table 1 for recommended values.

modulation. Apply a clock source to the SYNC pin for

n

V

(Bank 5): Input power for the channel 3/4 regulator.

IN34

The V

synchronization to an external frequency. The LTM8060

will be in forced continuous mode when an external fre-

quency is applied.

bank powers the internal control circuitry for

both channel 3/4 and is monitored by undervoltage lock-

out circuitry. The V_IN34voltage must be greater than 3V for

either channel 3/4 of the LTM8060 to operate. Decouple

CLKOUT12/34 (Pins C10/N2): Synchronization Output.

When SYNC12/34 > 2.8V, the CLKOUT12/34 pins pro-

vide a waveform about 90 degrees out-of-phase with

Channel 1/3, respectively. This allows synchronization with

other regulators with up to four phases. When an external

clock is applied to the SYNC12/34 pins, the CLKOUT12/34

pins will output a waveform with about the same phase,

duty cycle, and frequency as the SYNC12/34 waveform.

In Burst Mode operation, the CLKOUT12/34 pins will be

internally grounded. Float these pin if the CLKOUT12/34

function is not used. Do not drive these pins.

V

to ground with an external, low ESR capacitor. See

IN34

Table 1 for recommended values.

GND (Bank 2): Tie these GND pins to a local ground plane

below the LTM8060 and the circuit components. In most

applications, the bulk of the heat flow out of the LTM8060

is through these pads, so the printed circuit design has a

large impact on the thermal performance of the part. See

the PCB Layout and Thermal Considerations sections for

more details. Return the feedback divider (R ) to this net.

FB

V_OUT1/2/3/4(Banks 8/3/1/7): Power Output for

Channel 1/2/3/4, Respectively. Apply the output filter

capacitor and the output load between these pins and

GND plane.

FB1/2/3/4 (Pins K11/K10/F1/F2): The LTM8060 regulates

the FB pin to 800mV. Connect the feedback resistor to

n

this pin to set the output voltage.

RT12/34 (Pins L11/E1): Connect a resistor between RT

n

AUX1/2/3/4 (Pins N10/L10/C2/E2): Low Current Voltage

Source for BIAS. In many designs, the BIAS pin is simply

and ground to set the switching frequency. Do not drive

these pins.

connected to V

by way of the AUX pin. The AUX pins

OUT

n

are internally connected to V_OUTnand placed adjacent

RUN1/2/3/4 (Pins E11/D11/L1/M1): The corresponding

to the BIAS pins to ease printed circuit board routing.

channel of the LTM8060 is shutdown when these pins

n

Although these pins are internally connected to V , it

are low and active when these pins are high. Tie to V if

OUT

INn

is not intended to deliver a higher current, so do NOT

connect these pins to the load. If thess pins are not tied

to BIAS, leave it floating.

shutdown feature is not used. An external resistor divider

from V can be used to program a V threshold below

INn

which ^It^Nhⁿe corresponding channel of the LTM8060 will

shut down. Do not float these pins.

BIAS12/34 (Pins M10/D2): The internal regulator will

draw current from BIAS instead of V or V when

n

IN1

IN34

BIAS is tied to a voltage higher than 3.2V. For output

n

Rev. 0

10

For more information www.analog.com

LTM8060

PIN FUNCTIONS

TRSS1/2/3/4 (Pins N11/M11): Output Tracking and Soft-

PG1/2/3/4 (Pins E9/D10/L3/M2): The PG_npind str the

open-drain output of an internal comparator. PG_nremains

low until the FB pin is within 7.5% of the final regulation

Start Pins. These pins allow user control of output volt-

age ramp rate during start-up. A TRSS voltage below

n

0.8V forces the LTM8060 to regulate the FB pin to equal

voltage, and thⁿere are no fault conditions. PG is pulled

n

the TRSS pin voltage. When TRSS is above 0.8V, the

low during V UVLO, thermal shutdown, or when the

tracking fⁿunction is disabled and the internal reference

resumes control of the error amplifier. An internal 2μA

pull-up current on these pins allow a capacitor to pro-

gram output voltage slew rate. These pins are pulled to

ground during shutdown and fault conditions; use a series

resistor if driving from a low impedance output. These

pins may be left floating if the soft-start feature is not

being used.

RUN pins are low.

n

INn

n

SHARE1/2/3/4 (Pind K8/K9/F4/F3): Channel 1/2/3/4

Current Sharing Control. Tie SHARE_ntogether when

paralleling outputs. LTM8060 can also share current

between modules. See Typical Application section for

current sharing between channels and current sharing

between modules.

DNC (Pind E10/L2): Do not connect.

BLOCK DIAGRAM

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢄꢄꢆꢇꢈꢉ

ꢀ0ꢁꢂ

ꢀꢁRꢀꢂꢁꢃRꢄ

ꢀ.ꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢂ

ꢀꢁꢂꢃRꢁꢄꢄꢅR

ꢀRꢁꢁꢂ

ꢀ0ꢁꢂ

0.ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ0ꢁꢂ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢂ

ꢀꢁꢂꢃRꢁꢄꢄꢅR

ꢀRꢁꢁꢂ

ꢀ0ꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢄꢄꢆꢇꢈꢉ

ꢀꢁRꢀꢂꢁꢃRꢄ

ꢀ0ꢁꢂ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢂ

ꢀꢁꢂꢃRꢁꢄꢄꢅR

ꢀRꢁꢁꢂ

ꢀ0ꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢂ

ꢀꢁꢂꢃRꢁꢄꢄꢅR

ꢀRꢁꢁꢂ

ꢀ0ꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ0ꢁ0 ꢂꢃ

Rev. 0

11

For more information www.analog.com

LTM8060

OPERATION

The LTM8060 is a quad standalone nonisolated step-

down switching DC/DC power supply that can deliver a

peak current of up to 6A per channel. The continuous cur-

rent is determined by the internal operating temperature.

It provides a precisely regulated output voltage program-

mable via one external resistor from 0.8V to 8V. The input

To enhance efficiency, the LTM8060 automatically

switches to Burst Mode operation in light or no load

situations. Between bursts, all circuitry associated with

controlling the output switch is shut down reducing the

input supply current to just a few µA.

The TRSSn node acts as an auxiliary input to the error

amplifier. The voltage at FBn servos to the TRSSn voltage

until TRSSn goes above 0.8V. Soft-start is implemented

by generating a voltage ramp at the TRSSn pin using an

external capacitor which is charged by an internal 2μA

constant current. Alternatively, driving the TRSSn pin with

a signal source or resistive network provides a tracking

function. Do not drive the TRSSn pin with a low imped-

ance voltage source. See the Applications Information

section for more details.

voltage range for V and V

is 3V to 40V, while the

IN1

IN34

input voltage range for V is 2V to 40V.

IN2

Given that the LTM8060 is a step-down converter, make

sure that the input voltage is high enough to support the

desired output voltage and load current. See simplified

Block Diagram.

The LTM8060 contains current mode controllers, power

switching elements, power inductors and a modest

amount of input and output capacitance. The LTM8060 is

a fixed frequency PWM regulator. The switching frequency

is set by simply connecting the appropriate resistor value

from the RTn pin to GND.

The LTM8060 contains power good comparators which

trip when the FBn pin is at about ±8% of its regulated

value. The PGn output is an open-drain transistor that is

off when the output is in regulation, allowing an external

resistor to pull the PGn pin high.

Internal regulators provide power to the control circuit-

ries. Bias regulators normally draw power from the V

INn

pin, but if the BIASn pin is connected to an external volt-

age higher than 3.2V, bias power is drawn from the exter-

nal source (typically the regulated output voltage). This

improves efficiency. Tie BIASn to GND if it is not used.

The LTM8060 is equipped with a thermal shutdown that

inhibits power switching at high junction temperatures.

The activation threshold of this function is above the max-

imum temperature rating to avoid interfering with normal

operation, so prolonged or repetitive operation under a

condition in which the thermal shutdown activates may

damage or impair the reliability of the device.

Rev. 0

12

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LTM8060

APPLICATIONS INFORMATION

For most applications, the design process is straight-

forward, summarized as follows:

Set Output Voltage

The Output Voltage is programmed with a FB resistor

as shown in the Figure below. Choose the resistor value

according to Equation 1.

1. Look at Table 1 and find the row that has the desired

input range and output voltage.

249kΩ

2. Apply the recommended C_IN, C_OUT, R_FBand R_Tvalues.

3. Connect BIAS as indicated.

R_FB

=

(2)

V

^OUT−1

0.8V

When using the LTM8060 with different output voltages,

the higher frequency recommended by Table 1 will usu-

ally result in the best operation. While these component

combinations have been tested for proper operation, it is

incumbent upon the user to verify proper operation over

the intended system’s line, load and environmental condi-

tions. Bear in mind that the maximum output current is

limited by junction temperature, the relationship between

the input and output voltage magnitude and other fac-

tors. Please refer to the graphs in the Typical Performance

Characteristics section for guidance.

1% resistor is recommended to maintain output voltage

accuracy.

ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢂ

ꢀꢁꢂꢃRꢁꢄꢄꢅR

ꢀ

ꢀꢁꢂ

ꢀ.ꢁꢂꢃ

0.ꢀꢁ

0.ꢀꢁꢂ

ꢀ0ꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁ

R

ꢀꢁ

ꢀ0ꢁ0 ꢂ0ꢃ

The maximum frequency (and attendant R_Tvalue) at

which the LTM8060 should be allowed to switch is given

Figure 1. Set Output Voltage with a FB Resistor

in Table 1 in the Maximum f column, while the recom-

SW

mended frequency (and R value) for optimal efficiency

T

over the given input condition is given in the f column.

SW

There are additional conditions that must be satisfied if

the synchronization function is used. Please refer to the

Synchronization section for details.

Rev. 0

13

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LTM8060

APPLICATIONS INFORMATION

Capacitor Selection Considerations

Ceramic capacitors are also piezoelectric. In Burst Mode

operation, the LTM8060’s switching frequency depends

on the load current, and can excite a ceramic capacitor

at audio frequencies, generating audible noise. Since the

LTM8060 operates at a lower current limit during Burst

Mode operation, the noise is typically very quiet to a

casual ear.

The C and C

capacitor values in Table 1 are the mini-

OUT

mum^Ir^Necommended values for the associated operating

conditions. Applying capacitor values below those indi-

cated in Table 1 is not recommended and may result in

undesirable operation. Using larger values is generally

acceptable, and can yield improved dynamic response,

if it is necessary. Again, it is incumbent upon the user to

verify proper operation over the intended system’s line,

load and environmental conditions.

If this audible noise is unacceptable, use a high perfor-

mance electrolytic capacitor at the output. It may also be

a parallel combination of a ceramic capacitor and a low

cost electrolytic capacitor.

Ceramic capacitors are small, robust and have very low

ESR. However, not all ceramic capacitors are suitable. X5R

and X7R types are stable over temperature and applied

voltage and give dependable service. Other types, includ-

ing Y5V and Z5U have very large temperature and voltage

coefficients of capacitance. In an application circuit they

may have only a small fraction of their nominal capaci-

tance resulting in much higher output voltage ripple

than expected.

A final precaution regarding ceramic capacitors concerns

the maximum input voltage rating of the LTM8060. A

ceramic input capacitor combined with trace or cable

inductance forms a high-Q (underdamped) tank circuit.

If the LTM8060 circuit is plugged into a live supply, the

input voltage can ring to twice its nominal value, possi-

bly exceeding the device’s rating. This situation is easily

avoided; see the Hot-Plugging Safely section.

Table 1. Recommended Component Values and Configuration (T_A= 25°C)

R

f

R

MAX f

MIN R

(Ω)

FB

SW

T

SW

T

1

2

V

(Ω)

0.8V Open 4.7µF 50V X5R 1206 2 × 100µF 4V X5R 0805 3.2V to 10V 100pF

1V 1M 4.7µF 50V X5R 1206 2 × 100µF 4V X5R 0805 3.2V to 10V 100pF

C

BIAS

CFF

(Hz)

400k

(Ω)

(Hz)

600k

725k

IN

OUT

IN

OUT

3V to 40V

100k

64.9k

52.3k

3V to 40V

3.2V to 40V

3.5V to 40V

4.2V to 40V

5.5V to 40V

8.5V to 40V

11V to 40V

1.2V 499k 4.7µF 50V X5R 1206 2 × 100µF 4V X5R 0805 3.2V to 10V

1.5V 287k 4.7µF 50V X5R 1206 2 × 100µF 4V X5R 0805 3.2V to 10V

1.8V 200k 4.7µF 50V X5R 1206 1 × 100µF 4V X5R 0805 3.2V to 10V

68pF

500k

600k

650k

700k

800k

1M

76.8k

64.9k

59k

875k

1M

42.2k

35.7k

25.5k

23.2k

18.2k

12.7k

8.06k

–

1.3M

1.4M

1.7M

2.2M

3M

2V

2.5V 118k 4.7µF 50V X5R 1206 1 × 47µF 4V X5R 0805

3.3V 78.7k 4.7µF 50V X5R 1206 1 × 47µF 6.3V X5R 0805 3.2V to 10V

165k 4.7µF 50V X5R 1206 1 × 100µF 4V X5R 0805 3.2V to 10V

54.9k

46.4k

35.7k

27.4k

19.6k

3.2V to 10V

5V

8V

47.5k 4.7µF 50V X5R 1206 1 × 47µF 6.3V X5R 1206 3.2V to 10V

27.4k 4.7µF 50V X5R 1206 1 × 47µF 10V X5R 1206 3.2V to 10V

1.2M

1.6M

3M

Note 1: The LTM8060 may be capable of the operating at lower input voltages but may skip switching cycles.

Note 2: A bulk input capacitor is required.

Rev. 0

14

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LTM8060

APPLICATIONS INFORMATION

Frequency Selection

excessive heat or even damage the LTM8060 if the output

is overloaded or short-circuited. A frequency that is too

low can result in a final design that has too much output

ripple or too large of an output capacitor.

The LTM8060 uses a constant frequency PWM architec-

ture that can be programmed to switch from 200kHz to

3MHz by using a resistor tied from the RT pin to ground.

Table 2 provides a list of R resistor values and their resul-

T

BIASn Pin Considerations

tant frequencies. The resistors in the table are standard

The BIASn pin is used to provide drive power for the

internal power switching stage and operate other internal

circuitry. For proper operation, it must be powered by at

least 3.2V. If the output voltage is programmed to 3.2V

1% E96 values.

Operating Frequency Trade-Offs

It is recommended that the user apply the optimal R_Tvalue

given in Table 1 for the input and output operating condi-

tion. When using the LTM8060 with different output volt-

ages, the higher frequency recommended by Table 1 will

usually result in the best operation. System level or other

considerations, however, may necessitate another operat-

ing frequency. While the LTM8060 is flexible enough to

accommodate a wide range of operating frequencies, a

haphazardly chosen one may result in undesirable opera-

tion under certain operating or fault conditions. A fre-

quency that is too high can reduce efficiency, generate

or higher, BIASn may be simply tied to V

. If V

is less than 3.2V, BIASn can be tied to ^OV^U_IN^Tn_nor s^Oo^Um^Teⁿ

other voltage source. If the BIASn pin voltage is too high,

the efficiency of the LTM8060 may suffer. The optimum

BIASn voltage is dependent upon many factors, such as

load current, input voltage, output voltage and switching

frequency. In all cases, ensure that the maximum volt-

age at the BIASn pin is less than 10V. If BIASn power is

applied from a remote or noisy voltage source, it may be

necessary to apply a decoupling capacitor locally to the

pin. A 1µF ceramic capacitor works well. The BIASn pin

may also be tied to GND at the cost of a small degrada-

tion in efficiency.

Table 2. Switching Frequency vs R_TValue

f

(MHz)

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

R (kΩ)

T

SW

200

137

Maximum Load

The maximum practical continuous load that the LTM8060

can drive per channel, while rated at 3A, actually depends

upon both the internal current limit and the internal tem-

perature. The internal current limit is designed to prevent

damage to the LTM8060 in the case of overload or short-

circuit. The internal temperature of the LTM8060 depends

upon operating conditions such as the ambient tempera-

ture, the power delivered, and the heat sinking capabil-

100

76.8

64.9

54.9

46.4

41.2

35.7

27.4

23.2

19.6

16.9

14.7

12.7

11.3

10.2

9.09

8.06

ity of the system. For example, if V

configured to regulate at 1.5V, and the other 3 channels

are turned off, V may continuously deliver 6A from

of LTM8060 is

OUT1

24V_INif the ambient temperature is controlled to less

than 60°C. This is quite a bit higher than the 3A continu-

ous rating. Please see graphs in the Typical Performance

Characteristics section. Similarly, if all 4 channels of the

LTM8060 are delivering 3.3V

and the ambient tem-

OUT

perature is 100°C, each channel will deliver at most 1.5A

from 24V , which is less than the 3A continuous rating.

IN

Rev. 0

15

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LTM8060

APPLICATIONS INFORMATION

Power Derating

resistance. Thermal models are derived from several

temperature measurements in a controlled temperature

chamber along with thermal FEA modeling.

The 12V , 24V and 36V power loss curves can be

IN

used in coordination with the load current derating curves

for calculating an approximate θ thermal resistance for

The junction temperatures are monitored while ambient

temperature is increased with and without airflow. The

power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at ~120°C maximum while lowering output

current or power while increasing ambient temperature.

The decreased output current will decrease the internal

module loss as ambient temperature is increased.

JA

the LTM8060 with airflow conditions. The power loss

curves are taken at room temperature, and are increased

with a 1.35 to 1.4 multiplicative factor at 125°C. These

factors come from the fact that the power loss of the

regulator increases about 45% from 25°C to 150°C, thus

a 45% spread over 125°C delta equates to ~0.35%/°C loss

increase. A 125°C maximum junction minus 25°C room

temperature equates to a 100°C increase. This 100°C

increase multiplied by 0.35%/°C equals a 35% power loss

increase at the 125°C junction, thus the 1.35 multiplier.

The derived thermal resistances in Table 3 through Table 5

for the various conditions can be multiplied by the calcu-

lated power loss as a function of ambient temperature to

derive temperature rise above ambient, thus maximum

junction temperature. Room temperature power loss can

be derived from the power loss curves and adjusted with

the above ambient temperature multiplicative factors. The

printed circuit board is a 1.6mm thick 6-layer board with

two ounce copper (50μm) for all the layers.

The derating curves are plotted with four V

at the

same operating condition starting at 16A o^Of ^Uto^Tntal load

current and low ambient temperature. The derating curves

with airflow are measured at output voltages of 1.5V,

3.3V and 5V. These are chosen to include the lower and

higher output voltage ranges for correlating the thermal

Table 3. 1.5V Output

DERATING CURVE

8060 G33-35

V

(V)

POWER LOSS CURVE

8060 G04

AIRFLOW (LFM)

HEAT SINK

None

θ

JA

θ

JA

θ

JA

(°C/W)

9

IN

12, 24, 36

0

8060 G04

200

400

None

7.5

8060 G04

None

6.5

Table 4. 3.3V Output

DERATING CURVE

8060 G36-38

V

(V)

POWER LOSS CURVE

8060 G08

AIRFLOW (LFM)

HEAT SINK

None

(°C/W)

9

IN

12, 24, 36

0

8060 G36-38

8060 G08

200

400

None

7.5

8060 G36-38

8060 G08

None

6.5

Table 5. 5V Output

DERATING CURVE

8060 G39-41

V

(V)

POWER LOSS CURVE

8060 G09

AIRFLOW (LFM)

HEAT SINK

None

(°C/W)

9

IN

12, 24, 36

0

8060 G39-41

8060 G09

200

400

None

7.5

8060 G39-41

8060 G09

None

6.5

Rev. 0

16

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LTM8060

APPLICATIONS INFORMATION

Load Sharing

V_IN1must be above 3V for channel 1 and channel 2 to

operate. If V_IN1is above 3V, channel 2 will operate as long

The four LTM8060 channels may be paralleled to produce

higher currents. To do this on two or more LTM8060, tie

as V is above 2V.

IN2

the V , V

, FBn and SHAREn pins of all the paral-

V_IN34must be above 3V for channel 3 and channel 4

to operate.

INn OUTn

leled channels/modules together. To ensure that paralleled

channels start up together, the TRSSn pins may be tied

together, as well. If it is inconvenient to tie the TRSSn

pins together, make sure that the same value soft-start

capacitors are used for each µModule regulator. When

Output Voltage Tracking and Soft-Start

The LTM8060 allows the user to adjust its output voltage

ramp rate by means of the TRSSn pin. An internal 2μA

pulls up the TRSSn pin to about 2.4V. Putting an external

capacitor on TRSSn enables soft starting the output to

reduce current surges on the input supply. During the

soft-start ramp the output voltage will proportionally track

the TRSSn pin voltage. For output tracking applications,

TRSSn can be externally driven by another voltage source.

From 0V to 0.8V, the TRSSn voltage will override the

internal 0.8V reference input to the error amplifier, thus

regulating the FBn pin voltage to that of the TRSSn pin.

When TRSSn is above 0.8V, tracking is disabled and the

feedback voltage will regulate to the internal reference

voltage. The TRSSn pin may be left floating if the function

is not needed.

load sharing among n units and using a single R resis-

FB

tor, the value of the resistor is given by Equation 1.

199.2

n(V_OUT− 0.8)

(1)

R_FB=

,where R_FBis in kΩ

Examples of load sharing applications are given in Figure 6

through Figure 9.

Burst Mode Operation

To enhance efficiency at light loads, the LTM8060

automatically switches to Burst Mode operation which

keeps the output capacitor charged to the proper volt-

age while minimizing the input quiescent current. During

Burst Mode operation, the LTM8060 delivers single cycle

bursts of current to the output capacitor followed by sleep

periods where most of the internal circuitry is powered off

and energy is delivered to the load by the output capacitor.

During the sleep time, V_INnand BIASn quiescent currents

are greatly reduced, so, as the load current decreases

towards a no load condition, the percentage of time that

the LTM8060 operates in sleep mode increases and the

average input current is greatly reduced, resulting in

higher light load efficiency.

An active pull-down circuit is connected to the TRSSn

pin which will discharge the external soft-start capacitor

in the case of fault conditions and restart the ramp when

the faults are cleared. Fault conditions that clear the soft-

start capacitor are the RUNn pin transitioning low, V

INn

voltage falling too low, or thermal shutdown.

Pre-Biased Output

As discussed in the Output Voltage Tracking and Soft-Start

section, the LTM8060 regulates the output to the FBn volt-

age determined by the TRSSn pin whenever TRSSn is less

than 0.8V. If the LTM8060 output is higher than the target

output voltage, and SYNCn is not held below 0.8V, the

LTM8060 will attempt to regulate the output to the target

voltage by returning a small amount of energy back to the

input supply. If there is nothing loading the input supply,

its voltage may rise. Take care that it does not rise so high

that the input voltage exceeds the absolute maximum rat-

ing of the LTM8060. If SYNC is grounded, the LTM8060

will not return current to the input.

Burst Mode operation is enabled by tying SYNC to GND.

Minimum Input Voltage

The LTM8060 is a step-down converter, so a minimum

amount of headroom is required to keep the output in

regulation. Keep the input above 3V to ensure proper

operation. Voltage transients or ripple valleys that cause

the input to fall below 3V may turn off the LTM8060.

Rev. 0

17

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LTM8060

APPLICATIONS INFORMATION

Frequency Foldback

Shorted Input Protection

The LTM8060 is equipped with frequency foldback which

acts to reduce the thermal and energy stress on the inter-

nal power elements during a short circuit or output over-

load condition. If the LTM8060 detects that the output

has fallen out of regulation, the switching frequency is

reduced as a function of how far the output is below the

target voltage. This in turn limits the amount of energy

that can be delivered to the load under fault. During the

start-up time, frequency foldback is also active to limit

the energy delivered to the potentially large output capaci-

Care needs to be taken in systems where the output is

held high when the input to the LTM8060 is absent. This

may occur in battery charging applications or in battery

backup systems where a battery or some other supply

is diode OR’ed with the LTM8060’s output. If the V

INn

pin is allowed to float and the RUNn pin is held high

(either by a logic signal or because it is tied to V_INn),

then the LTM8060’s internal circuitry pulls its quiescent

current through its internal power switch. This is fine if

your system can tolerate a few milliamps in this state.

If you ground the RUNn pin, the internal current drops

tance of the load. When a clock is applied to the SYNC

n

pin, the SYNC pin is floated or held high, the frequency

foldback is diⁿsabled, and the switching frequency will

slow down only during overcurrent conditions.

to essentially zero. However, if the V pin is grounded

INn

while the output is held high, parasitic diodes inside the

LTM8060 can pull large currents from the output through

the V pin. Figure 2 shows a circuit that runs only when

INn

Synchronization

the input voltage is present and that protects against a

shorted or reversed input.

To select low ripple Burst Mode operation, tie the SYNC

n

pin below about 0.8V (this can be ground or a logic low

output). To synchronize the LTM8060 oscillator to an

external frequency, connect a square wave (with about

ꢀ

ꢁꢂ

20% to 80% duty cycle) to the SYNC pin. The square

n

ꢀꢁꢂꢃ0ꢄ0

wave amplitude should have valleys that are below 0.8V

and peaks above 1.5V.

Rꢀꢁ

ꢀ0ꢁ0 ꢂ0ꢃ

The LTM8060 may be synchronized over a 200kHz to

3MHz range. The LTM8060 will not enter Burst Mode

operation at light output loads while synchronized to an

Figure 2. The Input Diode Prevents a Shorted Input from

Discharging a Backup Battery Tied to the Output. It Also Protects

the Circuit from a Reversed Input. The LTM8060 Runs Only

When the Input Is Present.

external clock. The R resistor should be chosen to set

T

the switching frequency equal to or below the lowest

synchronization input. For example, if the synchroniza-

tion signal will be 500kHz and higher, the R should be

PCB Layout

T

selected for 500kHz or lower.

Most of the headaches associated with PCB layout have

been alleviated or even eliminated by the high level of

integration of the LTM8060. The LTM8060 is neverthe-

less a switching power supply, and care must be taken to

minimize EMI and ensure proper operation. Even with the

high level of integration, you may fail to achieve specified

operation with a haphazard or poor layout. See Figure 3

for a suggested layout. Ensure that the grounding and

heat sinking are acceptable.

The LTM8060 features spread spectrum operation to fur-

ther reduce EMI/EMC emissions. To enable spread spec-

trum operation, apply between 2.8V and 4V to the SYNC

n

pin. In this mode, triangular frequency modulation is used

to vary the switching frequency between the value pro-

grammed by R to about 20% higher than that value. The

T

modulation frequency is about 7kHz. For example, when

the LTM8060 is programmed to 2MHz, the frequency will

vary from 2MHz to 2.4MHz at a 7kHz rate. When spread

spectrum operation is selected, Burst Mode operation is

disabled, and the part may run in discontinuous mode.

Rev. 0

18

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LTM8060

APPLICATIONS INFORMATION

A few rules to keep in mind are:

ꢀ

ꢇꢈꢉ

ꢀ

ꢇꢈꢄ

Rꢃꢉꢄ

1. Place the R and R resistors as close as possible to

FB

T

their respective pins.

2. Place the C capacitor as close as possible to the V

IN

ꢀ

ꢁꢂꢃꢅ

ꢁꢂꢃꢄ

and GND connection of the LTM8060.

3. Place the C

capacitor as close as possible to the

OUT

V

and GND connection of the LTM8060.

OUT

ꢀ

ꢁꢂꢃꢅ

ꢁꢂꢃꢆ

4. Place the C_INand C_OUTcapacitors such that their

ground current flow directly adjacent to or underneath

the LTM8060.

ꢀ

ꢇꢈꢅꢆ

Rꢃꢅꢆ

5. Connect all of the GND connections to as large a cop-

per pour or plane area as possible on the top layer.

Avoid breaking the ground connection between the

external components and the LTM8060.

ꢊ0ꢋ0 ꢌ0ꢅ

Figure 3. Layout Showing Suggested External Components,

GND Plane and Thermal Vias

6. Use vias to connect the GND copper area to the

board’s internal ground planes. Liberally distribute

these GND vias to provide both a good ground con-

nection and thermal path to the internal planes of the

printed circuit board. Pay attention to the location and

density of the thermal vias in Figure 3. The LTM8060

can benefit from the heat sinking afforded by vias that

connect to internal GND planes at these locations,

due to their proximity to internal power handling

components. The optimum number of thermal vias

depends upon the printed circuit board design. For

example, a board might use very small via holes. It

should employ more thermal vias than a board that

uses larger holes.

of the LTM8060 can ring to more than twice the nominal

input voltage, possibly exceeding the LTM8060’s rating

and damaging the part. If the input supply is poorly con-

trolled or the LTM8060 is hot-plugged into an energized

supply, the input network should be designed to prevent

this overshoot. This can be accomplished by installing

a small resistor in series to V , but the most popular

INn

method of controlling input voltage overshoot is add an

electrolytic bulk cap to the V net. This capacitor’s rela-

INn

tively high equivalent series resistance damps the circuit

and eliminates the voltage overshoot. The extra capacitor

improves low frequency ripple filtering and can slightly

improve the efficiency of the circuit, though it is likely to

be the largest component in the circuit.

Hot-Plugging Safely

Thermal Considerations

The small size, robustness and low impedance of ceramic

capacitors make them an attractive option for the input

bypass capacitor of LTM8060. However, these capacitors

can cause problems if the LTM8060 is plugged into a

live supply (see Application Note 88 for a complete dis-

cussion). The low loss ceramic capacitor combined with

stray inductance in series with the power source forms an

The LTM8060 output current may need to be derated if

it is required to operate in a high ambient temperature.

The amount of current derating is dependent upon the

input voltage, output power and ambient temperature.

The derating curves given in the Typical Performance

Characteristics section can be used as a guide. These

underdamped tank circuit, and the voltage at the V pin

INn

Rev. 0

19

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LTM8060

APPLICATIONS INFORMATION

curves were generated by the LTM8060 mounted to a

104cm²6-layer FR4 printed circuit board. Boards of

other sizes and layer count can exhibit different thermal

behavior, so it is incumbent upon the user to verify proper

operation over the intended system’s line, load and envi-

ronmental operating conditions.

3. θ_JCtopis determined with nearly all of the compo-

nent power dissipation flowing through the top of the

package. As the electrical connections of the typical

µModule regulator are on the bottom of the package,

it is rare for an application to operate such that most

of the heat flows from the junction to the top of the

part. As in the case of θ_JCbot, this value may be useful

for comparing packages but the test conditions don’t

generally match the user’s application.

For increased accuracy and fidelity to the actual applica-

tion, many designers use FEA (Finite Element Analysis) or

CFD (Computational Fluid Dynamics) to predict thermal

performance. To that end, the Pin Configuration typically

gives three dominant thermal coefficients:

Given these definitions, it should now be apparent that

none of these thermal coefficients reflects an actual physi-

cal operating condition of a µModule regulator. Thus, none

of them can be individually used to accurately predict the

thermal performance of the product. Likewise, it would

be inappropriate to attempt to use any one coefficient to

correlate to the junction temperature vs load graphs given

in the product’s data sheet. The only appropriate way to

use the coefficients is when running a detailed thermal

analysis, such as FEA, which considers all of the thermal

resistances simultaneously.

1. θ – Thermal resistance from junction to ambient

JA

2. θ

– Thermal resistance from junction to the bot-

JCbot

tom of the product case

3. θ

– Thermal resistance from junction to top of

JCtop

the product case

While the meaning of each of these coefficients may seem

to be intuitive, JEDEC has defined each to avoid confusion

and inconsistency. These definitions are given in JESD

51-12, and are quoted or paraphrased below:

A graphical approximation of these dominant thermal

resistances is given in Figure 4. Some thermal resis-

tance elements, such as heat flow out the side of the

package, are not defined by the JEDEC standard, and are

not shown. The blue resistances are contained within the

µModule regulator, and the green are outside.

1. θ_JAis the natural convection junction-to-ambient

air thermal resistance measured in a one cubic foot

sealed enclosure. This environment is sometimes

referred to as “still air” although natural convection

causes the air to move. This value is determined with

the part mounted to a JESD 51-9 defined test board,

which does not reflect an actual application or viable

operating condition.

The die temperature of the LTM8060 must be lower than

the maximum rating, so care should be taken in the layout

of the circuit to ensure good heat sinking of the LTM8060.

The bulk of the heat flow out of the LTM8060 is through

the bottom of the package and the pads into the printed

circuit board. Consequently a poor printed circuit board

design can cause excessive heating, resulting in impaired

performance or reliability. Please refer to the PCB Layout

section for printed circuit board design suggestions.

2. θ_JCbotis the junction-to-board thermal resistance

with all of the component power dissipation flow-

ing through the bottom of the package. In the typical

µModule regulator, the bulk of the heat flows out the

bottom of the package, but there is always heat flow

out into the ambient environment. As a result, this

thermal resistance value may be useful for compar-

ing packages but the test conditions don’t generally

match the user’s application.

Rev. 0

20

For more information www.analog.com

LTM8060

APPLICATIONS INFORMATION

ꢄꢅꢆꢇꢈꢉe ꢊꢋꢌꢍꢎꢋ

θ

ꢏꢒꢓꢎꢔꢍꢕꢓꢖꢔꢕꢖꢗꢅꢜꢍꢋꢓꢔ Rꢋꢘꢍꢘꢔꢗꢓꢎꢋ

ꢏꢗ

θ

ꢏꢒꢓꢎꢔꢍꢕꢓꢖꢔꢕꢖꢎꢗꢘꢋ

ꢎꢗꢘꢋ ꢙꢔꢕꢚꢛꢖꢔꢕꢖꢗꢅꢜꢍꢋꢓꢔ

ꢏꢎꢐꢆꢑ

ꢙꢔꢕꢚꢛ Rꢋꢘꢍꢘꢔꢗꢓꢎꢋ

Rꢋꢘꢍꢘꢔꢗꢓꢎꢋ

ꢏꢒꢓꢎꢔꢍꢕꢓ

ꢗꢅꢜꢍꢋꢓꢔ

θ

ꢏꢎꢝꢆꢐ

ꢏꢒꢓꢎꢔꢍꢕꢓꢖꢔꢕꢖꢎꢗꢘꢋ

ꢎꢗꢘꢋ ꢙꢜꢕꢔꢔꢕꢅꢛꢖꢔꢕꢖꢜꢕꢗRꢊ

Rꢋꢘꢍꢘꢔꢗꢓꢎꢋ

ꢜꢕꢗRꢊꢖꢔꢕꢖꢗꢅꢜꢍꢋꢓꢔ

Rꢋꢘꢍꢘꢔꢗꢓꢎꢋ

ꢙꢜꢕꢔꢔꢕꢅꢛ Rꢋꢘꢍꢘꢔꢗꢓꢎꢋ

ꢀ0ꢁ0 ꢂ0ꢃ

Figure 4. Graphical Representation of Thermal Coefficients, Including JESD51-12 Terms

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅ

ꢀ

ꢀꢁ

ꢀ.ꢁꢂ ꢃꢄ ꢅ0ꢂ

Rꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁ.ꢂꢃ

ꢀ ꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁ.ꢂꢃ

Rꢀꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢀ.ꢀꢁ

ꢀꢁ

ꢀꢁꢂꢃ

ꢀꢁ.ꢀꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁ

PINS NOT USED:

ꢀꢁ.ꢂꢃ

ꢀ ꢁꢂꢃꢄ

ꢀꢁ

ꢀꢁ.ꢂꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄ ꢀꢁꢂꢅꢄ ꢆRꢇꢇꢈꢄ

ꢆRꢇꢇꢃꢄ ꢆRꢇꢇꢉꢄ ꢆRꢇꢇꢅꢄ

ꢇꢊꢀRꢋꢈꢄ ꢇꢊꢀRꢋꢃꢄ

ꢇꢊꢀRꢋꢉꢄ ꢇꢊꢀRꢋꢅꢄ

ꢌꢍꢈꢄ ꢌꢍꢃꢄ ꢌꢍꢉꢄ

Rꢀꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢀ.ꢀꢁ

ꢌꢍꢅꢄ ꢎꢏꢐꢑꢁꢆꢈꢃꢄ

ꢎꢏꢐꢑꢁꢆꢉꢅ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁ.ꢀꢂ

ꢀꢁꢂ

ꢀ0ꢁ0 ꢂ0ꢃ

ꢀ.ꢁꢂꢃ

ꢀꢁ

Figure 5. 8.5V to 40V Input to 5V at 3A, 3.3V at 3A, 5V at 3A, and 3.3V at 3A

Rev. 0

21

For more information www.analog.com

LTM8060

TYPICAL APPLICATIONS

ꢀ

ꢀꢁꢂ

ꢀRꢁꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁꢂ

ꢀ.ꢀꢁ ꢂꢃ ꢄ0ꢁ

Rꢀꢁꢂ

ꢀRꢁꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁ.ꢂꢃ

ꢀ ꢁꢂꢃꢄ

ꢀꢁ.ꢂꢃ

Rꢀꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

ꢀ

ꢀꢁꢂꢃꢀ

ꢀ

ꢀꢁꢂꢃ

ꢀ.ꢀꢁ

ꢀꢁ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀ

ꢀꢁꢂ

Rꢀꢁꢂ

ꢀꢁꢂRꢃꢄ

ꢀ.ꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂRꢃꢄ

ꢀ

ꢀꢁꢂꢃ

ꢀRꢁꢁꢂ

ꢀꢁ

ꢀꢁꢂ

ꢀ.ꢁꢂ ꢃꢄ ꢅ0ꢂ

ꢀRꢁꢁꢂ

ꢀ.ꢁꢂꢃ

ꢄꢅ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁ.ꢂꢃ

ꢀ ꢁ00ꢂꢃꢄ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅ

ꢀ

ꢀꢁꢂꢃꢀ

ꢀ

ꢀꢁꢂꢃ

ꢀ.ꢁꢂ

ꢀꢁ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀꢁꢂ

PINS NOT USED:

ꢀꢁꢂꢃꢄ ꢀꢁꢂꢅꢄ ꢀꢁꢂꢆꢄ ꢀꢁꢂꢇꢄ

ꢈꢉꢀꢊꢃꢅꢄ ꢈꢉꢀꢊꢆꢇ

ꢋꢌꢃꢄ ꢋꢌꢅꢄ ꢋꢌꢆꢄ

ꢀꢁꢂRꢃꢄ

ꢀ0ꢁ0 ꢂ0ꢁ

ꢋꢌꢇꢄ ꢍꢎꢏꢐꢁꢑꢃꢅꢄ

Figure 6. 5.5V to 40V Input to Paralleled 3.3V at 6A; 3.2V to 40V Input to Paralleled 1.5V at 6A

Rev. 0

22

For more information www.analog.com

LTM8060

TYPICAL APPLICATIONS

ꢀꢁ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢂꢃ ꢄ0ꢁ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ00ꢁ

Rꢀꢁꢂ

ꢀ

ꢀ ꢁ00ꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

Rꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

Rꢀꢁꢂ

ꢀ.ꢁꢂꢃ

ꢄꢀ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀ00ꢁ

Rꢀꢁꢂ

ꢀ

ꢀ ꢁ00ꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀꢁꢂ

PINS NOT USED:

ꢀꢁꢂꢃꢄ ꢀꢁꢂꢅꢄ ꢀꢁꢂꢆꢄ ꢀꢁꢂꢇꢄ

ꢈꢉꢀꢊꢃꢅꢄ ꢈꢉꢀꢊꢆꢇꢄ

ꢀꢁꢂ

ꢋꢌꢃꢄ ꢋꢌꢅꢄ ꢋꢌꢆꢄ ꢋꢌꢇꢄ

ꢍꢎꢏꢐꢁꢑꢆꢇ

ꢀ0ꢁ0 ꢂ0ꢃ

Figure 7. 3V to 40V Input to Paralleled 1V at 12A

Rev. 0

23

For more information www.analog.com

LTM8060

TYPICAL APPLICATIONS

ꢀꢁ

ꢀ.ꢁꢂꢃ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢂꢃ

ꢄ0ꢁ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ00ꢁ

ꢀ ꢁ00ꢂꢃꢄ

ꢀ00ꢁ

ꢀ ꢁ00ꢂꢃꢄ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

Rꢀꢁꢂ

ꢀꢁꢂ

Rꢀꢁꢂ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂꢃꢄꢅ

Rꢀꢁꢂ

ꢀ.ꢁꢂꢃ

ꢄꢀ

ꢀ.ꢁꢂꢃ

ꢄꢀ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀ00ꢁ

ꢀ ꢁ00ꢂꢃꢄ

ꢀ00ꢁ

ꢀ ꢁ00ꢂꢃꢄ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀꢁ

ꢀꢁꢂ

PINS NOT USED:

0

0 0

ꢀꢁꢂꢃ ꢀꢁꢂꢄꢃ ꢀꢁꢂꢅꢃ ꢀꢁꢂꢆꢃ

ꢇꢈꢀꢉꢊꢄꢃ ꢇꢈꢀꢉꢅꢆ

ꢋꢌꢊꢃ ꢋꢌꢄꢃ ꢋꢌꢅꢃ ꢋꢌꢆ

Figure 8. Two LTM8060 are Paralleled to Supply 1V/24A Output in Forced Continuous Mode

Rev. 0

24

For more information www.analog.com

LTM8060

TYPICAL APPLICATIONS

ꢀꢁ

ꢀ.ꢁꢂꢃ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁ

ꢀꢁ ꢂꢃ ꢄ0ꢁ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ00ꢁ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁꢂꢃꢄ0ꢄ

ꢀꢁꢂꢃ

ꢀ

ꢀ ꢁ00ꢂꢃꢄ

ꢀꢁ

ꢀ.ꢁꢂꢃ

ꢄꢀ

ꢀ.ꢁꢂꢃ

ꢄꢀ

ꢀ

ꢀꢁꢂꢃ

Rꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ00ꢁ

Rꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀ00ꢁꢂ

ꢃꢄ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅ

0

0 0

PINS NOT USED:

ꢀꢁꢂꢃꢄ ꢀꢁꢂꢅ. ꢀꢁꢂꢆꢄ ꢀꢁꢂꢇꢄ

ꢈꢉꢀꢊꢃꢅꢄ ꢈꢉꢀꢊꢆꢇꢄ

ꢋꢌꢃꢄ ꢋꢌꢅꢄ ꢋꢌꢆꢄ ꢋꢌꢇꢄ

ꢍꢎꢏꢐꢁꢑꢃꢅꢄ ꢍꢎꢏꢐꢁꢑꢆꢇ

Figure 9. Two LTM8060 are Paralleled to Supply 1V/24A Output with 45° Phase Shift Interleaving Through All Eight Channels

Rev. 0

25

For more information www.analog.com

LTM8060

PACKAGE DESCRIPTION

Table 6. LTM8060 Pinout (Sorted by Pin Number)

Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name

A1

A2

V

B1

B2

V

C1

C2

C3

C4

C5

C6

C7

C8

C9

TRSS3

AUX3

GND

D1

D2

D3

D4

D5

D6

D7

D8

D9

TRSS4

BIAS34

GND

E1

E2

RT34

AUX4

GND

PG1

F1

F2

FB3

FB4

G1

G2

V

H1

H2

V

OUT3

IN34

A3

B3

E3

F3

SHARE4 G3

SHARE3 G4

GND

H3

GND

A4

B4

GND

E4

F4

H4

A5

GND

B5

GND

E5

F5

GND

G5

G6

H5

A6

B6

GND

E6

F6

H6

A7

B7

GND

E7

F7

G7

H7

A8

V

B8

V

GND

E8

F8

G8

H8

OUT2

A9

V

B9

V

GND

E9

F9

G9

H9

A10

A11

B10

B11

C10 CLKOUT12 D10

C11 SYNC12 D11

PG2

E10

E11

DNC

RUN1

F10

F11

V

G10

G11

V

H10

H11

V

IN2

IN1

RUN2

Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name

J1

J2

V

K1

K2

K3

K4

K5

K6

K7

V

L1

L2

L3

L4

L5

L6

L7

RUN3

DNC

PG3

M1

M2

M3

M4

M5

M6

M7

M8

M9

RUN4

PG4

N1 SYNC34

P1

V

R1

R2

V

IN34

OUT4

N2 CLKOUT34 P2

J3

GND

N3

N4

N5

N6

N7

N8

N9

GND

P3

P4

R3

J4

GND

AUX2

RT12

R4

J5

GND

P5

GND

R5

GND

J6

GND

P6

R6

J7

GND

P7

R7

J8

K8 SHARE1 L8

K9 SHARE2 L9

GND

P8

V

R8

V

OUT1

J9

GND

P9

V

R9

V

J10

J11

V

K10

K11

FB2

FB1

L10

L11

M10 BIAS12 N10

M11 TRSS2 N11

AUX1

TRSS1

P10

P11

R10

R11

IN1

Rev. 0

26

For more information www.analog.com

LTM8060

PACKAGE DESCRIPTION

ꢟ

ꢴ ꢴ ꢭ ꢭ ꢭ

ꢟ

ꢒ . 0 0 0

ꢑ . 0 0 0

ꢐ . 0 0 0

ꢏ . 0 0 0

ꢎ . 0 0 0

0 . 0 0 0

ꢎ . 0 0 0

ꢏ . 0 0 0

ꢐ . 0 0 0

ꢑ . 0 0 0

ꢒ . 0 0 0

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

27

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.analog.com

LTM8060

PACKAGE PHOTO

DESIGN RESOURCES

SUBJECT

DESCRIPTION

µModule Design and Manufacturing Resources

Design:

Manufacturing:

• Selector Guides

• Quick Start Guide

• Demo Boards and Gerber Files

• Free Simulation Tools

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

Digital Power System Management

Analog Devices’ family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

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LTM8071

LTM8051

LTM4643

LTM4644

40V, 3.5A Step-Down Silent Switcher µModule Regulator

3.4V ≤ V ≤ 40V, 0.97V ≤ V

IN

OUT

BGA Package

40V, Dual 1.4A Step-Down Silent Switcher µModule

Regulator

3V ≤ V ≤ 40V, 0.8V ≤ V

≤ 10V, 6.25mm × 6.25mm × 2.32mm

≤ 8V, 9mm × 11.25mm × 3.32mm

IN

OUT

BGA Package

40V, Dual 3.5A Step-Down Silent Switcher µModule Regulator 3V ≤ V ≤ 40V, 0.8V ≤ V

IN

OUT

BGA Package

60V, 3A Step-Down µModule Regulator

3.4V ≤ V ≤ 60V, 0.85V ≤ V

≤ 15V, 6.25mm × 9mm × 3.32mm

≤ 15V, 9mm × 11.25mm × 3.32mm

IN

OUT

BGA Package

60V, 5A Step-Down Silent Switcher µModule Regulator

3.6V ≤ V ≤ 60V, 0.97V ≤ V

IN

OUT

BGA Package

40V, Quad 1.2A Step-Down Silent Switcher µModule Regulator 3V ≤ V ≤ 40V, 0.8V ≤ V

≤ 8V, 6.25mm × 11.25mm × 2.32mm

IN

OUT

BGA Package

Quad 3A, 20V Step-Down µModule Regulator

Quad 4A, 14V Step-Down µModule Regulator

4V ≤ V ≤ 20V, 0.6V ≤ V

IN

≤ 3.3V, 9mm × 15mm × 1.82mm

OUT

LGA, 9mm × 15mm × 2.42mm BGA Packages

4V ≤ V ≤ 14V, 0.6V ≤ V ≤ 5.5V, 9mm × 15mm × 5.01mm BGA Package

IN

OUT

Rev. 0

04/21

www.analog.com

28

 ANALOG DEVICES, INC. 2021

For more information www.analog.com


型号：	LTM8060IY
厂家：	ADI
描述：	Quad 40VIN, Silent Switcher Î¼Module Regulator with Configurable 3A Output Array
文件：	总28页 (文件大小：2696K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM8060IY [ADI]

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