LTM8071 [ADI]
Quad 40VIN Silent Switcher μModule Regulator with Configurable 1.2A Output Array;型号: | LTM8071 |
厂家: | ADI |
描述: | Quad 40VIN Silent Switcher μModule Regulator with Configurable 1.2A Output Array |
文件: | 总28页 (文件大小:2571K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM8051
Quad 40V Silent Switcher μModule Regulator
IN
with Configurable 1.2A Output Array
FEATURES
DESCRIPTION
The LTM®8051 is quad 40VIN, 1.2A step-down Silent
Switcher μModule® regulator. The Silent Switcher archi-
tecture minimizes EMI while delivering high efficiency at
frequencies up to 3MHz. Included in the package are the
controllers, power switches, inductors, and support com-
ponents. Operating over a wide input voltage range, the
LTM8051 supports output voltages from 0.8V to 8V, and
a switching frequency range of 300kHz to 3MHz, each set
by a single resistor. Only the bulk input and output filter
capacitors are needed to finish the design. The LTM8051
product video is available on website.
n
Four Complete Step-Down Switching Power Supplies
Low Noise Silent Switcher® Architecture
CISPR22 Class B Compliant
n
n
n
n
n
n
CISPR25 Class 5 Compliant
Wide Input Voltage Range: 3V to 40V
Wide Output Voltage Range: 0.8V to 8V
1.2A Continuous Output Current per Channel at
12V , 3.3V , T = 85°C
IN
OUT
A
n
n
1.5A Continuous Output Current per Channel at
12V , 3.3V , T = 60°C
IN
OUT
A
Multiphase or Multi-µModule Parallelable for
The LTM8051 is packaged in a compact (6.25mm ×
11.25mm × 2.22mm) over-molded Ball Grid Array (BGA)
package suitable for automated assembly by standard
surface mount equipment. The LTM8051 is available with
SnPb (BGA) or RoHS compliant.
Increased Output Current
n
n
Selectable Switching Frequency: 300kHz to 3MHz
Compact Package (6.25mm × 11.25mm × 2.22mm)
Surface Mount BGA
Configurable Output Array
APPLICATIONS
The LTM8051 outputs can be paralleled in an array for up
to 4.8A capability.
n
Automated Test Equipment
n
Distributed Supply Regulation
1.2A
n
Industrial Supplies
Medical Equipment
2.4A
1.2A
1.2A
1.2A
3.6A
1.2A
n
4.8A
1.2A
1.2A
All registered trademarks and trademarks are the property of their respective owners.
Click to view associated Video Design Idea.
TYPICAL APPLICATION
1.8-5VOUT from 7-40VIN Quad Step-Down Converter
Efficiency, VIN = 24V, BIAS = 5V
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1
Document Feedback
For more information www.analog.com
LTM8051
ABSOLUTE MAXIMUM RATINGS
(Note 1)
SYNCn .......................................................................6V
Maximum Internal Temperature (Note 2).............. 125°C
Storage Temperature ............................. –55°C to 125°C
Peak Solder Reflow Package Body Temperature ..260°C
V
V
, RUNn, PGn ......................................................42V
OUTn
INn
, BIASn ...........................................................10V
FBn, TRSSn, SHAREn , RT , VCC .............................4V
n
n
PIN CONFIGURATION
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ORDER INFORMATION
PART MARKING*
PACKAGE
MSL
TEMPERATURE RANGE
(SEE NOTE 2)
PART NUMBER
LTM8051EY#PBF
LTM8051IY#PBF
LTM8051IY
PAD OR BALL FINISH
SAC305 (RoHS)
SnPb (63/37)
DEVICE
FINISH CODE
TYPE
RATING
e1
LTM8051Y
BGA
3
–40°C to 125°C
e0
• Device temperature grade is indicated by a label on the shipping container. • This product is not recommended for second side reflow.
This product is moisture sensitive. For more information, go to
Recommended BGA PCB Assembly and Manufacturing Procedures.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• BGA Package and Tray Drawings
Rev. 0
2
For more information www.analog.com
LTM8051
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
internal temperature range, otherwise specifications are at TA = 25°C. VIN1n = 12V, RUNn = 2V unless otherwise noted (Note 2).
PARAMETER
Minimum V Input Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
3.0
3.0
2.0
V
V
V
IN1
Minimum V
Input Voltage
IN23
Minimum V Input Voltage
V
IN1
= 3V
IN4
Output DC Voltage
FBn open
FBn = 27.4kΩ
0.8
8
V
V
Maximum Output DC Current
(Note 3)
2.5
4
A
Quiescent Current into V
RUNn = 0
BIASn = 5V, SYNCn = 0V, No load
BIASn = 5V, SYNCn = 3.3V, No load
2
60
10
μA
µA
mA
INn
Current into BIAS
RUNn = 0, BIASn = 5V
BIASn = 5V, SYNCn = 3.3V, No load
1
μA
mA
n
7
Line Regulation
Load Regulation
Output RMS Ripple
FBn Voltage
5V < V < 40V
0.1
0.2
10
%
%
INn
12V , 0.1A < I
<2A
INn
OUTn
3.3V
mV
OUTn
792
784
800
800
808
816
mV
mV
l
Current out of FBn
V n = 1V, FBn = 0V
OUT
4
μA
V
Minimum BIASn for Proper Operation
3.2
Switching Frequency
RTn = 113KΩ
RTn = 30.9KΩ
RTn = 7.15KΩ
300
1
3
KHz
MHz
MHz
RUNn Threshold
0.74
V
RUNn Input Current
PGn Threshold at FBn
RUNn = 0V
1
μA
FBn Rising
FBn Falling
740
860
mV
mV
PGn Output Sink Current
PGn = 0.1V
100
μA
V
CLKOUTn V
CLKOUTn V
0
OL
OH
3.3
V
SYNCn Input High Threshold
SYNCn Input Low Threshold
SYNCn Threshold to Enable Spread Spectrum
SYNCn Current
1.5
2.8
V
0.8
4
V
V
SYNCn = 6V
65
2
μA
μA
Ω
TRSSn Source Current
TRSSn = 0V
TRSSn Pull-Down Resistance
Fault Condition, TRSSn = 0.1V
230
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM8051E is guaranteed to meet performance specifications
from 0°C to 125°C internal. Specifications over the full –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls.
The LTM8051I is guaranteed to meet specifications over the full –40°C
to 125°C internal operating temperature range. Note that the maximum
internal temperature is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 3: The maximum current out of either channel may be limited by the
internal temperature of the LTM8051. See output current derating curves
for different V , V , and T .
IN OUT
A
Rev. 0
3
For more information www.analog.com
LTM8051
TA = 25°C, operating per Table 1,unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency, VOUT = 0.8V
BIAS = 5V
Efficiency, VOUT = 1.0V
BIAS = 5V, Burst Mode
Efficiency, VOUT = 1.2V
BIAS = 5V, Burst Mode
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Efficiency, VOUT = 1.5V
BIAS = 5V, Burst Mode
Efficiency, VOUT = 1.8V
BIAS = 5V, Burst Mode
Efficiency, VOUT = 2.0V
BIAS = 5V, Burst Mode
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Efficiency, VOUT = 2.5V
BIAS = 5V, Burst Mode
Efficiency, VOUT = 3.3V
BIAS = 5V, Burst Mode
Efficiency, VOUT = 3.3V, 2MHz
BIAS = 5V, Burst Mode
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Rev. 0
4
For more information www.analog.com
LTM8051
TA = 25°C, operating per Table 1,unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency, VOUT = 5.0V
BIAS = 5V, Burst Mode
Efficiency, VOUT = 5.0V, 2MHz
BIAS = 5V, Burst Mode
Efficiency, VOUT = 8.0V
BIAS = 5V, Burst Mode
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ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀ0ꢁꢂ ꢃꢂ0
ꢀ0ꢁꢂ ꢃꢂꢂ
ꢀ0ꢁꢂ ꢃꢂꢄ
Input vs Load Current
OUT = 0.8V, BIAS = 5V, Burst Mode
Input vs Load Current
VOUT = 1.0V, BIAS = 5V, Burst Mode
Input vs Load Current
VOUT = 1.2V, BIAS = 5V, Burst Mode
V
0.ꢀ
0.ꢀ
0.ꢀ
0
0.ꢀ
0.ꢀ
0.ꢀ
0
0.ꢀ
0.ꢀ
0.ꢀ
0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀ0ꢁꢂ ꢃꢂꢄ
ꢀ0ꢁꢂ ꢃꢂꢄ
ꢀ0ꢁꢂ ꢃꢂꢁ
Input vs Load Current
VOUT = 1.5V, BIAS = 5V, Burst Mode
Input vs Load Current
VOUT = 1.8V, BIAS = 5V, Burst Mode
Input vs Load Current
VOUT = 2.0V, BIAS = 5V, Burst Mode
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
0
0.ꢀ
0.ꢀ
0.ꢀ
0
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀ0ꢁꢂ ꢃꢂꢄ
ꢀ0ꢁꢂ ꢃꢂꢀ
ꢀ0ꢁꢂ ꢃꢂꢄ
Rev. 0
5
For more information www.analog.com
LTM8051
TA = 25°C, operating per Table 1,unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Input vs Load Current
VOUT = 2.5V, BIAS = 5V, Burst
Mode
Input vs Load Current
VOUT = 3.3V, 2MHz, BIAS = 5V,
Burst Mode
Input vs Load Current
VOUT = 3.3V, BIAS = 5V, Burst
Mode
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
0
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0.ꢀ
0.ꢀ
0.ꢀ
0
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀ0ꢁꢂ ꢃꢄ0
ꢀ0ꢁꢂ ꢃꢄꢂ
ꢀ0ꢁꢂ ꢃꢂꢄ
Input vs Load Current
VOUT = 5V, 2MHz, BIAS = 5V,
Burst Mode
Input vs Load Current
VOUT = 5V, BIAS = 5V, Burst Mode
Input vs Load Current
VOUT = 8V, BIAS = 5V, Burst Mode
ꢀ.ꢁ
0.ꢀ
0.ꢀ
0.ꢀ
0
ꢀ.ꢁ
ꢀ.ꢁ
0.ꢀ
0.ꢀ
0
ꢀ.ꢁ
0.ꢀ
0.ꢀ
0.ꢀ
0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
0
0.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀ0ꢁꢂ ꢃꢄꢄ
ꢀ0ꢁꢂ ꢃꢄꢅ
ꢀ0ꢁꢂ ꢃꢄꢅ
Derating, VOUT = 1V
Derating, VOUT = 1.2V
Derating, VOUT = 0.8V
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
All Channels At Same Load
All Channels At Same Load
All Channels At Same Load
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
0 ꢀꢁꢂ
0 ꢀꢁꢂ
0 ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀ0ꢁꢂ ꢃꢄꢁ
ꢀ0ꢁꢂ ꢃꢄꢅ
ꢀ0ꢁꢂ ꢃꢄꢅ
Rev. 0
6
For more information www.analog.com
LTM8051
TA = 25°C, operating per Table 1,unless otherwise noted.
Derating, VOUT = 2V
TYPICAL PERFORMANCE CHARACTERISTICS
Derating, VOUT = 1.5V
Derating, VOUT = 1.8V
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
All Channels At Same Load
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
All Channels At Same Load
All Channels At Same Load
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
0 ꢀꢁꢂ
0 ꢀꢁꢂ
0 ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀ0ꢁꢂ ꢃꢄꢅ
ꢀ0ꢁꢂ ꢃꢄ0
ꢀ0ꢁꢂ ꢃꢄꢀ
Derating, VOUT = 2.5V
Derating, VOUT = 3.3V
Derating, VOUT = 3.3V, FSW = 2MHz
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
All Channels At Same Load
All Channels At Same Load
All Channels At Same Load
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
0 ꢀꢁꢂ
0 ꢀꢁꢂ
0 ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀ0ꢁꢂ ꢃꢄꢂ
ꢀ0ꢁꢂ ꢃꢄꢅ
ꢀ0ꢁꢂ ꢃꢄꢄ
Derating, VOUT = 5V
Derating, VOUT = 5V, FSW = 2MHz
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
Derating, VOUT = 8V
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
All Channels At Same Load
All Channels At Same Load
All Channels At Same Load
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
0 ꢀꢁꢂ
0 ꢀꢁꢂ
0 ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀ0ꢁꢂ ꢃꢄꢅ
ꢀ0ꢁꢂ ꢃꢄꢁ
ꢀ0ꢁꢂ ꢃꢄꢅ
Rev. 0
7
For more information www.analog.com
LTM8051
TA = 25°C, operating per Table 1,unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Derating with Airflow,
Derating with Airflow,
Derating with Airflow,
12VIN to 1.5VOUT, TJ =120°C
BIAS = 5V, DC2860A Demo Board
Forced Continuous Mode
All Channels At Same Load
24VIN to 1.5VOUT, TJ =120°C
36VIN to 1.5VOUT, TJ =120°C
BIAS = 5V, DC2860A Demo Board
Forced Continuous Mode
BIAS = 5V, DC2860A Demo Board
Forced Continuous Mode
All Channels At Same Load
All Channels At Same Load
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀ0ꢁꢂ ꢃꢄꢅ
ꢀ0ꢁꢂ ꢃꢄꢀ
ꢀ0ꢁꢂ ꢃꢄꢅ
Derating with Airflow,
Derating with Airflow,
Derating with Airflow,
12VIN to 3.3VOUT, TJ =120°C
24VIN to 3.3VOUT, TJ =120°C
36VIN to 3.3VOUT, TJ =120°C
BIAS = 5V, DC2860A Demo Board
Forced Continuous Mode
All Channels At Same Load
BIAS = 5V, DC2860A Demo Board
Forced Continuous Mode
All Channels At Same Load
BIAS = 5V, DC2860A Demo Board
Forced Continuous Mode
All Channels At Same Load
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉ ꢀꢁ
ꢀ0ꢁꢂ ꢃꢄ0
ꢀ0ꢁꢂ ꢃꢄꢅ
ꢀ0ꢁꢂ ꢃꢄꢂ
Rev. 0
8
For more information www.analog.com
LTM8051
TA = 25°C, operating per Table 1,unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Derating with Airflow,
Derating with Airflow,
Derating with Airflow,
12VIN to 5VOUT, TJ =120°C
BIAS = 5V, DC2860A Demo Board
Forced Continuous Mode
All Channels At Same Load
24VIN to 5VOUT, TJ =120°C
36VIN to 5VOUT, TJ =120°C
BIAS = 5V, DC2860A Demo Board
Forced Continuous Mode
BIAS = 5V, DC2860A Demo Board
Forced Continuous Mode
All Channels At Same Load
All Channels At Same Load
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
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Single Channel Derating, VOUT = 1.5V
CH1 ON, CH2/CH3/CH4 OFF
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
Single Channel Derating, VOUT = 5V
CH1 ON, CH2/CH3/CH4 OFF
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
Single Channel Derating, VOUT = 3.3V
CH1 ON, CH2/CH3/CH4 OFF
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
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Rev. 0
9
For more information www.analog.com
LTM8051
TA = 25°C, operating per Table 1,unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Dual Channel Derating, VOUT = 1.5V
CH1/CH2 ON, CH3/CH4 OFF
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
Dual Channel Derating, VOUT = 3.3V
Dual Channel Derating, VOUT = 5V
CH1/CH2 ON, CH3/CH4 OFF
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
CH1/CH2 ON, CH3/CH4 OFF
BIAS = 5V, DC2860A Demo Board
TJ = 120°C, Burst Mode
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BIAS Current vs Frequency
12VIN to 3.3 VOUT
Forced Continuous Mode
Input Current vs VIN
VOUT Short Circuited
Dropout Voltage vs Load Current
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Rev. 0
10
For more information www.analog.com
LTM8051
TA = 25°C, operating per Table 1,unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Output Noise Spectrum
Output Noise Spectrum
DC2860A, 100MHz Span
DC2860A, 100kHz Span
VIN = 12V, VOUT = 3.3V
IOUT = 1.2A, fSW = 1.2MHz
Output Voltage Ripple
DC2860A Demo Board
VIN = 12V, VOUT = 3.3V
V
IN = 12V, VOUT = 3.3V
IOUT = 1.2A, fSW = 1.2MHz
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CISPR25 Radiated Emission
with Class 5 Peak Limit
DC2860A Demo Board,
VIN = 14V, VOUT = 3.3V
Four Channels Paralleled,
IOUT = 4.8A, fSW = 2 MHz
CISPR22 Class B Emissions
DC2860A Demo Board
Output Noise Spectrum
DC2860A, 500MHz Span
VIN = 12V, VOUT = 3.3V
IOUT = 1.2A, fSW = 1.2MHz
VINn = 12V, IOUTn = 1.2A
5VOUT1, 3.3VOUT2, 2.5VOUT3, 1.8VOUT4
Spread Spectrum On, No EMI Filter
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0
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ꢀꢁꢂꢃe ꢄꢅꢁꢁꢆ
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0
0
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0
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0
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Rev. 0
11
For more information www.analog.com
LTM8051
PIN FUNCTIONS
VIN1 (Pin E7): Input power for the channel 1 regulator.
the CLKOUT pin will be internally grounded. Float this pin
if the CLKOUT function is not used. Do not drive this pin.
The V powers the internal control circuitry for channel
IN1
1/4 and is monitored by undervoltage lockout circuitry.
The VIN1 voltage must be greater than 3.0V for either
FB1/2/3/4 (Pin L2/D2/D1/L1): The LTM8051 regulates the
FBn pins to 800mV. Connect the feedback resistor to this
pin to set the output voltage.
channel1/4 of the LTM8051 to operate. Decouple V to
IN1
ground with an external, low ESR capacitor. See Table 1
for recommended values.
PG1/2/3/4 (Pin L6/K6/K7/L7): The PGn pin is the open-
drain output of an internal comparator. PGn remains low
until the FBn pin is within 7.5% of the final regulation
voltage, and there are no fault conditions. PGn is pulled
VIN4 (Pin F7): Input power for the channel 4 regulator.
Decouple VIN4 to ground with an external, low ESR capaci-
tor. See Table 1 for recommended values.
low during V UVLO, Thermal Shutdown, or when the
INn
V
(Bank 5): Input power for the channel 2/3 regula-
RUNn pin is low.
IN23
tor. The V
bank powers the internal control circuitry
IN23
RT14/23 (Pin K1/J1): Connect a resistor between RTn
and ground to set the switching frequency. Do not drive
this pin.
for both channel 2/3 and is monitored by undervoltage
lockout circuitry. The V voltage must be greater than
IN23
3.0V for either channel2/3 of the LTM8051 to operate.
Decouple VIN23 to ground with an external, low ESR
capacitor. See Table 1 for recommended values.
RUN14/23 (Pin D7/C7): The corresponding channel of
the LTM8051 is shutdown when this pin is low and active
when this pin is high. Tie to V if shutdown feature is
INn
VOUT1/2/3/4 (Bank 1/2/3/4): Power Output for channel
1/2/3/4, respectively. Apply the output filter capacitor and
the output load between these pins and GND pins.
not used. An external resistor divider from V can be
INn
used to program a V threshold below which the cor-
INn
responding channel of the LTM8051 will shut down. Do
GND (Bank 6): Tie these GND pins to a local ground plane
below the LTM8051 and the circuit components. In most
applications, the bulk of the heat flow out of the LTM8051
is through these pads, so the printed circuit design has a
large impact on the thermal performance of the part. See
the PCB Layout and Thermal Considerations sections for
more details. Return the feedback divider (RFB) to this net.
not float this pin.
SHARE14/23 (Pin N5/A3): Sharing Control. Float
SHARE14 when VOUT1 and VOUT4 are load sharing.
Connect SHARE14 to V
pendent. Float SHARE23 when V
sharing. Connect SHARE23 to V
if V
and V
are inde-
CC14
OUT1
OUT4
and V
are load
OUT3
OUT2
CC23
if V
and V
OUT2
OUT3
are independent. Connect SHARE14 and SHARE23 if par-
allel all four channels. Connect this pin to the SHAREn
pin of another LTM8051 when load sharing with another
LTM8051.
BIAS14/23 (Pin N3/A5): The internal regulator will draw
current from BIASn instead of V or V
when BIASn
IN1
IN23
is tied to a voltage higher than 3.2V. For output voltages
of 3.3V and above this pin should be tied to V . If this
OUTn
V
(Pin N4/A4): Internal Regulator Bypass Pin. The
CC14/23
pin is tied to a supply other than VOUTn use a local bypass
internal power drivers and control circuits are powered
capacitor on this pin.
from this voltage. VCCn current will be supplied from
CLKOUT14/23 (Pin D6/C6): Synchronization output.
When SYNC14/23>2.8V, the CLKOUT14/23 pin provides
a waveform about 90 degrees out-of-phase with Channel
1/2 respectively. This allows synchronization with other
regulators with up to four phases. When an external clock
is applied to the SYNC pin, the CLKOUT pin will output a
waveform with about the same phase, duty cycle, and fre-
quency as the SYNC waveform. In Burst Mode operation,
BIASn if V
> 3.2V, otherwise current will be drawn
BIASn
from VINn. If VOUT1 and VOUT4 are load sharing, leave
V
V
floating. If V
and V
are load sharing, leave
are independent volt-
CC14
CC23
OUT2
OUT3
floating. If V
and V
OUT1
ages, connect SHARE14 to VCC14
OUT4 ; if VOUT2 and VOUT3
are independent voltages, connect SHARE23 to V
,
CC23
otherwise the LTM8051 will not regulate properly. Do not
load the V with external circuitry.
CCn
Rev. 0
12
For more information www.analog.com
LTM8051
PIN FUNCTIONS
TRSS1/2/3/4 (Pin J2/C2/C1/K2): Output Tracking and
Soft-Start Pin. This pin allows user control of output volt-
age ramp rate during startup. A TRSSn voltage below
0.8V forces the LTM8051 to regulate the FBn pin to equal
the TRSSn pin voltage. When TRSSn is above 0.8V, the
tracking function is disabled and the internal reference
resumes control of the error amplifier. An internal 2μA
pull-up current on this pin allows a capacitor to program
output voltage slew rate. This pin is pulled to ground dur-
ing shutdown and fault conditions; use a series resistor if
driving from a low impedance output. This pin may be left
floating if the soft-start feature is not being used.
SYNC14/23 (Pin F6/E6): External clock synchronization
input. Ground this pin for low ripple Burst Mode opera-
tion at low output loads; this will also disable the CLKOUT
function. Apply a DC voltage between 2.8V and 4.2V for
forced continuous mode operation with spread spectrum
modulation. Float the SYNCn pin for forced continuous
mode operation without spread spectrum modulation.
Apply a clock source to the SYNCn pin for synchronization
to an external frequency. The LTM8051 will be in forced
continuous mode when an external frequency is applied.
BLOCK DIAGRAM
V
IN1
HOUSEKEEPING
10nF
CIRCUITRY
2.2μH
2.2μH
2.2μH
V
RUN14
TRSS1
OUT1
CURRENT MODE
CONTROLLER
10pF
3.3nF
249k
FB1
V
IN4
0.1μF
V
OUT4
CURRENT MODE
CONTROLLER
TRSS4
10pF
3.3nF
249k
FB4
V
IN23
HOUSEKEEPING
CIRCUITRY
10nF
V
V
OUT2
RUN23
TRSS2
CURRENT MODE
CONTROLLER
10pF
3.3nF
249k
FB2
2.2μH
OUT3
CURRENT MODE
CONTROLLER
TRSS3
3.3nF
10pF
249k
FB3
8051 BD
Rev. 0
13
For more information www.analog.com
LTM8051
OPERATION
The LTM8051 is a quad standalone non-isolated step-
down switching DC/DC power supply that can deliver a
peak current of up to 2.5A per channel. The continuous
current is determined by the internal operating tempera-
ture. It provides a precisely regulated output voltage pro-
grammable via one external resistor from 0.8V to 8V. The
To enhance efficiency, the LTM8051 automatically
switches to Burst Mode operation in light or no load
situations. Between bursts, all circuitry associated with
controlling the output switch is shut down reducing the
input supply current to just a few µA.
The TRSSn node acts as an auxiliary input to the error
amplifier. The voltage at FBn servos to the TRSSn voltage
until TRSSn goes above 0.8V. Soft-start is implemented
by generating a voltage ramp at the TRSSn pin using an
external capacitor which is charged by an internal 2μA
constant current. Alternatively, driving the TRSSn pin with
a signal source or resistive network provides a tracking
function. Do not drive the TRSSn pin with a low imped-
ance voltage source. See the Applications Information
section for more details.
input voltage range for V , V
input voltage range for V is 2V to 40V.
is 3V to 40V, while the
IN1 IN23
IN4
Given that the LTM8051 is a step-down converter, make
sure that the input voltage is high enough to support the
desired output voltage and load current. See simplified
Block Diagram.
The LTM8051 contains current mode controllers, power
switching elements, power inductors and a modest
amount of input and output capacitance. The LTM8051 is
a fixed frequency PWM regulator. The switching frequency
is set by simply connecting the appropriate resistor value
from the RTn pin to GND.
The LTM8051 contains power good comparators which
trip when the FBn pin is at about 92% to 108% of its regu-
lated value. The PGn output is an open-drain transistor
that is off when the output is in regulation, allowing an
external resistor to pull the PGn pin high.
Internal regulators provide power to the control circuit-
ries. Bias regulators normally draw power from the V
INn
pin, but if the BIASn pin is connected to an external volt-
age higher than 3.2V, bias power is drawn from the exter-
nal source (typically the regulated output voltage). This
improves efficiency. Tie BIASn to GND if it is not used.
The LTM8051 is equipped with a thermal shutdown that
inhibits power switching at high junction temperatures.
The activation threshold of this function is above the max-
imum temperature rating to avoid interfering with normal
operation, so prolonged or repetitive operation under a
condition in which the thermal shutdown activates may
damage or impair the reliability of the device.
Rev. 0
14
For more information www.analog.com
LTM8051
APPLICATIONS INFORMATION
Set Output Voltage
For most applications, the design process is straight-
forward, summarized as follows:
The output voltage is programmed with a FB resistor as
shown in the Figure below. Choose the resistor value
according to:
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
249kΩ
2. Apply the recommended CIN, COUT, RFB and RT values.
3. Connect BIAS as indicated.
RFB =
V
OUT −1
0.8V
When using the LTM8051 with different output voltages,
the higher frequency recommended by Table 1 will usu-
ally result in the best operation. While these component
combinations have been tested for proper operation, it is
incumbent upon the user to verify proper operation over
the intended system’s line, load and environmental condi-
tions. Bear in mind that the maximum output current is
limited by junction temperature, the relationship between
the input and output voltage magnitude and other fac-
tors. Please refer to the graphs in the Typical Performance
Characteristics section for guidance.
1% resistor is recommended to maintain output voltage
accuracy.
ꢀꢁRRꢂꢃꢄ ꢅꢆꢇꢂ
ꢀꢁꢂꢃRꢁꢄꢄꢅR
ꢀ
ꢀ.ꢀꢁꢂ
ꢀꢁꢂ
0.ꢀꢁ
ꢀ
ꢁ
ꢀ.ꢀꢁꢂ
ꢀ0ꢁꢂ
ꢀꢁ
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R
ꢀꢁ
The maximum frequency (and attendant RT value) at
which the LTM8051 should be allowed to switch is given
ꢂ0ꢃꢄ ꢅ0ꢄ
in Table 1 in the Maximum f column, while the recom-
Figure 1. Set Output Voltage with a FB Resistor
SW
mended frequency (and R value) for optimal efficiency
T
over the given input condition is given in the f column.
SW
There are additional conditions that must be satisfied if
the synchronization function is used. Please refer to the
Synchronization section for details.
Rev. 0
15
For more information www.analog.com
LTM8051
APPLICATIONS INFORMATION
Capacitor Selection Considerations
Ceramic capacitors are also piezoelectric. In Burst Mode
operation, the LTM8051’s switching frequency depends
on the load current, and can excite a ceramic capacitor
at audio frequencies, generating audible noise. Since the
LTM8051 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet to a
casual ear.
The C and C
capacitor values in Table 1 are the mini-
OUT
mumIrNecommended values for the associated operating
conditions. Applying capacitor values below those indi-
cated in Table 1 is not recommended and may result in
undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response,
if it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
If this audible noise is unacceptable, use a high perfor-
mance electrolytic capacitor at the output. It may also be
a parallel combination of a ceramic capacitor and a low
cost electrolytic capacitor.
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable. X5R
and X7R types are stable over temperature and applied
voltage and give dependable service. Other types, includ-
ing Y5V and Z5U have very large temperature and voltage
coefficients of capacitance. In an application circuit they
may have only a small fraction of their nominal capaci-
tance resulting in much higher output voltage ripple
than expected.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8051. A
ceramic input capacitor combined with trace or cable
inductance forms a high-Q (underdamped) tank circuit.
If the LTM8051 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possi-
bly exceeding the device’s rating. This situation is easily
avoided; see the Hot-Plugging Safely section.
Table 1. Recommended Component Values and Configuration (TA = 25°C)
V
R
f
MAX f
MIN
RT
OUT
FB
(kΩ)
SW
SW
2
V
(V)
0.8
1
C
C
BIAS
C
(kHz)
R (kΩ)
(kHz)
1200
1400
1400
1400
1800
1800
2000
2800
3000
3000
(kΩ)
24.9
21
IN
IN
OUT
FF
T
1
1
1
1
3V to 40V
3V to 40V
3V to 40V
3V to 40V
Open 1µF 50V X5R 0805 2 x 100uF 4V X5R 0805
3.2V to 10V
3.2V to 10V
3.2V to 10V
3.2V to 10V
3.2V to 10V
3.2V to 10V
3.2V to 10V
3.2V to 10V
3.2V to 10V
3.2V to 10V
47pF
450
75
1000
499
287
200
165
118
78.7
47.5
27.4
1µF 50V X5R 0805 2 x 100uF 4V X5R 0805
1µF 50V X5R 0805 2 x 100uF 4V X5R 0805
1µF 50V X5R 0805 2 x 100uF 4V X5R 0805
33pF
550
60.4
49.9
40.2
40.2
34.8
27.4
24.9
22.1
16.5
1.2
1.5
1.8
2
22pF
650
21
22pF
800
21
1
3.2V to 40V
3.5V to 40V
4.2V to 40V
1µF 50V X5R 0805
1µF 50V X5R 0805
1µF 50V X5R 0805
1µF 50V X5R 0805
1µF 50V X5R 0805
1µF 50V X5R 0805
100uF 4V X5R 0805
100uF 4V X5R 0805
100uF 4V X5R 0805
100uF 4V X5R 0805
47uF 6.3V X5R 0805
22uF 10V X5R 0805
-
-
-
-
-
-
800
15
1
1
900
15
2.5
3.3
5
1100
1200
1300
1700
13.3
8.06
7.15
7.15
1
1
5V to 40V
7V to 40V
1
10.5V to 40V
8
Note 1: The LTM8051 may be capable of the operating at lower input voltages but may skip switching cycles.
Note 2: A bulk input capacitor is required.
Rev. 0
16
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LTM8051
APPLICATIONS INFORMATION
Frequency Selection
excessive heat or even damage the LTM8051 if the output
is overloaded or short-circuited. A frequency that is too
low can result in a final design that has too much output
ripple or too large of an output capacitor.
The LTM8051 uses a constant frequency PWM architec-
ture that can be programmed to switch from 300kHz to
3MHz by using a resistor tied from the RT pin to ground.
Table 2 provides a list of R resistor values and their resul-
T
BIASn Pin Considerations
tant frequencies. The resistors in the table are standard
The BIASn pin is used to provide drive power for the
internal power switching stage and operate other internal
circuitry. For proper operation, it must be powered by at
least 3.2V. If the output voltage is programmed to 3.2V
1% E96 values.
Operating Frequency Trade-Offs
It is recommended that the user apply the optimal RT value
given in Table 1 for the input and output operating condi-
tion. When using the LTM8051 with different output volt-
ages, the higher frequency recommended by Table 1 will
usually result in the best operation. System level or other
considerations, however, may necessitate another operat-
ing frequency. While the LTM8051 is flexible enough to
accommodate a wide range of operating frequencies, a
haphazardly chosen one may result in undesirable opera-
tion under certain operating or fault conditions. A fre-
quency that is too high can reduce efficiency, generate
or higher, BIASn may be simply tied to V
. If V
is less than 3.2V, BIASn can be tied to OVUINTnn or sOoUmTen
other voltage source. If the BIASn pin voltage is too high,
the efficiency of the LTM8051 may suffer. The optimum
BIASn voltage is dependent upon many factors, such as
load current, input voltage, output voltage and switching
frequency. In all cases, ensure that the maximum volt-
age at the BIASn pin is less than 10V. If BIASn power is
applied from a remote or noisy voltage source, it may be
necessary to apply a decoupling capacitor locally to the
pin. A 1µF ceramic capacitor works well. The BIASn pin
may also be tied to GND at the cost of a small degradation
in efficiency.
Table 2. Switching Frequency vs RT Value
f
SW
(MHz)
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
R (kΩ)
T
113
86.6
68.1
54.9
46.4
40.2
34.8
30.9
24.9
21.0
17.8
15.0
13.3
11.5
10.2
9.09
8.06
7.15
Maximum Load
The maximum practical continuous load that the
LTM8051 can drive per channel, while rated at 1.2A,
actually depends upon both the internal current limit
and the internal temperature. The internal current limit is
designed to prevent damage to the LTM8051 in the case
of overload or short-circuit. The internal temperature of
the LTM8051 depends upon operating conditions such
as the ambient temperature, the power delivered, and
the heat sinking capability of the system. For example,
if V
of LTM8051 is configured to regulate at 1V, and
OUT1
the other 3 channels are turned off, V
may continu-
OUT1
ously deliver 3A from 24V if the ambient temperature
IN
is controlled to less than 60°C. This is quite a bit higher
than the 1.2A continuous rating. Please see graphs in the
Typical Performance Characteristics section. Similarly,
if all 4 channels of the LTM8051 are delivering 8V
OUT
and the ambient temperature is 100°C, each channel will
deliver at most 0.6A from 24V , which is less than the
IN
1.2A continuous rating.
Rev. 0
17
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LTM8051
APPLICATIONS INFORMATION
Power Derating
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
The 12V , 24V and 36V power loss curves can be
IN
IN
IN
used in coordination with the load current derating curves
for calculating an approximate θ thermal resistance for
JA
the LTM8051 with airflow conditions. The power loss
curves are taken at room temperature, and are increased
with a 1.35 to 1.4 multiplicative factor at 125°C. These
factors come from the fact that the power loss of the
regulator increases about 45% from 25°C to 150°C, thus
a 45% spread over 125°C delta equates to ~0.35%/°C loss
increase. A 125°C maximum junction minus 25°C room
temperature equates to a 100°C increase. This 100°C
increase multiplied by 0.35%/°C equals a 35% power loss
increase at the 125°C junction, thus the 1.35 multiplier.
The derived thermal resistances in Tables 3 through 5
for the various conditions can be multiplied by the calcu-
lated power loss as a function of ambient temperature to
derive temperature rise above ambient, thus maximum
junction temperature. Room temperature power loss can
be derived from the power loss curves and adjusted with
the above ambient temperature multiplicative factors. The
printed circuit board is a 1.6mm thick 4-layer board with
two-ounce copper (70µm) for all the layers.
The derating curves are plotted with four V
at the
OUTn
same operating condition starting at 6A of total load cur-
rent and low ambient temperature. The derating curves
with airflow are measured at output voltages of 1.5V, 3.3V
and 5V. These are chosen to include the lower and higher
output voltage ranges for correlating the thermal resis-
tance. Thermal models are derived from several tempera-
ture measurements in a controlled temperature chamber
along with thermal FEA modeling.
Table 3. 1.5V Output
DERATING CURVE
V
IN
(V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θ
JA
(°C/W)
Graph 37-39
12, 24, 36
Graph 04
0
None
16
Graph 37-39
Graph 37-39
12, 24, 36
12, 24, 36
Graph 04
Graph 04
200
400
None
None
13.5
12.5
Table 4. 3.3V Output
DERATING CURVE
Graph 40-42
V
(V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θ
JA
(°C/W)
IN
12, 24, 36
Graph 08
0
None
16
Graph 40-42
Graph 40-42
12, 24, 36
12, 24, 36
Graph 08
Graph 08
200
400
None
None
13.5
12.5
Table 5. 5V Output
DERATING CURVE
Graph 43-45
V
(V)
POWER LOSS CURVE
AIRFLOW (LFM)
HEAT SINK
θ
JA
(°C/W)
IN
12, 24, 36
Graph 10
0
None
16
Graph 43-45
Graph 43-45
12, 24, 36
12, 24, 36
Graph 10
Graph 10
200
400
None
None
13.5
12.5
Rev. 0
18
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LTM8051
APPLICATIONS INFORMATION
Load Sharing
Minimum Input Voltage
The four LTM8051 channels may be paralleled to produce
higher currents. To do this on two or more LTM8051, tie
The LTM8051 is a step-down converter, so a minimum
amount of headroom is required to keep the output in
regulation. Keep the input above 3V to ensure proper
operation. Voltage transients or ripple valleys that cause
the input to fall below 3V may turn off the LTM8051.
the V , V
, FBn and SHAREn pins of all the paral-
INn OUTn
leled channels/modules together (see Figure 7). To ensure
that paralleled channels start up together, the TRSSn pins
may be tied together, as well. If it is inconvenient to tie
the TRSSn pins together, make sure that the same value
soft-start capacitors are used for each µModule regulator.
VIN1 must be above 3V for channel 1 and channel 4 to
operate. If VIN1 is above 3V, channel 4 will operate as long
as V is above 2V.
IN4
When load sharing among n units and using a single R
FB
V
must be above 3V for channel 2 and channel 3 to
resistor, the value of the resistor is:
IN23
operate.
199.2
n(VOUT −0.8)
RFB =
,where RFB is in kΩ
Output Voltage Tracking and Soft-Start
The LTM8051 allows the user to adjust its output voltage
ramp rate by means of the TRSSn pin. An internal 2μA
pulls up the TRSSn pin to about 2.4V. Putting an external
capacitor on TRSSn enables soft starting the output to
reduce current surges on the input supply. During the
soft-start ramp the output voltage will proportionally track
the TRSSn pin voltage. For output tracking applications,
TRSSn can be externally driven by another voltage source.
From 0V to 0.8V, the TRSSn voltage will override the
internal 0.8V reference input to the error amplifier, thus
regulating the FBn pin voltage to that of the TRSSn pin.
When TRSSn is above 0.8V, tracking is disabled and the
feedback voltage will regulate to the internal reference
voltage. The TRSSn pin may be left floating if the function
is not needed.
Examples of load sharing applications are given in Figure 6
through Figure 8.
Burst Mode Operation
To enhance efficiency at light loads, the LTM8051
automatically switches to Burst Mode operation which
keeps the output capacitor charged to the proper volt-
age while minimizing the input quiescent current. During
Burst Mode operation, the LTM8051 delivers single cycle
bursts of current to the output capacitor followed by sleep
periods where most of the internal circuitry is powered off
and energy is delivered to the load by the output capacitor.
During the sleep time, VINn and BIASn quiescent currents
are greatly reduced, so, as the load current decreases
towards a no load condition, the percentage of time that
the LTM8051 operates in sleep mode increases and the
average input current is greatly reduced, resulting in
higher light load efficiency.
An active pull-down circuit is connected to the TRSSn
pin which will discharge the external soft-start capacitor
in the case of fault conditions and restart the ramp when
the faults are cleared. Fault conditions that clear the soft-
Burst Mode operation is enabled by tying SYNC to GND.
start capacitor are the RUNn pin transitioning low, V
INn
voltage falling too low, or thermal shutdown.
Rev. 0
19
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LTM8051
APPLICATIONS INFORMATION
Pre-Biased Output
Shorted Input Protection
As discussed in the Output Voltage Tracking and Soft-Start
section, the LTM8051 regulates the output to the FBn volt-
age determined by the TRSSn pin whenever TRSSn is less
than 0.8V. If the LTM8051 output is higher than the target
output voltage, and SYNCn is not held below 0.8V, the
LTM8051 will attempt to regulate the output to the target
voltage by returning a small amount of energy back to the
input supply. If there is nothing loading the input supply,
its voltage may rise. Take care that it does not rise so high
that the input voltage exceeds the absolute maximum rat-
ing of the LTM8051. If SYNC is grounded, the LTM8051
will not return current to the input.
Care needs to be taken in systems where the output is
held high when the input to the LTM8051 is absent. This
may occur in battery charging applications or in battery
backup systems where a battery or some other supply
is diode OR’ed with the LTM8051’s output. If the V
INn
pin is allowed to float and the RUNn pin is held high
(either by a logic signal or because it is tied to VINn),
then the LTM8051’s internal circuitry pulls its quiescent
current through its internal power switch. This is fine if
your system can tolerate a few milliamps in this state.
If you ground the RUNn pin, the internal current drops
to essentially zero. However, if the V pin is grounded
INn
while the output is held high, parasitic diodes inside the
LTM8051 can pull large currents from the output through
Synchronization
the V pin. Figure 5 shows a circuit that runs only when
INn
To select low ripple Burst Mode operation, tie the SYNC
pin below about 0.8V (this can be ground or a logic low
output). To synchronize the LTM8051 oscillator to an
external frequency, connect a square wave (with about
20% to 80% duty cycle) to the SYNCn pin. The square
wave amplitude should have valleys that are below 0.8V
and peaks above 1.5V.
the input voltage is present and that protects against a
shorted or reversed input.
ꢀ
ꢀ
ꢁꢂ
ꢁꢂ
ꢀꢁꢂꢃ0ꢄꢅ
Rꢀꢁ
The LTM8051 may be synchronized over a 300kHz to
3MHz range. The LTM8051 will not enter Burst Mode
operation at light output loads while synchronized to an
ꢀ0ꢁꢂ ꢃ0ꢄ
external clock. The R resistor should be chosen to set
T
Figure 2. The Input Diode Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output. It Also Protects
the Circuit from a Reversed Input. The LTM8051 Runs Only
When the Input Is Present
the switching frequency equal to or below the lowest
synchronization input. For example, if the synchroniza-
tion signal will be 500kHz and higher, the R should be
T
selected for 500kHz or lower.
PCB Layout
The LTM8051 features spread spectrum operation to fur-
ther reduce EMI/EMC emissions. To enable spread spec-
trum operation, apply between 2.8V and 4.2V to the SYNC
pin. In this mode, triangular frequency modulation is used
to vary the switching frequency between the value pro-
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8051. The LTM8051 is neverthe-
less a switching power supply, and care must be taken to
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 3
for a suggested layout. Ensure that the grounding and
heat sinking are acceptable.
grammed by R to about 20% higher than that value. The
T
modulation frequency is about 7kHz. For example, when
the LTM8051 is programmed to 2MHz, the frequency will
vary from 2MHz to 2.4MHz at a 7kHz rate. When spread
spectrum operation is selected, Burst Mode operation is
disabled, and the part may run in discontinuous mode.
Rev. 0
20
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LTM8051
APPLICATIONS INFORMATION
A few rules to keep in mind are:
1. Place the R and R resistors as close as possible to
FB
T
COUT2
COUT4
their respective pins.
2. Place the C capacitor as close as possible to the V
IN
IN
and GND connection of the LTM8051.
3. Place the C
capacitor as close as possible to the
OUT
COUT3
COUT1
V
and GND connection of the LTM8051.
OUT
4. Place the CIN and COUT capacitors such that their
ground current flow directly adjacent to or underneath
the LTM8051.
Figure 3. Layout Showing Suggested External Components,
GND Plane and Vias
5. Connect all of the GND connections to as large a cop-
per pour or plane area as possible on the top layer.
Avoid breaking the ground connection between the
external components and the LTM8051.
of the LTM8051 can ring to more than twice the nominal
input voltage, possibly exceeding the LTM8051’s rating
and damaging the part. If the input supply is poorly con-
trolled or the LTM8051 is hot-plugged into an energized
supply, the input network should be designed to prevent
this overshoot. This can be accomplished by installing
a small resistor in series to VIN, but the most popular
method of controlling input voltage overshoot is add an
6. Use vias to connect the GND copper area to the
board’s internal ground planes. Liberally distribute
these GND vias to provide both a good ground con-
nection and thermal path to the internal planes of the
printed circuit board. Pay attention to the location and
density of the thermal vias in Figure 3. The LTM8051
can benefit from the heat sinking afforded by vias that
connect to internal GND planes at these locations,
due to their proximity to internal power handling
components. The optimum number of thermal vias
depends upon the printed circuit board design. For
example, a board might use very small via holes. It
should employ more thermal vias than a board that
uses larger holes.
electrolytic bulk cap to the V net. This capacitor’s rela-
IN
tively high equivalent series resistance damps the circuit
and eliminates the voltage overshoot. The extra capacitor
improves low frequency ripple filtering and can slightly
improve the efficiency of the circuit, though it is likely to
be the largest component in the circuit.
Thermal Considerations
The LTM8051 output current may need to be derated if
it is required to operate in a high ambient temperature.
The amount of current derating is dependent upon the
input voltage, output power and ambient temperature.
The derating curves given in the Typical Performance
Characteristics section can be used as a guide. These
curves were generated by the LTM8051 mounted to
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8051. However, these capacitors
can cause problems if the LTM8051 is plugged into a
live supply (see Application Note 88 for a complete dis-
cussion). The low loss ceramic capacitor combined with
stray inductance in series with the power source forms an
underdamped tank circuit, and the voltage at the V pin
IN
Rev. 0
21
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LTM8051
APPLICATIONS INFORMATION
a 74cm2 4-layer FR4 printed circuit board. Boards of
other sizes and layer count can exhibit different thermal
behavior, so it is incumbent upon the user to verify proper
operation over the intended system’s line, load and envi-
ronmental operating conditions.
3. θJCtop is determined with nearly all of the compo-
nent power dissipation flowing through the top of the
package. As the electrical connections of the typical
µModule regulator are on the bottom of the package,
it is rare for an application to operate such that most
of the heat flows from the junction to the top of the
part. As in the case of θJCbot, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
For increased accuracy and fidelity to the actual applica-
tion, many designers use FEA (Finite Element Analysis) or
CFD (Computational Fluid Dynamics) to predict thermal
performance. To that end, the Pin Configuration typically
gives three dominant thermal coefficients:
Given these definitions, it should now be apparent that
none of these thermal coefficients reflects an actual physi-
cal operating condition of a µModule regulator. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
1. θ – Thermal resistance from junction to ambient
JA
2. θ
– Thermal resistance from junction to the bot-
JCbot
tom of the product case
3. θ
– Thermal resistance from junction to top of
JCtop
the product case
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased below:
A graphical approximation of these dominant thermal
resistances is given in Figure 4. Some thermal resis-
tance elements, such as heat flow out the side of the
package, are not defined by the JEDEC standard, and are
not shown. The blue resistances are contained within the
µModule regulator, and the green are outside.
1. θJA is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD 51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
The die temperature of the LTM8051 must be lower than
the maximum rating, so care should be taken in the layout
of the circuit to ensure good heat sinking of the LTM8051.
The bulk of the heat flow out of the LTM8051 is through
the bottom of the package and the pads into the printed
circuit board. Consequently a poor printed circuit board
design can cause excessive heating, resulting in impaired
performance or reliability. Please refer to the PCB Layout
section for printed circuit board design suggestions.
2. θJCbot is the junction-to-board thermal resistance
with all of the component power dissipation flow-
ing through the bottom of the package. In the typical
µModule regulator, the bulk of the heat flows out the
bottom of the package, but there is always heat flow
out into the ambient environment. As a result, this
thermal resistance value may be useful for compar-
ing packages but the test conditions don’t generally
match the user’s application.
Rev. 0
22
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LTM8051
APPLICATIONS INFORMATION
ꢅꢆꢇꢈꢉꢊe ꢋꢌꢍꢎꢏꢌ
θ
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ꢐꢘ
θ
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ꢚꢕꢖꢛꢜ Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
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θ
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Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
ꢝꢖꢘRꢋꢗꢕꢖꢗꢘꢆꢝꢎꢌꢔꢕ
Rꢌꢙꢎꢙꢕꢘꢔꢏꢌ
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ꢀ0ꢁꢂ ꢃ0ꢄ
Figure 4. Graphical Representation of Thermal Coefficients, Including JESD51-12 Terms
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ꢀꢁ
ꢀꢁ ꢂꢃ ꢄ0ꢁ
Rꢀꢁꢂꢃ
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ꢀ ꢁ.ꢂꢃꢄꢅ
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ꢀꢁꢂꢃ
ꢀ
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Rꢀꢁꢂ
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ꢀꢁꢂꢃ
ꢀ.ꢁꢂ
ꢀꢁꢁꢂꢃ
ꢀꢁ
ꢀ00ꢁꢂ
ꢀ00ꢁ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
Rꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ.ꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
Rꢀꢁꢂ
ꢀ.ꢀꢁ
ꢀ
ꢀꢁ
ꢀ.ꢁꢂ
ꢀ00ꢁꢂ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀ00ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ0ꢁꢂ ꢃ0ꢁ
ꢀꢁꢂꢃ ꢂꢄꢅ ꢆꢃꢇꢈꢉ ꢅRꢃꢃꢊꢋ ꢅRꢃꢃꢌꢋ ꢅRꢃꢃꢍꢋ ꢅRꢃꢃꢎꢋ ꢀꢏꢊꢋ ꢀꢏꢌꢋ ꢀꢏꢍꢋ ꢀꢏꢎꢋ ꢐꢑꢒꢄꢆꢅꢊꢎꢋ ꢐꢑꢒꢄꢆꢅꢌꢍ
Figure 5. 7V to 40V Input to 5V at 1A, 1.8V at 2A, and Paralleled 3.3V at 2.5A
Rev. 0
23
For more information www.analog.com
LTM8051
TYPICAL APPLICATIONS
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ ꢂꢃ ꢄ0ꢁ
Rꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ.ꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃ
Rꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀ.ꢀꢁ
ꢀ00ꢁꢂ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀ00ꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
Rꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ.ꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃ
Rꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀ00ꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀ00ꢁꢂ
ꢀꢁꢂ
ꢀꢁ
0
0
ꢀꢁꢂꢃ ꢂꢄꢅ ꢆꢃꢇꢈꢉ ꢅRꢃꢃꢊꢋ ꢅRꢃꢃꢌꢋ ꢅRꢃꢃꢍꢋ ꢅRꢃꢃꢎꢋ ꢀꢏꢊꢋ ꢀꢏꢌꢋ ꢀꢏꢍꢋ ꢀꢏꢎꢋ ꢃꢐꢂꢑꢊꢎꢋ ꢑꢒꢓꢄꢆꢅꢌꢍꢋ ꢔꢑꢑꢊꢎꢋ ꢔꢑꢑꢌꢍ
Figure 6. 5V to 40V Input to Paralleled 3.3V at 5A, frequency is synchronized.
ꢀ
ꢀꢁꢂ
ꢀꢁ.ꢀꢂ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃ
Rꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁ
ꢀ.ꢁꢂ
ꢀ00ꢁꢂ
ꢀ00ꢁ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀ.ꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂRꢃꢄꢅ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ ꢂꢃ ꢄ0ꢁ
ꢀꢁꢂ
Rꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
Rꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ.ꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄ
Rꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁ
ꢀ.ꢀꢁ
ꢀ00ꢁꢂ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀ.ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃ
ꢀ00ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
0
0
ꢀꢁꢂꢃ ꢂꢄꢅ ꢆꢃꢇꢈꢉ ꢅRꢃꢃꢊꢋ ꢅRꢃꢃꢌꢋ ꢅRꢃꢃꢍꢋ ꢅRꢃꢃꢎꢋ ꢀꢏꢊꢋ ꢀꢏꢌꢋ ꢀꢏꢍꢋ ꢀꢏꢎꢋ ꢐꢑꢒꢄꢆꢅꢊꢎꢋ ꢐꢑꢒꢄꢆꢅꢌꢍ
Figure 7. 7V to 40V Input to Cascaded 1.8V at 1.5A and Paralleled 3.3V at 2.5A
Rev. 0
24
For more information www.analog.com
LTM8051
TYPICAL APPLICATIONS
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ ꢂꢃ ꢄ0ꢁ
Rꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
Rꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ.ꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀꢁ.ꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁ
ꢀ.ꢀꢁ
ꢀ0ꢁ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ.ꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂRꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
Rꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
Rꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁ.ꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀꢁ.ꢂꢃ
ꢀ ꢁ.ꢂꢃꢄꢅ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ00ꢁꢂ ꢃ ꢄ
ꢀ00ꢁꢂ ꢃ ꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀ0ꢁꢂ ꢃ0ꢀ
ꢀꢁꢂꢃ ꢂꢄꢅ ꢆꢃꢇꢈꢉ ꢅRꢃꢃꢊꢋ ꢅRꢃꢃꢌꢋ ꢅRꢃꢃꢍꢋ ꢅRꢃꢃꢎꢋ ꢀꢏꢊꢋ ꢀꢏꢌꢋ ꢀꢏꢍꢋ ꢀꢏꢎꢋ ꢐꢑꢑꢊꢎꢋ ꢐꢑꢑꢌꢍ
Figure 8. Two LTM8051 are Paralleled to Supply 3.3V/10A
Rev. 0
25
For more information www.analog.com
LTM8051
PACKAGE DESCRIPTION
Table 6. LTM8051 Pinout (Sorted by Pin Number)
Pin
A1
A2
A3
A4
A5
A6
A7
Pin
H1
H2
H3
H4
H5
H6
H7
Pin Name
Pin
B1
B2
B3
B4
B5
B6
B7
Pin
J1
Pin Name
Pin
C1
C2
C3
C4
C5
C6
C7
Pin
K1
K2
K3
K4
K5
K6
K7
Pin Name
TRSS3
TRSS2
GND
Pin
D1
D2
D3
D4
D5
D6
D7
Pin
L1
L2
L3
L4
L5
L6
L7
Pin Name
FB3
Pin
E1
Pin Name
GND
Pin
F1
Pin Name
GND
Pin
G1
G2
G3
G4
G5
G6
G7
Pin Name
V
V
V
OUT3
V
OUT3
V
IN23
OUT3
OUT3
FB2
E2
GND
F2
GND
GND
GND
GND
GND
GND
GND
SHARE23
GND
GND
GND
GND
E3
GND
F3
GND
V
GND
GND
E4
GND
F4
GND
CC23
BIAS23
GND
GND
E5
GND
F5
GND
V
OUT2
V
OUT2
V
CLKOUT23
RUN23
Pin Name
RT14
CLKOUT14
RUN14
Pin Name
FB4
E6
SYNC23
F6
SYNC14
OUT2
OUT2
V
E7
V
F7
V
IN4
IN1
Pin Name
Pin Name
RT23
TRSS1
GND
Pin
M1
M2
M3
M4
M5
M6
M7
Pin Name
Pin
N1
N2
N3
N4
N5
N6
N7
Pin Name
V
V
OUT1
V
OUT1
V
OUT1
V
OUT1
IN23
GND
GND
GND
GND
GND
GND
J2
TRSS4
GND
FB1
J3
GND
GND
GND
GND
BIAS14
J4
GND
GND
GND
V
CC14
J5
GND
GND
GND
SHARE14
J6
GND
PG2
PG1
V
V
OUT4
V
OUT4
OUT4
OUT4
J7
GND
PG3
PG4
V
PACKAGE PHOTO
Rev. 0
26
For more information www.analog.com
LTM8051
PACKAGE DESCRIPTION
BGA Package
91-Lead (11.25mm × 6.25mm × 2.22mm)
ꢡReꢢeꢣeꢤꢥe ꢂꢕꢊ ꢉꢙꢆꢦ 0ꢑꢧ0ꢨꢧꢍꢒ0ꢨ Rev ꢩꢪ
ꢠꢈꢈ ꢀꢖꢕꢈꢠ
ꢉꢈꢕꢌꢘꢂ ꢌ
ꢌ
ꢎꢷ
ꢞꢞꢞ ꢟ
ꢒ
ꢈ
ꢜ
ꢌꢎ
ꢝ
ꢓ
ꢒ
ꢑ
ꢐ
ꢏ
ꢎ
ꢍ
ꢠꢈꢈ ꢀꢖꢕꢈꢠ
ꢏ
ꢌ
ꢋ
ꢊ
ꢉ
ꢈ
ꢌꢍ
ꢔꢘꢀ ꢚꢌꢍꢛ
ꢊꢖRꢀꢈR
ꢥꢥꢥ
ꢟ
ꢔꢘꢀ ꢍ
ꢐ
ꢯ
ꢯꢍ
ꢁꢖꢂꢉ
ꢊꢌꢔ
ꢇ
ꢠꢮꢋꢠꢕRꢌꢕꢈ
ꢅꢍ
ꢉ
ꢆ
ꢅ
ꢄ
ꢅꢎ
ꢇ
ꢉꢈꢕꢌꢘꢂ ꢋ
ꢃ
ꢂ
ꢩꢯ ꢡꢫꢍ ꢔꢂꢌꢊꢈꢠꢪ
e
ꢰꢰꢰ
eee
ꢁ
ꢁ
ꢟ
ꢟ
ꢝ ꢜ
ꢁ
ꢀ
ꢎꢷ
ꢞꢞꢞ ꢟ
e
ꢯ
ꢆ
ꢔꢌꢊꢃꢌꢆꢈ ꢕꢖꢔ ꢗꢘꢈꢙ
ꢉꢈꢕꢌꢘꢂ ꢋ
ꢔꢌꢊꢃꢌꢆꢈ ꢠꢘꢉꢈ ꢗꢘꢈꢙ
ꢔꢌꢊꢃꢌꢆꢈ ꢋꢖꢕꢕꢖꢁ ꢗꢘꢈꢙ
ꢉꢈꢕꢌꢘꢂ ꢌ
ꢀꢖꢕꢈꢠꢬ
ꢍ. ꢉꢘꢁꢈꢀꢠꢘꢖꢀꢘꢀꢆ ꢌꢀꢉ ꢕꢖꢂꢈRꢌꢀꢊꢘꢀꢆ ꢔꢈR ꢌꢠꢁꢈ ꢜꢍꢐ.ꢑꢁꢧꢍꢫꢫꢐ
ꢐ.ꢨ00
ꢐ.000
ꢏ.ꢎ00
ꢎ.ꢐ00
ꢍ.ꢒ00
0.ꢨ00
0.000
0.ꢨ00
ꢍ.ꢒ00
ꢎ.ꢐ00
ꢏ.ꢎ00
ꢐ.000
ꢐ.ꢨ00
ꢎ. ꢌꢂꢂ ꢉꢘꢁꢈꢀꢠꢘꢖꢀꢠ ꢌRꢈ ꢘꢀ ꢁꢘꢂꢂꢘꢁꢈꢕꢈRꢠ
DIMENSIONS
ꢏ
ꢐ
ꢋꢌꢂꢂ ꢉꢈꢠꢘꢆꢀꢌꢕꢘꢖꢀ ꢔꢈR ꢄꢈꢔꢫꢑ
SYMBOL
MIN
ꢎ.0ꢏ
0.ꢏ0
ꢍ.ꢓꢏ
0.ꢐꢑ
0.ꢏꢓ
NOM
ꢎ.ꢎꢎ
0.ꢐ0
ꢍ.ꢨꢎ
0.ꢑ0
0.ꢐ0
ꢍꢍ.ꢎꢑ
ꢒ.ꢎꢑ
0.ꢨ0
ꢫ.ꢒ0
ꢐ.ꢨ0
0.ꢏꢎ
ꢍ.ꢑ0
MAX
NOTES
ꢉꢈꢕꢌꢘꢂꢠ ꢖꢇ ꢔꢘꢀ ꢦꢍ ꢘꢉꢈꢀꢕꢘꢇꢘꢈR ꢌRꢈ ꢖꢔꢕꢘꢖꢀꢌꢂꢭ
ꢋꢮꢕ ꢁꢮꢠꢕ ꢋꢈ ꢂꢖꢊꢌꢕꢈꢉ ꢙꢘꢕꢅꢘꢀ ꢕꢅꢈ ꢟꢖꢀꢈ ꢘꢀꢉꢘꢊꢌꢕꢈꢉ.
ꢕꢅꢈ ꢔꢘꢀ ꢦꢍ ꢘꢉꢈꢀꢕꢘꢇꢘꢈR ꢁꢌꢜ ꢋꢈ ꢈꢘꢕꢅꢈR ꢌ ꢁꢖꢂꢉ ꢖR
ꢁꢌRꢃꢈꢉ ꢇꢈꢌꢕꢮRꢈ
ꢌ
ꢌꢍ
ꢌꢎ
ꢯ
ꢯꢍ
ꢉ
ꢈ
e
ꢇ
ꢆ
ꢅꢍ
ꢅꢎ
ꢞꢞꢞ
ꢯꢯꢯ
ꢥꢥꢥ
ꢰꢰꢰ
eee
ꢎ.ꢐꢍ
0.ꢑ0
ꢍ.ꢫꢍ
0.ꢑꢑ
0.ꢐꢏ
ꢋꢌꢂꢂ ꢅꢕ
0.ꢐ00 0.0ꢎꢑ ꢩ ꢫꢍꢵ
ꢋꢌꢂꢂ ꢉꢘꢁꢈꢀꢠꢘꢖꢀ
ꢔꢌꢉ ꢉꢘꢁꢈꢀꢠꢘꢖꢀ
ꢑ. ꢔRꢘꢁꢌRꢜ ꢉꢌꢕꢮꢁ ꢧꢟꢧ ꢘꢠ ꢠꢈꢌꢕꢘꢀꢆ ꢔꢂꢌꢀꢈ
ꢔꢌꢊꢃꢌꢆꢈ Rꢖꢙ ꢌꢀꢉ ꢊꢖꢂꢮꢁꢀ ꢂꢌꢋꢈꢂꢘꢀꢆ ꢁꢌꢜ ꢗꢌRꢜ
ꢒ
!
ꢌꢁꢖꢀꢆ ꢱꢁꢲꢰꢳꢴe ꢔRꢖꢉꢮꢊꢕꢠ. Rꢈꢗꢘꢈꢙ ꢈꢌꢊꢅ ꢔꢌꢊꢃꢌꢆꢈ
ꢂꢌꢜꢖꢮꢕ ꢊꢌRꢈꢇꢮꢂꢂꢜ
ꢠꢮꢋꢠꢕRꢌꢕꢈ ꢕꢅꢃ
ꢁꢖꢂꢉ ꢊꢌꢔ ꢅꢕ
0.ꢍꢑ
0.ꢍ0
0.ꢎ0
0.ꢍꢑ
0.0ꢨ
ꢂꢕꢁꢝꢝꢝꢝꢝꢝ
ꢱꢁꢲꢰꢳꢴe
ꢊꢖꢁꢔꢖꢀꢈꢀꢕ
ꢔꢘꢀ ꢚꢌꢍꢛ
ꢠꢮꢆꢆꢈꢠꢕꢈꢉ ꢔꢊꢋ ꢂꢌꢜꢖꢮꢕ
ꢕꢖꢔ ꢗꢘꢈꢙ
ꢕꢖꢕꢌꢂ ꢀꢮꢁꢋꢈR ꢖꢇ ꢋꢌꢂꢂꢠꢬ ꢫꢍ
ꢕRꢌꢜ ꢔꢘꢀ ꢍ
ꢋꢈꢗꢈꢂ
ꢔꢌꢊꢃꢌꢆꢈ ꢘꢀ ꢕRꢌꢜ ꢂꢖꢌꢉꢘꢀꢆ ꢖRꢘꢈꢀꢕꢌꢕꢘꢖꢀ
ꢋꢆꢌ ꢫꢍ 0ꢍꢍꢨ Rꢈꢗ ꢩ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
27
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTM8051
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM8074
LTM8063
40V, 1.2A Silent Switcher µModule Regulator
3.2V ≤ V ≤ 40V, 0.8V ≤ V
≤ 12V, 4mm × 4mm × 1.82mm BGA
IN
OUT
40V, 2A Step-Down Silent Switcher µModule Regulator
40V, 2.5A Step-Down Silent Switcher µModule Regulator
40V, 3.5A Step-Down μModule Regulator
3.2V ≤ V ≤ 40V, 0.8V ≤ V
≤ 15V, 4mm × 6.25mm × 2.22mm BGA
IN
OUT
Package
LTM8065
3.4V ≤ V ≤ 40V, 0.97V ≤ V
≤ 18V, 6.25mm × 6.25mm × 2.32mm
IN
OUT
BGA Package
LTM8053
LTM8003
3.4V ≤ V ≤ 40V, 0.97V ≤ V
≤ 15V, 6.25mm × 9mm × 3.32mm BGA
IN
OUT
40V, 3.5A, H-Grade, 150°C Operation, FMAE-Compliant Pinout 3.4V ≤ V ≤ 40V, 0.97V ≤ V
≤ 15V, I
= 3.5A, 6.25mm × 9mm ×
IN
OUT
OUT
3.32mm BGA
LTM8052
LTM4613
36V, 5A CVCC Step-Down μModule Regulator
36V, 8A Low EMI Step-Down μModule Regulator
6V ≤ V ≤ 36V, 1.2V ≤ V
≤ 24V, Constant Voltage Constant Current,
IN
OUT
11.25mm × 15mm × 2.82mm LGA, 11.25mm × 15mm × 3.42mm BGA
5V ≤ V ≤ 36V, 3.3V ≤ V ≤ 15V, EN55022B Compliant, 15mm ×
IN
OUT
15mm × 4.32mm LGA, 15mm × 15mm × 4.92mm BGA.
LTM8073
LTM8071
LTM4622
60V, 3A Step-Down µModule Regulator
60V, 5A Silent Switcher µModule Regulator
Dual 2.5A, 20V Step-Down µModule Regulator
3.4V ≤ V ≤ 60V, 0.85V ≤ V
≤ 15V, 6.25mm × 9mm × 3.32mm BGA
≤ 15V, 9mm × 11.25mm × 3.32mm BGA
≤ 5.5V, 6.25mm × 6.25mm × 1.82mm
IN
OUT
OUT
OUT
3.6V ≤ V ≤ 60V, 0.97V ≤ V
IN
3.6V ≤ V ≤ 20V, 0.6V ≤ V
IN
LGA, 6.25mm × 6.25mm × 2.42mm BGA
LTM4642
LTM4643
Dual 4A, 20V Step-Down µModule Regulator
Quad 3A, 20V Step-Down µModule Regulator
4.5V ≤ V ≤ 20V, 0.6V ≤ V ≤ 5.5V, 9mm × 11.25mm × 4.92mm BGA
IN
OUT
4V ≤ V ≤ 20V, 0.6V ≤ V
≤ 3.3V, 9mm × 15mm × 1.82mm LGA,
IN
OUT
9mm × 15mm × 2.42mm BGA
LTM4644
Quad 4A, 14V Step-Down µModule Regulator
4V ≤ V ≤ 14V, 0.6V ≤ V ≤ 5.5V, 9mm × 15mm × 5.01mm BGA
IN
OUT
Rev. 0
10/20
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