OP07CS-REEL7 [ADI]
Ultralow Offset Voltage Operational Amplifier; 超低失调电压运算放大器
| 型号： | OP07CS-REEL7 |
| 厂家： | 
ADI |
| 描述： | Ultralow Offset Voltage Operational Amplifier |
| 文件： | 总16页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Offset Voltage
Operational Amplifier
OP07
FEATURES
PIN CONFIGURATION
Low VOS: 75 μV maximum
1
2
3
4
8
7
6
5
V
TRIM
–IN
+IN
V–
V
TRIM
OS
OS
OP07
Low VOS drift: 1.3 μV/°C maximum
Ultrastable vs. time: 1.5 μV per month maximum
Low noise: 0.6 μV p-p maximum
Wide input voltage range: 14 V typical
Wide supply voltage range: 3 V to 18 V
125°C temperature-tested dice
V+
OUT
NC
NC = NO CONNECT
Figure 1.
APPLICATIONS
Wireless base station control circuits
Optical network control circuits
Instrumentation
The wide input voltage range of ±±1 V minimum combined
with a high CMRR of ±06 dB (OP07E) and high input
Sensors and controls
Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements
Precision filters
impedance provide high accuracy in the noninverting circuit
configuration. Excellent linearity and gain accuracy can be
maintained even at high closed-loop gains. Stability of offsets
and gain with time or variations in temperature is excellent. The
accuracy and stability of the OP07, even at high gain, combined
with the freedom from external nulling have made the OP07 an
industry standard for instrumentation applications.
GENERAL DESCRIPTION
The OP07 is available in two standard performance grades. The
OP07E is specified for operation over the 0°C to 70°C range,
and the OP07C is specified over the −40°C to +85°C
temperature range.
The OP07 has very low input offset voltage (75 μV maximum for
OP07E) that is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external
nulling. The OP07 also features low input bias current (±4 nA for
the OP07E) and high open-loop gain (200 V/mV for the OP07E).
The low offset and high open-loop gain make the OP07
The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow
SOIC packages. For CERDIP and TO-99 packages and standard
microcircuit drawing (SMD) versions, see the OP77.
particularly useful for high gain instrumentation applications.
V+
7
1
1
R2B
R2A
(OPTIONAL
NULL)
R7
C1
8
1
R1B
R1A
Q19
R9
Q10
Q9
Q11
Q12
Q8
OUT
6
Q7
Q3 Q6
Q1
Q4
Q5
C3
R5
Q17
R3
R4
C2
Q27
Q26
Q25
R10
Q20
NONINVERTING
INPUT
Q16
Q15
3
2
Q23
Q24
Q21
Q22
INVERTING
INPUT
Q2
Q14
Q18
R8
Q13
R6
4
V–
1
R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE.
Figure 2. Simplified Schematic
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
OP07
TABLE OF CONTENTS
Features .............................................................................................. ±
Absolute Maximum Ratings ............................................................6
Thermal Resistance.......................................................................6
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Typical Applications....................................................................... ±±
Applications Information.......................................................... ±2
Outline Dimensions....................................................................... ±1
Ordering Guide .......................................................................... ±4
Applications....................................................................................... ±
General Description......................................................................... ±
Pin Configuration............................................................................. ±
Revision History ............................................................................... 2
Specifications..................................................................................... 1
OP07E Electrical Characteristics ............................................... 1
OP07C Electrical Characteristics............................................... 4
REVISION HISTORY
7/06—Rev. C. to Rev D
3/03—Rev. A to Rev. B
Changes to Features.......................................................................... ±
Changes to General Description .................................................... ±
Changes to Specifications Section.................................................. 1
Changes to Table 4............................................................................ 6
Changes to Figure 6 and Figure 8................................................... 7
Changes to Figure ±1 and Figure ±4............................................... 8
Changes to Figure 20........................................................................ 9
Changes to Figure 2± to Figure 25................................................ ±0
Changes to Figure 26 and Figure 10............................................. ±±
Replaced Figure 28 ......................................................................... ±±
Changes to Applications Information Section............................ ±2
Updated Outline Dimensions....................................................... ±1
Changes to Ordering Guide .......................................................... ±4
Updated Package Titles......................................................Universal
Updated Outline Dimensions....................................................... ±±
2/02—Rev. 0 to Rev. A
Edits to Features.................................................................................±
Edits to Ordering Guide ...................................................................±
Edits to Pin Connection Drawings .................................................±
Edits to Absolute Maximum Ratings..............................................2
Deleted Electrical Characteristics .............................................. 2–1
Deleted OP07D Column from Electrical Characteristics....... 4–5
Edits to TPCs ................................................................................ 7–9
Edits to High-Speed, Low VOS Composite Amplifier ...................9
8/03—Rev. B to Rev. C
Changes to OP07E Electrical Specifications................................. 2
Changes to OP07C Electrical Specifications................................. 1
Edits to Ordering Guide .................................................................. 5
Edits to Figure 6................................................................................ 9
Updated Outline Dimensions....................................................... ±±
Rev. D | Page 2 of 16
OP07
SPECIFICATIONS
OP07E ELECTRICAL CHARACTERISTICS
VS = ±±5 V, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
INPUT CHARACTERISTICS
TA = 25°C
Input Offset Voltage1
Long-Term VOS Stability2
Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise Voltage Density
VOS
VOS/Time
IOS
IB
en p-p
en
30
0.3
0.5
±1.2
0.35
10.3
10.0
9.6
75
1.5
3.8
±±.0 nA
0.6
18.0
13.0
11.0
30
0.80
0.23
0.17
μV
μV/Month
nA
0.1 Hz to 10 Hz3
fO = 10 Hz
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
pA p-p
pA/√Hz
pA/√Hz
pA/√Hz
MΩ
GΩ
V
dB
μV/V
fO = 100 Hz3
fO = 1 kHz
Input Noise Current
Input Noise Current Density
In p-p
In
1±
fO = 10 Hz
fO = 100 Hz3
fO = 1 kHz
0.32
0.1±
0.12
50
160
±1±
123
5
Input Resistance, Differential Mode±
Input Resistance, Common Mode
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
RIN
RINCM
IVR
CMRR
PSRR
AVO
15
±13
106
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ, VO = ±10 V
RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V±
20
200
150
500
±00
V/mV
V/mV
0°C ≤ TA ≤ 70°C
Input Offset Voltage1
VOS
±5
130
1.3
1.3
5.3
35
μV
Voltage Drift Without External Trim±
Voltage Drift with External Trim3
Input Offset Current
TCVOS
TCVOSN
IOS
TCIOS
IB
TCIB
IVR
CMRR
PSRR
AVO
0.3
0.3
0.9
8
±1.5
13
±13.5
123
7
μV/°C
μV/°C
nA
RP = 20 kΩ
Input Offset Current Drift
Input Bias Current
Input Bias Current Drift
Input Voltage Range
pA/°C
±5.5 nA
35
pA/°C
V
dB
μV/V
V/mV
±13
103
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
OUTPUT CHARACTERISTICS
TA = 25°C
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ, VO = ±10 V
32
180
±50
Output Voltage Swing
VO
RL ≥ 10 kΩ
RL ≥ 2 kΩ
RL ≥ 1 kΩ
±12.5 ±13.0
±12.0 ±12.8
±10.5 ±12.0
V
V
V
0°C ≤ TA ≤ 70°C
Output Voltage Swing
VO
RL ≥ 2 kΩ
±12
±12.6
V
Rev. D | Page 3 of 16
OP07
Parameter
Symbol
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
TA = 25°C
Slew Rate
SR
BW
RO
RL ≥ 2 kΩ3
0.1
0.±
0.3
0.6
60
75
±
V/μs
MHz
Ω
mW
mW
mV
Closed-Loop Bandwidth
Open-Loop Output Resistance
Power Consumption
AVOL = 15
VO = 0, IO = 0
VS = ±15 V, No load
VS = ±3 V, No load
RP = 20 kΩ
Pd
120
6
Offset Adjustment Range
±±
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2 Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is
sample tested.
3 Sample tested.
± Guaranteed by design.
5 Guaranteed but not tested.
OP07C ELECTRICAL CHARACTERISTICS
VS = ±±5 V, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max Unit
INPUT CHARACTERISTICS
TA = 25°C
Input Offset Voltage1
Long-Term VOS Stability2
Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise Voltage Density
VOS
VOS/Time
IOS
IB
en p-p
en
60
0.±
0.8
±1.8
0.38
10.5
10.2
9.8
150
2.0
6.0
μV
μV/Month
nA
±7.0 nA
0.1 Hz to 10 Hz3
fO = 10 Hz
0.65 μV p-p
20.0 nV/√Hz
13.5 nV/√Hz
11.5 nV/√Hz
fO = 100 Hz3
fO = 1 kHz
Input Noise Current
Input Noise Current Density
In p-p
In
15
35
pA p-p
fO = 10 Hz
fO = 100 Hz3
fO = 1 kHz
0.35
0.15
0.13
33
120
±1±
120
7
0.90 pA/√Hz
0.27 pA/√Hz
0.18 pA/√Hz
Input Resistance, Differential Mode±
Input Resistance, Common Mode
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
RIN
RINCM
IVR
CMRR
PSRR
AVO
8
MΩ
GΩ
V
±13
100
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ, VO = ±10 V
RL ≥ 500 Ω, VO = ±0.5 V, VS = ±3 V±
dB
32
μV/V
V/mV
V/mV
120
100
±00
±00
−40°C ≤ TA ≤ +85°C
Input Offset Voltage1
VOS
85
0.5
0.±
1.6
12
±2.2
18
±13.5
120
10
250
1.8
1.6
8.0
50
μV
Voltage Drift Without External Trim±
Voltage Drift with External Trim3
Input Offset Current
TCVOS
TCVOSN
IOS
TCIOS
IB
TCIB
IVR
CMRR
PSRR
AVO
μV/°C
μV/°C
nA
RP = 20 kΩ
Input Offset Current Drift
Input Bias Current
Input Bias Current Drift
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
pA/°C
±9.0 nA
50
pA/°C
V
dB
μV/V
V/mV
±13
97
VCM = ±13 V
VS = ±3 V to ±18 V
RL ≥ 2 kΩ, VO = ±10 V
51
100
±00
Rev. D | Page ± of 16
OP07
Parameter
Symbol
Conditions
Min
Typ
Max Unit
OUTPUT CHARACTERISTICS
TA = 25°C
Output Voltage Swing
VO
RL ≥ 10 kΩ
RL ≥ 2 kΩ
RL ≥ 1 kΩ
±12.0 ±13.0
±11.5 ±12.8
±12.0
V
V
V
−40°C ≤ TA ≤ +85°C
Output Voltage Swing
DYNAMIC PERFORMANCE
TA = 25°C
VO
RL ≥ 2 kΩ
±12
±12.6
V
Slew Rate
SR
BW
RO
RL ≥ 2 kΩ3
AVOL = 15
VO = 0, IO = 0
VS = ±15 V, No load
VS = ±3 V, No load
RP = 20 kΩ
0.1
0.±
0.3
0.6
60
80
±
V/μs
MHz
Ω
mW
mW
mV
Closed-Loop Bandwidth
Open-Loop Output Resistance
Power Consumption
Pd
150
8
Offset Adjustment Range
±±
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2 Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is
sample tested.
3 Sample tested.
± Guaranteed by design.
5 Guaranteed but not tested.
Rev. D | Page 5 of 16
OP07
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Ratings
Supply Voltage (VS)
Input Voltage1
±22 V
±22 V
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
S and P Packages
±30 V
Indefinite
−65°C to +125°C
THERMAL RESISTANCE
Operating Temperature Range
OP07E
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
0°C to 70°C
−40°C to +85°C
150°C
OP07C
Junction Temperature
Lead Temperature, Soldering (60 sec)
Table 4. Thermal Resistance
300°C
Package Type
θJA
θJC
43
43
Unit
°C/W
°C/W
8-Lead PDIP (P-Suffix)
8-Lead SOIC_N (S-Suffix)
103
158
1 For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 6 of 16
OP07
TYPICAL PERFORMANCE CHARACTERISTICS
1000
1.0
0.8
0.6
0.4
0.2
0
V
T
= ±15V
= 25°C
V
= ±15V
S
S
900
800
700
600
500
400
300
200
100
0
A
OP07C
OP07E
–75
–50
–25
0
25
50
75
100
125
100
1k
10k
100k
100k
30
TEMPERATURE (°C)
MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω)
Figure 3. Open-Loop Gain vs. Temperature
Figure 6. Maximum Error vs. Source Resistance
30
25
20
15
10
5
1.2
1.0
0.8
0.6
0.4
0.2
0
V
T
= ±15V
= 25°C, T = 70°C
V
= ±15V
S
S
0°C ≤ T ≤ 70°C
A
A
A
THERMAL
SHOCK
RESPONSE
BAND
OP07C
OP07E
DEVICE IMMERSED
IN 70°C OIL BATH
0
–20
0
20
40
60
80
100
100
1k
10k
TIME (Seconds)
MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω)
Figure 4. Offset Voltage Change due to Thermal Shock
Figure 7. Maximum Error vs. Source Resistance
25
20
15
10
5
30
20
AT |V
DIFF
V
T
| ≤ 1.0V, | I | ≤ 7nA (OP07C)
B
V
T
= ±15V
= 25°C
S
= ±15V
= 25°C
S
A
A
10
0
OP07C
–10
–20
–30
OP07E
0
0
1
2
3
4
5
–30
–20
–10
0
10
20
TIME AFTER SUPPLY TURN-ON (Minutes)
DIFFERENTIAL INPUT VALUE (V)
Figure 5. Warm-Up Drift
Figure 8. Input Bias Current vs. Differential Input Voltage
Rev. D | Page 7 of 16
OP07
4
1000
100
10
V
= ±15V
S
R
= R = 200kΩ
S2
S1
THERMAL NOISE SOURCE
RESISTORS INCLUDED
EXCLUDED
3
2
1
0
OP07C
OP07E
R
= 0
S
V
T
= ±15V
= 25°C
S
A
1
–75
–50
–25
0
25
50
75
100
125
1
10
100
FREQUENCY (Hz)
1000
TEMPERATURE (°C)
Figure 9. Input Bias Current vs. Temperature
Figure 12. Total Input Noise Voltage vs. Frequency
2.5
2.0
1.5
1.0
0.5
0
10
V
T
= ±15V
= 25°C
V
= ±15V
S
A
S
1
OP07C
OP07E
0.1
100
–100
–75
–50
–25
0
25
50
75
100
1k
10k
BANDWIDTH (Hz)
100k
TEMPERATURE (°C)
Figure 10. Input Offset Current vs. Temperature
Figure 13. Input Wideband Noise vs. Bandwidth,
0.1 Hz to Frequency Indicated
130
REFERRED TO INPUT
5mV/CM AT OUTPUT
120
110
100
90
OP07C
80
70
60
1
10
100
1k
10k
100k
FREQUENCY (Hz)
TIME (1s/DIV)
Figure 14. CMRR vs. Frequency
Figure 11. Low Frequency Noise
Rev. D | Page 8 of 16
OP07
120
110
100
90
100
80
60
40
20
0
V
T
= ±15V
= 25°C
S
A
T
= 25°C
A
OP07C
80
70
60
50
0.1
–20
10
1
10
100
1k
10k
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. PSRR vs. Frequency
Figure 18. Closed-Loop Frequency Response for Various Gain Configurations
1000
800
600
400
200
0
28
V
T
= ±15V
= 25°C
S
T
= 25°C
A
A
24
20
16
12
8
4
0
1k
0
±5
±10
±15
±20
10k
100k
FREQUENCY (Hz)
1M
POWER SUPPLY VOLTAGE (V)
Figure 16. Open-Loop Gain vs. Power Supply Voltage
Figure 19. Maximum Output Swing vs. Frequency
120
100
80
20
15
10
5
V
T
= ±15V
= 25°C
S
A
V
V
T
= ±15V
= ±10mV
= 25°C
S
IN
A
POSITIVE SWING
NEGATIVE SWING
60
40
20
0
–20
–40
0.1
0
100
1
10
100
1k
10k
100k
1M
10M
1k
LOAD RESISTANCE TO GROUND (Ω)
10k
FREQUENCY (Hz)
Figure 17. Open-Loop Frequency Response
Figure 20. Maximum Output Voltage vs. Load Resistance
Rev. D | Page 9 of 16
OP07
1000
30.0
22.5
15.0
7.5
T
= 25°C
A
V
TRIMMED TO < 5µV AT 25°C
OS
NULLING POT = 20kΩ
100
10
1
OP07C
OP07E
OP07C
OP07E
0
0
10
20
30
40
50
60
–100
–75
–50
–25
0
25
50
75
100
TOTAL SUPPLY VOLTAGE, V+ TO V– (V)
TEMPERATURE (°C)
Figure 21. Power Consumption vs. Power Supply
Figure 24. Trimmed Offset Voltage vs. Temperature
35
30
25
20
15
16
12
8
V
T
= ±15V
= 25°C
S
A
0.3µV/MONTH
TREND LINE
0.2µV/MONTH
0.2µV/MONTH
0.3µV/MONTH
TREND LINE
4
TREND LINE
TREND LINE
0.3µV/MONTH
TREND LINE
0
0.2µV/MONTH
TREND LINE
V
V
(PIN 3) = +10mV, V = –15V
O
IN
–4
–8
–12
–16
(PIN 3) = –10mV, V = +15V
O
IN
0
1
2
3
4
0
1
2
3
4
5
6
7
8
9
10 11 12
TIME FROM OUTPUT BEING SHORTED (Minutes)
TIME (Months)
Figure 22. Output Short-Circuit Current vs. Time
Figure 25. Offset Voltage Drift vs. Time
85.00
63.75
42.50
21.25
0
V
R
= ±15V
= 100Ω
S
S
OP07C
OP07E
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 23. Untrimmed Offset Voltage vs. Temperature
Rev. D | Page 10 of 16
OP07
TYPICAL APPLICATIONS
RF
V+
R1
R3
10kΩ
R4
10kΩ
R5
10kΩ
SUM MODE
E
IN
BIAS
V+
7
R3
7
V+
3kΩ
V+
7
2
3
–
FD333
D1
R1
10kΩ
2
3
7
–
+
6
2
3
E
AD7115 OR
AD8510
2
3
IN
±10V
–
E
O
–
+
R5
10kΩ
6
E
O
OP07
6
6
OP07C
A1
+
4
OP07
0V TO +10V
R2
100kΩ
+
4
FD333
D2
V–
4
4
V–
R2
10kΩ
V–
V–
RF
R1
E
= –E
IN
–I RF
B
R1 R2
=
O
R3 R4
Figure 26. Typical Offset Voltage Test Circuit
Figure 29. Burn-In Circuit
RF
R1
SUM MODE
BIAS
E
IN
V+
R3
R4
7
V+
3kΩ
10kΩ
2
3
–
+
R1
10kΩ
7
6
2
3
OP07C
A2
+15V
7
–
E
O
E
E
E
1
2
3
R1
10kΩ
R2
6
OP07C
A1
10kΩ
2
3
–
4
R2
100kΩ
R3
10kΩ
+
6
E
OP07C
V–
O
4
RF
+ I RF
B
+
V–
E
= –E
IN
O
R1
R5
2.5kΩ
4
NOTES
1. PINOUT SHOWN FOR P PACKAGE
–15V
Figure 27. Typical Low Frequency Noise Circuit
Figure 30. High Speed, Low VOS Composite Amplifier
R4
10kΩ
R1
10kΩ
+15V
E
E
E
1
2
3
R2
10kΩ
20kΩ
7
V+
2
–
1
–
R3
10kΩ
2
3
8
6
–
+
E
OP07
7
O
6
INPUT
+
3
OUT
OP07
+
R5
2.5kΩ
4
4
–15V
NOTES
1. PINOUT SHOWN FOR P PACKAGE
V–
Figure 28. Optional Offset Nulling Circuit
Figure 31. Adjustment-Free Precision Summing Amplifier
Rev. D | Page 11 of 16
OP07
R1
R3
V+
APPLICATIONS INFORMATION
The OP07 provides stable operation with load capacitance of up
to 500 pF and ±±0 V swings; larger capacitances should be
decoupled with a 50 Ω decoupling resistor.
SENDING
JUNCTION
7
2
3
–
+
6
E
OP07
O
REFERENCE
JUNCTION
Stray thermoelectric voltages generated by dissimilar metals at
the contacts to the input terminals can degrade drift
performance. Therefore, best operation is obtained when both
input contacts are maintained at the same temperature,
preferably close to the package temperature.
R2
R1 R2
R3 R4
=
4
R4
V–
NOTES
1. PINOUT SHOWN FOR P PACKAGE
Figure 32. High Stability Thermocouple Amplifier
R3
10kΩ
R4
10kΩ
R5
10kΩ
V+
7
V+
7
FD333
D1
R1
10kΩ
2
3
–
+
E
2
3
IN
–
+
6
±10V
OP07
A2
E
O
6
OP07
A1
0V TO +10V
4
FD333
D2
4
V–
R2
10kΩ
V–
V
A
NOTES
1. PINOUT SHOWN FOR P PACKAGE
Figure 33. Precision Absolute-Value Circuit
Rev. D | Page 12 of 16
OP07
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 34. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body S-Suffix
(R-8)
Dimensions shown in millimeters and (inches)
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 35. 8-Lead Plastic Dual-in-Line Package [PDIP]
P-Suffix
(N-8)
Dimensions shown in inches and (millimeters)
Rev. D | Page 13 of 16
OP07
ORDERING GUIDE
Model
OP07EP
OP07EPZ1
OP07CP
OP07CPZ1
Temperature Range
0°C to 70°C
0°C to 70°C
Package Description
8-Lead PDIP
8-Lead PDIP
Package Option
N-8 (P-Suffix)
N-8 (P-Suffix)
N-8 (P-Suffix)
N-8 (P-Suffix)
R-8 (S-Suffix)
R-8 (S-Suffix)
R-8 (S-Suffix)
R-8 (S-Suffix)
R-8 (S-Suffix)
R-8 (S-Suffix)
8-Lead PDIP
−±0°C to +85°C
−±0°C to +85°C
−±0°C to +85°C
−±0°C to +85°C
−±0°C to +85°C
−±0°C to +85°C
−±0°C to +85°C
−±0°C to +85°C
8-Lead PDIP
OP07CS
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
OP07CS-REEL
OP07CS-REEL7
OP07CSZ1
OP07CSZ-REEL1
OP07CSZ-REEL71
1 Z = Pb-free part.
Rev. D | Page 1± of 16
OP07
NOTES
Rev. D | Page 15 of 16
OP07
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00316-0-7/06(D)
Rev. D | Page 16 of 16
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