OP184FS-REEL7 [ADI]
Precision Rail-to-Rail Input and Output Operational Amplifiers; 精密轨到轨输入和输出运算放大器
| 型号： | OP184FS-REEL7 |
| 厂家： | 
ADI |
| 描述： | Precision Rail-to-Rail Input and Output Operational Amplifiers |
| 文件： | 总24页 (文件大小：507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Rail-to-Rail
Input and Output Operational Amplifiers
OP184/OP284/OP484
PIN CONFIGURATIONS
FEATURES
Single-supply operation
Wide bandwidth: 4 MHz
Low offset voltage: 65 μV
Unity-gain stable
High slew rate: 4.0 V/μs
Low noise: 3.9 nV/√Hz
1
2
3
4
OP184
8
7
6
5
NC
NULL
–IN A
V+
–
+
+IN A
V–
OUT A
NULL
TOP VIEW
(Not to Scale)
NC = NO CONNECT
APPLICATIONS
Figure 1. 8-Lead SOIC (S-Suffix)
Battery-powered instrumentation
Power supply control and protection
Telecom
DAC output amplifier
ADC input buffer
OP284
V+
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
GENERAL DESCRIPTION
Figure 2. 8-Lead PDIP (P-Suffix)
8-Lead SOIC (S-Suffix)
The OP184/OP284/OP484 are single, dual, and quad single-supply,
4 MHz bandwidth amplifiers featuring rail-to-rail inputs and
outputs. They are guaranteed to operate from 3 V to 36 V (or
1.ꢀ V to 18 V) and function with a single supply as low as 1.ꢀ V.
1
2
3
4
5
6
7
14
13
12
11
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
V–
These amplifiers are superb for single-supply applications
requiring both ac and precision dc performance. The combi-
nation of bandwidth, low noise, and precision makes the
OP184/OP284/OP484 useful in a wide variety of applications,
including filters and instrumentation.
OP484
TOP VIEW
(Not to Scale)
+IN B
–IN B
OUT B
10 +IN C
9
8
–IN C
OUT C
Figure 3. 14-Lead PDIP (P-Suffix)
14-Lead Narrow-Body SOIC (S-Suffix)
Other applications for these amplifiers include portable telecom
equipment, power supply control and protection, and as
amplifiers or buffers for transducers with wide output ranges.
Sensors requiring a rail-to-rail input amplifier include Hall
effect, piezo electric, and resistive transducers.
The ability to swing rail-to-rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
The OP184/OP284/OP484 are specified over the hot extended
industrial (–40°C to +12ꢀ°C) temperature range. The single is
available in 8-lead SOIC surface mount packages. The dual is
available in 8-lead PDIP and SOIC surface mount packages.
The quad OP484 is available in 14-lead PDIP and 14-lead,
narrow-body SOIC packages.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
OP184/OP284/OP484
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Phase Reversal............................................................... 1ꢀ
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Applications Information .............................................................. 14
Functional Description.............................................................. 14
Input Overvoltage Protection ................................................... 14
Designing Low Noise Circuits in Single-Supply
Applications ................................................................................ 1ꢀ
Overdrive Recovery ................................................................... 16
Single-Supply, 3 V Instrumentation Amplifier ...................... 17
2.ꢀ V Reference from a 3 V Supply .......................................... 17
ꢀ V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 17
High-Side Current Monitor...................................................... 18
Capacitive Load Drive Capability ............................................ 18
Low Dropout Regulator with Current Limiting..................... 19
3 V, ꢀ0 Hz/60 Hz Active Notch Filter with False Ground..... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 22
REVISION HISTORY
4/06—Rev. C to Rev. D
9/02—Rev. A to Rev. B
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ ꢀ
Deleted Reference to 1993 System Applications Guide...............1ꢀ
Changes to Pin Configurations ...................................................... 1
Changes to Specifications, Input Bias Current Maximum.......... 2
Changes to Ordering Guide............................................................ ꢀ
Updated Outline Dimensions....................................................... 19
3/06—Rev. B to Rev. C
6/02—Rev. 0 to Rev. A
Changes to Figure 1 Caption........................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ ꢀ
Changes to Table 4............................................................................ 6
Changes to Figure ꢀ through Figure 9 ........................................... 7
Changes to Functional Description Section ...............................14
Deleted SPICE Macro Model........................................................21
Updated Outline Dimensions.......................................................21
Changes to Ordering Guide ..........................................................22
Rev. D | Page 2 of 24
OP184/OP284/OP484
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = ꢀ.0 V, VCM = 2.ꢀ V, TA = 2ꢀ°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage, OP184/OP284E Grade1
VOS
65
μV
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
165
125
350
75
175
150
450
450
600
50
μV
μV
μV
μV
μV
μV
μV
nA
Offset Voltage, OP184/OP284F Grade1
Offset Voltage, OP484E Grade1
Offset Voltage, OP484F Grade1
Input Bias Current
VOS
VOS
VOS
IB
60
2
nA
nA
nA
Input Offset Current
IOS
50
Input Voltage Range
0
5
V
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 5 V
VCM = 1.0 V to 4.0 V, −40°C ≤ TA ≤ +125°C
RL = 2 kΩ, 1 V ≤ VO ≤ 4 V
60
86
50
25
dB
dB
V/mV
V/mV
pA/°C
Large Signal Voltage Gain
240
150
RL = 2 kΩ, −40°C ≤ TA ≤ +125°C
Bias Current Drift
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
ΔIB/ΔT
VOH
VOL
IOUT
IL = 1.0 mA
IL = 1.0 mA
4.85
6.5
76
V
mV
mA
125
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Voltage Range
DYNAMIC PERFORMANCE
Slew Rate
PSRR
ISY
VS
VS = 2.0 V to 10 V, −40°C ≤ TA ≤ +125°C
VO = 2.5 V, −40°C ≤ TA ≤ +125°C
dB
mA
V
1.45
36
3
SR
tS
GBP
Øo
RL = 2 kΩ
To 0.01%, 1.0 V step
1.65
2.4
2.5
3.25
45
V/ꢀs
ꢀs
MHz
Degrees
Settling Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
0.3
3.9
0.4
μV p-p
nV/√Hz
pA/√Hz
Voltage Noise Density
Current Noise Density
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Rev. D | Page 3 of 24
OP184/OP284/OP484
@ VS = 3.0 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage, OP184/OP284E Grade1 VOS
65
μV
μV
μV
μV
μV
μV
μV
μV
nA
nA
nA
V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
165
125
350
100
200
150
450
450
600
50
Offset Voltage, OP184/OP284F Grade1 VOS
Offset Voltage, OP484E Grade1
Offset Voltage, OP484F Grade1
Input Bias Current
VOS
VOS
IB
60
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
0
3
Common-Mode Rejection Ratio
CMRR
VCM = 0 V to 3 V
VCM = 0 V to 3 V, −40°C ≤ TA ≤ +125°C
60
56
dB
dB
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
IL = 1.0 mA
IL = 1.0 mA
2.85
ꢀ6
V
mV
Output Voltage Low
125
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise Density
PSRR
ISY
VS = 1.25 V to 1.ꢀ5 V
VO = 1.5 V, −40°C ≤ TA ≤ +125°C
dB
mA
1.35
GBP
en
3
MHz
f = 1 kHz
3.9
nV/√Hz
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Rev. D | Page 4 of 24
OP184/OP284/OP484
@ VS = 1ꢀ.0 V, VCM = 0 V, TA = 2ꢀ°C, unless otherwise noted.
Table 3.
Parameter
Symbol
VOS
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage, OP184/OP284E Grade1
100
200
175
375
150
300
250
500
450
575
50
μV
μV
μV
μV
μV
μV
μV
μV
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage, OP184/OP284F Grade1
Offset Voltage, OP484E Grade1
Offset Voltage, OP484F Grade1
Input Bias Current
VOS
VOS
VOS
IB
80
nA
nA
nA
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
−15
86
80
150
75
+15
V
dB
dB
V/mV
V/mV
μV/°C
pA/°C
CMRR
AVO
VCM = −14.0 V to +14.0 V, −40°C ≤ TA ≤ +125°C
VCM = −15.0 V to +15.0 V
RL = 2 kΩ, −10 V ≤ VO ≤ 10 V
90
Large Signal Voltage Gain
1000
RL = 2 kΩ, −40 V ≤ TA ≤ +125°C
Offset Voltage Drift E Grade
Bias Current Drift
ΔVOS/ΔT
ΔVB/ΔT
0.2
150
2.00
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
VOH
VOL
IOUT
IL = 1.0 mA
IL = 1.0 mA
14.8
10
V
V
mA
−14.875
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
PSRR
ISY
ISY
VS = 2.0 V to 18 V, −40°C ≤ TA ≤ +125°C
VO = 0 V, −40°C ≤ TA ≤ +125°C
VS = 18 V, −40°C ≤ TA ≤ +125°C
90
dB
mA
mA
2.0
2.25
SR
BWp
tS
RL = 2 kΩ
2.4
4.0
35
4
V/ꢀs
kHz
ꢀs
Full-Power Bandwidth
Settling Time
1% distortion, RL = 2 kΩ, VO = 29 V p-p
To 0.01%, 10 V step
Gain Bandwidth Product
Phase Margin
GBP
Øo
4.25
50
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
0.3
3.9
0.4
ꢀV p-p
nV/√Hz
pA/√Hz
Voltage Noise Density
Current Noise Density
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Rev. D | Page 5 of 24
OP184/OP284/OP484
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
18 V
18 V
Supply Voltage
Input Voltage
Differential Input Voltage1
0.6 V
Output Short-Circuit Duration to
GND
Indefinite
Storage Temperature Range
P-Suffix, S-Suffix Packages
Operating Temperature Range
−65°C to +150°C
Absolute maximum ratings apply to both DICE and packaged
parts, unless otherwise noted.
OP184/OP284/OP484E/OP484F −40°C to +125°C
Junction Temperature Range
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is
specified for device in socket for CERDIP and PDIP. θJA is
specified for device soldered in circuit board for SOIC packages.
P-Suffix, S-Suffix Packages
Lead Temperature
(Soldering 60 sec)
1 For input voltages greater than 0.6 V, the input current should be limited to
less than 5 mA to prevent degradation or destruction of the input devices.
−65°C to +150°C
300°C
Table 5. Thermal Resistance
Package Type
θJA
103
158
83
θJC
43
43
39
27
Unit
°C/W
°C/W
°C/W
°C/W
8-Lead PDIP (P-Suffix)
8-Lead SOIC (S-Suffix)
14-Lead PDIP (P-Suffix)
14-Lead SOIC (S-Suffix)
92
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
V
CC
RB1
QB5
R4
QB6
RB4
RB3
R3
Q3
R11
TP
Q17
Q16
Q12
Q11
Q9
JB1
Q8
QB9
Q7
Q5
QL1
Q1
Q4
Q2
QB10
–IN
+IN
CC2
Q10
R6
OUT
QL2
O
C
C
FF
Q6
QB2
Q18
CB1 N+
P+
QB1
QB3
R7
RB2
R1
M
QB4
Q14
Q15
R10
Q13
R8
QB7
QB8
R2
R9
CC1
R5
JB2
V
EE
Figure 4. Simplified Schematic
Rev. D | Page 6 of 24
OP184/OP284/OP484
TYPICAL PERFORMANCE CHARACTERISTICS
300
250
200
150
100
50
300
V
= 3V
S
V
= 5V
S
T
V
= 25°C
A
270
240
210
180
150
120
90
–40°C ≤ T ≤ +125°C
A
= 1.5V
CM
60
30
0
0
–100
0
0.25
0.50
0.75
1.00
1.25
1.50
1.50
125
–75
–50
–25
0
25
50
75
100
OFFSET VOLTAGE DRIFT, TCV (µV/°C)
OS
INPUT OFFSET VOLTAGE (µV)
Figure 8. Input Offset Voltage Drift Distribution
Figure 5. Input Offset Voltage Distribution
300
250
200
150
100
50
300
270
240
210
180
150
120
90
V
T
V
= 5V
= 25°C
= 2.5V
S
A
V
= ±15V
S
–40°C ≤ T ≤ +125°C
A
CM
60
30
0
0
–100
0
0.25
0.50
0.75
1.00
1.25
–75
–50
–25
0
25
50
75
100
OFFSET VOLTAGE DRIFT, TCV (µV/°C)
OS
INPUT OFFSET VOLTAGE (µV)
Figure 6. TPC 2. Input Offset Voltage Distribution
Figure 9. Input Offset Voltage Drift Distribution
–40
–45
–50
–55
–60
–65
–70
–75
–80
200
175
150
125
100
75
V
= ±15V
= 25°C
S
A
V
= V /2
S
CM
T
V
= +5V
S
50
V
= ±15V
S
25
0
–40
25
85
–125 –100 –75 –50 –25
0
25
50
75
100 125
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (µV)
Figure 7. Input Offset Voltage Distribution
Figure 10. Bias Current vs. Temperature
Rev. D | Page 7 of 24
OP184/OP284/OP484
500
1.50
1.25
1.00
0.75
0.50
0.25
0
V
= ±15V
S
T
= 25°C
A
400
300
200
100
0
–100
–200
–300
–400
–500
–15
–10
–5
0
5
10
15
0
±2.5
±5.0
±7.5
±10.0 ±12.5 ±15.0 ±17.5 ±20.0
COMMON-MODE VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 11. Input Bias Current vs. Common-Mode Voltage
Figure 14. Supply Current vs. Supply Voltage
1000
100
10
50
40
30
20
10
0
V
= ±15V
S
V
= ±15V
S
+I
SC
SOURCE
–I
SC
–I
SC
+I
SC
SINK
V
= +5V, V
50
= +2.5V
75
S
CM
0.01
0.1
1
10
–50
–25
0
25
100
125
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 12. Output Voltage to Supply Rail vs. Load Current
Figure 15. Short-Circuit Current vs. Temperature
1.2
70
60
V
T
= 5V
= 25°C
S
A
1.1
NO LOAD
50
V
= ±15V
S
1.0
0.9
0.8
0.7
0.6
0.5
40
0
30
45
20
90
10
135
180
225
270
V
V
= +5V
= +3V
S
0
S
–10
–20
–30
–40
25
85
125
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 13. Supply Current vs. Temperature
Figure 16. Open-Loop Gain and Phase vs. Frequency (No Load)
Rev. D | Page 8 of 24
OP184/OP284/OP484
70
60
60
50
V
R
= 5V
= 2kΩ
= 25°C
V
T
= 3V
= 25°C
S
S
L
A
T
NO LOAD
A
50
40
40
0
30
30
45
20
20
90
10
10
135
180
225
270
0
0
–10
–20
–30
–40
–10
–20
–30
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Open-Loop Gain and Phase vs. Frequency (No Load)
Figure 20. Closed-Loop Gain vs. Frequency (2 kΩ Load)
70
60
V
R
= ±15V
= 2kΩ
= 25°C
V
T
= ±15V
= 25°C
S
S
60
50
50
40
L
A
T
NO LOAD
A
40
0
30
30
45
20
20
90
10
10
135
180
225
270
0
0
–10
–20
–30
–40
–10
–20
–30
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Open-Loop Gain and Phase vs. Frequency (No Load)
Figure 21. Closed-Loop Gain vs. Frequency (2 kΩ Load)
2500
60
50
V
R
= 3V
= 2kΩ
= 25°C
S
L
T
A
2000
1500
40
30
20
V
= ±15V
S
–10V < V < +10V
O
10
R
= 2kΩ
L
1000
500
0
0
–10
–20
–30
–40
V
= +5V
S
+1V < V < +10V
R
O
= 2kΩ
L
–50
–25
0
25
50
75
100
125
10
100
1k
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 19. Open-Loop Gain vs. Temperature
Figure 22. Closed-Loop Gain vs. Frequency (2 kΩ Load)
Rev. D | Page 9 of 24
OP184/OP284/OP484
300
5
4
3
2
1
0
V
T
= 5V
= 25°C
S
270
240
210
180
150
120
90
A
A
= +10
V
A
= +100
V
60
V
V
R
= 5V
S
A
= +1
= 0.5V TO 4.5V
= 2kΩ
V
IN
30
L
T
= 25°C
A
0
10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Output Impedance vs. Frequency
Figure 26. Maximum Output Swing vs. Frequency
300
270
240
210
180
150
120
90
6
5
4
3
2
1
0
V
V
R
= 15V
S
V
T
= 15V
= 25°C
S
= ±14V
= 2kΩ
IN
A
L
T
= 25°C
A
A
= +10
A
= +100
V
V
60
30
A
= +1
V
0
10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. Output Impedance vs. Frequency
Figure 27. Maximum Output Swing vs. Frequency
300
270
240
210
180
150
120
90
180
160
140
120
100
80
V
T
= 3V
= 25°C
S
T = 25°C
A
A
= +10
V
A
A
= +100
V
V
= ±15V
S
60
40
V
= +3V
S
60
20
V
= +5V
S
A
= +1
V
30
0
0
10
–20
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. Output Impedance vs. Frequency
Figure 28. CMRR vs. Frequency
Rev. D | Page 10 of 24
OP184/OP284/OP484
160
140
120
100
80
30
25
20
15
10
5
±2.5V ≤ V ≤ ±15V
T
= 25°C
S
A
T
= 25°C
A
V
= ±15V
S
60
40
V
= +5V
S
20
0
V
= +3V
1M
–20
S
–40
10
0
100
1k
10k
100k
10M
1000
125
1
1
0
10
100
FREQUENCY (Hz)
1000
FREQUENCY (Hz)
Figure 29. PSRR vs. Frequency
Figure 32. Voltage Noise Density vs. Frequency
80
70
60
50
40
30
20
10
0
10
8
V
= ±2.5V
= 25°C, A
S
±2.5V ≤ V ≤ ±15V
S
T
= 1
VCL
A
T = 25°C
A
V
= ±50mV
IN
–OS
+OS
6
4
2
0
10
100
CAPACITIVE LOAD (pF)
10
100
FREQUENCY (Hz)
1000
Figure 30. Small Signal Overshoot vs. Capacitive Load
Figure 33. Current Noise Density vs. Frequency
7
6
5
4
3
2
1
0
5
4
V
= 5V
S
A
V
R
= ±15V
= 2kΩ
T
= 25°C
S
L
3
+SLEW RATE
–SLEW RATE
2
1
0.1%
0.01%
0
–1
–2
–3
–4
–5
+SLEW RATE
–SLEW RATE
V
R
= ±5V
= 2kΩ
S
L
–50
–25
0
25
50
75
100
1
2
3
4
5
6
TEMPERATURE (°C)
SETTLING TIME (µs)
Figure 31. Slew Rate vs. Temperature
Figure 34. Step Size vs. Settling Time
Rev. D | Page 11 of 24
OP184/OP284/OP484
10
160
140
120
100
80
V
T
= ±15V
= 25°C
T
= 25°C
= ±15V
S
A
8
A
6
V
S
4
2
0.1%
0.01%
0
–2
60
V
= +3V
S
40
–4
20
–6
0
–8
–20
–10
–40
100
0
1
2
3
4
5
6
1k
10k
100k
1M
10M
SETTLING TIME (µs)
FREQUENCY (Hz)
Figure 35. Step Size vs. Settling Time
Figure 38. Channel Separation vs. Frequency
V
A
= ±15V
= 100kΩ
V
S
= 5V
= +1
= OPEN
= 300pF
= 25°C
S
A
R
C
T
enV = 0.3µV p-p
V
L
L
100
90
100
90
A
400mV
10
10
0V
0%
0%
10mV
1s
100mV
1µs
Figure 36. 0.1 Hz to 10 Hz Noise
Figure 39. Small Signal Transient Response
V
A
= 5V, 0V
= 100kΩ
V
= 5V
= +1
= 2kΩ
= 300pF
= 25°C
S
S
A
R
C
T
enV = 0.3µV p-p
V
L
L
100
90
100
90
A
400mV
10
10
0V
0%
0%
10mV
1s
100mV
1µs
Figure 37. 0.1 Hz to 10 Hz Noise
Figure 40. Small Signal Transient Response
Rev. D | Page 12 of 24
OP184/OP284/OP484
0.1
V
= ±0.75V
V
A
= ±1.5V
= +1
O
S
V
NO LOAD
100
90
T
= 25°C
A
A
= +1000
= ±2.5V
= 2kΩ
V
+200mV
0V
V
S
R
L
0.01
V
= ±2.5V
= ±1.5V
O
10
–200mV
V
O
0%
0.001
100mV
500ns
0.0005
20
100
1k
FREQUENCY (Hz)
10k 20k
Figure 41. Small Signal Transient Response
Figure 43. Total Harmonic Distortion vs. Frequency
V
A
= ±0.75V
= +1
S
V
NO LOAD
100
90
T
= 25°C
A
+200mV
0V
10
–200mV
0%
100mV
1µs
Figure 42. Small Signal Transient Response
Rev. D | Page 13 of 24
OP184/OP284/OP484
APPLICATIONS INFORMATION
To achieve rail-to-rail output, the OP284 output stage design
employs a unique topology for both sourcing and sinking
current. This circuit topology is illustrated in Figure 4ꢀ. The
output stage is voltage-driven from the second gain stage. The
signal path through the output stage is inverting; that is, for
positive input signals, Q1 provides the base current drive to Q6
so that it conducts (sinks) current. For negative input signals,
the signal path via Q1→Q2→D1→Q4→Q3 provides the base
current drive for Qꢀ to conduct (source) current. Both
amplifiers provide output current until they are forced into
saturation, which occurs at approximately 20 mV from the
negative supply rail and 100 mV from the positive supply rail.
FUNCTIONAL DESCRIPTION
The OP184/OP284/OP484 are precision single-supply, rail-to-rail
operational amplifiers. Intended for the portable instrumentation
marketplace, the OPx84 family of devices combine the attributes
of precision, wide bandwidth, and low noise to make them a
superb choice in single-supply applications that require both ac
and precision dc performance. Other low supply voltage
applications for which the OP284 is well suited are active filters,
audio microphone preamplifiers, power supply control, and
telecommunications. To combine all of these attributes with
rail-to-rail input/output operation, novel circuit design techniques
are used.
V
POS
V
POS
R4
Q3
R1
R2
I1
4kΩ
4kΩ
I2
INPUT FROM
SECOND GAIN
STAGE
–
Q5
Q6
Q1
V
01
D1
D2
V
OUT
Q1
Q3
Q4
Q2
R1
–IN
+IN
R2
Q4
D1
–
V
Q2
02
R5
R3
3kΩ
I1
R4
3kΩ
I2
R3
R6
V
NEG
V
NEG
Figure 44. OP284 Equivalent Input Circuit
Figure 45. OP284 Equivalent Output Circuit
Thus, the saturation voltage of the output transistors sets the
limit on the OP284 maximum output voltage swing. Output
short-circuit current limiting is determined by the maximum
signal current into the base of Q1 from the second gain stage.
Under output short-circuit conditions, this input current level
is approximately 100 μA. With transistor current gains around 200,
the short-circuit current limits are typically 20 mA. The output
stage also exhibits voltage gain. This is accomplished by the use
of common-emitter amplifiers, and, as a result, the voltage gain
of the output stage (thus, the open-loop gain of the device)
exhibits a dependence to the total load resistance at the output
of the OP284.
For example, Figure 44 illustrates a simplified equivalent circuit
for the input stage of the OP184/OP284/OP484. It comprises
an NPN differential pair, Q1→Q2, and a PNP differential pair,
Q3→Q4, operating concurrently. Diode Network D1→Diode
Network D2 serves to clamp the applied differential input
voltage to the OP284, thereby protecting the input transistors
against avalanche damage. Input stage voltage gains are kept low
for input rail-to-rail operation. The two pairs of differential
output voltages are connected to the OP284’s second stage,
which is a compound folded cascade gain stage. It is also in the
second gain stage, where the two pairs of differential output
voltages are combined into a single-ended, output signal voltage
used to drive the output stage. A key issue in the input stage is
the behavior of the input bias currents over the input common-
mode voltage range. Input bias currents in the OP284 are the
arithmetic sum of the base currents in Q1→Q3 and in Q2→Q4.
As a result of this design approach, the input bias currents in
the OP284 not only exhibit different amplitudes; they also
exhibit different polarities. This effect is best illustrated by
Figure 10. It is, therefore, of paramount importance that the
effective source impedances connected to the OP284 inputs
be balanced for optimum dc and ac performance.
INPUT OVERVOLTAGE PROTECTION
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the input overvoltage I-V characteristic of the device must be
considered. When an overvoltage occurs, the amplifier could be
damaged, depending on the magnitude of the applied voltage
and the magnitude of the fault current. Figure 46 illustrates the
overvoltage I-V characteristic of the OP284. This graph was
generated with the supply pins connected to GND and a curve
tracer’s collector output drive connected to the input.
Rev. D | Page 14 of 24
OP184/OP284/OP484
5
4
OUTPUT PHASE REVERSAL
Some operational amplifiers designed for single-supply
operation exhibit an output voltage phase reversal when their
inputs are driven beyond their useful common-mode range.
Typically, for single-supply bipolar op amps, the negative supply
determines the lower limit of their common-mode range. With
these devices, external clamping diodes, with the anode
connected to ground and the cathode to the inputs, prevent
input signal excursions from exceeding the device’s negative
supply (that is, GND), preventing a condition that causes the
output voltage to change phase. JFET-input amplifiers can also
exhibit phase reversal, and, if so, a series input resistor is usually
required to prevent it.
3
2
1
0
–1
–2
–3
–4
–5
–5
–4
–3
–2
–1
0
1
2
3
4
5
INPUT VOLTAGE (V)
Figure 46. Input Overvoltage I-V Characteristics of the OP284
The OP284 is free from reasonable input voltage range
restrictions, provided that input voltages no greater than the
supply voltages are applied. Although device output does not
change phase, large currents can flow through the input
protection diodes as shown in Figure 46. Therefore, the technique
recommended in the Input Overvoltage Protection section
should be applied to those applications where the likelihood of
input voltages exceeding the supply voltages is high.
As shown in Figure 46, internal p-n junctions to the OP284
energize and permit current flow from the inputs to the supplies
when the input is 1.8 V more positive and 0.6 V more negative
than the respective supply rails. As illustrated in the simplified
equivalent circuit shown in Figure 44, the OP284 does not have
any internal current limiting resistors; thus, fault currents can
quickly rise to damaging levels.
DESIGNING LOW NOISE CIRCUITS IN SINGLE-
SUPPLY APPLICATIONS
This input current is not inherently damaging to the device,
provided that it is limited to ꢀ mA or less. For the OP284, once
the input exceeds the negative supply by 0.6 V, the input current
quickly exceeds ꢀ mA. If this condition continues to exist, an
external series resistor should be added at the expense of
additional thermal noise. Figure 47 illustrates a typical
noninverting configuration for an overvoltage-protected
amplifier where the series resistance, RS, is chosen such that
In single-supply applications, devices like the OP284 extend the
dynamic range of the application through the use of rail-to-rail
operation. In fact, the OPx84 family is the first of its kind to
combine single-supply, rail-to-rail operation and low noise in
one device. It is the first device in the industry to exhibit an
input noise voltage spectral density of less than 4 nV/√Hz at
1 kHz. It was also designed specifically for low-noise, single-
supply applications, and as such, some discussion on circuit
noise concepts in single-supply applications is appropriate.
VIN
) −VSUPPLY
MAX
(
RS =
ꢀ mA
Referring to the op amp noise model circuit configuration
illustrated in Figure 48, the expression for an amplifier’s total
equivalent input noise voltage for a source resistance level, RS,
is given by
For example, a 1 kΩ resistor protects the OP284 against input
signals up to ꢀ V above and below the supplies. For other
configurations where both inputs are used, then each input
should be protected against abuse with a series resistor. Again,
to ensure optimum dc and ac performance, it is recommended
to balance source impedance levels.
V
2
enT
=
2
enR
)
2 +
i
nOA ×R
)
]
+
(
enOA
2 , units in
)
Hz
R2
where:
RS = 2R is the effective, or equivalent, circuit source resistance.
1/2
OP284
V
OUT
(enOA)2 is the op amp equivalent input noise voltage spectral
R1
V
IN
power (1 Hz BW).
Figure 47. Resistance in Series with Input Limits Overvoltage Currents
to Safe Values
(inOA)2 is the op amp equivalent input noise current spectral
power (1 Hz BW).
(enR)2 is the source resistance thermal noise voltage power (4 kTR).
k = Boltzmann’s constant = 1.38 × 10–23 J/K.
T is the ambient temperature in Kelvins of the circuit = 273.1ꢀ +
TA (°C).
Rev. D | Page 15 of 24
OP184/OP284/OP484
eNR
eNOA
R
Circuit noise figure is straightforward to calculate because the
signal level in the application is not required to determine it.
However, many designers using NF calculations as the basis for
achieving optimum SNR believe that low noise figure is equal to
low total noise. In fact, the opposite is true, as shown in Figure ꢀ0.
Here, the noise figure of the OP284 is expressed as a function of
the source resistance level. Note that the lowest noise figure for
the OP284 occurs at a source resistance level of 10 kΩ. However,
Figure 49 shows that this source resistance level and the OP284
generate approximately 14 nV/√Hz of total equivalent circuit
noise. Signal levels in the application invariably increase to
maximize circuit SNR, which is not an option in low voltage,
single-supply applications.
"NOISELESS"
iNOA
IDEAL
NOISELESS
OP AMP
eNR
R
"NOISELESS"
R
= 2R
iNOA
S
Figure 48. Op Amp Noise Circuit Model Used to Determine Total Circuit
Equivalent Input Noise Voltage and Noise Figure
As a design aid, Figure 49 shows the total equivalent input noise
of the OP284 and the total thermal noise of a resistor for com-
parison. Note that for source resistance less than 1 kΩ, the
equivalent input noise voltage of the OP284 is dominant.
10
100
FREQUENCY = 1kHz
FREQUENCY = 1kHz
T
= 25°C
9
8
7
6
5
4
3
2
1
0
A
T
= 25°C
A
OP284 TOTAL
EQUIVALENT NOISE
10
RESISTOR THERMAL
NOISE ONLY
1
100
100
1k
10k
100k
1k
10k
100k
TOTAL SOURCE RESISTANCE, R (Ω)
S
TOTAL SOURCE RESISTANCE, R (Ω)
S
Figure 50. OP284 Noise Figure vs. Source Resistance
Figure 49. OP284 Total Noise vs. Source Resistance
In single-supply applications, therefore, it is recommended for
optimum circuit SNR to choose an operational amplifier with
the lowest equivalent input noise voltage and to choose source
resistance levels consistent in maintaining low total circuit
noise.
Because circuit SNR is the critical parameter in the final
analysis, the noise behavior of a circuit is often expressed in
terms of its noise figure, NF. Noise figure is defined as the ratio
of a circuit’s output signal-to-noise to its input signal-to-noise.
An expression of a circuit NF in dB, and in terms of the
operational amplifier voltage and current noise parameters
defined previously, is given by
OVERDRIVE RECOVERY
The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to its linear
region from a saturated condition. The recovery time is
important in applications where the amplifier must recover
quickly after a large transient event. The circuit shown in
Figure ꢀ1 was used to evaluate the OP284 overload recovery
time. The OP284 takes approximately 2 ꢁs to recover from
positive saturation and approximately 1 ꢁs to recover from
negative saturation.
2
2
⎡
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
(
enOA
)
+
inOA RS
NF
(
dB
)
=10 log 1+
⎢
2
(
enRS
)
⎢
⎣
⎥
⎦
where:
NF (dB) is the noise figure of the circuit, expressed in dB.
RS is the effective, or equivalent, source resistance presented to
the amplifier.
R1
10kΩ
R2
10kΩ
(enOA)2 is the OP284 noise voltage spectral power (1 Hz BW).
(inOA)2 is the OP284 noise current spectral power (1 Hz BW).
+5V
2
8
(enRS)2 is the source resistance thermal noise voltage power =
(4kTRS).
1/2
3 OP284
1
R3
9kΩ
V
OUT
4
V
IN
10V STEP
–5V
Figure 51. Output Overload Recovery Test Circuit
Rev. D | Page 16 of 24
OP184/OP284/OP484
The low TCVOS of the OP284 at 1.ꢀ μV/°C helps maintain an
output voltage temperature coefficient that is dominated by the
temperature coefficients of R2 and R3. In this circuit with
100 ppm/°C TCR resistors, the output voltage exhibits a
temperature coefficient of 200 ppm/°C. Lower tempco resistors
are recommended for more accurate performance over
temperature.
SINGLE-SUPPLY, 3 V INSTRUMENTATION
AMPLIFIER
The low noise, wide bandwidth, and rail-to-rail input/output
operation of the OP284 make it ideal for low supply voltage
applications such as in the two op amp instrumentation
amplifier shown in Figure ꢀ2. The circuit uses the classic two
op amp instrumentation amplifier topology with four resistors
to set the gain. The transfer equation of the circuit is identical to
that of a noninverting amplifier. Resistor R2 and Resistor R3
should be closely matched to each other, as well as to Resistors
(R1 + P1) and Resistor R4 to ensure good common-mode
rejection performance. Resistor networks should be used in this
circuit for R2 and R3 because they exhibit the necessary relative
tolerance matching for good performance. Matched networks
also exhibit tight relative resistor temperature coefficients for
good circuit temperature stability. Trimming Potentiometer P1
is used for optimum dc CMR adjustment, and C1 is used to
optimize ac CMR. With the circuit values as shown, Circuit CMR
is better than 80 dB over the frequency range of 20 Hz to 20 kHz.
Circuit RTI (Referred-to-Input) noise in the 0.1 Hz to 10 Hz
band is an impressively low 0.4ꢀ μV p-p. Resistor RP1 and
Resistor RP2 serve to protect the OP284 inputs against input
overvoltage abuse. Capacitor C2 can be included to the limit
circuit bandwidth and, therefore, wide bandwidth noise
in sensitive applications. The value of this capacitor should be
adjusted depending on the required closed-loop bandwidth of
the circuit. The R4 to C2 time constant creates a pole at a
frequency equal to
One measure of the performance of a voltage reference is its
capacity to recover from sudden changes in load current. While
sourcing a steady-state load current of 1 mA, this circuit recovers
to 0.01% of the programmed output voltage in 1.ꢀ μs for a total
change in load current of 1 mA.
3V
3V
R1
17.4kΩ
8
3
2
0.1µF
1/2
1
+
–
2.5V
OP284
REF
AD589
4
R3
100kΩ
R2
100kΩ
P1
5kΩ
RESISTORS = 1%, 100ppm/°C
POTENTIOMETER = 10 TURN, 100ppm/°C
Figure 53. 2.5 V Reference That Operates on a Single 3 V Supply
5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL
The OP284 is ideal for use with a CMOS DAC to generate a
digitally controlled voltage with a wide output range. Figure ꢀ4
shows a DAC8043 used in conjunction with the ADꢀ89 to gen-
erate a voltage output from 0 V to 1.23 V. The DAC is actually
operating in voltage switching mode, where the reference is
connected to the current output, IOUT, and the output voltage is
taken from the VREF pin. This topology is inherently noninverting,
as opposed to the classic current output mode, which is
inverting and not usable in single-supply applications.
1
(
)
f 3dB =
2π R4C2
2.5 V REFERENCE FROM A 3 V SUPPLY
In many single-supply applications, the need for a 2.ꢀ V
reference often arises. Many commercially available monolithic
2.ꢀ V references require at least a minimum operating supply of
4 V. The problem is exacerbated when the minimum operating
supply voltage is 3 V. The circuit illustrated in Figure ꢀ3 is an
example of a 2.ꢀ V reference that operates from a single 3 V
supply. The circuit takes advantage of the OP284 rail-to-rail
input/output voltage ranges to amplify an ADꢀ89 1.23ꢀ V
output to 2.ꢀ V.
5V
8
R1
17.8kΩ
2
1
V
DD
R
RB
3
V
DAC8043
REF
I
1.23V
OUT
5V
8
AD589
GND CLK SR1 LD
3
2
4
7
6
5
1/2
RP1
D
4096
1
V =
OUT
(5V)
1kΩ
OP284
3V
+
DIGITAL
CONTROL
4
5
6
8
V
RP2
1kΩ
IN
7
3
2
R3
1.1kΩ
A2
V
OUT
–
1
R3
232Ω 32.4Ω
1% 1%
R2
R4
100kΩ
1%
A1
4
R2
1.1kΩ
R4
10kΩ
Figure 54. 5 V Only, 12-Bit DAC Swings Rail-to-Rail
C1
AC CMRR
TRIM
R1
9.53kΩ
In this application the OP284 serves two functions. First, it
5pF TO 40pF
C2
A1, A2 = 1/2 OP284
buffers the high output impedance of the DAC’s VREF pin, which
is on the order of 10 kΩ. The op amp provides a low impedance
output to drive any following circuitry.
P1
500Ω
R4
GAIN = 1 +
R3
SET R2 = R3
R1 + P1 = R4
Figure 52. Single Supply, 3 V Low Noise Instrumentation Amplifier
Rev. D | Page 17 of 24
OP184/OP284/OP484
Second, the op amp amplifies the output signal to provide a rail-
to-rail output swing. In this particular case, the gain is set to 4.1
so that the circuit generates a ꢀ V output when the DAC output
is at full scale. If other output voltage ranges are needed, such as
0 V ≤ VOUT ≤ 4.09ꢀ V, the gain can be easily changed by adjusting
the values of R2 and R3.
A snubber consists of a series R-C network (RS, CS), as shown in
Figure ꢀ6, connected from the output of the device to ground.
This network operates in parallel with the load capacitor, CL, to
provide the necessary phase lag compensation. The value of the
resistor and capacitor is best determined empirically.
5V
0.1µF
HIGH-SIDE CURRENT MONITOR
1/2
OP284
In the design of power supply control circuits, a great deal of
design effort is focused on ensuring the long-term reliability a
of a pass transistor over a wide range of load current conditions.
As a result, monitoring and limiting device power dissipation is
of prime importance in these designs. The circuit illustrated in
Figure ꢀꢀ is an example of a 3 V, single-supply, high-side current
monitor that can be incorporated into the design of a voltage
regulator with fold-back current limiting or a high current
power supply with crowbar protection. This design uses an
OP284’s rail-to-rail input voltage range to sense the voltage
drop across a 0.1 Ω current shunt. A P-channel MOSFET used
as the feedback element in the circuit converts the op amp’s
differential input voltage into a current. This current is applied
to R2 to generate a voltage that is a linear representation of the
load current. The transfer equation for the current monitor is
given by
V
OUT
V
IN
100mV p-p
R
50Ω
S
C
1nF
L
C
100nF
S
Figure 56. Snubber Network Compensates for Capacitive Load
The first step is to determine the value of Resistor RS. A good
starting value is 100 Ω (typically, the optimum value is less than
100 Ω). This value is reduced until the small-signal transient
response is optimized. Next, CS is determined; 10 μF is a good
starting point. This value is reduced to the smallest value for
acceptable performance (typically, 1 μF). For the case of a 10 nF
load capacitor on the OP284, the optimal snubber network is a
20 Ω in series with 1 μF. The benefit is immediately apparent, as
shown in the scope photo in Figure ꢀ7. The top trace was taken
with a 1 nF load, and the bottom trace was taken with the ꢀ0 Ω,
100 nF snubber network in place. The amount of overshoot and
ringing is dramatically reduced. Table 6 shows a few sample
snubber networks for large load capacitors.
R
⎛
⎜
⎝
⎞
⎟
⎠
SENSE
Monitor Output = R2×
× I
L
R1
For the element values shown, the transfer characteristic of the
monitor output is 2.ꢀ V/A.
DLY
5.49µs
R
0.1Ω
SENSE
I
100
90
L
3V
3V
1nF LOAD
ONLY
3V
0.1µF
1
R1
100Ω
3
2
8
1/2
OP284
4
S
SNUBBER
IN
CIRCUIT
G
M1
SI9433
10
0%
D
MONITOR
OUTPUT
B
50mV 50mV
2µs
R2
2.49kΩ
W
Figure 57. Overshoot and Ringing Is Reduced by Adding a Snubber Network
in Parallel with the 1 nF Load
Figure 55. High-Side Load Current Monitor
Table 6. Snubber Networks for Large Capacitive Loads
CAPACITIVE LOAD DRIVE CAPABILITY
Load Capacitance (CL)
Snubber Network (RS, CS)
The OP284 exhibits excellent capacitive load driving capa-
bilities. It can drive up to 1 nF, as shown in Figure 28. Even
though the device is stable, a capacitive load does not come
without penalty in bandwidth. The bandwidth is reduced to less
than 1 MHz for loads greater than 2 nF. A snubber network
on the output does not increase the bandwidth, but it does
significantly reduce the amount of overshoot for a given
capacitive load.
1 nF
10 nF
100 nF
50 Ω, 100 nF
20 Ω, 1 ꢀF
5 Ω, 10 ꢀF
Rev. D | Page 18 of 24
OP184/OP284/OP484
For this example, because VOUT of 4.ꢀ V with VOUT2 = 2.ꢀ V
requires a U1B gain of 1.8 times, R3 and R2 are chosen for a
ratio of 1.2:1 or 10.0 kΩ:8.06 kΩ (using closest 1% values). Note
that for the lowest VOUT dc error, R2||R3 should be maintained
equal to R1 (as in this example), and the R2 to R3 resistors
should be stable, close tolerance metal film types. The table in
Figure ꢀ8 summarizes R1 to R3 values for some popular
voltages. However, note that, in general, the output can be
anywhere between VOUT2 and the 12 V maximum rating of Q1.
LOW DROPOUT REGULATOR WITH CURRENT
LIMITING
Many circuits require stable, regulated voltages relatively close
in potential to an unregulated input source. This low dropout
type of regulator is readily implemented with a rail-to-rail
output op amp, such as the OP284, because the wide output
swing allows easy drive to a low saturation voltage pass device.
Furthermore, it is particularly useful when the op amp also
employs a rail-to-rail input feature because this factor allows it
to perform high-side current sensing for positive rail current
limiting. Typical examples are voltages developed from 3 V to
9 V range system sources or anywhere that low dropout
performance is required for power efficiency. This 4.ꢀ V example
works from ꢀ V nominal sources with worst-case levels down to
4.6 V or less. Figure ꢀ8 shows such a regulator set up, using an
OP284 plus a low RDS(ON), P-channel MOSFET pass device. Part
of the low dropout performance of this circuit is provided by
Q1, which has a rating of 0.11 Ω with a gate drive voltage of
only 2.7 V. This relatively low gate drive threshold allows
operation of the regulator on supplies as low as 3 V without
compromising overall performance.
While the low voltage saturation characteristic of Q1 is a key
part of the low dropout, another component is a low current
sense comparison threshold with good dc accuracy. Here, this
is provided by Current Sense Amplifier U1A, which is provided
by a 20 mV reference from the 1.23ꢀ V, ADꢀ89 Reference
Diode D2 and the R7 to R8 divider. When the product of the
output current and the RS value match this voltage threshold,
the current control loop is activated, and U1A drives the Q1
gate through D1. This causes the overall circuit operation to
enter current mode control with a current limit, ILIMIT, defined
as
V
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
R7
R7 + R8
R
(
D2
)
⎛
⎜
⎝
⎞
⎟
⎠
ILIMIT
=
The circuit’s main voltage control loop operation is provided by
U1B, half of the OP284. This voltage control amplifier amplifies
the 2.ꢀ V reference voltage produced by Three Terminal U2, a
REF192. The regulated output voltage VOUT is then
RS
R2
R3
⎛
⎝
⎞
⎟
⎠
VOUT = VOUT 1+
⎜
2
C4
0.1µF
R
0.05Ω
S
Q1
SI9433DY
+V
S
V
> V + 0.1V
S
OUT
R7
R6
U1A
OP284
R5
4.99kΩ
4.99kΩ
22.1kΩ
D1
D2
AD589
3
2
8
1N4148
1
R8
301kΩ
4
R4
2.21kΩ
C1
0.01µF
C5
0.01µF
R9
27.4kΩ
6
5
7
D3
1N4148
R11
1kΩ
U1B
OP284
R2
8.06kΩ
R1
4.53kΩ
V
=
OUT
4.5V @ 350mA
(SEE TABLE)
U2
REF192
OUTPUT TABLE
R1kΩ R2kΩ R3kΩ
V
2
OUT
C2
0.1µF
6
R3
10kΩ
5.0V
4.5V
3.3V
3.0V
4.99
4.53
2.43
1.69
10.0
8.08
3.24
2.00
10.0
10.0
10.0
10.0
V
2.5V
OUT2
3
C6
10µF
V
C
R10
1kΩ
C2
1µF
OPTIONAL
4
ON/OFF CONTROL INPUT
CMOS HI (OR OPEN) = ON
LO = OFF
V
COMMON
V
COMMON
IN
OUT
Figure 58. Low Dropout Regulator with Current Limiting
Rev. D | Page 19 of 24
OP184/OP284/OP484
Notch filters are commonly used to reject power line frequency
interference that often obscures low frequency physiological
signals, such as heart rates, blood pressure readings, EEGs, and
EKGs. This notch filter effectively squelches 60 Hz pickup at a
Filter Q of 0.7ꢀ. Substituting 3.16 kΩ resistors for the 2.67 kΩ
resistor in the Twin-T section (R1 through Rꢀ) configures the
active filter to reject ꢀ0 Hz interference.
Obviously, it is desirable to keep this comparison voltage small
because it becomes a significant portion of the overall dropout
voltage. Here, the 20 mV reference is higher than the typical
offset of the OP284 but is still reasonably low as a percentage
of VOUT (<0.ꢀ%). In adapting the limiter for other ILIMIT levels,
Sense Resistor RS should be adjusted along with R7 to R8, to
maintain this threshold voltage between 20 mV and ꢀ0 mV.
R2
3V
4
Performance of the circuit is excellent. For the 4.ꢀ V output
version, the measured dc output change for a 22ꢀ mA load
change was on the order of a few micro volts, while the dropout
voltage at this same current level was about 30 mV. The current
limit, as shown, is 400 mA, allowing the circuit to be used at
levels up to 300 mA or more. While the Q1 device can actually
support currents of several amperes, a practical current rating
takes into account the 2.ꢀ W, 2ꢀ°C dissipation of the the SOIC-8
device. Because a short-circuit current of 400 mA at an input
level of ꢀ V causes a 2 W dissipation in Q1, other input
conditions should be considered carefully in terms of potential
overheating of Q1. Of course, if higher powered devices are
used for Q1, this circuit can support outputs of tens of amperes
as well as the higher VOUT levels already noted.
2.67kΩ
R1
2.67kΩ
C1
C2
2
3
1µF
1µF
5
6
1
A1
7
V
V
O
A2
11
IN
R3
2.67kΩ
R4
2.67kΩ
R6
10kΩ
R7
1kΩ
C3
2µF
R5
1.33kΩ
R8
1kΩ
(1µF × 2)
(2.68kΩ ÷ 2)
R11
10kΩ
Q = 0.75
C5
0.03µF
NOTE: FOR 50Hz APPLICATIONS
CHANGE R1, R2, R3, AND R4 TO 3.1kΩ
AND R5 TO 1.58kΩ (3.16kΩ ÷ 2).
3V
R12
9
R9
150Ω
20kΩ
8
A3
C6
10
1µF
1.5V
C4
1µF
R10
20kΩ
A1, A2, A3 = OP484
The circuit shown can be used as either a standard low dropout
regulator, or it can be used with on/off control. By driving Pin 3
of U1 with the optional logic control signal, VC, the output is
switched between on and off. Note that when the output is off
in this circuit, it is still active (that is, not an open circuit). This
is because the off state simply reduces the voltage input to R1,
leaving the U1A/U1B amplifiers and Q1 still active.
Figure 59. A 3 V Single-Supply, 50Hz to 60 Hz Active Notch Filter
with False Ground
Amplifier A3 is the heart of the false ground bias circuit. It buffers
the voltage developed at R9 and R10 and is the reference for the
active notch filter. Because the OP484 exhibits a rail-to-rail input
common-mode range, R9 and R10 are chosen to split the 3 V
supply symmetrically. An in-the-loop compensation scheme is
used around the OP484 that allows the op amp to drive C6,
a 1 μF capacitor, without oscillation. C6 maintains a low
impedance ac ground over the operating frequency range of
the filter.
When the on/off control is used, Resistor R10 should be used
with U1 to speed on/off switching and to allow the output of the
circuit to settle to a nominal zero voltage. Component D3 and
Component R11 also aid in speeding up the on/off transition by
providing a dynamic discharge path for C2. Off/on transition
time is less than 1 ms, while the on/off transition is longer, but
less than 10 ms.
The filter section uses an OP484 in a Twin-T configuration
whose frequency selectivity is very sensitive to the relative
matching of the capacitors and resistors in the Twin-T section.
Mylar is the material of choice for the capacitors, and the
relative matching of the capacitors and resistors determines the
pass band symmetry of the filter. Using 1% resistors and ꢀ%
capacitors produces satisfactory results.
3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH
FALSE GROUND
To process signals in a single-supply system, it is often best to
use a false ground biasing scheme. A circuit that uses this approach
is shown in Figure ꢀ9. In this circuit, a false ground circuit
biases an active notch filter used to reject ꢀ0 Hz/60 Hz power
line interference in portable patient monitoring equipment.
Rev. D | Page 20 of 24
OP184/OP284/OP484
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
5.00 (0.1968)
4.80 (0.1890)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.25 (0.0098)
0.10 (0.0040)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-001-BA
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 60. 8-Lead Plastic Dual In-Line Package [PDIP]
Figure 62. 8-Lead Standard Small Outline Package [SOIC]
(N-8)
P-Suffix
Narrow Body
(R-8)
S-Suffix
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters and (inches)
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
1
8
7
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
8.75 (0.3445)
8.55 (0.3366)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
14
1
8
7
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
× 45°
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.25 (0.0098)
0.10 (0.0039)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
8°
0°
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-001-AA
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 61. 14-Lead Plastic Dual In-Line Package [PDIP]
Figure 63. 14-Lead Standard Small Outline Package [SOIC]
(N-14)
P-Suffix
Narrow Body
(R-14)
S-Suffix
Dimensions shown in inches and (millimeters)
Dimensions shown in millimeters and (inches)
Rev. D | Page 21 of 24
OP184/OP284/OP484
ORDERING GUIDE
Model
OP184ES
OP184ES-REEL
OP184ES-REEL7
OP184ESZ1
OP184ESZ-REEL1
OP184ESZ-REEL71
OP184FS
OP184FS-REEL
OP184FS–REEL7
OP184FSZ1
OP184FSZ-REEL1
OP184FSZ-REEL71
OP284EP
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead PDIP
8-Lead PDIP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
Die
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
OP284EPZ1
OP284ES
OP284ES-REEL
OP284ES-REEL7
OP284ESZ1
OP284ESZ-REEL1
OP284ESZ-REEL71
OP284FS
OP284FS-REEL
OP284FS-REEL7
OP284FSZ1
OP284FSZ-REEL1
OP284FSZ-REEL71
OP284GBC
OP484ES
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead PDIP
14-Lead PDIP
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
R-14
R-14
R-14
R-14
N-14
N-14
R-14
R-14
R-14
R-14
R-14
R-14
OP484ES-REEL
OP484ESZ1
OP484ESZ-REEL1
OP484FP
OP484FPZ1
OP484FS
OP484FS-REEL
OP484FS-REEL7
OP484FSZ1
OP484FSZ-REEL1
OP484FSZ-REEL71
1 Z = Pb-free part.
Rev. D | Page 22 of 24
OP184/OP284/OP484
NOTES
Rev. D | Page 23 of 24
OP184/OP284/OP484
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00293-0-4/06(D)
Rev. D | Page 24 of 24
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