OP2177ARMZ-R7 [ADI]
Precision Low Noise, Low Input Bias Current Dual Operational Amplifier;
| 型号： | OP2177ARMZ-R7 |
| 厂家： | 
ADI |
| 描述： | Precision Low Noise, Low Input Bias Current Dual Operational Amplifier 放大器 PC 光电二极管 |
| 文件： | 总24页 (文件大小：373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Low Noise, Low Input
Bias Current Operational Amplifiers
OP1177/OP2177/OP4177
FEATURES
PIN CONFIGURATIONS
Low offset voltage: 60 μV maximum
Very low offset voltage drift: 0.7 μV/°C maximum
Low input bias current: 2 nA maximum
Low noise: 8 nV/√Hz typical
CMRR, PSRR, and AVO > 120 dB minimum
Low supply current: 400 μA per amplifier
Dual supply operation: 2.ꢀ V to 1ꢀ V
Unity-gain stable
NC
–IN
+IN
V–
NC
V+
1
2
3
4
8
7
6
5
OP1177
1
8
NC
–IN
+IN
V–
NC
V+
OUT
NC
OUT
NC
OP1177
4
5
NC = NO CONNECT
NC = NO CONNECT
Figure 1. 8-Lead MSOP (RM Suffix)
Figure 2. 8-Lead SOIC_N (R Suffix)
OUT A
–IN A
+IN A
V–
V+
1
2
3
4
8
7
6
5
No phase reversal
Inputs internally protected beyond supply voltage
OUT B
–IN B
+IN B
OP2177
1
8
OUT A
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN B
OP2177
4
5
APPLICATIONS
Figure 3. 8-Lead MSOP (RM Suffix)
Figure 4. 8-Lead SOIC_N (R Suffix)
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls
Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements
Precision filters
OUT A
1
2
OUT D
–IN D
14
13
–IN A
+IN A
V+
+IN D
V–
3
4
12
11
OP4177
OUT A
OUT D
–IN D
+IN D
V–
1
7
14
–IN A
+IN A
V+
+IN B
–IN B
+IN C
–IN C
OUT C
+IN B
–IN B
5
6
7
10
9
OP4177
+IN C
–IN C
OUT C
8
OUT B
8
OUT B
Figure 5. 14-Lead SOIC_N (R Suffix)
Figure 6. 14-Lead TSSOP (RU Suffix)
GENERAL DESCRIPTION
performance in the SOIC package. MSOP and TSSOP are
available in tape and reel only.
The OPx177 family consists of very high precision, single, dual,
and quad amplifiers featuring extremely low offset voltage and
drift, low input bias current, low noise, and low power consump-
tion. Outputs are stable with capacitive loads of over 1000 pF
with no external compensation. Supply current is less than 500 μA
per amplifier at 30 V. Internal 500 Ω series resistors protect the
inputs, allowing input signal levels several volts beyond either
supply without phase reversal.
The OPx177 family offers the widest specified temperature
range of any high precision amplifier in surface-mount packaging.
All versions are fully specified for operation from −40°C to
+125°C for the most demanding operating environments.
Applications for these amplifiers include precision diode
power measurement, voltage and current level setting, and
level detection in optical and wireless transmission systems.
Additional applications include line-powered and portable
instrumentation and controls—thermocouple, RTD, strain-
bridge, and other sensor signal conditioning—and precision filters.
Unlike previous high voltage amplifiers with very low offset
voltages, the OP1177 (single) and OP2177 (dual) amplifiers
are available in tiny 8-lead surface-mount MSOP and 8-lead
narrow SOIC packages. The OP4177 (quad) is available in
TSSOP and 14-lead narrow SOIC packages. Moreover, specified
performance in the MSOP and the TSSOP is identical to
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2009 Analog Devices, Inc. All rights reserved.
OP1177/OP2177/OP4177
TABLE OF CONTENTS
Features .............................................................................................. 1
Overload Recovery Time .......................................................... 15
THD + Noise............................................................................... 16
Capacitive Load Drive ............................................................... 16
Stray Input Capacitance Compensation.................................. 17
Reducing Electromagnetic Interference.................................. 17
Proper Board Layout.................................................................. 18
Difference Amplifiers ................................................................ 18
A High Accuracy Thermocouple Amplifier........................... 19
Low Power Linearized RTD...................................................... 19
Single Operational Amplifier Bridge....................................... 20
Realization of Active Filters .......................................................... 21
Band-Pass KRC or Sallen-Key Filter........................................ 21
Channel Separation.................................................................... 21
References on Noise Dynamics and Flicker Noise ............... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Functional Description.................................................................. 14
Total Noise-Including Source Resistors................................... 14
Gain Linearity ............................................................................. 14
Input Overvoltage Protection ................................................... 15
Output Phase Reversal............................................................... 15
Settling Time............................................................................... 15
REVISION HISTORY
Changes to Figure 67 and Figure 68............................................. 21
Removed SPICE Model Section ................................................... 21
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide.......................................................... 24
11/09—Rev. F to Rev. G
Changes to Figure 64...................................................................... 19
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions....................................................... 22
4/04—Rev. B to Rev. C
5/09—Rev. E to Rev. F
Changes to Ordering Guide.............................................................4
Changes to TPC 6..............................................................................5
Changes to TPC 26............................................................................7
Updated Outline Dimensions....................................................... 17
Changes to Figure 64...................................................................... 19
Changes to Ordering Guide .......................................................... 24
10/07—Rev. D to Rev. E
Changes to General Description .................................................... 1
Changes to Table 4............................................................................ 5
Updated Outline Dimensions....................................................... 22
4/02—Rev. A to Rev. B
Added OP4177.........................................................................Global
Edits to Specifications.......................................................................2
Edits to Electrical Characteristics Headings..................................4
Edits to Ordering Guide ...................................................................4
7/06—Rev. C to Rev. D
Changes to Table 4............................................................................ 5
Changes to Figure 51...................................................................... 14
Changes to Figure 52...................................................................... 15
Changes to Figure 54...................................................................... 16
Changes to Figure 58 to Figure 61................................................ 17
Changes to Figure 62 and Figure 63............................................. 18
Changes to Figure 64...................................................................... 19
Changes to Figure 65 and Figure 66............................................. 20
11/01—Rev. 0 to Rev. A
Edit to Features ..................................................................................1
Edits to TPC 6 ...................................................................................5
7/01—Revision 0: Initial Version
Rev. G | Page 2 of 24
OP1177/OP2177/OP4177
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
OP1177
VOS
VOS
VOS
VOS
IB
15
15
25
25
+0.5
+0.2
60
75
100
120
+2
μV
μV
μV
μV
nA
nA
V
dB
dB
V/mV
OP2177/OP4177
OP1177/OP2177
OP4177
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
−40°C < TA < +125°C
−40°C < TA < +125°C
−40°C < TA < +125°C
−40°C < TA < +125°C
−2
−1
−3.5
120
118
1000
IOS
+1
+3.5
CMRR
AVO
VCM = −3.5 V to +3.5 V
−40°C < TA < +125°C
RL = 2 kΩ, VO = −3.5 V to +3.5 V
126
125
2000
Large Signal Voltage Gain
Offset Voltage Drift
OP1177/OP2177
ΔVOS/ΔT
ΔVOS/ΔT
−40°C < TA < +125°C
−40°C < TA < +125°C
0.2
0.3
0.7
0.9
μV/°C
μV/°C
OP4177
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
VOH
VOL
IOUT
IL = 1 mA, −40°C < TA < +125°C
IL = 1 mA, −40°C < TA < +125°C
VDROPOUT < 1.2 V
+4
+4.1
−4.1
10
V
V
mA
−4
POWER SUPPLY
Power Supply Rejection Ratio
OP1177
PSRR
PSRR
ISY
VS = 2.5 V to 15 V
−40°C < TA < +125°C
VS = 2.5 V to 15 V
−40°C < TA < +125°C
VO = 0 V
120
115
118
114
130
125
121
120
400
500
dB
dB
dB
dB
μA
μA
OP2177/OP4177
Supply Current per Amplifier
500
600
−40°C < TA < +125°C
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
MULTIPLE AMPLIFIERS CHANNEL SEPARATION
SR
GBP
RL = 2 kΩ
0.7
1.3
V/μs
MHz
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
DC
0.4
7.9
0.2
μV p-p
nV/√Hz
pA/√Hz
μV/V
8.5
CS
0.01
−120
f = 100 kHz
dB
1 Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as typical give unrealistically
low estimates for parameters that can have both positive and negative values.
Rev. G | Page 3 of 24
OP1177/OP2177/OP4177
ELECTRICAL CHARACTERISTICS
VS = 15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
OP1177
VOS
VOS
VOS
VOS
IB
15
15
25
25
+0.5
+0.2
60
75
100
120
+2
μV
μV
μV
μV
nA
nA
V
OP2177/OP4177
OP1177/OP2177
OP4177
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
−40°C < TA < +125°C
−40°C < TA < +125°C
−40°C < TA < +125°C
−40°C < TA < +125°C
−2
−1
−13.5
IOS
+1
+13.5
CMRR
AVO
VCM = −13.5 V to +13.5 V,
−40°C < TA < +125°C
RL = 2 kΩ, VO = –13.5 V to +13.5 V
120
1000
125
3000
dB
V/mV
Large Signal Voltage Gain
Offset Voltage Drift
OP1177/OP2177
ΔVOS/ΔT
ΔVOS/ΔT
−40°C < TA < +125°C
−40°C < TA < +125°C
0.2
0.3
0.7
0.9
μV/°C
μV/°C
OP4177
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
Short-Circuit Current
POWER SUPPLY
VOH
VOL
IOUT
ISC
IL = 1 mA, −40°C < TA < +125°C
IL = 1 mA, −40°C < TA < +125°C
VDROPOUT < 1.2 V
+14
+14.1
−14.1
10
V
V
mA
mA
−14
25
Power Supply Rejection Ratio
OP1177
PSRR
PSRR
ISY
VS = 2.5 V to 15 V
−40°C < TA < +125°C
VS = 2.5 V to 15 V
−40°C < TA < +125°C
VO = 0 V
120
115
118
114
130
125
121
120
400
500
dB
dB
dB
dB
μA
μA
OP2177/OP4177
Supply Current per Amplifier
500
600
−40°C < TA < +125°C
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
MULTIPLE AMPLIFIERS CHANNEL SEPARATION
SR
GBP
RL = 2 kΩ
0.7
1.3
V/μs
MHz
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
DC
0.4
7.9
0.2
μV p-p
nV/√Hz
pA/√Hz
μV/V
8.5
CS
0.01
−120
f = 100 kHz
dB
1 Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as typical give unrealistically
low estimates for parameters that can have both positive and negative values.
Rev. G | Page 4 of 24
OP1177/OP2177/OP4177
ABSOLUTE MAXIMUM RATINGS
Table 3.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Supply Voltage
36 V
Input Voltage
VS− to VS+
Supply Voltage
Table 4. Thermal Resistance
Package Type
8-Lead MSOP (RM-8)1
8-Lead SOIC_N (R-8)
14-Lead SOIC_N (R-14)
14-Lead TSSOP (RU-14)
Differential Input Voltage
Storage Temperature Range
R, RM, and RU Packages
Operating Temperature Range
OP1177/OP2177/OP4177
Junction Temperature Range
R, RM, and RU Packages
Lead Temperature, Soldering (10 sec)
θJA
θJC
44
43
36
43
Unit
°C/W
°C/W
°C/W
°C/W
190
158
120
240
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
1 MSOP is available in tape and reel only.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. G | Page 5 of 24
OP1177/OP2177/OP4177
TYPICAL PERFORMANCE CHARACTERISTICS
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
50
V
= ±15V
V
= ±15V
SY
T = 25°C
A
SY
45
40
35
30
25
20
15
10
5
SOURCE
SINK
0.2
0
0
–40
–30
–20
–10
0
10
20
30
40
0.001
0.01
0.1
1
10
INPUT OFFSETVOLTAGE (µV)
LOAD CURRENT (mA)
Figure 7. Input Offset Voltage Distribution
Figure 10. Output Voltage to Supply Rail vs. Load Current
90
3
2
V
= ±15V
SY
V
= ±15V
SY
80
70
60
50
40
30
20
10
0
1
0
–1
–2
–3
0
50
100
–50
150
0.05
0.15
0.25
0.35
0.45
0.55
0.65
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
Figure 8. Input Offset Voltage Drift Distribution
Figure 11. Input Bias Current vs. Temperature
140
120
100
80
60
50
40
30
20
10
0
270
225
180
135
90
V
= ±15V
V
C
R
= ±15V
= 0
SY
SY
L
L
=
∞
GAIN
60
PHASE
45
40
0
20
–10
–20
–45
–90
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
100k
1M
10M
INPUT BIAS CURRENT (nA)
FREQUENCY (Hz)
Figure 9. Input Bias Current Distribution
Figure 12. Open-Loop Gain and Phase Shift vs. Frequency
Rev. G | Page 6 of 24
OP1177/OP2177/OP4177
120
100
80
V
= ±15V
= 1,000pF
= 2kΩ
= 100mV
= 1
SY
V
V
C
R
= ±15V
= 4mV p-p
= 0
SY
IN
C
R
V
L
L
L
L
IN
=
∞
A
V
60
A
A
= 100
= 10
V
40
V
20
0
A
= 1
V
–20
–40
–60
–80
GND
1k
10k
100k
1M
10M
100M
TIME (100µs/DIV)
FREQUENCY (Hz)
Figure 16. Small Signal Transient Response
Figure 13. Closed-Loop Gain vs. Frequency
50
45
40
35
30
25
20
15
10
500
V
V
= ±15V
= 50mV p-p
V
R
= ±15V
= 2kΩ
= 100mV p-p
SY
IN
SY
450
400
350
300
250
200
150
100
L
V
IN
A
= 1
V
A
= 10
V
+OS
A
= 100
V
–OS
5
0
50
0
1
10k
10
100
CAPACITANCE (pF)
1k
1k
10k
FREQUENCY (Hz)
100k
1M
100
Figure 14. Output Impedance vs. Frequency
Figure 17. Small Signal Overshoot vs. Load Capacitance
V
C
R
= ±15V
= 300pF
= 2kΩ
= 4V
= 1
V
= ±15V
= 10kΩ
= –100
SY
SY
R
A
V
L
L
V
L
OUTPUT
V
= 200mV
IN
IN
0V
A
V
–15V
+200mV
0V
GND
INPUT
TIME (100µs/DIV)
TIME (10µs/DIV)
Figure 18. Positive Overvoltage Recovery
Figure 15. Large Signal Transient Response
Rev. G | Page 7 of 24
OP1177/OP2177/OP4177
V
= ±15V
SY
OUTPUT
15V
0V
V
R
A
= ±15V
= 10kΩ
= –100
SY
L
V
V
= 200mV
IN
0V
–200mV
INPUT
TIME (4µs/DIV)
TIME (1s/DIV)
Figure 19. Negative Overvoltage Recovery
Figure 22. 0.1 Hz to 10 Hz Input Voltage Noise
18
16
14
12
10
8
140
120
100
80
V
= ±15V
V
= ±15V
SY
SY
60
40
6
20
4
0
2
10
100
1k
10k
100k
1M
10M
0
50
100
150
200
250
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. CMRR vs. Frequency
Figure 23. Voltage Noise Density vs. Frequency
35
30
25
20
15
10
5
140
120
100
80
V
= ±15V
SY
V
= ±15V
SY
+I
SC
–I
SC
–PSRR
+PSRR
60
40
20
0
0
–50
10
100
1k
10k
100k
1M
10M
0
50
TEMPERATURE (°C)
100
150
FREQUENCY (Hz)
Figure 21. PSRR vs. Frequency
Figure 24. Short-Circuit Current vs. Temperature
Rev. G | Page 8 of 24
OP1177/OP2177/OP4177
14.40
14.35
14.30
14.25
14.20
14.15
133
132
131
130
V
= ±15V
SY
V
= ±15V
SY
+V
OH
129
128
127
–V
OL
126
14.10
14.05
14.00
125
124
123
–50
0
50
TEMPERATURE (°C)
100
150
140
150
–50
0
50
100
150
150
40
TEMPERATURE (°C)
Figure 25. Output Voltage Swing vs. Temperature
Figure 28. CMRR vs. Temperature
0.5
0.4
133
132
131
130
V
= ±15V
V
= ±15V
SY
SY
0.3
0.2
0.1
129
128
127
0
–0.1
–0.2
–0.3
–0.4
–0.5
126
125
124
123
20
40
60
80
100
120
0
–50
0
50
100
TIME FROM POWER SUPPLY TURN-ON (Sec)
TEMPERATURE (°C)
Figure 26. Warm-Up Drift
Figure 29. PSRR vs. Temperature
18
50
V
= ±15V
V
= ±5V
SY
SY
45
40
35
30
25
16
14
12
10
8
6
20
15
4
10
5
2
0
0
–50
0
50
100
–40
–30
–20
–10
0
10
20
30
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (µV)
Figure 27. Input Offset Voltage vs. Temperature
Figure 30. Input Offset Voltage Distribution
Rev. G | Page 9 of 24
OP1177/OP2177/OP4177
1.4
500
450
400
350
300
250
200
150
100
V
T
= ±5V
V
V
= ±5V
= 50mV p-p
SY
= 25°C
SY
IN
A
1.2
1.0
0.8
0.6
0.4
0.2
0
SINK
SOURCE
A
= 1
A
= 100
V
V
A
= 10
V
50
0
100
1M
1k
10k
FREQUENCY (Hz)
100k
0.01
0.1
LOAD CURRENT (mA)
1
0.001
10
Figure 31. Output Voltage to Supply Rail vs. Load Current
Figure 34. Output Impedance vs. Frequency
60
50
270
225
180
135
90
V
C
R
V
A
= ±5V
= 300pF
= 2kΩ
= 1V
SY
V
C
R
= ±5V
= 0
SY
L
L
L
=
∞
L
IN
40
= 1
V
30
GAIN
20
PHASE
10
45
GND
0
0
–10
–45
–90
–20
100k
1M
10M
TIME (100µs/DIV)
FREQUENCY (Hz)
Figure 32. Open-Loop Gain and Phase Shift vs. Frequency
Figure 35. Large Signal Transient Response
120
100
80
V
C
R
V
= ±5V
= 1,000pF
= 2kΩ
= 100mV
= 1
SY
V
V
C
R
= ±5V
= 4mV p-p
= 0
SY
IN
L
L
L
L
IN
=
∞
A
V
60
A
A
= 100
= 10
V
40
V
20
0
A
= 1
V
–20
–40
–60
–80
GND
1k
10k
100k
1M
10M
100M
TIME (10µs/DIV)
FREQUENCY (Hz)
Figure 36. Small Signal Transient Response
Figure 33. Closed-Loop Gain vs. Frequency
Rev. G | Page 10 of 24
OP1177/OP2177/OP4177
50
45
40
35
30
25
20
15
10
V
A
R
= ±5V
= 1
= 10kΩ
S
V
R
V
= ±5V
= 2kΩ
= 100mV
SY
V
L
INPUT
L
IN
GND
+OS
OUTPUT
–OS
5
0
1
10k
10
100
CAPACITANCE (pF)
1k
TIME (200µs/DIV)
Figure 40. No Phase Reversal
Figure 37. Small Signal Overshoot vs. Load Capacitance
140
120
100
80
V
R
A
= ±5V
= 10kΩ
= –100
SY
V
= ±5V
SY
L
V
OUTPUT
V
= 200mV
IN
0V
–15V
60
+200mV
0V
40
INPUT
20
0
10
100
1k
10k
100k
1M
10M
TIME (4µs/DIV)
FREQUENCY (Hz)
Figure 41. CMRR vs. Frequency
Figure 38. Positive Overvoltage Recovery
200
180
160
140
120
100
80
V
R
A
= ±5V
= 10kΩ
= –100
V
SY
= ±5V
SY
L
V
V
= 200mV
OUTPUT
INPUT
IN
5V
0V
–PSRR
0V
60
+PSRR
40
–200mV
20
0
10
100
1k
10k
100k
1M
10M
TIME (4µs/DIV)
FREQUENCY (Hz)
Figure 42. PSRR vs. Frequency
Figure 39. Negative Overvoltage Recovery
Rev. G | Page 11 of 24
OP1177/OP2177/OP4177
4.40
4.35
4.30
4.25
4.20
4.15
V
= ±5V
SY
V
= ±5V
SY
+V
OH
–V
OL
4.10
4.05
4.00
–50
0
50
TEMPERATURE (°C)
100
150
150
150
TIME (1s/DIV)
Figure 43. 0.1 Hz to 10 Hz Input Voltage Noise
Figure 46. Output Voltage Swing vs. Temperature
18
16
14
12
10
8
25
V
= ±5V
V
= ±5V
SY
SY
20
15
10
6
5
0
4
2
–50
0
50
100
0
50
100
150
200
250
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 44. Voltage Noise Density vs. Frequency
Figure 47. Input Offset Voltage vs. Temperature
35
30
25
20
15
10
5
600
V
= ±5V
SY
500
400
300
V
= ±15V
+I
SY
SC
–I
SC
V
= ±5V
SY
200
100
0
0
–50
0
50
TEMPERATURE (°C)
100
150
–50
0
50
TEMPERATURE (°C)
100
Figure 45. Short-Circuit Current vs. Temperature
Figure 48. Supply Current vs. Temperature
Rev. G | Page 12 of 24
OP1177/OP2177/OP4177
450
0
T
= 25°C
A
400
350
300
250
–20
–40
–60
–80
200
150
–100
–120
–140
–160
100
50
0
0
5
10
15
20
25
30
35
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 50. Channel Separation vs. Frequency
Figure 49. Supply Current vs. Supply Voltage
Rev. G | Page 13 of 24
OP1177/OP2177/OP4177
FUNCTIONAL DESCRIPTION
The OPx177 series is the fourth generation of Analog Devices,
Inc., industry-standard OP07 amplifier family. OPx177 is a high
precision, low noise operational amplifier with a combination of
extremely low offset voltage and very low input bias currents.
Unlike JFET amplifiers, the low bias and offset currents are
relatively insensitive to ambient temperatures, even up to 125°C.
For RS < 3.9 kꢁ, en dominates and
n,TOTAL ≈ en
e
For 3.9 kꢁ < RS < 412 kꢁ, voltage noise of the amplifier, the
current noise of the amplifier translated through the source
resistor, and the thermal noise from the source resistor all
contribute to the total noise.
Analog Devices proprietary process technology and linear design
expertise has produced a high voltage amplifier with superior
performance to the OP07, OP77, and OP177 in a tiny MSOP
8lead package. Despite its small size, the OPx177 offers numerous
improvements, including low wideband noise, very wide input
and output voltage range, lower input bias current, and complete
freedom from phase inversion.
For RS > 412 kꢁ, the current noise dominates and
en,TOTAL ≈ inRS
The total equivalent rms noise over a specific bandwidth is
expressed as
e n
=
e n , TOTAL
)
BW
OPx177 has a specified operating temperature range as wide as
any similar device in a plastic surface-mount package. This is
increasingly important as PCB and overall system sizes continue
to shrink, causing internal system temperatures to rise. Power
consumption is reduced by a factor of four from the OP177, and
bandwidth and slew rate increase by a factor of two. The low
power dissipation and very stable performance vs. temperature
also act to reduce warmup drift errors to insignificant levels.
where BW is the bandwidth in hertz.
The preceding analysis is valid for frequencies larger than 50 Hz.
When considering lower frequencies, flicker noise (also known
as 1/f noise) must be taken into account.
For a reference on noise calculations, refer to the Band-Pass
KRC or Sallen-Key Filter section.
Open-loop gain linearity under heavy loads is superior to compet-
itive parts, such as the OPA277, improving dc accuracy and
reducing distortion in circuits with high closed-loop gains.
Inputs are internally protected from overvoltage conditions
referenced to either supply rail.
GAIN LINEARITY
Gain linearity reduces errors in closed-loop configurations. The
straighter the gain curve, the lower the maximum error over the
input signal range. This is especially true for circuits with high
closed-loop gains.
Like any high performance amplifier, maximum performance is
achieved by following appropriate circuit and PCB guidelines.
The following sections provide practical advice on getting the
most out of the OPx177 under a variety of application conditions.
The OP1177 has excellent gain linearity even with heavy loads,
as shown in Figure 51. Compare its performance to the OPA277,
shown in Figure 52. Both devices are measured under identical
conditions, with RL = 2 kꢁ. The OP2177 (dual) has virtually no
distortion at lower voltages. Compared to the OPA277 at several
supply voltages and various loads, OP1177 performance far
exceeds that of its counterpart.
TOTAL NOISE-INCLUDING SOURCE RESISTORS
The low input current noise and input bias current of the OPx177
make it useful for circuits with substantial input source resistance.
Input offset voltage increases by less than 1 ꢀV maximum per
500 ꢁ of source resistance.
V
= ±15V
SY
R
= 2kΩ
L
The total noise density of the OPx177 is
inRS
2 + 4kTRS
)
2
en,TOTAL = en +
(
OP1177
where:
en is the input voltage noise density.
in is the input current noise density.
RS is the source resistance at the noninverting terminal.
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the ambient temperature in Kelvin (T = 273 + temperature
in degrees Celsius).
(5V/DIV)
Figure 51. Gain Linearity
Rev. G | Page 14 of 24
OP1177/OP2177/OP4177
V
= ±15V
V
SY
=
10V
SY
R
= 2kΩ
A
V
= 1
L
V
IN
V
OUT
OPA277
TIME (400µs/DIV)
(5V/DIV)
Figure 53. No Phase Reversal
Figure 52. Gain Linearity
SETTLING TIME
INPUT OVERVOLTAGE PROTECTION
Settling time is defined as the time it takes an amplifier output
to reach and remain within a percentage of its final value after
application of an input pulse. It is especially important in measure-
ment and control circuits in which amplifiers buffer ADC inputs
or DAC outputs.
When input voltages exceed the positive or negative supply
voltage, most amplifiers require external resistors to protect
them from damage.
The OPx177 has internal protective circuitry that allows voltages as
high as 2.5 V beyond the supplies to be applied at the input of
either terminal without any harmful effects.
To minimize settling time in amplifier circuits, use proper
bypassing of power supplies and an appropriate choice of circuit
components. Resistors should be metal film types, because they
have less stray capacitance and inductance than their wire-wound
counterparts. Capacitors should be polystyrene or polycarbonate
types to minimize dielectric absorption.
Use an additional resistor in series with the inputs if the voltage
exceeds the supplies by more than 2.5 V. The value of the resistor
can be determined from the formula
VIN −VS
RS + 500 Ω
≤ 5 mA
The leads from the power supply should be kept as short as
possible to minimize capacitance and inductance. The OPx177
has a settling time of about 45 ꢀs to 0.01% (1 mV) with a 10 V
step applied to the input in a noninverting unity gain.
With the OPx177 low input offset current of <1 nA maximum,
placing a 5 kꢁ resistor in series with both inputs adds less than
5 ꢀV to input offset voltage and has a negligible impact on the
overall noise performance of the circuit.
OVERLOAD RECOVERY TIME
Overload recovery is defined as the time it takes the output
voltage of an amplifier to recover from a saturated condition to
its linear response region. A common example is one in which
the output voltage demanded by the transfer function of the
circuit lies beyond the maximum output voltage capability of
the amplifier. A 10 V input applied to an amplifier in a closed-
loop gain of 2 demands an output voltage of 20 V. This is beyond
the output voltage range of the OPx177 when operating at 15 V
supplies and forces the output into saturation.
5 kꢁ protects the inputs to more than 27 V beyond either supply.
Refer to the THD + Noise section for additional information on
noise vs. source resistance.
OUTPUT PHASE REVERSAL
Phase reversal is defined as a change of polarity in the amplifier
transfer function. Many operational amplifiers exhibit phase
reversal when the voltage applied to the input is greater than the
maximum common-mode voltage. In some instances, this can
cause permanent damage to the amplifier. In feedback loops, it
can result in system lockups or equipment damage. The OPx177
is immune to phase reversal problems even at input voltages
beyond the supplies.
Recovery time is important in many applications, particularly
where the operational amplifier must amplify small signals in
the presence of large transient voltages.
Rev. G | Page 15 of 24
OP1177/OP2177/OP4177
R2
100kΩ
Figure 56 is a scope shot of the output of the OPx177 in response
to a 400 mV pulse. The load capacitance is 2 nF. The circuit is
configured in positive unity gain, the worst-case condition for
stability.
V+
R1
1kΩ
7
2
3
V
OUT
6
+
–
200mV
OP1177
10kΩ
As shown in Figure 58, placing an R-C network parallel to the
load capacitance (CL) allows the amplifier to drive higher values
of CL without causing oscillation or excessive overshoot.
4
V–
Figure 54. Test Circuit for Overload Recovery Time
There is no ringing, and overshoot is reduced from 27% to 5%
using the snubber network.
Figure 18 shows the positive overload recovery time of the
OP1177. The output recovers in less than 4 ꢀs after being
overdriven by more than 100%.
Optimum values for RS and CS are tabulated in Table 5 for several
capacitive loads, up to 200 nF. Values for other capacitive loads can
be determined experimentally.
The negative overload recovery of the OP1177 is 1.4 ꢀs, as seen
in Figure 19.
Table 5. Optimum Values for Capacitive Loads
THD + NOISE
CL
RS
CS
The OPx177 has very low total harmonic distortion. This indicates
excellent gain linearity and makes the OPx177 a great choice for
high closed-loop gain precision circuits.
10 nF
50 nF
200 nF
20 Ω
30 Ω
200 Ω
0.33 ꢀF
6.8 nF
0.47 ꢀF
Figure 55 shows that the OPx177 has approximately 0.00025%
distortion in unity gain, the worst-case configuration for distortion.
V
R
C
= ±5V
= 10kΩ
= 2nF
SY
0.1
L
L
V
= ±15V
SY
R
= 10kΩ
L
BW = 22kHz
0.01
0.001
0
GND
TIME (10µs/DIV)
0.0001
100
1k
20
6k
Figure 56. Capacitive Load Drive Without Snubber
FREQUENCY (Hz)
Figure 55. THD + N vs. Frequency
CAPACITIVE LOAD DRIVE
V
= ±5V
= 10kΩ
= 200Ω
= 2nF
SY
R
R
C
C
L
S
L
S
OPx177 is inherently stable at all gains and capable of driving
large capacitive loads without oscillation. With no external
compensation, the OPx177 safely drives capacitive loads up to
1000 pF in any configuration. As with virtually any amplifier,
driving larger capacitive loads in unity gain requires additional
circuitry to assure stability.
= 0.47µF
GND
In this case, a snubber network is used to prevent oscillation
and reduce the amount of overshoot. A significant advantage of
this method is that it does not reduce the output swing because
the Resistor RS is not inside the feedback loop.
TIME (10µs/DIV)
Figure 57. Capacitive Load Drive with Snubber
Rev. G | Page 16 of 24
OP1177/OP2177/OP4177
C
f
V+
7
2
3
R1
R2
V+
6
V
OUT
OP1177
R
+
–
S
400mV
C
L
4
+
–
C
S
7
2
3
V1
V–
6
V
OUT
C
t
OP1177
Figure 58. Snubber Network Configuration
4
Caution: The snubber technique cannot recover the loss of
bandwidth induced by large capacitive loads.
V–
Figure 60. Compensation Using Feedback Capacitor
STRAY INPUT CAPACITANCE COMPENSATION
REDUCING ELECTROMAGNETIC INTERFERENCE
The effective input capacitance in an operational amplifier
circuit (Ct) consists of three components. These are the internal
differential capacitance between the input terminals, the internal
common-mode capacitance of each input to ground, and the
external capacitance including parasitic capacitance. In the
circuit in Figure 59, the closed-loop gain increases as the signal
frequency increases.
A number of methods can be utilized to reduce the effects of
EMI on amplifier circuits.
In one method, stray signals on either input are coupled to the
opposite input of the amplifier. The result is that the signal is
rejected according to the CMRR of the amplifier.
This is usually achieved by inserting a capacitor between the inputs
of the amplifier, as shown in Figure 61. However, this method can
also cause instability, depending on the value of capacitance.
The transfer function of the circuit is
R2
R1
1+
(
1+ sCt R1
)
R1
R2
V+
indicating a zero at
+
–
7
2
3
R2 + R1
s =
1
V1
=
6
V
OUT
OP1177
R2R1Ct
2π
(
R1/R2
)
Ct
C
4
Depending on the value of R1 and R2, the cutoff frequency of
the closed-loop gain can be well below the crossover frequency.
In this case, the phase margin (ΦM) can be severely degraded,
resulting in excessive ringing or even oscillation.
V–
Figure 61. EMI Reduction
Placing a resistor in series with the capacitor (see Figure 62)
increases the dc loop gain and reduces the output error. Positioning
the breakpoint (introduced by R-C) below the secondary pole of
the operational amplifier improves the phase margin and,
therefore, stability.
A simple way to overcome this problem is to insert a capacitor
in the feedback path, as shown in Figure 60.
The resulting pole can be positioned to adjust the phase margin.
Setting Cf = (R1/R2) Ct achieves a phase margin of 90°.
R can be chosen independently of C for a specific phase margin
according to the formula
R1
R2
R2
jf2
R2
R1
⎛
⎝
⎞
⎟
⎠
V+
R =
− 1 +
⎜
+
–
a
(
)
7
2
3
V1
6
V
where:
OUT
C
t
OP1177
a is the open-loop gain of the amplifier.
4
f2 is the frequency at which the phase of a = ΦM − 180°.
V–
R2
Figure 59. Stray Input Capacitance
V+
R1
7
2
+
–
R
6
V
OUT
OP1177
V1
C
3
4
V–
Figure 62. Compensation Using Input R-C Network
Rev. G | Page 17 of 24
OP1177/OP2177/OP4177
In the single instrumentation amplifier (see Figure 63), where
PROPER BOARD LAYOUT
R4
R3
R2
R1
The OPx177 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout.
=
R2
VO =
(
V2 −V1
)
R1
To avoid leakage currents, the surface of the board should be
kept clean and free of moisture. Coating the surface creates a
barrier to moisture accumulation and helps reduce parasitic
resistance on the board.
a mismatch between the ratio R2/R1 and R4/R3 causes the
common-mode rejection ratio to be reduced.
To better understand this effect, consider that, by definition,
Keeping supply traces short and properly bypassing the power
supplies minimizes power supply disturbances due to output
current variation, such as when driving an ac signal into a heavy
load. Bypass capacitors should be connected as closely as possible
to the device supply pins. Stray capacitances are a concern at the
outputs and the inputs of the amplifier. It is recommended that
signal traces be kept at least 5 mm from supply lines to
minimize coupling.
ADM
CMRR =
ACM
where ADM is the differential gain and ACM is the common-
mode gain.
VO
VDIFF
VO
VCM
ADM
=
and ACM =
1
2
A variation in temperature across the PCB can cause a mismatch in
the Seebeck voltages at solder joints and other points where dissi-
milar metals are in contact, resulting in thermal voltage errors. To
minimize these thermocouple effects, orient resistors so heat
sources warm both ends equally. Input signal paths should contain
matching numbers and types of components, where possible to
match the number and type of thermocouple junctions. For
example, dummy components such as zero value resistors can
be used to match real resistors in the opposite input path.
Matching components should be located in close proximity and
should be oriented in the same manner. Ensure leads are of equal
length so that thermal conduction is in equilibrium. Keep heat
sources on the PCB as far away from amplifier input circuitry as
is practical.
VDIFF = V1 −V2 andVCM
=
(
V1 +V2
)
For this circuit to act as a difference amplifier, its output must
be proportional to the differential input signal.
From Figure 63,
R2
R1
R3
⎡
⎢
⎢
⎢
⎤
⎥
⎥
⎥
⎛
⎜
⎝
⎛
⎜
⎝
⎞
⎟
⎠
⎞
⎟
⎠
1+
1+
R2
R1
⎛
⎜
⎝
⎞
⎟
⎠
V = −
V +
V2
1
O
⎢
⎣
⎥
⎦
R4
Arranging terms and combining the previous equations yields
R4R1+ R3R2 + 2R4R2
CMRR =
(1)
2R4R1−2R2R3
The use of a ground plane is highly recommended. A ground
plane reduces EMI noise and also helps to maintain a constant
temperature across the circuit board.
The sensitivity of CMRR with respect to the R1 is obtained by
taking the derivative of CMRR, in Equation 1, with respect to R1.
δCMRR
δR1
δ
R1R4
2R2R4 + R2R3
DIFFERENCE AMPLIFIERS
⎛
⎝
⎞
⎟
⎠
=
=
+
⎜
δR1 2R1R4 −2R2R3 2R1R4 −2R2R3
Difference amplifiers are used in high accuracy circuits to improve
the common-mode rejection ratio (CMRR).
δCMRR
δR1
1
(
2R2R3)
R2
100kΩ
2 −
R1R4
V+
Assuming that
7
R1
2
3
V1
V2
6
V
R1 ≈ R2 ≈ R3 ≈ R4 ≈ R
OUT
OP1177
4
and
V–
R(1 − δ) < R1, R2, R3, R4 < R(1 + δ)
R3 = R1
R4 = R1
R4 R2
R3 R1
the worst-case CMRR error arises when
=
Figure 63. Difference Amplifier
R1 = R4 = R(1 + δ) and R2 = R3 = R(1 − δ)
Rev. G | Page 18 of 24
OP1177/OP2177/OP4177
V
CC
Plugging these values into Equation 1 yields
1
R9
200kΩ
C1
2.2µF
CMRRMIN
≅
ADR293
2δ
V+
R3
47kΩ
R7
80.6kΩ
0.1µF
where δ is the tolerance of the resistors.
10µF
D1
R6
50Ω
Lower tolerance value resistors result in higher common-mode
rejection (up to the CMRR of the operational amplifier).
D1
TR
R2
10µF
R8
1kΩ
4.02kΩ
7
Cu
2
3
(–)
6
V
Using 5% tolerance resistors, the highest CMRR that can be
guaranteed is 20 dB. Alternatively, using 0.1% tolerance resistors
results in a common-mode rejection ratio of at least 54 dB
(assuming that the operational amplifier CMRR × 54 dB).
OUT
OP1177
T
V
TC
J
R5
100Ω
TR
Cu
(+)
10µF
4
10µF
R1
50Ω
R4
50Ω
ISOTHERMAL
BLOCK
0.1µF
With the CMRR of OPx177 at 120 dB minimum, the resistor
match is the limiting factor in most circuits. A trimming resistor
can be used to further improve resistor matching and CMRR of
the difference amplifier circuit.
V–
Figure 64. Type K Thermocouple Amplifier Circuit
LOW POWER LINEARIZED RTD
A common application for a single element varying bridge is an
RTD thermometer amplifier, as shown in Figure 65. The excita-
tion is delivered to the bridge by a 2.5 V reference applied at the
top of the bridge.
A HIGH ACCURACY THERMOCOUPLE AMPLIFIER
A thermocouple consists of two dissimilar metal wires placed in
contact. The dissimilar metals produce a voltage
VTC = α(TJ − TR)
RTDs may have thermal resistance as high as 0.5°C to 0.8°C
per mW. To minimize errors due to resistor drift, the current
through each leg of the bridge must be kept low. In this circuit,
the amplifier supply current flows through the bridge. However,
at the OPx177 maximum supply current of 600 ꢀA, the RTD
dissipates less than 0.1 mW of power, even at the highest resis-
tance. Errors due to power dissipation in the bridge are kept
under 0.1°C.
where:
TJ is the temperature at the measurement of the hot junction.
TR is the temperature at the cold junction.
α is the Seebeck coefficient specific to the dissimilar metals used
in the thermocouple.
V
TC is the thermocouple voltage and becomes larger with
increasing temperature.
Maximum measurement accuracy requires cold junction compen-
sation of the thermocouple. To perform the cold junction compen-
sation, apply a copper wire short across the terminating junctions
(inside the isothermal block) simulating a 0°C point. Adjust the
output voltage to zero using the R5 trimming resistor, and remove
the copper wire.
Calibration of the bridge is made at the minimum value of
temperature to be measured by adjusting RP until the output is zero.
To calibrate the output span, set the full-scale and linearity
potentiometers to midpoint and apply a 500°C temperature to
the sensor or substitute the equivalent 500°C RTD resistance.
Adjust the full-scale potentiometer for a 5 V output. Finally,
apply 250°C or the equivalent RTD resistance and adjust the
linearity potentiometer for 2.5 V output. The circuit achieves
better than 0.5°C accuracy after adjustment.
The OPx177 is an ideal amplifier for thermocouple circuits
because it has a very low offset voltage, excellent PSRR and
CMRR, and low noise at low frequencies.
It can be used to create a thermocouple circuit with great
linearity. Resistor R1, Resistor R2, and Diode D1, shown in
Figure 64, are mounted in an isothermal block.
Rev. G | Page 19 of 24
OP1177/OP2177/OP4177
+15V
where δ = ΔR/R is the fractional deviation of the RTD resistance
with respect to the bridge resistance due to the change in temper-
ature at the RTD.
500Ω
200Ω
0.1µF
ADR421
4.37kΩ
For δ << 1, the preceding expression becomes
4.12kΩ
⎛
⎜
⎞
⎟
6
V
R2
R
δ
4.12kΩ
100Ω
OUT
⎛
⎜
⎝
⎞
⎟
⎠
1/2
OP2177
7
⎜
⎟
V ≅
V
=
O
REF
R1 R1
R
⎜
⎜
⎝
⎟
⎟
⎠
5
1+
+
R2
100Ω
20Ω
R2
R
R1
R2
R1
⎞
R2
⎠
⎡
⎤
⎛
⎜
⎝
⎞⎛
⎠⎝
⎞
⎠
⎛
⎜
⎝
1+
+
VREF δ
⎟⎜
⎟
⎟
⎢
⎥
⎣
⎦
5kΩ
49.9kΩ
100Ω
RTD
V+
8
With VREF constant, the output voltage is linearly proportional
to δ with a gain factor of
2
3
R2
R
R1
R2
R1
R2
⎡
⎠ ⎝
⎣
⎤
⎛
⎜
⎝
⎞ ⎛
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
1/2
OP2177
1
VREF
1+
+
V
⎟ ⎜
⎢
OUT
⎥
⎦
4
15V
V–
R
F
Figure 65. Low Power Linearized RTD Circuit
0.1µF
ADR421
V+
R
R
R
SINGLE OPERATIONAL AMPLIFIER BRIDGE
7
2
3
V
The low input offset voltage drift of the OP1177 makes it very
effective for bridge amplifier circuits used in RTD signal condi-
tioning. It is often more economical to use a single bridge
operational amplifier as opposed to an instrumentation amplifier.
OUT
6
R(1+δ)
OP1177
4
V–
R
F
In the circuit shown in Figure 66, the output voltage at the
operational amplifier is
Figure 66. Single Bridge Amplifier
⎡
⎢
⎤
⎥
⎥
⎥
⎛
⎜
⎞
⎟
R2
R
δ
R1
R2
⎜
⎜
⎟
⎟
⎢
VO =
VREF
R1
R
⎢
⎛
⎝
⎞
⎟
⎠
+ 1+
(1+ δ)
⎜
⎜
⎝
⎟
⎠
⎢
⎣
⎥
⎦
Rev. G | Page 20 of 24
OP1177/OP2177/OP4177
REALIZATION OF ACTIVE FILTERS
BAND-PASS KRC OR SALLEN-KEY FILTER
CHANNEL SEPARATION
The low offset voltage and the high CMRR of the OPx177 make
it an excellent choice for precision filters, such as the band-pass
KRC filter shown in Figure 67. This filter type offers the capability
to tune the gain and the cutoff frequency independently.
Multiple amplifiers on a single die are often required to reject
any signals originating from the inputs or outputs of adjacent
channels. OP2177 input and bias circuitry is designed to prevent
feedthrough of signals from one amplifier channel to the other.
As a result, the OP2177 has an impressive channel separation of
greater than −120 dB for frequencies up to 100 kHz and greater
than −115 dB for signals up to 1 MHz.
Because the common-mode voltage into the amplifier varies with
the input signal in the KRC filter circuit, a high CMRR is required
to minimize distortion. Also, the low offset voltage of the OPx177
allows a wider dynamic range when the circuit gain is chosen to
be high.
C3
680pF
R2
10kΩ
The circuit of Figure 67 consists of two stages. The first stage is
a simple high-pass filter where the corner frequency (fC) is
V+
2
3
1
8
1/2
OP2177
1
6
5
(2)
V
R3
33kΩ
R4
33kΩ
OUT
2π C1C2R1R2
1/2
OP2177
7
C2
10nF
C1
10nF
C4
330pF
and
4
+
V1
–
R1
20kΩ
V–
R1
(3)
Q = K
R2
Figure 67. Two-Stage, Band-Pass KRC Filter
where K is the dc gain.
Choosing equal capacitor values minimizes the sensitivity and
simplifies Equation 2 to
10kΩ
V+
1
8
100Ω
6
5
2
3
1/2
OP2177
2πC R1R2
1/2
OP2177
7
1
4
The value of Q determines the peaking of the gain vs. frequency
(ringing in transient response). Commonly chosen values for Q
are generally near unity.
+
V1
50mV
V–
–
Figure 68. Channel Separation Test Circuit
1
Setting Q =
yields minimum gain peaking and minimum
REFERENCES ON NOISE DYNAMICS
AND FLICKER NOISE
2
ringing. Determine values for R1 and R2 by using Equation 3.
S. Franco, Design with Operational Amplifiers and Analog
Integrated Circuits. McGraw-Hill, 1998.
1
For
R1/R2 = 2 in the circuit example. Select R1 = 5 kꢁ
,
Q =
2
Analog Devices, Inc., The Best of Analog Dialogue, 1967 to
1991. Analog Devices, Inc., 1991.
and R2 = 10 kꢁ for simplicity.
The second stage is a low-pass filter where the corner frequency
can be determined in a similar fashion. For R3 = R4 = R
1
1
2
C3
C4
fC
=
and Q =
C3
C4
2πR
Rev. G | Page 21 of 24
OP1177/OP2177/OP4177
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 69. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 70. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Rev. G | Page 22 of 24
OP1177/OP2177/OP4177
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 71. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. G | Page 23 of 24
OP1177/OP2177/OP4177
ORDERING GUIDE
Model
OP1177AR
OP1177ARZ1
OP1177ARZ-REEL1
OP1177ARZ-REEL71
OP1177ARM-REEL
OP1177ARMZ1
OP1177ARMZ-REEL1
OP1177ARMZ-R71
OP2177AR
Temperature Range
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Package Option
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
R-8
Branding
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
AZA
AZA#
AZA#
AZA#
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
OP2177AR-REEL
OP2177AR-REEL7
OP2177ARZ1
R-8
R-8
R-8
R-8
OP2177ARZ-REEL1
OP2177ARZ-REEL71
OP2177ARM-REEL
OP2177ARMZ1
OP2177ARMZ-REEL1
OP2177ARMZ-R71
OP4177AR
OP4177AR-REEL
OP4177AR-REEL7
OP4177ARZ1
OP4177ARZ-REEL1
OP4177ARZ-REEL71
OP4177ARU
R-8
RM-8
RM-8
RM-8
RM-8
R-14
R-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
B2A
B2A#
B2A#
B2A#
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
OP4177ARU-REEL
OP4177ARUZ1
OP4177ARUZ-REEL1
1 Z = RoHS Compliant Part; # denotes Pb-free product may be top or bottom marked.
©2001–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02627-0-11/09(G)
Rev. G | Page 24 of 24
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