OP262GS-REEL7 [ADI]
15 MHz Rail-to-Rail Operational Amplifiers; 15 MHz的轨至轨运算放大器
| 型号： | OP262GS-REEL7 |
| 厂家： | 
ADI |
| 描述： | 15 MHz Rail-to-Rail Operational Amplifiers |
| 文件： | 总20页 (文件大小：798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
15 MHz Rail-to-Rail
Operational Amplifiers
OP162/OP262/OP462
FEATURES
PIN CONFIGURATIONS
Wide bandwidth: 15 MHz
Low offset voltage: 325 µV max
NULL
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
NULL
V+
OP162
OUT A
NC
Hz
TOP VIEW
(Not to Scale)
Low noise: 9.5 nV/√ @ 1 kHz
Single-supply operation: 2.7 V to 12 V
Rail-to-rail output swing
Low TCVOS: 1 µV/°C typ
High slew rate: 13 V/µs
No phase inversion
NC = NO CONNECT
Figure 1. 8-Lead Narrow-Body SOIC (S Suffix)
1
NULL
–IN A
+IN A
V–
8
7
6
5
NULL
V+
2
3
4
Unity-gain stable
OP162
TOP VIEW
(Not to Scale)
OUT A
NC
APPLICATIONS
NC = NO CONNECT
Portable instrumentation
Sampling ADC amplifier
Wireless LANs
Figure 2. 8-Lead TSSOP (RU Suffix)
8-Lead MSOP (RM Suffix)
Direct access arrangement
Office automation
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OP262
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
GENERAL DESCRIPTION
The OP162 (single), OP262 (dual), and OP462 (quad) rail-to-
rail 15 MHz amplifiers feature the extra speed new designs
require, with the benefits of precision and low power operation.
With their incredibly low offset voltage of 45 µV (typical) and
low noise, they are perfectly suited for precision filter applica-
tions and instrumentation. The low supply current of 500 µA
(typical) is critical for portable or densely packed designs. In
addition, the rail-to-rail output swing provides greater dynamic
range and control than standard video amplifiers.
Figure 3. 8-Lead Narrow-Body SOIC (S Suffix)
1
2
3
4
OUT A
–IN A
+IN A
V–
8
7
6
5
V+
OUT B
–IN B
+IN B
OP262
TOP VIEW
(Not to Scale)
Figure 4. 8-Lead TSSOP (RU Suffix)
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 –IN D
12 +IN D
11 V–
OP462
These products operate from single supplies as low as 2.7 V to
dual supplies of 6 V. The fast settling times and wide output
swings recommend them for buffers to sampling A/D converters.
The output drive of 30 mA (sink and source) is needed for
many audio and display applications; more output current can
be supplied for limited durations. The OPx62 family is specified
over the extended industrial temperature range (–40°C to
+125°C). The single OP162 amplifiers are available in 8-lead
SOIC, MSOP, and TSSOP packages. The dual OP262 amplifiers
are available in 8-lead SOIC and TSSOP packages. The quad
OP462 amplifiers are available in 14-lead, narrow-body SOIC
and TSSOP packages.
TOP VIEW
(Not to Scale)
+IN B
–IN B
OUT B
10 +IN C
9
8
–IN C
OUT C
Figure 5. 14-Lead Narrow-Body SOIC (S Suffix)
1
2
3
4
5
6
7
OUT A
–IN A
+IN A
V+
14
13
12
11
OUT D
–IN D
+IN D
V–
OP462
TOP VIEW
(Not to Scale)
+IN B
–IN B
OUT B
10 +IN C
9
8
–IN C
OUT C
Figure 6. 14-Lead TSSOP (RU Suffix)
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
OP162/OP262/OP462
TABLE OF CONTENTS
Specifications...........................................................................................3
Absolute Maximum Ratings.................................................................6
Power-On Settling Time............................................................ 14
Capacitive Load Drive ............................................................... 14
Total Harmonic Distortion and Crosstalk .............................. 15
ESD Caution.................................................................................. 6
Typical Performance Characteristics ..................................................7
Applications ...........................................................................................12
PCB Layout Considerations...................................................... 15
Application Circuits ............................................................................ 16
Single-Supply Stereo Headphone Driver................................. 16
Functional Description.............................................................. 12
Offset Adjustment ...................................................................... 12
Rail-to-Rail Output .................................................................... 12
Output Short-Circuit Protection.............................................. 12
Input Overvoltage Protection ................................................... 13
Output Phase Reversal............................................................... 13
Power Dissipation....................................................................... 13
Unused Amplifiers ..................................................................... 14
Instrumentation Amplifier........................................................ 16
Direct Access Arrangement ...................................................... 17
Spice Macro-Model.................................................................... 18
Outline Dimensions ............................................................................ 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
1/05—Rev. E to Rev. F
Changes to Absolute Maximum Ratings Table 4 and Table 5 .... 6
Change to Figure 36 ....................................................................... 13
Changes to Ordering Guide .......................................................... 20
12/04—Rev. D to Rev. E
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Changes to Specifications................................................................ 3
Changes to Package Type................................................................. 6
Change to Figure 16 ......................................................................... 8
Change to Figure 22 ......................................................................... 9
Change to Figure 36 ....................................................................... 13
Change to Figure 37 ....................................................................... 14
Changes to Ordering Guide .......................................................... 20
10/02—Rev. C to Rev. D
Deleted 8-Lead Plastic DIP (N-8) ....................................Universal
Deleted 14-Lead Plastic DIP (N-14) ................................Universal
Edits to ORDERING GUIDE........................................................ 19
Edits to Figure 30............................................................................ 19
Edits to Figure 31............................................................................ 19
Updated Outline Dimensions....................................................... 19
Rev. F | Page 2 of 20
OP162/OP262/OP462
SPECIFICATIONS
@ VS = 5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP162G, OP262G, OP462G
–40°C ≤ TA ≤ +125°C
H grade, –40°C ≤ TA ≤ +125°C
D grade
45
325
800
1
3
5
600
650
25
40
4
µV
µV
mV
mV
mV
nA
nA
nA
nA
V
0.8
360
2.5
–40°C ≤ TA ≤ +125°C
Input Bias Current
IB
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
Input Voltage Range
VCM
0
Common-Mode Rejection
Large Signal Voltage Gain
CMRR
AVO
0 V ≤ VCM ≤ 4.0 V, –40°C ≤ TA ≤ +125°C
RL = 2 kΩ, 0.5 ≤ VOUT ≤ 4.5 V
RL = 10 kΩ, 0.5 ≤ VOUT ≤ 4.5 V
RL = 10 kΩ, –40°C ≤ TA ≤ +125°C
G grade
70
110
30
88
dB
V/mV
V/mV
V/mV
µV
µV/°C
pA/°C
65
40
Long-Term Offset Voltage1
Offset Voltage Drift2
VOS
600
1
∆VOS/∆T
∆IB/∆T
Bias Current Drift
250
OUTPUT CHARACTERISTICS
Output Voltage Swing High
VOH
VOL
IL = 250 µA, –40°C ≤ TA ≤ +125°C
IL = 5 mA
IL = 250 µA, –40°C ≤TA ≤ +125°C
IL = 5 mA
4.95
4.85
4.99
4.94
14
65
80
V
V
mV
mV
mA
mA
Output Voltage Swing Low
50
150
Short-Circuit Current
Maximum Output Current
POWER SUPPLY
ISC
IOUT
Short to ground
30
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 7 V
120
600
500
dB
dB
µA
mA
µA
µA
–40°C ≤ TA ≤ +125°C
OP162, VOUT = 2.5 V
–40°C ≤ TA ≤ +125°C
OP262, OP462, VOUT = 2.5 V
–40°C ≤ TA ≤ +125°C
90
Supply Current/Amplifier
750
1
700
850
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
tS
GBP
φm
1 V < VOUT < 4 V, RL = 10 kΩ
To 0.1%, AV = –1, VO = 2 V step
10
540
15
V/µs
ns
MHz
Degrees
61
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
0.5
9.5
0.4
µV p-p
Hz
nV/√
f = 1 kHz
Hz
pA/√
1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.
2 Offset voltage drift is the average of the −40°C to +25°C delta and the +25°C to +125°C delta.
Rev. F | Page 3 of 20
OP162/OP262/OP462
@ VS = 3.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2. Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
50
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP162G, OP262G, OP462G
G, H grades, –40°C ≤ TA ≤ +125°C
D grade
325
1
3
µV
mV
mV
mV
nA
nA
V
0.8
–40°C ≤ TA ≤ +125°C
5
Input Bias Current
IB
IOS
VCM
CMRR
AVO
360
2.5
600
25
2
Input Offset Current
Input Voltage Range
Common-Mode Rejection
Large Signal Voltage Gain
0
70
0 V ≤ VCM ≤ 2.0 V, –40°C ≤ TA ≤ +125°C
RL = 2 kΩ, 0.5 V ≤ VOUT ≤ 2.5 V
RL = 10 kΩ, 0.5 V ≤ VOUT ≤ 2.5 V
G grade
110
20
30
dB
V/mV
V/mV
µV
20
Long-Term Offset Voltage1
OUTPUT CHARACTERISTICS
Output Voltage Swing High
VOS
VOH
VOL
600
IL = 250 µA
IL= 5 mA
IL = 250 µA
IL= 5 mA
2.95
2.85
2.99
2.93
14
V
V
mV
mV
Output Voltage Swing Low
50
150
66
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 7 V,
–40°C ≤ TA ≤ +125°C
OP162, VOUT = 1.5 V
–40°C ≤ TA ≤ +125°C
OP262, OP462, VOUT = 1.5 V
–40°C ≤ TA ≤ +125°C
60
110
600
dB
µA
mA
µA
µA
Supply Current/Amplifier
700
1
650
850
500
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
tS
GBP
φm
RL = 10 kΩ
To 0.1%, AV = –1, VO = 2 V step
10
575
15
V/µs
ns
MHz
Degrees
59
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
0.5
9.5
0.4
µV p-p
Hz
nV/√
f = 1 kHz
Hz
pA/√
1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.
Rev. F | Page 4 of 20
OP162/OP262/OP462
@ VS = 5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3. Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP162G, OP262G, OP462G
−40°C ≤ TA ≤ +125°C
H grade, –40°C ≤ TA ≤ +125°C
D grade
25
325
800
1
3
5
µV
µV
mV
mV
mV
nA
0.8
260
2.5
−40°C ≤ TA ≤ +125°C
Input Bias Current
IB
500
650
25
40
+4
nA
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
nA
nA
Input Voltage Range
Common-Mode Rejection
Large Signal Voltage Gain
VCM
CMRR
AVO
–5
70
V
dB
110
35
120
−4.9 V ≤ VCM ≤ +4.0 V, –40°C ≤ TA ≤ +125°C
RL = 2 kΩ, –4.5 V ≤ VOUT ≤ +4.5 V
RL = 10 kΩ, –4.5 V ≤ VOUT ≤ +4.5 V
−40°C ≤ TA ≤ +125°C
V/mV
V/mV
V/mV
µV
µV/°C
pA/°C
75
25
Long-Term Offset Voltage1
Offset Voltage Drift2
VOS
G grade
600
1
∆VOS/∆T
∆IB/∆T
Bias Current Drift
250
OUTPUT CHARACTERISTICS
Output Voltage Swing High
VOH
VOL
IL = 250 µA, –40°C ≤ TA ≤ +125°C
IL= 5 mA
IL = 250 µA, –40°C ≤ TA ≤ +125°C
IL= 5 mA
4.95
4.85
4.99
4.94
–4.99
–4.94
80
V
V
V
V
mA
mA
Output Voltage Swing Low
–4.95
–4.85
Short-Circuit Current
Maximum Output Current
ISC
IOUT
Short to ground
30
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 1.35 V to 6 V,
−40°C ≤ TA ≤ +125°C
OP162, VOUT = 0 V
60
110
650
dB
µA
mA
µA
mA
V
Supply Current/Amplifier
800
1.15
775
1
−40°C ≤ TA ≤ +125°C
OP262, OP462, VOUT = 0 V
−40°C ≤ TA ≤ +125°C
550
Supply Voltage Range
VS
3.0 ( 1.5ꢀ
12 ( 6ꢀ
DYNAMIC PERFORMANCE
Slew Rate
SR
tS
GBP
φm
13
V/µs
ns
MHz
Degrees
−4 V < VOUT < 4 V, RL = 10 kΩ
To 0.1%, AV = –1, VO = 2 V step
Settling Time
Gain Bandwidth Product
Phase Margin
475
15
64
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
0.5
9.5
0.4
µV p-p
Hz
nV/√
f = 1 kHz
Hz
pA/√
1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125°C, with an LTPD of 1.3.
2 Offset voltage drift is the average of the −40°C to +25°C delta and the +25°C to +125°C delta.
Rev. F | Page 5 of 20
OP162/OP262/OP462
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operation section
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Min
Supply Voltage
Input Voltage1
6 V
6 V
Differential Input Voltage2
Internal Power Dissipation
SOIC (Sꢀ
MSOP (RMꢀ
TSSOP (RUꢀ
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
0.6 V
Observe Derating Curves
Observe Derating Curves
Observe Derating Curves
Observe Derating Curves
–65°C to +150°C
Table 5.
Package Type
1
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
θJC
–40°C to +125°C
–65°C to +150°C
8-Lead SOIC (Sꢀ
157
208
190
105
148
56
8-Lead TSSOP (RUꢀ
8-Lead MSOP (RMꢀ
14-Lead SOIC (Sꢀ
14-Lead TSSOP (RUꢀ
____________________________
Lead Temperature Range
(Soldering, 10 secꢀ
300°C
44
1 For supply voltages greater than 6 V, the input voltage is limited to less than
or equal to the supply voltage.
2 For differential input voltages greater than 0.6 V, the input current should be
limited to less than 5 mA to prevent degradation or destruction of the input
devices.
1 θ is specified for the worst-case conditions, that is, θ is specified for a
JA
JA
device soldered in circuit board for SOIC, MSOP, and TSSOP packages.
ESD CAUTION
ESD (electrostatic dischargeꢀ sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 6 of 20
OP162/OP262/OP462
TYPICAL PERFORMANCE CHARACTERISTICS
250
125
100
75
V
= 5V
S
V
= 5V
S
T
= 25°C
A
200
150
100
COUNT =
720 OP AMPS
50
50
0
25
0
–200
–140
–80
–20
40
100
160
–75
–50
–25
0
25
50
75
100
125 150
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
Figure 7. OP462 Input Offset Voltage Distribution
Figure 10. OP462 Input Offset Voltage vs. Temperature
100
80
0
–100
–200
–300
V
= 5V
S
V
= 5V
= 25°C
S
T
A
COUNT =
360 OP AMPS
60
40
20
0
–400
–500
0.2
0.3
0.5
0.7
0.9
1.1
OS
1.3
1.5
–50
–25
0
25
50
75
100
125
150
INPUT OFFSET DRIFT, TCV (µV,°C)
TEMPERATURE (°C)
Figure 8. OP462 Input Offset Voltage Drift (TCVOS)
Figure 11. OP462 Input Bias Current vs. Temperature
420
15
10
V
= 5V
V
= 5V
S
S
340
260
180
100
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–75
–50
–25
0
25
50
75
100
125 150
COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
Figure 9. OP462 Input Bias Current vs. Common-Mode Voltage
Figure 12. OP462 Input Offset Current vs. Temperature
Rev. F | Page 7 of 20
OP162/OP262/OP462
100
80
5.12
5.06
5.00
4.94
V
= 5V
S
I
= 250µA
OUT
60
V
= 10V
S
V
= 3V
40
S
I
= 5mA
OUT
20
0
4.88
4.82
0
1
2
3
4
5
6
7
–75
–50
–25
0
25
50
75
100
125 150
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 13. OP462 Output High Voltage vs. Temperature
Figure 16. Output Low Voltage to Supply Rail vs. Load Current
1.0
0.9
0.8
0.100
0.080
0.060
0.040
V
= 5V
S
V
= 10V
S
I
= 5mA
OUT
0.7
0.6
0.5
0.4
V
= 5V
S
V
= 3V
S
0.3
0.2
0.1
0
0.020
0.000
I
= 250µA
OUT
–75
–50
–25
0
25
75
100
125
150
–75
–50
–25
0
25
50
75
100
125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Supply Current/Amplifier vs. Temperature
Figure 14. OP462 Output Low Voltage vs. Temperature
100
0.7
0.6
R
= 10kΩ
L
T
= 25°C
A
80
V
= 5V
S
60
40
0.5
0.4
R
= 2kΩ
L
20
0
R
= 600kΩ
L
0
2
4
6
8
10
12
–75
–50
–25
0
25
50
75
100
125 150
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 15. OP462 Open-Loop Gain vs. Temperature
Figure 18. OP462 Supply Current/Amplifier vs. Supply Voltage
Rev. F | Page 8 of 20
OP162/OP262/OP462
50
40
30
20
10
0
4
3
V
T
= 5V
= 25°C
S
A
GAIN
0.1%
0.01%
V
T
= 5V
= 25°C
S
A
45
2
1
90
PHASE
135
180
0
–1
–10
225
270
–2
–3
0.1%
0.01%
–20
–30
–4
100k
1M
10M
FREQUENCY (Hz)
100M
0
200
400
600
800
1000
1000
1k
SETTLING TIME (nS)
Figure 19. Open-Loop Gain and Phase vs. Frequency (No Load)
Figure 22. Step Size vs. Settling Time
60
60
50
40
30
20
V
T
T
= 5V
S
A
A
V
T
R
C
= 5V
S
A
= 25°C
= ±50mV
= 10kΩ
= 25°C
= 830Ω
= 5pF
L
L
40
20
0
R
L
+OS
–OS
–20
–30
10
0
10k
100k
1M
10M
100M
10
100
CAPACITANCE (pF)
FREQUENCY (Hz)
Figure 20. Closed-Loop Gain vs. Frequency
Figure 23. Small-Signal Overshoot vs. Capacitance
5
4
3
2
70
60
50
V
= 5V
= 25°C
S
A
T
40
30
20
V
= 5V
S
A
R
C
= 1
VCL
= 10kΩ
= 15pF
= 25°C
L
L
1
0
10
0
T
A
DISTORTION<1%
10k
100k
FREQUENCY (Hz)
1M
10M
1
10
100
FREQUENCY (Hz)
Figure 21. Maximum Output Swing vs. Frequency
Figure 24. Voltage Noise Density vs. Frequency
Rev. F | Page 9 of 20
OP162/OP262/OP462
7
6
5
90
80
70
60
50
40
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
S
A
S
A
4
3
2
+PSRR
–PSRR
1
0
30
20
1
10
100
FREQUENCY (Hz)
1k
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 25. Current Noise Density vs. Frequency
Figure 28. PSRR vs. Frequency
300
250
200
20mV
2s
V
T
= 5V
= 25°C
S
A
100
90
150
100
A
= 10
VCL
10
0%
A
= 1
VCL
V = 5V
S
ꢀ
A
= 100kΩ
50
0
V
en = 0.5µV p-p
100k
1M
FREQUENCY (Hz)
10M
Figure 26. Output Impedance vs. Frequency
Figure 29. 0.1 Hz to 10 Hz Noise
90
V
= 5V
= 25°C
2V
S
V
V
A
= 12V p-p
= ±5V
= 1
IN
T
80
70
60
50
40
A
S
100
V
90
10
0%
30
20
2V
20µs
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 27. CMRR vs. Frequency
Figure 30. No Phase Reversal (VIN = 12 V p-p, VS = 5 V, AV = 1)
Rev. F | Page 10 of 20
OP162/OP262/OP462
V
= 5V
S
A
T
= 1
= 25°C
= 100pF
V
A
V
= 5V
= 1
= 25°C
= 100pF
S
100
90
A
T
100
90
V
C
L
A
C
L
10
10
0%
0%
500mV
100µs
20mV
200ns
Figure 31. Small Signal Transient Response
Figure 32. Large Signal Transient Response
Rev. F | Page 11 of 20
OP162/OP262/OP462
APPLICATIONS
FUNCTIONAL DESCRIPTION
OFFSET ADJUSTMENT
The OPx62 family is fabricated using Analog Devices’ high
speed complementary bipolar process, also called XFCB. This
process trench isolates each transistor to lower parasitic capaci-
tances for high speed performance. This high speed process has
been implemented without sacrificing the excellent transistor
matching and overall dc performance characteristic of Analog
Devices’ complementary bipolar process. This makes the OPx62
family an excellent choice as an extremely fast and accurate low
voltage op amp.
Because the OP162/OP262/OP462 have an exceptionally low
typical offset voltage, adjustment to correct offset voltage may
not be needed. However, the OP162 has pinouts to attach a
nulling resistor. Figure 34 shows how the OP162 offset voltage
can be adjusted by connecting a potentiometer between Pin 1
and Pin 8, and connecting the wiper to VCC. It is important to
avoid accidentally connecting the wiper to VEE, as this can damage
the device. The recommended value for the potentiometer is
20 kΩ.
+5V
Figure 33 shows a simplified equivalent schematic for the OP162.
A PNP differential pair is used at the input of the device. The
cross connecting of the emitters lowers the transconductance of
the input stage improving the slew rate of the device. Lowering
the transconductance through cross connecting the emitters has
another advantage in that it provides a lower noise factor than if
emitter degeneration resistors were used. The input stage can
function with the base voltages taken all the way to the negative
power supply, or up to within 1 V of the positive power supply.
20kΩ
1
8
3
2
7
4
6
OP162
V
OS
–5V
Figure 34. Offset Adjustment Schematic
V
CC
RAIL-TO-RAIL OUTPUT
The OP162/OP262/OP462 have a wide output voltage range
that extends to within 60 mV of each supply rail with a load
current of 5 mA. Decreasing the load current extends the output
voltage range even closer to the supply rails. The common-mode
input range extends from ground to within 1 V of the positive
supply. It is recommended that there be some minimal amount
of gain when a rail-to-rail output swing is desired. The minimum
gain required is based on the supply voltage and can be found as
+IN
–IN
V
OUT
VS
VS −1
AV,min
=
where VS is the positive supply voltage. With a single-supply
voltage of 5 V, the minimum gain to achieve rail-to-rail output
should be 1.25.
V
EE
Figure 33. Simplified Schematic
Two complementary transistors in a common-emitter
configuration are used for the output stage. This allows the
output of the device to swing to within 50 mV of either supply
OUTPUT SHORT-CIRCUIT PROTECTION
To achieve a wide bandwidth and high slew rate, the output of
the OP162/OP262/OP462 are not short-circuit protected. Shorting
the output directly to ground or to a supply rail may destroy the
device. The typical maximum safe output current is 30 mA.
Steps should be taken to ensure the output of the device will not
be forced to source or sink more than 30 mA.
rail at load currents less than 1 mA. As load current increases,
the maximum voltage swing of the output decreases. This is due
to the collector-to-emitter saturation voltages of the output
transistors increasing. The gain of the output stage, and conse-
quently the open-loop gain of the amplifier, is dependent on the
load resistance connected at the output. Because the dominant pole
frequency is inversely proportional to the open-loop gain, the
unity-gain bandwidth of the device is not affected by the load
resistance. This is typically the case in rail-to-rail output
devices.
In applications where some output current protection is needed,
but not at the expense of reduced output voltage headroom, a
low value resistor in series with the output can be used. This is
shown in Figure 35. The resistor is connected within the feed-
back loop of the amplifier so that if VOUT is shorted to ground
Rev. F | Page 12 of 20
OP162/OP262/OP462
To calculate the internal junction temperature of the OPx62, use
the formula
and VIN swings up to 5 V, the output current will not exceed
30 mA. For single 5 V supply applications, resistors less than
169 Ω are not recommended.
TJ = PDISS × θJA + TA
5V
where:
TJ is the OPx62 junction temperature.
V
IN
P
DISS is the OPx62 power dissipation.
169Ω
OPx62
V
OUT
θJA is the OPx62 package thermal resistance, junction-to-
ambient temperature.
TA is the ambient temperature of the circuit.
The power dissipated by the device can be calculated as
Figure 35. Output Short-Circuit Protection
PDISS = ILOAD × (VS – VOUT
)
INPUT OVERVOLTAGE PROTECTION
where:
The input voltage should be limited to 6 V, or damage to the
device can occur. Electrostatic protection diodes placed in the
input stage of the device help protect the amplifier from static
discharge. Diodes are connected between each input as well as
from each input to both supply pins as shown in the simplified
equivalent circuit in Figure 33. If an input voltage exceeds either
supply voltage by more than 0.6 V, or if the differential input
voltage is greater than 0.6 V, these diodes energize causing
overvoltage damage.
I
LOAD is the OPx62 output load current.
VS is the OPx62 supply voltage.
OUT is the OPx62 output voltage.
V
Figure 36 and Figure 37 provide a convenient way to determine
if the device is being overheated. The maximum safe power
dissipation can be found graphically, based on the package type
and the ambient temperature around the package. By using the
previous equation, it is a simple matter to see if PDISS exceeds the
device’s power derating curve. To ensure proper operation, it is
important to observe the recommended derating curves shown
in Figure 36 and Figure 37.
The input current should be limited to less than 5 mA to
prevent degradation or destruction of the device by placing an
external resistor in series with the input at risk of being overdriven.
The size of the resistor can be calculated by dividing the maxi-
mum input voltage by 5 mA. For example, if the differential
input voltage could reach 5 V, the external resistor should be
5 V/5 mA = 1 kΩ. In practice, this resistor should be placed in
series with both inputs to balance any offset voltages created by
the input bias current.
0.9
0.8
0.7
8-LEAD SOIC
0.6
0.5
8-LEAD MSOP
OUTPUT PHASE REVERSAL
0.4
8-LEAD TSSOP
0.3
The OP162/OP262/OP462 are immune to phase reversal as
long as the input voltage is limited to 6 V. Figure 30 shows the
output of a device with the input voltage driven beyond the
supply voltages. Although the device’s output does not change
phase, large currents due to input overvoltage could result,
damaging the device. In applications where the possibility of an
input voltage exceeding the supply voltage exists, overvoltage
protection should be used, as described in the previous section.
0.2
0.1
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 36. Maximum Power Dissipation vs. Temperature for
8-Lead Package Types
POWER DISSIPATION
The maximum power that can be safely dissipated by the
OP162/OP262/OP462 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
is 150°C; device performance suffers when this limit is
exceeded. If this maximum is only momentarily exceeded,
proper circuit operation will be restored as soon as the die
temperature is reduced. Leaving the device in an “overheated”
condition for an extended period can result in permanent
damage to the device.
Rev. F | Page 13 of 20
OP162/OP262/OP462
1.2
1.1
1.0
1
0 TO +5V
SQUARE
14-LEAD SOIC
0.9
0.8
OP462
V
OUT
10KΩ
0.7
0.6
0.5
0.4
14-LEAD TSSOP
Figure 39. Test Circuit for Power-On Settling Time
0.3
0.2
CAPACITIVE LOAD DRIVE
0.1
0
The OP162/OP262/OP462 are high speed, extremely accurate
devices that tolerate some capacitive loading at their outputs. As
load capacitance increases, unity-gain bandwidth of an OPx62
device decreases. This also causes an increase in overshoot and
settling time for the output. Figure 41 shows an example of this
with the device configured for unity gain and driving a 10 kΩ
resistor and 300 pF capacitor placed in parallel.
20
45
70
95
120
AMBIENT TEMPERATURE (°C)
Figure 37. Maximum Power Dissipation vs. Temperature for
14-Lead Package Types
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in a dual or a
quad package be configured as a unity-gain follower with a
1 kΩ feedback resistor connected from the inverting input to
the output, and the noninverting input tied to the ground plane.
By connecting a series R-C network, commonly called a
“snubber” network, from the output of the device to ground,
this ringing can be eliminated and overshoot can be
significantly reduced. Figure 40 shows how to set up the
snubber network, and Figure 42 shows the improvement in
output response with the network added.
POWER-ON SETTLING TIME
The time it takes for the output of an op amp to settle after a
supply voltage is delivered can be an important consideration in
some power-up-sensitive applications. An example of this
would be in an A/D converter where the time until valid data
can be produced after power-up is important.
5V
OPx62
V
OUT
C
V
R
L
IN
X
The OPx62 family has a rapid settling time after power-up.
Figure 38 shows the OP462 output settling times for a single-
supply voltage of VS = +5 V. The test circuit in Figure 39 was
used to find the power-on settling times for the device.
C
X
Figure 40. Snubber Network Compensation for Capacitive Loads
V
= 5V
= 1
= 300pF
= 10k
S
2V
500ns
A
C
R
V
L
L
100
90
100
90
Ω
V
A
R
= 5V
= 1
= 10kΩ
S
V
L
10
10
0%
0%
50mV
1µs
50mV
Figure 41. A Photo of a Ringing Square Wave
Figure 38. Oscilloscope Photo of VS and VOUT
Rev. F | Page 14 of 20
OP162/OP262/OP462
Figure 45 shows the worst case crosstalk between two amplifiers
in the OP462. A 1 V rms signal is applied to one amplifier while
measuring the output of an adjacent amplifier. Both amplifiers
are configured for unity gain and supplied with 2.5 V.
V
= 5V
= 1
= 300pF
= 10k
S
A
C
R
V
L
L
100
90
Ω
WITH SNUBBER:
R
C
= 140Ω
= 10nF
0.010
X
X
V
A
= ±2.5V
= 1
S
V
V
R
= 1.0V rms
= 10kΩ
IN
L
BANDWIDTH:
<10Hz TO 22kHz
10
0%
0.001
µ
1ꢁs
50mV
Figure 42. A Photo of a Nice Square Wave at the Output
The network operates in parallel with the load capacitor, CL,
and provides compensation for the added phase lag. The actual
values of the network resistor and capacitor are empirically
determined to minimize overshoot and maximize unity-gain
bandwidth. Table 6 shows a few sample snubber networks for
large load capacitors.
0.0001
20
100
1k
10k 20k
FREQUENCY (Hz)
Figure 44. THD + N vs. Frequency
–40
–50
A
= 1
= 1.0V rms
(0dBV)
= 10kΩ
= ±2.5V
Table 6. Snubber Networks for Large Capacitive Loads
V
V
IN
CLOAD
RX
CX
–60
R
L
S
< 300 pF
500 pF
1 nF
140 Ω
100 Ω
80 Ω
10 Ω
10 nF
10 nF
10 nF
47 nF
V
–70
–80
–90
10 nF
–100
–110
–120
Higher load capacitance will reduce the unity-gain bandwidth
of the device. Figure 43 shows unity-gain bandwidth vs.
capacitive load. The snubber network does not provide any
increase in bandwidth, but it substantially reduces ringing and
overshoot, as shown between Figure 41 and Figure 42.
–130
–140
20
100
1k
10k 20k
10
FREQUENCY (Hz)
9
Figure 45. Crosstalk vs. Frequency
8
PCB LAYOUT CONSIDERATIONS
7
Because the OP162/OP262/OP462 can provide gains at high
frequency, careful attention to board layout and component
selection is recommended. As with any high speed application,
a good ground plane is essential to achieve the optimum
performance. This can significantly reduce the undesirable
effects of ground loops and I × R losses by providing a low
impedance reference point. Best results are obtained with a
multilayer board design with one layer assigned to ground
plane.
6
5
4
3
2
1
0
10pF
100pF
1nF
10nF
C
LOAD
Use chip capacitors for supply bypassing, with one end of the
capacitor connected to the ground plane and the other end
connected within 1/8 inch of each power pin. An additional
large tantalum electrolytic capacitor (4.7 µF to 10 µF) should be
connected in parallel. This capacitor provides current for fast,
large-signal changes at the device’s output; therefore, it does not
need to be placed as close to the supply pins.
Figure 43. Unity-Gain Bandwidth vs. CLOAD
TOTAL HARMONIC DISTORTION AND CROSSTALK
The OPx62 device family offers low total harmonic distortion
making it an excellent choice for audio applications. Figure 44
shows a graph of THD plus noise figures at 0.001% for the
OP462.
Rev. F | Page 15 of 20
OP162/OP262/OP462
APPLICATION CIRCUITS
SINGLE-SUPPLY STEREO HEADPHONE DRIVER
INSTRUMENTATION AMPLIFIER
Figure 46 shows a stereo headphone output amplifier that can
operate from a single 5 V supply. The reference voltage is
derived by dividing the supply voltage down with two 100 kΩ
resistors. A 10 µF capacitor prevents power supply noise from
contaminating the audio signal and establishes an ac ground for
the volume control potentiometers.
Because of their high speed, low offset voltages, and low noise
characteristics, the OP162/OP262/OP462 can be used in a wide
variety of high speed applications, including precision instru-
mentation amplifiers. Figure 47 shows an example of such an
application.
–V
IN
OP462-A
The audio signal is ac-coupled to each noninverting input
through a 10 µF capacitor. The gain of the amplifier is con-
trolled by the feedback resistors and is (R2/R1) + 1. For this
example, the gain is 6. By removing R1, the amplifier would
have unity gain. To short-circuit protect the output of the
device, a 169 Ω resistor is placed at the output in the feedback
network. This prevents any damage to the device if the head-
phone output becomes shorted. A 270 µF capacitor is used at
the output to couple the amplifier to the headphone. This value
is much larger than that used for the input because of the low
impedance of headphones, which can range from 32 Ω to 600 Ω
or more.
2kΩ
1kΩ
2kΩ
10kΩ
2kΩ
OP462-D
OP462-C
OUTPUT
R
G
1kΩ
1.9kΩ
10kΩ
OP462-B
200Ω
10 TURN
(OPTIONAL)
+V
IN
Figure 47. High Speed Instrumentation Amplifier
The differential gain of the circuit is determined by RG, where
R1 = 10kΩ
R2 = 50kΩ
10µF
5V
2
ADIFF = 1+
RG
LEFT IN
10µF
270µF
47kΩ
L VOLUME
CONTROL
169Ω
HEADPHONE
LEFT
OP262-A
with the RG resistor value in kΩ. Removing RG sets the circuit
gain to unity.
10kΩ
5V
100kΩ
100kΩ
10µF
The fourth op amp, OP462-D, is optional and is used to
improve CMRR by reducing any input capacitance to the
amplifier. By shielding the input signal leads and driving the
shield with the common-mode voltage, input capacitance is
eliminated at common-mode voltages. This voltage is derived
from the midpoint of the outputs of OP462-A and OP462-B by
using two 10 kΩ resistors followed by OP462-D as a unity-gain
buffer.
5V
10kΩ
10µF
270µF
47kΩ
169Ω
HEADPHONE
RIGHT
OP262-B
R VOLUME
CONTROL
RIGHT IN
R2 = 50kΩ
R1 = 10kΩ
It is important to use 1% or better tolerance components for the
2 kΩ resistors, as the common-mode rejection is dependent on
their ratios being exact. A potentiometer should also be connected
in series with the OP462-C noninverting input resistor to ground
to optimize common-mode rejection.
10µF
Figure 46. Headphone Output Amplifier
The circuit in Figure 47 was implemented to test its settling
time. The instrumentation amp was powered with −5 V, so the
input step voltage went from −5 V to +4 V to keep the OP462
within its input range. Therefore, the 0.05% settling range is
when the output is within 4.5 mV. Figure 48 shows the positive
slope settling time to be 1.8 µs, and Figure 49 shows a settling
time of 3.9 µs for the negative slope.
Rev. F | Page 16 of 20
OP162/OP262/OP462
DIRECT ACCESS ARRANGEMENT
5mV
2V
Figure 50 shows a schematic for a 5 V single-supply transmit/
receive telephone line interface for 600 Ω transmission systems.
It allows full-duplex transmission of signals on a transformer-
coupled 600 Ω line. Amplifier A1 provides gain that can be
adjusted to meet the modem output drive requirements. Both
A1 and A2 are configured to apply the largest possible differential
signal to the transformer. The largest signal available on a single
5 V supply is approximately 4.0 V p-p into a 600 Ω transmission
system. Amplifier A3 is configured as a difference amplifier to
extract the receive information from the transmission line for
amplification by A4. A3 also prevents the transmit signal from
interfering with the receive signal. The gain of A4 can be adjusted
in the same manner as A1 to meet the modem’s input signal
requirements. Standard resistor values permit the use of SIP
(single in-line package) format resistor arrays. Couple this with
the OP462 14-lead SOIC or TSSOP package and this circuit
offers a compact solution.
100
90
10
0%
1µs
Figure 48. Positive Slope Settling Time
5
mV
2V
100
90
P1
TX GAIN
ADJUST
R2
9.09kΩ
C1
0.1µF
TRANSMIT
TXA
R1
10kΩ
TO TELEPHONE
LINE
2k
ꢀ
R3
360Ω
2
10
1
1:1
A1
3
0%
R5
10kΩ
6.2V
6.2V
Z
600Ω
O
1µs
5V DC
T1
R6
10kΩ
6
5
R7
10kΩ
Figure 49. Negative Slope Settling Time
MIDCOM
671-8005
7
A2
R8
10kΩ
10µF
R9
10kΩ
R10
10kΩ
P2
RX GAIN
ADJUST
RECEIVE
RXA
R14
14.3kΩ
R13
10kΩ
2
3
R11
10kΩ
1
A3
2kΩ
C2
0.1µF
6
R12
10kΩ
7
A4
5
A1, A2 = 1/2 AD8532
A3, A4 = 1/2 AD8532
Figure 50. Single-Supply Direct Access Arrangement for Modems
Rev. F | Page 17 of 20
OP162/OP262/OP462
SPICE MACRO-MODEL
* OP162/OP262/OP462 SPICE Macro-model
* 7/96, Ver. 1
ECM 13 98 POLY (2) (1, 98) (2, 98) 0 0.5 0.5
R2 13 14 1E+6
* Troy Murphy / ADSC
*
R3 14 98 70
C3 13 14 80E-12
* Copyright 1996 by Analog Devices
*
*
* POLE AT 1.5MHz, ZERO AT 3MHz
*
*
*
Refer to “README.DOC” file for License Statement. Use of this model
indicates your acceptance of the terms and provisions in the License G2 21 98 (10, 98) .588E-6
* Statement
*
R4 21 98 1.7E6
R5 21 22 1.7E6
* Node Assignments
C4 22 98 31.21E-15
*
* POLE AT 6MHz, ZERO AT 3MHz
*
E1 23 98 (21, 98) 2
R6 23 24 53E+3
R7 24 98 53E+3
C5 23 24 1E-12
*
*
*
*
*
*
*
noninverting input
|
|
|
|
|
|
inverting input
|
|
|
|
|
2
positive supply
|
|
|
|
99
negative supply
|
|
output
|
|
50
|
45
.SUBCKT OP162 1
*
*
* SECOND GAIN STAGE
*
G3 25 98 (24, 98) 40E-6
*INPUT STAGE
*
Q1
Q2
Ios 1
5
6
7
2
2
3
4
PIX 5
PIX 5
R8 25 98 1.65E+6
D3 25 99 DX
D4 50 25 DX
1.25E-9
I1 99 15 85E-6
*
EOS 7 POLY(1) (14, 20) 45E-6 1
1
* OUTPUT STAGE
RC1 5 50 3.035E+3
RC2 6 50 3.035E+3
RE1 3 15 607
*
GSY 99 50 POLY (1) (99, 50) 277.5E-6 7.5E-6
R9 99 20 100E3
R10 20 50 100E3
RE2 4 15 607
C1
D1
D2
5
3
4
6
8
9
600E-15
DX
DX
Q3 45 41 99 POUT 4
Q4 45 43 50 NOUT 2
EB1 99 40 POLY (1) (98, 25) 0.70366 1
EB2 42 50 POLY (1) (25, 98) 0.73419 1
V1 99 8 DC 1
V2 99 9 DC 1
*
RB1 40 41 500
RB2 42 43 500
* 1st GAIN STAGE
*
CF 45 25 11E-12
D5 46 99 DX
EREF 98 0 (20, 0) 1
G1
R1
C2
*
98 10 (5, 6) 10.5
10 98 1
10 98 3.3E-9
* COMMON-MODE STAGE WITH ZERO AT 4kHz
*
.MODEL POUT PNP (BF=119, IS=2.782E-17, VAF=28, KF=3E-7)
.MODEL NOUT NPN (BF=110, IS=1.786E-17, VAF=90, KF=3E-7)
.MODEL DX
.ENDS
D()
Rev. F | Page 18 of 20
OP162/OP262/OP462
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5.10
5.00
4.90
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
14
8
7
4.50
4.40
4.30
6.40
BSC
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
1
0.25 (0.0098)
0.10 (0.0040)
PIN 1
8°
0.51 (0.0201)
0.31 (0.0122)
0.65
BSC
1.05
1.00
0.80
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
0.20
0.09
1.20
MAX
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MS-012AA
0.15
0.05
0.30
0.19
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 51. 8-Lead Standard Small Outline Package [SOIC] Narrow Body
S-Suffix (R-8)
Figure 54. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters and (inches)
Dimensions shown in millimeters
3.00
BSC
8.75 (0.3445)
8.55 (0.3366)
14
1
8
7
8
1
5
4
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
4.90
BSC
3.00
BSC
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
× 45°
PIN 1
0.25 (0.0098)
0.10 (0.0039)
0.65 BSC
8°
0°
1.10 MAX
0.51 (0.0201)
0.31 (0.0122)
0.15
0.00
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
0.80
0.60
0.40
8°
0°
0.38
0.22
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 52. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Figure 55. 14-Lead Standard Small Outline Package [SOIC] Narrow Body
S-Suffix (R-14)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
3.10
3.00
2.90
8
5
4
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65 BSC
0.15
0.05
1.20
MAX
8°
0°
0.30
0.19
0.75
0.60
0.45
SEATING
PLANE
COPLANARITY
0.10
0.20
0.09
COMPLIANT TO JEDEC STANDARDS MO-153AA
Figure 53. 8-Lead Thin Shrink Small Outline Package [TSSOP)
(RU-8)
Dimensions shown in millimeters
Rev. F | Page 19 of 20
OP162/OP262/OP462
ORDERING GUIDE
Model
OP162GS
OP162GS-REEL
OP162GS-REEL7
OP162GSZ1
OP162GSZ-REEL1
OP162GSZ-REEL71
OP162DRU-REEL
OP162DRUZ-REEL1
OP162HRU-REEL
OP162HRUZ-REEL1
OP162DRM-REEL
OP162DRMZ-REEL1
OP262DRU-REEL
OP262DRUZ-REEL1
OP262GS
Temperature Range
Package Description
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
Package Option
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
RU-8
RU-8
RU-8
RU-8
RM-8
Branding
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead SOIC
8-Lead SOIC
8-Lead TSSOP
8-Lead TSSOP
8-Lead TSSOP
8-Lead TSSOP
8-Lead MSOP
8-Lead MSOP
8-Lead TSSOP
8-Lead TSSOP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
AND
AOJ
RM-8
RU-8
RU-8
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
S-Suffix (R-8ꢀ
RU-8
OP262GS-REEL
OP262GS-REEL7
OP262GSZ1
OP262GSZ-REEL1
OP262GSZ-REEL71
OP262HRU-REEL
OP262HRUZ-REEL1
OP462DRU-REEL
OP462DRUZ-REEL1
OP462DS
OP462DS-REEL
OP462DS-REEL7
OP462DSZ1
OP462DSZ-REEL1
OP462DSZ-REEL71
OP462GS
OP462GS-REEL
OP462GS-REEL7
OP462GSZ1
OP462GSZ-REEL1
OP462GSZ-REEL71
OP462HRU-REEL
OP462HRUZ-REEL1
8-Lead SOIC
8-Lead TSSOP
8-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead TSSOP
14-Lead TSSOP
RU-8
RU-14
RU-14
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
S-Suffix (R-14ꢀ
RU-14
RU-14
1
Z = Pb-free part.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00288–0–1/05(F)
Rev. F | Page 20 of 20
相关型号：
OP262GSZ-REEL7
DUAL OP-AMP, 800 uV OFFSET-MAX, 15 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8
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OP262HRUZ
DUAL OP-AMP, 1000 uV OFFSET-MAX, 15 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, TSSOP-8
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OP262HRUZ-REEL
DUAL OP-AMP, 1000 uV OFFSET-MAX, 15 MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MS-153AA, TSSOP-8
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