OP270GP_技术文档

Dual Very Low Noise Precision

Operational Amplifier

a

OP270

CONNECTION DIAGRAMS

FEATURES

Very Low Noise 5 nV/÷Hz @ 1 kHz Max

Excellent Input Offset Voltage 75 ␮V Max

Low Offset Voltage Drift 1 ␮V/؇C Max

Very High Gain 1500 V/mV Min

Outstanding CMR 106 dB Min

Slew Rate 2.4 V/␮s Typ

16-Lead SOIC

(S-Suffix)

8-Lead PDIP (P-Suffix)

8-Lead CERDIP

(Z-Suffix)

16

15

14

13

1

2

3

4

5

6

7

8

–IN A

+IN A

NC

OUT A

NC

8

7

6

5

1

2

3

4

OUT A

–IN A

+IN A

V–

V+

NC

Gain Bandwidth Product 5 MHz Typ

Industry-Standard 8-Lead Dual Pinout

OUT B

–IN B

+IN B

A

B

V–

V+

OP270

NC

12 NC

GENERAL DESCRIPTION

OP270

11

10

9

+IN B

–IN B

NC

The OP270 is a high performance, monolithic, dual operational

amplifier with exceptionally low voltage noise, 5 nV/÷Hz max at

1 kHz. It offers comparable performance to ADI’s industry

standard OP27.

OUT B

NC

NC = NO CONNECT

The OP270 features an input offset voltage below 75 mV and an

offset drift under 1 mV/∞C, guaranteed over the full military tem-

perature range. Open-loop gain of the OP270 is over 1,500,000

into a 10 kW load, ensuring excellent gain accuracy and linearity,

even in high gain applications. Input bias current is under 20 nA,

which reduces errors due to signal source resistance. The OP270’s

CMR of over 106 dB and PSRR of less than 3.2 mV/V signifi-

cantly reduce errors due to ground noise and power supply

fluctuations. Power consumption of the dual OP270 is one-third

less than two OP27s, a significant advantage for power conscious

applications. The OP270 is unity-gain stable with a gain bandwidth

product of 5 MHz and a slew rate of 2.4 V/ms.

The OP270 offers excellent amplifier matching, which is important

for applications such as multiple gain blocks, low noise instru-

mentation amplifiers, dual buffers, and low noise active filters.

The OP270 conforms to the industry-standard 8-lead DIP pinout.

It is pin compatible with the MC1458, SE5532/A, RM4558, and

HA5102 dual op amps, and can be used to upgrade systems

using those devices.

For higher speed applications, the OP271, with a slew rate of

8 V/ms, is recommended. For a quad op amp, see the OP470.

SIMPLIFIED SCHEMATIC

(One of Two Amplifiers Is Shown)

V+

BIAS

OUT

+IN

–IN

V–

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(V = ؎15 V, T = 25؇C, unless otherwise noted.)

OP270–SPECIFICATIONS

S

A

OP270E

OP270F

OP270G

PARAMETER

SYMBOL CONDITIONS

MIN TYP MAX

MIN TYP MAX MIN TYP MAX UNIT

Input Offset Voltage

Input Offset Current

Input Bias Current

Input Noise Voltage

V_OS

l_OS

I_B

e_np-p

10 75

20

3

10

80

150

15

40

50

5

15

80

250

20

60

mV

V_CM= 0 V

0.1 Hz to 10 Hz

(Note 1)

1

5

10

20

nA

nV p-p

80 200

200

Input Noise

Voltage Density

f_O= 10 Hz

f_O= 100 Hz

f_O= 1 kHz

(Note 2)

f_O= 10 Hz

f_O= 100 Hz

f_O= 1 kHz

V_O= ±10 V

R_L= 10 kW

R_L= 2 kW

(Note3)

3.6 6.5

3.2 5.5

3.2 5.0

3.6

3.2

6.5

5.5

5.0

3.6

3.2

nV/÷Hz

e_n

i_n

Input Noise

Current Density

1.1

0.7

0.6

1.1

0.7

0.6

1.1

0.7

0.6

pA/÷Hz

Large-Signal

Voltage Gain

A_VO

IVR

1500 2300

1000 1700

500 900

±12 ±12.5

±12 ±13.5

750

350

±12

1500

700

±12.5

±13.5

V/mV

V

750 1200

±12 ±12.5

±12 ±13.5

Input Voltage Range

Output Voltage Swing V_O

Common-Mode

R_L≥ 2 kW

V

Rejection

Power Supply

Rejection Ratio

CMR

V_CM= ±11 V

106 125

100 120

1.0

90

110

1.5

dB

PSRR

V_S= ±4.5 V

to ±18 V

0.56 3.2

5.6

6.5

6

mV/V

Slew Rate

SR

I_SY

1.7 2.4

4

1.7

2.4

4

1.7

2.4

4

V/ms

mA

Supply Current

(All Amplifiers)

Gain Bandwidth

Product

No Load

6.5

GBP

CS

5

MHz

dB

Channel Separation

V_O= ±20 V p-p

f_O= 10 Hz

(Note 1)

125 175

175

Input Capacitance

Input Resistance

Differential-Mode

Input Resistance

Common-Mode

Settling Time

C_IN

R_IN

3

0.4

3

0.4

3

0.4

pF

MW

R_INCM

t_S

20

5

20

5

20

5

GW

ms

A_V= +1, 10 V

Step to 0.01%

NOTES

1. Guaranteed but not 100% tested.

2. Sample tested.

3. Guaranteed by CMR test.

Specifications subject to change without notice.

–2–

REV. C

OP270

SPECIFICATIONS

(Vs = ؎15 V, –40∞C £ T_A£ 85؇C, unless otherwise noted.)

ELECTRICAL SPECIFICATIONS

OP270E

OP270F

OP270G

PARAMETER

SYMBOL CONDITIONS

V_OS

MIN TYP MAX

MIN TYP MAX MIN TYP MAX UNIT

Input Offset Voltage

Average Input

25 150

45

275

100 400

mV

Offset Voltage Drift TCV_OS

0.2

1.5 30

6

1

0.4

5

15

2

40

70

0.7

15

19

3

50

80

mV/∞C

nA

Input Offset Current

Input Bias Voltage

Large-Signal

I_OS

I_B

V_CM= 0 V

V_O= ±10 V

R_L= 10 kW

R_L= 2 kW

60

Voltage Gain

A_VO

1000 1800

500 900

±12 ±12.5

±12 ±13.5

600 1400

300 700

±12 ±12.5

±12 ±13.5

400

225

±12

1250

670

±12.5

±13.5

V/mV

V

Input Voltage Range* IVR

Output Voltage Swing V_O

Common-Mode

R_L≥ 2 kW

V

Rejection

Power Supply

Rejection Ratio

CMR

V_CM= ±11 V

100 120

94

115

1.8

4.4

90

100

2.0

4.4

dB

PSRR

I_SY

V_S= ±4.5 V

to ±18 V

No Load

0.7 5.6

4.4 7.2

10

1.5

7.2

mV/V

mA

Supply Current

(All Amplifiers)

7.2

* Guaranteed by CMR test.

Specifications subject to change without notice.

–3–

REV. C

OP270

ABSOLUTE MAXIMUM RATINGS¹

Operating Temperature Range

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Differential Input Voltage². . . . . . . . . . . . . . . . . . . . . . 1.0 V

Differential Input Current². . . . . . . . . . . . . . . . . . . . 25 mA

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage

Output Short-Circuit Duration . . . . . . . . . . . . . . .Continuous

Storage Temperature Range

P, S, Z Package . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C

Junction Temperature (T_J) . . . . . . . . . . . . . –65°C to +150°C

OP270E, OP270F, OP270G . . . . . . . . . . . –40°C to +85°C

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²The OP270’s inputs are protected by back-to-back diodes. Current limiting

resistors are not used, in order to achieve low noise performance. If differential

voltage exceeds +10 V, the input current should be limited to 25 mA.

ORDERING GUIDE

T_A= +25°C

V_OSMax

(␮V)

θ_JC

C/W)

θ_JA

*

Temperature

Range

Package

Description

Package

Option

Model

(

°

(

°

C/W)

OP270EZ

OP270FZ

OP270GP

OP270GS

75

12

37

27

134

96

XIND

8-Lead CERDIP Q-8 (Z-Suffix)

150

250

8-Lead PDIP

N-8 (P-Suffix)

RW-16 (S-Suffix)

92

16-Lead SOIC

*θ_JAis specified for worst-case mounting conditions, i.e., θ_JAis specified for device

in socket for CERDIP and PDIP packages; θ_JAis specified for device soldered to

printed circuit board for SOIC package.

For military processed devices, please refer to the Standard

Microcircuit Drawing (SMD) available at

www.dscc.dla.mil/programs/milspec/default.asp.

SMD Part Number

ADI Equivalent

5962-8872101PA

OP270AZMDA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the OP270 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. C

OP270

Typical Performance Characteristics–

10

9

5

4

3

2

1

0.1HzTO 10Hz NOISE

T

= 25؇C

= ؎15V

A

S

T

= 25؇C

A

V

8

7

6

5

4

AT 10Hz

AT 1kHz

3

2

1/f CORNER = 5Hz

1

10

100

1k

0

؎5

؎10

؎15

؎20

TIME (1sec/DIV)

T

= 25؇C

= ؎15V

A

S

SUPPLYVOLTAGE (V)

FREQUENCY (Hz)

V

TPC 2. Voltage Noise Density

vs. Supply Voltage

TPC 1. Voltage Noise Density

vs. Frequency

TPC 3. 0.1 Hz to 10 Hz Input

Voltage Noise

5

40

10

T

V

= 25؇C

= ؎15V

A

V

= ؎15V

T

= 25؇C

S

A

S

V

= ؎15V

30

20

S

4

3

2

1

0

10

1.0

0.1

0

–10

–20

–30

1/f CORNER = 200Hz

0

1

2

3

4

5

–75 –50 –25

0

25

50

75 100 125

10

100

1k

10k

TIME (Minutes)

TEMPERATURE (؇C)

FREQUENCY (Hz)

TPC 4. Current Noise Density

vs. Frequency

TPC 6. Warm-Up Offset Voltage

Drift

TPC 5. Input Offset Voltage vs.

Temperature

7

5

7

V

= ؎15V

V

= ؎15V

S

= 0V

T

V

= 25؇C

= ؎15V

S

A

= 0V

V

CM

S

6

5

4

3

2

4

3

2

1

0

6

5

4

3

2

–75 –50 –25

0

25

50

75 100 125

–75 –50 –25

0

25

50

75 100 125

–10.0

–12.5

–5.0

0.0

5.0

10.0

–7.5

–2.5

2.5

7.5

12.5

TEMPERATURE (؇C)

COMMON-MODEVOLTAGE (V)

TPC 9. Input Bias Current vs.

Common-Mode Voltage

TPC 7. Input Bias Current vs.

Temperature

TPC 8. Input Offset Current vs.

Temperature

–5–

REV. C

OP270

130

120

110

100

90

6

5

4

3

2

8

7

6

5

4

3

2

1

0

T

V

= 25؇C

= ؎15V

A

V

= ؎15V

S

80

70

+125؇C

+25؇C

–55؇C

60

50

40

30

20

10

1

10

100

1k

10k

100k

1M

0

؎5

؎10

؎15

؎20

–75 –50 –25

0

25

50

75 100 125

FREQUENCY (Hz)

SUPPLYVOLTAGE (V)

TEMPERATURE (؇C)

TPC 10. CMR vs. Frequency

TPC 11. Total Supply Current

vs. Supply Voltage

TPC 12. Total Supply Current

vs. Temperature

140

120

100

80

140

T

V

= 25؇C

= ؎15V

T

V

= 25؇C

= ؎15V

S

T

= 25؇C

A

S

120

100

80

60

40

20

0

60

40

20

0

–PSR

60

+PSR

40

20

0

–20

1

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

1k

10k

100k

FREQUENCY (Hz)

1M

10M

1

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

TPC 13. PSR vs. Frequency

TPC 14. Open-Loop Gain vs.

Frequency

TPC 15. Closed-Loop Gain vs.

Frequency

25

80

5000

4000

3000

2000

1000

0

80

70

T

V

= 25؇C

= ؎15V

A

8

7

6

5

4

S

20

15

10

5

100

120

140

160

180

PHASE

GAIN

⌽

PHASE

MARGIN = 62؇

60

0

GBP

50

–5

–10

40

1

2

3

4

5

6 7 8 910

–75 –50 –25

0

25 50 75 100 125 150

0

؎5

؎10

؎15

؎20

؎25

FREQUENCY (Hz)

TEMPERATURE ( C)

؇

SUPPLY VOLTAGE (V)

TPC 16. Open-Loop Gain Phase

Shift vs. Frequency

TPC 17. Open-Loop Gain vs.

Supply Voltage

TPC 18. Gain-Bandwidth Phase

Margin vs. Temperature

–6–

REV. C

OP270

28

24

20

16

12

8

15

14

13

12

11

10

9

50

40

30

20

10

0

T

= 25؇C

T

= 25؇C

= ؎15V

T

= 25؇C

= ؎15V

= 100mV

= +1

POSITIVE

SWING

A

S

A

S

A

S

IN

V

= ؎15V

V

THD = 1%

A

NEGATIVE

SWING

8

7

4

6

0

5

1k

10k

100k

1M

10M

1k

10k

100k

0

200

400

600

800

1000

FREQUENCY (Hz)

LOAD RESISTANCE (⍀)

CAPACITIVE LOAD (pF)

TPC 19. Maximum Output

Swing vs. Frequency

TPC 20. Maximum Output

Voltage vs. Load Resistance

TPC 21. Small-Signal Overshoot

vs. Capacitive Load

2.8

2.7

2.6

2.5

2.4

2.3

2.2

190

180

170

160

150

140

130

120

110

100

90

100

75

50

25

0

V

= ؎15V

T

= +25؇C

= ؎15V

S

A

S

V

A

= 1

V

A

= 10

V

–SR

+SR

A

= 100

100k

V

T

= 25؇C

A

S

O

V

= ؎15V

80

70

= 20V p-pTO 10kHz

–75 –50 –25

0

25

50

75 100 125

1k

10k

1M

10M

1

10

100

1k

10k

100k

1M

TEMPERATURE (؇C)

FREQUENCY (Hz)

TPC 22. Output Impedance vs.

Frequency

TPC 23. Slew Rate vs.

Temperature

TPC 24. Channel Separation vs.

Frequency

0.1

T

= 25؇C

A

S

O

L

V

= ؎15V

= 20V p-p

=2k⍀

R

A

= 10

V

0.01

A

= 1

V

20␮s

5V

50mV

200nS

T

= 25؇C

T

= 25؇C

0.001

A

S

V

L

A

S

V

L

10

100

1k

10k

V

= ؎15V

= +1

V

= ؎15V

= +1

A

R

A

R

FREQUENCY (Hz)

= 2k⍀

TPC 25. Total Harmonic Distor-

tion vs. Frequency

TPC 26. Large Signal Transcient

Response

TPC 27. Small-Signal

Transient Response

–7–

REV. C

OP270

5k⍀

TOTAL NOISE AND SOURCE RESISTANCE

The total noise of an op amp can be calculated by:

500⍀

1/2

OP270

2

V

20V

p-p

1

E_n=

e

n

+ i R

+ e

(

)

(

)

( )

n

S

t

where:

5k⍀

E_n= total input referred noise

e_n= op amp voltage noise

i_n= op amp current noise

50⍀

1/2

OP270

V

2

e_t= source resistance thermal noise

R_S= source resistance

V

1

CHANNEL SEPARATION = 20 log

V /1000

2

The total noise is referred to the input and at the output would

be amplified by the circuit gain.

Figure 1. Channel Separation Test Circuit

+18V

Figure 3 shows the relationship between total noise at 1 kHz

and source resistance. For R_S< 1 kW the total noise is dominated

by the voltage noise of the OP270. As R_Srises above 1 kW, total

noise increases and is dominated by resistor noise rather than by

the voltage or current noise of the OP270. When R_Sexceeds

20 kW, current noise of the OP270 becomes the major contributor

to total noise.

8

100k⍀

2

1

1/2

OP270

3

200k⍀

100

6

7

1/2

OP270

5

100k⍀

OP200

10

4

–18V

OP270

Figure 2. Burn-In Circuit

RESISTOR

NOISE ONLY

1

100

APPLICATIONS INFORMATION

VOLTAGE AND CURRENT NOISE

1k

10k

100k

R

– SOURCE RESISTANCE (⍀)

S

The OP270 is a very low noise dual op amp, exhibiting atypical

voltage noise of only 3.2 nV/÷Hz @ 1 kHz. The exceptionally

low noise characteristic of the OP270 is achieved in part by

operating the input transistors at high collector currents since

the voltage noise is inversely proportional to the square root of

the collector current. Current noise, however, is directly propor-

tional to the square root of the collector current. As a result, the

outstanding voltage noise performance of the OP270 is gained

at the expense of current noise performance, which is normal for

low noise amplifiers.

Figure 3. Total Noise vs. Source Resistance

(Including Resistor Noise) at 1 kHz

Figure 4 also shows the relationship between total noise and

source resistance, but at 10 Hz. Total noise increases more

quickly than shown in Figure 3 because current noise is inversely

proportional to the square root of frequency. In Figure 4, current

noise of the OP270 dominates the total noise when R_S> 5 kW.

Figures 3 and 4 show that to reduce total noise, source resistance

must be kept to a minimum. In applications with a high source

resistance, the OP200, with lower current noise than the OP270,

will provide lower total noise.

To obtain the best noise performance in a circuit, it is vital to

understand the relationship between voltage noise (e_n), current

noise (i_n), and resistor noise (e_t).

–8–

REV. C

OP270

100

10

1

Figure 5 shows peak-to-peak noise versus source resistance over the

0.1 Hz to 10 Hz range. Once again, at low values of R_S, the voltage

noise of the OP270 is the major contributor to peak-to-peak

noise, with current noise the major contributor as R_Sincreases.

The crossover point between the OP270 and the OP200 for

peak-to-peak noise is at R_S= 17 kW.

The OP271 is a higher speed version of the OP270, with a slew

rate of 8 V/ms. Noise of the OP271 is slightly higher than that of

the OP270. Like the OP270, the OP271 is unity-gain stable.

OP200

OP270

For reference, typical source resistances of some signal sources

are listed in Table I.

RESISTOR

NOISE ONLY

Table I.

Source

100

1k

10k

100k

R

– SOURCE RESISTANCE (⍀)

S

Device

Impedance Comments

Figure 4. Total Noise vs. Source Resistance

(Including Resistor Noise) at 10 Hz

Strain gage

<500 W

Typically used in low

frequency applications.

Magnetic

tapehead,

microphone

<1500 W

Low I_Bvery important to reduce

self-magnetization problems

when direct coupling is used.

OP270 I_Bcan be neglected.

1000

100

10

OP200

Magnetic

phonograph

cartridge

<1500 W

Similar need for low I_Bin

direct coupled applications.

OP270 will not introduce any

self-magnetization problem.

OP270

Linear variable <1500 W

differential

transformer

Used in rugged servo-feedback

applications. Bandwidth of

interest is 400 Hz to 5 kHz.

RESISTOR

NOISE ONLY

100

1k

10k

100k

R

– SOURCE RESISTANCE (⍀)

S

Figure 5. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs.

Source Resistance (Includes Resistor Noise)

R3

1.24k⍀

R1

5⍀

–

C1

2␮F

OP270

DUT

+

R2

5⍀

C4

OP27E

0.22␮F

D1, D2

1N4148

R6

600⍀

–

R5

909⍀

R10

65.4k⍀

R11

65.4k⍀

+

R14

4.99k⍀

+

OP27E

R4

200⍀

C3

0.22␮F

e

OP42E

OUT

–

R9

C5

306k⍀

R13

5.9k⍀

–

1␮F

R8

10k⍀

R12

10k⍀

C2

0.032␮F

GAIN = 50,000

= ؎15V

V

S

Figure 6. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)

REV. C

–9–

OP270

NOISE MEASUREMENTS

Noise Measurement — Noise Voltage Density

Peak-to-Peak Voltage Noise

The circuit of Figure 8 shows a quick and reliable method of

measuring the noise voltage density of dual op amps. The first

amplifier is in unity-gain, with the final amplifier in a noninverting

gain of 101. As noise voltages of each amplifier are uncorrelated,

they add in rms fashion to yield:

The circuit of Figure 6 is a test setup for measuring peak-to-peak

voltage noise. To measure the 200 nV peak-to-peak noise specifica-

tion of the OP270 in the 0.1 Hz to 10 Hz range, the following

precautions must be observed:

1. The device has to be warmed up for at least five minutes. As

shown in the warm-up drift curve, the offset voltage typically

changes 2 mV due to increasing chip temperature after power-up.

In the 10-second measurement interval, these temperature

induced effects can exceed tens of nanovolts.

2

Ê

ˆ

e_OUT= 101

e

+ e

(

)

(

)

Á

Ë

˜

¯

nA

nB

The OP270 is a monolithic device with two identical amplifi-

ers. The noise voltage density of each individual amplifier will

match, giving:

2. For similar reasons, the device has to be well shielded from

air currents. Shielding also minimizes thermocouple effects.

2

Ê

ˆ

e_OUT= 101 2e_n= 101 2e_n

Á

˜

3. Sudden motion in the vicinity of the device can also “feed

through” to increase the observed noise.

(

)

Ë

¯

4. The test time to measure noise of 0.1 Hz to 10 Hz should not

exceed 10 seconds. As shown in the noise-tester frequency

response curve of Figure 7, the 0.1 Hz corner is defined by

only one pole. The test time of 10 seconds acts as an additional

pole to eliminate noise contribution from the frequency band

below 0.1 Hz.

R1

R2

100⍀

10k⍀

–

1/2

OP270

+

e_OUT

–

1/2

TO SPECTRUM ANALYZER

e_n

OP270

+

e_OUT(nV/ Hz) =ෂ 101 (

2

)

ෂ

100

80

60

40

20

0

V

= 15V

S

Figure 8. Noise Voltage Density Test Circuit

R3

1.24k⍀

R1

5⍀

R2

100k⍀

–

OP270

DUT

–

e_nOUT

OP27E

+

TO SPECTRUM ANALYZER

+

R5

8.06k⍀

R4

GAIN = 10,000

= ؎15V

200⍀

V

S

0.01

0.1

1.0

10

100

FREQUENCY (Hz)

Figure 9. Current Noise Density Test Circuit

Figure 7. 0.1 Hz to 10 Hz Peak-to-Peak Voltage

Noise Test Circuit Frequency Response

Noise Measurement — Current Noise Density

The test circuit shown in Figure 9 can be used to measure cur-

rent noise density. The formula relating the voltage output to

current noise density is:

5. A noise-voltage-density test is recommended when measuring

noise on a large number of units. A 10 Hz noise-voltage-density

measurement will correlate well with a 0.1 Hz to 10 Hz

peak-to-peak noise reading, since both results are determined by

the white noise and the location of the 1/f corner frequency.

2

Ê

ˆ²

e_nOUT

G

- 40 nV/ Hz

Á

Ë

˜

¯

(

)

i_n=

6. Power should be supplied to the test circuit by well bypassed

low noise supplies, e.g., batteries. They will minimize output

noise introduced via the amplifier supply pins.

R_S

where:

G = gain of 10,000

R_S= 100 kW source resistance

–10–

REV. C

OP270

CAPACITIVE LOAD DRIVING AND POWER SUPPLY

CONSIDERATIONS

APPLICATIONS

Low Phase Error Amplifier

The OP270 is unity-gain stable and capable of driving large

capacitive loads without oscillating. Nonetheless, good supply

bypassing is highly recommended. Proper supply bypassing

reduces problems caused by supply line noise and improves the

capacitive load driving capability of the OP270.

The simple amplifier depicted in Figure 12 utilizes a monolithic

dual operational amplifier and a few resistors to substantially

reduce phase error compared to conventional amplifier designs.

At a given gain, the frequency range for a specified phase accuracy is

over a decade greater than for a standard single op amp amplifier.

In the standard feedback amplifier, the op amp’s output resis-

tance combines with the load capacitance to form a low-pass

filter that adds phase shift in the feedback network and reduces

stability. A simple circuit to eliminate this effect is shown in

Figure 10. The added components, C1 and R3, decouple the

amplifier from the load capacitance and provide additional

stability. The values of C1 and R3 shown in Figure 10 are for a

load capacitance of up to 1,000 pF when used with the OP270.

The low phase error amplifier performs second-order frequency

compensation through the response of op amp A2 in the feed-

back loop of A1. Both op amps must be extremely well matched

in frequency response. At low frequencies, the A1 feedback

loop forces V₂/(K1 + 1) = V_IN. The A2 feedback loop forces

Vo/(K1 + 1) = V₂/(K1 + 1), yielding an overall transfer function

of V_O/V_IN= K1 + 1. The dc gain is determined by the resistor

divider at the output, V_O, and is not directly affected by the resis-

tor divider around A2. Note that like a conventional single op amp

amplifier, the dc gain is set by resistor ratios only. Minimum

gain for the low phase error amplifier is 10.

V+

+

C3

0.1␮F

C2

10␮F

R2

R2 = R1

R2

K1

R2

–

1/2

OP270E

A2

C1

200pF

R1

V

R3

50⍀

–

IN

V

2

V

OP270

OUT

+

C1

1000pF

C5

0.1␮F

C4

–

1/2

OP270E

A1

R1

K1

10␮F

+

R2

PLACE SUPPLY DECOUPLING

CAPACITOR AT OP270

V–

+

V

IN

V

O

Figure 10. Driving Large Capacitive Loads

ASSUME A1 AND A1 ARE MATCHED.

V = (K + 1)V

O 1

IN

␻

T

s

A

(s) =

O

UNITY-GAIN BUFFER APPLICATIONS

When R_f£ 100 W and the input is driven with a fast, large

signal pulse (>1 V), the output waveform will look like the one

in Figure 11.

Figure 12. Low Phase Error Amplifier

Figure 13 compares the phase error performance of the low

phase error amplifier with a conventional single op amp ampli-

fier and a cascaded two-stage amplifier. The low phase error

amplifier shows a much lower phase error, particularly for fre-

quencies where w/bw_T< 0.1. For example, phase error of –0.1∞

occurs at 0.002 w/bw_Tfor the single op amp amplifier, but at

0.11 w/bw_Tfor the low phase error amplifier.

During the fast feedthrough-like portion of the output, the input

protection diodes effectively short the output to the input, and a

current, limited only by the output short-circuit protection, will be

drawn by the signal generator. With R_f≥ 500 W, the output is

capable of handling the current requirements (I_L£ 20 mA at 10 V);

the amplifier will stay in its active mode and a smooth transition

will occur.

When R_f> 3 kW, a pole created by R_fand the amplifier’s input

capacitance (3 pF) creates additional phase shift and reduces

phase margin. A small capacitor (20 pF to 50 pF) in parallel

with R_fhelps eliminate this problem.

Figure 11. Pulsed Operation

REV. C

–11–

OP270

0

–1

–2

–3

–4

–5

–6

–7

FIVE-BAND LOW NOISE STEREO GRAPHIC EQUALIZER

The graphic equalizer circuit shown in Figure 14 provides 15 dB of

boost or cut over a 5-band range. Signal-to-noise ratio over a 20 kHz

bandwidth is better than 100 dB and referred to a 3 V rms input.

Larger inductors can be replaced by active inductors, but this

reduces the signal-to-noise ratio.

SINGLE OP AMP.

CONVENTIONAL DESIGN

CASCADED

(TWO STAGES)

DIGITAL PANNING CONTROL

Figure 15 uses a DAC8221, a dual 12-bit CMOS DAC, to pan

a signal between two channels. One channel is formed by the

current output of DAC A driving one-half of an OP270 in a

current-to-voltage converter configuration. The other channel is

formed by the complementary output current of DAC A, which

normally flows to ground through the AGND pin. This comple-

mentary current is converted to a voltage by the other half of the

OP-270, which also holds AGND at virtual ground.

LOW PHASE ERROR

AMPLIFIER

0.001

0.01

0.1

1.0

0.005

0.05

0.5

FREQUENCY RATIO (1/␤␻)(␻/␻ )

T

Gain error due to mismatching between the internal DAC ladder

resistors and the current-to-voltage feedback resistors is elimi-

nated by using feedback resistors internal to the DAC8221. Only

DAC A passes a signal; DAC B provides the second feedback

resistor. With V_REFB unconnected, the current-to-voltage converter,

using R_FBB, is accurate and not influenced by digital data reach-

ing DAC B. Distortion of the digital panning control is less than

0.002% over the 20 Hz to 20 kHz audio range. Figure 16 shows

the complementary outputs for a 1 kHz input signal and a digital

ramp applied to the DAC data input.

Figure 13. Phase Error Comparison

C1

0.47␮F

V

+

IN

R2

3.3k⍀

R1

47k⍀

1/2

+

OP270E

R14

100⍀

1/2

OP270E

V

OUT

–

R4

1k⍀

–

C2

R3

680⍀

R13

3.3k⍀

6.8␮F

L1

1H

60Hz

+

TANTALUM

DUAL PROGRAMMABLE GAIN AMPLIFIER

R6

1k⍀

The dual OP270 and the DAC8221, a dual 12-bit CMOS

DAC, can be combined to form a space-saving dual program-

mable amplifier. The digital code present at the DAC, which is

easily set by a microprocessor, determines the ratio between the

internal feedback resistor and the resistance the DAC ladder

presents to the op amp feedback loop. Gain of each amplifier is

C3

R5

680⍀

1␮F

L2

200Hz

+

600mH

TANTALUM

R8

1k⍀

C4

0.22␮F

R7

680⍀

L3

800Hz

3kHz

180mH

V_OUT

V_IN

4096

n

R10

1k⍀

= –

C5

0.047␮F

R9

680⍀

L4

where n equals the decimal equivalent of the 12-bit digital code

present at the DAC. If the digital code present at the DAC

consists of all zeros, the feedback loop will open, causing the op

amp output to saturate. A 20 MW resistor placed in parallel with

the DAC feedback loop eliminates this problem with only a very

small reduction in gain accuracy.

60mH

R12

1k⍀

C6

0.022␮F

R11

680⍀

L5

10kHz

10mH

Figure 14. 5-Band Low Noise Graphic Equalizer

–12–

REV. C

OP270

+5V

21

+15V

+5V

21

V

DAC8221HP

DD

0.01␮F

V

DD

DAC8221HP

V

A

4

2

0.01␮F

10␮F

REF

R

A

FB

3

R

A

FB

3

+

V

A

IN

20M⍀

10␮F

–

+

–

I

A

OUT

2

–

8

DAC A

V

A

I

A

4

2

1

REF

OUT

2

3

8

V

1/2

OP270EZ

DAC A

–

1

IN

1/2

OP270GP

V

A

1

OUT

3

+

4

AGND

+

4

DAC DATA BUS

PINS 6 (MSB) - 17 (LSB)

AGND

–

+

1

0.1␮F

10␮F

R

B

FB

23

–

+

V

B

IN

0.1␮F

10␮F

–15V

R

B

–15V

FB

I

B

23

24

OUT

6

DAC B

–

1/2

7

V

B

I

B

22

18

REF

OUT

6

5

OP270GP

NC

DAC B

–

V

B

OUT

5

20M⍀

1/2

OP270GP

7

+

OUT

DAC DATA BUS

PINS 6 (MSB) - 17 (LSB)

DAC A/DAC B

+

V

B

22

REF

18

19

20

WRITE

CONTROL

19

20

CS

WRITE

CONTROL

DGND

5

WR

DGND

5

Figure 17. Dual Programmable Gain Amplifier

Figure 15. Digital Panning Control

A OUT

5V 5V

1ms

Figure 16. Digital Panning Control Output

REV. C

–13–

OP270

OUTLINE DIMENSIONS

8-Lead Plastic Dual In-Line Package [PDIP]

8-Lead Ceramic Dual In-Line Package [CERDIP]

P-Suffix

(N-8)

Z-Suffix

(Q-8)

Dimensions shown in inches and (millimeters)

0.375 (9.53)

0.365 (9.27)

0.355 (9.02)

0.005 (0.13) 0.055 (1.40)

MIN

MAX

8

5

8

1

5

0.295 (7.49)

0.285 (7.24)

0.275 (6.98)

0.310 (7.87)

0.220 (5.59)

PIN 1

1

4

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.100 (2.54) BSC

0.405 (10.29) MAX

0.100 (2.54)

BSC

0.320 (8.13)

0.290 (7.37)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.060 (1.52)

0.015 (0.38)

0.015

(0.38)

MIN

0.180

(4.57)

MAX

0.200 (5.08)

MAX

0.150 (3.81)

0.200 (5.08)

0.125 (3.18)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

MIN

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

SEATING

PLANE

0.015 (0.38)

0.008 (0.20)

0.023 (0.58)

0.014 (0.36)

SEATING

PLANE

15

0

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095AA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

16-Lead Standard Small Outline Package [SOIC]

Wide Body

S-Suffix

(RW-16)

Dimensions shown in millimeters and (inches)

10.50 (0.4134)

10.10 (0.3976)

16

1

9

8

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

1.27 (0.0500)

0.75 (0.0295)

0.25 (0.0098)

2.65 (0.1043)

2.35 (0.0925)

BSC

؋

45؇

0.30 (0.0118)

0.10 (0.0039)

8؇

0؇

0.51 (0.0201)

0.33 (0.0130)

SEATING

PLANE

1.27 (0.0500)

0.40 (0.0157)

0.32 (0.0126)

0.23 (0.0091)

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MS-013AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

–14–

REV. C

OP270

Revision History

Location

Page

4/03—Data Sheet changed from REV. B to REV. C.

Deletion of OP270A model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Deletion of WAFER LIMITS and DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to equations in Noise Measurements section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Change to Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

11/02—Data Sheet changed from REV. A to REV. B.

Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

9/02—Data Sheet changed from REV. 0 to REV. A.

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

REV. C

–15–

–16–


型号：	OP270GP
厂家：	ADI
描述：	Dual Very Low Noise Precision Operational Amplifier DUAL非常低的噪声精密运算放大器运算放大器光电二极管
文件：	总16页 (文件大小：516K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

OP270GP [ADI]

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