OP270GSZ-REEL2 [ADI]
Dual Very Low Noise Precision Operational Amplifier; DUAL非常低的噪声精密运算放大器
| 型号： | OP270GSZ-REEL2 |
| 厂家： | 
ADI |
| 描述： | Dual Very Low Noise Precision Operational Amplifier |
| 文件： | 总20页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Very Low Noise Precision
Operational Amplifier
OP270
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Very low noise density of 5 nV/√Hz at 1 kHz maximum
Excellent input offset voltage of 75 μV maximum
Low offset voltage drift of 1 μV/°C maximum
Very high gain of 1500 V/mV minimum
Outstanding CMR of 106 dB minimum
Slew rate of 2.4 V/μs typical
–IN A
+IN A
NC
1
2
3
4
5
6
7
8
16 OUT A
15 NC
14 NC
V–
13 V+
OP270
NC
12 NC
+IN B
–IN B
NC
11 NC
10 OUT B
Gain bandwidth product of 5 MHz typical
Industry-standard 8-lead dual pinout
9
NC
NC = NO CONNECT
Figure 1. 16-Lead SOIC
(S-Suffix)
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
A
B
OUT B
–IN B
+IN B
OP270
Figure 2. 8-Lead PDIP (P-Suffix)
8-Lead CERDIP
(Z-Suffix)
GENERAL DESCRIPTION
The OP270 is a high performance, monolithic, dual operational
amplifier with exceptionally low voltage noise density (5 nV/√Hz
maximum at 1 kHz). It offers comparable performance to the
industry-standard OP27 from Analog Devices, Inc.
devices, a significant advantage for power conscious applications.
The OP270 is unity-gain stable with a gain bandwidth product
of 5 MHz and a slew rate of 2.4 V/μs.
The OP270 offers excellent amplifier matching, which is
important for applications such as multiple gain blocks, low
noise instrumentation amplifiers, dual buffers, and low noise
active filters.
The OP270 features an input offset voltage of less than 75 μV
and an offset drift of less than 1 μV/°C, guaranteed over the full
military temperature range. Open-loop gain of the OP270 is more
than 1,500,000 into a 10 kΩ load, ensuring excellent gain accuracy
and linearity, even in high gain applications. The input bias
current is less than 20 nA, which reduces errors due to signal
source resistance. With a common-mode rejection (CMR) of
greater than 106 dB and a power supply rejection ratio (PSRR)
of less than 3.2 μV/V, the OP270 significantly reduces errors
due to ground noise and power supply fluctuations. The power
consumption of the dual OP270 is one-third less than two OP27
The OP270 conforms to the industry-standard 8-lead DIP
pinout. It is pin compatible with the MC1458, SE5532/A,
RM4558, and HA5102 dual op amps, and can be used to
upgrade systems using those devices.
For higher speed applications, the ADA4004-2 or the AD8676 are
recommended. For a quad op amp, see the OP470 data sheet.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2010 Analog Devices, Inc. All rights reserved.
OP270
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage and Current Noise........................................................ 12
Total Noise and Source Resistance........................................... 12
Noise Measurements.................................................................. 14
Capacitive Load Driving and Power Supply Considerations.. 15
Unity-Gain Buffer Applications ............................................... 15
Low Phase Error Amplifier....................................................... 16
Five-Band, Low Noise, Stereo Graphic Equalizer.................. 16
Digital Panning Control............................................................ 17
Dual Programmable Gain Amplifier....................................... 17
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits..................................................................................... 11
Applications Information .............................................................. 12
REVISION HISTORY
2/10—Rev. D to Rev. E
4/03—Rev. B to Rev. C
Change to General Description Section........................................ 1
Change to Input Noise Current Density Parameter, Table 1 ...... 3
Change to Figure 18 ......................................................................... 8
Changes to Total Noise and Source Resistance Section ............ 13
Changes to Figure 41...................................................................... 16
Deletion of OP270A model...............................................Universal
Edits to Features.................................................................................1
Changes to Specifications.................................................................2
Deletion of Wafer Limits and Dice Characteristics ......................4
Changes to Absolute Maximum Ratings........................................4
Changes to Ordering Guide.............................................................4
Changes to Equations in Noise Measurements section............. 10
Change to Figure 10 ....................................................................... 11
Updated Outline Dimensions....................................................... 14
2/09—Rev. C to Rev. D
Updated Format..................................................................Universal
Reorganized Layout............................................................Universal
Changes to Figure 7.......................................................................... 6
Changes to Figure 22........................................................................ 9
Deleted Applications Heading ...................................................... 11
Changes to Figure 44...................................................................... 17
Changes to Figure 46...................................................................... 18
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
11/02—Rev. A to Rev. B
Updated Ordering Guide .............................................................. 15
9/02—Rev. 0 to Rev. A
Edits to Absolute Maximum Ratings..............................................5
Edits to Ordering Guide ................................................................ 15
2/01—Revision 0: Initial Version
Rev. E | Page 2 of 20
OP270
SPECIFICATIONS
VS = ±±1 V, TA = 21°C, unless otherwise noted.
Table 1.
OP270E
Typ
10
1
5
OP270F
Typ
20
3
10
OP270G
Max Min Typ Max Unit
Parameter
Symbol Test Conditions
Min
Max Min
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Noise Voltage1
VOS
IOS
75
10
20
200
6.5
5.5
5.0
150
15
50
5
250
20
μV
nA
VCM = 0 V
IB
VCM = 0 V
40
15
60
nA
en p-p
0.1 Hz to 10 Hz
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
80
80
200
6.5
5.5
5.0
80
3.6
3.2
3.2
1.1
nV p-p
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
pA/√Hz
V/mV
Input Noise Voltage Density2 en
3.6
3.2
3.2
1.1
0.7
0.6
3.6
3.2
3.2
1.1
0.7
0.6
en
en
Input Noise Current Density in
in
in
0.7
0.6
Large-Signal Voltage Gain
AVO
VO = 10 V,
RL = 10 kΩ
1500 2300
1000 1700
750 1500
VO = 10 V,
RL = 2 kΩ
750
1200
500
900
350 700
V/mV
Input Voltage Range3
Output Voltage Swing
Common-Mode Rejection
Power Supply Rejection
Ratio
Slew Rate
Supply Current
(All Amplifiers)
IVR
VO
CMR
PSRR
12
12
106
12.5
13.5
125
12
12
100
12.5
13.5
120
12
12
90
12.5
13.5
110
V
V
dB
μV/V
RL ≥ 2 kΩ
VCM = 11 V
VS = 4.5 V
to 18 V
0.56
3.2
6.5
1.0
5.6
6.5
1.5
5.6
6.5
SR
ISY
1.7
2.4
4
1.7
2.4
4
1.7
2.4
4
V/μs
mA
No load
Gain Bandwidth Product
Channel Separation1
GBP
CS
5
175
5
175
5
175
MHz
dB
VO = 20 V p-p,
fO = 10 Hz
125
125
Input Capacitance
Input Resistance
Differential Mode
Common Mode
Settling Time
CIN
3
3
3
pF
RIN
RINCM
tS
0.4
20
5
0.4
20
5
0.4
20
5
MΩ
GΩ
μs
AV = +1, 10 V,
step to 0.01%
1 Guaranteed but not 100% tested.
2 Sample tested.
3 Guaranteed by CMR test.
Rev. E | Page 3 of 20
OP270
ELECTRICAL SPECIFICATIONS
VS = ±±1 V, −40°C ≤ TA ≤ 81°C, unless otherwise noted.
Table 2.
OP270E
Typ
OP270F
Max Min Typ
OP270G
Max Min Typ Max Unit
Parameter
Symbol Test Conditions
Min
Input Offset Voltage
Average Input Offset
Voltage Drift
VOS
TCVOS
25
0.2
150
1
45
0.4
275
2
100
0.7
400
3
μV
μV/°C
Input Offset Current
Input Bias Voltage
IOS
IB
VCM = 0 V
VCM = 0 V
1.5
6
30
60
5
15
40
70
15
19
50
80
nA
nA
Large-Signal Voltage Gain AVO
VO = 10 V,
RL = 10 kΩ
1000 1800
600 1400
400 1250
V/mV
AVO
VO = 10 V,
RL = 2 kΩ
500
900
300 700
225 670
V/mV
Input Voltage Range1
Output Voltage Swing
Common-Mode Rejection CMR
Power Supply Rejection
Ratio
Supply Current
(All Amplifiers)
IVR
VO
12
12
100
12.5
13.5
120
12
12
94
12.5
13.5
115
12
12
90
12.5
13.5
100
V
V
dB
μV/V
RL ≥ 2 kΩ
VCM = 11 V
VS = 4.5 V to 18 V
PSRR
0.7
5.6
7.2
1.8
10
2.0
1.5
7.2
ISY
No load
4.4
4.4
7.2
4.4
mA
1 Guaranteed by CMR test.
Rev. E | Page 4 of 20
OP270
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage
18 V
Differential Input Voltage1
Differential Input Current1
Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Lead Temperature Range (Soldering, 60 sec)
Junction Temperature (TJ)
Operating Temperature Range
1.0 V
25 mA
Supply voltage
Continuous
−65°C to +150°C
300°C
−65°C to +150°C
−40°C to +85°C
For military processed devices, refer to the Standard Micro-
circuit Drawing (SMD) available at the Defense Logistics
Agency website.
Table 4. Analog Devices Equivalent to SMD
1 The OP270 inputs are protected by back-to-back diodes. To achieve low noise
performance, current-limiting resistors are not used. If the differential voltage
exceeds +10 V, the input current should be limited to 25 mA.
SMD Part Number
Analog Devices Equivalent
5962-8872101PA
OP270AZMDA
ESD CAUTION
Rev. E | Page 5 of 20
OP270
TYPICAL PERFORMANCE CHARACTERISTICS
10
10
T
V
= 25°C
= ±15V
T
= 25°C
= ±15V
9
8
7
A
A
V
S
S
6
5
4
3
1
1/f CORNER = 5Hz
2
1/f CORNER = 200Hz
1
0.1
1
10
100
FREQUENCY (Hz)
1k
10
100
FREQUENCY (Hz)
1k
10k
125
5
Figure 3. Voltage Noise Density vs. Frequency
Figure 6. Current Noise Density vs. Frequency
5
4
3
2
1
40
30
20
10
0
V
= ±15V
T
A
= 25°C
S
AT 10kHz
AT 1kHz
–10
–20
–30
0
±5
±10
±15
±20
–75
–50
–25
0
25
50
75
100
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 4. Voltage Noise Density vs. Supply Voltage
Figure 7. Input Offset Voltage vs. Temperature
0.1Hz TO 10Hz NOISE
5
4
3
2
T
= 25°C
= ±15V
A
V
S
1
0
T
T
= 25°C
= ±15V
A
S
0
1
2
3
4
TIME (Minutes)
TIME (1 sec/DIV)
Figure 5. 0.1 Hz to 10 Hz Input Voltage Noise
Figure 8. Warm-Up Offset Voltage Drift
Rev. E | Page 6 of 20
OP270
7
6
5
4
130
120
110
100
V
V
= ±15V
= 0V
T
V
= 25°C
= ±15V
S
A
CM
S
90
80
70
60
50
40
30
20
3
2
10
–75
–50
–25
0
25
50
75
100
125
1
10
100
1k
10k
100k
1M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 9. Input Bias Current vs. Temperature
Figure 12. CMR vs. Frequency
5
4
3
2
6
5
4
3
2
V
V
= ±15V
S
= 0V
CM
+125°C
+25°C
–55°C
1
0
–75
–50
–25
0
25
50
75
100
125
0
±5
±10
±15
±20
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 10. Input Offset Current vs. Temperature
Figure 13. Total Supply Current vs. Supply Voltage
7
6
5
4
8
7
V
= ±15V
T
V
= +25°C
= ±15V
S
A
S
6
5
4
3
2
1
0
3
2
–10.0
–5.0
0
5.0
10.0
–75
–50
–25
0
25
50
75
100
125
–12.5
–7.5
–2.5
2.5
7.5
12.5
TEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)
Figure 11. Input Bias Current vs. Common-Mode Voltage
Figure 14. Total Supply Current vs. Temperature
Rev. E | Page 7 of 20
OP270
80
140
120
100
80
25
20
15
T
= 25°C
A
T
V
= 25°C
= ±15V
A
S
100
120
140
160
180
PHASE
–PSR
10
5
PHASE
MARGIN = 62°
+PSR
60
GAIN
40
0
20
–5
–10
0
1
10
100
1k
10k
100k
1M
10M
100M
1
2
3
4
5
6
7
8
9 10
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 15. PSR vs. Frequency
Figure 18. Open-Loop Gain and Phase Shift vs. Frequency
140
120
100
80
5000
4000
3000
2000
1000
0
T
V
= 25°C
= ±15V
A
S
60
40
20
0
1
10
100
1k
10k
100k
1M
10M
100M
0
±5
±10
±15
±20
±25
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 16. Open-Loop Gain vs. Frequency
Figure 19. Open-Loop Gain vs. Supply Voltage
80
60
80
T
V
= 25°C
= ±15V
A
8
7
S
70
60
50
40
40
20
0
Ф
6
5
GBP
4
–20
1k
10k
100k
1M
10M
–75
–50
–25
0
25
50
75
100
125
150
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 17. Closed-Loop Gain vs. Frequency
Figure 20. Phase Margin and Gain Bandwidth Product vs. Temperature
Rev. E | Page 8 of 20
OP270
28
24
20
16
12
8
100
75
50
25
0
T
V
= 25°C
= ±15V
T
= 25°C
V = ±15V
S
A
A
S
THD = 1%
A
= 1
V
A
= 10
V
A
= 100
V
4
0
1k
10k
100k
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
125
1M
FREQUENCY (Hz)
Figure 21. Maximum Output Swing vs. Frequency
Figure 24. Output Impedance vs. Frequency
15
14
13
12
11
10
9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
T
V
= 25°C
= ±15V
V
= ±15V
A
S
POSITIVE
SWING
S
NEGATIVE
SWING
–SR
+SR
8
7
6
5
100
1k
10k
–75
–50
–25
0
25
50
75
100
LOAD RESISTANCE (Ω)
TEMPERATURE (°C)
Figure 22. Maximum Output Voltage vs. Load Resistance
Figure 25. Slew Rate vs. Temperature
50
40
30
20
10
0
190
180
170
160
150
T
V
V
= 25°C
= ±15V
= 100mV
= +1
A
S
IN
A
V
140
130
120
110
100
90
T
= 25°C
= ±15V
A
V
V
S
80
= 20V p-p TO 10kHz
O
70
0
200
400
600
800
1000
1
10
100
1k
10k
100k
CAPACITIVE LOAD (pF)
FREQUENCY (Hz)
Figure 23. Small-Signal Overshoot vs. Capacitive Load
Figure 26. Channel Separation vs. Frequency
Rev. E | Page 9 of 20
OP270
0.1
T
V
V
= 25°C
= ±15V
= 20V p-p
= 2kΩ
T
V
S
A
R
= 25°C
= ±15V
= +1
A
A
S
O
V
L
R
= 2kΩ
L
A
= 10
V
0.01
A
= 1
V
50mV
200ns
0.001
10
100
FREQUENCY (Hz)
1k
10k
Figure 29. Small-Signal Transient Response
Figure 27. Total Harmonic Distortion vs. Frequency
T
V
A
R
= 25°C
= ±15V
= +1
A
S
V
L
= 2kΩ
5V
20µs
Figure 28. Large-Signal Transient Response
Rev. E | Page 10 of 20
OP270
TEST CIRCUITS
5kΩ
500Ω
1/2
OP270
V
20V
p-p
1
5kΩ
50Ω
1/2
OP270
V
2
V
1
CHANNEL SEPARATION = 20 LOG
V /1000
2
Figure 30. Channel Separation Test Circuit
+18V
8
100kΩ
2
3
1/2
OP270
1
200kΩ
100kΩ
6
5
1/2
OP270
7
4
–18V
Figure 31. Burn-In Circuit
Rev. E | Page 11 of 20
OP270
APPLICATIONS INFORMATION
Figure 33 also shows the relationship between total noise and
source resistance, but at ±0 Hz. Total noise increases more
quickly than shown in Figure 32 because current noise is
inversely proportional to the square root of frequency. In
Figure 33, the current noise of the OP270 dominates the total
noise when RS is greater than 1 kΩ.
VOLTAGE AND CURRENT NOISE
The OP270 is a very low noise dual op amp, exhibiting a typical
voltage noise density of only 3.2 nV/√Hz at ± kHz. Because the
voltage noise is inversely proportional to the square root of the
collector current, the exceptionally low noise characteristic of
the OP270 is achieved in part by operating the input transistors
at high collector currents. Current noise, however, is directly
proportional to the square root of the collector current. As a
result, the outstanding voltage noise density performance of the
OP270 is gained at the expense of current noise performance,
which is normal for low noise amplifiers.
Figure 32 and Figure 33 show that to reduce total noise, source
resistance must be kept to a minimum. In applications with a
high source resistance, the OP200, with lower current noise
than the OP270, can provide lower total noise.
100
To obtain the best noise performance in a circuit, it is vital to
understand the relationships among voltage noise (en), current
noise (in), and resistor noise (et).
TOTAL NOISE AND SOURCE RESISTANCE
OP200
10
The total noise of an op amp can be calculated by
En = (en )2 + (inRs )2 + (et )2
OP270
where:
En is the total input-referred noise.
en is the op amp voltage noise.
in is the op amp current noise.
et is the source resistance thermal noise.
RS is the source resistance.
RESISTOR
NOISE ONLY
1
100
1k
10k
100k
SOURCE RESISTANCE (Ω)
Figure 33. Total Noise vs. Source Resistance
(Including Resistor Noise) at 10 Hz
The total noise is referred to the input and at the output is
amplified by the circuit gain.
Figure 34 shows peak-to-peak noise vs. source resistance over
the 0.± Hz to ±0 Hz range. At low values of RS, the voltage noise
of the OP270 is the major contributor to peak-to-peak noise,
with current noise becoming the major contributor as RS
increases. The crossover point between the OP270 and the
OP200 for peak-to-peak noise is at a source resistance of ±7 kΩ.
1k
Figure 32 shows the relationship between total noise at ± kHz
and source resistance. When RS is less than ± kΩ, the total noise
is dominated by the voltage noise of the OP270. As RS rises
above ± kΩ, total noise increases and is dominated by resistor
noise rather than by the voltage or current noise of the OP270.
When RS exceeds 20 kΩ, the current noise of the OP270
becomes the major contributor to total noise.
OP200
100
100
OP200
10
OP270
RESISTOR
NOISE ONLY
OP270
10
100
1k
10k
100k
SOURCE RESISTANCE (Ω)
RESISTOR
NOISE ONLY
Figure 34. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs. Source Resistance
(Including Resistor Noise)
1
100
1k
10k
100k
SOURCE RESISTANCE (Ω)
Figure 32. Total Noise vs. Source Resistance
(Including Resistor Noise) at 1 kHz
Rev. E | Page 12 of 20
OP270
For reference, typical source resistances of some signal sources are listed in Table 5.
Table 5. Typical Source Resistances
Device
Source Impedance Comments
Strain Gage
<500 Ω
Typically used in low frequency applications.
Magnetic Tapehead, Microphone
<1500 Ω
Low IB is very important to reduce self-magnetization problems when
direct coupling is used. OP270 IB can be disregarded.
Magnetic Phonograph Cartridge
<1500 Ω
Low IB is important to reduce self-magnetization problems in direct-coupled
applications. OP270 does not introduce any self-magnetization problems.
Linear Variable Differential Transformer <1500 Ω
Used in rugged servo-feedback applications. The bandwidth of interest is
400 Hz to 5 kHz.
R3
1.24kΩ
R1
5Ω
OP270
DUT
C1
C4
R2
5Ω
2µF
0.22µF
OP27E
D1, D2
1N4148
R10
65.4kΩ
R11
R6
600Ω
R5
909Ω
65.4kΩ
R14
OP27E
4.99kΩ
e
C3
0.22µF
OUT
OP42E
R4
200Ω
R9
306Ω
C5
1µF
R13
5.9kΩ
R8
10kΩ
R12
10kΩ
C2
0.032µF
GAIN = 50,000
V
= ±15V
S
Figure 35. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
Rev. E | Page 13 of 20
OP270
Noise Measurement—Noise Voltage Density
NOISE MEASUREMENTS
The circuit of Figure 37 shows a quick and reliable method for
measuring the noise voltage density of dual op amps. The first
amplifier is in unity gain, with the final amplifier in a noninverting
gain of ±0±. Because the noise voltages of the amplifiers are
uncorrelated, they add in rms to yield
Peak-to-Peak Voltage Noise
The circuit of Figure 31 is a test setup for measuring peak-to-
peak voltage noise. To measure the 200 nV peak-to-peak noise
specification of the OP270 in the 0.± Hz to ±0 Hz range, the
following precautions must be observed:
2
2
eOUT =±0±
e
)
+ e
nB
)
•
The device has to be warmed up for at least five minutes.
As shown in the warm-up drift curve (see Figure 8), the
offset voltage typically changes 2 μV due to increasing chip
temperature after power-up. In the ±0 sec measurement
interval, these temperature-induced effects can exceed tens
of nanovolts.
nA
The OP270 is a monolithic device with two identical amplifiers.
Therefore, the noise voltage densities of the amplifiers match,
giving
2
eOUT =±0±
2en
=±0±
2en
)
•
•
•
For similar reasons, the device has to be well shielded from
air currents. Shielding also minimizes thermocouple effects.
R1
R2
10kΩ
100Ω
Sudden motion in the vicinity of the device can also feed
through to increase the observed noise.
1/2
OP270
e
OUT
The test time to measure noise of 0.± Hz to ±0 Hz should
not exceed ±0 sec. As shown in the noise-tester frequency
response curve of Figure 36, the 0.± Hz corner is defined by
only one pole. The test time of ±0 sec acts as an additional
pole to eliminate noise contribution from the frequency
band below 0.± Hz.
1/2
TO SPECTRUM ANALYZER
OP270
e
(nV/√Hz) ≈ 101 (√2e )
n
OUT
V
= ±15V
S
Figure 37. Noise Voltage Density Test Circuit
Noise Measurement—Current Noise Density
•
•
A noise voltage density test is recommended when measuring
noise on several units. A ±0 Hz noise voltage density mea-
surement correlates well with a 0.± Hz to ±0 Hz peak-to-peak
noise reading because both results are determined by the
white noise and the location of the ±/f corner frequency.
The test circuit shown in Figure 38 can be used to measure current
noise density. The formula relating the voltage output to the current
noise density is
2
e
2
⎛
⎜
⎝
⎞
⎟
⎠
nOUT
−
(
40nV / Hz
)
G
Power should be supplied to the test circuit by well bypassed
low noise supplies, such as batteries. Such supplies will min-
imize output noise introduced via the amplifier supply pins.
100
in =
RS
where:
G is a gain of ±0,000.
RS = ±00 kΩ source resistance.
80
60
40
20
0
R3
1.24kΩ
R1
R2
5Ω 100kΩ
OP270
DUT
e
OP27E
nOUT
TO SPECTRUM ANALYZER
R5
8.06kΩ
GAIN = 10,000
R4
200Ω
V
= ±15V
S
0.01
0.1
1
10
100
Figure 38. Current Noise Density Test Circuit
FREQUENCY (Hz)
Figure 36. 0.1 Hz to 10 Hz Peak-to-Peak Voltage Noise
Test Circuit Frequency Response
Rev. E | Page 14 of 20
OP270
CAPACITIVE LOAD DRIVING AND POWER SUPPLY
CONSIDERATIONS
UNITY-GAIN BUFFER APPLICATIONS
When Rf ≤ ±00 Ω and the input is driven with a fast, large signal
pulse (>± V), the output waveform looks like the one in Figure 40.
The OP270 is unity-gain stable and capable of driving large
capacitive loads without oscillating. Nonetheless, good supply
bypassing is highly recommended. Proper supply bypassing
reduces problems caused by supply line noise and improves the
capacitive load driving capability of the OP270.
During the fast feedthrough-like portion of the output, the input
protection diodes effectively short the output to the input, and
a current, limited only by the output short-circuit protection, is
drawn by the signal generator. With Rf ≥ 100 Ω, the output is
capable of handling the current requirements (IL ≤ 20 mA at ±0 V);
the amplifier stays in its active mode and a smooth transition occurs.
In the standard feedback amplifier, the output resistance of the
op amp combines with the load capacitance to form a low-pass
filter that adds phase shift in the feedback network and reduces
stability. A simple circuit to eliminate this effect is shown in
Figure 39. The components C± and R3 decouple the amplifier
from the load capacitance and provide additional stability. The
values of C± and R3 shown in Figure 39 are for a load capacitance
of up to ±000 pF when used with the OP270.
When Rf > 3 kΩ, a pole created by Rf and the input capacitance
(3 pF) of the amplifier creates additional phase shift and reduces
phase margin. A small capacitor (20 pF to 10 pF) in parallel with
Rf helps eliminate this problem.
R
f
V+
+
C2
10µF
OP270
2.4V/µs
C3
0.1µF
R2
C1
200pF
R1
V
R3
50Ω
IN
Figure 40. Pulsed Operation
OP270
V
OUT
C1
1000pF
C5
0.1µF
C4
10µF
+
PLACE SUPPLY DECOUPLING
CAPACITOR AT OP270
V–
Figure 39. Driving Large Capacitive Loads
Rev. E | Page 15 of 20
OP270
0
–1
–2
–3
–4
–5
–6
–7
LOW PHASE ERROR AMPLIFIER
The simple amplifier depicted in Figure 41 utilizes a monolithic
dual operational amplifier and a few resistors to substantially
reduce phase error compared with conventional amplifier
designs. At a given gain, the frequency range for a specified
phase accuracy is more than a decade greater than that of a
standard single op amp amplifier.
SINGLE OP AMP.
CONVENTIONAL DESIGN
CASCADED
(TWO STAGES)
The low phase error amplifier performs second-order fre-
quency compensation through the response of Op Amp A2 in
the feedback loop of A1. Both op amps must be extremely well
matched in frequency response. At low frequencies, the A1
feedback loop forces V2/(K1 + 1) = VIN. The A2 feedback loop
forces VO/(K1 + 1) = V2/(K1 + 1), yielding an overall transfer
function of VO/VIN = K1 + 1. The dc gain is determined by the
resistor divider at the output, VO, and is not directly affected by
the resistor divider around A2. Note that, like a conventional
single op amp amplifier, the dc gain is set by resistor ratios only.
Minimum gain for the low phase error amplifier is 10.
LOW PHASE ERROR
AMPLIFIER
0.001
0.01
0.1
1
0.005
0.05
0.5
FREQUENCY RATIO (1/βω)(ω/ω )
T
Figure 42. Phase Error Comparison
FIVE-BAND, LOW NOISE, STEREO GRAPHIC
EQUALIZER
The graphic equalizer circuit shown in Figure 43 provides 15 dB
of boost or cut over a five-band range. Signal-to-noise ratio over
a 20 kHz bandwidth is better than 100 dB and referred to a 3 V
rms input. Larger inductors can be replaced by active inductors,
but consequently reduces the signal-to-noise ratio.
R2
R2 = R1
R2
K2
1/2
OP270E
A2
V
2
C1
0.47µF
V
R2
3.3kΩ
IN
1/2
R14
100Ω
R1
47kΩ
OP270E
1/2
V
OUT
OP270E
R1
K1
R4
1kΩ
1/2
OP270E
A1
R1
C2
6.8µF
+
R3
680Ω
R13
3.3kΩ
L1
60Hz
V
IN
1H
TANTALUM
V
O
R6
1kΩ
ASSUME A1 AND A2 ARE MATCHED.
V
= (K + 1)V
IN
O
1
C3
1µF
+
ω
R5
680Ω
T
L2
200Hz
A
(s) =
O
s
600mH
TANTALUM
Figure 41. Low Phase Error Amplifier
R8
1kΩ
C4
0.22µF
+
Figure 42 compares the phase error performance of the low
phase error amplifier with a conventional single op amp
amplifier and a cascaded two-stage amplifier. The low phase
error amplifier shows a much lower phase error, particularly for
frequencies where ω/βωT < 0.1. For example, a phase error of
−0.1° occurs at 0.002 ω/βωT for the single op amp amplifier, but
at 0.11 ω/βωT for the low phase error amplifier.
R7
L3
800Hz
3kHz
680Ω
180mH
R10
1kΩ
C5
0.047µF
+
R9
680Ω
L4
60mH
R12
1kΩ
C6
0.022µF
+
R11
680Ω
L5
10kHz
10mH
Figure 43. Five-Band, Low Noise Graphic Equalizer
Rev. E | Page 16 of 20
OP270
+5V
21
DIGITAL PANNING CONTROL
+15V
Figure 44 uses a DAC822± (a dual ±2-bit CMOS DAC) to pan a
signal between two channels. One channel is formed by the
current output of DAC A driving one-half of an OP270 in a
current-to-voltage converter configuration. The other channel
is formed by the complementary output current of DAC A,
which normally flows to ground through the AGND pin. This
complementary current is converted to a voltage by the other
half of the OP270, which also holds AGND at virtual ground.
V
DD
DAC8221P
0.01µF
R
FBA
3
+
10µF
–
I
A
V
A
8
OUT
4
2
1
REF
2
3
V
DAC A
IN
1/2
OP270GP
1
OUT
AGND
4
DAC DATA BUS
PINS 6 (MSB) TO 17 (LSB)
Gain error due to mismatching between the internal DAC
ladder resistors and the current-to-voltage feedback resistors is
eliminated by using feedback resistors internal to the DAC822±.
Only DAC A passes a signal; DAC B provides the second
feedback resistor. With VREFB unconnected, the current-to-
voltage converter, using RFBB, is accurate and not influenced by
digital data reaching DAC B. Distortion of the digital panning
control is less than 0.002% over the 20 Hz to 20 kHz audio
range. Figure 41 shows the complementary outputs for a ± kHz
input signal and a digital ramp applied to the DAC data input.
+
0.1µF
10µF
–
–15V
R
FBB
23
24
V
B
I
B
REF
22
18
OUT
6
NC
DAC B
1/2
OP270GP
7
OUT
5
DAC A/DAC B
19
20
CS
WRITE
CONTROL
WR
DGND
5
DUAL PROGRAMMABLE GAIN AMPLIFIER
Figure 44. Digital Panning Control
The dual OP270 and the DAC822± (a dual ±2-bit CMOS DAC)
can be combined to form a space-saving, dual programmable
amplifier. The digital code present at the DAC, which is easily
set by a microprocessor, determines the ratio between the internal
feedback resistor and the resistance that the DAC ladder presents
to the op amp feedback loop. Gain of each amplifier is
A OUT
VO
VIN
4096
n
= −
A OUT
where n is the decimal equivalent of the ±2-bit digital code
present at the DAC.
5V
5V
1ms
If the digital code present at the DAC consists of all 0s, the
feedback loop opens, causing the op amp output to saturate. A
20 MΩ resistor placed in parallel with the DAC feedback loop
eliminates this problem with only a very small reduction in gain
accuracy.
Figure 45. Digital Panning Control Output
Rev. E | Page 17 of 20
OP270
+15V
+5V
21
0.01µF
V
DD
DAC8221P
R
V
I
A
REF
4
FBA
3
+
V
A
IN
10µF
20MΩ
–
A
2
2
OUT
8
DAC A
1/2
OP270EZ
1
V
+
A
OUT
3
4
AGND
1
0.1µF
10µF
–
R
FBB
23
–15V
V
B
IN
I
B
24
OUT
6
5
DAC B
1/2
OP270GP
7
V
B
OUT
20MΩ
DAC DATA BUS
PINS 6 (MSB) TO 17 (LSB)
V
B
REF 22
18
19
WRITE
CONTROL
20
DGND
5
Figure 46. Dual Programmable Gain Amplifier
V+
BIAS
OUT
–IN
+IN
V–
Figure 47. Simplified Schematic
(One of Two Amplifiers Is Shown)
Rev. E | Page 18 of 20
OP270
OUTLINE DIMENSIONS
0.005 (0.13)
MIN
0.055 (1.40)
MAX
8
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.405 (10.29) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
15°
0°
0.070 (1.78)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 48. 8-Lead Ceramic Dual In-Line Package [CERDIP]
Z-Suffix
(Q-8)
Dimensions shown in inches and (millimeters)
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 49. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
P-Suffix
(N-8)
Dimensions shown in inches and (millimeters)
Rev. E | Page 19 of 20
OP270
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.
0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
S-Suffix
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
1
TA = +25°C
VOS Max (μV)
θJC
(°C/W)
θJA
Package
Option
Model
(°C/W)
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead CERDIP
8-Lead CERDIP
8-Lead PDIP
OP270EZ
75
12
12
37
134
134
96
Q-8 (Z-Suffix)
Q-8 (Z-Suffix)
N-8 (P-Suffix)
N-8 (P-Suffix)
RW-16 (S-Suffix)
RW-16 (S-Suffix)
RW-16 (S-Suffix)
RW-16 (S-Suffix)
OP270FZ
OP270GP
OP270GPZ2
150
250
8-Lead PDIP
OP270GS
250
27
92
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
OP270GS-REEL
OP270GSZ2
OP270GSZ-REEL2
1 θJA is specified for worst-case mounting conditions, that is, θJA is specified for device in socket for CERDIP and PDIP packages; θJA is specified for device soldered to
printed circuit board for SOIC package.
2 Z = RoHS Compliant Part.
©2001–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00325-0-2/10(E)
Rev. E | Page 20 of 20
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