OP271EZ [ADI]
High-Speed, Dual Operational Amplifier; 高速，双路运算放大器
| 型号： | OP271EZ |
| 厂家： | 
ADI |
| 描述： | High-Speed, Dual Operational Amplifier |
| 文件： | 总12页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High-Speed, Dual
Operational Amplifier
a
OP271
PIN CONNECTIONS
FEATURES
Excellent Speed: 8.5 V/
Fast Settling (0.01%): 2
Unity-Gain Stable
m
s Typ
s Typ
m
OUT A
NC
1
2
3
4
5
6
7
8
16
15
14
13
–IN A
+IN A
NC
High-Gain Bandwidth: 5 MHz Typ
Low Input Offset Voltage: 200 V Max
V/ C Max
m
NC
Low Offset Voltage Drift: 21
High Gain: 400 V/mV Min
m
∞
V–
NC
V+
12 NC
11 NC
Outstanding CMR: 106 dB Min
Industry Standard 8-Pin Dual Pinout
Available in Die Form
+IN B
–IN B
NC
OUT B
10
9
NC
NC = NO CONNECT
GENERAL DESCRIPTION
The OP271 is a unity-gain stable monolithic dual op amp
featuring excellent speed, 8.5 V/ms typical, and fast settling
time, 2 ms typical to 0. 01%. The OP271 has a gain bandwidth
of 5 MHz with a high phase margin of 62∞.
16-Pin SOL
(S-Suffix)
Input offset voltage of the OP271 is under 200 mV with input
offset voltage drift below 2 mV/∞C, guaranteed over the full
military temperature range. Open-loop gain exceeds 400,000
into a 10 kW load ensuring outstanding gain accuracy and
linearity. The input bias current is under 20 nA limiting
errors due to source resistance. The OP271’s outstanding
CMR, over 106 dB, and low PSRR, under 5.6 mV/V, reduce
errors caused by ground noise and power supply fluctuations.
In addition, the OP27l exhibits high CMR and PSRR over a
wide frequency range, further improving system accuracy.
1
2
3
4
8
7
6
5
V+
OUT A
–IN A
+IN A
V–
A
–
B
+
OUT B
–IN B
+IN B
+
–
Epoxy Mini-DIP
(P-Suffix)
8-Pin Hermetic DIP
(Z-Suffix)
V+
BIAS
OUT
–IN
+IN
V–
Figure 1. Simplified Schematic
(One of the two amplifiers is shown.)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
OP271–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VS = ±15 V, TA = 25∞C, unless otherwise noted.)
OP271A/E
OP271F
Typ Max Min
OP271G
Typ Max
Parameter
Symbol Conditions
Min Typ Max Min
Unit
mV
INPUT OFFSET
VOLTAGE
VOS
75
1
200
10
150
4
300
15
200
7
400
20
INPUT OFFSET
CURRENT
IOS
IB
VCM = 0 V
VCM = 0 V
nA
INPUT BIAS
CURRENT
4
20
6
40
12
60
nA
INPUT NOISE
VOLTAGE
DENSITY
en
fO = 1 kHz
7.6
7.6
7.6
nV/Hz
LARGE-SIGNAL
VOLTAGE
GAIN
VO = ±10 V
RL = 10 kW
RL = 2 kW
AVO
400
300
650
500
300
200
500
300
250
175
400
250
V/mV
V/mV
INPUT VOLTAGE
RANGE
IVR
±12
±12
106
±12.5
±13
120
±12
±12
100
±12.5
±13
115
±12
±12
90
±12.5
±13
105
V
OUTPUT
VOLTAGE SWING VO
RL ≥ 2 kW
V
COMMON-MODE
REJECTION
CMR
VCM = ±12 V
dB
mV/V
POWER SUPPLY
REJECTION
RATIO
PSRR
VS = ±4.5 V
to ±18 V
0.6
3.2
6.5
1.8
5.6
6.5
2.4
7.0
6.5
SLEW RATE
SR
um
5.5
8.5
62
5.5
8.5
62
5.5
8.5
62
V/ms
PHASE MARGIN
AV = +1
No Load
degrees
SUPPLY CURRENT
(ALL AMPLIFIERS) ISY
4 5
4.5
4.5
mA
GAIN
BANDWIDTH
PRODUCT
GBW
5
5
5
MHz
CHANNEL
SEPARATION
CS
VO = 20 Vp-p
fO = 10 Hz
125
125
175
175
125
125
175
175
175
175
dB
dB
INPUT
CAPACITANCE
CIN
3
3
3
pF
INPUT
RESISTANCE
DIFFERENTIAL-
MODE
RIN
0.4
0.4
0.4
MW
INPUT
RESISTANCE
COMMON
MODE
RINCM
20
2
20
2
20
2
GW
ms
SETTLING TIME tS
AV = +1,
10 V Step
to 0.01%
NOTES
1Guaranteed by CMR test.
2Guaranteed but not 100% tested.
–2–
REV. A
OP271
ELECTRICAL CHARACTERISTICS (VS = ±15 V, –55∞C £ TA £ 125∞C for OP271A, unless otherwise noted.)
OP271A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT OFFSET VOLTAGE
VOS
115
400
mV
AVERAGE INPUT OFFSET
VOLTAGE DRIFT
TCVOS
IOS
0.4
1.5
7
2
mV/∞C
nA
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
VCM = 0 V
VCM = 0 V
30
60
IB
nA
LARGE-SIGNAL VOLTAGE
GAIN
AVO
VO = ±10 V
RL = 10 kW
RL = 2 kW
300
200
600
500
V/mV
V/mV
INPUT VOLTAGE RANGE1
OUTPUT VOLTAGE SWING
COMMON-MODE REJECTION
IVR
VO
±12
±12
100
±12.5
±13
V
RL ≥ 2 kW
V
CMR
VCM = ±12 V
120
dB
POWER SUPPLY REJECTION
RATIO
PSRR
ISY
VS = ±4.5 V to ±18 V
1.0
5.3
5.6
75
mV/V
SUPPLY CURRENT
(ALL AMPLIFIERS)
No Load
mA
NOTE
1Guaranteed by CMR test.
(VS = ±15 V, –40∞C £ TA £ +85∞C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
OP271A/E
Typ Max Min
OP271F
Typ Max Min
OP271G
Typ Max
Parameter
Symbol Conditions Min
Unit
INPUT OFFSET
VOLTAGE
VOS
100
330
215
560
300
700
mV
AVERAGE INPUT
OFFSET
VOLTAGE DRIFT TCVOS
0.4
1
2
1
4
2.0
15
15
5
mV/∞C
nA
INPUT OFFSET
CURRENT
IOS
VCM = 0 V
VCM = 0 V
30
60
5
40
70
50
80
INPUT BIAS
CURRENT
IB
6
10
nA
LARGE-SIGNAL
VOLTAGE GAIN
AVO
VO = ± 10 V
RL = 10 kW
RL = 2 kW
300
200
600
500
200
100
500
400
150
90
400
300
V/mV
V/mV
INPUT VOLTAGE
RANGE1
IVR
±12
±12
±12.5
±13
120
±12
±12
94
±12.5
±13
±12
±12
90
±12.5
±13
V
OUTPUT
VOLTAGE SWING VO
RL ≥ 2 kW
V
COMMON-MODE
REJECTION
CMR
PSRR
VCM = ±12 V 100
115
100
dB
mV/V
POWER SUPPLY
REJECTION
RATIO
VS = ±4.5 V
to ±18 V
0.7
5.6
7.2
51.8
10
2.0
15
SUPPLY CURRENT
(ALL AMPLIFIERS) ISY
No Load
5.2
5.2
7.2
5.2
7.2
mA
NOTE
1Guaranteed by CMR test.
–3–
REV. A
OP271
(Continued from Page 1)
ORDERING GUIDE
Package
The OP271 offers outstanding dc and ac matching between chan-
nels. This is especially valuable for applications such as multiple
gain blocks, high-speed instrumentation and amplifiers, buffers
and active filters.
TA = 25∞C
VOS Max
Operating
Temperature
Range
CERDIP
(
mV)
8-Pin
Plastic
The OP271 conforms to the industry standard, 8-pin dual op amp
pinout. It is pin compatible with the TL072, TL082, LF412,
and 1458/1558 dual op amps and can be used to significantly
improve systems using these devices.
200
200
300
400
400
*OP271AZ
*OP271EZ
*OP271FZ
MIL
XND
XND
XND
XND
OP271GP
For applications requiring lower voltage noise, see the OP270.
For a quad version of the OP271, see the OP471.
*OP271GS
*Not for new design, obsolete April 2002.
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . ±1.0 V
Differential Input Current2 . . . . . . . . . . . . . . . . . . . . ±25 mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . Continuous
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . 300∞C
Junction Temperature (Tj) . . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range
OP271A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C
OP271E, OP271F, OP271G . . . . . . . . . . . –40∞C to +85∞C
3
Package Type
jA
jC
Unit
8-Pin Hermetic DIP (Z)
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
134
96
92
12
37
27
∞C/W
∞C/W
∞C/W
NOTES
1Absolute maximum ratings apply to packaged parts, unless otherwise noted.
2The OP271’s inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low-noise performance. If differential
voltage exceeds ±1.0 V, the input current should be limited to ±25 mA.
3
jA is specified for worst case mounting conditions, i.e., jA is specified for
device in socket for CERDIP and P-DIP packages; jA is specified for device
soldered to printed circuit board for SOIC package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP271 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
OP271
Typical Performance Characteristics–
25
20
15
10
5
100
0.1
T
= 25ꢀC
T
= 25ꢀC
A
S
O
L
T
= 25ꢀC
= ꢁ15V
A
A
S
V
V
= ꢁ15V
V
= 10V
p-p
A
= 100
40
20
10
V
R
= 2kꢃ
AT 10Hz
A
A
= 10
= 1
0.01
V
V
5
4
3
1/f CORNER = 40Hz
AT 1kHz
2
1
0.001
1
100
1k
0
ꢁ5
ꢁ10
100
1k
10k
10
ꢁ15
ꢁ20
10
SUPPLY VOLTAGE – Volts
FREQUENCY – Hz
FREQUENCY – Hz
TPC 2. Voltage Noise Density vs.
Supply Voltage
TPC 1. Voltage Noise Density vs.
Frequency
TPC 3. Total Harmonic Distortion vs.
Frequency
10
120
10.0
T
= 25ꢀC
= ꢁ15V
V
= ꢁ15V
A
S
T
= 25ꢀC
= ꢁ15V
S
9
8
7
6
5
4
3
2
1
0
A
S
V
V
100
80
60
40
20
0
1.0
0.1
1/f CORNER = 40Hz
100
–20
0
1
2
3
4
5
10
1k
10k
–75 –50 –25
0
25
50
75 100 125
TIME – Minutes
TEMPERATURE – ꢀC
FREQUENCY – Hz
TPC 4. Current Noise Density vs.
Frequency
TPC 5. Input Offset Voltage vs.
Temperature
TPC 6. Warm-Up Offset Voltage Drift
10
5
4
3
2
1
0
7
T
= 25ꢀC
= ꢁ15V
V
V
= ꢁ15V
CM
A
S
S
V
= 0V
8
6
6
5
4
3
2
4
–1
2
–2
–3
–4
–5
0
–2
–75 –50 –25
0
25
50
75 100 125
–75 –50 –25
0
25
50
75 100 125
–12.5
–7.5
–2.5
0
2.5
7.5
12.5
TEMPERATURE – ꢀC
TEMPERATURE – ꢀC
COMMON MODE VOLTAGE – Volts
TPC 7. Input Bias Current vs.
Temperature
TPC 8. Input Offset Current vs.
Temperature
TPC 9. Input Bias Current vs.
Common-Mode Voltage
–5–
REV. A
OP271
130
120
110
100
90
7
6
5
4
3
7
6
5
4
3
V
= ꢁ15V
S
T
= +125ꢀC
= +25ꢀC
A
80
70
60
50
T
A
40
30
T
= 25ꢀC
A
S
20
10
V
= ꢁ15V
T
= –55ꢀC
ꢁ15
A
1M
–75 –50 –25
0
25
50
75 100 125
1
10
100
1k
10k
100k
0
ꢁ5
ꢁ10
ꢁ20
FREQUENCY – Hz
SUPPLY VOLTAGE – Volts
TEMPERATURE – ꢀC
TPC 10. CMR vs. Frequency
TPC 11. Total Supply Current vs.
Supply Voltage
TPC 12. Total Supply Current vs.
Temperature
140
140
80
T
= 25ꢀC
T
= 25ꢀC
T
= 25ꢀC
= ꢁ15V
A
S
A
A
S
V
= ꢁ15V
V
120
100
80
60
40
20
0
120
100
80
60
40
20
0
60
40
20
0
–PSR
+PSR
–20
1
10
100 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz
1k
10k
100k
FREQUENCY – Hz
1M
10M
1
10 100 1k
100k
10M 100M
1M
10k
FREQUENCY – Hz
TPC 13. PSR vs. Frequency
TPC 14. Open-Loop Gain vs.
Frequency
TPC 15. Closed-Loop Gain vs.
Frequency
25
20
15
10
5
8
6
4
2
0
80
2000
1500
1000
T
= 25ꢀC
V
= ꢁ15V
A
S
S
T
= 25ꢀC
A
L
V
= ꢁ15V
100
120
140
160
180
PHASE
GAIN
R
= 10kꢃ
70
60
50
40
GBW
PHASE MARGIN = 62ꢀC
ꢄ
m
0
500
0
–5
–10
1
2
3
4
5
6 7 8 10
–75 –50 –25
25 50 75 100 125 150
TEMPERATURE – ꢀC
0
ꢁ5
ꢁ10
ꢁ15
ꢁ20
0
FREQUENCY – MHz
SUPPLY VOLTAGE – Volts
TPC 16. Open-Loop Gain, Phase Shift
vs. Frequency
TPC 18. Gain-Bandwidth Product,
Phase Margin vs. Temperature
TPC 17. Open-Loop Gain vs. Supply
Voltage
–6–
REV. A
OP271
28
24
20
16
12
8
180
160
140
120
100
80
20
18
16
14
12
10
8
T
= 25ꢀC
T
= 25ꢀC
T
= 25ꢀC
= ꢁ15V
A
S
A
S
A
S
V
= ꢁ15V
V
= ꢁ15V
V
THD = 1%
R
POSITIVE SWING
= 10kꢃ
L
NEGATIVE SWING
A
= 1
60
V
6
40
4
4
A
= 100
10k
20
V
2
0
0
0
1k
10k
100k
FREQUENCY – Hz
1M
10M
100
1k
100k
1M
10M
100
1k
10k
FREQUENCY – Hz
LOAD RESISTANCE – ꢃ
TPC 19. Maximum Output Swing
vs. Frequency
TPC 21. Output Impedance vs.
Frequency
TPC 20. Maximum Output Voltage
vs. Load Resistance
12
190
180
170
160
T
= 25ꢀC
= ꢁ15V
A
S
V
= ꢁ15V
S
V
11
10
9
150
140
130
120
110
100
90
–SR
+SR
8
7
80
6
70
10
100
1k
10k
100k
1M
10M
–75 –50 –25
0
25
50
75 100 125
TEMPERATURE – ꢀC
FREQUENCY – Hz
TPC 22. Slew Rate vs. Temperature
TPC 23. Channel Separation vs.
Frequency
T
= 25ꢀC
= ꢁ15V
= +1
T
= 25ꢀC
= ꢁ15V
= +1
A
S
V
A
V
V
S
A
A
V
5V
5ꢂs
50mV
200ns
TPC 24. Large-Signal Transient
Response
TPC 25. Small Signal Transient
Response
–7–
REV. A
OP271
When Rf > 3 k⍀, a pole created by Rf and the amplifier’s
input capacitance (3 pF) creates additional phase shift and
reduces phase margin. A small capacitor in parallel with Rf
helps eliminate this problem.
APPLICATION INFORMATION
Capacitive Load Driving and Power Supply Considerations
The OP217 is unity-gain stable and is capable of driving large
capacitive loads without oscillating. Nonetheless, good supply
bypassing is highly recommended. Proper supply bypassing
reduces problems caused by supply line noise and improves
the capacitive load driving capability of the OP271.
Computer Simulations
Many electronic design and analysis programs include models
for op amps which calculate AC performance from the location
of poles and zeros. As an aid to designers utilizing such a
program, major poles and zeros of the OP271 are listed below.
Their location will vary slightly between production lots.
Typically, they will be within ؎15% of the frequency listed.
Use of this data will enable the designer to evaluate gross
circuit performance quickly, but should not supplant rigorous
characterization of a breadboard circuit.
In the standard feedback amplifier, the op amp’s output resistance
combines with the load capacitance to form a low-pass filter that
adds phase shift in the feedback network and reduces stability. A
simple circuit to eliminate this effect is shown in Figure 2. The
added components, C1 and R3, decouple the amplifier from the
load capacitance and provide additional stability. The values of
C1 and R3 shown in Figure 8 are for a load capacitance of up to
1000 pF when used with the OP271.
POLES
15Hz
1.2 MHz
2 X 32 MHz
8 X 40 MHz
ZEROS
2.5 MHz
4 X 23 MHz
V+
C2
10F
-
-
+
APPLICATIONS
Low Phase Error Amplifier
C3
0.1F
R2
The simple amplifier depicted in Figure 4, utilizes a monolithic
dual operational amplifier and a few resistors to substantially
reduce phase error compared to conventional amplifier designs.
At a given gain, the frequency range for a specified phase
accuracy is over a decade greater than for a standard single op
amp amplifier.
C1
200pF
R1
R3
V
IN
50⍀
V
OP271
OUT
C4
C
L
10F
1000pF
+
The low phase error amplifier performs second-order frequency
compensation through the response of op amp A2 in the
feedback loop of A1. Both op amps must be extremely well
matched in frequency response. At low frequencies, the A1
feedback loop forces V2/(K1 + 1)=VIN. The A2 feedback loop
forces VO/VIN=K1 + 1. The DC gain is determined by the
resistor divider around A2. Note that, like a conventional
single op amp amplifier, the DC gain is set by resistor ratios
only. Minimum gain for the low phase error amplifier is 10.
C5
PLACE SUPPLY DECOUPLING
CAPACITORS AT OP271
0.1F
V–
Figure 2. Driving Large Capacitive Loads
Unity-Gain Buffer Applications
When Rf Յ 100 ⍀ and the input is driven with a fast, large-signal
pulse (>1 V), the output waveform will look as shown in Figure
3.
R2
R2 = R1
R2
K1
During the fast feedthrough-like portion of the output, the input
protection diodes effectively short the output to the input, and a
current, limited only by the output short-circuit protection, will
be drawn by the signal generator. With Rf Ն 500 ⍀, the output is
capable of handling the current requirements (IL Յ 20 mA at
10 V); the amplifier will stay in its active mode and a smooth
transition will occur.
1/2
OP271E
A2
V
2
R1
K1
1/2
R1
R1
OP271E
A1
V
IN
V
O
ASSUME: A1 AND A2 ARE MATCHED.
V
= (K +1) V
1
8.5V/s
O
IN
A
(s) =
O
s
OP271
Figure 4. Low Phase Error Amplifier
Figure 3. Pulsed Operation
–8–
REV. A
OP271
Dual 12-Bit Voltage Output DAC
0
The dual voltage output DAC shown in Figure 6 will settle to
12-bit accuracy from zero to full scale in 2 ꢂs typically. The
CMOS DAC-8222 utilizes a 12-bit, double-buffered input
structure allowing faster digital throughput and minimizing
digital feedback.
–1
–2
–3
–4
–5
–6
–7
SINGLE OP AMP,
CONVENTIONAL
DESIGN
Fast Current Pump
CASCADED
(TWO STAGES)
Maximum output current of the fast current pump shown in
Figure 7 is ꢁ11 mA. Voltage compliance exceeds ꢁ10 V with
ꢁ15 V supplies. The current pump has an output resistance
of over 3 Mꢃ and maintains 12-bit linearity over its entire
output range.
LOW PHASE ERROR
AMPLIFIER
0.001
0.01
0.1
1.0
0.005
0.005
0.5
R3
FREQUENCY RATIO – 1/ꢅ ꢆ/ꢆ
10kꢃ
Figure 5. Phase Error Comparison
R1
Figure 5 compares the phase error performance of the low
phase error amplifier with a conventional single op amp
amplifier and a cascaded two-stage amplifier. The low phase
error amplifier shows a much lower phase error, particularly for
frequencies where ꢆꢇꢈꢆT<0.1. For example, phase error of
-0.1ꢀ occurs at 0.002 ꢆꢇꢈꢆT for the single op amplifier, but
at 0.11 ꢆꢇꢈꢆT for the low phase error amplifier.
10kꢃ
2
3
R5
100ꢃ
1/2
1
I
OUT
ꢁ11mA
V
OP271FZ
IN
R2
10kꢃ
+15V
8
5
R4
1/2
10kꢃ
7
OP271FZ
4
For more detailed information on the low phase error amplifier,
see Application Note AN-107.
6
V
V
IN
IN
=
10mA/V
I
=
=
OUT
RS 100ꢃ
–15V
Figure 7. Fast Current Pump
+15V
10ꢂF
5V
21
0.1ꢂF
V
DD
R
A
FB
3
2
DAC-8222EW
8
10V
REFERENCE
VOLTAGE
10pF
I
A
V
A
OUT
4
REF
2
3
DAC A
–
1/2
V
A
OP271EZ
OUT
+
1
AGND
4
7
–15V
12-BIT DATABUS PINS 6–17
0.1ꢂF
10ꢂF
I
B
V
B
OUT
24
23
6
5
22 REF
DAC B
–
1/2
V
B
10pF
OP271EZ
OUT
R
B
FB
18
DAC A/DAC B
+
19
20
DAC
LDAC
WR
CONTROL
DGND
Figure 6. Dual 12-Bit Voltage Output DAC
REV. A
–9–
OP271
OUTLINE DIMENSIONS
8-Lead Plastic Dual-in-Line Package [PDIP]
8-Lead Ceramic Dip-Glass Hermetic Seal [CERDIP]
(Q-8)
(N-8)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
0.005 (0.13) 0.055 (1.40)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
MIN
MAX
8
5
8
1
5
0.310 (7.87)
0.220 (5.59)
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
PIN 1
1
4
4
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54) BSC
0.405 (10.29) MAX
0.100 (2.54)
BSC
0.320 (8.13)
0.290 (7.37)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.060 (1.52)
0.015 (0.38)
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.200 (5.08)
MAX
0.150 (3.81)
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15
0
0.070 (1.78)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCH; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES)
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
ꢉ 45ꢀ
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8ꢀ
0.51 (0.0201)
0.33 (0.0130)
0ꢀ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.19 (0.0075)
SEATING
PLANE
0.41 (0.0160)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
–10–
REV. A
OP271
Revision History
Location
Page
10/02—Data Sheet changed from REV. 0 to REV. A.
Deleted PIN CONNECTIONS Caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
REV. A
–11–
–12–
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