OP275GP [ADI]
Dual Bipolar/JFET, Audio Operational Amplifier; 双双极性/ JFET ，音频运算放大器
| 型号： | OP275GP |
| 厂家： | 
ADI |
| 描述： | Dual Bipolar/JFET, Audio Operational Amplifier |
| 文件： | 总12页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Bipolar/JFET, Audio
Operational Amplifier
a
OP275*
PIN CONNECTIONS
FEATURES
Excellent Sonic Characteristics
Low Noise: 6 nV/√Hz
Low Distortion: 0.0006%
High Slew Rate: 22 V/s
Wide Bandwidth: 9 MHz
Low Supply Current: 5 mA
Low Offset Voltage: 1 mV
Low Offset Current: 2 nA
Unity Gain Stable
8-Lead Narrow-Body SO
8-Lead Epoxy DIP
(P Suffix)
(S Suffix)
1
8
7
6
5
OUT A
–IN A
+IN A
V–
V+
OP275
8
7
6
5
1
2
3
4
OUT A
–IN A
+IN A
V–
V+
2
OUT B
–IN B
+IN B
OP275
OUT B
–IN B
+IN B
3
4
SOIC-8 Package
APPLICATIONS
High Performance Audio
Active Filters
Fast Amplifiers
Integrators
GENERAL DESCRIPTION
Improved dc performance is also provided with bias and offset
currents greatly reduced over purely bipolar designs. Input off-
set voltage is guaranteed at 1 mV and is typically less than
200 µV. This allows the OP275 to be used in many dc coupled
or summing applications without the need for special selections
or the added noise of additional offset adjustment circuitry.
The OP275 is the first amplifier to feature the Butler Amplifier
front-end. This new front-end design combines both bipolar
and JFET transistors to attain amplifiers with the accuracy and
low noise performance of bipolar transistors, and the speed and
sound quality of JFETs. Total Harmonic Distortion plus Noise
equals that of previous audio amplifiers, but at much lower sup-
ply currents.
The output is capable of driving 600 Ω loads to 10 V rms while
maintaining low distortion. THD + Noise at 3 V rms is a low
0.0006%.
A very low l/f corner of below 6 Hz maintains a flat noise density
response. Whether noise is measured at either 30 Hz or 1 kHz,
it is only 6 nV/√Hz. The JFET portion of the input stage gives
the OP275 its high slew rates to keep distortion low, even when
large output swings are required, and the 22 V/µs slew rate of
the OP275 is the fastest of any standard audio amplifier. Best of
all, this low noise and high speed are accomplished using less
than 5 mA of supply current, lower than any standard audio
amplifier.
The OP275 is specified over the extended industrial (–40°C to
+85°C) temperature range. OP275s are available in both plastic
DIP and SOIC-8 packages. SOIC-8 packages are available in
2500 piece reels. Many audio amplifiers are not offered in
SOIC-8 surface mount packages for a variety of reasons; how-
ever, the OP275 was designed so that it would offer full perfor-
mance in surface mount packaging.
*Protected by U.S. Patent No. 5,101,126.
REV. A
© Analog Devices, Inc., 1995
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
OP275–SPECIFICATIONS
(@ VS = Ϯ15.0 V, TA = +25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
AUDIO PERFORMANCE
THD + Noise
VIN = 3 V rms,
RL = 2 kΩ, f = 1 kHz
f = 30 Hz
0.006
7
6
%
Voltage Noise Density
en
nV/√Hz
nV/√Hz
pA/√Hz
f = 1 kHz
Current Noise Density
Headroom
in
f = 1 kHz
THD + Noise ≤ 0.01%,
RL = 2 kΩ, VS = ±18 V
1.5
>12.9
dBu
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
1
mV
mV
nA
nA
nA
nA
V
–40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V, –40°C ≤ TA ≤ +85°C
VCM = 0 V
1.25
350
400
50
100
+10.5
Input Bias Current
Input Offset Current
100
100
2
IOS
VCM = 0 V, –40°C ≤ TA ≤ +85°C
2
Input Voltage Range
VCM
–10.5
Common-Mode Rejection Ratio
CMRR
VCM = ±10.5 V,
–40°C ≤ TA ≤ +85°C
RL = 2 kΩ
RL = 2 kΩ, –40°C ≤ TA ≤ +85°C
RL = 600 Ω
80
250
175
106
dB
Large Signal Voltage Gain
AVO
V/mV
V/mV
V/mV
µV/°C
200
2
Offset Voltage Drift
∆VOS/∆T
OUTPUT CHARACTERISTICS
Output Voltage Swing
VO
RL = 2 kΩ
RL = 2 kΩ, –40°C ≤ TA ≤ +85°C
RL = 600 Ω, VS = ±18 V
–13.5
–13
±13.9
±13.9
+14, –16
+13.5
+13
V
V
V
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = ±4.5 V to ±18 V
VS = ±4.5 V to ±18 V,
–40°C ≤ TA ≤ +85°C
VS = ±4.5 V to ±18 V, VO = 0 V,
RL = ∞, –40°C ≤ TA ≤ +85°C
VS = ±22 V, VO = 0 V, RL = ∞,
–40°C ≤ TA ≤ +85°C
85
80
111
4
dB
dB
mA
Supply Current
5
5.5
±22
mA
V
Supply Voltage Range
VS
±4.5
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Gain Bandwidth Product
Phase Margin
SR
RL = 2 kΩ
15
22
V/µs
kHz
MHz
Degrees
BWP
GBP
øm
9
62
Overshoot Factor
VIN = 100 mV, AV = +1,
RL = 600 Ω, CL = 100 pF
10
%
Specifications subject to change without notice.
–2–
REV. A
OP275
WAFER TEST LIMITS
Parameter
(@ VS = ؎15.0 V, TA = +25؇C unless otherwise noted)
Symbol
Conditions
Limit
Units
Offset Voltage
Input Bias Current
VOS
IB
IOS
VCM
CMRR
PSRR
AVO
VO
1
350
50
±10.5
80
mV max
nA max
nA max
V min
dB min
dB min
V/mV min
V min
VCM = 0 V
VCM = 0 V
Input Offset Current
Input Voltage Range1
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply Current
V
CM = ±10.5 V
V = ±4.5 V to ±18 V
RL = 2 kΩ
RL = 10 kΩ
85
250
±13.5
5
ISY
VO = 0 V, RL = ∞
mA max
NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1Guaranteed by CMRR test.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Model
Temperature Range Package Option
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ±7.5 V
Output Short-Circuit Duration to GND3 . . . . . . . . . Indefinite
Storage Temperature Range
OP275GP
OP275GS
OP275GSR –40°C to +85°C
OP275GBC +25°C
–40°C to +85°C
–40°C to +85°C
8-Pin Plastic DIP
8-Pin SOIC
SO-8 Reel, 2500 pcs.
DICE
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP275G . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C
DICE CHARACTERISTICS
4
Package Type
θJA
θJC
Units
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
103
158
43
43
°C/W
°C/W
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2For supply voltages greater than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
3Shorts to either supply may destroy the device. See data sheet for full details.
4θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for cerdip, P-DIP, and LCC packages; θJA is specified for device soldered in circuit
board for SOIC package.
Die Size 0.070 × 0.108 in. (7,560 sq. mils)
Substrate is connected to V–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP275 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
OP275–Typical Performance Curves
1500
1250
1000
750
500
250
0
25
T
R
= +25°C
= 2kΩ
V
V
= ±15V
= ±10V
40
30
20
180
A
S
20
V
T
= ±15V
L
O
S
135
90
15
+GAIN
= 2kΩ
= +25°C
A
+VOM
R
L
10
10
0
45
5
–GAIN
0
0
R
= 2kΩ
L
+GAIN
R
–10
–20
–30
–40
–45
–90
–135
–5
= 600Ω
L
–10
–15
–20
–25
–VOM
–GAIN
= 600Ω
R
L
–180
1M
FREQUENCY – Hz
10M
10k
100k
–50
–25
0
25
50
75
100
0
±5
±10
±15
±20
±25
TEMPERATURE – °C
SUPPLY VOLTAGE – V
Open-Loop Gain vs. Temperature
Closed-Loop Gain and Phase, AV = +1
Output Voltage Swing vs. Supply
Voltage
60
50
MARKER 15 309.059Hz
MAG (A/H)
60.115dB
V
T
= ±15V
= +25°C
60
50
40
S
V
T
= ±15V
S
40
30
V
T
= ±15V
50
40
30
20
10
0
S
A
A
= +100
= +25°C
VCL
A
= +25°C
A
A
= +1
VCL
20
A
= +10
135
90
VCL
30
20
A
A
= +10
= +1
VCL
VCL
10
A
= +100
VCL
MARKER 15 309.058Hz
PHASE (A/R 90.606Deg
10
45
0
0
0
–10
–20
–30
–10
–20
–45
–90
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
100M
1M
FREQUENCY – Hz
10M
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
Closed-Loop Output Impedance vs.
Frequency
Closed-Loop Gain vs. Frequency
Open-Loop Gain, Phase vs. Frequency
100
120
120
V
= ±15V
= 2kΩ
= +25°C
S
80
60
0
R
T
V
T
= ±15V
= +25°C
L
S
A
100
GAIN
100
80
60
40
20
0
A
+PSRR
45
80
40
90
Ø
= 58°
m
V
T
= ±15V
= +25°C
PHASE
S
A
20
135
180
225
270
60
40
20
0
0
–PSRR
–20
–40
–60
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Open-Loop Gain, Phase vs. Frequency
Power Supply Rejection vs.
Frequency
Common-Mode Rejection vs.
Frequency
–4–
REV. A
OP275
11
10
9
100
90
80
70
60
50
40
30
20
10
0
16
65
60
55
50
40
A
= +1
VCL
NEGATIVE EDGE
14
12
–VOM
Øm
10
8
A
= +1
VCL
POSITIVE EDGE
+VOM
GBW
6
4
2
0
V
= ±15V
S
8
R
V
= 2kΩ
T
= +25°C
L
A
= 100mV p-p
V
= ±15V
IN
S
7
–50
0
100
200
300
400
500
100
1k
LOAD RESISTANCE – Ω
10k
–25
0
25
50
75
100
TEMPERATURE – °C
LOAD CAPACITANCE – pF
Gain Bandwidth Product, Phase
Margin vs. Temperature
Small-Signal Overshoot vs. Load
Capacitance
Maximum Output Voltage vs. Load
Resistance
30
25
20
15
5.0
4.5
120
V
= ±15V
110
100
90
80
70
60
50
40
30
20
S
SINK
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
4.0
3.5
3.0
T
V
A
R
= +25°C
= ±15V
= +1
VCL
= 2kΩ
A
S
10
5
L
SOURCE
0
0
±5
±10
±15
±20
±25
1k
10k
100k
1M
10M
–50
–25
0
25
50
75
100
FREQUENCY – Hz
SUPPLY VOLTAGE – V
TEMPERATURE – °C
Maximum Output Swing vs.
Frequency
Supply Current vs. Supply Voltage
Short Circuit Current vs. Temperature
500
5
300
250
200
150
100
50
V
= ±15V
S
V
= ±15V
= +25°C
S
V
= ±15V
S
–40°C to +85°C
T
A
400
300
200
100
0
4
3
BASED ON 920 OP AMPS
2
1
0
–50
0
1
2
3
4
5
6
7
8
9
10
10
100
1k
100k
–25
0
25
50
75
100
TCV – µV/°C
OS
FREQUENCY – Hz
TEMPERATURE – °C
Current Noise Density vs. Frequency
TCVOS Distribution
Input Bias Current vs. Temperature
REV. A
–5–
OP275–Typical Performance Curves
50
45
40
35
30
25
20
10
200
V
T
= ±15V
= +25°C
T
V
= +25°C
= ±15V
BASED ON 920 OP AMPS
S
A
8
A
S
160
6
+0.1%
+0.01%
4
120
80
40
0
2
0
–SR
+SR
–2
–4
–6
–8
–10
–0.01%
–0.1%
0
100
200
300
400
500
0
100 200 300 400 500 600 700 800 900
SETTLING TIME – ns
–400–300–200
–500 –100
0
100 200
INPUT OFFSET VOLTAGE – µV
400
500
300
CAPACITIVE LOAD – pF
Slew Rate vs. Capacitive Load
Settling Time vs. Step Size
Input Offset (VOS) Distribution
40
50
45
40
35
30
25
20
V
= ±15V
= 2kΩ
35
30
25
20
15
10
5
S
V
R
= ±15V
= 2kΩ
S
R
T
L
–SR
L
= +25°C
A
+SR
0
0
.2
.4
.6
.8
1.0
–50
–25
0
25
50
TEMPERATURE – °C
75
100
DIFFERENTIAL INPUT VOLTAGE – V
Slew Rate vs. Temperature
Slew Rate vs. Differential Input Voltage
100
90
100
90
10
10
0%
0%
5V
200ns
5V
200ns
Negative Slew Rate
RL = 2 kΩ, VS = ±15 V, AV = +1
Positive Slew Rate
RL = 2 kΩ, VS = ±15 V, AV = +1
CH A: 80.0 µV FS
MKR: 6.23 nV/
10.0 µV/DIV
√
Hz
100
90
10
0%
50mV
100ns
0 Hz
MKR:
2.5 kHz
BW: 15.0 MHz
1 000 Hz
Small Signal Response
RL = 2 kΩ, VS = ±15 V, AV = +1
Voltage Noise Density vs. Frequency
VS = ±15 V
–6–
REV. A
OP275
0.010
APPLICATIONS
Short Circuit Protection
The OP275 has been designed with inherent short circuit pro-
tection to ground. An internal 30 Ω resistor, in series with the
V
R
= ±18V
= 600Ω
S
L
0.001
output, limits the output current at room temperature to ISC
+
= 40 mA and ISC– = –90 mA, typically, with ±15 V supplies.
However, shorts to either supply may destroy the device when
excessive voltages or currents are applied. If it is possible for a
user to short an output to a supply, for safe operation, the out-
put current of the OP275 should be design-limited to ±30 mA,
as shown in Figure 1.
0.0001
0.5
1
10
OUTPUT SWING – V rms
Figure 4. Headroom, THD + Noise vs. Output Amplitude
(V rms); RLOAD = 600 Ω, VSUP = ±18 V
Total Harmonic Distortion
Total Harmonic Distortion + Noise (THD + N) of the OP275
is well below 0.001% with any load down to 600 Ω. However,
this is dependent upon the peak output swing. In Figure 2 it is
seen that the THD + Noise with 3 V rms output is below
0.001%. In the following Figure 3, THD + Noise is below
0.001% for the 10 kΩ and 2 kΩ loads but increases to above
0.1% for the 600 Ω load condition. This is a result of the output
swing capability of the OP275. Notice the results in Figure 4,
showing THD vs. VIN (V rms). This figure shows that the THD
+ Noise remains very low until the output reaches 9.5 volts rms.
This performance is similar to competitive products.
The output of the OP275 is designed to maintain low harmonic
distortion while driving 600 Ω loads. However, driving 600 Ω
loads with very high output swings results in higher distortion if
clipping occurs. A common example of this is in attempting to
drive 10 V rms into any load with ±15 volt supplies. Clipping
will occur and distortion will be very high.
To attain low harmonic distortion with large output swings,
supply voltages may be increased. Figure 5 shows the perfor-
mance of the OP275 driving 600 Ω loads with supply voltages
varying from ±18 volts to ±20 volts. Notice that with ±18 volt
supplies the distortion is fairly high, while with ±20 volt supplies
it is a very low 0.0007%.
RFB
0.0001
FEEDBACK
RX
332Ω
V
A1
OUT
0.001
A1 = 1/2 OP275
R
V
= 600Ω
L
= 10 Vrms @ 1kHz
OUT
Figure 1. Recommended Output Short Circuit Protection
0.01
0.1
0
0.010
R
V
= 600Ω, 2k, 10k
= ±15V
= 3V rms
L
S
V
IN
A
= +1
V
±17
±18
±19
±20
±21
±22
0.001
SUPPLY VOLTAGE – V
0.0005
20
100
1k
FREQUENCY – Hz
10k
20k
Figure 5. THD + Noise vs. Supply Voltage
Noise
Figure 2. THD + Noise vs. Frequency vs. RLOAD
The voltage noise density of the OP275 is below 7 nV/√Hz from
30 Hz. This enables low noise designs to have good perfor-
mance throughout the full audio range. Figure 6 shows a typical
OP275 with a 1/f corner at 2.24 Hz.
1
600Ω
0.1
A
= +1
V
V
V
= ±18V
= 10V rms
S
CH A: 80.0 µV FS
MKR: 45.6 µV/
10.0 µV/DIV
√Hz
IN
0.010
0.001
80kHz FILTER
2k
10k
0.0001
20
100
1k
10k
20k
FREQUENCY – Hz
Figure 3. THD + Noise vs. RLOAD; VIN =10 V rms,
±18 V Supplies
0 Hz
MKR:
10 Hz
BW: 0.145 Hz
2.24 Hz
Figure 6. 1/f Noise Corner, VS = ±15 V, AV = 1000
REV. A
–7–
OP275
Noise Testing
this effect from occurring in noninverting applications. For these
applications, the fix is a simple one and is illustrated in Figure 9.
A 3.92 kΩ resistor in series with the noninverting input of the
OP275 cures the problem.
For audio applications the noise density is usually the most im-
portant noise parameter. For characterization the OP275 is
tested using an Audio Precision, System One. The input signal
to the Audio Precision must be amplified enough to measure it
accurately. For the OP275 the noise is gained by approximately
1020 using the circuit shown in Figure 7. Any readings on the
Audio Precision must then be divided by the gain. In imple-
menting this test fixture, good supply bypassing is essential.
R
FB*
V
OUT
V
IN
R
R
L
S
2kΩ
3.92kΩ
100Ω
909Ω
*R IS OPTIONAL
FB
A
Figure 9. Output Voltage Phase Reversal Fix
OP37
OP37
Overload, or Overdrive, Recovery
OP275
Overload, or overdrive, recovery time of an operational amplifier
is the time required for the output voltage to recover to a rated
output voltage from a saturated condition. This recovery time is
important in applications where the amplifier must recover
quickly after a large abnormal transient event. The circuit
shown in Figure 10 was used to evaluate the OP275’s overload
recovery time. The OP275 takes approximately 1.2 µs to recover
OUTPUT
B
909Ω
4.42kΩ
100Ω
490Ω
909Ω
100Ω
Figure 7. Noise Test Fixture
to VOUT = +10 V and approximately 1.5 µs to recover to VOUT
=
Input Overcurrent Protection
–10 V.
The maximum input differential voltage that can be applied to
the OP275 is determined by a pair of internal Zener diodes con-
nected across its inputs. They limit the maximum differential in-
put voltage to ±7.5 V. This is to prevent emitter-base junction
breakdown from occurring in the input stage of the OP275
when very large differential voltages are applied. However, in or-
der to preserve the OP275’s low input noise voltage, internal re-
sistances in series with the inputs were not used to limit the
current in the clamp diodes. In small signal applications, this is
not an issue; however, in applications where large differential
voltages can be inadvertently applied to the device, large tran-
sient currents can flow through these diodes. Although these di-
odes have been designed to carry a current of ±5 mA, external
resistors as shown in Figure 8 should be used in the event that
the OP275’s differential voltage were to exceed ±7.5 V.
R1
1kΩ
R2
10kΩ
2
1
A1
V
OUT
3
V
R
IN
R
L
S
4V p-p
@100Hz
2.43kΩ
909Ω
A1 = 1/2 OP275
Figure 10. Overload Recovery Time Test Circuit
Measuring Settling Time
The design of OP275 combines high slew rate and wide gain-
bandwidth product to produce a fast-settling (tS < 1 µs) ampli-
fier for 8- and 12-bit applications. The test circuit designed to
measure the settling time of the OP275 is shown in Figure 11.
This test method has advantages over false-sum node tech-
niques in that the actual output of the amplifier is measured, in-
stead of an error voltage at the sum node. Common-mode
settling effects are exercised in this circuit in addition to the slew
rate and bandwidth effects measured by the false-sum-node
method. Of course, a reasonably flat-top pulse is required as the
stimulus.
1.4kΩ
2
–
6
OP275
1.4kΩ
3
+
Figure 8. Input Overcurrent Protection
Output Voltage Phase Reversal
The output waveform of the OP275 under test is clamped by
Schottky diodes and buffered by the JFET source follower. The
signal is amplified by a factor of ten by the OP260 and then
Schottky-clamped at the output to prevent overloading the
oscilloscope’s input amplifier. The OP41 is configured as a fast
integrator which provides overall dc offset nulling.
Since the OP275’s input stage combines bipolar transistors for
low noise and p-channel JFETs for high speed performance, the
output voltage of the OP275 may exhibit phase reversal if either
of its inputs exceed its negative common-mode input voltage.
This might occur in very severe industrial applications where a
sensor, or system, fault might apply very large voltages on the
inputs of the OP275. Even though the input voltage range of the
OP275 is ±10.5 V, an input voltage of approximately –13.5 V
will cause output voltage phase reversal. In inverting amplifier
configurations, the OP275’s internal 7.5 V input clamping di-
odes will prevent phase reversal; however, they will not prevent
High Speed Operation
As with most high speed amplifiers, care should be taken with
supply decoupling, lead dress, and component placement. Rec-
ommended circuit configurations for inverting and noninverting
applications are shown in Figures 12 and Figure 13.
–8–
REV. A
OP275
16–20V
–
+
+15V
1kΩ
OUTPUT
(TO SCOPE)
0.1µF
R
L
D3
D4
V+
DUT
V–
1kΩ
2N4416
1/2 OP260AJ
1µF
D1
D2
0.1µF
R
F
2kΩ
10kΩ
10kΩ
+
–
IC2
16–20V
R
G
222Ω
±5V
2N2222A
750Ω
1N4148
15kΩ
SCHOTTKY DIODES D1–D4 ARE
HEWLETT-PACKARD HP5082-2835
IC1 IS 1/2 OP260AJ
–15V
IC2 IS PMI OP41EJ
Figure 11. OP275’s Settling Time Test Fixture
C
FB
+15V
R
FB
10µF
+
0.1µF
V
R
C
S
C
OUT
S
IN
2
3
8
1/2
1
V
OUT
OP275
V
IN
R
L
4
0.1µF
2kΩ
10µF
+
Figure 14. Compensating the Feedback Pole
Attention to Source Impedances Minimizes Distortion
Since the OP275 is a very low distortion amplifier, careful atten-
tion should be given to source impedances seen by both inputs.
As with many FET-type amplifiers, the p-channel JFETs in the
OP275’s input stage exhibit a gate-to-source capacitance that
varies with the applied input voltage. In an inverting configura-
tion, the inverting input is held at a virtual ground and, as such,
does not vary with input voltage. Thus, since the gate-to-source
voltage is constant, there is no distortion due to input capaci-
tance modulation. In noninverting applications, however, the
gate-to-source voltage is not constant. The resulting capacitance
modulation can cause distortion above 1 kHz if the input im-
pedance is > 2 kΩ and unbalanced.
–15V
Figure 12. Unity Gain Follower
+15V
10µF
+
0.1µF
10pF
V
IN
4.99kΩ
4.99kΩ
2
3
8
1/2
OP275
1
V
OUT
Figure 15 shows some guidelines for maximizing the distortion
performance of the OP275 in noninverting applications. The
best way to prevent unwanted distortion is to ensure that the
parallel combination of the feedback and gain setting resistors
(RF and RG) is less than 2 kΩ. Keeping the values of these resis-
tors small has the added benefits of reducing the thermal noise
2kΩ
4
2.49kΩ
10µF
+
0.1µF
–15V
R
R
G
F
Figure 13. Unity Gain Inverter
In inverting and noninverting applications, the feedback resis-
tance forms a pole with the source resistance and capacitance
(RS and CS) and the OP275’s input capacitance (CIN), as shown
in Figure 14. With RS and RF in the kilohm range, this pole can
create excess phase shift and even oscillation. A small capacitor,
CFB, in parallel and RFB eliminates this problem. By setting RS
(CS + CIN) = RFBCFB, the effect of the feedback pole is com-
pletely removed.
0P275
V
R
OUT
S*
V
IN
* R = R //R IF R //R > 2kΩ
S
G
F
G
F
FOR MINIMUM DISTORTION
Figure 15. Balanced Input Impedance to Minimize
Distortion in Noninverting Amplifier Circuits
REV. A
–9–
OP275
of the circuit and dc offset errors. If the parallel combination of
RF and RG is larger than 2 kΩ, then an additional resistor, RS,
should be used in series with the noninverting input. The value
of RS is determined by the parallel combination of RF and RG to
maintain the low distortion performance of the OP275.
importance. Like the transformer based design, either output
can be shorted to ground for unbalanced line driver applications
without changing the circuit gain of 1. Other circuit gains can be
set according to the equation in the diagram. This allows the
design to be easily set to noninverting, inverting, or differential
operation.
Driving Capacitive Loads
The OP275 was designed to drive both resistive loads to 600 Ω
and capacitive loads of over 1000 pF and maintain stability.
While there is a degradation in bandwidth when driving capaci-
tive loads, the designer need not worry about device stability.
The graph in Figure 16 shows the 0 dB bandwidth of the OP275
with capacitive loads from 10 pF to 1000 pF.
A 3-Pole, 40 kHz Low-Pass Filter
The closely matched and uniform ac characteristics of the
OP275 make it ideal for use in GIC (Generalized Impedance
Converter) and FDNR (Frequency-Dependent Negative Resis-
tor) filter applications. The circuit in Figure 18 illustrates a lin-
ear-phase, 3-pole, 40 kHz low-pass filter using an OP275 as an
inductance simulator (gyrator). The circuit uses one OP275 (A2
and A3) for the FDNR and one OP275 (A1 and A4) as an input
buffer and bias current source for A3. Amplifier A4 is config-
ured in a gain of 2 to set the pass band magnitude response to
0 dB. The benefits of this filter topology over classical ap-
proaches are that the op amp used in the FDNR is not in the
signal path and that the filter’s performance is relatively insensi-
tive to component variations. Also, the configuration is such that
large signal levels can be handled without overloading any of the
the filter’s internal nodes. As shown in Figure 19, the OP275’s
symmetric slew rate and low distortion produce a clean, well-
behaved transient response.
10
9
8
7
6
5
4
3
2
1
0
R1
95.3kΩ
0
200
400
600
800
1000
C1
2200pF
2
CLOAD – pF
1
A1
3
V
IN
Figure 16. Bandwidth vs. CLOAD
High Speed, Low Noise Differential Line Driver
R2
787Ω
R6
4.12kΩ
5
7
A4
V
OUT
C4
2200pF
C2
2200pF
The circuit of Figure 17 is a unique line driver widely used in
industrial applications. With ±18 V supplies, the line driver can
deliver a differential signal of 30 V p-p into a 2.5 kΩ load. The
high slew rate and wide bandwidth of the OP275 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
density of 10 nV/√Hz.
6
R7
100kΩ
5
6
7
A3
R3
1.82kΩ
R8
1kΩ
R9
1kΩ
2
3
1
A2
C3
2200pF
R4
1.87kΩ
R3
2k
A1, A4 = 1/2 OP275
A2, A3 = 1/2 OP275
R9
50
R5
1.82kΩ
2
1
VO1
A2
3
R11
1k
R1
2k
R7
2k
Figure 18. A 3-Pole, 40 kHz Low-Pass Filter
R4
2k
V
– V = V
O1
3
2
O2
IN
V
IN
1
P1
10k
A1
R5
2k
100
90
R6
2k
R2
2k
R12
1k
V
OUT
R10
50
10Vp-p
10kHz
6
5
7
A3
V
O2
A1 = 1/2 OP275
R8
2k
10
A2, A3 = 1/2 OP275
R3
GAIN =
R1
0%
SET R2, R4, R5 = R1 AND R6, R7, R8 = R3
SCALE: VERTICAL–2V/ DIV
HORIZONTAL–10µs/ DIV
Figure 17. High Speed, Low Noise Differential Line Driver
The design is a transformerless, balanced transmission system
where output common-mode rejection of noise is of paramount
Figure 19. Low-Pass Filter Transient Response
–10–
REV. A
OP275
OP275 SPICE Model
*
* POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz
*
* Node assignments
*
*
*
R8
R9
C4
G2
*
21
21
22
98
98
22
98
21
1E-3
noninverting input
inverting input
positive supply
negative supply
1.25E-3
47.2E-12
18
28
28
28
1E-3
*
*
*
*
output
* POLE AT 100 MHz
*
R10
C5
G3
*
23
23
98
98
98
23
1
.SUBCKT OP275
*
* INPUT STAGE & POLE AT 100 MHz
*
R3
R4
CIN
CM1
CM2
C2
1
2
99
50 34
1.59E-9
21
1
* POLE AT 100 MHz
*
5
6
1
1
2
5
97
1
9
5
6
7
8
2
1
3
0
0
51
51
2
98
98
6
4
2
3
2
9
4
4
36
36
1
2
1
2.188
2.188
R11
C6
G4
*
24
24
98
98
98
24
1
3.7E-12
7.5E-12
7.5E-12
364E-12
100E-3
1E-9
POLY(1) 26
7
8
1.672
1.672
DZ
DZ
10
13
16
1.59E-9
23
1
* COMMON-MODE GAIN NETWORK WITH ZERO AT
I1
1 kHz
*
R12
C7
R13
E2
*
IOS
EOS
Q1
Q2
R5
R6
D1
D2
EN
GN1
GN2
*
28 0.5E-3 1
25
25
26
25
26
26
98
98
1E6
1.5915E-12
1
QX
QX
POLY(2)
1
98
2
98
0
2.50 2.50
* POLE AT 100 MHz
*
0
0
0
1
1E-3
1E-3
R14
C8
G5
*
27
27
98
98
98
27
1
1.59E-9
24
28
1
0
0
0
28
99
50
0
0
0
1
1
1
* OUTPUT STAGE
*
R15
R16
C9
ISY
R17
R18
L2
G6
G7
G8
G9
V4
V5
F1
F2
D5
D6
D7
D8
D9
D10
*
28
28
28
99
29
29
29
32
33
29
50
30
29
29
0
27
31
99
99
50
50
99
50
50
50
99
50
34
50
50
99
29
29
31
0
29
30
27
32
33
32
33
100E3
100E3
1E-6
1.85E-3
100
100
1E-9
27
29
99
27
1.3
3.8
V4
V5
DX
DX
DX
DX
DY
10
11
0
DEN
DEN
DC
2
2
11
DC
29
27
27
50
10E-3
10E-3
10E-3
10E-3
13
14
0
DIN
DIN
DC
2
2
1
1
14
DC
16
17
0
DIN
DIN
DC
2
2
DY
17
DC
* MODELS USED
*
.MODEL QX
.MODEL DX
.MODEL DY
.MODEL DZ
PNP(BF=5E5)
D(IS=1E-12)
D(IS=1E-15 BV=50)
D(IS=1E-15 BV=7.0)
98
98
18
19
51
19
18
1.09E6
4.55E-9
5
1.35
1.35
DX
6
4.57E-1
.MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1)
.MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1)
.ENDS
DX
REV. A
–11–
OP275
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Narrow-Body SOIC
(S Suffix)
8-Lead Epoxy DIP
(P Suffix)
0.1968 (5.00)
0.1890 (4.80)
0.430 (10.92)
0.348 (8.84)
8
1
5
4
8
5
4
0.280 (7.11)
0.240 (6.10)
0.2440 (6.20)
0.1574 (4.00)
0.1497 (3.80)
0.2284 (5.80)
1
0.325 (8.25)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
x 45°
0.0099 (0.25)
0.130
(3.30)
MIN
0.0098 (0.25)
0.0040 (0.10)
0.160 (4.06)
0.115 (2.93)
8°
0°
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.0500 0.0192 (0.49)
0.0500 (1.27)
0.0160 (0.41)
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
(1.27)
0.0138 (0.35)
BSC
–12–
REV. A
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