OP282GS [ADI]
Dual/Quad Low Power, High Speed JFET Operational Amplifiers; 双/四通道，低功耗，高速JFET运算放大器
| 型号： | OP282GS |
| 厂家： | 
ADI |
| 描述： | Dual/Quad Low Power, High Speed JFET Operational Amplifiers |
| 文件： | 总12页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual/Quad Low Power, High Speed
JFET Operational Amplifiers
a
OP282/OP482
P IN CO NNECTIO NS
FEATURES
8-Lead Nar r ow-Body SO IC
(S Suffix)
8-Lead Epoxy D IP
(P Suffix)
High Slew Rate: 9 V/ s
Wide Bandw idth: 4 MHz
Low Supply Current: 250 A/ Am plifier
Low Offset Voltage: 3 m V
Low Bias Current: 100 pA
Fast Settling Tim e
1
2
3
4
8
7
6
5
V+
V+
1
2
3
4
8
7
6
5
OUT A
–IN A
+IN A
V–
OUT A
–IN A
+IN A
V–
OP282
OUT B
–IN B
OUT B
–IN B
OP282
Com m on-Mode Range Includes V+
Unity Gain Stable
+IN B
+IN B
APPLICATIONS
Active Filters
Fast Am plifiers
Integrators
14-Lead Epoxy D IP
(P Suffix)
14-Lead Nar r ow-Body SO IC
(S Suffix)
Supply Current Monitoring
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
1
2
3
4
5
6
7
14
13
12
11
10
9
14
OUT A
–IN A
+IN A
V+
OUT B
1
2
3
4
5
6
7
13 –IN D
+IN D
12
GENERAL D ESCRIP TIO N
OP482
V–
11
10
9
V–
OP482
T he OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. Slew rate
exceeds 7 V/µs with supply current under 250 µA per amplifier.
T hese unity gain stable amplifiers have a typical gain bandwidth
of 4 MHz.
+IN C
+IN B
–IN B
OUT B
+IN C
+IN B
–IN B
OUT B
–IN C
–IN C
OUT C
8
OUT C
8
T he JFET input stage of the OP282/OP482 insures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 volts of each supply, low
power consumption and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power restricted applica-
tions. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for high-
side signal conditioning.
T he OP282/OP482 are specified over the extended industrial
temperature range. Both dual and quad amplifiers are available
in plastic and ceramic DIP plus SOIC surface mount packages.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
OP282/OP482–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = ؎15.0 V, T = +25؇C unless otherwise noted)
S
A
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
VOS
IB
OP282
OP282, –40 ≤ T A ≤ +85°C
OP482
OP482, –40 ≤ T A ≤ +85°C
VCM = 0 V
VCM = 0 V, Note 1
VCM = 0 V
0.2
0.2
3
3
4.5
4
mV
mV
mV
mV
pA
Offset Voltage
6
Input Bias Current
Input Offset Current
100
500
50
pA
pA
IOS
1
VCM = 0 V, Note 1
250
+15
pA
V
dB
V/mV
V/mV
µV/°C
pA/°C
Input Voltage Range
–11
70
20
Common-Mode Rejection
Large Signal Voltage Gain
CMR
AVO
–11 V ≤ VCM ≤ +15 V, –40 ≤ T A ≤ +85°C
RL = 10 kΩ
RL = 10 kΩ, –40 ≤ T A ≤ +85°C
90
15
Offset Voltage Drift
Bias Current Drift
∆VOS/∆T
∆IB/∆T
10
8
OUT PUT CHARACT ERIST ICS
Output Voltage Swing
Short Circuit Limit
VO
ISC
RL = 10 kΩ
Source
Sink
–13.5 ±13.9 13.5
V
3
10
mA
mA
Ω
–8
–12
200
Open-Loop Output Impedance
ZOUT
f = 1 MHz
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
VS = ±4.5 V to ±18 V,
–40 ≤ T A ≤ +85°C
25
210
316
250
±18
µV/V
µA
V
Supply Current/Amplifier
Supply Voltage Range
ISY
VS
VO = 0 V, 40 ≤ T A ≤ +85°C
±4.5
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling T ime
Gain Bandwidth Product
Phase Margin
SR
BWP
tS
GBP
ØO
RL = 10 kΩ
1% Distortion
T o 0.01%
7
9
V/µs
kHz
µs
MHz
Degrees
125
1.6
4
55
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
1.3
36
0.01
µV p-p
nV/√Hz
pA/√Hz
Current Noise Density
NOT E
1T he input bias and offset currents are tested at T A = TJ = +85°C. Bias and offset currents are guaranteed but not tested at –40 °C.
Specifications subject to change without notice.
WAFER TEST LIMITS (@ V = ؎15.0 V, T = +25؇C unless otherwise noted)
S
A
P aram eter
Sym bol
Conditions
Lim it
Units
Offset Voltage
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range1
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Range
Supply Current/Amplifier
VOS
VOS
IB
OP282
OP482
VCM = 0 V
VCM = 0 V
3
4
mV max
mV max
pA max
pA max
V min/max
dB min
µV/V
V/mV min
V min
µA max
100
50
–11, +15
70
316
20
IOS
CMRR
PSRR
AVO
VO
ISY
–11 V ≤ VCM ≤ +15 V
V = ±4.5 V to ±18 V
RL = 10 kΩ
RL = 10 kΩ
VO = 0 V, RL = ∞
±13.5
250
NOT ES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1Guaranteed by CMR test.
Specifications subject to change without notice.
REV. B
–2–
OP282/OP482
ABSO LUTE MAXIMUM RATINGS
D ICE CH ARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . 36 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage T emperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range
OP282A, OP482A . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP282G, OP482G . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction T emperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead T emperature Range (Soldering, 60 sec) . . . . . . +300°C
2
P ackage Type
JA
JC
Units
OP282 Die Size 0.063 ϫ 0.060 Inch, 3,780 Sq. Mils
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
14-Pin Plastic DIP (P)
14-Pin SOIC (S)
103
158
83
43
43
39
36
°C/W
°C/W
°C/W
°C/W
120
NOT ES
1For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
2θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for cerdip, P-DIP; θJA is specified for device soldered in circuit board for
SOIC package.
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
OP282GP
OP282GS
OP482GP
OP482GS
–40°C to +85°C 8-Pin Plastic DIP N-8
–40°C to +85°C 8-Pin SOIC
SO-8
–40°C to +85°C 14-Pin Plastic DIP N-14
–40°C to +85°C 14-Pin SOIC
SO-14
OP482 Die Size 0.070 ϫ 0.098 Inch, 6,860 Sq. Mils
REV. B
–3–
OP282/OP482
AP P LICATIO NS INFO RMATIO N
P H ASE INVERSIO N
T he OP282 and OP482 are single and dual JFET op amps that
have been optimized for high speed at low power. T his
combination makes these amplifiers excellent choices for battery
powered or low power applications requiring above average
performance. Applications benefiting from this performance
combination include telecom, geophysical exploration, portable
medical equipment and navigational instrumentation.
Most JFET -input amplifiers will invert the phase of the input
signal if either input exceeds the input common-mode range.
For the OP282 and OP482 negative signals in excess of approxi-
mately 14 volts will cause phase inversion. T he cause of this
effect is saturation of the input stage leading to the forward-
biasing of a drain-gate diode. A simple fix for this in noninverting
applications is to place a resistor in series with the noninverting
input. T his limits the amount of current through the forward-
biased diode and prevents the shutting down of the output
stage. For the OP282/OP482, a value of 200 kΩ has been found
to work. However, this adds a significant amount of noise.
H IGH SID E SIGNAL CO ND ITIO NING
T here are many applications that require the sensing of signals
near the positive rail. OP282s and OP482s have been tested and
guaranteed over a common-mode range (–11 V ≤ VCM ≤ +15 V)
that includes the positive supply.
15
One application where this is commonly used is in the sensing of
power supply currents. T his enables it to be used in current
sensing applications such as the partial circuit shown in Figure
1. In this circuit, the voltage drop across a low value resistor,
such as the 0.1 Ω shown here, is amplified and compared to 7.5
volts. T he output can then be used for current limiting.
10
5
0
+15V
0.1Ω
-5
500k
-10
-15
100k
R
L
100k
100k
-15
5
-10
-5
10
0
15
V
OUT
1/2
OP282
+
Figure 2. OP282 Phase Reversal
ACTIVE FILTERS
T he OP282 and OP482’s wide bandwidth and high slew rates
make either an excellent choice for many filter applications.
Figure 1. Phase Inversion
T here are many types of active filter configurations, but the four
most popular configurations are Butterworth, elliptical, Bessel,
and Chebyshev. Each type has a response that is optimized for a
given characteristic as shown in T able I.
P RO GRAMMABLE STATE-VARIABLE FILTER
Table I.
Am plitude
Am plitude
Type
Selectivity O vershoot
P hase
(P ass Band)
(Stop Band)
Butterworth
Chebyshev
Elliptical
Moderate
Good
Best
Good
Moderate
Poor
Max Flat
Nonlinear Equal Ripple
Equal Ripple
Equal Ripple
Bessel (T hompson)
Poor
Best
Linear
–4–
REV. B
OP282/OP482
T he circuit shown in Figure 3 can be used to accurately
program the “Q,” the cutoff frequency fC, and the gain of a two
pole state-variable filter. OP482s have been used in this design
because of their high bandwidths, low power and low noise.
T his circuit takes only three packages to build because of the
quad configuration of the op amps and DACs.
D1
1
fc =
2πR1C1 256
where D1 is the digital code for the DAC.
Gain of this circuit is set by adjusting D3. T he gain equation is:
R4 D3
T he DACs shown are all used in the voltage mode so all values
are dependent only on the accuracy of the DAC and not on the
absolute values of the DAC’s resistive ladders. T his make this
circuit unusually accurate for a programmable filter.
Gain =
R5 256
DAC 2 is used to set the “Q” of the circuit. Adjusting this DAC
controls the amount of feedback from the bandpass node to the
input summing node. Note that the digital value of the DAC is
in the numerator, therefore zero code is not a valid operating point.
Adjusting DAC 1 changes the signal amplitude across R1;
therefore, the DAC attenuation times R1 determines the
amount of signal current that charges the integrating capacitor,
C1. T his cutoff frequency can now be expressed as:
R2 256
Q =
R3 D2
R7
2k
1/4
DAC8408
R4
2k
1/4
DAC8408
C1
1000pF
1/4
DAC8408
C1
1000pF
V
IN
R5
2k
-
+
R1
2k
-
+
-
+
R1
2k
-
+
1/4
OP482
-
+
1/4
OP482
-
+
1/4
OP482
1/4
OP482
1/4
OP482
LOW
PASS
1/4
OP482
HIGH PASS
R6
2k
1/4
DAC8408
R3
2k
BANDPASS
R2
1k
-
-
+
+
1/4
OP482
1/4
OP482
Figure 3.
REV. B
–5–
OP282/OP482
minor changes in the circuit values. Contact ADI for a copy of
the latest SPICE model diskette for both listings.
O P 282/O P 482 SP ICE MACRO MO D EL
Figure 4 shows the OP282 SPICE macro model. T he model for
the OP482 is similar to that of the OP282, but there are some
99
I1
V2
8
4
D1
9
IN-
2
J1
5
J2
R5
G1
7
C3
R2
3
CIN
IOS
EOS
C2
98
6
R1
1
D2
V3
EREF
10
IN+
R3 R4
50
C4
C14
13
14
19
11
E2
12
20
E13
21
G2
G3
G11
R6
R21
C13
C5
C6
R8
R9
R19
R22
R7
98
99
D6
D5
ISY
R27
G19
R25
24
V4
D3
25
23
R23
L5
29
30
VOUT
G15
C15
V5
98
26
D4
R28
27
28
G20
R26
G18
G17
D7
D8
50
Figure 4.
–6–
REV. B
OP282/OP482
O P 282 SP ICE MACRO MO D EL
*
* Node assignments
* COMMON-MODE GAIN NET WORK
*
*
*
*
*
*
noninverting input
inverting input
positive supply
negative supply
WIT H ZERO AT 11 KHZ
*
R21
R22
C14
E13
*
20
21
20
98
21
98
21
20
1E6
1
14.38E-12
3
output
24 31.62
24 1E-6
.SUBCKT OP282
*
* INPUT ST AGE & POLE AT 15 MHZ
*
1
2
99
50
30
* POLE AT 15 MHZ
*
R23
C15
G15
*
23
23
98
98
98
23
1E6
10.6E-15
19
R1
R2
R3
R4
CIN
C2
I1
IOS
EOS
J1
1
2
5
6
1
5
99
1
7
5
3
3
50
50
2
6
4
2
1
5E11
5E11
3871.3
3871.3
5E-12
1.37E-12
0.1E-3
5E-13
* OUT PUT ST AGE
*
R25
R26
ISY
R27
R28
L5
G17
G18
G19
G20
V4
V5
D3
D4
D5
D6
D7
D8
24
24
99
29
29
29
27
28
29
50
25
29
23
26
99
99
50
50
99
50
50
99
50
30
50
50
99
29
29
26
25
23
27
28
27
28
5E6
5E6
107E-6
700
700
1E-8
23
29
99
23
2.8
POLY(1) 21 24 200E-6 1
2
7
4
4
JX
JX
J2
*
6
29 1.43E-3
23 1.43E-3
23 1.43E-3
50 1.43E-3
EREF 98
*
* GAIN ST AGE & POLE AT 124 HZ
*
R5
C3
G1
V2
V3
D1
D2
*
0
24
0 1
9
9
98
99
10
9
98
98
9
8
50
8
1.16E8
1.11E-11
5 6
3.5
DX
DX
DX
DX
DY
DY
2.58E-4
1.2
1.2
DX
DX
10
9
*
* NEGAT IVE ZERO AT 4 MHZ
*
* MODELS USED
*
R6
R7
C4
E2
*
11
12
11
11
12
98
12
98
1E6
1
39.8E-15
9
.MODEL JX PJF(BET A = 3.34E-4
VT O = –2.000 IS = 3E-12)
.MODEL DX D(IS = 1E-15)
.MODEL DY D(IS = 1E-15 BV = 50)
.ENDS OP282
24 1E6
24 1E-6
24 1E-6
24 1E-6
* POLE AT 15 MHZ
*
R8
C5
G2
*
* POLE AT 15 MHZ
*
R9
C6
G3
*
* POLE AT 15 MHZ
*
R19
C13
G11
13
13
98
98
98
13
1E6
10.6E-15
12
14
14
98
98
98
14
1E6
10.6E-15
13
19
19
98
98
98
19
1E6
10.6E-15
14
REV. B
–7–
OP282/OP482
0
35
30
25
80
60
40
20
0
70
60
50
40
30
20
10
0
T
V
= +25°C
= ±15V
V
= ±15V
A
= +1
A
S
VCL
NEGATIVE EDGE
V
= ±15V
S
S
R
V
= 2k
Ω
= 100mV p-p
L
R = 10k
L
45
90
135
180
IN
A
= +1
20
15
10
5
VCL
POSITIVE EDGE
0
100
200
300
500
400
1k
10k
100k
1M
10M 100M
0
25
50 75 100 125
–75 –50 –25
LOAD CAPACITANCE – pF
FREQUENCY – Hz
TEMPERATURE – °C
Figure 5. Open-Loop Gain, Phase
vs. Frequency
Figure 8. Open-Loop Gain (V/m V)
Figure 11. Sm all Signal Overshoot
vs. Load Capacitance
25
60
1000
T
V
= +25°C
= ±15V
A
V
V
= ±15V
= 0
S
– SR
50
40
S
A
= +100
= +10
CM
VCL
20
100
10
V = ±15V
S
R = 10k
L
30
C = 50pF
L
15
10
5
A
VCL
20
10
A
= +1
VCL
+ SR
0
1.0
0.1
–10
–20
1k
10k
100k
1M
10M
100M
–75 –50 –25
0
25
50 75 100 125
0
25
50 75 100 125
–50 –25
TEMPERATURE –°C
FREQUENCY – Hz
TEMPERATURE – °C
Figure 6. Closed-Loop Gain vs.
Frequency
Figure 9. OP282/OP482 Slew Rate
vs. Tem perature
Figure 12. OP282 Input Bias Current
vs. Tem perature
50
4.5
4.0
3.5
3.0
60
80
1000
V = ±15V
S
V
T
= ±15V
= +25°C
V
= ±15V
S
S
70
60
R
= 10k
L
T
= +25°C
A
A
55
50
45
40
100
10
1
50
40
GBW
Ø
M
30
20
10
0
0.1
–15
–75 –50 –25
0
25 50
75 100 125
–10
–5
5
10
15
0
10
100
FREQUENCY – Hz
10k
1k
COMMON - MODE VOLTAGE – V
TEMPERATURE – °C
Figure 7. OP482 Phase Margin and
Gain Bandwidth Product vs.
Tem perature
Figure 13. OP282 Input Bias Current
vs. Com m on-Mode Voltage
Figure 10. Voltage Noise Density
vs. Frequency
–8–
REV. B
OP282/OP482
1.15
1.10
1.05
20
15
10
5
600
500
400
300
200
100
0
T
= +25°C
A
T
= +25°C
= ±15V
A
R
= 10kΩ
L
V
S
T
= +25°C
A
A
= 1000
VCL
1.00
0.95
0.90
0.85
0
–5
–10
A
A
= +10
= 1
VCL
A
= 100
VCL
–15
–20
VCL
0
±5
±10
±15
±20
0
±5
±10
±15
±20
100
1k
10k
100k
1M
SUPPLY VOLTAGE – Volts
SUPPLY VOLTAGE – Volts
FREQUENCY – Hz
Figure 17. Output Voltage Swing
vs. Supply Voltage
Figure 14. Relative Supply Current
vs. Supply Voltage
Figure 20. OP482 Closed-Loop Out-
put Im pedance vs. Frequency
100
1.20
16
V
= ±15V
S
∆
T
V = 100mV
= +25
T
V
= +25°C
= ±15V
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
V
= ±15
SUP
14
12
10
8
A
S
+ PSRR
– PSRR
°C
80
60
40
20
0
A
POSITIVE
SWING
NEGATIVE
SWING
6
4
2
–20
100
0
1k
10k
100k
1M
–75 –50 –25
0
25 50 75 100 125
100
1k
LOAD RESISTANCE – Ω
10k
TEMPERATURE – °C
FREQUENCY – Hz
Figure 15. Relative Supply Current
vs. Tem perature
Figure 21. OP282 Power Supply
Rejection Ratio (PSRR) vs. Frequency
Figure 18. Maxim um Output Voltage
vs. Load Resistance
20
30
100
T
V
A
R
= +25°C
= ±15V
= +1
A
S
V
= ±15V
S
V = ±15V
S
25
20
15
10
5
80
SINK
VCL
V
= 100mV
CM
15
10
5
Ω
= 10k
L
T
= +25°C
A
60
40
SOURCE
20
0
0
–20
100
–75 –50 –25
0
25
50 75 100 125
10k
100k
1M
1k
1k
10k
100k
1M
TEMPERATURE – °C
FREQUENCY – Hz
FREQUENCY – Hz
Figure 19. Maxim um Output Swing
vs. Frequency
Figure 16. OP282/OP482 Short
Circuit Current vs. Tem perature
Figure 22. OP282 Com m on-Mode
Rejection Ratio (CMRR) vs. Frequency
REV. B
–9–
OP282/OP482
320
280
240
200
160
120
80
700
600
500
400
300
200
100
0
280
240
200
V = ±15V
S
V
= ±15V
S
T = +25°C
-40°C ≤T ≤ +125
°
C
A
A
×
×
315 OP282
300 OP482
1200 OP AMPS
(630 OP AMPS )
160
120
80
40
40
0
0
0
4
8
12 16 20
24 28 32
-2000 -1600 -1200 -800 -400
0
400 800 1200 1600 2000
0
4
8
12 16
20 24 28
32
TCV – µV/°C
V
– µV
TCV – µV/°C
OS
OS
OS
Figure 25. OP282 TCVOS (µV/°C)
Distribution "P" Package
Figure 23. VOS Distribution "P"
Package
Figure 27. OP482 TCVOS Distribution
"Z" Package
280
700
320
280
240
200
160
120
80
V
T
= ±15V
S
V
= ±15V
S
240
200
160
120
80
= +25°C
×
600
500
400
300
200
100
0
A
≤
≤
+85°C
-40°C
T
320 OP282
(640 OP AMPS)
A
×
300 OP482
1200 OP AMPS
40
40
0
0
–2000 –1600 –1200 –800–400
0
4
8
12
16 20 24
28 32
0
400 800 1200 1600 2000
0
4
8
12 16
20 24 28
32
V
OS
– µV
TCV – µV/°C
TCV – µV/°C
OS
OS
Figure 24. VOS Distribution "Z"
Package
Figure 26. OP282 TCVOS (µV/°C)
Distribution "Z" Package
Figure 28. TCVOS Distribution "P"
Package
700
600
700
600
500
400
300
200
100
0
T
V
= +25°C
= ±15V
A
T
V
= +25°C
A
S
= ±15V
S
300 ϫ OP482
1200 OP AMPS
300 ϫ OP482
1200 OP AMPS
500
400
300
200
100
0
–2000–1600 –1200–800 –400
0
400 800 1200 1600 2000
–2000 –1600–1200 –800 –400
0
400 800 1200 1600 2000
V – µV
OS
V
– µV
OS
Figure 29. OP482 VOS Distribution “Z”
Package
Figure 30. OP482 VOS Distribution “P”
Package
–10–
REV. B
OP282/OP482
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead Nar r ow-Body SO IC
(S Suffix)
8-Lead Epoxy D IP
(P Suffix)
14-Lead Nar r ow-Body SO IC
(S Suffix)
14-Lead Epoxy D IP
(P Suffix)
20-P osition Chip Car r ier
(RC Suffix)
REV. B
–11–
REV. B
–12–
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