OP293FS-REEL [ADI]
Precision, Micropower Operational Amplifiers; 高精度，微功耗运算放大器
| 型号： | OP293FS-REEL |
| 厂家： | 
ADI |
| 描述： | Precision, Micropower Operational Amplifiers |
| 文件： | 总16页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision, Micropower
Operational Amplifiers
a
OP193/OP293/OP493*
P IN CO NFIGURATIO NS
FEATURES
Operates from +1.7 V to ؎18 V
Low Supply Current: 15 A/ Am plifier
Low Offset Voltage: 75 V
Outputs Sink and Source: ؎8 m A
No Phase Reversal
Single or Dual Supply Operation
High Open-Loop Gain: 600 V/ m V
Unity-Gain Stable
8-Lead SO
(S Suffix)
8-Lead Epoxy D IP
(P Suffix)
NULL
–IN A
+IN A
V–
NC
NULL
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
NC
OP193
V+
OP193
V+
OUT A
NULL
OUT A
NULL
APPLICATIONS
NC = NO CONNECT
Digital Scales
Strain Gages
Portable Medical Equipm ent
Battery Pow ered Instrum entation
Tem perature Transducer Am plifier
8-Lead SO
(S Suffix)
8-Lead Epoxy D IP
(P Suffix)
OUT A
–IN A
+IN A
V–
V+
GENERAL D ESCRIP TIO N
V+
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
OP293
OUT B
–IN B
+IN B
T he OP193 family of single-supply operational amplifiers fea-
tures a combination of high precision, low supply current and
the ability to operate at low voltages. For high performance in
single supply systems the input and output ranges include
ground, and the outputs swing from the negative rail to within
600 mV of the positive supply. For low voltage operation the
OP193 family can operate down to 1.7 volts or ±0.85 volts.
OP293
OUT B
–IN B
+IN B
16-Lead Wide Body SO L
(S Suffix)
14-Lead Epoxy D IP
(P Suffix)
T he combination of high accuracy and low power operation
make the OP193 family useful for battery powered equipment.
Its low current drain and low voltage operation allow it to con-
tinue performing long after other amplifiers have ceased func-
tioning either because of battery drain or headroom.
OUT A
OUT D
OUT A
1
2
3
4
5
6
7
OUT D
–IN D
+IN D
V–
14
13
12
11
10
9
–IN A
+IN A
V+
–IN D
+IN D
V–
–IN A
+IN A
V+
T he OP193 family is specified for single +2 volt through dual
±15 volt operation over the HOT (–40°C to +125°C) tempera-
ture range. T hey are available in plastic DIPs, plus SOIC sur-
face mount packages.
OP493
+IN B
–IN B
OUT B
NC
+IN C
–IN C
OUT C
NC
OP493
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
8
NC = NO CONNECT
*P atent pending.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood. MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
OP193/OP293/OP493–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS(@ V = ؎15.0 V, T = +25؇C unless otherwise noted)
S
A
“ E” Grade
“ F” Grade
Min Typ Max
P aram eter
Sym bol
Conditions
Min
Typ Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
OP193
75
150
250
250
350
275
375
µV
µV
µV
µV
µV
µV
OP193, –40°C ≤ T A ≤ +125°C
OP293
OP293, –40°C ≤ T A ≤ +125°C
OP493
OP493, –40°C ≤ T A ≤ +125°C
VCM = 0 V,
–40°C ≤ T A ≤ +125°C
VCM = 0 V,
175
100
200
125
225
Input Bias Current
Input Offset Current
IB
15
20
nA
IOS
–40°C ≤ T A ≤ +125°C
2
4
nA
V
dB
Input Voltage Range
VCM
–14.9
100
+13.5 –14.9
97
+13.5
Common-Mode Rejection
CMRR
–14.9 ≤ VCM ≤ +14 V
–14.9 ≤ VCM ≤ +14 V,
–40°C ≤ T A ≤ +125°C
RL = 100 kΩ,
116
116
97
94
dB
Large Signal Voltage Gain
Large Signal Voltage Gain
Large Signal Voltage Gain
AVO
AVO
AVO
–10 V ≤ VOUT ≤ +10 V
–40°C ≤ TA ≤ +85°C
–40°C ≤ T A ≤ +125°C
RL = 10 kΩ,
–10 V ≤ VOUT ≤ +10 V
–40°C ≤ TA ≤ +85°C
–40°C ≤ T A ≤ +125°C
RL = 2 kΩ,
–10 V ≤ VOUT ≤ +10 V
–40°C ≤ TA ≤ +85°C
–40°C ≤ T A ≤ +125°C
Note 1
500
300
500
300
V/mV
V/mV
V/mV
300
150
300
150
100
350
200
350
200
V/mV
V/mV
V/mV
200
125
200
125
V/mV
V/mV
V/mV
µV
100
0.2
Long T erm Offset Voltage
Offset Voltage Drift
VOS
∆VOS/∆T
150
1.75
300
Note 2
µV/°C
OUT PUT CHARACT ERIST ICS
Output Voltage Swing High
VOH
IL = 1 mA
+14.1 14.2
+14.1 14.2
V
IL = 1 mA,
–40°C ≤ T A ≤ +125°C
IL = 5 mA
IL = –1 mA
+14.0
+13.9 14.1
+14.0
+13.9 14.1
V
V
V
Output Voltage Swing Low
VOL
–14.7 –14.6
-14.7 –14.6
IL = –1 mA,
–40°C ≤ T A ≤ +125°C
IL = –5 mA
–14.4
14.2 –14.1
±25
–14.4
14.2 –14.1
±25
V
V
mA
Short Circuit Current
ISC
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
VS = ±1.5 V to ±18 V
VS = ±1.5 V to ±18 V,
–40°C ≤ T A ≤ +125°C
–40°C ≤ TA ≤ +125°C, RL = ∞
VOUT = 0 V, VS = ±18 V
100
97
120
97
94
120
dB
dB
µA
Supply Current/Amplifier
ISY
30
30
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
µV p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Channel Separation
SR
GBP
RL = 2 kΩ
15
35
15
35
V/ms
kHz
VOUT = 10 V p-p,
RL = 2 kΩ, f = 1 kHz
120
120
dB
NOT ES
1Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 °C, with an LT PD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
–2–
REV. A
OP193/OP293/OP493
(@ V = +5.0 V, V = 0.1 V, T = +25؇C unless otherwise noted)
ELECTRICAL SPECIFICATIONS
S
CM
A
“ E” Grade
“ F” Grade
P aram eter
Sym bol Conditions
Min Typ Max
Min Typ Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
OP193
75
150
250
250
350
275
375
20
µV
µV
µV
µV
µV
µV
nA
nA
V
OP193, –40°C ≤ T A ≤ +125°C
OP293
OP293, –40°C ≤ T A ≤ +125°C
OP493
OP493, –40°C ≤ T A ≤ +125°C
–40°C ≤ T A ≤ +125°C
–40°C ≤ T A ≤ +125°C
175
100
200
125
225
15
Input Bias Current
IB
IOS
VCM
CMRR
Input Offset Current
Input Voltage Range
Common-Mode Rejection
2
4
4
4
0
0
96
0.1 ≤ VCM ≤ +4 V
0.1 ≤ VCM ≤ +4 V,
–40°C ≤ T A ≤ +125°C
RL = 100 kΩ,
0.03 ≤ VOUT ≤ +4.0 V
–40°C ≤ T A ≤ +85°C
–40°C ≤ T A ≤ +125°C
RL = 10 kΩ,
0.03 ≤ VOUT ≤ +4.0 V
–40°C ≤ T A ≤ +85°C
–40°C ≤ T A ≤ +125°C
Note 1
100 116
116
dB
92
92
dB
Large Signal Voltage Gain
Large Signal Voltage Gain
AVO
200
125
130
200
125
V/mV
V/mV
V/mV
130
70
AVO
75
50
70
75
50
V/mV
V/mV
V/mV
µV
Long T erm Offset Voltage
Offset Voltage Drift
VOS
∆VOS/∆T
150
1.25
300
Note 2
0.2
µV/°C
OUT PUT CHARACT ERIST ICS
Output Voltage Swing High
VOH
IL = 100 µA
IL = 1 mA
4.4
+4.1 4.4
4.4
+4.1 4.4
V
V
IL = 1 mA,
–40°C ≤ T A ≤ +125°C
IL = 5 mA
+4.0
+4.0 4.4
+4.0
+4.0 4.4
V
V
Output Voltage Swing Low
VOL
IL = –100 µA
IL = –100 µA,
–40°C ≤ T A ≤ +125°C
No Load
140 160
140 160
mV
220
5
280 400
220
5
280 400
mV
mV
mV
IL = –1 mA
IL = –1 mA,
–40°C ≤ T A ≤ +125°C
IL = –5 mA
500
700 900
±8
500
700 900
±8
mV
mV
mA
Short Circuit Current
ISC
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
VS = ±1.7 V to ±6.0 V
VS = ±1.5 V to ±18 V,
–40°C ≤ T A ≤ +125°C
VCM = 2.5 V, RL = ∞
100 120
94
97
90
120
dB
dB
µA
Supply Current/Amplifier
ISY
14.5
14.5
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
µV p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
SR
GBP
RL = 2 kΩ
12
35
12
35
V/ms
kHz
NOT ES
1Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 °C, with an LT PD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
REV. A
–3–
OP193/OP293/OP493
ELECTRICAL SPECIFICATIONS (@ V = +3.0 V, V = 0.1 V, T = +25؇C unless otherwise noted)
S
CM
A
“ E” Grade
“ F” Grade
P aram eter
Sym bol Conditions
Min Typ Max
Min Typ Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
OP193
75
150
250
250
350
275
375
20
µV
µV
µV
µV
µV
µV
nA
nA
V
OP193, –40°C ≤ T A ≤ +125°C
OP293
OP293, –40°C ≤ T A ≤ +125°C
OP493
OP493, –40°C ≤ T A ≤ +125°C
–40°C ≤ T A ≤ +125°C
–40°C ≤ T A ≤ +125°C
175
100
200
125
225
15
Input Bias Current
IB
IOS
VCM
CMRR
Input Offset Current
Input Voltage Range
Common-Mode Rejection
2
2
4
2
0
97
0
94
0.1 ≤ VCM ≤ +2 V
116
116
100
dB
0.1 ≤ VCM ≤ +2 V,
–40°C ≤ T A ≤ +125°C
RL = 100 kΩ, 0.03 ≤ VOUT ≤ 2 V
–40°C ≤ T A ≤ +85°C
–40°C ≤ T A ≤ +125°C
Note 1
90
100
75
87
100
75
dB
Large Signal Voltage Gain
AVO
V/mV
V/mV
V/mV
µV
100
0.2
Long T erm Offset Voltage
Offset Voltage Drift
VOS
150
1.25
300
∆VOS/∆T Note 2
µV/°C
OUT PUT CHARACT ERIST ICS
Output Voltage Swing High
VOH
VOL
ISC
IL = 1 mA
IL = 1 mA,
–40°C ≤ T A ≤ +125°C
IL = 5 mA
IL = –1 mA
IL = –1 mA
–40°C ≤ T A ≤ +125°C
IL = –5 mA
+2.1 2.14
+2.1 2.14
V
1.9
+1.9 2.1
1.9
+1.9 2.1
V
V
mV
Output Voltage Swing Low
280 400
280 400
500
700 900
±8
500
700 900
±8
mV
mV
mA
Short Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = +1.7 V to +6 V,
–40°C ≤ T A ≤ +125°C
VCM = 1.5 V, RL = ∞
–40°C ≤ T A ≤ +125°C
100
94
97
90
dB
µA
µA
V
Supply Current/Amplifier
Supply Voltage Range
14.5 22
22
14.5 22
22
VS
+2
±18
+2
±18
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
µV p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Channel Separation
SR
GBP
RL = 2 kΩ
10
25
10
25
V/ms
kHz
VOUT = 10 V p-p,
RL = 2 kΩ, f = 1 kHz
120
120
dB
NOT ES
1Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 °C, with an LT PD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
–4–
REV. A
OP193/OP293/OP493
ELECTRICAL SPECIFICATIONS (@ V = +2.0 V, V = 0.1 V, T = +25؇C unless otherwise noted)
S
CM
A
“ E” Grade
“ F” Grade
P aram eter
Sym bol
Conditions
Min Typ Max
Min Typ Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
OP193
75
150
250
250
350
275
375
20
µV
µV
µV
µV
µV
µV
nA
nA
V
V/mV
V/mV
µV
OP193, –40°C ≤ T A ≤ +125°C
OP293
OP293, –40°C ≤ T A ≤ +125°C
OP493
OP493, –40°C ≤ T A ≤ +125°C
–40°C ≤ T A ≤ +125°C
–40°C ≤ T A ≤ +125°C
175
100
175
125
225
15
Input Bias Current
IB
Input Offset Current
Input Voltage Range
Large Signal Voltage Gain
IOS
VCM
AVO
2
1
4
1
0
60
0
60
RL = 100 kΩ, 0.03 ≤ VOUT ≤ 1 V
–40°C ≤ T A ≤ +125°C
Note 1
70
70
Long T erm Offset Voltage
POWER SUPPLY
VOS
150
300
Power Supply Rejection Ratio PSRR
VS = +1.7 V to +6 V,
–40°C ≤ T A ≤ +125°C
VCM = 1.0 V, RL = ∞
–40°C ≤ T A ≤ +125°C
100
94
97
90
dB
µA
µA
V
Supply Current/Amplifier
Supply Voltage Range
ISY
VS
13.2 20
25
13.2 20
25
+2
±18
+2
±18
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
µV p-p
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
SR
GBP
RL = 2 kΩ
10
25
10
25
V/ms
kHz
(@ V = +5.0 V, V = 0.1 V, V = 2 V, T = +25؇C unless otherwise noted)
WAFER TEST LIMITS
P aram eter
S
CM
Sym bol
VOS
OUT
A
Conditions
Lim it
Units
Offset Voltage
VS = ±15 V, VOUT = 0 V
VS = +2 V, VOUT = 1.0 V
VCM = 1.0 V
±75
±75
20
µV max
µV max
nA max
nA max
V min
dB min
dB min
V/mV min
V min
Input Bias Current
IB
Input Offset Current
IOS
VCM = 1.0 V
4
Input Voltage Range1
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
0 to 4
96
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing High
Output Voltage Swing Low
Supply Current/Amplifier
0 ≤ VCM ≤ 4 V
VS = ±1.5 V to ±18 V
RL = 100 kΩ
IL = 1 mA
IL = –1 mA
100
100
4.1
400
25
mV max
µA max
VO = 0 V, RL = ∞, VS = ±18 V
NOT ES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1Guaranteed by CMRR test.
Specifications subject to change without notice.
REV. A
–5–
OP193/OP293/OP493
ABSO LUTE MAXIMUM RATINGS1
O RD ERING GUID E
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Output Short-Circuit Duration to Gnd . . . . . . . . . . Indefinite
Storage T emperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range
OP193/OP293/OP493E, F . . . . . . . . . . . . –40°C to +125°C
Junction T emperature Range
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
OP193EP
OP193ES
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
+25°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
+25°C
8-Pin Plastic DIP
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
DICE
8-Pin Plastic DIP
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
8-Pin SOIC
8-Pin SOIC
DICE
N-8
SO-8
SO-8
SO-8
N-8
SO-8
SO-8
SO-8
OP193ES-REEL
OP193ES-REEL7
OP193FP
OP193FS
OP193FS-REEL
OP193FS-REEL7
OP193GBC
OP293EP
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering, 60 sec) . . . . . . . +300°C
N-8
OP293ES
SO-8
SO-8
SO-8
N-8
SO-8
SO-8
SO-8
OP293ES-REEL
OP293ES-REEL7
OP293FP
3
P ackage Type
θJA
θJC
Units
OP293FS
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
14-Pin Plastic DIP (P)
16-Pin SOL (S)
103
158
83
43
43
39
27
°C/W
°C/W
°C/W
°C/W
OP293FS-REEL
OP293FS-REEL7
OP293GBC
OP493EP
OP493ES
OP493ES-REEL
OP493FP
OP493FS
OP493FS-REEL
OP493GBC
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
+25°C
14-Pin Plastic DIP N-14
16-Pin SOL
16-Pin SOL
92
SOL-16
SOL-16
NOT ES
14-Pin Plastic DIP N-14
1Absolute maximum ratings apply to both DICE and packaged parts, unless
16-Pin SOL
16-Pin SOL
DICE
SOL-16
SOL-16
otherwise noted.
2For supply voltages less than ±18 V, the input voltage is limited to the supply
voltage.
3θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for P-DIP, and θJA is specified for device soldered in circuit board for SOIC
package.
1
2
7
D ICE CH ARACTERISTICS
6
1
8
3
7
4
5
OP193 Die Size 0.070 × 0.055 Inch, 3,850 Sq. Mils Substrate
(Die Backside) Is Connected to V– Transistor Count, 55
1
8
7
6
2
6
2
5
3
4
5
OP493 Die Size 0.106 × 0.143 Inch, 15,158 Sq. Mils Substrate
3
4
(Die Backside) Is Connected to V– Transistor Count, 215
OP293 Die Size 0.072 × 0.110 Inch, 7,920 Sq. Mils Substrate
(Die Backside) Is Connected to V– Transistor Count, 105
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP193/OP293/OP493 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. A
Typical Performance Characteristics–OP193/OP293/OP493
150
200
200
160
120
80
V
V
T
= +3V
V
V
= +3V
S
S
= 0.1V
= 0.1V
V
T
= ±15V
= +25°C
CM
CM
S
= +25°C
120
–40°C ≤ T ≤ +125°C
A
A
160
120
80
A
450 x PDIPS
450 x PDIPS
450 x PDIPS
90
60
30
0
40
40
0
0
0
0.2
0.4
TCV
0.6
0.8
1.0
–75 –60–45 –30 –15
0
15 30
60 75
45
–75–60 –45 –30 –15
0
15 30 45 60
75
– µV/° C
OFFSET – µV
OFFSET – µV
OS
Figure 3. OP193 TCVOS Distribution,
VS = +3 V
Figure 1. OP193 Offset Distribution,
VS = ±15 V
Figure 2. OP193 Offset Distribution,
VS = +3 V
150
120
1
5V ≤ V ≤ 30V
S
V
= ±15V
S
V = +5V
S
T
= +25°C
–PSRR
A
–40°C ≤ T ≤ +125°C
100
A
120
90
0
–1
–2
–3
–4
–40°C
450 x PDIPS
80
60
40
20
0
+PSRR
+125°C
60
+25°C
30
0
0
0.2
0.4
TCV
0.6
0.8
1.0
0
1
2
3
4
5
10
100
1k
10k
– µV/° C
COMMON MODE VOLTAGE – Volts
OS
FREQUENCY – Hz
Figure 5. Input Bias Current vs.
Com m on-Mode Voltage
Figure 4. OP193 TCVOS Distribution,
VS = ±15 V
Figure 6. PSRR vs. Frequency
25
120
40
T
= +25°C
A
100
80
60
40
20
0
+ISC
20
+SR = –SR
V
= ±15V
S
30
20
10
0
V
= ±15V
S
V = ±15V
S
|
V
–ISC |
15
10
= ±15V
S
+SR = –SR
V
= +5V
S
V
= +5V
S
5
0
+ISC
|
V
–ISC
|
V
= +5V
S
= +5V
S
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
10
100
1k
10k
TEMPERATURE – °C
TEMPERATURE – °C
FREQUENCY – Hz
Figure 8. Slew Rate vs. Tem perature
Figure 9. Short Circuit Current vs.
Tem perature
Figure 7. CMRR vs. Frequency
REV. A
–7–
OP193/OP293/OP493–Typical Performance Characteristics
25
20
15
10
5
0
0
–1
–2
–3
–4
–5
V
= ±18V
S
–0.5
V
= ±15V
S
–0.10
–0.15
–0.20
–0.25
V
V
= +2V
S
V
V
= +2V
S
= 0.1V
CM
= +1V
CM
V
V
= +2V
S
= 0.1V
CM
V
= ±15V
S
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE – °C
TEMPERATURE – °C
TEMPERATURE – °C
Figure 10. Input Offset Current vs.
Tem perature
Figure 12. Supply Current vs.
Tem perature
Figure 11. Input Bias Current vs.
Tem perature
1000
10000
1000
5V ≤ V ≤ 30V
S
5V ≤ V ≤ 30V
S
T
= +25°C
5V ≤ V ≤ 30V
A
S
T
= +25°C
A
T
= +25°C
A
1000
100
10
100
10
1
100
10
DELTA
FROM V
CC
DELTA
FROM V
EE
1
1
0.1
0.1
1
10
100
1k
1
10
100
1k
0.1
1
10
100
1000 10000
FREQUENCY – Hz
FREQUENCY – Hz
LOAD CURRENT – µA
Figure 13. Voltage Noise Density vs.
Frequency
Figure 14. Current Noise Density vs.
Frequency
Figure 15. Delta Output Swing from
Either Rail vs. Current Load
2500
2000
60
1000
800
T
= +25°C
A
V
= +5V
S
V
= ±15V
40
20
V
= ±15V
S
S
–10V ≤ V
≤ +10V
–10V ≤ V
≤ +10V
OUT
OUT
1500
1000
500
0
600
400
200
0
V
= +5V
0.03V ≤ V
V
= +5V
S
S
≤ 4V
0.03V ≤ V
≤ 4V
OUT
OUT
0
–20
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
10
100
1k
10k
100k
TEMPERATURE – °C
TEMPERATURE – °C
FREQUENCY – Hz
Figure 16. Voltage Gain (RL = 100 kΩ)
vs. Tem perature
Figure 17. Voltage Gain (RL = 10 kΩ)
vs. Tem perature
Figure 18. Closed-Loop Gain vs.
Frequency, VS = 5 V
–8–
REV. A
OP193/OP293/OP493
60
50
40
30
20
10
0
60
40
20
0
60
V
= +5V
V
A
= +5V T = +25°C
= 1
S
S
A
T
V
= +25°C
= ±15V
A
+OS = | –OS
= 50kΩ
|
V
PHASE
S
R
50mV ≤ V ≤ 150mV
LOADS TO GND
L
90
45
IN
40
20
+OS
GAIN
R
= ∞
L
0
0
–45
–20
–40
+OS =
| –OS |
R
= 10kΩ
L
–OS
R
= ∞
L
–90
–20
100
1k
10k
100k
1M
10
100
1k
10k
100k
10
100
1000
10000
CAPACITIVE LOAD – pF
FREQUENCY – Hz
FREQUENCY – Hz
Figure 21. Open Loop, Gain and
Phase vs. Frequency
Figure 20. Sm all Signal Overshoot
vs. Capacitive Load
Figure 19. Closed-Loop Gain vs.
Frequency, VS = ±15 V
60
V
= ±15V
S
90
45
40
20
PHASE
V+
I
1
I
2
I
3
I4
+INPUT
–INPUT
2k
2k
GAIN
0
0
Q5
Q1
Q2
Q6
–45
–90
–20
–40
OP293,
OP493
ONLY
Q4
Q3
100
1k
10k
100k
1M
TO
Q7
Q8
OUTPUT
STAGE
FREQUENCY – Hz
D1
Figure 22. Open Loop, Gain and
Phase vs. Frequency
R1
R2
A
A
I
5
I6
R1
R2
B
B
FUNCTIO NAL D ESCRIP TIO N
V–
T he OP193 family of operational amplifiers are single-supply,
micropower, precision amplifiers whose input and output ranges
both include ground. Input offset voltage (VOS) is only 75 µV
maximum, while the output will deliver ±5 mA to a load. Sup-
ply current is only 17 µA.
NULLING
TERMINALS
(OP193 ONLY)
Figure 23. OP193/OP293/OP493 Equivalent Input Circuit
A simplified schematic of the input stage is shown in Figure 23.
Input transistors Q1 and Q2 are PNP devices, which permit the
inputs to operate down to ground potential. T he input transis-
tors have resistors in series with the base terminals to protect the
junctions from over voltage conditions. T he second stage is an
NPN cascode which is buffered by an emitter follower before
driving the final PNP gain stage.
V+
Q4
FROM
INPUT
STAGE
Q1
Q5
T he OP193 includes connections to taps on the input load resis-
OUTPUT
tors, which can be used to null the input offset voltage, VOS
.
Q3
T he OP293 and OP493 have two additional transistors, Q7 and
Q8. T he behavior of these transistors is discussed in the Output
Phase Reversal section of this data sheet.
Q2
I
2
I
3
I1
V–
T he output stage, shown in Figure 24, is a noninverting NPN
“totem-pole” configuration. Current is sourced to the load by
emitter follower Q1, while Q2 provides current sink capability.
When Q2 saturates, the output is pulled to within 5 mV of
ground without an external pull-down resistor. T he totem-pole
output stage will supply a minimum of 5 mA to an external
load, even when operating from a single 3.0 V power supply.
Figure 24. OP193/OP293/OP493 Equivalent Output Circuit
Q5 tracks the collector current of Q1. When Q1 is on, Q5 keeps
Q4 off, and current source I1 keeps Q2 turned off. When Q1 is
driven to cutoff (i.e., the output must move toward V–), Q5
allows Q4 to turn on. Q4’s collector current then provides the
base drive for Q3 and Q2, and the output low voltage swing is
set by Q2’s VCE,SAT which is about 5 mV.
By operating as an emitter follower, Q1 offers a high impedance
load to the final PNP collector of the input stage. Base drive to
Q2 is derived by monitoring Q1’s collector current. T ransistor
REV. A
–9–
OP193/OP293/OP493
D r iving Capacitive Loads
High performance portable equipment and instruments fre-
quently use lithium cells because of their long shelf life, light
weight, and high energy density relative to older primary cells.
Most lithium cells have a nominal output voltage of 3 V and are
noted for a flat discharge characteristic. T he low supply voltage
requirement of the OP193, combined with the flat discharge
characteristic of the lithium cell, indicates that the OP193 can
be operated over the entire useful life of the cell. Figure 25
shows the typical discharge characteristic of a 1 AH lithium cell
powering the OP193, OP293, and OP493, with each amplifier,
in turn, driving 2.1 Volts into a 100 kΩ load.
OP193 family amplifiers are unconditionally stable with capaci-
tive loads less than 200 pF. However, the small signal, unity-
gain overshoot will improve if a resistive load is added. For
example, transient overshoot is 20% when driving a 1000 pF/
10 kΩ load. When driving large capacitive loads in unity-gain
configurations, an in-the-loop compensation technique is rec-
ommended as illustrated in Figure 28.
Input O ver voltage P r otection
As previously mentioned, the OP193 family of op amps use a
PNP input stage with protection resistors in series with the
inverting and noninverting inputs. T he high breakdown of the
PNP transistors, coupled with the protection resistors, provides
a large amount of input protection from over voltage conditions.
T he inputs can therefore be taken 20 V beyond either supply
without damaging the amplifier.
4
3
2
O utput P hase Rever sal—O P 193
The OP193’s input PNP collector-base junction can be forward-
biased if the inputs are brought more than one diode drop
(0.7 V) below ground. When this happens to the noninverting
input, Q4 of the cascode stage turns on and the output goes
high. If the positive input signal can go below ground, phase
reversal can be prevented by clamping the input to the negative
supply (i.e., GND) with a diode. T he reverse leakage of the
diode will, of course, add to the input bias current of the ampli-
fier. If input bias current is not critical, a 1N914 will add less
than 10 nA of leakage. However, its leakage current will double
for every 10°C increase in ambient temperature. For critical
applications, the collector-base junction of a 2N3906 transistor
will only add about 10 pA of additional bias current. T o limit
the current through the diode under fault conditions, a 1 kΩ
resistor is recommended in series with the input. (T he OP193’s
internal current limiting resistors will not protect the external
diode).
OP193
OP493
OP293
1
0
0
1000
2000
3000
4000
5000
6000
7000
HOURS
Figure 25. Lithium Sulfur Dioxide Cell Discharge Charac-
teristic with OP193 Fam ily and 100 kΩ Loads
Input O ffset Voltage Nulling
T he OP193 provides two offset nulling terminals that can be
used to adjust the OP193’s internal VOS. In general, operational
amplifier terminals should never be used to adjust system offset
voltages. T he offset null circuit of Figure 26 provides about
±7 mV of offset adjustment range. A 100 kΩ resistor placed in
series with the wiper arm of the offset null potentiometer, as
shown in Figure 27, reduces the offset adjustment range to
400 µV and is recommended for applications requiring high null
resolution. Offset nulling does not adversely affect T CVOS per-
formance, providing that the trimming potentiometer tempera-
ture coefficient does not exceed ±100 ppm/°C.
O utput P hase Rever sal—O P 293 and O P 493
T he OP293 and OP493 include lateral PNP transistors Q7 and
Q8 to protect against phase reversal. If an input is brought more
than one diode drop (≈0.7 V) below ground, Q7 and Q8 com-
bine to level shift the entire cascode stage, including the bias to
Q3 and Q4, simultaneously. In this case Q4 will not saturate
and the output remains low.
T he OP293 and OP493 do not exhibit output phase reversal for
inputs up to –5 V below V– at +25°C. T he phase reversal limit
at +125°C is about –3 V. If the inputs can be driven below these
levels, an external clamp diode, as discussed in the previous sec-
tion, should be added.
V+
7
2
6
OP193
Batter y P ower ed Applications
4
OP193 series op amps can be operated on a minimum supply
voltage of +1.7 V, and draw only 13 µA of supply current per
amplifier from a 2.0 V supply. In many battery-powered cir-
cuits, OP193 devices can be continuously operated for thou-
sands of hours before requiring battery replacement, thus
reducing equipment downtime and operating cost.
3
5
1
100kΩ
V–
Figure 26. Offset Nulling Circuit
–10–
REV. A
OP193/OP293/OP493
V+
V+
R1
240kΩ
R2
1.5MΩ
(+2.5V TO +36V)
7
2
3
7
C1
1000pF
2
3
6
OP193
6
OP193
4
V
OUT
5
5
(1.23V @ 25°C)
1
4
100kΩ
100kΩ
MAT-01AH
Q1
6
1
3
7
5
V–
2
Q2
Figure 27. High Resolution Offset Nulling Circuit
V
V
BE2
BE1
A Micr opower False-Gr ound Gener ator
V1
R3 68kΩ
∆V
Some single supply circuits work best when inputs are biased
above ground, typically at 1/2 of the supply voltage. In these
cases a false ground can be created by using a voltage divider
buffered by an amplifier. One such circuit is shown in Figure 28.
BE
R4
130kΩ
R5 20kΩ
OUTPUT
ADJUST
T his circuit will generate a false-ground reference at 1/2 of the
supply voltage, while drawing only about 27 µA from a 5 V sup-
ply. T he circuit includes compensation to allow for a 1 µF by-
pass capacitor at the false-ground output. T he benefit of a large
capacitor is that not only does the false ground present a very
low dc resistance to the load, but its ac impedance is low as well.
T he OP193 can both sink and source more than 5 mA, which
improves recovery time from transients in the load current.
Figure 29. A Battery Powered Voltage Reference
A Single-Supply Cur r ent Monitor
Current monitoring essentially consists of amplifying the voltage
drop across a resistor placed in series with the current to be
measured. T he difficulty is that only small voltage drops can be
tolerated, and with low precision op amps this greatly limits the
overall resolution. T he single-supply current monitor of Figure
30 has a resolution of 10 µA and is capable of monitoring 30
mA of current. T his range can be adjusted by changing the cur-
rent sense resistor R1. When measuring total system current, it
may be necessary to include the supply current of the current
monitor, which bypasses the current sense resistor, in the final
result. T his current can be measured and calibrated (together
with the residual offset) by adjustment of the offset trim potenti-
ometer, R2. T his produces a deliberate temperature dependent
offset. However, the supply current of the OP193 is also propor-
tional to temperature, and the two effects tend to track. Current
in R4 and R5, which also bypasses R1, can be adjusted via a
gain trim.
+5V OR +12V
10kΩ
0.022µF
240kΩ
7
2
100Ω
+2.5V OR +6V
6
OP193
3
4
1µF
1µF
240kΩ
Figure 28. A Micropower False-Ground Generator
A Batter y P ower ed Voltage Refer ence
V+
T he circuit of Figure 29 is a battery-powered voltage reference
that draws only 17 µA of supply current. At this level, two AA
alkaline cells can power this reference for more than 18 months.
At an output voltage of 1.23 V @ 25°C, drift of the reference is
only 5.5 µV/°C over the industrial temperature range. Load
regulation is 85 µV/mA with line regulation at 120 µV/V.
TO CIRCUIT
UNDER TEST
7
3
6
OP193
I
TEST
V
OUT =
4
2
Design of the reference is based on the Brokaw bandgap core
technique. Scaling of resistors R1 and R2 produces unequal cur-
rents in Q1 and Q2. T he resulting ∆VBE across R3 creates a tem-
perature-proportional voltage (PT AT ) which, in turn, produces
a larger temperature-proportional voltage across R4 and R5, V1.
T he temperature coefficient of V1 cancels (first order) the
complementary to absolute temperature (CT AT ) coefficient of
100mV/mA(I
)
5
TEST
1
R2
9.9kΩ
R2
100kΩ
R1
1Ω
R5
100Ω
R3
100kΩ
VBE1. When adjusted to 1.23 V @ +25°C, output voltage
tempco is at a minimum. Bandgap references can have start-up
problems. With no current in R1 and R2, the OP193 is beyond
its positive input range limit and has an undefined output state.
Shorting Pin 5 (an offset adjust pin) to ground forces the output
high under these circumstances and insures reliable startup
without significantly degrading the OP193’s offset drift.
Figure 30. Single-Supply Current Monitor
REV. A
–11–
OP193/OP293/OP493
A Single-Supply Instr um entation Am plifier
R1
20k
R2
1.98M
Designing a true single-supply instrumentation amplifier with
zero-input and zero-output operation requires special care. T he
traditional configuration, shown in Figure 31, depends upon
amplifier A1’s output being at 0 V when the applied common-
mode input voltage is at 0 V. Any error at the output is multi-
plied by the gain of A2. In addition, current flows through
resistor R3 as A2’s output voltage increases. A1’s output must
remain at 0 V while sinking the current through R3, or a gain
error will result. With a maximum output voltage of 4 V, the
current through R3 is only 2 µA, but this will still produce an
appreciable error.
+5V
R3
20k
R4
1.98M
V+
A1
1/2 OP293
–IN
V–
+5V
10k
+5V
V+
Q2
Q1
VN2222
V
OUT
A2
1/2 OP293
+IN
V–
R1
20k
R2
1.98M
+5V
Figure 32. An Im proved Single-Supply, 0 VIN, 0 VOUT
Instrum entation Am plifier
R3
20k
R4
1.98M
V+
A1
1/2 OP293
A Low-P ower , Tem per atur e to 4–20 m A Tr ansm itter
A simple temperature to 4–20 mA transmitter is shown in Fig-
ure 33. After calibration, this transmitter is accurate to ±0.5°C
over the –50°C to +150°C temperature range. T he transmitter
operates from +8 V to +40 V with supply rejection better than
3 ppm/V. One half of the OP293 is used to buffer the VT EMP
pin, while the other half regulates the output current to satisfy
the current summation at its noninverting input:
+5V
V+
–IN
V–
I
SINK
V
OUT
A2
1/2 OP293
+IN
V–
Figure 31. A Conventional Instrum entation Am plifier
One solution to this problem is to use a pull-down resistor. For
example, if R3 = 20 kΩ, then the pull-down resistor must be
less than 400 Ω. However, the pull-down resistor appears as a
fixed load when a common-mode voltage is applied. With a 4 V
common-mode voltage, the additional load current will be 10 mA,
which is unacceptable in a low power application.
VTEMP × R6 + R7
R2 + R6 + R7
R2 × R10
(
)
– VSET
IOUT
+
R2 × R10
T he change in output current with temperature is the derivative
of the transfer function:
Figure 32 shows a better solution. A1’s sink current is provided
by a pair of N-channel FET transistors, configured as a current
mirror. With the values shown, sink current of Q2 is about
340 µA. T hus, with a common-mode voltage of 4 V, the addi-
tional load current is limited to 340 µA versus 10 mA with a
400 Ω resistor.
∆VTEMP
∆IOUT
∆T
(R6 + R7)
=
∆T
R2 × R10
1N4002
V+
+8V TO +40V
SPAN TRIM
R6
3kΩ
R4
REF-43BZ
20kΩ
R7
5kΩ
2
3
R2
1kΩ
V
2
6
3
4
IN
8
1/2 OP293
4
V
1
6
TEMP
R8
V
OUT
1kΩ
7
2N1711
1/2 OP293
V
TEMP
R3
100kΩ
V
R1 10kΩ
R5
5kΩ
SET
5
R9
100kΩ
GND
ZERO
TRIM
R10
100Ω
1%, 1/2 W
ALL RESISTORS 1/4W, 5% UNLESS OTHERWISE NOTED
I
OUT
R
LOAD
Figure 33. Tem perature to 4–20 m A Transm itter
–12–
REV. A
OP193/OP293/OP493
C1
75nF
From the formulas, it can be seen that if the span trim is ad-
justed before the zero trim, the two trims are not interactive,
which greatly simplifies the calibration procedure.
+5V
R5
200kΩ
+5V
8
R1
200kΩ
2
3
Calibration of the transmitter is simple. First, the slope of the
output current versus temperature is calibrated by adjusting the
span trim, R7. A couple of iterations may be required to be sure
the slope is correct.
V
CONTROL
A1
1/2 OP293
1
6
SQUARE
OUT
A2
1/2 OP293
7
4
R2
200kΩ
5
Once the span trim has been completed, the zero trim can be
made. Remember that adjusting the zero trim will not affect the
gain.
R4
200kΩ
R3
100kΩ
TRIANGLE
OUT
R7
200kΩ
R6
200kΩ
R8
200kΩ
T he zero trim can be set at any known temperature by adjusting
R5 until the output current equals:
+5V
∆IFS
IOUT
=
(TAMBIENT − TMIN ) + 4 mA
CD4066
1
2
3
4
5
6
7
IN/OUT
OUT/IN
OUT/IN
IN/OUT
CONT
14
∆TOPERATING
V
+5V
DD
S1
T able I shows the values of R6 required for various temperature
ranges.
CONT 13
CONT 12
IN/OUT 11
OUT/IN 10
S2
Table I. R6 Values vs. Tem perature
Tem p Range
R6
0°C to +70°C
–40°C to +85°C
–55°C to +150°C
10 kΩ
6.2 kΩ
3 kΩ
S3
S4
CONT
OUT/IN
IN/OUT
9
8
+5V
A Micr opower Voltage Contr olled O scillator
V
SS
An OP293 in combination with an inexpensive quad CMOS
analog switch forms the precision VCO of Figure 34. T his cir-
cuit provides triangle and square wave outputs and draws only
50 µA from a single 5 V supply. A1 acts as an integrator; S1
switches the charging current symmetrically to yield positive and
negative ramps. T he integrator is bounded by A2 which acts as
a Schmitt trigger with a precise hysteresis of 1.67 volts, set by
resistors R5, R6, and R7, and associated CMOS switches. T he
resulting output of A1 is a triangle wave with upper and lower
levels of 3.33 and 1.67 volts. T he output of A2 is a square wave
with almost rail-to-rail swing. With the components shown, fre-
quency of operation is given by the equation:
Figure 34. Micropower Voltage Controlled Oscillator
A Micr opower , Single-Supply Q uad Voltage O utput 8-Bit
D AC
T he circuit of Figure 35 uses the DAC8408 CMOS quad 8-bit
DAC and the OP493 to form a single-supply quad voltage out-
put DAC with a supply drain of only 140 µA. T he DAC8408 is
used in the voltage switching mode and each DAC has an out-
put resistance (≈10 kΩ) independent of the digital input code.
T he output amplifiers act as buffers to avoid loading the DACs.
T he 100 kΩ resistors ensure that the OP493 outputs will swing
to within 1/2 LSB of ground, i.e.:
fOUT = VCONTROL (Volts) × 10 Hz/V
but this can easily be changed by varying C1. T he circuit oper-
ates well up to 500 Hz.
1
2
1. 23 V
×
= 3 mV
256
REV. A
–13–
OP193/OP293/OP493
+5V
+5V
4
A Single-Supply Micr opower Q uad P r ogr am m able-Gain
Am plifier
3.6k
T he combination of the quad OP493 and the DAC8408 quad
8-bit CMOS DAC creates a quad programmable gain amplifier
with a quiescent supply drain of only 140 µA (Figure 36). T he
digital code present at the DAC, which is easily set by a micro-
processor, determines the ratio between the fixed DAC feedback
resistor and the resistance that the DAC feedback ladder pre-
sents to the op amp feedback loop. T he gain of each amplifier is:
+5V
AD589
1.23V
1
2
3
V
DD
V
A
OUT
A
1
I
1A
OUT
4
1/4 OP493
DAC A
1/4
DAC8408
V
A
REF
2
11
R1
100kΩ
VOUT
VIN
256
=
n
I
2A/2B
OUT
5
6
where n equals the decimal equivalent of the 8-bit digital code
present at the DAC.
6
5
V
B
OUT
B
7
14
8
1/4 OP493
DAC B
1/4
DAC8408
V
V
V
B
REF
8
R2
100kΩ
If the digital code present at the DAC consists of all zeros, the
feedback loop will be open causing the op amp to saturate. T he
10 MΩ resistors placed in parallel with the DAC feedback loop
eliminates this problem with a very small reduction in gain accu-
racy. T he 2.5 V reference biases the amplifiers to the center of
the linear region providing maximum output swing.
I
1B
OUT
13
12
V
C
OUT
C
I
1C
OUT
25
1/4 OP493
DAC C
1/4
DAC8408
C
27
REF
R3
100kΩ
I
2C/2D
OUT
24
23
9
V
D
OUT
D
1/4 OP493
DAC D
1/4
DAC8408
D
10
21
REF
R4
100kΩ
I
1D
OUT
OP493
DAC DATA BUS
PINS 9(LSB)–16(MSB)
17
18
19
20
A/B
R/W
DS1
DS2
DIGITAL
CONTROL
SIGNALS
DAC8408ET
DGND
28
Figure 35. Micropower Single-Supply Quad Voltage-
Output 8-Bit DAC
–14–
REV. A
OP193/OP293/OP493
1
V
C1
0.1µF
DD
+5V
R
A
3
FB
4
V
A
IN
V
I
A
2
4
REF
R1
10MΩ
1A
OUT
2
3
DAC A
1/4
DAC8408
A
1
V
A
OUT
1/4 OP493
I
2A/2B
OUT
11
5
8
C2
0.1µF
R
FB
B
7
V
IN
B
V
B
REF
R2
10MΩ
DAC B
1/4
DAC8408
I
1B
OUT
6
5
6
B
7
V
B
OUT
1/4 OP493
C3
0.1µF
R
FB
C
26
V
C
IN
V
C
REF
27
25
R3
I
10MΩ
1C
OUT
9
DAC C
1/4
C
8
V
C
OUT
1/4 OP493
DAC8408
10
I
2C/2D
D
OUT
24
21
C4
0.1µF
R
D
22
FB
V
D
V
IN
REF
R4
10MΩ
DAC D
1/4
DAC8408
I
1D
OUT
23
13
12
D
14
V
D
1/4 OP493
OUT
DAC DATA BUS
PINS 9(LSB)–16(MSB)
OP493
17
18
19
20
A/B
R/W
DS1
DS2
DIGITAL
CONTROL
SIGNALS
+2.5V
REFERENCE
VOLTAGE
DAC8408ET
DGND
28
Figure 36. Single-Supply Micropower Quad Program m able-Gain Am plifier
REV. A
–15–
OP193/OP293/OP493
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead Epoxy D IP
(P Suffix)
8-Lead SO
(S Suffix)
8
5
0.280 (7.11)
0.240 (6.10)
8
1
5
PIN 1
0.1574 (4.00)
0.1497 (3.80)
1
4
PIN 1
0.2440 (6.20)
0.2284 (5.80)
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.1968 (5.00)
0.1890 (4.80)
0.0196 (0.50)
0.0099 (0.25)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
x 45°
0.210
(5.33)
MAX
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.130
(3.30)
MIN
0.0040 (0.10)
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
8
0
°
°
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
0.100
(2.54)
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
BSC
16-Lead Wide Body SO L
(S Suffix)
14-Lead Epoxy D IP
(P Suffix)
14
8
0.280 (7.11)
0.240 (6.10)
9
16
PIN 1
0.2992 (7.60)
0.2914 (7.40)
1
7
0.325 (8.25)
0.300 (7.62)
0.795 (20.19)
0.725 (18.42)
0.4193 (10.65)
PIN 1
0.3937 (10.00)
8
1
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
0.1043 (2.65)
0.4133 (10.50)
0.3977 (10.00)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.0500 (1.27)
0.0157 (0.40)
8
0
°
°
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
–16–
REV. A
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