OP296HRUZ-REEL [ADI]
Micropower RRIO Operational Amplifiers; 微功耗RRIO运算放大器
| 型号： | OP296HRUZ-REEL |
| 厂家： | 
ADI |
| 描述： | Micropower RRIO Operational Amplifiers |
| 文件： | 总19页 (文件大小：2373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Micropower RRIO
Operational Amplifiers
a
OP196/OP296/OP496
FEATURES
PIN CONFIGURATIONS
Rail-to-Rail Input and Output Swing
Low Power: 60 A/Amplifier
Gain Bandwidth Product: 450 kHz
Single-Supply Operation: 3 V to 12 V
Low Offset Voltage: 300 V max
High Open-Loop Gain: 500 V/mV
Unity-Gain Stable
8-Lead Narrow-Body SO
8-Lead Narrow-Body SO
1
2
3
4
8
7
6
5
V+
NULL
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
NC
OUT A
–IN A
+IN A
V–
OUT B
–IN B
+IN B
V+
OP296
OP196
OUT A
NULL
NC = NO CONNECT
No Phase Reversal
APPLICATIONS
Battery Monitoring
Sensor Conditioners
Portable Power Supply Control
Portable Instrumentation
8-Lead TSSOP
1
8
V+
OUT A
–IN A
+IN A
V–
OUT B
–IN B
+IN B
OP296
4
5
GENERAL DESCRIPTION
The OP196 family of CBCMOS operational amplifiers features
micropower operation and rail-to-rail input and output ranges.
The extremely low power requirements and guaranteed opera-
tion from 3 V to 12 V make these amplifiers perfectly suited to
monitor battery usage and to control battery charging. Their
dynamic performance, including 26 nV/√Hz voltage noise
density, recommends them for battery-powered audio applica-
tions. Capacitive loads to 200 pF are handled without oscillation.
14-Lead Narrow-Body SO
OUT A
1
2
OUT D
14
13
extended
The OP196/OP296/OP496 are specified over the
industrial (–40°C to +125°C) temperature range. 3 V operation
–IN A
–IN D
+IN D
V–
+IN A
V+
3
4
12
11
is specified over the 0°C to 125°C temperature range.
OP496
+IN B
5
6
+IN C
10
9
The single OP196 and the dual OP296 are available in 8-lead
SOIC and TSSOP packages. The quad OP496 is available in
14-lead SOIC and TSSOP packages.
–IN B
–IN C
OUT B
7
OUT C
8
14-Lead TSSOP
(RU Suffix)
1
14
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP496
7
8
E
REV.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/
www.analog.com
2002-2011 Analog Devices, Inc.
461-3113
©
OP196/OP296/OP496–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ VS = 5.0 V, VCM = 2.5 V, TA = 25؇C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP196G, OP296G, OP496G
–40°C ≤ TA ≤ +125°C
OP296H, OP496H
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
35
300
650
800
1.2
50
8
20
µV
µV
µV
mV
nA
nA
nA
V
Input Bias Current
Input Offset Current
IB
IOS
10
1.5
–40°C ≤ TA ≤ +125°C
Input Voltage Range
VCM
0
5.0
Common-Mode Rejection Ratio
CMRR
0 V ≤ VCM ≤ 5.0 V,
–40°C ≤ TA ≤ +125°C
RL = 100 kΩ,
65
dB
Large Signal Voltage Gain
AVO
0.30 V ≤ VOUT ≤ 4.7 V,
–40°C ≤ TA ≤ +125°C
G Grade, Note 1
H Grade, Note 1
G Grade, Note 2
150
200
V/mV
µV
Long-Term Offset Voltage
Offset Voltage Drift
VOS
550
1
mV
∆VOS/∆T
1.5
2
µV/°C
µV/°C
H Grade, Note 2
OUTPUT CHARACTERISTICS
Output Voltage Swing High
+
VOH
VOL
IOUT
IL = 100 µA
4.85
4.30
4.92
4.56
4.1
36
350
750
4
V
V
V
mV
mV
mV
mA
IL = 1 mA
IL = 2 mA
IL = –
IL = –1 mA
IL = –2 mA
100 μA
Output Voltage Swing Low
70
550
Output Current
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
2.5 V ≤ VS ≤ 6 V,
–40°C ≤ TA ≤ +125°C
85
dB
µA
µA
Supply Current per Amplifier
VOUT = 2.5 V, RL =
–40°C ≤ TA ≤ +125°C
∞
60
80
45
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
øm
RL = 100 kΩ
0.3
350
47
V/µs
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.8
26
0.19
µV p-p
nV/√Hz
pA/√Hz
Current Noise Density
NOTES
1Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 12 5°C, with an LTPD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
REV.E
–2–
OP196/OP296/OP496
(@ VS = 3.0 V, VCM = 1.5 V, TA = 25؇C, unless otherwise noted.)
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP196G, OP296G, OP496G
0°C ≤ TA ≤ 125°C
OP296H, OP496H
0°C ≤ TA ≤ 125°C
35
300
650
800
1.2
50
µV
µV
µV
mV
nA
nA
V
Input Bias Current
Input Offset Current
Input Voltage Range
IB
IOS
VCM
10
1
8
3.0
0
Common-Mode Rejection Ratio
CMRR
0 V ≤ VCM ≤ 3.0 V,
0°C ≤ TA ≤ 125°C
RL = 100 kΩ
G Grade, Note 1
H Grade, Note 1
G Grade, Note 2
H Grade, Note 2
60
80
dB
Large Signal Voltage Gain
Long-Term Offset Voltage
AVO
VOS
200
V/mV
µV
mV
µV/°C
µV/°C
550
1
Offset Voltage Drift
∆VOS/∆T
1.5
2
OUTPUT CHARACTERISTICS
Output Voltage Swing High
Output Voltage Swing Low
VOH
VOL
IL = 100 µA
IL = –100 µA
2.85
V
mV
70
POWER SUPPLY
Supply Current per Amplifier
ISY
VOUT = 1.5 V, RL =
0°C ≤ TA ≤ 125°C
∞
40
60
80
µA
µA
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
øm
RL = 100 kΩ
0.25
350
45
V/µs
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.8
26
0.19
µV p-p
nV/√Hz
pA/√Hz
Current Noise Density
NOTES
1Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 12 5°C, with an LTPD of 1.3.
2Offset voltage drift is the average of the 0°C to 25°C delta and the 25°C to 125°C delta.
Specifications subject to change without notice.
REV.
E
–3–
OP196/OP296/OP496
(@ V = 12.0 V, VCM = 6 V, TA = 25؇C, unless otherwise noted.)
ELECTRICAL SPECIFICATIONS
S
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP196G, OP296G, OP496G
0°C ≤ TA ≤ 125°C
35
300
650
800
1.2
50
8
15
µV
µV
µV
mV
nA
nA
nA
V
OP296H, OP496H
0°C ≤ TA ≤ 125°C
–40°C ≤ TA ≤ +125°C
Input Bias Current
Input Offset Current
IB
IOS
10
1
–40°C ≤ TA ≤ +125°C
Input Voltage Range
VCM
0
12
Common-Mode Rejection Ratio
CMRR
0 V ≤ VCM ≤ 12 V,
–40°C ≤ TA ≤ +125°C
RL = 100 kΩ
G Grade, Note 1
H Grade, Note 1
G Grade, Note 2
H Grade, Note 2
65
300
dB
Large Signal Voltage Gain
Long-Term Offset Voltage
AVO
VOS
1000
V/mV
µV
mV
µV/°C
µV/°C
550
1
Offset Voltage Drift
∆VOS/∆T
1.5
2
OUTPUT CHARACTERISTICS
Output Voltage Swing High
VOH
VOL
IOUT
IL = 100 µA
11.85
11.30
V
V
mV
mV
mA
IL = 1 mA
100 μA
Output Voltage Swing Low
IL = –
70
550
IL = –1 mA
Output Current
4
POWER SUPPLY
Supply Current per Amplifier
ISY
VS
VOUT = 6 V, RL =
–40°C ≤ TA ≤ +125°C
∞
60
80
12
µA
µA
V
Supply Voltage Range
3
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
øm
RL = 100 kΩ
0.3
450
50
V/µs
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.8
26
0.19
µV p-p
nV/√Hz
pA/√Hz
NOTES
1Long-term offset voltage is guaranteed by a 1,000 hour life test performed on three independent lots at 125°C, with an LTPD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
–4–
REV.
E
OP196/OP296/OP496
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
S, RU Package . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP196G, OP296G, OP496G, H . . . . . . . –40°C to +125°C
Junction Temperature Range
S, RU Package . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C
3
Package Type
JA
JC
Unit
8-Lead SOIC
8-Lead TSSOP
158
240
43
43
°C/W
°C/W
14-Lead SOIC
14-Lead TSSOP
120
180
36
35
°C/W
°C/W
NOTES
1Absolute maximum ratings apply to
packaged parts, unless otherwise noted.
2For supply voltages less than 15 V, the absolute maximum input voltage is
equal to the supply voltage.
3θJA is specified for the worst case conditions
; θJA is specified for device soldered in circuit board for SOIC and TSSOP packages.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP196/OP296/OP496 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. E
–5–
OP196/OP296/OP496–Typical Performance Characteristics
25
20
15
10
5
250
200
150
V
V
= 5V
S
= 2.5V
CM
V
T
= 3V
= 25؇C
S
T
= –40؇C TO ؉125؇C
A
A
COUNT = 400
100
50
0
0
–4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0
–250 –200 –150 –100 –50
0
50
100 150 200 250
INPUT OFFSET DRIFT, TCV – V/؇C
INPUT OFFSET VOLTAGE – V
OS
TPC 1. Input Offset Voltage Distribution
TPC 4. Input Offset Voltage Distribution (TCVOS)
25
250
200
150
100
50
V
V
= 12V
S
= 6V
V
T
= 5V
= 25؇C
CM
S
T = –40؇C TO ؉125؇C
A
20
15
10
5
A
COUNT = 400
0
0
–4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5
–250 –200 –150 –100 –50
0
50
100 150 200 250
INPUT OFFSET DRIFT, TCV – V/؇C
INPUT OFFSET VOLTAGE – V
OS
TPC 2. Input Offset Voltage Distribution
TPC 5. Input Offset Voltage Distribution (TCVOS
)
250
200
150
100
50
600
V
T
= 12V
= 25؇C
S
3V
V
12V
S
400
200
0
A
V
S
COUNT = 400
V
=
CM
2
–200
0
–400
–250 –200 –150 –100 –50
0
50
100 150 200 250
–75
–50
–25
0
25
50
75
100
125
150
INPUT OFFSET VOLTAGE – V
TEMPERATURE – ؇C
TPC 3. Input Offset Voltage Distribution
TPC 6. Input Offset Voltage vs. Temperature
–6–
REV.
E
OP196/OP296/OP496
25
20
15
10
5
1000
V
V
= 5V
S
= 2.5V
CM
V
= ؎1.5V
S
100
10
1
SOURCE
SINK
0
–75
–50
–25
0
25
50
75
100
125
150
0.001
0.01
0.1
LOAD CURRENT – mA
1
10
TEMPERATURE – ؇C
TPC 7. Input Bias Current vs. Temperature
TPC 10. Output Voltage to Supply Rail vs. Load Current
1000
16
V
= ؎2.5V
S
12
100
10
1
SOURCE
SINK
8
4
2
3
5
12
14
0.001
0.01
0.1
LOAD CURRENT – mA
1
10
SUPPLY VOLTAGE – V
TPC 8. Input Bias Current vs. Supply Voltage
TPC 11. Output Voltage to Supply Rail vs. Load Current
40
1000
V
T
= ؎2.5V
= 25؇C
S
A
30
20
V
= ؎6V
S
100
10
SOURCE
0
SINK
–10
–20
–30
–40
10
1
0.001
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0 1.5
2.0 2.5
0.01
0.1
LOAD CURRENT – mA
1
10
COMMON-MODE VOLTAGE – V
TPC 9. Input Bias Current vs. Common-Mode Voltage
TPC 12. Output Voltage to Supply Rail vs. Load Current
REV. E
–7–
OP196/OP296/OP496
4.95
90
80
70
60
50
40
30
20
10
0
I
I
= 100A
L
V
= ؎2.5V
= –40؇C
S
T
A
4.70
4.45
4.2
= 1mA
L
GAIN
0
I
= 2mA
45
L
90
V
= 5V
S
PHASE
3.85
3.7
135
180
225
–10
–75
–50
–25
0
25
50
75
100 125
150
10
100
1k
10k
100k
1M
TEMPERATURE – ؇C
FREQUENCY – Hz
TPC 13. Output Voltage Swing vs. Temperature
TPC 16. Open-Loop Gain and Phase vs. Frequency
(No Load)
0.80
90
V
= 5V
S
V
T
= ؎2.5V
= 125؇C
S
A
80
70
60
50
40
30
20
10
0
0.60
0.50
0.30
0.10
I
= –1mA
L
GAIN
0
45
90
PHASE
135
180
225
I
= –100A
L
–10
–75 –50
–25
0
25
50
75
100
125
150
10
100
1k
10k
100k
1M
TEMPERATURE – ؇C
FREQUENCY – Hz
TPC 14. Output Voltage Swing vs. Temperature
TPC 17. Open-Loop Gain and Phase vs. Frequency
(No Load)
90
950
V
= 5V
V
T
= ؎2.5V
= 25؇C
S
S
80
70
60
50
40
30
20
10
0
0.3V
< V < 4.7V
O
= 100k⍀
A
800
650
500
350
200
R
L
GAIN
0
45
90
PHASE
135
180
225
–10
10
100
1k
10k
100k
1M
–75
–50
–25
0
25
50
75
100
125 150
FREQUENCY – Hz
TEMPERATURE – ؇C
TPC 18. Open-Loop Gain vs. Temperature
TPC 15. Open-Loop Gain and Phase vs. Frequency
(No Load)
–8–
REV.
E
OP196/OP296/OP496
160
140
120
100
80
600
500
400
300
200
100
0
V
= ؎2.5V
= 25؇C
S
V
T
= 5V
S
T
A
= 25؇C
ALL CHANNELS
A
60
40
20
0
–20
–40
150
100
50
10
2
1
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
LOAD – k⍀
TPC 19. Open-Loop Gain vs. Resistive Load
TPC 22. CMRR vs. Frequency
70
160
140
120
100
80
V
T
= 5V
= 25؇C
V
= ؎2.5V
= 10k⍀
= 25؇C
S
A
S
60
50
R
T
L
A
40
30
+PSRR
20
60
10
40
–PSRR
0
20
–10
–20
–30
0
–20
–40
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
TPC 23. PSRR vs. Frequency
TPC 20. Closed-Loop Gain vs. Frequency
6
5
4
3
2
1000
V
V
A
R
= ؎2.5V
= 5V p-p
= 1
S
900
800
700
600
500
400
300
200
100
0
IN
V
T
= ؎2.5V
= 25؇C
S
A
V
L
= 100k⍀
A
= 10
CL
A
= 1
CL
1
0
1k
10k
100k
FREQUENCY – Hz
1M
100
1k
10k
FREQUENCY – Hz
100k
1M
TPC 21. Output Impedance vs. Frequency
TPC 24. Maximum Output Swing vs. Frequency
REV. E
–9–
OP196/OP296/OP496
90
80
70
60
50
40
0.6
0.5
0.4
0.3
0.2
0.1
0
V
T
= ؎2.5V
= 25؇C
= 0V
S
A
V
CM
V
= 12V
S
V
= 5V
S
V
= 3V
S
30
20
–75 –50 –40 –25
0
25 50
75
85 100 125 150
1
10
100
FREQUENCY – Hz
1k
TEMPERATURE – ؇C
TPC 25. Supply Current/Amplifier vs. Temperature
TPC 28. Input Bias Current Noise Density vs. Frequency
55
10
T
= 25؇C
V
= ؎6V
= 25؇C
8
6
A
S
T
A
TO 0.1%
؉OUTPUT SWING
50
45
40
35
4
2
0
–2
–4
–6
–8
–10
– OUTPUT SWING
1
3
5
7
9
11
12
13
0
5
10
15
20
25
30
SETTLING TIME – s
SUPPLY VOLTAGE – V
TPC 29. Settling Time to 0.1% vs. Step Size
TPC 26. Supply Current/Amplifier vs. Supply Voltage
80
V
T
= ؎2.5V
= 25؇C
= 0V
S
70
60
50
40
30
20
10
0
2mV
A
1s
V
CM
100
90
10
V
= ؎2.5V
S
0%
A
= 10k
V
e
= 0.8V p-p
n
1
10
100
FREQUENCY – Hz
1k
TPC 30. 0.1 Hz to 10 Hz Noise
TPC 27. Voltage Noise Density vs. Frequency
–10–
REV.
E
OP196/OP296/OP496
V
R
= ؎2.5V
= 10k⍀
L
S
100
90
100mV
100
90
V
=
2.5V
S
A
R
C
= 1
V
L
10
= 10k⍀
= 100pF
= 25؇C
10
0%
0V
0%
L
T
A
20mV
2s
1V
10s
TPC 31. Small Signal Transient Response
TPC 33. Large Signal Transient Response
V
= ؎2.5V
= 100k⍀
S
R
100
90
L
100
100mV
90
V
= ؎2.5V
= 1
S
A
R
C
T
V
L
L
10
10
= 100k⍀
= 100pF
= 25؇C
0%
0%
0V
1V
10s
20mV
A
2s
TPC 32. Small Signal Transient Response
TPC 34. Large Signal Transient Response
CH A: 40.0V FS
MKR: 36.8V/ Hz
5.00V/DIV
10Hz
0Hz
MKR: 1.00Hz
BW: 145mHz
TPC 35. 1/f Noise Corner, VS = 5 V, AV = 1,000
V
CC
R2
R1
R8
R7
I1
R6
I4
I5
D3
Q22
D9
QL1
Q11
Q12
Q6
Q5
Q7
D4
Q17
D8
Q21
2x
2x
Q4
QC1
Q3
CC2
OUT
1x
1x
CF1
1x
1x
CF2
Q13
Q14
Q8
2x
D5
D6
2x
Q10
Q18
Q19
1x
Q9
2x
+IN
Q1
Q2
QC2
Q23
R5
–IN
CC1
R9
R3A
R3B
R4A
R4B
Q20
1.5x
I3
I2
Q16
Q15
D7
D10
1x
V
EE
1
*
5
*
*OP196 ONLY
TPC 36. Simplified Schematic
–11–
REV. E
OP196/OP296/OP496
APPLICATIONS INFORMATION
Functional Description
the supply rails. In the circuit of Figure 2, the source ampli-
tude is 15 V, while the supply voltage is only 5 V. In this
case, a 2 kΩ source resistor limits the input current to 5 mA.
The OP196 family of operational amplifiers is comprised of single-
supply, micropower, rail-to-rail input and output amplifiers. Input
offset voltage (VOS) is only 300 µV maximum, while the output
will deliver 5 mA to a load. Supply current is only 50 µA, while
bandwidth is over 450 kHz and slew rate is 0.3 V/µs. TPC 36 is
a simplified schematic of the OP196—it displays the novel cir-
cuit design techniques used to achieve this performance.
5V
V
5V
S
A
= 1
V
100
90
V
IN
0
Input Overvoltage Protection
V
OUT
The OPx96 family of op amps uses a composite PNP/NPN
input stage. Transistor Q1 in Figure 36 has a collector-base
voltage of 0 V if +IN = VEE. If +IN then exceeds VEE, the junc-
tion will be forward biased and large diode currents will flow,
which may damage the device. The same situation applies to
+IN on the base of transistor Q5 being driven above VCC. There-
fore, the inverting and noninverting inputs must not be driven
above or below either supply rail unless the input current is
limited.
10
0
0%
5V
1ms
TIME – 1ns/DIV
Figure 2. Output Voltage Phase Reversal Behavior
Input Offset Voltage Nulling
The OP196 provides two offset adjust terminals that can be
used to null the amplifier’s internal VOS. In general, operational
amplifier terminals should never be used to adjust system offset
voltages. A 100 kΩ potentiometer, connected as shown in Fig-
ure 3, is recommended to null the OP196’s offset voltage. Offset
nulling does not adversely affect TCVOS performance, providing
that the trimming potentiometer temperature coefficient does
not exceed 100 ppm/°C.
Figure 1 shows the input characteristics for the OPx96 family.
This photograph was generated with the power supply pins
connected to ground and a curve tracer’s collector output drive
connected to the input. As shown in the figure, when the input
voltage exceeds either supply by more than 0.6 V, internal
pn-junctions energize and permit current flow from the inputs
to the supplies. If the current is not limited, the amplifier may
be damaged. To prevent damage, the input current should be
limited to no more than 5 mA.
V+
7
2
8
OP196
6
6
4
100
3
5
90
4
1
2
0
100k⍀
V–
–2
10
–4
Figure 3. Offset Nulling Circuit
Driving Capacitive Loads
OP196 family amplifiers are unconditionally stable with capaci-
tive loads less than 170 pF. When driving large capacitive loads
in unity-gain configurations, an in-the-loop compensation
technique is recommended, as illustrated in Figure 4.
0%
–6
–8
–1.5 –1 –0.5
0
0.5
1
1.5
INPUT VOLTAGE – V
Figure 1. Input Overvoltage I-V Characteristics of the
OPx96 Family
R
R
G
F
Output Phase Reversal
V
IN
Some other operational amplifiers designed for single-supply
operation exhibit an output voltage phase reversal when their
inputs are driven beyond their useful common-mode range.
Typically for single-supply bipolar op amps, the negative supply
determines the lower limit of their common-mode range. With
these common-mode limited devices, external clamping diodes
are required to prevent input signal excursions from exceeding
the device’s negative supply rail (i.e., GND) and triggering
output phase reversal.
C
F
R
X
V
OP296
OUT
C
L
R
R
G
O
R
=
WHERE R = OPEN-LOOP OUTPUT RESISTANCE
O
X
R
F
) (R
|
)
C R
L O
+ R
I
F
G
C
I +
(
|A
R
CL
F
The OPx96 family of op amps is free from output phase reversal
effects due to its novel input structure. Figure 2 illustrates the
performance of the OPx96 op amps when the input is driven
beyond the supply rails. As previously mentioned, amplifier
input current must be limited if the inputs are driven beyond
Figure 4. In-the-Loop Compensation Technique for
Driving Capacitive Loads
–12–
REV. E
OP196/OP296/OP496
A Micropower False-Ground Generator
same potential and no current flows in R1. Since there is no
current flow in R1, the same condition must exist in R2; thus,
the output of the circuit tracks the input signal. When the input
signal is below 0 V, the output voltage of A1 is forced to 0 V.
This condition now forces A2 to operate as an inverting voltage
follower because the noninverting terminal of A2 is also at 0 V.
The output voltage of VOUTA is then a full-wave rectified
version of the input signal. A resistor in series with A1’s
noninverting input protects the ESD diodes when the input
signal goes below ground.
Some single supply circuits work best when inputs are biased
above ground, typically at 1/2 of the supply voltage. In these
cases, a false-ground can be created by using a voltage divider
buffered by an amplifier. One such circuit is shown in Figure 5.
This circuit will generate a false-ground reference at 1/2 of the
supply voltage, while drawing only about 55 µA from a 5 V
supply. The circuit includes compensation to allow for a 1 µF
bypass capacitor at the false-ground output. The benefit of a
large capacitor is that not only does the false-ground present a
very low dc resistance to the load, but its ac impedance is low as well.
Square Wave Oscillator
The oscillator circuit in Figure 7 demonstrates how a rail-to-rail
output swing can reduce the effects of power supply variations
on the oscillator’s frequency. This feature is especially valuable
in battery powered applications, where voltage regulation may
not be available. The output frequency remains stable as the
supply voltage changes because the RC charging current, which
is derived from the rail-to-rail output, is proportional to the
supply voltage. Since the Schmitt trigger threshold level is also
proportional to supply voltage, the frequency remains relatively
independent of supply voltage. For a supply voltage change
from 9 V to 5 V, the output frequency only changes about 4 Hz.
The slew rate of the amplifier limits the oscillation frequency to
a maximum of about 200 Hz at a supply voltage of 5 V.
5V OR 12V
10k⍀
0.022F
240k⍀
2
3
7
100⍀
6
2.5V OR 6V
OP196
1F
4
240k⍀
1F
Figure 5. A Micropower False-Ground Generator
Single-Supply Half-Wave and Full-Wave Rectifiers
An OP296, configured as a voltage follower operating from a
single supply, can be used as a simple half-wave rectifier in low
frequency (<400 Hz) applications. A full-wave rectifier can be
configured with a pair of OP296s as illustrated in Figure 6.
V+
100k⍀
59k⍀
8
4
3
2
R2
R1
1
FREQ OUT
1
100k⍀
100k⍀
100k⍀
1/2
f
=
< 200Hz @ V+ = 5V
RC
OSC
OP296/
OP496
5V
8
R
V
A
6
5
OUT
2k⍀
2Vp-p
500Hz
FULL-WAVE
RECTIFIED
OUTPUT
A2
7
3
2
C
<
1
A1
1/2
OP296
4
1/2
OP296
Figure 7. Square Wave Oscillator Has Stable Frequency
Regardless of Supply Voltage Changes
V
B
OUT
HALF-WAVE
RECTIFIED
OUTPUT
A 3 V Low Dropout, Linear Voltage Regulator
Figure 8 shows a simple 3 V voltage regulator design. The regu-
lator can deliver 50 mA load current while allowing a 0.2 V
dropout voltage. The OP296’s rail-to-rail output swing easily
drives the MJE350 pass transistor without requiring special
drive circuitry. With no load, its output can swing to less than
the pass transistor’s base-emitter voltage, turning the device
nearly off. At full load, and at low emitter-collector voltages, the
transistor beta tends to decrease. The additional base current is
easily handled by the OP296 output.
1V
500mV
500µs
100
90
INPUT
V
B
OUT
(HALF-WAVE
OUTPUT)
f = 500Hz
10
V
A
0%
OUT
(FULL-WAVE
OUTPUT)
500mV
The AD589 provides a 1.235 V reference voltage for the regula-
tor. The OP296, operating with a noninverting gain of 2.43,
drives the base of the MJE350 to produce an output voltage of
3.0 V. Since the MJE350 operates in an inverting (common-
emitter) mode, the output feedback is applied to the OP296’s
noninverting input.
Figure 6. Single-Supply Half-Wave and Full-Wave
Rectifiers Using an OP296
The circuit works as follows: When the input signal is above
0 V, the output of amplifier A1 follows the input signal. Since
the noninverting input of amplifier A2 is connected to A1’s
output, op amp loop control forces A2’s inverting input to the
same potential. The result is that both terminals of R1 are at the
REV. E
–13–
OP196/OP296/OP496
The next two DACs, B and C, sum their outputs into the other
OP296 amplifier. In this circuit DAC C provides the coarse
output voltage setting and DAC B is used for fine adjustment.
The insertion of R1 in series with DAC B attenuates its contri-
bution to the voltage sum node at the DAC C output.
I
<
50mA
L
MJE 350
V
O
V
IN
44.2k⍀
1%
100F
5V TO 3.2V
8
3
2
30.9k⍀
1%
1/2
OP296
1
A High-Side Current Monitor
4
In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a result,
monitoring and limiting device power dissipation is of prime
importance in these designs. The circuit illustrated in Figure 11
is an example of a 5 V, single-supply high-side current monitor
that can be incorporated into the design of a voltage regulator
with fold-back current limiting or a high current power supply
with crowbar protection. This design uses an OP296’s rail-to-
rail input voltage range to sense the voltage drop across a 0.1 Ω
current shunt. A p-channel MOSFET is used as the feedback
element in the circuit to convert the op amp’s differential input
voltage into a current. This current is then applied to R2 to gen-
erate a voltage that is a linear representation of the load current.
The transfer equation for the current monitor is given by:
1000pF
43k⍀
1.235V
AD589
Figure 8. 3 V Low Dropout Voltage Regulator
Figure 9 shows the regulator’s recovery characteristics when its
output underwent a 20 mA to 50 mA step current change.
2V
50mA
STEP
CURRENT
CONTROL
100
90
WAVEFORM
30mA
RSENSE
10
× I
L
OUTPUT
Monitor Output = R2 ×
0%
R1
10mV
50µs
For the element values shown, the Monitor Output’s transfer
characteristic is 2.5 V/A.
Figure 9. Output Step Load Current Recovery
R
SENSE
I
L
0.1⍀
Buffering a DAC Output
5V
5V
®
Multichannel TrimDACs such as the AD8801/AD8803, are
5V
8
widely used for digital nulling and similar applications. These
DACs have rail-to-rail output swings, with a nominal output
resistance of 5 kΩ. If a lower output impedance is required, an
OP296 amplifier can be added. Two examples are shown in
Figure 10. One amplifier of an OP296 is used as a simple buffer
to reduce the output resistance of DAC A. The OP296 provides
rail-to-rail output drive while operating down to a 3 V supply
and requiring only 50 µA of supply current.
R1
100⍀
3
2
1/2
OP296
4
1
S
D
G
M1
3N163
MONITOR
OUTPUT
R2
2.49k⍀
5V
Figure 11. A High-Side Load Current Monitor
V
V
REFH DD
A Single-Supply RTD Amplifier
OP296
V
H
The circuit in Figure 12 uses three op amps on the OP496 to
produce a bridge driver for an RTD amplifier while operating
from a single 5 V supply. The circuit takes advantage of the
OP496’s wide output swing to generate a bridge excitation
voltage of 3.9 V. An AD589 provides a 1.235 V reference for
the bridge current. Op amp A1 drives the bridge to maintain
1.235 V across the parallel combination of the 6.19 kΩ and
2.55 MΩ resistors, which generates a 200 µA current source.
This current divides evenly and flows through both halves of
the bridge. Thus, 100 µA flows through the RTD to generate
an output voltage which is proportional to its resistance. For
improved accuracy, a 3-wire RTD is recommended to balance
the line resistance in both 100 Ω legs of the bridge.
V
SIMPLE BUFFER
0V TO 5V
L
+4.983V
V
H
+1.1mV
V
L
R1
100k⍀
V
H
SUMMER CIRCUIT
WITH FINE TRIM
ADJUSTMENT
V
L
AD8801/
AD8803
V
GND
REFL
DIGITAL INTERFACING
OMITTED FOR CLARITY
Figure 10. Buffering a TrimDAC OutputTPC
TrimDAC is a registered trademark of Analog Devices Inc.
–14–
REV. E
OP196/OP296/OP496
Amplifiers A2 and A3 are configured in a two op amp instru-
mentation amplifier configuration. For ease of measurement,
the IA resistors are chosen to produce a gain of 259, so that
each 1°C increase in temperature results in a 10 mV increase in
the output voltage. To reduce measurement noise, the band-
width of the amplifier is limited. A 0.1 µF capacitor, connected
in parallel with the 100 kΩ resistor on amplifier A3, creates a
pole at 16 Hz.
GAIN = 259
5V
200⍀
10-TURNS
26.7k⍀
26.7k⍀
1/4
OP496
1/4
OP496
A3
V
100⍀
RTD
OUT
A2
100⍀
2.55M⍀
392⍀
100k⍀
0.1F
392⍀
1/4
OP496
6.17k⍀
20k⍀
100k⍀
A1
NOTE:
AD589
37.4k⍀
ALL RESISTORS 1% OR BETTER
5V
Figure 12. A Single-Supply RTD Amplifier
CIN
1
2
1P
* OP496 SPICE Macro-model
REV. C, 5/95
ARG / ADSC
*
*
*
* GAIN STAGE
*
* Copyright 1995 by Analog Devices, Inc.
EREF 98
0
POLY(2)
POLY(2)
251.641MEG
8P
DX
DX
(99,0) (50,0) 0 0.5 0.5
(6,5) (13,12) 0 10U 10U
*
G1
R10
CC
D1
D2
*
98
15
15
15
50
15
98
49
99
15
* Refer to “README.DOC” file for License Statement.
* Use of this model indicates your acceptance of the
* terms and provisions in the License Statement.
*
* Node assignments
*
Noninverting input
Inverting input
* COMMON-MODE STAGE
*
*
*
Positive supply
ECM 16
98
17
98
POLY(2)
1MEG
10
(1,98) (2,98)
0
0.5 0.5
*
Negative supply
Output
R11
R12
*
16
17
*
*
*
* OUTPUT STAGE
*
ISY
.SUBCKT OP496
1
2
99
50
49
*
99
50
50
35
37
37
39
38
42
40
40
41
41
43
42
43
43
45
46
46
47
47
48
51
46
48
44
20U
POLY(1)
* INPUT STAGE
*
EIN 35
Q24 37
QD4 37
Q27 40
R5
R6
Q26 39
QD5 40
Q28 41
QL1 37
R7
I4
(15,98) 1.42735
1
36
50
99
99
QN
QP
QP
1
1
1
IREF 21
QB1 21
QB2 22
50
21
21
21
22
22
4
1U
99
99
99
50
50
7
38
99
99
99
50
50
50
50
50
50
99
99
QP
QP
QP
QN
QN
QN
QN
QN
QN
QP
QP
1
1
38
36
99
150K
45K
50
QB3
4
1.5
QB4 22
QB5 11
2
3
2
2
1
1
2
2
50
50
50
99
QN
QN
QN
QP
3
1
1
1
39
Q1
Q2
Q3
Q4
Q5
Q6
EOS
Q7
Q8
Q9
5
44
6
4
8
99
4
4
4
7
99
99
10.7K
2U
50
4
8
50
50
3
99
99
12
1
7
QD7 42
QD6 43
Q29 47
Q30 44
QD10 45
50
50
50
50
50
QN
QN
QN
QN
QN
2
3
8
42
2
2
POLY(1)
(17,98) 35U
1
44
1
1.5
1
1
9
50
QN
QN
QP
QP
QP
QP
2
2
2
2
1
1
50
3
10
50
99
99
99
99
50
11
11
11
11
5
9
R9
45
175
48
Q10 13
Q11 11
Q12 11
10
Q31 46
QD8 47
QD9 48
99
99
99
QP
QP
QP
1
1
5
9
48
51
10
R1
99
99
12
13
1
50K
50K
50K
50K
0.75N
3.183P
3.183P
R8
I5
99
99
2.9K
1U
99
R2
6
R3
R4
IOS
C10
C11 12
50
50
2
Q32 49
Q33 49
.MODEL
.MODEL
.MODEL
.ENDS
99
50
QP
QN
10
4
50
DX D()
QN NPN(BF=120VAF=100)
QP PNP(BF=80 VAF=60)
5
6
13
REV. E
–15–
OP196/OP296/OP496
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure13. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 14. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
–18–
REV. E
OP196/OP296/OP496
3.10
3.00
2.90
8
5
4
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65 BSC
0.15
0.05
1.20
MAX
8°
0°
0.75
0.60
0.45
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
0.20
0.09
COMPLIANT TO JEDEC STANDARDS MO-153-AA
Figure 15. 8-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-8)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 16. 14-Lead Thin Shrink Small Outline Package
(RU-14)
Dimensions shown in millimeters
REV. E
–17–
OP196/OP296/OP496
ORDERING GUIDE
Model1, 2
OP196GSZ
OP196GSZ-REEL
OP196GSZ-REEL7
OP296GSZ
OP296GSZ-REEL
OP296GSZ-REEL7
OP296HRUZ-REEL
OP496GS
OP496GS-REEL
OP496GS-REEL7
OP496GSZ
OP496GSZ-REEL
OP496GSZ-REEL7
OP496HRUZ-REEL
Temperature Range
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead TSSOP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
Package Option
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
−40°C to +85°C (Ambient)
R-8
R-8
R-8
R-8
R-8
R-8
RU-8
R-14
R-14
R-14
R-14
R-14
R-14
RU-14
1 Z = RoHS Compliant Part.
2 Note OP496GS, OP496GS-REEL, and OP496GS-REEL7 are not RoHS compliant parts.
–18–
REV. E
OP196/OP296/OP496
12/10—Rev. C to Rev. D
REVISION HISTORY
Change to Data Sheet Title ..............................................................1
Deleted DIP Pin Configuration Figures.........................................1
Changes to Absolute Maximum Ratings Table and Package
Type Table, Moved Ordering Guide ...............................................5
Updated Outline Dimensions........................................................16
Changes to Ordering Guide...........................................................16
9/11—Rev. D to Rev. E
Changes to General Description Section.......................................1
Changes to Electrical Specifications Table (@VS = 5.0 V),
Output Voltage Swing High and Output Swing Low Parameters,
Conditions Column ..........................................................................2
Change to Electrical Specifications Table (@VS = 12.0 V),
Output Swing Low Parameter, Conditions Column ....................4
Changes to Ordering Guide...........................................................18
1/02—Rev. B to Rev. C
Edits to Typical Performance Characteristics .............................10
©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00312-0-9/11(E)
REV. E
–19–
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