OP297FS-REEL7 [ADI]
Dual Low Bias Current Precision Operational Amplifier; 双通道，低偏置电流精密运算放大器
| 型号： | OP297FS-REEL7 |
| 厂家： | 
ADI |
| 描述： | Dual Low Bias Current Precision Operational Amplifier |
| 文件： | 总16页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8/21/97 4:00 PM
Dual Low Bias Current
Precision Operational Amplifier
a
OP297
FEATURES
PIN CONNECTIONS
Precision Performance in Standard SO-8 Pinout
Low Offset Voltage: 50 V max
Low Offset Voltage Drift: 0.6 V/؇C max
Very Low Bias Current:
Plastic Epoxy-DIP (P Suffix)
8-Pin Cerdip (Z Suffix)
8-Pin Narrow Body SOIC (S Suffix)
␣ ␣ +25؇C (100 pA max)
␣␣␣55؇C to +125؇C (450 pA max)
Very High Open-Loop Gain (2000 V/mV min)
Low Supply Current (Per Amplifier): 625 A max
Operates From 62 V to 620 V Supplies
High Common-Mode Rejection: 120 dB min
Pin Compatible to LT1013, AD706, AD708, OP221,
␣ ␣ LM158, and MC1458/1558 with Improved Performance
OUT A 1
8 V+
B
A
–
–IN A
+IN A
V–
2
3
4
7 OUT B
6 –IN B
–
5
+IN B
APPLICATIONS
Strain Gauge and Bridge Amplifiers
High Stability Thermocouple Amplifiers
Instrumentation Amplifiers
Photo-Current Monitors
High-Gain Linearity Amplifiers
Long-Term Integrators/Filters
Sample-and-Hold Amplifiers
Peak Detectors
Errors due to common-mode signals are eliminated by the
OP297’s common-mode rejection of over 120 dB. The
OP297’s power supply rejection of over 120 dB minimizes
offset voltage changes experienced in battery powered systems.
Supply current of the OP297 is under 625 µA per amplifier and
it can operate with supply voltages as low as ±2 V.
The OP297 utilizes a super-beta input stage with bias current
cancellation to maintain picoamp bias currents at all tempera-
tures. This is in contrast to FET input op amps whose bias
currents start in the picoamp range at 25°C, but double for
every 10°C rise in temperature, to reach the nanoamp range
above 85°C. Input bias current of the OP 297 is under 100 pA
at 25°C and is under 450 pA over the military temperature
range.
Logarithmic Amplifiers
Battery-Powered Systems
GENERAL DESCRIPTION
The OP297 is the first dual op amp to pack precision perfor-
mance into the space-saving, industry standard 8-pin SO pack-
age. Its combination of precision with low power and extremely
low input bias current makes the dual OP297 useful in a wide
variety of applications.
Combining precision, low power and low bias current, the
OP297 is ideal for a number of applications including instru-
mentation amplifiers, log amplifiers, photodiode preamplifiers
and long-term integrators. For a single device, see the OP97;
for a quad, see the OP497.
Precision performance of the OP297 includes very low offset,
under 50 µV, and low drift, below 0.6 µV/°C. Open-loop gain
exceeds 2000 V/mV insuring high linearity in every application.
400
60
I
–
B
1200 UNITS
V
V
= ±15V
T
V
V
= +25°C
= ±15V
S
A
= 0V
CM
S
40
20
= 0V
CM
300
200
100
0
I
+
B
0
I
OS
20
–40
–60
–100 –80 –60 –40 –20
0
20 40 60 80 100
–75 –50 –25
0
25 50 75 100 125
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
Figure 1. Low Bias Current Over Temperature
REV. D
Figure 2. Very Low Offset
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1997
8/21/97 4:00 PM
OP297–SPECIFICATIONS
(@ VS = ؎15 V, TA = +25؇C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
OP297A/E
OP297F
OP297G
Parameter
Symbol Conditions
Min Typ Max Min Typ Max Min Typ Max
Units
Input Offset Voltage
Long-Term Input
Voltage Stability
Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise
Voltage Density
Input Noise Current Density
Input Resistance
VOS
25
50
50
100
80
200
µV
0.1
20
20
0.5
20
17
20
0.1
35
35
0.5
20
17
20
0.1
50
50
0.5
20
17
20
µV/mo
pA
pA
µV p-p
nV/√Hz
nV/√Hz
fA√Hz
IOS
IB
en p-p
en
en
in
VCM = 0 V
VCM = 0 V
0.1 Hz to 10 Hz
fO = 10 Hz
fO = 1000 Hz
fO = 10 Hz
100
±100
150
±150
200
±200
Differential Mode
Input Resistance
Common-Mode
RIN
30
30
30
MΩ
GΩ
RINCM
500
500
500
Large-Signal
VO = ±10 V
Voltage Gain
AVO
IVR
CMR
PSR
VO
RL = 2 kΩ
(Note 1)
VCM = ±13 V
VS = ±2 V to ±20 V 120
RL = 10 kΩ
RL = 2 kΩ
2000 4000
±13 ±14
1500 3200
±13 ±14
1200 3200
±13 ±14
V/mV
V
dB
dB
V
V
µA
V
Input Voltage Range
Common-Mode Rejection
Power Supply Rejection
Output Voltage Swing
120
140
130
114
114
135
125
114
114
135
125
±13 ±14
±13 ±13.7
525
±13 ±14
±13 ±13.7
525
±13 ±14
±13 ±13.7
525
VO
Supply Current Per Amplifier ISY
Supply Voltage
Slew Rate
Gain Bandwidth Product
Channel Separation
No Load
Operating Range
625
625
625
±20
VS
SR
±2
±20 ±2
0.05 0.15
±20 ±2
0.05 0.15
0.05 0.15
500
V/µs
kHz
dB
GBWP AV = +1
CS
500
150
500
150
V
O = 20 V p–p
150
fO = 10 Hz
Input Capacitance
CIN
3
3
3
pF
NOTES
1Guaranteed by CMR test.
Specifications subject to change without notice.
(@ VS = ؎15 V, –55؇C ≤ TA ≤ +125؇C for OP297A, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
OP297A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input Offset Voltage
Average Input Offset Voltage Drift
Input Offset Current
Input Bias Current
Large-Signal Voltage Gain
Input Voltage Range
Common-Mode Rejection
Power Supply Rejection
Output Voltage Swing
Supply Current Per Amplifier
Supply Voltage
VOS
TCVOS
IOS
45
0.2
60
60
2700
±13.5
130
125
±13.4
575
100
0.6
450
±450
µV
µV/°C
pA
pA
V/mV
V
dB
dB
V
VCM = 0 V
VCM = 0 V
VO = ±10 V, RL = 2 kΩ
(Note 1)
VCM = ±13
VS = ±2.5 V to ±20 V
RL = 10 kΩ
No Load
IB
AVO
IVR
CMR
PSR
VO
ISY
VS
1200
±13
114
114
±13
750
±20
µA
V
Operating Range
±2.5
NOTES
1Guaranteed by CMR test.
Specifications subject to change without notice.
–2–
REV. D
8/21/97 4:00 PM
OP297
(@ V = ؎15 V, –40؇C ≤ T ≤ +85؇C for OP297E/F/G, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
S
A
OP297E
Min Typ Max
OP297F
Min Typ
OP297G
Max Min Typ Max
Parameter
Symbol
Conditions
Units
Input Offset Voltage
Average Input Offset
Voltage Drift
Input Offset Current
Input Bias Current
Large-Signal Voltage Gain
VOS
35
100
80
300
110
400
µV
TCVOS
IOS
IB
0.2
50
50
0.6
450
±450
0.5
80
80
2.0
750
±750
0.6
80
80
2.0
750
±750 pA
µV/°C
pA
VCM = 0 V
VCM = 0 V
VO = ±10 V,
RL = 2 kΩ
(Note 1)
VCM = ±13
VS = ±2.5 V
to ±20 V
AVO
1200 3200
1000 2500
±13 ±13.5
700
±13
108
2500
±13.5
130
V/mV
V
dB
Input Voltage Range
Common-Mode Rejection
Power Supply Rejection
IVR
CMR
PSR
±13
114
±13.5
130
108
130
114
±13
0.15
±13.4
550
108
0.15
±13 ±13.4
550
108
±13
0.3
±13.4
550
dB
V
µA
V
Output Voltage Swing
Supply Current Per Amplifier ISY
Supply Voltage
VO
RL = 10 kΩ
No Load
Operating Range ±2.5
750
±20
750
±20
750
±20
VS
±2.5
±2.5
NOTES
1Guaranteed by CMR test.
Specifications subject to change without notice.
(@ VS = ؎15 V, TA = +25؇C, unless otherwise noted.)
Wafer Test Limits
Parameter
Symbol
Conditions
Limit
Units
Input Offset Voltage
Input Offset Current
VOS
IOS
200
200
µV max
pA max
VCM = 0 V
VCM = 0 V
VO = ±10 V, RL = 2 kΩ
(Note 1)
Input Bias Current
IB
±200
1200
±13
114
114
±13
625
pA max
V/mV min
V min
dB min
dB min
V min
Large-Signal Voltage Gain
Input Voltage Range
Common-Mode Rejection
Power Supply
Output Voltage Swing
Supply Current Per Amplifier
AVO
IVR
CMR
PSR
VO
VCM = ±13 V
VS = ±2 V to ±l 8 V
RL = 2 kΩ
No Load
ISY
µA max
NOTES
1. Guaranteed by CMR test.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
DICE CHARACTERISTICS
Dimension shown in inches and (mm).
Contact factory for latest dimensions
+V
OUTPUT A
S
0.118 (3.00)
–INPUT A
+INPUT A
OUTPUT B
–INPUT B
+INPUT B
–V
S
0.074 (1.88)
REV. D
–3–
8/21/97 4:00 PM
OP297
ABSOLUTE MAXIMUM RATINGS1
3
Package Type
Units
JA
JC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . 40 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP297A (Z) . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP297E, F (Z) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
OP297F, G (P, S) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature
8-Pin Cerdip (Z)
8-Pin Plastic DIP (P)
8-Pin SO (S)
134
96
150
12
37
41
°C/W
°C/W
°C/W
NOTES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2For supply voltages less than ±20 V, the absolute maximum input voltage is equal
to the supply voltage.
3θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in
socket for cerdip and P-DIP, packages; θJA is specified for device soldered to printed
circuit board for SO package.
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . .+300°C
ORDERING GUIDE1
Temperature Package
Range
Package
Option1
Model
Description
OP297AZ
OP297EZ
OP297EP
OP297FP
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Pin Cerdip
8-Pin Cerdip
8-Pin Plastic DIP
8-Pin Plastic DIP
8-Pin SO
8-Pin SO
8-Pin SO
8-Pin Plastic DIP
8-Pin SO
8-Pin SO
Q-8
Q-8
N-8
N-8
SO-8
SO-8
SO-8
N-8
SO-8
SO-8
SO-8
OP297FS
OP297FS-REEL
OP297FS-REEL7
OP297GP
OP297GS
OP297GS-REEL
OP297GS-REEL72
8-Pin SO
NOTES
1Burn-in is available on extended industrial temperature range parts in cerdip, and plastic DIP
packages. For outline information see Package Information section.
2For availability and burn-in information on SO packages, contact your local sales office.
–
1/2
OP-297
V
20V @ 10Hz
p-p
1
+
2kΩ
50kΩ
50Ω
–
1/2
V
2
OP-297
+
V
1
CHANNEL SEPARATION = 20 log
)
)
V /10000
2
Figure 3. Channel Separation Test Circuit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP297 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. D
8/21/97 4:00 PM
Typical Performance Characteristics–
OP297
400
250
200
150
100
50
400
1200 UNITS
T
V
V
= +25°C
= ±15V
= 0V
1200
UNITS
T
V
V
= +25°C
= ±15V
= 0V
A
1200 UNITS
A
T
V
V
= +25°C
= ±15V
A
S
S
S
CM
CM
= 0V
CM
300
200
100
300
200
100
0
0
0
–100 –80 –60 –40 –20
0
20 40 60 80 100
–100 –80 –60 –40 –20
0
20 40 60 80 100
–100 –80 –60 –40 –20
0
20 40 60 80 100
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET CURRENT (pA)
INPUT BIAS CURRENT (pA)
Figure 6. Typical Distribution of In-
put Offset Current
Figure 5. Typical Distribution of Input
Bias Current
Figure 4. Typical Distribution of Input
Offset Voltage
±3
60
60
T
A
= +25°C
= ±15V
= 0V
I –
T
V
= +25°C
= ±15V
B
A
V
V
= ±15V
S
V
V
S
S
= 0V
CM
40
20
40
20
I –
B
CM
I +
B
I +
B
±2
±1
0
0
0
I
OS
I
OS
–20
–40
–60
20
–40
–60
0
1
2
3
4
5
–15 –10
–5
0
5
10
15
–75 –50 –25
0
25 50 75 100 125
TIME AFTER POWER APPLIED (MINUTES)
COMMON-MODE VOLTAGE (VOLTS)
TEMPERATURE (°C)
Figure 9. Input Offset Voltage Warm-
Up Drift
Figure 8. Input Bias, Offset Current
vs. Common-Mode Voltage
Figure 7. Input Bias, Offset Current
vs. Temperature
100
10000
35
BALANCED OR UNBALANCED
BALANCED OR UNBALANCED
30
25
T
= –55°C
= +25°C
A
V
V
= ±15V
V
V
= ±15V
S
S
= 0V
= 0V
CM
CM
T
A
20
15
10
1
T
= +125°C
1000
100
10
A
10
5
V
S
= ±15V
OUTPUT SHORTED
TO GROUND
0
–5
–10
–15
–20
–25
–30
–35
T
= +125°C
A
–55°C
≤ T ≤ 125°C
A
T
= +25°C
= –55°C
A
A
T
A
= +25°C
T
0.1
10
100
1k
10k
100k 1M 10M
100
1k
10k 100k
1M
10M 100M
0
1
2
3
4
SOURCE RESISTANCE (Ω)
TIME FROM OUTPUT SHORT (MINUTES)
SOURCE RESISTANCE (Ω)
Figure 10. Effective Offset Voltage
vs. Source Resistance
Figure 11. Effective TCVOS vs. Source
Resistance
Figure 12. Short Circuit Current vs.
Time, Temperature
REV. D
–5–
8/21/97 4:00 PM
–Typical Performance Characteristics
OP297
1300
1200
1100
1000
900
160
140
120
100
80
140
120
100
80
NO LOAD
T
V
= +25°C
= ±15V
T
V
= +25°C
= ±15V
A
A
S
S
T
= +125°C
A
∆V = 10V
S
p-p
T
= +25°C
A
60
–PSR
60
+PSR
100
T
A
= –55°C
±15
40
40
20
800
0
20
0.1
1
10
1k 10k 100k 1M
1
10
100
1k
10k
100k 1M
0
±5
±10
±20
FREQUENCY (Hz)
FREQUENCY (Hz)
SUPPLY VOLTAGE (VOLTS)
Figure 13. Total Supply Current vs.
Supply Voltage
Figure 14. Noise Density vs.
Frequency
Figure 15. Open Loop Gain Linearity
10000
10
100
1000
100
10
T
V
= +25°C
= ±2V TO ±15V
T
T
= –55°C
A
T
V
= +25°C
= ±2V TO ±20V
A
A
S
T
= +25°C
S
A
1
0.1
0
= +125°C
CURRENT
NOISE
A
10Hz
1kHz
1000
VOLTAGE
NOISE
100
10
V
V
= ±15V
= ±10V
S
1kHz
O
10Hz
100
0.01
1
3
1
2
5
10
20
2
10
3
10
4
10
5
10
6
10
7
10
1
10
100
1000
LOAD RESISTANCE (kΩ)
SOURCE RESISTANCE (Ω)
FREQUENCY (Hz)
Figure 17. Total Noise Density vs.
Source Resistance
Figure 18. Maximum Output Swing
vs. Load Resistance
Figure 16. Common-Mode Rejection
vs. Frequency
35
35
R
V
= 10kΩ
= ±15V
= 0V
T
V
A
= +25°C
= ±15V
= +1
VCL
T
V
A
= +25°C
= ±15V
= +1
L
A
A
30
25
20
15
10
5
30
25
20
15
10
5
S
S
S
V
CM
VCL
T
A
T
A
T
A
= +125°C
= +25°C
= –55°C
1%THD
= 10kΩ
1%THD
= 1kHz
R
f
L
o
0
0
10
1k
100
LOAD RESISTANCE (Ω)
10k
100
10k
1k
FREQUENCY (Hz)
100k
–15
–10
–5
0
5
10
15
OUTPUT VOLTAGE (VOLTS)
Figure 21. Maximum Output Swing
vs. Frequency
Figure 20. Open Loop Gain vs. Load
Resistance
Figure 19. Power Supply Rejection
vs. Frequency
–6–
REV. D
8/21/97 4:00 PM
OP297
100
1000
100
10
70
60
50
40
30
20
10
0
T
= +25°C
V = ±15V
S
V
C
R
= ±15V
= 30pF
= 1MΩ
T
= +25°C
= ±15V
–EDGE
A
S
A
80
V
A
V
L
L
S
GAIN
= +1
= 100mV
VCL
OUT
60
p-p
+EDGE
PHASE
40
90
T
= –55°C
A
1
20
0
135
180
225
0.1
0.01
0.001
–20
–40
T
= +125°C
A
10
100
1k
10k
100k
100
1M
1k
10k
100
1M
10M
10
1000
100
10000
FREQUENCY (Hz)
LOAD CAPACITANCE (pF)
FREQUENCY (Hz)
Figure 23. Small Signal Overshoot
vs. Capacitance Load
Figure 24. Open Loop Output
Impedance vs Frequency
Figure 22. Open Loop Gain,
Phase vs. Frequency
APPLICATIONS INFORMATION
Extremely low bias current over the full military temperature
range makes the OP297 attractive for use in sample-and-hold
amplifiers, peak detectors, and log amplifiers that must operate
over a wide temperature range. Balancing input resistances is
not necessary with the OP297 Offset voltage and TCVOS are
degraded only minimally by high source resistance, even when
unbalanced.
100
90
The input pins of the OP297 are protected against large differ-
ential voltage by back-to-back diodes and current-limiting resis-
tors. Common-mode voltages at the inputs are not restricted,
and may vary over the full range of the supply voltages used.
10
0%
20mV
5µs
The OP297 requires very little operating headroom about the
supply rails, and is specified for operation with supplies as low
as +2 V. Typically, the common-mode range extends to within
one volt of either rail. The output typically swings to within one
volt of the rails when using a 10 kΩ load.
Figure 26. Small-Signal Transient Response
(CLOAD = 1000 pF, AVCL = +1)
100
90
AC PERFORMANCE
The OP297’S AC characteristics are highly stable over its full
operating temperature range. Unity-gain small-signal response is
shown in Figure 25. Extremely tolerant of capacitive loading on
the output, the OP297 displays excellent response even with
1000 pF loads (Figure 26).
10
0%
20mV
5µs
100
90
Figure 27. Large-Signal Transient Response
(AVCL = +1)
GUARDING AND SHIELDING
To maintain the extremely high input impedances of the
OP297, care must be taken in circuit board layout and manu-
10
0%
facturing. Board surfaces must be kept scrupulously clean and
free of moisture. Conformal coating is recommended to provide
20mV
5µs
Figure 25. Small-Signal Transient Response
(CLOAD = 100 pF, AVCL = +1)
REV. D
–7–
8/21/97 4:00 PM
OP297
UNITY-GAIN FOLLOWER
NONINVERTING AMPLIFIER
–
–
1/2
1/2
OP-297
OP-297
+
+
INVERTING AMPLIFIER
MINI-DIP
BOTTOM VIEW
8
1
–
1/2
OP-297
A
+
B
Figure 28. Guard Ring Layout and Connections
APPLICATIONS
a humidity barrier. Even a clean PC board can have 100 pA of
leakage currents between adjacent traces, so guard rings should
be used around the inputs. Guard traces are operated at a volt-
age close to that on the inputs, as shown in Figure 28, so that
leakage currents become minimal. In noninverting applications,
the guard ring should be connected to the common-mode volt-
age at the inverting input. In inverting applications, both inputs
remain at ground, so the guard trace should be grounded. Guard
traces should be on both sides of the circuit board.
PRECISION ABSOLUTE VALUE AMPLIFIER
The circuit of Figure 30 is a precision absolute value amplifier
with an input impedance of 30 MΩ. The high gain and low
TCVOS of the OP297 insure accurate operation with microvolt
input signals. In this circuit, the input always appears as a
common-mode signal to the op amps. The CMR of the OP297
exceeds 120 dB, yielding an error of less than 2 ppm.
+15V
C
2
OPEN-LOOP GAIN LINEARITY
0.1µF
The OP297 has both an extremely high gain of 2000 V/mV
minimum and constant gain linearity. This enhances the preci-
sion of the OP297 and provides for very high accuracy in high
closed loop gain applications. Figure 29 illustrates the typical
open-loop gain linearity of the OP297 over the military tempera-
ture range.
R
R
3
1
1kΩ
1kΩ
D
C
30pF
1
1
6
5
–
1N4148
8
1/2
OP-297
2
3
7
–
D
2
1/2
OP-297
1
0V < V
< 10V
OUT
+
V
+
IN
1N4148
C
3
4
R
2
R
= 10kΩ
= ±15V
= 0V
L
2kΩ
V
V
S
0.1µF
CM
T
T
T
= +125°C
= +25°C
= –55°C
A
A
A
–15V
Figure 30. Precision Absolute Value Amplifier
PRECISION CURRENT PUMP
Maximum output current of the precision current pump shown
in Figure 31 is ±10 mA. Voltage compliance is ± 10 V with
±15 V supplies. Output impedance of the current transmitter
exceeds 3 MΩ with linearity better than 16 bits.
–15
–10
–5
0
5
10
15
OUTPUT VOLTAGE (VOLTS)
Figure 29. Open-Loop Linearity of the OP297
–8–
REV. D
8/21/97 4:00 PM
OP297
PRECISION POSITIVE PEAK DETECTOR
In Figure 32, the CH must be of polystyrene, Teflon®*, or poly-
ethylene to minimize dielectric absorption and leakage. The
droop rate is determined by the size of CH and the bias current
of the OP297.
SIMPLE BRIDGE CONDITIONING AMPLIFIER
Figure 33 shows a simple bridge conditioning amplifier using
the OP297. The transfer function is:
∆R RF
VOUT =VREF
R + ∆R
R
R
3
The REF43 provides an accurate and stable reference voltage
for the bridge. To maintain the highest circuit accuracy, RF
should be 0.1% or better with a low temperature coefficient.
10kΩ
R
1
2
3
–
+
–
R
5
10kΩ
R
2
1/2
1
I
OUT
V
IN
OP-297
1kΩ
±10mA
100Ω
+
+15V
8
10kΩ
+15V
1N4148
0.1µF
2
5
6
–
+
1/2
6
5
1
8
–
2N930
R
4
OP-297
+
1kΩ
1/2
OP-297
7
3
1/2
OP-297
7
V
V
OUT
IN
1kΩ
+
4
10kΩ
0.1µF
–
C
H
4
–15V
RESET
1kΩ
V
V
IN
100Ω
IN
I
=
=
= 10mA/V
OUT
R
–15V
5
Figure 32. Precision Positive Peak Detector
Figure 31. Precision Current Pump
+5V
2
V
REF
2.5V
R
6
R
F
REF-43
4
R
2
3
–
1
1/2
OP-297
V
OUT
R
R + ∆R
+
+5V
∆R
R
F
V
V
REF
=
OUT
(
(
R + ∆R
R
6
5
8
–
1/2
OP-297
7
+
4
–5V
Figure 33. A Simple Bridge Conditioning Amplifier Using the OP297
*Teflon is a registered trademark of the Dupont Company
REV. D
–9–
8/21/97 4:00 PM
OP297
Exponentiating both sides of the equation leads to:
NONLINEAR CIRCUITS
Due to its low input bias currents, the OP297 is an ideal log
amplifier in nonlinear circuits such as the square and square-
root circuits shown in Figures 34 and 35. Using the squaring
circuit of Figure 34 as an example, the analysis begins by writing
a voltage loop equation across transistors Q1, Q2, Q3 and Q4.
2
(IIN
)
IO
=
IREF
Op amp A2 forms a current-to-voltage converter which gives
OUT = R2 × 10. Substituting (VIN/R1) for IIN and the above
V
equation for IO yields:
IIN
IS1
IIN
IS2
IO
IS3
IREF
IS4
VT1 ln
+VT2 ln
=VT3 ln
+VT4 ln
2
R2 VIN
IREF R1
VOUT
=
All the transistors of the MAT04 are precisely matched and at
the same temperature, so the IS and VT terms cancel, giving:
A similar analysis made for the square-root circuit of Figure 35
leads to its transfer function:
2 ln IIN = ln IO + ln IREF = ln (IO × IREF
)
(VIN )(IREF
R1
)
VOUT = R2
C
2
100pF
R
2
33kΩ
6
5
–
1/2
OP-297
2
7
V
OUT
I
O
A
+
1
2
Q
1
7
3
6
Q
2
5
MAT-04E
C
1
14
Q
13
8
Q
I
4
REF
9
100pF
3
V+
8
12
10
R
1
I
IN
2
3
–
V
IN
R
3
1/2
33kΩ
1
OP-297
A
+
50kΩ
1
R
4
4
50kΩ
–15V
V–
Figure 34. Squaring Amplifier
–10–
REV. D
8/21/97 4:00 PM
OP297
R
2
33kΩ
C
2
100pF
6
5
–
7
1/2
OP-297
V
OUT
I
O
+
MAT-04E
Q
1
3
1
I
I
IN
REF
2
6
C
1
14
13
9
Q
4
100pF
V+
12
7
8
Q
Q
3
2
R
10
5
1
2
8
–
V
IN
R
R
3
5
33kΩ
1
1/2
OP-297
3
50kΩ
2kΩ
R
4
+
4
50kΩ
–15V
V–
Figure 35. Square-Root Amplifier
In these circuits, IREF is a function of the negative power supply.
To maintain accuracy, the negative supply should be well regu-
lated. For applications where very high accuracy is required, a
voltage reference may be used to set IREF. An important consid-
eration for the squaring circuit is that a sufficiently large input
voltage can force the output beyond the operating range of the
output op amp. Resistor R4 can be changed to scale IREF, or R1,
and R2 can be varied to keep the output voltage within the
usable range.
OP297 SPICE MACRO-MODEL
Figures 36 and 37 show the node end net list for a SPICE
macro model of the OP297. The model is a simplified version of
the actual device and simulates important dc parameters such as
VOS, IOS, IB, AVO, CMR, VO and ISY. AC parameters such as
slew rate, gain and phase response and CMR change with fre-
quency are also simulated by the model.
The model uses typical parameters for the OP297. The poles
and zeros in the model were determined from the actual open
and closed-loop gain and phase response of the OP297. In this
way, the model presents an accurate ac representation of the
actual device. The model assumes an ambient temperature
of 25°C.
Unadjusted accuracy of the square-root circuit is better than
0.1% over an input voltage range of 100 mV to 10 V. For a
similar input voltage range, the accuracy of the squaring circuit
is better than 0.5%.
REV. D
–11–
8/21/97 4:00 PM
OP297
99
R
R
6
V
3
4
2
–
13
C
R
4
C
2
D
3
5
12
8
15
16
R
R
2
1
IN2
8
Q
Q
R
7
G
–IN
1
C
3
2
E
1
9
1
–
R
3
1
11
R
10
R
I
D
2
D
1
C
IN
OS
98
5
4
6
E
REF
D
4
R
–
2
R
IN1
+IN
14
– +
9
7
E
OS
V
I
3
1
–
50
C
6
C
7
R
11
R
13
22
17
R
15
R
10
G
3
R
12
R
14
G
C
8
C
5
E
2
E
3
2
–
–
98
99
D
7
D
8
G
R
18
R
16
6
I
SY
D
5
V
4
26
27
+
–
22
25
L
1
23
D
6
V
5
–
+
28
29
R
19
R
17
G
G
G
5
D
9
D
7
4
10
50
Figure 36. OP297 Macro-Model
–12–
REV. D
8/21/97 4:00 PM
OP297
Table I. SPICE Net-List
• POLE AT 1.8 MHz
OP297 SPICE MACRO-MODEL
•
• NODE ASSIGNMENTS
•
R10
C5
G2
•
17 98 1E6
17 98 88 4E-15
98 17 16 23 1 E-6
•NONINVERTING INPUT
INVERTING INPUT
OUTPUT
• COMMON-MODE GAIN NETWORK WITH ZERO AT 50 HZ
•
POSITIVE SUPPLY
NEGATIVE SUPPLY
R11
C6
R12
E2
•
18 19 1E6
18 19 3.183E-9
•
•
SUBCKT OP297 1 2 30 99 50
19 98
1
INPUT STAGE & POLE AT 6 MHz
•
18 98 3 23 100E-3
RIN1
RIN2
R1
R2
R3
1
2
8
7
5
6
7
8
3
3
2500
2500
5E11
5E11
• POLE AT 6 MHz
•
R15
C8
G3
•
22 98 1E6
22 98 26.53E-15
98 22 17 23 1 E-6
99 612
99 612
R4
CIN
C2
7
5
8
6
3E-12
21.67E-12
• OUTPUT STAGE
•
I1
4
7
9
5
50 0.1E-3
R16
R17
ISY
R18
R19
L1
G4
G5
G6
G7
V4
23 99 160K
23 50 160K
99 50 331 E-6
25 99 200
IOS
EOS
Q1
Q2
R5
8
7
8
9
4
4
9
8
20E-12
POLY(1) 19 23 25E-6
10 QX
11 QX
96
1
6
25 50 200
10
11
8
25 30 1 E-7
28 50 22 25 5E-3
29 50 25 22 5E-3
25 99 99 22 5E-3
50 25 22 50 5E-3
26 25 1.8
R6
96
DX
DX
D1
D2
•
EREF 98
•
9
0
23
0
1
V5
25 27 1.3
GAIN STAGE & DOMINANT POLE AT 0.13 HZ
•
D5
D6
D7
D8
D9
D10
•
22 26 DX
27 22 DX
99 28 DX
99 29 DX
50 28 DY
50 29 DY
R7
C3
G1
12 98 2.45E9
12 98 500E-12
98 12 5 6 1.634E-3
V2
V3
D3
D4
•
99 13 1.5
14 50 1.5
12 13 DX
14 12 DX
• MODELS USED
•
• MODEL QX NPN BF=2.5E6)
• MODEL DX D IS = 1 E-15)
• MODEL DY D IS = 1 E-15 BV = 50)
• ENDS OP297
• NEGATIVE ZERO AT -1 8 MHz
•
R8
C4
R9
E1
•
15 16 1E6
15 16 –88.4E-15
16 98
1
15 98 12 23 1E6
REV. D
–13–
8/21/97 4:00 PM
OP297
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
4
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.008 (0.204)
8-Lead Cerdip
(Q-8)
0.055 (1.4)
MAX
0.005 (0.13)
MIN
8
5
0.310 (7.87)
0.220 (5.59)
1
4
PIN 1
0.320 (8.13)
0.290 (7.37)
0.405 (10.29)
MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
0.070 (1.78)
0.023 (0.58)
0.100
(2.54)
BSC
15°
0°
PLANE
0.014 (0.36)
0.030 (0.76)
8-Lead Narrow Body (SOIC)
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
–14–
REV. D
–15–
8/21/97 4:00 PM
OP297
–16–
REV. D
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