OP77AZMDA [ADI]
Next Generation OP07 Ultralow Offset Voltage Operational Amplifier; 下一代OP07超低失调电压运算放大器
| 型号： | OP77AZMDA |
| 厂家： | 
ADI |
| 描述： | Next Generation OP07 Ultralow Offset Voltage Operational Amplifier |
| 文件： | 总16页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Next Generation OP07
aUltralow Offset Voltage Operational Amplifier
OP77
FEATURES
P IN CO NNECTIO NS
Outstanding Gain Linearity
Ultrahigh Gain 5000 V/mV Min
Low VOS Over Temperature 60 V Max
Excellent TCVos 0.3 V/؇C Max
High PSRR 3 V/V Max
Low Power Consumption 60 mW Max
Fits OP07, 725,108A/308A, 741 Sockets
Available in Die Form
Epoxy Mini-D ip (P -Suffix)
8-P in H er m etic D IP
1
2
3
4
8
7
6
5
V
TRIM
V
TRIM
–IN
+IN
V–
OS
OS
OP07
V+
OUT
NC
NC = NO CONNECT
TO -99
(J-Suffix)
GENERAL D ESCRIP TIO N
The OP77 significantly advances the state-of-the-art in precision
op amps. T he OP77’s outstanding gain of 10,000,000 or more
is maintained over the full 10 V output range. T his exceptional
gain-linearity eliminates incorrectable system nonlinearities
common in previous monolithic op amps, and provides superior
performance in high closed-loop gain applications. Low initial
VOS drift and rapid stabilization time, combined with only 50
mW power consumption, are significant improvements over
previous designs. T hese characteristics, plus the exceptional
T CVOS of 0.3 mV/∞C maximum and the low VOS of 25 mV maxi-
mum, eliminates the need for VOS adjustment and increases
system accuracy over temperature.
V
TRIM
OS
V+
V
TRIM 1
OS
OP07
OUT
–IN 2
NC
+IN 3
4V– (CASE)
NC = NO CONNECT
PSRR of 3 mV/V (110 dB) and CMRR of 1.0 mV/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode signals. T his combination of outstanding char-
acteristics makes the OP77 ideally suited for high-resolution
instrumentation and other tight error budget systems.
V+
7
R2A
R1A
R2B
R1B
(OPTIONAL
NULL)
1
R7
NOTE:
C1
R2A AND R2B ARE
ELECTRONICALLY
ADJUSTED ON CHIP
AT FACTORY.
8
Q19
Q10
Q9
Q11
R9
R10
Q20
Q12
C2
OUTPUT
6
Q7
Q8
Q6
Q4
Q5
Q3
Q17
Q16
C3
R5
Q27
Q26
Q25
NON-
INVERTING
3
R3
Q1
INPUT
Q21
Q22
Q23
Q24
Q15
R6
2
R4
INVERTING
INPUT
Q2
Q18
R8
Q14
Q13
4
V–
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
OP77–SPECIFICATIONS
(@ V = ؎15 V, T = 25؇C, unless otherwise noted.)
ELECTRICAL SPECIFICATIONS
s
A
O P 77A
Typ
P ar am eter
Sym bol
Conditions
Min
Max
Unit
INPUT OFFSET VOLT AGE
LONG-T ERM INPUT OFFSET
VOLT AGE ST ABILIT Y1
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
INPUT NOISE VOLT AGE2
VOS
10
25
mV
DVOS/T ime
0.2
mV/Mo
nA
IOS
IB
0.3
–0.2
1.2
2.0
0.6
nA
enp-p
0.1 Hz to 10 Hz
0.35
mV p-p
nV/÷Hz
INPUT NOISE VOLT AGE DENSIT Y2 en
fO = 10 Hz
fO = 100 Hz
fO = 1000 Hz
10.3
10.0
9.6
18.0
13.0
11.0
INPUT NOISE CURRENT2
inp-p
0.1 Hz to10 Hz
14
30
pA p-p
INPUT NOISE CURRENT DENSIT Y2 in
fO = 10 Hz
fO = 100 Hz
fO = 1000 Hz
0.32
0.14
0.12
0.80
0.23
0.17
pA/÷Hz
INPUT RESIST ANCE
Differential Mode3
Common Mode
RIN
RINCM
26
45
200
MV
GV
INPUT VOLT AGE RANGE
IVR
±13
±14
V
COMMON-MODE
REJECT ION RAT IO
CMRR
PSRR
VCM = ±13 V
0.1
1.0
3
mV/V
mV/V
POWER SUPPLY
REJECT ION RAT IO
VS = ±3 V to ±18 V
0.7
LARGE-SIGNAL
VOLT AGE GAIN
AVO
VO
RL ≥ 2 kW ≥ VO = ±10V
5000
12000
V/mV
V
OUT PUT VOLT AGE SWING
RL ≥ 10 kW
RL ≥ 2 kW
RL ≥ 1 kW
±13.5
±12.5
±12.0
±14.0
±13.0
±12.5
SLEW RAT E2
CLOSED-LOOP BANDWIDT H2
SR
RL ≥ 2 kW
0.1
0.4
0.3
0.6
60
V/ms
MHz
W
BW
AVCL = +1
OPEN-LOOP OUT PUT RESIST ANCE RO
POWER CONSUMPT ION
Pd
VS = ±15 V, No Load
VS = ±3 V, No Load
50
3.5
60
4.5
mW
OFFSET ADJUST MENT RANGE
RP = 20 kW
±3
mV
NOT ES
1Long-T erm Input Offset Voltage Stability refers to the averaged trend line of VOS vs. T ime over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 mV.
2Sample tested.
3Guaranteed by design.
–2–
REV. C
OP77
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = ؎15 V, –55؇C £ T £ 125؇C, unless otherwise noted.)
s
A
O P 77A
Typ
P ar am eter
Sym bol
Conditions
Min
Max
Unit
INPUT OFFSET VOLT AGE
VOS
25
60
mV
AVERAGE INPUT OFFSET
VOLT AGE DRIFT1
T CVOS
IOS
0.1
0.5
0.3
2.2
mV/∞C
INPUT OFFSET CURRENT
nA
AVERAGE INPUT OFFSET
CURRENT DRIFT2
T CIOS
IB
1.5
2.4
25
4
pA/∞C
INPUT BIAS CURRENT
–0.2
nA
AVERAGE INPUT BIAS
CURRENT DRIFT2
T CIB
IVR
8
25
pA/∞C
INPUT VOLT AGE RANGE
±13
±13.5
0.6
V
COMMON-MODE
REJECT ION RAT IO
CMRR
PSRR
VCM = ±13 V
0.1
1
1.0
3
mV/V
mV/V
POWER SUPPLY
REJECT ION RAT IO
VS = ±3 V to ±18 V
LARGE-SIGNAL
VOLT AGE GAIN
AVO
VO
Pd
RL ≥ 2 kW ≥ VO = ±10 V
RL ≥ 10 kW
2000
6000
±13.0
60
V/mV
V
OUT PUT VOLT AGE SWING
POWER CONSUMPT ION
±12
VS = ±15 V, No Load
75
mW
NOT ES
1OP77A: T CVCS is 100% tested.
2Guaranteed by design.
–3–
REV. C
OP77–SPECIFICATIONS
(@ V = ؎15 V, T = 125؇C, unless otherwise noted.)
s
A
ELECTRICAL CHARACTERISTICS
O P 77E
Typ
O P 77F
Typ
P ar am eter
Sym bol
Conditions
Min
Max
Min
Max
Unit
INPUT OFFSET VOLT AGE
VOS
10
25
20
60
mV
LONG-T ERM
ST ABILIT Y1
VOS/T ime
IOS
0.3
0.3
1.2
0.35
0.4
0.3
1.2
mV/Mo
nA
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
INPUT NOISE VOLT AGE2
1.5
2.0
0.6
2.8
2.8
IB
–0.2
–0.2
nA
enp-p
0.1 Hz to 10 Hz
0.38 0.65
mVp-p
INPUT NOISE
VOLT AGE DENSIT Y
en
fO = 10 Hz
10.3 18.0
10.0 13.0
10.5 20.0
10.2 13.5
nV/÷Hz
fO = 100 Hz2
fO = 1000 Hz
9.6
11.0
9.8
11.5
INPUT NOISE CURRENT2
inp-p
in
0.1 Hz to 10 Hz
14
30
15
35
pAp-p
INPUT NOISE
CURRENT DENSIT Y
fO = 10 Hz
0.32 0.80
0.14 0.23
0.12 0.17
0.35 0.90
0.15 0.27
0.13 0.18
pA÷Hz
fO = 100 Hz2
fO = 1000 Hz
INPUT RESIST ANCE
Differential Mode3
Common Mode
RIN
RINCM
26
45
200
18.5 45
200
MW
GW
INPUT RESIST ANCE
Common Mode
RINCM
IVR
200
200
GW
INPUT VOLT AGE RANGE
Ϯ13 Ϯ14
Ϯ13 Ϯ14
V
COMMON-MODE
REJECT ION RAT IO
CMRR
PSRR
AVO
VCM = Ϯ13 V
VS = 3 V to 18 V
RL ≥ 2 k⍀
0.1
1.0
3.0
0.1
0.7
1.6
3.0
mV/V
mV/V
V/mV
V
POWER SUPPLY
REJECT ION RAT IO
0.7
LARGE-SIGNAL
VOLT AGE GAIN
5000 12000
2000 6000
OUT PUT VOLT AGE
SWING
VO
RL ≥ 10 k⍀
RL ≥ 2 k⍀
RL ≥ 1 k⍀
Ϯ13.5 Ϯ14.0
Ϯ12.5 Ϯ13.0
Ϯ12.0 Ϯ12.5
Ϯ13.5 Ϯ14.0
Ϯ12.5 Ϯ13.0
Ϯ12.0 Ϯ12.5
SLEW RAT E2
SR
RL ≥ 2 k⍀
0.1
0.3
0.6
60
0.1
0.3
0.6
60
V/ms
MHz
W
CLOSED-LOOP
BANDWIDT H2
BW
AVCL 1
0.4
0.4
OPEN-LOOP OUT PUT
RESIST ANCE
RO
Pd
POWER CONSUMPT ION
VS = Ϯ15 V, No Load
VS = Ϯ3 V, No Load
50
3.5
60
4.5
50
3.5
60
4.5
mW
mV
OFFSET ADJUST MENT
RANGE
Rp = 20 kn
Ϯ3
Ϯ3
NOT ES
1Long-T erm Input Offset Voltage Stability refers to the averaged trend line of VOS vs. T ime over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 mV.
2Sample tested.
3Guaranteed by design.
–4–
REV. C
OP77
SPECIFICATIONS
(@ V = ؎15 V, –25؇C £ T £ +85؇C for OP77E/FJ and OP77E/FZ, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
s
A
O P 77E
Typ
O P 77F
Typ
P ar am eter
Sym bol
Conditions
Min
Max
Min
Max
Unit
INPUT OFFSET VOLT AGE
V
J. Z Packages
10
10
45
55
20
20
100
100
mV
AVERAGE INPUT OFFSET
VOLT AGE DRIFT1
T VCOS
IOS
J. Z Packages
0.1
0 3
0.3
0.6
0.2
0.4
0.6
1.0
mV/∞C
INPUT OFFSET CURRENT
0.5
2.2
0.5
4.5
nA
AVERAGE INPUT OFFSET
CURRENT DRIFT2
T CIOS
IB
1.5
2.4
4.0
4.0
1.5
2.4
85
pA/ЊC
INPUT BIAS CURRENT
E, F
-0.2
-0.2
6.0
nA
AVERAGE INPUT BIAS
CURRENT DRIFT2
T CIB
IVR
8
40
15
60
pA/∞C
INPUT VOLT AGE RANGE
Ϯ13.0 Ϯ13.5
Ϯ13.0 Ϯ13.5
V
COMMON-MODE
REJECT ION RAT IO
CMRR
PSRR
AVO
VCM = Ϯ13 V
0.1
1.0
3.0
0.1
3.0
5.0
pVlV
mV/V
V/mV
POWER SUPPLY
REJECT ION RAT IO
VS = Ϯ3 V to Ϯ18 V
1.0
1.0
LARGE-SIGNAL
VOLT AGE GAIN
RL ≥ 2 kW
VO = Ϯ10 V
2000 6000
1000 4000
OUT PUT VOLT AGE SWING
POWER CONSUMPT ION
NOT ES
VO
Pd
RL ≥ 2 kW
Ϯ12 Ϯ13.0
Ϯ12 Ϯ13.0
V
VS = Ϯ15 V, No Load
60
75
60
75
mW
1OP77E: T CVOS is 100% tested on J and Z packages.
2Guaranteed by end-point limits.
–5–
REV. C
OP77–SPECIFICATIONS
(@ V = ؎15 V, T = 25؇C, for OP77N devices, unless otherwise noted.)
WAFER TEST LIMITS
s
A
O P 77N
Lim it
P ar am eter
Sym bol
Conditions
Unit
INPUT OFFSET VOLT AGE
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
VOS
IOS
IB
40
mV Max
nA Max
nA Max
2.0
±2
INPUT RESIST ANCE
Differential Mode
RIN
26
±13
1
MW Min
V Min
INPUT VOLT AGE RANGE
IVR
COMMON-MODE REJECT ION RAT IO
POWER SUPPLY REJECT ION RAT IO
OUT PUT VOLT AGE SWING
CMRR
PSRR
VO
VCM = ±13 V
mV/V Max
mV/VMax
V Min
VS = ±3 V to ±18 V
3
RL = 10 kW
RL = 2 kW
RL = 1 kW
±13.5
±12.5
±12.0
LARGE-SIGNAL VOLT AGE GAIN
AVO
RL = 2 kW
VO = ±10 V
2000
V/mV Min
DIFFERENT IAL INPUT VOLT AGE
POWER CONSUMPT ION
±30
V Max
Pd
VOUT = 0 V
60
mW Max
NOT ES
1Guaranteed by design.
2Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
(@ V = ؎15 V, T = 25؇C, unless otherwise noted.)
TYPICAL ELECTRICAL CHARACTERISTICS
s
A
O P 77N
Lim it
P ar am eter
Sym bol
Conditions
Unit
AVERAGE INPUT OFFSET VOLT AGE DRIFT
NULLED INPUT OFFSET VOLT AGE DRIFT
AVERAGE INPUT OFFSET CURRENT DRIFT
SLEW RAT E
T CVOS
T CVOSn
T CIOS
SR
RS = 50 W
0.1
0.1
0.5
0.3
0.6
mV/OC
mV/∞C
pA/∞C
V/ms
RS = 50 W, RP = 20 kW
RL ≥ 2 kW
BANDWIDT H
BW
AVCL + 1
MHz
–6–
REV. C
OP77
ABSO LUTE MAXIMUM RATINGS1
BO ND ING D IAGRAM
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage T emperature Range
1. BALANCE
2. INVERTING INPUT
3. NONINVERTING INPUT
4. V-
6. OUTPUT
7. V+
J and Z Packages . . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Operating T emperature Range
8. BALANCE
OP77A . . . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C
OP77E, OPP77F (J, Z) . . . . . . . . . . . . . . . . –25∞C to +85∞C
Junction T emperature (Tj) . . . . . . . . . . . . . –65∞C to +150∞C
Lead T emperature (Soldering, 60 sec.) . . . . . . . . . . . . . 300∞C
NOT ES
DIE SIZE 0.093
؋
0.057 inch, 5301 sq. mm (2.36
؋
1.45 mm, 3.42 sq. mm) 1Absolute Maximum Ratings apply to both DICE and packaged parts, unless
otherwise noted.
2For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
O RD ERING GUID E
P ackage O ptions
CERD IP *
O perating
Tem perature
ء
P ackage Type
jA
jC
Unit
T O-99 (J)
8-Lead Hermetic DIP (Z)
150
148
18
16
∞C/W
∞C/W
TO -99
8-Lead
Range
OP77AZ
OP77EZ
OP77FZ
MIL
IND
IND
NOT E
OP77EJ
OP77FJ
ء
jA is specified for worst-case mounting conditions, i.e., is specified for
jA
device in socket for T O, CERDIP, P-DIP, and PLCC packages; is specified
for device soldered to printed circuit board for SO package.
jA
ء
Not for new designs; obsolete April 2002. For Military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at
www.dscc.dla.mil/programs/milspec/default.asp
SMD P art Num ber
AD I Equivalent
5962-87738012A
5962-8773802GA
5962-8773802PA
OP77BRCMDA
OP77AJMDA
OP77AZMDA
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP77 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. T herefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–7–
–Typical Performance Characteristics
OP77
2
16
12
8
25
V
= ؎15V
= 25؇C
= 10k⍀
V
= ؎15V
S
S
T
= 25؇C
= 2k⍀
A
T
A
R
20
15
L
1
0
R
L
10
5
–1
4
–2
–10
0
0
–5
0
5
10
0
؎5
؎10
؎15
؎20
–15
–55 –35
5
25 45 65 85 105 125
OUTPUT VOLTAGE – V
POWER SUPPLY VOLTAGE – V
TEMPERATURE – ؇C
TPC 1. Gain Linearity (Input
Voltage vs. Output Voltage)
TPC 3. Open-Loop Gain vs.
Power Supply Voltage
TPC 2. Open-Loop Gain vs.
Temperature
30
20
4
3
2
1
30
25
20
15
10
5
J, Z PACKAGES
+0.3V/؇C
V
= ؎15V
V
= ؎15V
= 25؇C
S
S
T
A
DEVICE IMMERSED IN
70؇C OIL BATH (20 UNITS)
MEAN
S.D.
10
0
0
–1
–2
–3
–4
–10
MAX
–20
–30
AVE
MIN
–0.3V/؇C
0
0
10
20
30 40
50 60 70
–55 –35 –15
5
25 45 65 85 105 125
0
0.5
1
1.5
2
2.5
3
3.5
TIME – SEC
TEMPERATURE – ؇C
TIME AFTER POWER SUPPLY TURN-ON – MINUTES
TPC 6. Offset Voltage Change
Due to Thermal Shock
TPC 4. Untrimmed Offset
Voltage vs. Temperature
TPC 5. Warm-Up Drift
0
100
80
160
140
120
100
80
150
V
= ؎15V
= 25؇C
S
T
= 25؇C
V
= ؎15V
= 25؇C
A
S
T
A
140
130
120
110
100
90
T
A
45
60
40
20
0
90
60
135
40
20
180
–20
0
80
10
100
1k
10k
10k
1M
10M
0.01 0.1
1
10 100 1k 10k 100k 1M
FREQUENCY – Hz
1
10
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 7. Closed-Loop Response for
Various Gain Configurations
TPC 8. Open-Loop Gain/Phase
Response
TPC 9. CMRR vs. Frequency
–8–
REV. C
OP77
130
120
110
100
90
4
3
2
1
0
2.0
1.5
1.0
0.5
0
V
= ؎15V
V = ؎15V
S
S
T
= 25؇C
A
80
70
60
–50
0
50
100
–50
0
50
100
0.1
1.0
10
100
1k
10k
TEMPERATURE – ؇C
TEMPERATURE – ؇C
FREQUENCY – Hz
TPC 10. PSRR vs. Frequency
TPC 11. Input Bias Current
vs. Temperature
TPC 12. Input Offset Current
vs. Temperature
10
1.0
0.1
1000
100
10
32
28
24
20
16
12
8
RS1 = RS2 = 200kV
THERMAL NOISE OF SOURCE
RESISTORS INCLUDED
V
= ؎15V
= 25؇C
S
V
= ؎15V
= 25؇C
S
T
A
T
A
EXCLUDED
R
= 0
S
V
= ؎15V
= 25؇C
4
S
T
A
1
0
1k
100
1k
10k
100k
1
10
100
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 13. Input Wideband Noise vs.
Bandwidth (0.1 Hz to Frequency
Indicated)
TPC 14. Total Input Noise
Voltage vs. Frequency
TPC 15. Maximum Output Swing
vs. Frequency
100
20
15
10
40
V
= ؎15V
= 25؇C
T
= 25؇C
S
A
V
= ؎15V
= 25؇C
S
T
A
T
A
35
30
25
20
V
= ؎10mV
IN
POSITIVE SWING
NEGATIVE SWING
10
5
0
0
15
0
10
20
30
40
0
1
2
3
4
100
1k
LOAD RESISTANCE TO GROUND – ⍀
10k
TOTAL SUPPLY VOLTAGE, V+ TO V – V
TIME FROM OUTPUT BEING SHORTED –
MINUTES
TPC 16. Power Consumption vs.
Power Supply
TPC 17. Maximum Output Voltage
vs. Load Resistance
TPC 18. Output Short-Circuit
Current vs. Time
–9–
REV. C
OP77
200k⍀
TYPICAL
PRECISION OP AMP
50⍀
10k⍀
100k⍀
V
OP77
O
V
Y
1M⍀
10⍀
V
O
V
= 10V
V
=
IN
OS
V
X
4000
V
X
–10V
0V
+10V
Figure 1. Typical Offset Voltage Test Circuit
R
L
2.5M⍀
~
A
R
650V/mV
VO
= 2k⍀
V+
L
NOTES
1. GAIN NOT CONSTANT. CAUSES NONLINEAR ERRORS.
2. A SPEC IS ONLY PART OF THE SOLUTION.
100⍀
100⍀
2
3
7
3.3k⍀
6
OUTPUT
4.7F
10Hz FILTER)
OP77
VO
4
3. CHECK THE OP AMP PERFORMANCE, ESPECIALLY AT TEMPERATURES.
(
V–
Figure 5. Open-Loop Gain Linearity
V
O
=
INPUT REFERRED NOISE
25,000
Actual open-loop voltage gain can vary greatly at various output
voltages. All automated testers use endpoint testing and therefore
only show the average gain. T his causes errors in high closed-
loop gain circuits. Since this is so difficult for manufacturers to
test, users should make their own evaluation. T his simple test
circuit makes it easy. An ideal op amp would show a horizontal
scope trace.
Figure 2. Typical Low-Frequency Noise Test Circuit
20k⍀
V+
1
–
8
OP77
4
2
3
7
6
OUTPUT
INPUT
+
V–
Figure 3. Optional Offset Nulling Circuit
V
Y
100k⍀
+18V
+
*
10F
10⍀
0V
–10V
+10V
V
X
0.1F
2
7
OP77
3
6
4
10k⍀ 10k⍀
10⍀
0.1F
*
10F
+
–18V
*
1 PER BOARD
Figure 4. Burn-In Circuit
Figure 6. Output Gain Linearity Trace
T his is the output gain linearity trace for the new OP77. T he
output trace is virtually horizontal at all points, assuring extremely
high gain accuracy. T he average open-loop gain is truly impres-
sive—approximately 10,000,000.
–10–
REV. C
OP77
AP P LICATIO NS INFO RMATIO N
Bilater al Cur r ent Sour ce
R3
R2
1M⍀
1k⍀
+15V
0.1F
R1
2
V
IN
100k⍀
6
I
< 15mA
OP77
OUT
R2
3
R1
2
3
7
100k⍀
R5
10⍀
1k⍀
6
OP77E
4
R3
R4
1k⍀
0.1F
990⍀
R4
1M⍀
Figure 9. Basic Current Source
–15V
R3
+15V
Figure 7. Precision High-Gain Differential Amplifier
R1
2
3
2N2222
2N2907
V
IN
6
OP77
T he high gain, gain linearity, CMRR, and low T CVos of the
OP77 make it possible to obtain performance not previously
available in single-stage very high-gain amplifier applications.
R2
R5
–15V
R4
I
< 100mA
OUT
R1
R2
R3
R4
For best CMR,
must equal
. In this example,
R3
R1 – R5
I
= V
IN
(
)
OUT
GIVEN R3 = R4 ؉ R5, R1 = R2
with a 10 mV differential signal, the maximum errors are as listed
in T able I.
Figure 10. 100 mA Current Source
T hese current sources will supply both positive and negative
current into a grounded load.
Table I. Maxim um Errors
TYP E
AMO UNT
Ê R4
ˆ
R5
+ 1
Á
˜
COMMON-MODE VOLT AGE
GAIN LINEARIT Y, WORST CASE
T CVOS
0.01%/V
0.02%
0.003%/∞C
0.008%/∞C
Ë
¯
R2
Note that ZO
=
R5 + R4
R3
R1
R2
T CI OS
and that for ZO to be infinite,
R
F
10pF
+15V
0.1F
R
S
2
7
4
INPUT
100⍀
6
OUTPUT
OP77
3
C
LOAD
0.1F
–15V
Figure 8. Isolating Large Capacitive Loads
T his circuit reduces maximum slew-rate but allows driving
capacitive loads of any size without instability. Because the boon
resistor is inside the feedback loop, its effect on output imped-
ance is reduced to insignificance by the high open-loop gain
of the OP77.
REV. C
–11–
OP77
In these circuits, OP77’s high gain, high CMRR, and low TCVOS
ensure high accuracy.
R5 + R4
R2
R3
R1
must =
R1
P r ecision Cur r ent Sinks
1.8k⍀
2mA
V+
15V
R
L
3
2
7
I
V
IN
O
=
I
6
O
R1
E
= 10V
1.6
OP77
O
V
IN
V
> OV
IN
200⍀
4
R2
3.6k⍀
OP77
IRF520
D1
1N4579A
6.4V ؎5%
؎5ppm/؇C
FULL SCALE OF 1V,
=
I
1A/V
O
A
VCL
R3
6.4k⍀
R1
1⍀
1W
Figure 13. High Stability Voltage Reference
Figure 11. Positive Current Sink
This simple bootstrapped voltage reference provides a precise 10 V
virtually independent of changes in power supply voltage, ambi-
ent temperature and output loading. Correct Zener operating
current of exactly 2 mA is maintained by R1, a selected 5 ppm/∞C
resistor, connected to the regulated output. Accuracy is prima-
rily determined by three factors: the 5 ppm/∞C temperature
coefficient of D1, 1 ppm/∞C ratio tracking of R2 and R3, and
operational amplifier VOS errors.
R1
200⍀
IRF520
OP77
V
IN
V
I
IN
O
=
I
O
R1
> OV
VOs errors, amplified by 1.6 (AVCL), appear at the output and
can be significant with most monolithic amplifiers. For example,
an ordinary amplifier with TCVOS of 5 mV/∞C contributes 0.8 ppm/
∞C of output error while the OP77, with T CVOS of 0.3 mV/∞C,
contributes but 0.05 ppm/∞C of output error, thus effectively
eliminating T CVOS as an error consideration.
R
L
V
IN
V–
Figure 12. Positive Current Source
T he high gain and low T CVOS assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
These simple high-current sinks require the load to float between
the power supply and the sink.
1k⍀
1k⍀
+15V
+15V
0.1F
D1
1N4148
C1
30pF
0.1F
2
3
7
2
3
6
7
V
D2
OUT
OP77E
4
0 < V
< 10V
6
OUT
OP77E
4
2N4393
0.1F
V
IN
R3
2k⍀
0.1F
–15V
–15V
Figure 14. Precision Absolute Value Amplifier
T he high gain and low T CVOS assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
appears as a common-mode signal to the op amps. T he OP77E
CMRR of 1 V/V assures errors of less than 2 ppm.
–12–
REV. C
OP77
15V
+
10F
2
2
2
REF-01
REF-01
REF-01
6
6
6
O
V
V
V
O
O
V
OP77
OUT
100⍀
4
4
4
100⍀
100⍀
0.1F
Figure 15. Low Noise Precision Reference
T his circuit relies upon OP77’s low T CVOS and noise combined
with very high CMRR to provide precision buffering of the
averaged REF01 voltage outputs.
CH must be of polystyrene, Teflon*, or polyethylene to minimize
dielectric absorption and leakage. T he droop rate is determined
by the size of CH and the bias current of the AD820.
*T eflon is a registered trademark of the Dupont Company
1k⍀
15V
0.1F
1N4148
15V
0.1F
2
3
7
6
2N930
2
3
OP77
4
7
AD820
4
1k⍀
V
IN
6
V
OUT
1k⍀
0.1F
0.1F
C
H
–15V
RESET
–15V
Figure 16. Precision Positive Peak Detector
REV. C
–13–
OP77
+15V
C
C
0.1F
R
F
100k⍀
2
+15V
0.1F
V
R
C
R
IN
A
6
5
V
O
TRIM
50k⍀
R
S
2
3
7
D1
1N4148
V
TH
REF-02
1k⍀
6
V
R
V
OUT
OP77
–15V
OP77
4
OUT
b1
1.5k⍀
3
R1
TEMP
GND
4
V
IN
0.1F
2k⍀
0.1F
R
bp
–15V
Figure 17. Precision Threshold Detector/Amplifier
Figure 18. Precision Temperature Sensor
Table II. Resistor Values
When VIN < VT H, amplifier output swings negative, reverse
biasing diode D1. VOUT = VT H if RL= • when VIN > VT H, the
loop closes,
T CVOUT SLOPE (S)
10 mV/∞C 100 mV/∞C 10 mV/∞F
T EMPERAT URE
RANGE
–55∞C to
+125∞C
–55∞C to
+125∞C
–67∞F to
+257∞C
Ê
Ë
RF ˆ
˜
VOUT =VTH + V – VTH 1 +
(
)
Á
IN
RS ¯
OUT PUT VOLT AGE –0.55 V to –5.5 V to
–0.67 V to
+2.57V
RANGE
+1.25 V
+12.5V
CC is selected to smooth the response of the loop.
ZERO-SCALE
Ra (±1% Resistor)
Rb1 (±1% Resistor)
Rbp (Potentiometer)
Rc (±1% Resistor)
0 V @ 0∞C 0 V @ 0∞C 0 V @ 0ЊF
9.09 kW
1.5 kW
200 W
15 kW
7.5 kW
1.21 kW
200 W
1.82 kW
500 W
5.11 kW
84.5 kW
8.25 kW
–14–
REV. C
OP77
OUTLINE DIMENSIONS
8-Lead Ceramic Dip – Glass Hermetic Seal [CERDIP]
8-Lead Metal Can [TO-99]
(Q-8)
(H-08)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
0.005 (0.13) 0.055 (1.40)
REFERENCE PLANE
MIN
MAX
0.5000 (12.70)
MIN
0.1850 (4.70)
0.1650 (4.19)
8
5
0.2500 (6.35) MIN
0.1000 (2.54) BSC
5
0.310 (7.87)
0.220 (5.59)
0.1600 (4.06)
0.1400 (3.56)
0.0500 (1.27) MAX
PIN 1
1
4
6
4
0.0450 (1.14)
0.0270 (0.69)
0.100 (2.54) BSC
0.405 (10.29) MAX
0.2000
(5.08)
BSC
0.320 (8.13)
0.290 (7.37)
3
7
0.060 (1.52)
0.015 (0.38)
2
8
0.200 (5.08)
MAX
1
0.1000
0.0190 (0.48)
0.0160 (0.41)
(2.54)
BSC
0.150 (3.81)
0.200 (5.08)
0.125 (3.18)
0.0340 (0.86)
0.0280 (0.71)
MIN
0.0400 (1.02) MAX
0.0210 (0.53)
0.0160 (0.41)
0.0400 (1.02)
0.0100 (0.25)
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
SEATING
PLANE
15
0
0.070 (1.78)
0.030 (0.76)
45 BSC
BASE & SEATING PLANE
CONTROLLING DIMENSIONS ARE IN INCH; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-002AK
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. C
–15–
Revision History
Location
P age
10/02—D ata Sheet changed fr om REV. B to REV. C.
Edits to SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2 Caption Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3 Caption Changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edits to Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Updated OUT LINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/02—D ata Sheet changed fr om REV. A to REV. B.
Remove 8-Lead SO PIN CONNECT ION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to ABSOLUT E MAXIMUM RAT INGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Remove OP77B column from SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Remove OP77B column from ELECT RICAL CHARACT ERIST ICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Remove OP77G column from WAFER T EST LIMIT S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Remove OP77G column from T YPICAL ELECT RICAL CHARACT ERIST ICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
–16–
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