REF196GS [ADI]
Precision Micropower, Low Dropout, Voltage References; 精密微功耗，低压差，电压基准
| 型号： | REF196GS |
| 厂家： | 
ADI |
| 描述： | Precision Micropower, Low Dropout, Voltage References |
| 文件： | 总23页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Micropower, Low Dropout,
Voltage References
a
REF19x Series
PIN CONFIGURATIONS
FEATURES
Initial Accuracy: ؎2 mV max
Temperature Coefficient: 5 ppm/°C max
Low Supply Current: 45 A max
Sleep Mode: 15 A max
8-Lead Narrow-Body SO and TSSOP
(S Suffix and RU Suffix)
NC
1
2
3
4
TP
8
7
6
5
Low Dropout Voltage
REF19x
SERIES
Load Regulation: 4 ppm/mA
Line Regulation: 4 ppm/V
High Output Current: 30 mA
Short Circuit Protection
NC
V
S
OUTPUT
TP
SLEEP
GND
TOP VIEW
(Not to Scale)
APPLICATIONS
Portable Instrumentation
A-to-D and D-to-A Converters
Smart Sensors
Solar Powered Applications
Loop Current Powered Instrumentations
8-Lead Epoxy DIP (P Suffix)
NC
1
2
TP
8
7
6
5
REF19x
SERIES
NC
V
S
TOP VIEW
(Not to Scale)
OUTPUT
TP
3
4
SLEEP
GND
GENERAL DESCRIPTION
REF19x series precision bandgap voltage references use a pat-
ented temperature drift curvature correction circuit and laser
trimming of highly stable thin film resistors to achieve a very low
temperature coefficient and a high initial accuracy.
NC = NO CONNECT
TP PINS ARE FACTORY TEST POINTS
NO USER CONNECTION
The REF19x series are micropower, Low Dropout Voltage
(LDV) devices providing a stable output voltage from supplies
as low as 100 mV above the output voltage and consuming less
than 45 µA of supply current. In sleep mode, which is enabled
by applying a low TTL or CMOS level to the sleep pin, the
output is turned off and supply current is further reduced to less
than 15 µA.
Table I
Part Number
Nominal Output Voltage (V)
REF191
REF192
REF193
REF194
REF195
REF196
REF198
2.048
2.50
3.00
4.50
5.00
3.30
4.096
The REF19x series references are specified over the extended
industrial temperature range (–40°C to +85°C) with typical
performance specifications over –40°C to +125°C for applica-
tions such as automotive.
All electrical grades are available in 8-Lead SOIC; the PDIP and
TSSOP are only available in the lowest electrical grade. Prod-
ucts are also available in die form.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option1
Model
Test Pins (TP)
The test pins, Pin 1 and Pin 5, are reserved for in-package
zener-zap. To achieve the highest level of accuracy at the out-
put, the zener-zapping technique is used to trim the output
voltage. Since each unit may require a different amount of ad-
justment, the resistance value at the test pins will vary widely
from pin-to-pin as well as from part-to-part. The user should
not make any physical nor electrical connections to Pin 1 and
Pin 5.
REF19xGP
REF19xES3
REF19xFS3
REF19xGS
–40°C to +85°C 8-Lead Plastic DIP2 N-8
–40°C to +85°C 8-Lead SOIC
–40°C to +85°C 8-Lead SOIC
–40°C to +85°C 8-Lead SOIC
SO-8
SO-8
SO-8
RU-8
REF19xGRU –40°C to +85°C 8-Lead TSSOP
REF19xGBC +25°C
DICE
NOTES
1N = Plastic DIP, SO = Small Outline, RU = Thin Shrink Small Outline.
28-Lead plastic DIP only available in “G” grade.
3REF193 and REF196 are available in “G” grade only.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
REF19x Series
REF191–SPECIFICATIONS
(@ VS = 3.3 V, TA = +25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
INITIAL ACCURACY1
“E” Grade
“F” Grade
VO
IOUT = 0 mA
2.046
2.043
2.038
2.048
2.050
2.053
2.058
V
V
V
“G” Grade
LINE REGULATION2
“E” Grade
“F & G” Grades
LOAD REGULATION2
“E” Grade
∆VO/∆VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA
2
4
4
8
ppm/V
ppm/V
∆VO/∆VLOAD
4
6
10
15
ppm/mA
ppm/mA
“F & G” Grades
DROPOUT VOLTAGE
VS – VO
VS = 3.15 V, ILOAD = 2 mA
VS = 3.3 V, ILOAD = 10 mA
VS = 3.6 V, ILOAD = 30 mA
0.95
1.25
1.55
V
V
V
LONG-TERM STABILITY3
NOISE VOLTAGE
NOTES
∆VO
1000 Hours @ +125°C
1.2
20
mV
eN
0.1 Hz to 10 Hz
µV p-p
1Initial accuracy includes temperature hysteresis effect.
2Line and load regulation specifications include the effect of self-heating.
3Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, –40؇C ≤ TA ≤ +85؇C unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
LOAD REGULATION4
“E” Grade
“F & G” Grades
∆VO/∆VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA
5
10
10
20
ppm/V
ppm/V
∆VO/∆VLOAD
5
10
15
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.15 V, ILOAD = 2 mA
VS = 3.3 V, ILOAD = 10 mA
VS = 3.6 V, ILOAD = 25 mA
0.95
1.25
1.55
V
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
2.4
V
µA
V
–8
0.8
–8
µA
SUPPLY CURRENT
Sleep Mode
No Load
No Load
45
15
µA
µA
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. D
–2–
REF19x Series
REF191–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 3.3 V, –40؇C ≤ TA ≤ +125؇C unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
LOAD REGULATION4
“E” Grade
∆VO/∆VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA
10
20
ppm/V
ppm/V
∆VO/∆VLOAD
10
20
ppm/mA
ppm/mA
“F & G” Grades
DROPOUT VOLTAGE
VS – VO
VS = 3.3 V, ILOAD = 10 mA
VS = 3.6 V, ILOAD = 20 mA
1.25
1.55
V
V
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
–3–
REV. D
REF19x Series
REF192–SPECIFICATIONS
(@ V = 3.3 V, T = +25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
INITIAL ACCURACY1
“E” Grade
“F” Grade
VO
IOUT = 0 mA
2.498 2.500 2.502
V
V
V
2.495
2.490
2.505
2.510
“G” Grade
LINE REGULATION2
“E” Grade
“F & G” Grades
LOAD REGULATION2
“E” Grade
“F & G” Grades
∆VO/∆VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA
2
4
4
8
ppm/V
ppm/V
∆VO/∆VLOAD
4
6
10
15
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.5 V, ILOAD = 10 mA
VS = 3.9 V, ILOAD = 30 mA
1.00
1.40
V
V
LONG-TERM STABILITY3
NOISE VOLTAGE
NOTES
∆VO
1000 Hours @ +125°C
1.2
25
mV
eN
0.1 Hz to 10 Hz
µV p-p
1Initial accuracy includes temperature hysteresis effect.
2Line and load regulation specifications include the effect of self-heating.
3Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
(@ V = 3.3 V, T = –40؇C ≤ T ≤ +85؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA
5
10
10
20
ppm/V
ppm/V
LOAD REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VLOAD
5
10
15
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.5 V, ILOAD = 10 mA
VS = 4.0 V, ILOAD = 25 mA
1.00
1.50
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
2.4
V
µA
V
–8
0.8
–8
µA
SUPPLY CURRENT
Sleep Mode
No Load
No Load
45
15
µA
µA
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. D
–4–
REF19x Series
REF192–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, –40؇C ≤ TA ≤ +125؇C unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
LOAD REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VIN
3.0 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA
10
20
ppm/V
ppm/V
∆VO /∆VLOAD
10
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 3.5 V, ILOAD = 10 mA
VS = 4.0 V, ILOAD = 20 mA
1.00
1.50
V
V
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 3.3 V, TA = +25؇C unless otherwise noted)
Parameter
INITIAL ACCURACY1
“G” Grade
LINE REGULATION2
“G” Grades
LOAD REGULATION2
“G” Grade
Symbol
Condition
Min
Typ
3.0
4
Max
Units
V
VO
IOUT = 0 mA
2.990
3.010
8
∆
VO/
VO/
∆
VIN
3.3 V, ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA
ppm/V
ppm/mA
∆
∆VLOAD
6
15
DROPOUT VOLTAGE
VS – VO
VS = 3.8 V, ILOAD = 10 mA
VS = 4.0 V, ILOAD = 30 mA
0.80
1.00
V
V
LONG-TERM STABILITY 3
NOISE VOLTAGE
NOTES
∆
VO
1000 Hours @ +125°C
1.2
30
mV
eN
0.1 Hz to 10 Hz
µV p-p
1Initial accuracy includes temperature hysteresis effect.
2Line and load regulation specifications include the effect of self-heating.
3Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
REV. D
–5–
REF19x Series
REF193–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 3.3 V, TA = –40؇C ≤ TA ≤ +85؇C unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
25
Units
TEMPERATURE COEFFICIENT1, 2
“G” Grade3
TCVO/°C
∆VO/∆VIN
IOUT = 0 mA
10
ppm/°C
ppm/V
ppm/mA
LINE REGULATION4
“G” Grade
3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA
10
20
LOAD REGULATION4
“G” Grade
∆VO/∆VLOAD
10
20
DROPOUT VOLTAGE
VS – VO
VS = 3.8 V, ILOAD = 10 mA
VS = 4.1 V, ILOAD = 30 mA
0.80
1.10
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
2.4
V
µA
V
–8
0.8
–8
µA
SUPPLY CURRENT
Sleep Mode
No Load
No Load
45
15
µA
µA
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
(@ V = 3.3 V, –40؇C ≤ T ≤ +125؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“G” Grade3
TCVO/°C
∆VO /∆VIN
IOUT = 0 mA
10
ppm/°C
ppm/V
ppm/mA
LINE REGULATION4
“G” Grade
3.3 V ≤ VS ≤ 15 V, IOUT = 0 mA
20
LOAD REGULATION4
“G” Grade
∆VO /∆VLOAD
VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA
10
DROPOUT VOLTAGE
VS – VO
VS = 3.8 V, ILOAD = 10 mA
VS = 4.1 V, ILOAD = 20 mA
0.80
1.10
V
V
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. D
–6–
REF19x Series
REF194–SPECIFICATIONS
(@ V = 5.0 V, T = +25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
INITIAL ACCURACY1
“E” Grade
“F” Grade
VO
IOUT = 0 mA
4.498 4.5
4.495
4.490
4.502
4.505
4.510
V
V
V
“G” Grade
LINE REGULATION2
“E” Grade
“F & G” Grades
LOAD REGULATION2
“E” Grade
“F & G” Grades
∆VO /∆VIN
4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.8 V, 0 ≤ IOUT ≤ 30 mA
2
4
4
8
ppm/V
ppm/V
∆VO /∆VLOAD
2
4
4
8
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.00 V, ILOAD = 10 mA
VS = 5.8 V, ILOAD = 30 mA
0.50
1.30
V
V
LONG-TERM STABILITY3
NOISE VOLTAGE
NOTES
∆VO
1000 Hours @ +125°C
2
mV
eN
0.1 Hz to 10 Hz
45
µV p-p
1Initial accuracy includes temperature hysteresis effect.
2Line and load regulation specifications include the effect of self-heating.
3Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (@ VS = 5.0 V, TA = –40؇C ≤ TA ≤ +85؇C unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VIN
4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.80 V, 0 ≤ IOUT ≤ 25 mA
5
10
10
20
ppm/V
ppm/V
LOAD REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VLOAD
5
10
15
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.00 V, ILOAD = 10 mA
VS = 5.80 V, ILOAD = 25 mA
0.5
1.30
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
2.4
V
µA
V
–8
0.8
–8
µA
SUPPLY CURRENT
Sleep Mode
No Load
No Load
45
15
µA
µA
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. D
–7–
REF19x Series
REF194–SPECIFICATIONS
(@ V = 5.0 V, –40؇C ≤ T ≤ +125؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
LOAD REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VIN
4.75 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.80 V, 0 ≤ IOUT ≤ 20 mA
5
10
ppm/V
ppm/V
∆VO /∆VLOAD
5
10
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.10 V, ILOAD = 10 mA
VS = 5.95 V, ILOAD = 20 mA
0.60
1.45
V
V
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. D
–8–
REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 5.10 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
INITIAL ACCURACY1
“E” Grade
VO
IOUT = 0 mA
4.998
4.995
4.990
5.0
5.002
5.005
5.010
V
V
V
“F” Grade
“G” Grade
LINE REGULATION2
“E” Grade
“F & G” Grades
LOAD REGULATION2
“E” Grade
∆VO/∆VIN
5.10 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 6.30 V, 0 ≤ IOUT ≤ 30 mA
2
4
4
8
ppm/V
ppm/V
∆VO /∆VLOAD
2
4
4
8
ppm/mA
ppm/mA
“F & G” Grades
DROPOUT VOLTAGE
VS – VO
VS = 5.50 V, ILOAD = 10 mA
VS = 6.30 V, ILOAD = 30 mA
0.50
1.30
V
V
LONG-TERM STABILITY3
NOISE VOLTAGE
NOTES
∆VO
1000 Hours @ +125°C
1.2
50
mV
eN
0.1 Hz to 10 Hz
µV p-p
1Initial accuracy includes temperature hysteresis effect.
2Line and load regulation specifications include the effect of self-heating.
3Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
(@ VS = 5.15 V, TA = –40؇C ≤ TA ≤ +85؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VIN
5.15 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 6.30 V, 0 ≤ IOUT ≤ 25 mA
5
10
10
20
ppm/V
ppm/V
LOAD REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VLOAD
5
10
10
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.50 V, ILOAD = 10 mA
VS = 6.30 V, ILOAD = 25 mA
0.50
1.30
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
2.4
V
µA
V
–8
0.8
–8
µA
SUPPLY CURRENT
Sleep Mode
No Load
No Load
45
15
µA
µA
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
.
REV. D
–9–
REF19x Series
REF195–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = +5.20 V, –40؇C ≤ TA ≤ +125؇C unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
LOAD REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VIN
5.20 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 6.45 V, 0 ≤ IOUT ≤ 20 mA
5
10
ppm/V
ppm/V
∆VO /∆VLOAD
5
10
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 5.60 V, ILOAD = 10 mA
VS = 6.45 V, ILOAD = 20 mA
0.60
1.45
V
V
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REF196–SPECIFICATIONS
(@ V = +3.5 V, T = +25؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
V
INITIAL ACCURACY1
“G” Grade
VO
IOUT = 0 mA
3.290 3.3
3.310
8
LINE REGULATION2
“G” Grades
LOAD REGULATION2
“G” Grade
∆VO /∆VIN
3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 30 mA
4
6
ppm/V
ppm/mA
∆VO /∆VLOAD
15
DROPOUT VOLTAGE
VS – VO
VS = 4.1 V, ILOAD = 10 mA
VS = 4.3 V, ILOAD = 30 mA
0.80
1.00
V
V
LONG-TERM STABILITY3
NOISE VOLTAGE
NOTES
∆VO
1000 Hours @ +125°C
1.2
33
mV
eN
0.1 Hz to 10 Hz
µV p-p
1Initial accuracy includes temperature hysteresis effect.
2Line and load regulation specifications include the effect of self-heating.
3Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
REV. D
–10–
REF19x Series
REF196–SPECIFICATIONS
(@ VS = +3.5 V, TA = –40؇C ≤ TA ≤ +85؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
25
Units
TEMPERATURE COEFFICIENT1, 2
“G” Grade3
TCVO/°C
∆VO/∆VIN
IOUT = 0 mA
10
ppm/°C
ppm/V
ppm/mA
LINE REGULATION4
“G” Grade
LOAD REGULATION4
“G” Grade
3.5 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.0 V, 0 ≤ IOUT ≤ 25 mA
10
20
∆VO/∆VLOAD
10
20
DROPOUT VOLTAGE
VS – VO
VS = 4.1 V, ILOAD = 10 mA
VS = 4.3 V, ILOAD = 25 mA
0.80
1.00
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
2.4
V
µA
V
–8
0.8
–8
µA
SUPPLY CURRENT
Sleep Mode
No Load
No Load
45
15
µA
µA
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
(@ VS = +3.50 V, –40؇C ≤ TA ≤ +125؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“G” Grade3
TCVO/°C
∆VO /∆VIN
IOUT = 0 mA
10
ppm/°C
ppm/V
ppm/mA
LINE REGULATION4
“G” Grade
3.50 V ≤ VS ≤ 15 V, IOUT = 0 mA
20
LOAD REGULATION4
“G” Grade
∆VO /∆VLOAD
VS = 5.0 V, 0 ≤ IOUT ≤ 20 mA
20
DROPOUT VOLTAGE
VS – VO
VS = 4.1 V, ILOAD = 10 mA
VS = 4.4 V, ILOAD = 20 mA
0.80
1.10
V
V
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
–11–
REV. D
REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = 5.0 V, TA = +25؇C unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
INITIAL ACCURACY1
“E” Grade
“F” Grade
VO
IOUT = 0 mA
4.094 4.096 4.098
V
V
V
4.091
4.086
4.101
4.106
“G” Grade
LINE REGULATION2
“E” Grade
“F & G” Grades
LOAD REGULATION2
“E” Grade
“F & G” Grades
∆VO/∆VIN
4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.4 V, 0 ≤ IOUT ≤ 30 mA
2
4
4
8
ppm/V
ppm/V
∆VO/∆VLOAD
2
4
4
8
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 4.6 V, ILOAD = 10 mA
VS = 5.4 V, ILOAD = 30 mA
0.50
1.30
V
V
LONG-TERM STABILITY3
NOISE VOLTAGE
NOTES
∆VO
1000 Hours @ +125°C
1.2
40
mV
eN
0.1 Hz to 10 Hz
µV p-p
1Initial accuracy includes temperature hysteresis effect.
2Line and load regulation specifications include the effect of self-heating.
3Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
(@ VS = +5.0 V, –40؇C ≤ TA ≤ +85؇C unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
5
10
25
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VIN
4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.4 V, 0 ≤ IOUT ≤ 25 mA
5
10
10
20
ppm/V
ppm/V
LOAD REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VLOAD
5
10
10
20
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 4.6 V, ILOAD = 10 mA
VS = 5.4 V, ILOAD = 25 mA
0.50
1.30
V
V
SLEEP PIN
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VH
IH
VL
IL
2.4
V
µA
V
–8
0.8
–8
µA
SUPPLY CURRENT
Sleep Mode
No Load
No Load
45
15
µA
µA
.
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. D
–12–
REF19x Series
REF198–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VS = +5.0 V, –40؇C ≤ TA ≤ +125؇C unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
TEMPERATURE COEFFICIENT1, 2
“E” Grade
“F” Grade
“G” Grade3
TCVO/°C
IOUT = 0 mA
2
5
10
ppm/°C
ppm/°C
ppm/°C
LINE REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VIN
4.5 V ≤ VS ≤ 15 V, IOUT = 0 mA
VS = 5.6 V, 0 ≤ IOUT ≤ 20 mA
5
10
ppm/V
ppm/V
LOAD REGULATION4
“E” Grade
“F & G” Grades
∆VO /∆VLOAD
5
10
ppm/mA
ppm/mA
DROPOUT VOLTAGE
VS – VO
VS = 4.7 V, ILOAD = 10 mA
VS = 5.6 V, ILOAD = 20 mA
0.60
1.50
V
V
NOTES
1For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.
2TCVO is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.
TCVO = (V max–V min)/VO (TMAX–TMIN).
3Guaranteed by characterization.
4Line and load regulation specifications include the effect of self-heating.
Specifications subject to change without notice.
REV. D
–13–
REF19x Series
WAFER TEST LIMITS (@ ILOAD = 0 mA, TA = +25°C unless otherwise noted)
Parameter
Symbol
Condition
Limits
Units
INITIAL ACCURACY
REF191
REF192
REF193
REF194
REF195
REF196
REF198
VO
2.043/2.053
2.495/2.505
2.990/3.010
4.495/4.505
4.995/5.005
3.290/3.310
4.091/4.101
V
V
V
V
V
V
V
LINE REGULATION
LOAD REGULATION
DROPOUT VOLTAGE
∆VO /∆VIN
(VO + 0.5 V) < VIN < 15 V, IOUT = 0 mA
15
15
ppm/V
∆VO /∆ILOAD 0 mA < ILOAD < 30 mA, VIN = (VO + 1.3 V)
ppm/mA
VO – V+
ILOAD = 10 mA
ILOAD = 30 mA
1.25
1.55
V
V
SLEEP MODE INPUT
Logic Input High
Logic Input Low
VIH
VIL
2.4
0.8
V
V
SUPPLY CURRENT
Sleep Mode
V
IN = 15 V
No Load
No Load
45
15
µA
µA
NOTE
For proper operation, a 1 µF capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer probe to the limits shown. Due
to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications
based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS1
DICE CHARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V
Output to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VS + 0.3 V
Output to GND Short-Circuit Duration . . . . . . . . . . Indefinite
Storage Temperature Range
OUTPUT
6
OUTPUT
6
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
REF19x . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
2
Package Type
Units
JA
JC
8-Lead Plastic DIP (P)
8-Lead SOIC (S)
8-Lead TSSOP
103
158
240
43
43
43
°C/W
°C/W
°C/W
2
3
4
V+
SLEEP
GND
REF19x Die Size 0.041 × 0.057 Inch, 2,337 Sq. Mils
Substrate Is Connected to V+, Number of Transistors:
Bipolar 25, MOSFET4. Process: CBCMOS1
NOTES
1Absolute maximum rating applies to both DICE and packaged parts, unless
otherwise noted.
2θJA is specified for worst case conditions, i.e., θJA is specified for device in socket for
P-DIP, and θJA is specified for device soldered in circuit board for SOIC package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the REF19x features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–14–
REF19x Series
5.004
5.003
5.002
5.001
5.000
4.999
4.998
4.997
4.996
50
45
40
35
30
25
20
15
10
5
3 TYPICAL PARTS
5.15V < V < 15V
IN
BASED ON 600
UNITS, 4 RUNS
–40؇C
T
+85؇C
A
0
–20
–50
–25
0
25
50
75
100
–15
–10
–5
–V
0
5
10
15
20
T
– ppm/؇C
TEMPERATURE – ؇C
C
OUT
Figure 1. REF195 Output Voltage vs. Temperature
Figure 4. TC – VOUT Distribution
32
28
40
35
30
25
20
15
10
5
+5.15V
V
15V
NORMAL MODE
S
24
20
16
12
8
–40؇C
+25؇C
+85؇C
SLEEP MODE
4
0
0
–50
0
5
10
15
– mA
20
25
30
–25
0
25
50
75
100
I
TEMPERATURE – ؇C
LOAD
Figure 2. REF195 Line Regulation vs. ILOAD
Figure 5. Quiescent Current vs. Temperature
20
16
12
8
–6
O
I
< 25mA
OUT
+85؇C
–5
–4
–3
–2
+25؇C
–40؇C
V
V
L
4
–1
H
0
0
–50
4
6
8
10
– Volts
12
14
16
–25
0
25
50
75
100
V
IN
TEMPERATURE – ؇C
Figure 3. REF195 Load Regulation vs. VIN
Figure 6. SLEEP Pin Current vs. Temperature
REV. D
–15–
REF19x Series
2
4
6
V
= 15V
IN
REF19x
10mA
0
1F
0
–20
Figure 9b. Load Transient Response Measurement Circuit
–40
–60
–80
2V
100
90
–100
–120
1mA
LOAD
10
100
1k
10k
100k
1M
30mA
LOAD
FREQUENCY – Hz
10
0%
Figure 7a. Ripple Rejection vs. Frequency
2V
100s
10F
Figure 10a. Power ON Response Time
10F
1k⍀
1k⍀
2
6
OUTPUT
V
= +15V
REF19x
4
IN
2
4
6
1F
10F
REF19x
V
= 7.0V
1F
IN
REF
Figure 7b. Ripple Rejection vs. Frequency
Measurement Circuit
Figure 10b. Power ON Response Time Measurement
Circuit
V
= 7V
IN
200⍀
2
6
5V
REF19x
V
= 2V p-p
= 4.00V
100
90
ON
G
4
1F
1F
OFF
Z
V
S
I
= 1mA
L
V
OUT
4
3
2
I
= 10mA
L
10
0%
2ms
1V
1
0
Figure 11a. Sleep Response Time
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
V
= 15V
IN
2
3
Figure 8. Output Impedance vs. Frequency
V
OUT
REF19x
4
6
1F
5V
OFF
100
90
ON
Figure 11b. Sleep Response Time Measurement Circuit
10
0%
20mV
100s
Figure 9a. Load Transient Response
REV. D
–16–
REF19x Series
35
30
25
20
15
10
5
5V
100
90
10
0%
200mV
200s
Figure 12. Line Transient Response
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
REF195 DROPOUT VOLTAGE – V
Figure 13. Dropout Voltage vs. Load Current
+V
Output Voltage Bypassing
For stable operation, low dropout voltage regulators and refer-
ences, in general, require a bypass capacitor connected from
their VOUT pins to their GND pins. Although the REF19x
family of references is capable of stable operation with capacitive
loads exceeding 100 µF, a 1 µF capacitor is sufficient to guaran-
tee rated performance. The addition of a 0.1 µF ceramic ca-
pacitor in parallel with the bypass capacitor will improve load
current transient performance. For best line voltage transient
performance, it is recommended that the voltage inputs of these
devices be bypassed with a 10 µF electrolytic capacitor in paral-
lel with a 0.1 µF ceramic capacitor.
V
OUT
SHUTDOWN
Sleep Mode Operation
GND
All REF19x devices include a sleep capability that is TTL/CMOS
level compatible. Internal to the REF19x at the SLEEP pin, a
pull-up current source to VIN is connected. This permits the
SLEEP pin to be driven from an open collector/drain driver.
A logic LOW or a zero volt condition on the SLEEP pin is re-
quired to turn the output stage OFF. During sleep, the output
of the references becomes a high impedance state where its
potential would then be determined by external circuitry. If the
sleep feature is not used, it is recommended that the SLEEP pin
be connected to VIN (Pin 2).
Figure 14. Simplified Schematic
APPLICATIONS SECTION
Output Short Circuit Behavior
The REF19x family of devices is totally protected from damage
due to accidental output shorts to GND or to V+. In the event
of an accidental short circuit condition, the reference device will
shutdown and limit its supply current to 100 µA.
Device Power Dissipation Considerations
The REF19x family of references is capable of delivering load
currents to 30 mA with an input voltage that ranges from 3.3 V
to 15 V. When these devices are used in applications with large
input voltages, care should be exercised to avoid exceeding these
devices’ maximum internal power dissipation. Exceeding the
published specifications for maximum power dissipation or
junction temperature could result in premature device failure.
The following formula should be used to calculate a device’s
maximum junction temperature or dissipation:
Basic Voltage Reference Connections
The circuit in Figure 15 illustrates the basic configuration for
the REF19x family of references. Note the 10 µF/0.1 µF bypass
network on the input and the 1 µF/0.1 µF bypass network on the
output. It is recommended that no connections be made to
Pins 1, 5, 7 and 8. If the sleep feature is not required, Pin 3
should be connected to VIN.
NC
NC
NC
1
2
3
4
8
7
6
5
V
IN
TJ – TA
PD
=
REF19x
OUTPUT
10F
0.1F
θJA
SLEEP
1F
TANT
0.1F
NC
In this equation, TJ and TA are the junction and ambient tem-
peratures, respectively, PD is the device power dissipation and
θJA is the device package thermal resistance.
Figure 15. Basic Voltage Reference Configuration
REV. D
–17–
REF19x Series
Membrane Switch Controlled Power Supply
In this circuit, the power supply current of reference U1 flowing
through R1–R2 develops a base drive for Q1, whose collector
provides the bulk of the output current. With a typical gain of
100 in Q1 for 100 mA–200 mA loads, U1 is never required to
furnish more than a few mA, so this factor minimizes tempera-
ture related drift. Short circuit protection is provided by Q2,
which clamps drive to Q1 at about 300 mA of load current with
values as shown. With this separation of control and power
functions, dc stability is optimum, allowing best advantage use
of premium grade REF19x devices for U1. Of course, load
management should still be exercised. A short, heavy, low DCR
(DC Resistance) conductor should be used from U1–6 to the
VOUT sense point “S,” where the collector of Q1 connects to the
load, point “F.”
With output load currents in the tens of mA, the REF19x family
of references can operate as a low dropout power supply in
hand-held instrument applications. In the circuit shown in
Figure 16, a membrane ON/OFF switch is used to control the
operation of the reference. During an initial power-on condi-
tion, the SLEEP pin is held to GND by the 10 kΩ resistor.
Recall that this condition disables (read: three-state) the
REF19x output. When the membrane ON switch is pressed,
the SLEEP pin is momentarily pulled to VIN, enabling the
REF19x output. At this point, current through the 10 kΩ is
reduced and the internal current source connected to the
SLEEP pin takes control. Pin 3 assumes and remains at the
same potential as VIN. When the membrane OFF switch is
pressed, the SLEEP pin is momentarily connected to GND,
which once again disables the REF19x output.
Because of the current limiting configuration, the dropout volt-
age circuit is raised about 1.1 V over that of the REF19x de-
vices, due to the VBE of Q1 and the drop across current sense
resistor R4. However, overall dropout is typically still low
enough to allow operation of a 5 V to 3.3 V regulator/reference
using the REF196 for U1 as noted, with a VS as low as 4.5 V
and a load current of 150 mA.
NC
NC
8
7
6
5
NC
1
2
3
4
V
IN
REF19x
OUTPUT
1k⍀
5%
1F
TANT
NC
ON
The requirement for a heat sink on Q1 depends on the maxi-
mum input voltage and short circuit current. With VS = 5 V
and a 300 mA current limit, the worst case dissipation of Q1 is
1.5 W, less than the TO-220 package 2 W limit. However, if
smaller TO-39 or TO-5 packaged devices such as the 2N4033
are used, the current limit should be reduced to keep maximum
dissipation below the package rating. This is accomplished by
simply raising R4.
10k⍀
OFF
Figure 16. Membrane Switch Controlled Power Supply
Current-Boosted References with Current Limiting
While the 30 mA rated output current of the REF19x series is
higher than typical of other reference ICs, it can be boosted to
higher levels if desired, with the addition of a simple external
PNP transistor, as shown in Figure 17. Full time current limit-
ing is used for protection of the pass transistor against shorts.
A tantalum output capacitor is used at C1 for its low ESR
(Equivalent Series Resistance), and the higher value is required
for stability. Capacitor C2 provides input bypassing and can be
an ordinary electrolytic.
Shutdown control of the booster stage is shown as an option,
and when used some cautions are in order. Because of the
additional active devices in the VS line to U1, direct drive to
Pin 3 does not work as with an unbuffered REF19x device. To
enable shutdown control, the connection to U1-2 is broken at
the “X,” and diode D1 then allows a CMOS control source VC
to drive U1-3 for ON-OFF operation. Startup from shutdown is
not as clean under heavy load as it is in basic REF19x series and
can require several milliseconds under load. Nevertheless, it is
still effective and can fully control 150 mA loads. When shutdown
control is used, heavy capacitive loads should be minimized.
Q1
TIP32A
(SEE TEXT)
R4
2⍀
OUTPUT TABLE
+V = 6 TO 9V
S
(SEE TEXT)
R1
1k⍀
V
(V)
U1
OUT
Q2
REF192
REF193
REF196
REF194
REF195
2.5
3.0
3.3
4.5
5.0
2N3906
R2
1.5k⍀
C2
100F/25V
C3
0.1F
F
D1
U1
REF196
S
+V
3.3V
OUT
V
C
(SEE TABLE)
1N4148
(SEE TEXT
ON SLEEP)
@ 150mA
C1
10F/25V
(TANTALUM)
R3
1.82k⍀
R1
S
F
V
V
S
OUT
COMMON
COMMON
Figure 17. A Boosted 3.3 V Reference with Current
Limiting
REV. D
–18–
REF19x Series
Stacking Reference ICs for Arbitrary Outputs
A Negative Precision Reference without Precision Resistors
In many current-output CMOS DAC applications, where the
output signal voltage must be of the same polarity as the
reference voltage, it is often required to reconfigure a cur-
rent-switching DAC into a voltage-switching DAC through the
use of a 1.25 V reference, an op amp and a pair of resistors.
Using a current-switching DAC directly requires an additional
operational amplifier at the output to reinvert the signal. A
negative voltage reference is then desirable from the point that
an additional operational amplifier is not required for either
reinversion (current-switching mode) or amplification (voltage
switching mode) of the DAC output voltage. In general, any
positive voltage reference can be converted into a negative volt-
age reference through the use of an operational amplifier and a
pair of matched resistors in an inverting configuration. The
disadvantage to that approach is that the largest single source of
error in the circuit is the relative matching of the resistors used.
Some applications may require two reference voltage sources
that are a combined sum of standard outputs. The circuit of
Figure 19 shows how this “stacked output” reference can be
implemented.
OUTPUT TABLE
U1/U2
V
(V)
V
(V)
OUT1
OUT2
REF192/REF192
REF192/REF194
REF192/REF195
2.5
2.5
2.5
5.0
7.0
7.5
+V
OUT2
S
V
S
> V
+0.15V
C1
0.1F
U2
+V
REF19x
OUT2
(SEE TABLE)
C2
V
O
(U2)
1F
C3
0.1F
U1
+V
OUT1
REF19x
R1
3.9k⍀
(SEE TEXT)
(SEE TABLE)
C4
1F
The circuit illustrated in Figure 18 avoids the need for tightly
matched resistors with the use of an active integrator circuit. In
this circuit, the output of the voltage reference provides the
input drive for the integrator. The integrator, to maintain cir-
cuit equilibrium, adjusts its output to establish the proper rela-
tionship between the reference’s VOUT and GND. Thus, any
desired negative output voltage can be chosen by simply sub-
stituting for the appropriate reference IC. The sleep feature is
maintained in the circuit with the simple addition of a PNP
transistor and a 10 kΩ resistor. One caveat with this approach
should be mentioned: although rail-to-rail output amplifiers
work best in the application, these operational amplifiers require
a finite amount (mV) of headroom when required to provide
any load current. The choice for the circuit’s negative supply
should take this issue into account.
V
O
(U1)
V
V
IN
OUT
COMMON
COMMON
Figure 19. Stacking Voltage References with the REF19x
Two reference ICs are used, fed from a common unregulated
input, VS. The outputs of the individual ICs are simply con-
nected in series as shown, which provides two output voltages,
VOUT1 and VOUT2. VOUT1 is the terminal voltage of U1, while
VOUT2 is the sum of this voltage and the terminal voltage of U2.
U1 and U2 are simply chosen for the two voltages that supply
the required outputs (see table). If, for example, both U1 and
U2 are REF192s, the two outputs are 2.5 V and 5.0 V.
While this concept is simple, some cautions are in order. Since
the lower reference circuit must sink a small bias current from
U2 (50 µA–100 µA), plus the base current from the series PNP
output transistor in U2, either the external load of U1 or R1
must provide a path for this current. If the U1 minimum load is
not well defined, resistor R1 should be used, set to a value that
will conservatively pass 600 µA of current with the applicable
VOUT1 across it. Note that the two U1 and U2 reference circuits
are locally treated as macrocells, each having its own bypasses at
input and output for best stability. Both U1 and U2 in this
circuit can source dc currents up to their full rating. The mini-
mum input voltage, VS, is determined by the sum of the out-
puts, VOUT2, plus the dropout voltage of U2.
V
IN
10k⍀
SLEEP
TTL/CMOS
2N3906
V
IN
1F
+5V
1k⍀
1F
V
SLEEP
REF
REF19x
GND
100⍀
A1
–V
REF
10k⍀
100k⍀
–5V
A1 = 1/2 OP295,
1/2 OP291
A related variation on stacking two three-terminal references is
shown in Figure 19, where U1, a REF192, is stacked with a
two-terminal reference diode such as the AD589. Like the
three-terminal stacked reference above, this circuit provides two
outputs, VOUT1 and VOUT2, which are the individual terminal
voltages of D1 and U1 respectively. Here this is 1.235 and 2.5,
which provides a VOUT2 of 3.735 V. When using two-terminal
reference diodes such as D1, the rated minimum and maximum
device currents must be observed and the maximum load cur-
rent from VOUT1 can be no greater than the current set up by R1
and VO(U1). In the case with VO(U1) equal to 2.5 V, R1 provides
a 500 µA bias to D1, so the maximum load current available at
VOUT1 is 450 µA or less.
Figure 18. A Negative Precision Voltage Reference
Uses No Precision Resistors
REV. D
–19–
REF19x Series
Switched Output 5 V/3.3 V Reference
+V
OUT2
S
Applications often require digital control of reference voltages,
selecting between one stable voltage and a second. With the
sleep feature inherent to the REF19x series, switched output
reference configurations are easily implemented with relatively
little additional hardware.
V
S
> V
+0.15V
U1
+V
3.735V
OUT2
REF192
C1
0.1F
R1
C2
V
(U1)
(D1)
4.99k⍀
O
1F
(SEE TEXT)
The circuit of Figure 22 illustrates the general technique, which
takes advantage of the output “wire-OR” capability of the
REF19x device family. When OFF, a REF19x device is effec-
tively an open circuit at the output node with respect to the
power supply. When ON, a REF19x device can source current
up to its current rating, but sink only a few µA (essentially just
the relatively low current of the internal output scaling divider).
As a result, for two devices wired together at their common
outputs, the output voltage is simply that of the ON device.
The OFF state device will draw a small standby current of
15 µA (max), but otherwise will not interfere with operation of
the ON device, which can operate to its full current rating.
Note that the two devices in the circuit conveniently share
both input and output capacitors, and with CMOS logic
drive, it is power efficient.
+V
OUT1
1.235V
C3
1F
D1
V
O
AD589
V
V
OUT
COMMON
IN
COMMON
Figure 20. Stacking Voltage References with the REF19x
A Precision Current Source
Many times, in low power applications, the need arises for a
precision current source that can operate on low supply volt-
ages. As shown in Figure 21, any one of the devices in the
REF19x family of references can be configured as a precision
current source. The circuit configuration illustrated is a floating
current source with a grounded load. The reference’s output
voltage is bootstrapped across RSET, which sets the output cur-
rent into the load. With this configuration, circuit precision is
maintained for load currents in the range from the reference’s
supply current (typically, 30 µA) to approximately 30 mA. The
low dropout voltage of these devices maximizes the current
source’s output voltage compliance without excess headroom.
Using dissimilar REF19x series devices with this configuration
allows logic selection between the U1/U2 specified terminal
voltages. For example, with U1 (a REF195) and U2 (a REF196),
as noted in the table, changing the CMOS compatible VC logic
control voltage from HI to LO selects between a nominal output
of 5.000 V and 3.300 V and vice versa. Other REF19x family
units can also be used for U1/U2, with similar operation in a
logic sense, but with outputs as per the individual paired devices
(see table, again). Of course, the exact output voltage tolerance,
drift and overall quality of the reference voltage will be consis-
tent with the grade of individual U1 and U2 devices.
V
IN
V
IN
REF19x
V
SLEEP
OUTPUT TABLE
REF
GND
R1
P1
U1/U2
V
*
V
(V)
OUT
C
1F
R
SET
I
REF195/
REF196
HI
LO 3.3
5.0
SY
ADJUST
REF194/
REF195
HI
LO 5.0
4.5
+V = 6V
S
I
OUT
V
I
• R (MAX) + V (MIN)
IN
OUT L SY
* CMOS LOGIC LEVELS
U1
2
3
R
L
1
4
V
OUT
V
C
I
=
+ I (REF19x)
SY
OUT
REF19x
R
SET
(SEE TABLE)
V
E.G. REF195 : V
= 5mA
= 5V
OUT
U3A
U3B
OUT
>> I
SY
I
OUT
74HC04 74HC04
R
SET
R1 = 953⍀
P1 = 100⍀, 10-TURN
+V
OUT
Figure 21. A Low Dropout, Precision Current Source
U2
C2
1F
REF19x
(SEE TABLE)
The circuit’s governing equations are:
C1
0.1F
V
V
IN
OUT
VIN = IOUT × RL(max)+VSY (min, REF19x)
COMMON
COMMON
VOUT
RSET
IOUT
=
+ ISY (REF19x)
Figure 22. Switched Output Reference
VOUT
RSET
I
SY (REF19x)
REV. D
–20–
REF19x Series
resistance within the forcing loop of the op amp. Since the op
amp senses the load voltage, op amp loop control forces the
output to compensate for the wiring error and to produce the
correct voltage at the load. Depending on the reference device
chosen, operational amplifiers that can be used in this applica-
tion are the OP295, the OP291 and the OP183/OP283.
There is one application caveat that should be understood about
this circuit, which comes about due to the wire-OR nature.
Since U1 and U2 can only source current effectively, negative
going output voltage changes, which require the sinking of cur-
rent, will necessarily take longer than positive going changes. In
practice, this means that the circuit is quite fast when undergo-
ing a transition from 3.3 to 5 V, but the transition from 5 to
3.3 V will take longer. Exactly how much longer will be a func-
tion of the load resistance, RL, seen at the output and the
typical 1 µF value of C2. In general, a conservative transition
time here will be on the order of several milliseconds for load
resistances in the range of 100 Ω–1 kΩ. Note that for highest
accuracy at the new output voltage, several time constants
should be allowed (>7.6 time constants for <1/2 LSB error @
10 bits, for example).
V
V
IN
IN
R
LW
+V
OUT
SENSE
V
IN
2
3
R
LW
1
+V
OUT
REF19x
A1
FORCE
V
OUT
SLEEP
R
L
GND
1F
100k⍀
A1 = 1/2 OP295
1/2 OP292
1/2 OP283
Kelvin Connections
Figure 23. A Low Dropout, Kelvin Connected Voltage
Reference
In many portable instrumentation applications where PC board
cost and area go hand-in-hand, circuit interconnects are very
often of dimensionally minimum width. These narrow lines can
cause large voltage drops if the voltage reference is required to
provide load currents to various functions. In fact, a circuit’s
interconnects can exhibit a typical line resistance of 0.45 mΩ/
square (1 oz. Cu, for example). In those applications where
these devices are configured as low dropout voltage regulators,
these wiring voltage drops can become a large source of error.
To circumvent this problem, force and sense connections can be
made to the reference through the use of an operational ampli-
fier, as shown in Figure 23. This method provides a means by
which the effects of wiring resistance voltage drops can be elimi-
nated. Load currents flowing through wiring resistance produce
an I-R error (ILOAD × RWIRE) at the load. However, the Kelvin
connection overcomes the problem by including the wiring
A Fail-Safe 5 V Reference
Some critical applications require a reference voltage to be
maintained constant, even with a loss of primary power. The
low standby power of the REF19x series and the switched out-
put capability allow a “fail-safe” reference configuration to be
implemented rather easily. This reference maintains a tight
output voltage tolerance for either a primary power source (ac
line derived) or a standby (battery derived) power source, auto-
matically switching between the two as the power conditions
change.
The circuit in Figure 24 illustrates the concept, which borrows
from the switched output idea of Figure 21, again using the
REF19x device family output “wire-OR” capability. In this
case, since a constant 5 V reference voltage is desired for all
+V
BAT
C2
0.1F
+V
S
U1
R1
REF195
R3
10M⍀
R6
1.1M⍀
+5.000V
100⍀
Q1
2N3904
C1
0.1F
3
2
7
6
U3
C3
1F
4
AD820
U2
REF195
R2
100k⍀
R4
900k⍀
C4
0.1F
R5
100k⍀
V , V
V
BAT
S
OUT
COMMON
COMMON
Figure 24. A Fail-Safe 5 V Reference
REV. D
–21–
REF19x Series
conditions, two REF195 devices are used for U1 and U2, with
their ON/OFF switching controlled by the presence or absence
of the primary dc supply source, VS. VBAT is a 6 V battery
backup source that supplies power to the load only when VS
fails. For normal (VS present) power conditions, VBAT sees only
the 15 µA (max) standby current drain of U1 in its OFF state.
A Low Power, Strain Gage Circuit
As shown in Figure 25, the REF19x family of references can
be used in conjunction with low supply voltage operational
amplifiers, such as the OP492 and the OP283, in a self-con-
tained strain gage circuit. In this circuit, the REF195 was used
as the core of this low power, strain gage circuit. Other refer-
ences can be easily accommodated by changing circuit element
values. The references play a dual role as the voltage regulator
to provide the supply voltage requirements of the strain gage
and the operational amplifiers as well as a precision voltage
reference for the current source used to stimulate the bridge. A
distinct feature of the circuit is that it can be remotely controlled
ON or OFF by digital means via the SLEEP pin.
In operation, it is assumed that for all conditions either U1 or
U2 is ON and a 5 V reference output is available. With this
voltage constant, a scaled down version is applied to the com-
parator IC U3, providing a fixed 0.5 V input to the (–) input for
all power conditions. The R1–R2 divider provides a signal to
the U3 (+) input proportional to VS, which switches U3 and
U1/U2 dependent upon the absolute level of VS. Op amp U3 is
configured here as a comparator with hysteresis, which provides
for clean, noise free output switching. This hysteresis is impor-
tant to eliminate rapid switching at the threshold due to VS
ripple. Further, the device chosen is the AD820, a rail-rail
output device, which provides HI and LO output states within a
few mV of VS and ground for accurate thresholds and compat-
ible drive for U2 for all VS conditions. R3 provides positive
feedback for circuit hysteresis, changing the threshold at the (+)
input as a function of U3’s output.
100⍀
10F
REF195
1F
10F
57k⍀
1%
0.1F
For VS levels lower than the LOWER threshold, U3’s output is
low, thus U2 and Q1 are OFF, while U1 is ON. For VS levels
higher than the UPPER threshold, the situation reverses, with
U1 OFF and both U2 and Q1 ON. In the interest of battery
power conservation, all of the comparison switching circuitry is
powered from VS and is so arranged that when VS fails the de-
fault output comes from U1.
1/4
10k⍀
1%
2N2222
0.1F
OP492
500⍀
0.1%
0.01F
For the R1–R3 values as shown, the LOWER/UPPER VS
switching thresholds are approximately 5.5 V and 6 V, respec-
tively. These can obviously be changed to suit other VS sup-
plies, as can the REF19x devices used for U1 and U2, over a
range of 2.5 V to 5 V of output. U3 can operate down to a VS
of 3.3 V, which is generally compatible with all family devices.
10k⍀
1%
20k⍀
1%
20k⍀
1%
1/4
OP492
1/4
OP492
OUTPUT
10k⍀
1%
2.21k⍀
20k⍀
1%
1/4
OP492
20k⍀
1%
Figure 25. A Low Power, Strain Gage Circuit
REV. D
–22–
REF19x Series
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (P Suffix)
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
4
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
8-Lead Narrow Body SO (S Suffix)
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8-Lead TSSOP (RU Suffix)
(RU-8)
0.122 (3.10)
0.114 (2.90)
8
1
5
4
PIN 1
0.0256 (0.65)
BSC
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
REV. D
–23–
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