REF198ESZ_技术文档

Precision Micropower, Low Dropout

Voltage References

REF19x Series

TEST PINS

FEATURES

Test Pin 1 and Test Pin 5 are reserved for in-package Zener zap.

To achieve the highest level of accuracy at the output, the Zener

zapping technique is used to trim the output voltage. Since each

unit may require a different amount of adjustment, the resistance

value at the test pins varies widely from pin to pin and from

part to part. The user should leave Pin 1 and Pin 5

unconnected.

Initial accuracy: 2 mV maximum

Temperature coefficient: 5 ppm/°C maximum

Low supply current: 45 μA maximum

Sleep mode: 15 μA maximum

Low dropout voltage

Load regulation: 4 ppm/mA

Line regulation: 4 ppm/V

High output current: 30 mA

Short-circuit protection

TP

1

2

3

4

8

7

6

5

NC

REF19x

SERIES

TOP VIEW

(Not to Scale)

V

NC

S

APPLICATIONS

Portable instruments

ADCs and DACs

Smart sensors

Solar-powered applications

Loop current-powered instruments

SLEEP

GND

OUTPUT

TP

NOTES

1. NC = NO CONNECT.

2. TP PINS ARE FACTORY TEST

POINTS, NO USER CONNECTION.

Figure 1. 8-Lead SOIC_N and TSSOP Pin Configuration

(S Suffix and RU Suffix)

GENERAL DESCRIPTION

TP

1

2

3

4

8

7

6

5

NC

The REF19x series precision band gap voltage references use a

patented temperature drift curvature correction circuit and

laser trimming of highly stable, thin-film resistors to achieve a

very low temperature coefficient and high initial accuracy.

REF19x

SERIES

TOP VIEW

(Not to Scale)

V

NC

S

SLEEP

GND

OUTPUT

TP

NOTES

1. NC = NO CONNECT.

2. TP PINS ARE FACTORY TEST

POINTS, NO USER CONNECTION.

The REF19x series is made up of micropower, low dropout

voltage (LDV) devices, providing stable output voltage from

supplies as low as 100 mV above the output voltage and

consuming less than 45 μA of supply current. In sleep mode,

which is enabled by applying a low TTL or CMOS level to the

Figure 2. 8-Lead PDIP Pin Configuration

(P Suffix)

SLEEP

Table 1. Nominal Output Voltage

pin, the output is turned off, and supply current is

Part Number

Nominal Output Voltage (V)

further reduced to less than 15 μA.

REF191

REF192

REF193

REF194

REF195

REF196

REF198

2.048

2.50

3.00

4.50

5.00

3.30

4.096

The REF19x series references are specified over the extended

industrial temperature range (−40°C to +85°C), with typical

performance specifications over −40°C to +125°C for

applications such as automotive.

All electrical grades are available in an 8-lead SOIC_N package;

the PDIP and TSSOP packages are available only in the lowest

electrical grade. Products are also available in die form.

Rev. I

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

REF19x Series

TABLE OF CONTENTS

Specifications..................................................................................... 3

Wafer Test Limits........................................................................ 14

Absolute Maximum Ratings ......................................................... 15

Thermal Resistance.................................................................... 15

ESD Caution................................................................................ 15

Typical Performance Characteristics ........................................... 16

Applications..................................................................................... 19

Output Short-Circuit Behavior ................................................ 19

Device Power Dissipation Considerations.............................. 19

Output Voltage Bypassing......................................................... 19

Sleep Mode Operation............................................................... 19

Basic Voltage Reference Connections ..................................... 19

Membrane Switch-Controlled Power Supply......................... 19

Current-Boosted References with Current Limiting............. 20

Negative Precision Reference without Precision Resistors... 20

Stacking Reference ICs for Arbitrary Outputs ....................... 21

Precision Current Source .......................................................... 21

Switched Output 5 V/3.3 V Reference..................................... 22

Kelvin Connections.................................................................... 22

Fail-Safe 5 V Reference.............................................................. 23

Low Power, Strain Gage Circuit ............................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 26

Electrical Characteristics—REF191 @ T_A= 25°C.................... 3

Electrical Characteristics—REF191 @ −40°C ≤ T_A≤ +85°C .. 4

Electrical Characteristics—REF191 @ −40°C ≤ T_A≤+125°C. 5

Electrical Characteristics—REF192 @ T_A= 25°C.................... 5

Electrical Characteristics—REF192 @ −40°C ≤ T_A≤ +85°C.. 6

Electrical Characteristics—REF192 @ −40°C ≤ T_A≤ +125°C 6

Electrical Characteristics—REF193 @ T_A= 25°C.................... 7

Electrical Characteristics—REF193 @ −40°C ≤ T_A≤ +85°C.. 7

Electrical Characteristics—REF193 @ T_A≤ −40°C ≤ +125°C 8

Electrical Characteristics—REF194 @ T_a= 25°C..................... 8

Electrical Characteristics—REF194 @ −40°C ≤ T_A≤ +85°C.. 9

Electrical Characteristics—REF194 @ −40°C ≤ T_A≤ +125°C 9

Electrical Characteristics—REF195 @ T_A= 25°C.................. 10

Electrical Characteristics—REF195 @ −40°C ≤ T_A≤ +85°C 10

Electrical Characteristics—REF195 @ −40°C ≤ T_A≤ +125°C

....................................................................................................... 11

Electrical Characteristics—REF196 @ T_A= 25°C.................. 11

Electrical Characteristics—REF196 @ −40°C ≤ T_A≤ +85°C 12

Electrical Characteristics—REF196 @ −40°C ≤ T_A≤ +125°C

....................................................................................................... 12

Electrical Characteristics—REF198 @ T_A= 25°C.................. 13

Electrical Characteristics—REF198 @ −40°C ≤ T_A≤ +85°C 13

Electrical Characteristics—REF198 @ −40°C ≤ T_A≤ +125°C

....................................................................................................... 14

REVISION HISTORY

7/04—Rev. F to Rev. G

Changes to Ordering Guide.............................................................4

9/06—Rev. H to Rev. I

Updated Format..................................................................Universal

Changes to Table 25 ....................................................................... 15

Changes to Figure 6........................................................................ 16

Changes to Figure 10, Figure 12, Figure 14, and Figure 16....... 17

Changes to Figure 18...................................................................... 18

Changes to Figure 20...................................................................... 19

Changes to Figure 23...................................................................... 20

Changes to Figure 25...................................................................... 21

Updated Outline Dimensions....................................................... 25

Changes to Ordering Guide .......................................................... 26

3/04—Rev. E to Rev. F

Updated Absolute Maximum Rating..............................................4

Changes to Ordering Guide.......................................................... 14

Updated Outline Dimensions....................................................... 24

1/03—Rev. D to Rev. E

Changes to Figure 3 and Figure 4................................................. 15

Changes to Output Short Circuit Behavior................................. 17

Changes to Figure 20...................................................................... 17

Changes to Figure 24...................................................................... 19

Updated Outline Dimensions....................................................... 23

6/05—Rev. G to Rev. H

Updated Format..................................................................Universal

Changes to Caption in Figure 7 .................................................... 16

Updated Outline Dimensions....................................................... 25

Changes to Ordering Guide .......................................................... 26

1/96—Revision 0: Initial Version

Rev. I | Page 2 of 28

REF19x Series

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—REF191 @ T_A= 25°C

@ V_S= 3.3 V, T_A= 25°C, unless otherwise noted.

Table 2.

Parameter

INITIAL ACCURACY¹

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade

V_O

I_OUT= 0 mA

2.046

2.043

2.038

2.048

2.050

2.053

2.058

V

LINE REGULATION²

E Grade

ΔV_O/ΔV_IN

3.0 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 30 mA

2

4

8

ppm/V

F and G Grades

LOAD REGULATION²

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

4

6

10

15

ppm/mA

V_S= 3.15 V, I_LOAD= 2 mA

V_S= 3.3 V, I_LOAD= 10 mA

V_S= 3.6 V, I_LOAD= 30 mA

1000 hours @ 125°C

0.1 Hz to 10 Hz

0.95

1.25

1.55

V

LONG-TERM STABILITY³

NOISE VOLTAGE

DV_O

e_N

1.2

20

mV

μV p-p

¹Initial accuracy includes temperature hysteresis effect.

²Line and load regulation specifications include the effect of self-heating.

³Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

Rev. I | Page 3 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF191 @ −40°C ≤ T_A≤ +85°C

@ V_S= 3.3 V, −40°C ≤ T_A≤ +85°C, unless otherwise noted.

Table 3.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

5

10

25

ppm/°C

LINE REGULATION⁴

E Grade

ΔV_O/ΔV_IN

3.0 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 25°C

5

10

20

ppm/V

F and G Grades

LOAD REGULATION⁴

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

5

10

15

20

ppm/mA

V_S= 3.15 V, I_LOAD= 2 mA

V_S= 3.3 V, I_LOAD= 10 mA

V_S= 3.6 V, I_LOAD= 25 mA

0.95

1.25

1.55

V

SLEEP

Logic High Input Voltage

Logic High Input Current

Logic Low Input Voltage

Logic Low Input Current

SUPPLY CURRENT

V_H

I_H

V_L

I_L

2.4

V

μA

V

μA

−8

0.8

−8

45

15

No load

Sleep Mode

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 4 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF191 @ −40°C ≤ T_A≤+125°C

@ V_S= 3.3 V, −40°C ≤ T_A≤ +125°C, unless otherwise noted.

Table 4.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

Mnemonic

Condition

Min

Typ

Max Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

ppm/°C

LINE REGULATION⁴

E Grade

ΔV_O/ΔV_IN

3.0 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 20 mA

10

20

ppm/V

F and G Grades

LOAD REGULATION⁴

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

10

20

ppm/mA

V_S= 3.3 V, I_LOAD= 10 mA

V_S= 3.6 V, I_LOAD= 20 mA

1.25

1.55

V

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF192 @ T_A= 25°C

@ V_S= 3.3 V, T_A= 25°C, unless otherwise noted.

Table 5.

Parameter

INITIAL ACCURACY¹

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade

V_O

I_OUT= 0 mA

2.498

2.495

2.490

2.500

2.502

2.505

2.510

V

LINE REGULATION²

E Grade

ΔV_O/ΔV_IN

3.0 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 30 mA

2

4

8

ppm/V

F and G Grades

LOAD REGULATION²

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

4

6

10

15

ppm/mA

V

V_S= 3.5 V, I_LOAD= 10 mA

V_S= 3.9 V, I_LOAD= 30 mA

1000 hours @ 125°C

0.1 Hz to 10 Hz

1.00

1.40

V

LONG-TERM STABILITY³

NOISE VOLTAGE

DV_O

e_N

1.2

25

mV

μV p-p

¹Initial accuracy includes temperature hysteresis effect.

²Line and load regulation specifications include the effect of self-heating.

³Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

Rev. I | Page 5 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF192 @ −40°C ≤ T_A≤ +85°C

@ V_S= 3.3 V, −40°C ≤ T_A≤ +85°C, unless otherwise noted.

Table 6.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

5

10

25

ppm/°C

LINE REGULATION⁴

E Grade

ΔV_O/ΔV_IN

3.0 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 25 mA

5

10

20

ppm/V

F and G Grades

LOAD REGULATION⁴

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

5

10

15

20

ppm/mA

V_S= 3.5 V, I_LOAD= 10 mA

V_S= 4.0 V, I_LOAD= 25 mA

1.00

1.50

V

SLEEP

Logic High Input Voltage

Logic High Input Current

Logic Low Input Voltage

Logic Low Input Current

SUPPLY CURRENT

V_H

I_H

V_L

I_L

2.4

V

μA

V

μA

−8

0.8

−8

45

15

No load

Sleep Mode

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF192 @ −40°C ≤ T_A≤ +125°C

@ V_S= 3.3 V, −40°C ≤ T_A≤ +125°C, unless otherwise noted.

Table 7.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

ppm/°C

LINE REGULATION⁴

E Grade

ΔV_O/ΔV_IN

3.0 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 20 mA

10

20

ppm/V

F and G Grades

LOAD REGULATION⁴

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

10

20

ppm/mA

V_S= 3.5 V, I_LOAD= 10 mA

V_S= 4.0 V, I_LOAD= 20 mA

1.00

1.50

V

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 6 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF193 @ T_A= 25°C

@ V_S= 3.3 V, T_A= 25°C, unless otherwise noted.

Table 8.

Parameter

Mnemonic

V_O

Condition

Min

Typ

3.0

4

Max

3.010

8

Unit

V

INITIAL ACCURACY¹

G Grade

LINE REGULATION²

G Grade

I_OUT= 0 mA

2.990

ΔV_O/ΔV_IN

3.3 V, ≤ V_S≤ 15 V, I_OUT= 0 mA

ppm/V

LOAD REGULATION²

G Grade

ΔV_O/ΔV_LOAD

V_S− V_O

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 30 mA

V_S= 3.8 V, I_LOAD= 10 mA

V_S= 4.0 V, I_LOAD= 30 mA

1000 hours @ 125°C

6

15

0.80

1.00

ppm/mA

DROPOUT VOLTAGE

V

LONG-TERM STABILITY³

NOISE VOLTAGE

DV_O

e_N

1.2

30

mV

0.1 Hz to 10 Hz

μV p-p

¹Initial accuracy includes temperature hysteresis effect.

²Line and load regulation specifications include the effect of self-heating.

³Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

ELECTRICAL CHARACTERISTICS—REF193 @ −40°C ≤ T_A≤ +85°C

@ V_S= 3.3 V, −40°C ≤ T_A≤ +85°C, unless otherwise noted.

Table 9.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

G Grade³

LINE REGULATION⁴

G Grade

Mnemonic

TCV_O/°C

Condition

Min

Typ

10

Max

25

Unit

I_OUT= 0 mA

ppm/°C

ppm/V

ΔV_O/ΔV_IN

3.3 V ≤ V_S≤ 15 V, I_OUT= 0 mA

10

20

LOAD REGULATION⁴

G Grade

ΔV_O/ΔV_LOAD

V_S− V_O

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 25 mA

V_S= 3.8 V, I_LOAD= 10 mA

V_S= 4.1 V, I_LOAD= 30 mA

10

20

ppm/mA

DROPOUT VOLTAGE

0.80

1.10

V

SLEEP

Logic High Input Voltage

Logic High Input Current

Logic Low Input Voltage

Logic Low Input Current

SUPPLY CURRENT

V_H

I_H

V_L

I_L

2.4

V

μA

V

μA

−8

0.8

−8

45

15

No load

Sleep Mode

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 7 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF193 @ T_A≤ −40°C ≤ +125°C

@ V_S= 3.3 V, –40°C ≤ T_A≤ +125°C, unless otherwise noted.

Table 10.

Parameter

TEMPERATURE COEFFICIENT^{1 ,2}

G Grade³

LINE REGULATION⁴

G Grade

LOAD REGULATION⁴

G Grade

Mnemonic

TCV_O/°C

Condition

Min

Typ Max Unit

I_OUT= 0 mA

10

20

10

ppm/°C

ΔV_O/ΔV_IN

3.3 V ≤ V_S≤ 15 V, I_OUT= 0 mA

ppm/V

ΔV_O/ΔV_LOAD

V_S− V_O

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 20 mA

V_S= 3.8 V, I_LOAD= 10 mA

V_S= 4.1 V, I_LOAD= 20 mA

ppm/mA

DROPOUT VOLTAGE

0.80

1.10

V

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF194 @ T_A= 25°C

@ V_S= 5.0 V, T_A= 25°C, unless otherwise noted.

Table 11.

Parameter

INITIAL ACCURACY¹

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade

V_O

I_OUT= 0 mA

4.498 4.5

4.495

4.490

4.502

4.505

4.510

V

LINE REGULATION²

E Grade

∆V_O/∆V_IN

4.75 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.8 V, 0 mA ≤ I_OUT≤ 30 mA

2

4

8

ppm/V

F and G Grades

LOAD REGULATION²

E Grade

F and G Grades

DROPOUT VOLTAGE

∆V_O/∆V_LOAD

V_S− V_O

2

4

8

ppm/mA

V

V_S= 5.00 V, I_LOAD= 10 mA

V_S= 5.8 V, I_LOAD= 30 mA

1000 hours @ 125°C

0.1 Hz to 10 Hz

0.50

1.30

V

LONG-TERM STABILITY³

NOISE VOLTAGE

DV_O

e_N

2

mV

45

μV p-p

¹Initial accuracy includes temperature hysteresis effect.

²Line and load regulation specifications include the effect of self-heating.

³Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

Rev. I | Page 8 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF194 @ −40°C ≤ T_A≤ +85°C

@ V_S= 5.0 V, −40°C ≤ T_A≤ +85°C, unless otherwise noted.

Table 12.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

5

10

25

ppm/°C

LINE REGULATION⁴

E Grade

∆V_O/∆V_IN

4.75 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.80 V, 0 mA ≤ I_OUT≤ 25 mA

5

10

20

ppm/V

F and G Grades

LOAD REGULATION⁴

E Grade

F and G Grades

DROPOUT VOLTAGE

∆V_O/∆V_LOAD

V_S− V_O

5

10

15

20

ppm/mA

V_S= 5.00 V, I_LOAD= 10 mA

V_S= 5.80 V, I_LOAD= 25 mA

0.5

1.30

V

SLEEP

Logic High Input Voltage

Logic High Input Current

Logic Low Input Voltage

Logic Low Input Current

SUPPLY CURRENT

V_H

I_H

V_L

I_L

2.4

V

μA

V

μA

−8

0.8

−8

45

15

No load

Sleep Mode

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF194 @ −40°C ≤ T_A≤ +125°C

@ V_S= 5.0 V, −40°C ≤ T_A≤ +125°C, unless otherwise noted.

Table 13.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

ppm/°C

LINE REGULATION⁴

E Grade

ΔV_O/ΔV_IN

4.75 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.80 V, 0 mA ≤ I_OUT≤ 20 mA

5

10

ppm/V

F and G Grades

LOAD REGULATION

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

5

10

ppm/mA

V_S= 5.10 V, I_LOAD= 10 mA

V_S= 5.95 V, I_LOAD= 20 mA

0.60

1.45

V

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 9 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF195 @ T_A= 25°C

@ V_S= 5.10 V, T_A= 25°C, unless otherwise noted.

Table 14.

Parameter

Mnemonic

Condition

Min

Typ

Max

Unit

INITIAL ACCURACY¹

E Grade

F Grade

G Grade

V_O

I_OUT= 0 mA

4.998 5.0

4.995

4.990

5.002

5.005

5.010

V

LINE REGULATION²

E Grade

ΔV_O/ΔV_IN

5.10 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 6.30 V, 0 mA ≤ I_OUT≤ 30 mA

2

4

8

ppm/V

F and G Grades

LOAD REGULATION²

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

2

4

8

ppm/mA

V

V_S= 5.50 V, I_LOAD= 10 mA

V_S= 6.30 V, I_LOAD= 30 mA

1000 hours @ 125°C

0.1 Hz to 10 Hz

0.50

1.30

V

LONG-TERM STABILITY³

NOISE VOLTAGE

DV_O

e_N

1.2

50

mV

μV p-p

¹Initial accuracy includes temperature hysteresis effect.

²Line and load regulation specifications include the effect of self-heating.

³Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

ELECTRICAL CHARACTERISTICS—REF195 @ −40°C ≤ T_A≤ +85°C

@ V_S= 5.15 V, −40°C ≤ T_A≤ +85°C, unless otherwise noted.

Table 15.

Parameter

TEMPERATURE COEFFICIENT^1,2

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

5

10

25

ppm/°C

LINE REGULATION⁴

E Grade

ΔV_O/ΔV_IN

5.15 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 6.30 V, 0 mA ≤ I_OUT≤ 25 mA

5

10

20

ppm/V

F and G Grades

LOAD REGULATION⁴

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

5

10

20

ppm/mA

V_S= 5.50 V, I_LOAD= 10 mA

V_S= 6.30 V, I_LOAD= 25 mA

0.50

1.30

V

SLEEP

Logic High Input Voltage

Logic High Input Current

Logic Low Input Voltage

Logic Low Input Current

SUPPLY CURRENT

V_H

I_H

V_L

I_L

2.4

V

μA

V

μA

−8

0.8

−8

45

15

No load

Sleep Mode

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 10 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF195 @ −40°C ≤ T_A≤ +125°C

@ V_S= 5.20 V, −40°C ≤ T_A≤ +125°C, unless otherwise noted.

Table 16.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

ppm/°C

LINE REGULATION⁴

E Grade

ΔV_O/ΔV_IN

5.20 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 6.45 V, 0 mA ≤ I_OUT≤ 20 mA

5

10

ppm/V

F and G Grades

LOAD REGULATION⁴

E Grade

ΔV_O/ΔV_LOAD

5

ppm/mA

F and G Grades

DROPOUT VOLTAGE

10

ppm/mA

V_S= 5.60 V, I_LOAD= 10 mA

V_S= 6.45 V, I_LOAD= 20 mA

0.60

1.45

V

V_S− V_O

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF196 @ T_A= 25°C

@ V_S= 3.5 V, T_A= 25°C, unless otherwise noted.

Table 17.

Parameter

Mnemonic

V_O

Condition

Min

Typ

Max

3.310

8

Unit

V

INITIAL ACCURACY¹

G Grade

LINE REGULATION²

G Grade

LOAD REGULATION²

G Grade

I_OUT= 0 mA

3.290 3.3

ΔV_O/ΔV_IN

3.50 V ≤ V_S≤ 15 V, I_OUT= 0 mA

4

6

ppm/V

ΔV_O/ΔV_LOAD

V_S− V_O

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 30 mA

V_S= 4.1 V, I_LOAD= 10 mA

V_S= 4.3 V, I_LOAD= 30 mA

1000 hours @ 125°C

15

ppm/mA

DROPOUT VOLTAGE

0.80

1.00

V

LONG-TERM STABILITY³

NOISE VOLTAGE

DV_O

e_N

1.2

33

mV

0.1 Hz to 10 Hz

μV p-p

¹Initial accuracy includes temperature hysteresis effect.

²Line and load regulation specifications include the effect of self-heating.

³Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

Rev. I | Page 11 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF196 @ −40°C ≤ T_A≤ +85°C

@ V_S= 3.5 V, –40°C ≤ T_A≤ +85°C, unless otherwise noted.

Table 18.

Parameter

Mnemonic

TCV_O/°C

Condition

Min

Typ

10

Max

25

Unit

TEMPERATURE COEFFICIENT^{1, 2}

G Grade³

LINE REGULATION⁴

G Grade

I_OUT= 0 mA

ppm/°C

ppm/V

ΔV_O/ΔV_IN

3.5 V ≤ V_S≤ 15 V, I_OUT= 0 mA

10

20

LOAD REGULATION⁴

G Grade

ΔV_O/ΔV_LOAD

V_S− V_O

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 25 mA

V_S= 4.1 V, I_LOAD= 10 mA

V_S= 4.3 V, I_LOAD= 25 mA

10

20

ppm/mA

DROPOUT VOLTAGE

0.80

1.00

V

SLEEP

Logic High Input Voltage

Logic High Input Current

Logic Low Input Voltage

Logic Low Input Current

SUPPLY CURRENT

V_H

I_H

V_L

I_L

2.4

V

μA

V

μA

−8

0.8

−8

45

15

No load

Sleep Mode

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

ELECTRICAL CHARACTERISTICS—REF196 @ −40°C ≤ T_A≤ +125°C

@ V_S= 3.50 V, −40°C ≤ T_A≤ +125°C, unless otherwise noted.

Table 19.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

G Grade³

LINE REGULATION⁴

G Grade

Mnemonic

TCV_O/°C

Condition

Min

Typ

10

Max

Unit

I_OUT= 0 mA

ppm/°C

ppm/V

ΔV_O/ΔV_IN

3.50 V ≤ V_S≤ 15 V, I_OUT= 0 mA

20

LOAD REGULATION⁴

G Grade

ΔV_O/ΔV_LOAD

V_S− V_O

V_S= 5.0 V, 0 mA ≤ I_OUT≤ 20 mA

V_S= 4.1 V, I_LOAD= 10 mA

V_S= 4.4 V, I_LOAD= 20 mA

20

ppm/mA

DROPOUT VOLTAGE

0.80

1.10

V

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 12 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF198 @ T_A= 25°C

@ V_S= 5.0 V, T_A= 25°C, unless otherwise noted.

Table 20.

Parameter

INITIAL ACCURACY¹

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade

V_O

I_OUT= 0 mA

4.094

4.091

4.086

4.096

4.098

4.101

4.106

V

LINE REGULATION²

E Grade

ΔV_O/ΔV_IN

4.5 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.4 V, 0 mA ≤ I_OUT≤ 30 mA

2

4

8

ppm/V

F and G Grades

LOAD REGULATION²

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

2

4

8

ppm/mA

V

V_S= 4.6 V, I_LOAD= 10 mA

V_S= 5.4 V, I_LOAD= 30 mA

1000 hours @ 125°C

0.1 Hz to 10 Hz

0.502

1.30

V

LONG-TERM STABILITY³

NOISE VOLTAGE

DV_O

e_N

1.2

40

mV

μV p-p

¹Initial accuracy includes temperature hysteresis effect.

²Line and load regulation specifications include the effect of self-heating.

³Long-term stability specification is noncumulative. The drift in subsequent 1000-hour periods is significantly lower than in the first 1000-hour period.

ELECTRICAL CHARACTERISTICS—REF198 @ −40°C ≤ T_A≤ +85°C

@ V_S= 5.0 V, −40°C ≤ T_A≤ +85°C, unless otherwise noted.

Table 21.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

5

10

25

ppm/°C

LINE REGULATION⁴

E Grade

ΔV_O/ΔV_IN

4.5 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.4 V, 0 mA ≤ I_OUT≤ 25 mA

5

10

20

ppm/V

F and G Grades

LOAD REGULATION⁴

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

5

10

20

ppm/mA

V_S= 4.6 V, I_LOAD= 10 mA

V_S= 5.4 V, I_LOAD= 25 mA

0.502

1.30

V

SLEEP

Logic High Input Voltage

Logic High Input Current

Logic Low Input Voltage

Logic Low Input Current

SUPPLY CURRENT

V_H

I_H

V_L

I_L

2.4

V

μA

V

μA

−8

0.8

−8

45

15

No load

Sleep Mode

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

Rev. I | Page 13 of 28

REF19x Series

ELECTRICAL CHARACTERISTICS—REF198 @ −40°C ≤ T_A≤ +125°C

@ V_S= 5.0 V, −40°C ≤ T_A≤ +125°C, unless otherwise noted.

Table 22.

Parameter

TEMPERATURE COEFFICIENT^{1, 2}

Mnemonic

Condition

Min

Typ

Max

Unit

E Grade

F Grade

G Grade³

TCV_O/°C

I_OUT= 0 mA

2

5

10

ppm/°C

LINE REGULATION⁴

E Grade

ΔV_O/ΔV_IN

4.5 V ≤ V_S≤ 15 V, I_OUT= 0 mA

V_S= 5.6 V, 0 mA ≤ I_OUT≤ 20 mA

5

10

ppm/V

F and G Grades

LOAD REGULATION⁴

E Grade

F and G Grades

DROPOUT VOLTAGE

ΔV_O/ΔV_LOAD

V_S− V_O

5

10

ppm/mA

V_S= 4.7 V, I_LOAD= 10 mA

V_S= 5.6 V, I_LOAD= 20 mA

0.60

1.50

V

¹For proper operation, a 1 μF capacitor is required between the output pin and the GND pin of the device.

²TCV_Ois defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/°C.

TCV_O= (V_MAX− V_MIN)/V_O(T_MAX− T_MIN

)

³Guaranteed by characterization.

⁴Line and load regulation specifications include the effect of self-heating.

WAFER TEST LIMITS

For proper operation, a 1 μF capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer

probe to the limits are shown in

Table 23. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice.

Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

@ I_LOAD= 0 mA, T_A= 25°C, unless otherwise noted.

Table 23.

Parameter

INITIAL ACCURACY

REF191

REF192

REF193

REF194

REF195

REF196

REF198

Mnemonic

Condition

Limit

Unit

V_O

2.043/2.053

2.495/2.505

2.990/3.010

4.495/4.505

4.995/5.005

3.290/3.310

4.091/4.101

15

V

LINE REGULATION

LOAD REGULATION

DROPOUT VOLTAGE

ΔV_O/ΔV_IN

ΔV_O/ΔI_LOAD

V_O− V+

(V_O+ 0.5 V) < V_IN< 15 V, I_OUT= 0 mA

0 mA < I_LOAD< 30 mA, V_IN= (V_O+ 1.3 V)

I_LOAD= 10 mA

ppm/V

15

ppm/mA

1.25

1.55

V

I_LOAD= 30 mA

SLEEP

MODE INPUT

Logic Input High

Logic Input Low

SUPPLY CURRENT

Sleep Mode

V_IH

V_IL

2.4

0.8

45

V

V_IN= 15 V

No load

μA

15

Rev. I | Page 14 of 28

REF19x Series

ABSOLUTE MAXIMUM RATINGS

Table 24.

Parameter¹

Rating

THERMAL RESISTANCE

Supply Voltage

Output to GND

−0.3 V, +18 V

−0.3 V, V_S+ 0.3 V

Indefinite

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Output to GND Short-Circuit Duration

Storage Temperature Range

PDIP, SOIC_N Package

Operating Temperature Range

REF19x

Junction Temperature Range

PDIP, SOIC_N Package

Lead Temperature Range (Soldering 60 sec)

Table 25. Thermal Resistance

Package Type

1

−65°C to +150°C

−40°C to +85°C

Unit

θ_JA

θ_JC

43

8-Lead PDIP

8-Lead SOIC_N

103

158

°C/W

¹θ_JAis specified for worst-case conditions; that is, θ_JAis specified for the device

in socket for PDIP and is specified for the device soldered in the circuit board

for the SOIC package.

−65°C to +150°C

300°C

¹Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted.

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. I | Page 15 of 28

REF19x Series

TYPICAL PERFORMANCE CHARACTERISTICS

5.004

50

45

40

35

30

25

20

15

10

5

3 TYPICAL PARTS

BASED ON 600

UNITS, 4 RUNS

5.15V < V < 15V

IN

5.003

5.002

5.001

5.000

4.999

4.998

4.997

4.996

–40°C ≤ T ≤ +85°C

A

0

20

–50

–25

0

25

50

75

100

15

10

5

0

5

10

15

20

TEMPERATURE (°C)

T

—V

OUT

(ppm/°C)

C

Figure 3. REF195 Output Voltage vs. Temperature

Figure 6. T_C—V_OUTDistribution

32

28

24

20

16

12

8

40

35

30

25

20

15

10

5

5.15V ≤ V ≤ 15V

S

NORMAL MODE

–40°C

+25°C

+85°C

4

SLEEP MODE

0

–50

0

5

10

15

(mA)

20

25

30

–25

0

25

50

75

100

I

TEMPERATURE (°C)

LOAD

Figure 4. REF195 Load Regulator vs. I_LOAD

Figure 7. Supply Current vs. Temperature

20

16

12

8

–6

–5

–4

–3

–2

–1

0

0mA ≤ I

OUT

≤ 25mA

+85°C

+25°C

–40°C

V

L

4

H

0

4

6

8

10

(V)

12

14

16

–50

–25

0

25

50

75

100

V

TEMPERATURE (°C)

IN

Figure 5. REF195 Line Regulator vs. V_IN

SLEEP

Pin Current vs. Temperature

Figure 8.

Rev. I | Page 16 of 28

REF19x Series

REF19x

2

4

V

= 15V

IN

0

–20

6

10mA

0

1µF

Figure 13. Load Transient Response Measurement Circuit

–40

–60

–80

2V

100%

90%

–100

–120

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 9. Ripple Rejection vs. Frequency

1mA

LOAD

30mA

LOAD

10µF

10%

0%

REF19x

10µF

1kΩ

V

= 15V

2

6

OUTPUT

IN

2V

100µs

4

10µF

1µF

REF

Figure 10. Ripple Rejection vs. Frequency Measurement Circuit

Figure 14. Power-On Response Time

REF19x

V

= 7V

200V

IN

REF19x

2

6

2

4

V

= 2V p-p

= 4V

6

G

S

V

= 7V

4

IN

1µF

Z

Figure 15. Power-On Response Time Measurement Circuit

4

3

2

1

0

5V

100%

90%

ON

OFF

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 11. Output Impedance vs. Frequency

I

= 1mA

L

V

OUT

I

= 10mA

L

5V

10%

0%

OFF

ON

100%

90%

2ms

1V

SLEEP

Figure 16.

Response Time

REF19x

= 15V

V

IN

2

V

OUT

6

10%

0%

3

1µF

4

20mV

100µs

Figure 12. Load Transient Response

SLEEP

Response Time Measurement Circuit

Figure 17.

Rev. I | Page 17 of 28

REF19x Series

35

30

25

20

15

10

5

5V

100%

90%

10%

0%

200mV

200µs

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

REF195 DROPOUT VOLTAGE (V)

Figure 18. Line Transient Response

Figure 19. Load Current vs. Dropout Voltage

Rev. I | Page 18 of 28

REF19x Series

APPLICATIONS

OUTPUT SHORT-CIRCUIT BEHAVIOR

SLEEP MODE OPERATION

The REF19x family of devices is completely protected from

damage due to accidental output shorts to GND or to V⁺. In the

event of an accidental short-circuit condition, the reference

device shuts down and limits its supply current to 40 mA.

All REF19x devices include a sleep capability that is

TTL/CMOS-level compatible. Internally, a pull-up current

source to V_INis connected at the

pin. This permits the

SLEEP

pin to be driven from an open collector/drain driver. A

SLEEP

logic low or a 0 V condition on the

V

+

pin is required to

SLEEP

turn off the output stage. During sleep, the output of the

references becomes a high impedance state where its potential

would then be determined by external circuitry. If the sleep

V

OUT

SLEEP

feature is not used, it is recommended that the

connected to V_IN(Pin 2).

pin be

SLEEP (SHUTDOWN)

BASIC VOLTAGE REFERENCE CONNECTIONS

The circuit in Figure 21 illustrates the basic configuration for

the REF19x family of references. Note the 10 μF/0.1 μF bypass

network on the input and the 1 μF/0.1 μF bypass network on

the output. It is recommended that no connections be made to

Pin 1, Pin 5, Pin 7, and Pin 8. If the sleep feature is not required,

Pin 3 should be connected to V_IN.

GND

Figure 20. Simplified Schematic

DEVICE POWER DISSIPATION CONSIDERATIONS

REF19x

The REF19x family of references is capable of delivering load

currents to 30 mA with an input voltage that ranges from

3.3 V to 5 V. When these devices are used in applications with

large input voltages, exercise care to avoid exceeding the

maximum internal power dissipation of these devices.

Exceeding the published specifications for maximum power

dissipation or junction temperature can result in premature

device failure. The following formula should be used to

calculate a device’s maximum junction temperature or

dissipation:

1

2

3

4

8

7

6

5

NC

V

IN

NC

OUTPUT

10µF

0.1µF

SLEEP

+

1µF

TANT

0.1µF

NC

NC = NO CONNECT

Figure 21. Basic Voltage Reference Configuration

MEMBRANE SWITCH-CONTROLLED POWER

SUPPLY

With output load currents in the tens of mA, the REF19x family

of references can operate as a low dropout power supply in

hand-held instrument applications. In the circuit shown in

Figure 22, a membrane on/off switch is used to control the

operation of the reference. During an initial power-on condition,

T_J− T_A

P_D=

θ_JA

In this equation, T_Jand T_Aare the junction and ambient

temperatures, respectively; P_Dis the device power dissipation;

and θ_JAis the device package thermal resistance.

the

pin is held to GND by the 10 kΩ resistor. Recall that

SLEEP

this condition (read: three-state) disables the REF19x output.

SLEEP

OUTPUT VOLTAGE BYPASSING

When the membrane on switch is pressed, the

pin is

momentarily pulled to V_IN, enabling the REF19x output. At this

point, current through the 10 kΩ resistor is reduced, and the

For stable operation, low dropout voltage regulators and

references generally require a bypass capacitor connected from

their V_OUTpins to their GND pins. Although the REF19x family

of references is capable of stable operation with capacitive loads

exceeding 100 μF, a 1 μF capacitor is sufficient to guarantee

rated performance. The addition of a 0.1 μF ceramic capacitor

in parallel with the bypass capacitor improves load current

transient performance. For best line voltage transient

performance, it is recommended that the voltage inputs of these

devices be bypassed with a 10 μF electrolytic capacitor in

parallel with a 0.1 μF ceramic capacitor.

SLEEP

internal current source connected to the

control. Pin 3 assumes and remains at the same potential as V_IN.

When the membrane off switch is pressed, the pin is

pin takes

SLEEP

momentarily connected to GND, which once again disables the

REF19x output.

Rev. I | Page 19 of 28

REF19x Series

REF19x

The requirement for a heat sink on Q1 depends on the maximum

input voltage and short-circuit current. With V_S= 5 V and a 300

mA current limit, the worst-case dissipation of Q1 is 1.5 W, less

than the TO-220 package 2 W limit. However, if smaller TO-39

or TO-5 packaged devices, such as the 2N4033, are used, the

current limit should be reduced to keep maximum dissipation

below the package rating. This is accomplished by simply

raising R4.

1

2

3

4

8

7

6

5

NC

V

IN

NC

1kΩ

5%

OUTPUT

+

1µF

TANT

NC

ON

10kΩ

OFF

NC = NO CONNECT

A tantalum output capacitor is used at C1 for its low equivalent

series resistance (ESR), and the higher value is required for

stability. Capacitor C2 provides input bypassing and can be an

ordinary electrolytic.

Figure 22. Membrane Switch-Controlled Power Supply

CURRENT-BOOSTED REFERENCES WITH

CURRENT LIMITING

While the 30 mA rated output current of the REF19x series is

higher than is typical of other reference ICs, it can be boosted to

higher levels, if desired, with the addition of a simple external

PNP transistor, as shown in Figure 23. Full-time current

limiting is used to protect the pass transistor against shorts.

Shutdown control of the booster stage is an option, and when

used, some cautions are needed. Due to the additional active

devices in the V_Sline to U1, a direct drive to Pin 3 does not

work as with an unbuffered REF19x device. To enable shutdown

control, the connection from U1 to U2 is broken at the X, and

Diode D1 then allows a CMOS control source, V_C, to drive U1

to U3 for on/off operation. Startup from shutdown is not as

clean under heavy load as it is in basic REF19x series, and can

require several milliseconds under load. Nevertheless, it is still

effective and can fully control 150 mA loads. When shutdown

control is used, heavy capacitive loads should be minimized.

+V = 6V

TO 9V

(SEE TEXT)

S

Q1

TIP32A

(SEE TEXT)

OUTPUT TABLE

U1 (V)

R4

2Ω

V

OUT

REF192 2.5

REF193 3.0

REF196 3.3

REF194 4.5

REF195 5.0

R1

1kΩ

Q2

2N3906

C2

100µF

25V

R2

1.5kΩ

+

2

C3

0.1µF

F

U1

+V

3.3V

D1

OUT

S

NEGATIVE PRECISION REFERENCE WITHOUT

PRECISION RESISTORS

3

6

V

C

REF196

(SEE TABLE)

@ 150mA

1N4148

(SEE TEXT

ON SLEEP)

C1

10µF/25V

(TANTALUM)

4

R3

1.82kΩ

+

In many current-output CMOS DAC applications where the

output signal voltage must be the same polarity as the reference

voltage, it is often necessary to reconfigure a current-switching

DAC into a voltage-switching DAC using a 1.25 V reference, an

op amp, and a pair of resistors. Using a current-switching DAC

directly requires an additional operational amplifier at the

output to reinvert the signal. A negative voltage reference is

then desirable, because an additional operational amplifier is

not required for either reinversion (current-switching mode) or

amplification (voltage-switching mode) of the DAC output

voltage. In general, any positive voltage reference can be

converted into a negative voltage reference using an operational

amplifier and a pair of matched resistors in an inverting

configuration. The disadvantage to this approach is that the

largest single source of error in the circuit is the relative

matching of the resistors used.

R1

S

V

OUT

COMMON

F

V

S

COMMON

Figure 23. Boosted 3.3 V Referenced with Current Limiting

In this circuit, the power supply current of reference U1 flowing

through R1 to R2 develops a base drive for Q1, whose collector

provides the bulk of the output current. With a typical gain of

100 in Q1 for 100 mA to 200 mA loads, U1 is never required to

furnish more than a few mA, so this factor minimizes tempera-

ture-related drift. Short-circuit protection is provided by Q2,

which clamps the drive to Q1 at about 300 mA of load current,

with values as shown in Figure 23. With this separation of

control and power functions, dc stability is optimum, allowing

most advantageous use of premium grade REF19x devices for

U1. Of course, load management should still be exercised. A

short, heavy, low dc resistance (DCR) conductor should be used

from U1 to U6 to the V_OUTSense Point S, where the collector of

Q1 connects to the load, Point F.

The circuit illustrated in Figure 24 avoids the need for tightly

matched resistors by using an active integrator circuit. In this

circuit, the output of the voltage reference provides the input

drive for the integrator. To maintain circuit equilibrium, the

integrator adjusts its output to establish the proper relationship

between the reference’s V_OUTand GND. Thus, any desired

negative output voltage can be selected by substituting for the

appropriate reference IC. The sleep feature is maintained in the

circuit with the simple addition of a PNP transistor and a 10 kΩ

resistor.

Because of the current limiting configuration, the dropout

voltage circuit is raised about 1.1 V over that of the REF19x

devices, due to the V_BEof Q1 and the drop across Current Sense

Resistor R4. However, overall dropout is typically still low

enough to allow operation of a 5 V to 3.3 V regulator/reference

using the REF196 for U1 as noted, with a V_Sas low as 4.5 V and

a load current of 150 mA.

Rev. I | Page 20 of 28

REF19x Series

One caveat to this approach is that although rail-to-rail output

amplifiers work best in the application, these operational amplifiers

require a finite amount (mV) of headroom when required to

provide any load current. The choice for the circuit’s negative

supply should take this issue into account.

While this concept is simple, some cautions are needed. Since

the lower reference circuit must sink a small bias current from

U2 (50 μA to 100 μA), plus the base current from the series

PNP output transistor in U2, either the external load of U1 or

R1 must provide a path for this current. If the U1 minimum

load is not well defined, Resistor R1 should be used, set to a

value that conservatively passes 600 μA of current with the

applicable V_OUT1across it. Note that the two U1 and U2

reference circuits are locally treated as macrocells, each having

its own bypasses at input and output for best stability. Both U1

and U2 in this circuit can source dc currents up to their full

rating. The minimum input voltage, V_S, is determined by the

sum of the outputs, V_OUT2, plus the dropout voltage of U2.

V

IN

10kΩ

2N3906

SLEEP

TTL/CMOS

2

V

IN

1µF

1kΩ

3

6

SLEEP V

OUT

+5V

A1

REF19x

GND

4

100Ω

–V

1µF

REF

10kΩ

100kΩ

A related variation on stacking two 3-terminal references is

shown in Figure 26, where U1, a REF192, is stacked with a

2-terminal reference diode, such as the AD589. Like the

3-terminal stacked reference above, this circuit provides two

outputs, VOUT1 and VOUT2, which are the individual terminal

voltages of D1 and U1, respectively. Here this is 1.235 V and 2.5 V,

which provides a V_OUT2of 3.735 V. When using 2-terminal

reference diodes, such as D1, the rated minimum and maximum

device currents must be observed, and the maximum load

current from V_OUT1can be no greater than the current setup by

R1 and V_O(U1). When V_O(U1) is equal to 2.5 V, R1 provides a

500 μA bias to D1, so the maximum load current available at

–5V

A1 = 1/2 OP295,

1/2 OP291

Figure 24. Negative Precision Voltage Reference Uses No Precision Resistors

STACKING REFERENCE ICS FOR

ARBITRARY OUTPUTS

Some applications may require two reference voltage sources

that are a combined sum of standard outputs. The circuit shown

in Figure 25 shows how this stacked output reference can be

implemented.

OUTPUT TABLE

U1/U2

V

(V)

V

(V)

OUT1

OUT2

V

_OUT1is 450 μA or less.

+VS

REF192/REF192 2.5

REF192/REF194 2.5

REF192/REF195 2.5

5.0

7.0

7.5

V

> V

+ 0.15V

S

OUT2

+V

S

V

> V

+ 0.15V

S

OUT2

2

U2

2

C1

0.1µF

3

6

+V

REF19x

OUT2

(SEE TABLE)

U1

REF192

C1

0.1µF

+

3

6

+V

OUT2

3.735V

V

O

(U2)

C2

1µF

4

R1

4.99kΩ

(SEE TEXT)

+

V

(U1)

(D1)

C2

1µF

O

4

2

+V

OUT1

1.235V

U1

C3

1µF

D1

AD589

C3

0.1µF

3

6

O

+V

REF19x

OUT1

R1

3.9kΩ

(SEE TEXT)

(SEE TABLE)

V

+

C4

1µF

IN

COMMON

V

O

(U1)

4

V

OUT

COMMON

V

IN

COMMON

V

OUT

COMMON

Figure 26. Stacking Voltage References with the REF192

Figure 25. Stacking Voltage References with the REF19x

PRECISION CURRENT SOURCE

Two reference ICs are used, fed from a common unregulated

input, V_S. The outputs of the individual ICs are connected in

series, as shown in Figure 25, which provide two output

voltages, V_OUT1and V_OUT2. V_OUT1is the terminal voltage of U1,

while V_OUT2is the sum of this voltage and the terminal voltage

of U2. U1 and U2 are chosen for the two voltages that supply

the required outputs (see Output Table in Figure 25). If, for

example, both U1 and U2 are REF192s, the two outputs are 2.5 V

and 5.0 V.

In low power applications, the need often arises for a precision

current source that can operate on low supply voltages. As shown

in Figure 27, any one of the devices in the REF19x family of

references can be configured as a precision current source.

The circuit configuration illustrated is a floating current source

with a grounded load. The output voltage of the reference is

bootstrapped across R_SET, which sets the output current into the

load. With this configuration, circuit precision is maintained for

load currents in the range from the reference’s supply current

(typically 30 μA) to approximately 30 mA. The low dropout

voltage of these devices maximizes the current source’s output

voltage compliance without excess headroom.

Rev. I | Page 21 of 28

REF19x Series

V

OUTPUT TABLE

IN

*

U1/U2

V

(V)

C

OUT

5.0

LO 3.3

REF195/

REF196

HI

2

V

REF194/

REF195

HI

LO 5.0

4.5

IN

+V = 6V

S

REF19x

2

*

CMOS LOGIC LEVELS

3

6

SLEEP

V

REF

U1

1

2

3

4

1µF

R1

P1

GND

4

3

6

V

C

REF19x

R

SET

(SEE TABLE)

I

SY

ADJUST

U3A

U3B

4

74HC04 74HC04

+V

OUT

I

OUT

V

≥ I

× R (MAX) + V (MIN)

SY

IN

OUT

L

V

R

OUT

L

2

I

=

+ I (REF19x)

SY

OUT

R

+

C2

SET

U2

1µF

3

6

REF19x

V

E.G., REF195: V

= 5V

OUT

= 5mA

OUT

>> I

SY

(SEE TABLE)

I

OUT

R

SET

C1

0.1µF

R1 = 953Ω

P1 = 100Ω, 10-TURN

4

V

IN

COMMON

Figure 27. A Low Dropout, Precision Current Source

V

OUT

COMMON

The governing equations for the circuit are

Figure 28. Switched Output Reference

V_IN= I_OUT× R_L

(

Max

)

+ V_SY

(

Min, REF19x

)

Using dissimilar REF19x series devices with this configuration

allows logic selection between the U1/U2-specified terminal

voltages. For example, with U1 (a REF195) and U2 (a REF196),

as noted in the table in Figure 28, changing the CMOS-

compatible V_Clogic control voltage from HI to LO selects

between a nominal output of 5 V and 3.3 V, and vice versa.

Other REF19x family units can also be used for U1/U2, with

similar operation in a logic sense, but with outputs as per the

individual paired devices (see the table in Figure 28). Of course,

the exact output voltage tolerance, drift, and overall quality of

the reference voltage is consistent with the grade of individual

U1 and U2 devices.

V_OUT

R_SET

I_OUT

=

+ I_SY

(

REF19x

)

V_OUT

R_SET

〉〉 I_SY

(

REF19x

)

SWITCHED OUTPUT 5 V/3.3 V REFERENCE

Applications often require digital control of reference voltages,

selecting between one stable voltage and a second. With the

sleep feature inherent to the REF19x series, switched output

reference configurations are easily implemented with little

additional hardware.

Due to the nature of the wire-OR, one application caveat should

be understood about this circuit. Since U1 and U2 can only

source current effectively, negative going output voltage

changes, which require the sinking of current, necessarily takes

longer than positive going changes. In practice, this means that

the circuit is quite fast when undergoing a transition from 3.3 V

to 5 V, but the transition from 5 V to 3.3 V takes longer. Exactly

how much longer is a function of the load resistance, R_L, seen at

the output and the typical 1 μF value of C2. In general, a

conservative transition time is approximately several milliseconds

for load resistances in the range of 100 Ω to 1 kΩ. Note that for

highest accuracy at the new output voltage, several time

constants should be allowed (>7.6 time constants for <1/2 LSB

error @ 10 bits, for example).

The circuit in Figure 28 illustrates the general technique, which

takes advantage of the output wire-OR capability of the REF19x

device family. When off, a REF19x device is effectively an open

circuit at the output node with respect to the power supply.

When on, a REF19x device can source current up to its current

rating, but sink only a few μA (essentially, just the relatively low

current of the internal output scaling divider). Consequently,

when two devices are wired together at their common outputs,

the output voltage is the same as the output voltage for the on

device. The off state device draws a small standby current of

15 μA (max), but otherwise does not interfere with operation of

the on device, which can operate to its full current rating. Note

that the two devices in the circuit conveniently share both input

and output capacitors, and with CMOS logic drive, it is power

efficient.

KELVIN CONNECTIONS

In many portable applications where the PC board cost and area

go hand-in-hand, circuit interconnects are very often narrow.

These narrow lines can cause large voltage drops if the voltage

reference is required to provide load currents to various

functions. The interconnections of a circuit can exhibit a typical

line resistance of 0.45 mΩ/square (1 oz. Cu, for example).

Rev. I | Page 22 of 28

REF19x Series

In applications where these devices are configured as low

dropout voltage regulators, these wiring voltage drops can

become a large source of error. To circumvent this problem,

force and sense connections can be made to the reference

through the use of an operational amplifier, as shown in Figure 29.

This method provides a means by which the effects of wiring

resistance voltage drops can be eliminated. Load currents flowing

through wiring resistance produce an I-R error (I_LOAD× R_WIRE) at

the load. However, the Kelvin connection overcomes the problem

by including the wiring resistance within the forcing loop of the

op amp. Because the op amp senses the load voltage, op amp

loop control forces the output to compensate for the wiring

error and to produce the correct voltage at the load. Depending

on the reference device chosen, operational amplifiers that can

be used in this application are the OP295, OP292, and OP183.

The circuit in Figure 30 illustrates this concept, which borrows

from the switched output idea of Figure 28, again using the

REF19x device family output wire-OR capability. In this case,

since a constant 5 V reference voltage is desired for all

conditions, two REF195 devices are used for U1 and U2, with

their on/off switching controlled by the presence or absence of

the primary dc supply source, V_S. V_BATis a 6 V battery backup

source that supplies power to the load only when V_Sfails. For

normal (V_Spresent) power conditions, V_BATsees only the 15 μA

(maximum) standby current drain of U1 in its off state.

In operation, it is assumed that for all conditions, either U1 or

U2 is on, and a 5 V reference output is available. With this

voltage constant, a scaled down version is applied to the

Comparator IC U3, providing a fixed 0.5 V input to the negative

input for all power conditions. The R1 to R2 divider provides

a signal to the U3 positive input proportionally to V_S, which

switches U3 and U1/U2, dependent upon the absolute level of

V_S. In Figure 30, Op Amp U3 is configured as a comparator

with hysteresis, which provides clean, noise-free output

switching. This hysteresis is important to eliminate rapid

switching at the threshold due to V_Sripple. Furthermore, the

device chosen is the AD820, a rail-to-rail output device. This

device provides HI and LO output states within a few mV of V_S,

ground for accurate thresholds, and compatible drive for U2 for

all V_Sconditions. R3 provides positive feedback for circuit

hysteresis, changing the threshold at the positive input as

a function of the output of U3.

V

IN

V

IN

R

LW

+V

OUT

SENSE

2

3

V

IN

R

LW

1

+V

OUT

FORCE

A1

3

6

SLEEP

V

OUT

REF19x

GND

4

A1 = 1/2 OP295

1/2 OP292

R

L

1µF 100kΩ

OP183

Figure 29. A Low Dropout, Kelvin-Connected Voltage Reference

FAIL-SAFE 5 V REFERENCE

Some critical applications require a reference voltage to be

maintained at a constant voltage, even with a loss of primary

power. The low standby power of the REF19x series and the

switched output capability allow a fail-safe reference

configuration to be implemented rather easily. This reference

maintains a tight output voltage tolerance for either a primary

power source (ac line derived) or a standby (battery derived)

power source, automatically switching between the two as the

power conditions change.

+V

BAT

2

+V

C2

0.1µF

S

U1

R1

1.1MΩ

3

6

R3

10MΩ

R6

100Ω

REF195

(SEE TABLE)

Q1

5.000V

2N3904

4

C1

3

+

–

0.1µF

7

4

6

U3

AD820

2

+

C3

U2

1µF

3

6

REF195

R2

100kΩ

(SEE TABLE)

R4

4

900kΩ

C4

R5

0.1µF 100kΩ

V , V

BAT

COMMON

S

V

OUT

COMMON

Figure 30. A Fail-Safe 5 V Reference

Rev. I | Page 23 of 28

REF19x Series

100Ω

For V_Slevels lower than the lower threshold, U3 output is low;

thus, U2 and Q1 are off while U1 is on. For V_Slevels higher

than the upper threshold, the situation reverses, with U1 off and

both U2 and Q1 on. In the interest of battery power

conservation, all of the comparison switching circuitry is

powered from V_Sand is arranged so that when V_Sfails, the

default output comes from U1.

REF195

10µF

2

6

+

4

10µF

1µF

57kΩ

1%

0.1µF

4

For the R1 to R3 values, as shown in Figure 30, lower/upper V_S

switching thresholds are approximately 5.5 V and 6 V, respectively.

These can be changed to suit other V_Ssupplies, as can the REF19x

devices used for U1 and U2, over a range of 2.5 V to5 V of output.

U3 can operate down to a V_Sof 3.3 V, which is generally

compatible with all REF19x family devices.

3

+

1/4

OP492

1

2N2222

10kΩ

1%

–

2

11

0.1µF

500Ω

0.1%

LOW POWER, STRAIN GAGE CIRCUIT

10kΩ

1%

0.01µF

As shown in Figure 31, the REF19x family of references can be

used in conjunction with low supply voltage operational amplifiers,

such as the OP492 or the OP283, in a self-contained strain gage

circuit in which the REF195 is used as the core. Other

references can be easily accommodated by changing circuit

element values. The references play a dual role, first as the

voltage regulator to provide the supply voltage requirements of

the strain gage and the operational amplifiers, and second as

a precision voltage reference for the current source used to

stimulate the bridge. A distinct feature of the circuit is that it

can be remotely controlled on or off by digital means via

20kΩ

1%

20kΩ

13

12

–

1/4

OP492

+

10kΩ

1%

14

6

5

–

1/4

OP492

+

7

OUTPUT

2.21kΩ

20kΩ

9

–

1%

1/4

OP492

+

8

20kΩ

1%

10

Figure 31. A Low Power, Strain Gage Circuit

SLEEP

the

pin.

Rev. I | Page 24 of 28

REF19x Series

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

8

1

5

4

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

5.00 (0.1968)

4.80 (0.1890)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

8

1

5

4

0.100 (2.54)

6.20 (0.2440)

5.80 (0.2284)

BSC

4.00 (0.1574)

3.80 (0.1497)

0.060 (1.52)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.210 (5.33)

MAX

0.015

(0.38)

MIN

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)

GAUGE

PLANE

0.50 (0.0196)

45°

1.27 (0.0500)

BSC

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

SEATING

PLANE

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0099)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.25 (0.0098)

0.10 (0.0040)

8°

0°

0.430 (10.92)

MAX

0.005 (0.13)

MIN

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-001

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 32. 8-Lead Plastic Dual In-Line Package [PDIP]

Figure 34. 8-Lead Standard Small Outline Package [SOIC_N]

(N-8)

P-Suffix

Narrow Body

(R-8)

S-Suffix

Dimensions shown in inches and (millimeters)

Dimensions shown in millimeters and (inches)

3.10

3.00

2.90

8

5

4

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65 BSC

0.15

0.05

1.20

MAX

8°

0°

0.75

0.60

0.45

0.30

0.19

SEATING

PLANE

COPLANARITY

0.10

0.20

0.09

COMPLIANT TO JEDEC STANDARDS MO-153-AA

Figure 33. 8-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-8)

Dimensions shown in millimeters

Rev. I | Page 25 of 28

REF19x Series

ORDERING GUIDE

Model

REF191ES

REF191ES-REEL

REF191ESZ¹

REF191ESZ-REEL¹

REF191GP

REF191GPZ¹

REF191GS

Temperature Range

−40°C to +85°C

Package Description

8-Lead SOIC_N

8-Lead PDIP

Package Option

S-Suffix (R-8)

P-Suffix (N-8)

S-Suffix (R-8)

P-Suffix (N-8)

RU-8

Minimum Quantities/Reel

2500

8-Lead PDIP

8-Lead SOIC_N

8-Lead PDIP

REF191GS-REEL

REF191GSZ¹

REF191GSZ-REEL¹

2500

REF192ES

REF192ES-REEL

REF192ES-REEL7

REF192ESZ¹

REF192ESZ-REEL¹

REF192ESZ-REEL7¹

REF192FS

REF192FS-REEL

REF192FS-REEL7

REF192FSZ¹

REF192FSZ-REEL¹

REF192FSZ-REEL7¹

REF192GP

REF192GPZ¹

REF192GRU

REF192GRU-REEL7

REF192GRUZ¹

REF192GRUZ-REEL7¹

REF192GS

REF192GS-REEL

REF192GS-REEL7

REF192GSZ¹

REF192GSZ-REEL¹

REF192GSZ-REEL7¹

REF193GS

2500

1000

2500

1000

2500

1000

2500

1000

8-Lead PDIP

8-Lead TSSOP

8-Lead SOIC_N

8-Lead PDIP

RU-8

1000

S-Suffix (R-8)

P-Suffix (N-8)

S-Suffix (R-8)

2500

1000

2500

1000

REF193GS-REEL

REF193GSZ¹

REF193GSZ-REEL¹

2500

REF194ES

REF194ES-REEL

REF194ESZ¹

REF194ESZ-REEL¹

REF194FS

REF194FSZ¹

REF194GP

REF194GPZ¹

REF194GS

8-Lead PDIP

8-Lead SOIC_N

REF194GS-REEL

REF194GS-REEL7

REF194GSZ¹

2500

1000

REF194GSZ-REEL¹

2500

Rev. I | Page 26 of 28

REF19x Series

Model

Temperature Range

−40°C to +85°C

Package Description

8-Lead SOIC_N

8-Lead PDIP

Package Option

S-Suffix (R-8)

P-Suffix (N-8)

RU-8

S-Suffix (R-8)

RU-8

Minimum Quantities/Reel

REF194GSZ-REEL7¹

1000

REF195ES

REF195ES-REEL

REF195ESZ¹

REF195ESZ-REEL¹

2500

REF195FS

REF195FS-REEL

REF195FSZ¹

REF195FSZ-REEL¹

REF195GP

REF195GPZ¹

8-Lead PDIP

REF195GRU

8-Lead TSSOP

8-Lead SOIC_N

8-Lead TSSOP

8-Lead SOIC_N

8-Lead PDIP

REF195GRU-REEL7

REF195GRUZ¹

REF195GRUZ-REEL7¹

REF195GS

REF195GS-REEL

REF195GS-REEL7

REF195GSZ¹

REF195GSZ-REEL¹

REF195GSZ-REEL7¹

REF196GRU-REEL7

REF196GRUZ-REEL7¹

REF196GS

REF196GS-REEL

REF196GSZ¹

REF196GSZ-REEL¹

REF196GSZ-REEL7¹

REF198ES

REF198ES-REEL

REF198ESZ¹

REF198ESZ-REEL¹

REF198ESZ-REEL7¹

REF198FS

1000

2500

1000

2500

1000

RU-8

S-Suffix (R-8)

P-Suffix (N-8)

RU-8

S-Suffix (R-8)

2500

1000

2500

1000

REF198FS-REEL

REF198FSZ¹

REF198FSZ-REEL¹

REF198GP

REF198GPZ¹

2500

8-Lead PDIP

REF198GRU

8-Lead TSSOP

8-Lead SOIC_N

REF198GRU-REEL7

REF198GRUZ¹

REF198GRUZ-REEL7¹

REF198GS

REF198GS-REEL

REF198GSZ¹

REF198GSZ-REEL¹

1000

2500

¹Z = Pb-free part.

Rev. I | Page 27 of 28

REF19x Series

NOTES

registered trademarks are the property of their respective owners

C00371-0-10/06(I)

Rev. I | Page 28 of 28


型号：	REF198ESZ
厂家：	ADI
描述：	Precision Micropower, Low Dropout Voltage References 精密微功耗，低压差电压基准电源电路参考电压源光电二极管
文件：	总28页 (文件大小：659K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

REF198ESZ [ADI]

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