SMP04GBC [ADI]
CMOS Quad Sample-and-Hold Amplifier; CMOS四路采样和保持放大器
| 型号： | SMP04GBC |
| 厂家： | 
ADI |
| 描述： | CMOS Quad Sample-and-Hold Amplifier |
| 文件： | 总15页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMP04–SPECIFICATIONS
(@ V = +12.0 V, V = DGND = 0 V, R = No Load, T = Operating Temperature Range
ELECTRICAL CHARACTERISTICS
DD
SS
L
A
specified in Absolute Maximum Ratings, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Linearity Error
Buffer Offset Voltage
Hold Step
0.01
±2.5
2.5
%
VOS
VHS
VIN = 6 V
–10
+10
4
5
mV
mV
mV
mV/s
mA
mA
V
VIN = 6 V, TA = +25°C to +85°C
VIN = 6 V, TA = –40°C
VIN = 6 V, TA = +25°C
VIN = 6 V
VIN = 6 V
RL = 20 kΩ
Droop Rate
∆V/∆t
ISOURCE
ISINK
2
25
Output Source Current1
Output Sink Current1
Output Voltage Range
1.2
0.5
0.06
0.06
OVR
10.0
9.5
RL = 10 kΩ
V
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
2.4
V
V
µA
0.8
1
0.5
DYNAMIC PERFORMANCE2
Acquisition Time3
tAQ
TA = +25°C, 0 V to 10 V Step to 0.1%
–40°C ≤ TA ≤ +85°C
TA = +25°C, 0 V to 10 V Step to 0.01%
To 1 mV
RL = 20 kΩ
<30% Overshoot
3.5
3.75
9
1
4
500
–80
4.25
5.25
µs
µs
µs
µs
V/µs
pF
dB
Acquisition Time3
Hold Mode Settling Time
Slew Rate4
Capacitive Load Stability
Analog Crosstalk
tAQ
tH
SR
CL
3
0 V to 10 V Step
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
PSRR
IDD
PDIS
10.8 V ≤ VDD ≤ 13.2 V
60
75
4
dB
mA
mW
7
84
Power Dissipation
(@ V = +5.0 V, V = –5.0 V, DGND = 0.0 V, R = No Load, T = Operating Temperature
Range specified in Absolute Maximum Ratings, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
DD
SS
L
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Linearity Error
Buffer Offset Voltage
Hold Step
0.01
±2.5
2.5
%
VOS
VHS
VIN = 0 V
VIN = 0 V, TA = +25°C to +85°C
VIN = 0 V, TA = –40°C
–10
+10
4
5
mV
mV
mV
mV/s
Ω
mA
mA
V
Droop Rate
∆V/∆t
ROUT
ISOURCE
ISINK
V
IN = 0 V, TA = +25°C
2
1
25
Output Resistance
Output Source Current1
Output Sink Current1
Output Voltage Range
VIN = 0 V
VIN = 0 V
RL = 20 kΩ
1.2
0.5
–3.0
OVR
+3.0
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
2.4
V
V
µA
0.8
1
0.5
DYNAMIC PERFORMANCE2
Acquisition Time3
tAQ
tAQ
tH
SR
CL
–3 V to +3 V Step to 0.1%
–3 V to +3 V Step to 0.01%
To 1 mV
RL = 20 kΩ
<30% Overshoot
3.6
9
1
11
µs
µs
µs
V/µs
pF
Acquisition Time3
Hold Mode Settling Time
Slew Rate5
3
Capacitive Load Stability
500
60
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
PSRR
IDD
PDIS
±5 V ≤ VDD ≤ ±6 V
75
3.5
dB
mA
mW
5.5
55
Power Dissipation
NOTES
1Outputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels.
2All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3This parameter is guaranteed without test.
4Slew rate is measured in the sample mode with a 0 V to 10 V step from 20% to 80%.
5Slew rate is measured in the sample mode with a –3 V to +3 V step from 20% to 80%.
Specifications are subject to change without notice.
REV. D
–2–
SMP04
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C unless otherwise noted)
Package Type
JA*
JC
Units
16-Lead Cerdip
16-Lead Plastic DIP
16-Lead SO
94
76
92
12
33
27
°C/W
°C/W
°C/W
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
DD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V, 17 V
LOGIC to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
V
VIN to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
VOUT to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
(Not Short-Circuit Protected)
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V
Operating Temperature Range
EQ, EP, ES . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C
*JA is specified for worst case mounting conditions, i.e., JA is specified for device
in socket for cerdip and plastic DIP packages; JA is specified for device soldered
to printed circuit board for SO package.
CAUTION
1. Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; function operation
at or above this specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device reliability.
2. Digital inputs and outputs are protected; however, permanent damage may
occur on unprotected units from high energy electrostatic fields. Keep units in
conductive foam or packaging at all times until ready to use. Use proper antistatic
handling procedures.
3. Remove power before inserting or removing units from their sockets.
PIN CONNECTIONS
ORDERING GUIDE
16-Lead Cerdip
16-Lead Plastic DIP
16-Lead SO
Temperature
Range
Package
Description Options*
Package
Model
SMP04EQ
SMP04EP
SMP04ES
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Cerdip-16
PDIP-16
SO-16
Q-16
N-16
R-16A
V
V
V
V
V
V
V
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT2
OUT1
DD
OUT3
OUT4
SS
V
IN1
SMP04
*Q = Cerdip; N = Plastic DIP; R = Small Outline.
NC
TOP VIEW
(Not to Scale)
V
IN2
IN4
S/H
IN3
1
S/H
S/H
S/H
2
4
DGND
3
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP04 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
SMP04
V
V
V
V
V
OUT4
OUT1
OUT2 DD OUT3
V
V
V
V
SS
IN1
IN2
IN4
V
IN3
S/H
1
DGND
S/H
S/H
S/H
4
2
3
Dice Characteristics
Die Size: 0.80 x 0.120 mil = 9,600 sq. mil
(2.032 x 3.048mm = 6.193 sq. mm)
WAFER TEST LIMITS (@ VDD = +12 V, VSS = DGND = 0 V, RL = No Load, TA = +25؇C, unless otherwise noted.)
SMP04G
Limits
Parameter
Symbol
Conditions
Units
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
VOS
VHS
∆V/∆t
ISOURCE
ISINK
OVR
VIN = +6 V
VIN = +6 V
±10
±4
25
1.2
0.5
0.06/10.0
0.06/9.5
mV max
mV max
mV/s max
mA min
mA min
V min/max
V min/max
V
IN = +6 V
VIN = +6 V
VIN = +6 V
RL = 20 kΩ
RL = 10 kΩ
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
2.4
0.8
1
V min
V max
µA max
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
PSRR
IDD
PDIS
10.8 V ≤ VDD ≤ 13.2 V
60
7
84
dB min
mA max
mW max
Power Dissipation
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
REV. D
–4–
Typical Performance Characteristics–SMP04
10000
1000
5
3
1800
V
V
= +12V
= 0V
DD
SS
V
V
V
= +12V
= 0V
= +5V
V
V
= +12V
= 0V
DD
SS
DD
SS
1600
1400
1200
1000
IN
R
= 10k⍀
L
1
0
100
–1
10
0
–3
–5
800
600
–55 –35 –15
5
25 45 65 85 105 125
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE – ؇C
INPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
Figure 1. Droop Rate vs. Temperature
Figure 2. Droop Rate vs. Input
Figure 3. Droop Rate vs. Input
Voltage (TA = +25°C)
Voltage (TA = +125°C)
3
7
3
V
V
V
= +12V
= 0V
= +5V
T
V
V
= +25؇C
DD
A
T
= +25؇C
A
= +12V
SS
DD
V
= 0V
SS
2
1
0
2
1
0
= 0V
IN
SS
6
5
–SR
–1
–2
–3
–1
–2
–3
+SR
4
3
0
1
2
3
4
5
6
7
8
9
10
10
11
12
13 14
15 16
17 18
–55 –35 –15
5
25 45 65 85 105 125
V
– Volts
INPUT VOLTAGE – Volts
DD
TEMPERATURE – ؇C
Figure 4. Hold Step vs. Input Voltage
Figure 5. Hold Step vs. Temperature
Figure 6. Slew Rate vs. VDD
2
20
4
V
V
= +12V
= 0V
DD
SS
V
V
= +12V
= 0V
V
V
= +12V
= 0V
DD
SS
DD
SS
15
10
2
0
1
0
R
=
L
R
=
R
= 20k⍀
L
L
5
0
R
=
L
R
= 20k⍀
–2
–4
–6
L
R
= 20k⍀
–1
–2
L
–5
R
= 10k⍀
L
–10
R
= 10k⍀
L
R
= 10k⍀
–3
–4
L
–8
–15
–20
–10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
INPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
INPUT VOLTAGE – Volts
Figure 7. Offset Voltage vs. Input
Voltage (TA = +25°C)
Figure 8. Offset Voltage vs. Input
Voltage (TA = +125°C)
Figure 9. Offset Voltage vs. Input
Voltage (TA = –55°C)
REV. D
–5–
SMP04
7
6
5
0
90
80
V
= 0V
SS
V
V
V
= +12V
= 0V
= +5V
V
V
V
= +12V
= 0V
= +6V
DD
DD
SS
R
=
L
SS
IN
IN
–1
–2
–3
70
60
50
40
30
20
R
= 10k⍀
L
+125؇C
+PSSR
+25؇C
4
3
2
1
–PSSR
–55؇C
–4
–5
10
0
–55 –33 –15
5
25 45 65 85 105 125
4
6
8
10
12
– Volts
14
16
18
10
100
1k
10k
100k
1M
V
TEMPERATURE – ؇C
DD
FREQUENCY – Hz
Figure 10. Offset Voltage vs.
Temperature
Figure 11. Supply Current vs. VDD
Figure 12. Sample Mode
Power Supply Rejection
15
90
45
0
2
35
30
T
= +25؇C
A
V
V
= +6V
= –6V
DD
SS
1
0
12
9
25
20
15
10
–45
–1
–2
–3
PHASE
–90
6
–135
GAIN
100k
3
0
–180
–225
–4
–5
5
0
10k
100k
1M
10M
10
100
1k
10k
100k
1M
100
1k
10k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 15. Maximum Output Voltage
vs. Frequency
Figure 14. Output Impedance vs.
Frequency
Figure 13. Gain, Phase Shift vs.
Frequency
REV. D
–6–
SMP04
GENERAL INFORMATION
OUTPUT BUFFERS (Pins 1, 2, 14 and 15)
The SMP04 is a quad sample-and-hold with each track-and-
hold having its own input, output, control, and on-chip hold
capacitor. The combination of four high performance track-and-
hold capacitors on a single chip greatly reduces board space and
design time while increasing reliability.
The buffer offset specification is ±10 mV; this is less than 1/2 LSB
of an 8-bit DAC with 10 V full scale. Change in offset over the
output range is typically 3 mV. The hold step is the magnitude
of the voltage step caused when switching from sample-to-hold
mode. This error is sometimes referred to as the pedestal
error or sample-to-hold offset, and is about 2 mV with little
variation. The droop rate of a held channel is 2 µV/ms typical
and ±25 µV/ ms maximum.
After the device selection, the primary considerations in using
track-and-holds are the hold capacitor and layout. The SMP04
eliminates most of these problems by having the hold capacitors
internal, eliminating the problems of leakage, feedthrough,
guard ring layout and dielectric absorption.
The buffers are designed primarily to drive loads connected to
ground. The outputs can source more than 1.2 mA each, over
the full voltage range and maintain specified accuracy. In split
supply operation, symmetrical output swings can be obtained by
restricting the output range to 2 V from either supply.
POWER SUPPLIES
The SMP04 is capable of operating with either single or dual
supplies over a voltage range of 7 to 15 volts. Based on the
supply voltages chosen, VDD and VSS establish the output volt-
age range, which is:
On-chip SMP04 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with capaci-
tive loads up to 500 pF. However, since the SMP04’s buffer
outputs are not short-circuit protected, care should be taken to
avoid shorting any output to the supplies or ground.
V
SS + 0.05 V ≤ VOUT ≤ VDD –2 V
Note that several specifications, including acquisition time,
offset and output voltage compliance will degrade for a total
supply voltage of less than 7 V. Positive supply current is typi-
cally 4 mA with the outputs unloaded. The SMP04 has an inter-
nally regulated TTL supply so that TTL/CMOS compatibility
will be maintained over the full supply range.
SIGNAL INPUT (Pins 3, 5, 11 and 12)
The signal inputs should be driven from a low impedance
voltage source such as the output of an op amp. The op amp
should have a high slew rate and fast settling time if the SMP04’s
fast acquisition time characteristics are to be maintained. As
with all CMOS devices, all input voltages should be kept within
range of the supply rails (VSS ≤ VIN ≤ VDD) to avoid the possibil-
ity of setting up a latch-up condition.
Single Supply Operation Grounding Considerations
In single supply applications, it is extremely important that the
V
SS (negative supply) pin be connected to a clean ground. This
is because the hold capacitor is internally tied to VSS. Any noise
or disturbance in the ground will directly couple to the output of
the sample-and-hold, degrading the signal-to-noise performance.
It is advisable that the analog and digital ground traces on the
circuit board be physically separated to reduce digital switching
noise from entering the analog circuitry.
The internal hold capacitance is typically 60 pF and the internal
switch ON resistance is 2 kΩ.
If single supply operation is desired, op amps such as the OP183
or AD820, that have input and output voltage compliances
including ground, can be used to drive the inputs. Split sup-
plies, such as ±7.5 V, can be used with the SMP04 and the
above mentioned op amps.
Power Supply Bypassing
For optimum performance, the VDD supply pin must also be
bypassed with a good quality, high frequency ceramic capacitor.
The recommended value is 0.1 µF. In the case where dual sup-
plies are used, VSS (negative supply) bypassing is particularly
important. Again this is because the internal hold capacitor is
tied to VSS. Good bypassing prevents high frequency noise from
entering the sample-and-hold amplifier. A 0.1 µF ceramic bypass
capacitor is generally sufficient. For high noise environments,
adding a 10 µF tantalum capacitor in parallel with the 0.1 µF
provides additional protection.
APPLICATION TIPS
All unused digital inputs should be connected to logic LOW
and the analog inputs connected to analog ground. For connec-
tors or driven analog inputs that may become temporarily dis-
connected, a resistor to VSS or analog ground should be used
with a value ranging from 0.2 MΩ to 1 MΩ.
Do not apply signals to the SMP04 with power off unless the
input current’s value is limited to less than 10 mA.
Power Supply Sequencing
Track-and-holds are sensitive to layout and physical connections.
For the best performance, the SMP04 should not be socketed.
It may be advisable to have the VDD turn on prior to having logic
levels on the inputs. The SMP04 has been designed to be resis-
tant to latch-up, but standard precautions should still be taken.
REV. D
–7–
SMP04
FREQUENCY DOMAIN PERFORMANCE
Table III shows the effect of sampling pulsewidth on the SNR of
the SMP04. The recommended operating pulsewidth should be
a minimum of 5 µs to achieve a good balance between acqui-
sition time and SNR for the 1.4 V p-p signal shown. For larger
swings the pulsewidth will need to be larger to account for
the time required for the signal to slew the additional voltage.
This could be used as a method of measuring acquisition
time indirectly.
The SMP04 has been characterized in the frequency domain for
those applications that require capture of dynamic signals. See
Figure 16a for typical 86.1 kHz sample rate and an 8 kHz input
signal. Typically, the SMP04 can sample at rates up to 85 kHz.
In addition to the maximum sample rate, a minimum sample
pulsewidth will also be acceptable for a given design. Our testing
shows a drop in performance as the sample pulsewidth becomes
less than 4 µs.
Table I. SNR vs. VIN
Input
10 dB/DIV
RANGE 15.0 dBm
6.0 dBm
Voltage
(V p-p)
SNR
(dB)
1
2
3
4
5
6
–61
–53
–50
–47
–45
–44
START 1 000.0 Hz
STOP 100 000.0 Hz
Conditions: VS = ±6 V, fS = 14.4 kHz,
fIN = 1.8 kHz, tPW = 10 µs.
a.
10 dB/DIV
RANGE 15.0 dBm
6.3 dBm
Table II. SNR vs. Supply Voltage
Supply
Voltage
(V)
2nd
(dB)
3rd
(dB)
10
12
14
15
16
17
–49
–55
–60
–62
–63
–65
–62
–71
–80
<–80
<–83
<–85
START 1 000.0 Hz
STOP 100 000.0 Hz
b.
Figure 16. Spectral Response at a Sampling Frequency of
86 kHz. Photo (a) Shows a 20 kHz Carrier Frequency and
Photo (b) Shows an 8 kHz Frequency.
Table III. SNR vs. Sample Pulsewidth
Sample
Pulsewidth
(s)
SNR
(dB)
Optimizing Dynamic Performance of the SMP04
Various operating parameters such as input voltage amplitude,
sampling pulsewidth and, as mentioned before, supply bypass-
ing and grounding all have an effect on the signal-to-noise ratio.
Table I shows the SNR versus input level for the SMP04.
1
2
3
4
5
6
7
–37
–44
–50
–54
–54.9
–55
–55.3
Distortion of the SMP04 is reduced by increasing the supply
voltage. This has the effect of increasing the positive slew rate.
Table II shows data taken at 12.3 kHz sample rate and 2 kHz
input frequency. Total harmonic distortion is dominated by the
second and third harmonics.
Conditions: VS = ±6 V, VIN = 1.4 V p-p,
fS = 14.4 kHz, fIN = 1.8 kHz.
REV. D
–8–
SMP04
Sample-Mode Distortion Characteristics
different sampling frequencies of 14.4 kHz, 9.6 kHz and
7.2 kHz. The signal-to-noise ratios measure 58.2 dB, 59.3 dB
and 60 dB respectively.
Although designed as a sample-and-hold, the SMP04 may be
used as a straight buffer amplifier by configuring it in a continu-
ous sample mode. This is done by connecting the S/H control
pin to a logic LOW. Its buffer bandwidth is primarily limited by
the distortion content as the signal frequency increases. Figure
17 shows the distortion characteristics of the SMP04 versus
frequency. It maintains less than 1% total harmonic distortion
over a voiceband of 8 kHz. Output spot noise voltage measures
4 nV/√Hz at f = 1 kHz.
Figure 19 depicts SMP04’s spectral response operating with
voice frequency of 3 kHz sampling at a 15.7 kHz rate. Under
this condition, the signal-to-noise measures 53 dB.
10 dB/DIV
RANGE 15.0 dBm
5.9 dBm
10
V
V
= ؎6V
= 4Vp-p
S
IN
1
0.1
START 1 000.0 Hz
STOP 20 000.0 Hz
Figure 19. SMP04 Spectral Response with an Input Carrier
Frequency of 3 kHz and the Sampling Frequency of 15.7 kHz
0.010
Sampled Data Dynamic Performance
In continuous sampled data applications such as voice digitiza-
tion or communication circuits, it is important to analyze the
spectral response of a sample-and-hold. Figures 16a and 16b
show the SMP04 sampling at a frequency of 86 kHz with a
1.4 V p-p pure sine wave input of 20 kHz and 8 kHz respec-
tively. The photos include the sampling carrier frequency as well
as its multiplying frequencies. In the case of the 20 kHz carrier
frequency, the second harmonic measures 41 dB down from the
fundamental, because the second is dominant, the signal-to-
noise ratio is –40.9 dB. The 8 kHz case produces an improved
S/N performance of –48 dB.
0.001
0.0005
20
100
1k
10k
100k 200k
FREQUENCY – Hz
Figure 17. THD+N vs. Frequency
Sampled Data Dynamic Performance
In continuous sampled data applications such as voice digitiza-
tion or communication circuits, it is important to analyze the
spectral response of a sample-and-hold. Figures 16a and 16b
show the SMP04 sampling at a frequency of 86 kHz with a
1.4 V p-p pure sine wave input of 20 kHz and 8 kHz respec-
tively. The photos include the sampling carrier frequency as
well as its multiplying frequencies. In the case of the 20 kHz
carrier frequency, the second harmonic measures 41 dB down
from the fundamental, because the second is dominant, the
signal-to-noise ratio is –40.9 dB. The 8 kHz case produces an
improved S/N performance of –48 dB.
In the V.32 and V.33 modem environment, where a 1.8 kHz
carrier signal frequency is applied to the SMP04, Figure 18
compares the spectral responses of the SMP04 under three
different sampling frequencies of 14.4 kHz, 9.6 kHz and
7.2 kHz. The signal-to-noise ratios measure 58.2 dB, 59.3 dB
and 60 dB respectively.
In the V.32 and V.33 modem environment, where a 1.8 kHz
carrier signal frequency is applied to the SMP04, Figure 18
compares the spectral responses of the SMP04 under three
10 dB/DIV
RANGE 15.0 dBm
5.9 dBm
10 dB/DIV
RANGE 15.0 dBm
5.7 dBm
10 dB/DIV
RANGE 15.0 dBm
5.2 dBm
CENTER 10 500.0 Hz
SPAN 19 000.0 Hz
START 1 000.0 Hz
STOP 12 000.0 Hz
START 1 000.0 Hz
STOP 12 000.0 Hz
a.
b.
c.
Figure 18. SMP04 Spectral Response with a 1.8 kHz Carrier Frequency. (a) Shows the Sampling Frequency at 14.4 kHz;
it Exhibits a S/N Ratio of 58.2 dB. (b) Shows a 59.3 dB S/N at a Sampling Frequency of 8.6 kHz. (c) Shows a 60 dB S/N at
7.2 kHz.
REV. D
–9–
SMP04
APPLICATIONS
MULTIPLEXED QUAD DAC (Figure 20)
The SMP04 can be used to demultiplex a single DAC converter’s
output into four separate analog outputs. The circuit is greatly
simplified by using a voltage output DAC such as the DAC8228.
To minimize output voltage perturbation, 5 µs should be allowed
to settle to its final voltage before a sample signal is asserted.
Each sample-and-hold amplifier must be refreshed every second
or less in order to assure the droop does not exceed 10 mV or
1/2 LSB.
+12V
1F
+
+5V
REF02
+12V
0.1F
SMP04
V
V
V
V
OUT1
OUT2
OUT3
OUT4
+12V
V
V
V
V
SS
SS
SS
SS
WR
CS
V
V
DD
Z
5V TO 10V
V
1/2 DAC8228
O
V
REF
GND
DIGITAL
INPUTS
S/H
1
2
3
4
S/H
S/H
S/H
ADDRESS
INPUTS
CHANNEL
DECODE
DGND
Figure 20. Multiplexed Quad DAC
REV. D
–10–
SMP04
+5V
–5V
AMPLIFIER A
+5V
R1
20k⍀
V
V
SS
DD
D
1
1N914
D
2
V
OUT
1/2 OP221
–5V
POSITIVE
R2
100⍀
V
IN
(؎3.5V)
V
SS
G
D
S
RESET
Q
1
SD214
PD/H
POSITIVE
1/2 SMP04
AMPLIFIER B
1/2 OP221
R3
20k⍀
D
3
1N914
D
4
V
OUT
NEGATIVE
R4
100⍀
V
SS
G
D
S
Q
2
SD214
PD/H
NEGATIVE
DGND
Figure 21. Positive and Negative Peak Detector with Hold Control
POSITIVE AND NEGATIVE PEAK DETECTOR WITH
HOLD CONTROL (Figure 21)
GAIN OF 10 SAMPLE-AND-HOLD (Figure 22)
This application places the SMP04 in a feedback loop of an
amplifier. Because the SMP04 has no sign inversion and the
amplifier has very high open-loop gain, the gain of the circuit is set
by the ratio of the sum of the source and feedback resistances
In this application the top amplifier (Amplifier A) is the positive
peak detector and the bottom amplifier (Amplifier B) is the
negative peak detector. Operation can be analyzed as follows:
Assume that the S/H switch is closed. As a positive increasing
voltage is applied to VIN, D2 turns on, and D1 turns off, closing
the feedback loop around Amplifier A and the SMP04, causing
the output to track the input. Conversely, in the negative peak
detector circuit at the bottom, D4 turns off and D3 turns on,
holding the last most negative input voltage on the SMP04.
This voltage is buffered to the VO(NEG) output.
8.66k⍀
340⍀
+12V
1N914
+12V
1/4 SMP04
1k⍀
V
OUT
0V TO
10V
1/4 OP490
V
IN
As VIN falls in voltage the above conditions reverse, causing the
most positive peak voltage to be held at VO(POS) output. This
voltage will be held until the input has a more positive voltage
than the previously held peak voltage, or a reset condition is
applied.
100k⍀
0V TO
1.0V
V
SS
S/H
An optional HOLD control can be used by applying a logic HIGH
to the PD/H inputs. This HOLD mode further reduces leakage
current through the reverse-biased diodes (D2 and D4) during
peak hold.
Figure 22. Gain of 10 Sample-and-Hold Amplifier
to the source resistance. When a logic LOW is applied to the
S/H control input, the loop is closed around the OP490,
yielding a gain of 10 (in the example shown) amplifier. When
the S/H control goes HIGH, the loop opens and the SMP04
holds the last sampled voltage. The loop remains open and the
output is unaffected by the input until a logic LOW is reapplied
to the S/H control. The pair of back-to-back diodes from the
output of the op amp to the output of the track-and-hold pre-
vents the op amp from saturating when the track-and-hold is in
the hold mode and the loop is open.
REV. D
–11–
SMP04
+12V
INSTRUMENTATION AMP
+12V
V
V
V
V
1
2
DD
SS
V
(0V TO 8V)
IN
V
1
S/H
0
0
V
= G(V1–V2)
R
V
AMP02
OUT
G
V
V
SS
SS
50k⍀
G =
+1
2
R
G
S/H (DELAYED)
–5V OR –12V
t
1/2 SMP04
d
t
t
2
1
DGND
Figure 23. Time Delta Sample-and-Difference Measurement
SAMPLE AND DIFFERENCE AMPLIFIER (Figure 23)
This circuit uses two sample-and-holds to measure the voltage
difference of a signal between two time points, t1 and t2. The
sampled voltages are fed into the differential inputs of the AMP02
instrumentation amplifier. A single resistor RG sets the gain of
this instrumentation amplifier. Using two channels of the
SMP04 in this application has the advantage of matched
sample-and-hold performance, since they are both on the same
chip.
SINGLE SUPPLY, SAMPLING, INSTRUMENTATION
AMPLIFIER (Figure 24)
This application again uses two channels of the SMP04 and an
instrumentation amplifier to provide a sampled difference signal.
The sample-and-hold signals in this circuit are tied together to
sample at the same point in time. The other two parts of the
SMP04 are used as amplifiers by grounding their control lines
so they are always sampling. One section is used to drive a
guard to the common-mode voltage and the other to generate a
+6 V reference to serve as an offset for single supply operation.
GUARD
+12V
1/4
50k⍀
+1
GAIN =
+ INPUT
SMP04
R
G
0.1F
50k⍀
50k⍀
AMP02
R
S/H
G
REFERENCE
GUARD
1/4
SMP04
V
– INPUT
OUT
+12V
20k⍀
+6V REFERENCE
1/4
SMP04
+12V
0.01F
20k⍀
GUARD
DRIVE
1/4
SMP04
Figure 24. +12 V Single Supply Sampling Instrumentation Amplifier with Guard Drive
REV. D
–12–
SMP04
+15V
0.1F
V
OUT
A
REF
+5V
V
1
DD
0.1F–1F CERAMIC
A
0
V
IN
DAC C
OUT
V
1/4 DAC8426
OUT
DB
DB
MSB
LSB
9
DB –DB
2
9
S/H
10-BIT
2
COUNTER
V
AGND DGND
SS
WR
1/4 SMP04
DGND
V
V
SS
DD
ANALOG
RETURN
1F
DIGITAL
RETURN
AGND
+15V
CLOCK
GENERATOR
DB
0
DB
1
1/4 AD7432
1/4 AD7400
DEGLITCH LOGIC
Figure 25. DAC Deglitcher
D/A CONVERTER DEGLITCHER
Most D/A converters output an appreciable amount of glitch
energy during a transition from one code to another. The glitch
amplitude can range from several millivolts to hundreds of milli-
volts. This may become unacceptable in many applications. By
selectively delaying the DAC’s output transition, the SMP04
can be used to smooth the output waveform. Figure 25 shows
the schematic diagram of such a deglitcher circuit. Two simple
logic gates (an OR and a NAND gate) provide the proper timing
sequence for the DAC WR strobe and the S/H control signal to
the SMP04. In this example a linear ramp signal is generated by
feeding the most significant eight bits of the 10-bit binary
counter to the DAC. The two least significant bits are used to
produce the delayed WR strobe and the S/H control signals.
Referring to Figure 26a, new data to the DAC input is set up at
the S/H’s falling edge, but the DAC output does not change
until a WR strobe goes active. During this period, the SMP04 is
in a sample mode whose output tracks the DAC output. When
S/H goes HIGH, the current DAC output voltage is held by the
SMP04. After 1.2 µs settling, the WR strobe goes LOW to allow
the DAC output to change. Any glitch that occurs at the DAC
output is effectively blocked by the SMP04. As soon as the WR
strobe goes HIGH, the digital data is latched; at the same time
the S/H goes LOW, allowing the SMP04 to track to the new
DAC output voltage.
DB
0
DB
1
WR
5V
1s
S/H
a.
DLY
s
627.4
50m
1s
Figure 26b shows the deglitching operation. The top trace
shows the DAC output during a transition, while the bottom
trace shows the deglitched output of the SMP04.
b.
Figure 26. (a) Shows the Logic Timing of the Deglitcher.
The Top Two Traces Are the Two Least Significant Bits,
DB0 and DB1, Respectively. These Are Used to Generate
the WR and S/H Signals Which Are Shown in the Bottom
Two Traces. (b) Shows the Typical Glitch Amplitude of a
DAC (Top Trace) and the Deglitched Output of the AMP04
(Bottom Trace).
REV. D
–13–
SMP04
V
DD
V
OUT
N-CH
P-CH
V
IN
LOAD
V
C
H
DD
S/H
LOGIC
V
SS
DGND
V
SS
Figure 27. Simplified Schematic of One Channel
V
DD
+15V
R3
4k⍀
R4
1k⍀
D
1
C1
10F
+
R1
10⍀
C2
1F
1
2
3
16
15
14
13
12
SMP04
5
6
7
8
R2
R2
R2
R2
11
10
9
10k⍀ 10k⍀
10k⍀ 10k⍀
Figure 28. Burn-In Circuit
REV. D
–14–
SMP04
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Cerdip
(Q-16)
0.005 (0.13) MIN
0.080 (2.03) MAX
9
16
0.310 (7.87)
0.220 (5.59)
1
8
0.320 (8.13)
0.290 (7.37)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.840 (21.34) MAX
0.200 (5.08)
MAX
0.150
(3.81)
MIN
SEATING
PLANE
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
15°
0°
16-Lead Plastic DIP
(N-16)
0.840 (21.34)
0.745 (18.92)
16
1
9
8
0.280 (7.11)
0.240 (6.10)
0.325 (8.26)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
16-Lead SO
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
16
9
8
0.1574 (4.00)
0.2440 (6.20)
0.2284 (5.80)
1
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0098 (0.25)
0.0040 (0.10)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. D
–15–
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