SSM2163S [ADI]
Digitally Controlled 8 x 2 Audio Mixer; 数字控制的8× 2音频混合器
| 型号： | SSM2163S |
| 厂家： | 
ADI |
| 描述： | Digitally Controlled 8 x 2 Audio Mixer |
| 文件： | 总16页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Digitally Controlled
8
؋
2 Audio Mixer a
SSM2163
FEATURES
SIMP LIFIED BLO CK D IAGRAM
Each of 8 Inputs Can Be Assigned to Either or Both
Outputs
Voltage Inputs and Outputs – No Need For External
Am plifiers
Each Input Provides 63 dB of Attenuation in 1 dB Steps,
Plus Mute
–82 dBu Signal-to-Noise Ratio (0 dBu = 0.775 V rm s)
+10 dBu of Headroom
0.007% THD+N (Unity Gain, @ 1 kHz, 0 dBu)
Pow er-Up/ System Mute Feature
Industry-Standard 3-Wire Serial Interface
Data Out Term inal Perm its Daisy Chaining of Multiple
SSM2163s
DCA
DCA
DCA
DCA
DCA
DCA
DCA
DCA
V
V
V
V
V
V
V
V
IN1
IN2
IN3
IN4
IN5
SSM2163
V
CC
VOLTAGE
REFERENCE
GENERATOR
V
EE
ACOM
AGND
V
OUTL
Single or Dual Supply Operation
28-Pin Plastic DIP and SOIC Package
OUTPUT
SWITCHING
NETWORK
V
OUTR
APPLICATIONS
Multim edia System Mixing
Audio Mixing Consoles
Broadcast Equipm ent
Intercom / Paging System s
Musical Instrum ents
SYSTEM MUTE
DATA OUT
6
IN
IN
CLK
DATA
LD
SHIFT
REGISTER
AND
ADDRESS
DECODER
7
WRITE
DGND
V
DD
IN8
V
SS
GENERAL D ESCRIP TIO N
T he SSM2163 provides eight audio inputs, each of which can
be mixed under digital control to a stereo output. Each input
channel can be attenuated up to 63 dB in 1 dB intervals, plus
fully muted. Additionally, any input can be assigned to either or
both outputs. A standard 3-wire serial interface is employed,
plus a Data Out terminal to facilitate daisy chaining of multiple
mixer ICs. No external components are required for normal
operation.
DCA: DIGITALLY CONTROLLED ATTENUATOR
T he SSM2163 can be operated from single (+5 V to +14 V) or
dual (±4 V to ±7 V) supplies, and is housed in 28-pin plastic
DIP and SOIC packages.
Excellent audio performance is attained. T he SSM2163 has a
signal-to-noise ratio of –82 dBu (0 dBu = 0.775 V rms), with
10 dBu of headroom resulting in total dynamic range of 92 dBu.
T otal harmonic distortion plus noise is 0.007% at 1 kHz with all
levels set at unity gain.
T he SSM2163 is an ideal companion product to the Analog
Devices family of stereo codecs in high performance multi-
media systems requiring mixing of multiple signals.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
SSM2163–SPECIFICATIONS
AUDIO = 1 kHz, fCLK = 250 kHz, R = 100 k⍀,
ELECTRICAL SPECIFICATIONS (V = ؎5 V, A = 0 dB, V = 0 dBu = 0.775 V rms, f
–40؇C < T < +85؇C, unless otherwise noted. Typical specifications apply at T = +25؇C.)
S
V
IN
L
A
A
P aram eter
Conditions
Min
Typ
Max
Units
AUDIO PERFORMANCE
Noise
Headroom
VIN = GND, 20 kHz Bandwidth
Clip Point = 1% T HD+N
–82
+10
dBu
dBu
T otal Harmonic Distortion Plus Noise
2nd and 3rd Harmonics Only
A
A
V = 0 dB
V = –20 dB
0.007
0.02
0.035
0.03
15
%
%
%
AV = 0 dB, VS = +5 V, Single Supply
ANALOG INPUT
Input Impedance
7
10
kΩ
VOLUME CONT ROL
Step Size
1.0
dB
Gain Error
Relative to Same Channel
0 dB Attenuation
0.1
0.1
1.0
dB
dB
–20 dB Attenuation
–40 dB Attenuation
Channel-to-Channel; Same Level Setting
0 dB Attenuation
–20 dB Attenuation
–40 dB
0.25
Gain Match Error
0.01
0.05
0.4
dB
dB
dB
dB
Mute Attenuation
64
ANALOG OUT PUT
Output Impedance
Output Current
Minimum Resistive Load
Maximum Capacitive Drive
Offset Voltage
15
500
4
5000
50
Ω
µA
kΩ
pF
mV
T HD = 1%
Channel Muted
CONT ROL SECT ION
Logic Input LO
Logic Input HI
Logic Input Current
Logic Out LO
Logic Out HI
0.8
0.4
V
V
µA
V
V
2.0
2.4
Logic LO or HI
IOUT = 0.2 mA
IOUT = 0.2 mA
1
T iming Characteristics
See T iming Diagram
REFERENCE (ACOM)
Output Voltage
Output Impedance
Load Regulation
VS = +10 V (Single Supply)
4.7
5.0
10
0.2
5.3
V
Ω
%
–0.5 mA ≤ IL ≤ +0.5 mA (Single Supply)
POWER SUPPLIES
Supply Voltage Range
Dual Supply
±4
±7
V
Single Supply
VS = +10 V (Single Supply)
Delta Gain
+5
+14
15
V
mA
dB/V
Supply Current
Power Supply Rejection Ratio
8
0.005
Specifications subject to change without notice.
REV. 0
–2–
SSM2163
Tim ing D escr iption
Tim ing
Sym bol
D escription
Min
Typ
Max Units
tCL
tCH
tDS
tDH
tCW
tWC
tLW
tWL
tL
Input Clock Pulse Width
Input Clock Pulse Width
Data Setup T ime
50
50
25
35
25
35
20
20
250
250
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold T ime
Positive CLK Edge to End of Write
Write to Clock Setup T ime
End of Load Pulse to Next Write
End of Write to Start of Load
Load Pulse Width
tW3
tPD
Load Pulse Width (3-Wire Mode)
Propagation Delay from Rising
Clock to SDO T ransition
80
160
ns
(RL = 220 kΩ, CL = 20 pF)
NOT ES
1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the positive
edge.
2. For SPI or microwire three-wire bus operation, tie LD to WRITE and use WRITE pulse to drive
both pins. (T his generates an automatic internal LD signal.)
3. If an idle HI clock is used, tCW and tWL are measured from the final negative transition to the idle
state.
4. T he first data byte selects an address (MSB HI), and subsequent MSB LO states set gain levels. Re-
fer to the Address/Data Decoding T ruth T able.
5. Data must be sent MSB first.
1
CLK
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
DATA
WRITE & LOAD
0
tCL
tCH
1
0
CLK
tDH
tDS
1
0
DATA
tCW
tW3
tWC
1
0
WRITE & LOAD
tPD
1
0
SDO
Figure 1. Three-Wire Mode Tim ing Diagram
REV. 0
–3–
SSM2163
1
0
CLK
1
0
1
DATA
WRITE
LD
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
tCL
tCH
1
CLK
0
tDH
tDS
1
DATA
0
tCW
tWC
1
WRITE
0
tWL
tLW
tL
1
LOAD
0
tPD
1
SDO
0
Figure 2. Four-Wire Mode Tim ing Diagram
REV. 0
–4–
SSM2163
P IN CO NFIGURATIO NS
ABSO LUTE MAXIMUM RATINGS1
Epoxy P lastic D IP (P -Suffix)
and SO IC (S-Suffix)
Supply Voltage
Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8 V
Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Operating T emperature Range . . . . . . . . . . . . –40°C to +85°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction T emperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C
Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
SYSTEM MUTE
DATA IN
DGND
1
2
28
27
V
SS
3
26 CLK
25
DATA OUT
V
4
WRITE
DD
V
5
24 LD
IN1
SSM2163
TOP VIEW
6
NC (SHIELD)
23 NC (SHIELD)
(Not to Scale)
V
7
V
22
IN3
IN2
8
NC (SHIELD)
21 NC (SHIELD)
V
9
20
V
TH ERMAL CH ARACTERISTICS
IN5
IN4
T hermal Resistance2
V
10
11
12
13
14
19
18
17
16
15
NC (SHIELD)
CC
V
V
28-Pin Plastic DIP (SSM2163P)
IN7
IN6
V
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22°C/W
28-Pin SOIC (SSM2163S)
AGND
EE
ACOM
V
IN8
V
V
OUTL
OUTR
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20°C/W
TRANSISTO R CO UNT
Number of T ransistors . . . . . . . . . . . . . . . . . . 1711 MOSFET s
447 BJT s
ESD RATINGS
883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 1000 V
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
2θJA is specified for worst-case conditions, i.e., θJA is specified for device in socket
for P-DIP and device soldered in circuit board for SOIC package.
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
SSM2163P
SSM2163S
–40°C to +85°C
–40°C to +85°C
Plastic DIP
SOIC
N-28
R-28
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2163 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
SSM2163
P IN D ESCRIP TIO N
P in #
Mnem onic
Function
1
2
3
DGND
VSS
Digital Ground.
Digital Negative Supply.
DAT A OUT
Serial data output clocked on positive clock edge. Connect DAT A OUT to DAT A IN pin to
daisy-chain multiple SSM2163s. Output levels are VDD to DGND.
4
VDD
Digital Positive Supply.
5
VIN1
Audio Signal Input 1.
6
NC (Shield)
VIN3
Shield Pin. Should be tied to AGND to minimize crosstalk.
Audio Signal Input 3.
7
8
NC (Shield)
VIN5
Shield Pin. Should be tied to AGND to minimize crosstalk.
Audio Signal Input 5.
9
10
11
12
13
VCC
Analog Positive Supply.
VIN7
Audio Signal Input 7.
VEE
Analog Negative Supply.
ACOM
Analog Common Voltage. Provides a buffered voltage output halfway between VCC and VEE for use
as a pseudo ground in single supply applications.
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VOUT L
Left Audio Output.
VOUT R
Right Audio Output.
VIN8
Audio Signal Input 8.
AGND
VIN6
Analog Ground.
Audio Signal Input 6.
NC (Shield)
VIN4
Shield Pin. Should be tied to AGND to minimize crosstalk.
Audio Signal Input 4.
NC (Shield)
VIN2
Shield Pin. Should be tied to AGND to minimize crosstalk.
Audio Signal Input 2.
NC (Shield)
LD
Shield Pin. Should be tied to AGND to minimize crosstalk.
Load Data.
WRITE
CLK
Write Data.
Clock.
Data In
SYST EM MUT E
Serial Data Input. Clocked on positive clock edge.
Mutes all eight input channels thus left and right audio output are muted. System mute does not
change the state of internal latches. All digital data remains intact after system mute is applied.
Logic One: Mutes Output
Logic Zero: Normal Operation
MSB
LSB MSB
LSB
ADDRESS MODE
DATA MODE
DATA
DATA
ATTENUATION
0dB
SELECTION
ADDRESS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
INPUT CHANNEL 1
INPUT CHANNEL 2
INPUT CHANNEL 3
INPUT CHANNEL 4
INPUT CHANNEL 5
INPUT CHANNEL 6
INPUT CHANNEL 7
INPUT CHANNEL 8
X
X
X
X
X
X
X
X
–1dB
0
R
L
E
F
T
0
0
1
1
1
1
–2dB
I
G
H
T
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
–61dB
–62dB
–63dB
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
OUTPUT SELECT
1 = SELECTED, 0 = NOT SELECTED
INPUT SELECT
X = “DON’T CARE," SHADED AREA IS DATA
Figure 3. Address and Data Decoding Truth Table
REV. 0
–6–
SSM2163
20.000
1400
1050
700
350
0
V
T
= ±5V
= +25°C
10.000
0.0
S
A
A
= 0dB
V
–10.00
–20.00
–30.00
A
= –20dB
= –40dB
V
–40.00
–50.00
–60.00
A
V
V
= ±5V
S
LPF = 22kHz
R
= 100kΩ
L
T
= +25°C
A
–70.00
–80.00
0.0
0.002
0.004
0.006
0.008
0.010
0.012
100
20
10k
1k
FREQUENCY – Hz
20k
THD – %
Figure 4. Frequency Response
Figure 6. THD Distribution
1
0
A
= 0dB
V
–10
FREQ = 1kHz
LPF = 22kHz
V
V
= ±5V
S
–20
–30
= 0dBu
= 0dB
IN
A
R
T
= 100kΩ
= +25°C
L
V
–40
Notch F = 1kHz
0.1
A
R
= 100kΩ
L
–50
T
= +25°C
A
–60
–70
V
= ±5V
S
–80
–90
0.010
0.001
V
= ±7V
S
–100
–110
–120
–130
–140
0.1
1
AMPLITUDE – V rms
5
0
2
4
6
8
10 12
14 16
18 20
22 24
FREQUENCY – kHz
Figure 7. (THD+N) = 1 kHz Tone at 0 dBu (4k-Point FFT)
Figure 5. THD+N vs. Am plitude
REV. 0
–7–
SSM2163
1
1
A
= 0dB
V
V
V
= ±5V
S
FREQ = 1kHz
LPF = 22kHz
= 0dBu
= 0dB
IN
A
V
R
= 100kΩ
L
LPF = 22kHz
R
T
= +25°C
A
= 100kΩ
0.1
L
0.1
V
= 4.5V
S
T
= +25°C
A
V
= 5V
S
V
= 5.5V
S
0.010
0.010
0.001
0.001
20
100
1k
10k
20k
1
0.1
5
AMPLITUDE – V rms
FREQUENCY – Hz
Figure 11. THD+N vs. Am plitude – Single Supply
Figure 8. THD+N vs. Frequency
1
V
= 0dBu
= 0dB
IN
A
V
LPF = 22kHz
V
= 4.5V
S
R
= 100kΩ
V
= 5V
L
S
V
= ±5V
S
T
= +25°C
A
A
= 1
100
V
0.1
90 NO LOAD
V
= 7V
S
T
= +25°C
A
V
= 10V
= 12V
S
0.010
V
S
10
0%
0.001
0.005
50mV
10µS
100
1k
FREQUENCY – Hz
10k
20k
20
Figure 9. THD+N vs. Frequency – Single Supply
Figure 12. Sm all Signal Transient Response
1
A
= 0dB
V
FREQ = 1kHz
LPF = 22kHz
V = ±5V
S
R
= 100kΩ
L
V
= 5V
S
A
C
= 1
V
L
T
= +25°C
A
100
90
= 10,000pF
= +25°C
0.1
T
A
V
= 14V
S
0.010
0.001
10
0%
50mV
10µS
0.1
1
AMPLITUDE – V rms
5
Figure 10. THD+N vs. Am plitude – Single Supply
Figure 13. Sm all Signal Transient Response
REV. 0
–8–
SSM2163
V
T
A
V
= ±5V
50mS
S
= +25°C
= 100
V
= ±5V
A
S
100
90
NO LOAD
= +25°C
100
90
T
A
10
10
0%
0%
1V
20mV
1µS
Figure 14. Large Signal Transient Response
Figure 17. Broadband Noise
0.0
V
V
= ±5V
S
–10.00
–20.00
–30.00
–40.00
–50.00
= CHANNEL 1 0dBu
= 0dB
IN
A
V
100
90
LPF = 22kHz
R
T
= 100kΩ
= +25°C
L
V
= ±5V
S
A
NO LOAD
T
= +25°C
A
RIGHT OUTPUT WITH V STEERED FULL LEFT
IN
10
–60.00
–70.00
–80.00
LEFT OUTPUT WITH V STEERED FULL RIGHT
IN
0%
1V
1µS
100
1k
20
10k
20k
FREQUENCY – Hz
Figure 15. Large Signal Transient Response
Figure 18. Output Channel Separation vs. Frequency
0.0
30
25
V
= ±5V
S
–10.00
–20.00
–30.00
–40.00
–50.00
–60.00
–70.00
–80.00
–90.00
–100.00
LPF = 22kHz
R
= 100kΩ
L
T
= +25°C
= 100kΩ
A
T
= +25°C
A
R
L
20
15
10
5
ISY+
ISY–
0
4
4.5
5
5.5
6
6.5
7
100
20
10k
1k
20k
SUPPLY VOLTAGE – ±V
FREQUENCY – Hz
Figure 16. Noise Am plitude vs. Frequency
Figure 19. Supply Current vs. Supply Voltage
REV. 0
–9–
SSM2163
TH EO RY O F O P ERATIO N
TO ATTENUATOR
SWITCHES
TO MIXER
SWITCHES
T he SSM2163 is an eight-input, two-output audio mixer and
attenuator. T he device provides eight analog inputs, each of
which can be individually attenuated by 0 dB to 63 dB in 1 dB
steps (see the SSM2163 simplified block diagram). T he eight
signals can then be mixed into one or both of two analog
outputs. T he channel attenuation level and mixer functions
are controlled by digital registers, which are loaded via a
serial interface. A hardware mute input is included to
asynchronously force all inputs into the muted state.
ATTENUATOR
LEVEL
DATA
LATCHES
LEFT/RIGHT
CHANNEL
CONTROL
LATCHES
(2 BITS)
(6 BITS)
CLK
MUTE
INPUT
RESET
CLK
LOAD
Analog Section
T he analog signal path is shown in Figure 20. Each analog input
has a nominal impedance of 10 kΩ. Each input therefore
appears as a digitally programmable 10 kΩ potentiometer. T he
SSM2163 input impedance remains constant as the attenuation
level changes. T herefore, the sources which drive the SSM2163
do not have to drive complex and variable impedances.
DATA IN
CLK
DATA
INPUT SHIFT REGISTER
SERIAL DATA
OUTPUT
CLOCK
WRITE
T he attenuated analog input is applied to the left and right
channel inputs of the mixer. Each mixer channel consists of an
analog switch and a buffer amplifier. If the channel is selected
(via the appropriate bit in the mixer control register), the analog
switch is turned on. T he buffer amplifier is included after the
analog switch so that the gain of each channel will not be
affected by the potentiometer setting or by the on-resistance
(RDS(ON)) of the switch.
Figure 21. SSM2163 Serial Data Interface Block Diagram
T o access the SSM2163, the host controller (typically a micro-
computer) writes a value to the serial shift register which selects
the appropriate input channel register for subsequent attenuator-
load operations. T his write operation also controls the left and
right mixer switches. T he next write operation then loads the
6-bit attenuator level into the appropriate register. If a series of
values are going to be written to the same address, for instance
when fading a channel, then only one write operation to the
address register is required.
Each mixer channel which is ON is then summed into its
respective (Left or Right) mixer summing amplifier. (If both of
the mixer channels are ON, then the attenuated analog input
will be applied to both the Left and Right summing amplifiers.)
T he buffered output of the summing amplifier will supply
±500 µA to an external load.
Ser ial D ata Contr ol Inputs
T he SSM2163 provides a simple 3- or 4-wire serial interface
(Figures 22 and 23). Data is input on the DAT A IN pin, while
CLK is the serial clock. Data can be shifted into the SSM2163
clock rates up to 1 MHz.
MIXER
BUFFER AMP
OUTPUT
BUFFER
SUMMING
AMPLIFIER
T he shift register clock, CLK, is enabled when the WRIT E
input is low. T he WRIT E pin can therefore be used as a chip
select input. However, the shift register contents are not
transferred to the register banks until the rising edge of LOAD.
In most cases, WRIT E and LOAD will be tied together, forming
a traditional 3-wire serial interface. See the Microcomputer
Interfaces section of this data sheet for more information.
ATTENUATOR
MIXER
V
IN1
SWITCH
V
OUTL
K = 1
R1
R2
AGND
CH1L
SELECT
V
K = 1
T o enable a data transfer, the WRIT E and LOAD inputs are
driven low. T he 8-bit serial data, formatted MSB first, is input
on the DAT A IN input and clocked into the shift register on the
rising edge of CLK. T he data is latched on the rising edge of
WRIT E and LOAD. If the data is an address, then the mixer
control is updated. If the data is an attenuator value the rising
edge of WRIT E and LOAD will update the appropriate
attenuator value.
OUTR
TO INPUTS
AGND
V
– V
IN8
IN2
CH1R
SELECT
R63
1 OF 63
DECODER
AGND
ATTENTION VALUE
FROM DATA REGISTER
MUTE Input
T he MUT E pin provides a hardware input to force all the
SSM2163 channels into the muted state. T he MUT E input is
active HIGH. Most µC I/O pins are in a high impedance state or
configured as inputs at power-up, so the SSM2163 will
automatically be muted at power-up. A 10 kΩ resistor to +5 V is
recommended, to ensure that MUT E is pulled high reliably.
T he MUT E input can also be driven from a µC’s RESET signal
to force a power-on mute.
NOTE: ONLY ONE OF EIGHT CHANNELS
SHOWN FOR CLARITY
Figure 20. SSM2163 Analog Signal Path
D igital Inter face
T he digital interface consists of two banks of 8 data registers
with a serial interface (Figure 21). One register bank holds the
left/right mixer control bits, while the other register bank holds
the 6-bit attenuator value.
In addition to power-on, the MUT E input can be used to
asynchronously mute all channels at any time. T he mute
function of the SSM2163 does not affect the attenuator values
REV. 0
–10–
SSM2163
SSM2163 power supply connections
4
4
4
V
V
DD
V
VDD
DD
10
10
10
V
CC
V+
VCC
V+
0.1µF
V+
CC
+
10µF
+
0.1µF
10µF
+
0.1µF
10µF
17
17
17
AGND
ACOM
AGND
AGND
ACOM
EXTERNAL
REFERENCE
(NC)
2
(NC)
2
13
2
VREF
OUT
ACOM
VSS
V
V
SS
SS
+
0.1µF
10µF
12
1
12
12
V
V
VEE
V–
EE
EE
10µF
0.1µF
+
1
1
DGND
DGND
DGND
Figure 22c. Single Supply Using External
Reference
Figure 22a. Dual Supply
Figure 22b. Single Supply
stored in the attenuator control registers. T o re-enable the
system after a mute, use the address byte to turn on the desired
mixer channel. T he selected channel will then operate with the
previously set attenuator value.
P ower Supplies and D ecoupling
T he SSM2163 operates from either single or dual (split) power
supplies. In either case, proper supply decoupling is important
to maximize audio performance.
Ser ial D ata Input For m at
T o reduce noise, separate pins are provided for the digital and
analog power supply connections. T hese pins should be
connected together (VDD to VCC and VEE to VSS) as close to the
SSM2163 package as possible (Figures 22a, 22b, 22c, power
supply connections).
As previously mentioned, data is written to the SSM2163 in two
8-bit bytes. The serial data format is shown in the Address and
Data Decoding Truth Table, Figure 3. The first byte sent contains
the channel address and the Left/Right output mixer control bits.
The address byte is identified by the MSB being high.
Single Supply O per ation
T he second byte contains the data (i.e., the attenuator value).
T he six LSBs of this byte set the attenuation level, from 0 dB to
–63 dB. T he MSB of the data byte must be a logic zero.
T he SSM2163 will operate with a single power supply of +5 V
to +14 V. Single supply operation simplifies design and reduces
system cost in multimedia applications, battery powered
systems, and similar designs. T he SSM2163 provides about
2 dB of headroom (to 1% T HD+N) when operating from a
single +5 V supply.
T he standard format for data sent to the SSM2163 is an address
byte followed by a data (attenuator level) byte. In some cases,
however, only one byte needs to be sent. For example,
attenuation levels are not affected by the MUT E input. T o turn
a muted channel on, simply send an address byte with the Left
or Right mixer bit set. T he addressed channel will immediately
be enabled, using the previously-set attenuation level.
Furthermore, once a channel is addressed the attenuation level
can be varied by sending additional data bytes. For example,
fading a channel can be accomplished by simply incrementing
the data value sent to the SSM2163.
T he key to operating from a single supply is to reference all
analog common connections to a voltage midway between the
supply and ground. T o simplify single supply operation, the
SSM2163 provides a buffered pseudo-ground reference (ACOM)
on Pin 13. T his reference, shown in Figure 23, provides a low
impedance output at approximately one half of the supply
voltage. Connect Analog Ground (Pin 17) to the ACOM output
(Pin 13) for single supply operation. T o minimize noise caused
by modulation of the pseudo-ground, Pin 13 should be bypassed to
power supply ground with 0.1 µF and 10 µF capacitors.
Ser ial D ata O utput
T he MSB of the shift register is available on the serial DAT A
OUT PUT pin. T his output can be connected to the input of
another SSM2163 to permit “daisy-chain” operation. See
Figure 26 for a typical application. T he DAT A OUT PUT pin
swings between the digital power supply rails (i.e., from VDD to
VSS).
Logic Levels
All of the SSM2163 logic inputs have T T L and CMOS
compatible thresholds. However, the allowable voltage range
for these inputs extends from VDD to VSS
.
REV. 0
–11–
SSM2163
MIXER
MIXER SUMMING
BUFFER AMP
ATTENUATOR
AMPLIFIER
V
V
V
DD
AGND
ACOM
CC
V
MIXER
SWITCH
IN
+
OUT
V
Σ
+5V
10µF
0.1µF
SSM2163
V
OUT
V
+
SS
EE
DGND
10µF
+5V
POWER
SUPPLY
0.1µF
CHANNEL
SELECT
AGND
ACOM
V
CC
TTL/CMOS
LOGIC
GND
R1
CIRCUITS
10µF
0.1µF
R2
R1=R2
V
EE
V
EE
Figure 24. Use Separate Traces to Reduce Power Supply
Noise
Figure 23. Single-Supply Pseudo-Ground Reference
(ACOM) Generator
Even if the system includes separate analog and digital power
supplies, both the analog and digital power pins of the
SSM2163 should be connected to the analog supply. While this
connection will inject a small amount of digital noise into the
analog ground, the effect is small due to the SSM2163’s low
digital logic input currents and capacitances. If, on the other
hand, the SSM2163’s digital supply pins are connected to a
digital power supply, then noise from the digital supply will be
coupled into the SSM2163 and degrade performance.
For single supply operation, the inputs can either be ac-coupled,
as shown in Figure 25, or referenced to the pseudo-ground out-
put. AC coupling eliminates dc offset and offset drift
differentials between the input source and the SSM2163. In
addition, ac coupling reduces the risk of “clicks” when switching
between multiple dc-coupled inputs which have different
reference levels.
Since the input coupling capacitors are in series with the 10 kΩ
input of the attenuator, the impedance of these capacitors will
influence low frequency gain. T he inexpensive 10 µF aluminum
electrolytic capacitors shown will limit the gain error to 0.66 dB
at 20 Hz.
AP P LICATIO NS
An 8-Input, 2-O utput Mixer
A single-chip, 8-input, 2-output mixer using the SSM2163 is
shown in Figure 25. With this circuit, any of the eight channels
can be attenuated by 0 dB to –63 dB and mixed into the right,
left, or both outputs under software control.
If the entire system is operating from a single supply, then
typically the input voltage is already referenced to the midpoint
of the supply. In this case, the SSM2163 can be referenced to
the same midpoint reference source, as shown in Figure 22c.
T his connection will eliminate dc offset errors caused by having
the input signal common and the SSM2163 analog common
referenced to different voltages. DC offset errors can also be
eliminated, of course, by using the ac coupling technique
discussed above.
+5V
4
10
+
0.1µF
10µF
V
V
10µF
+
10µF
5
DD
CC
V
V
V
V
V
V
INPUT 1 LEFT
INPUT 2 LEFT
INPUT 3 LEFT
INPUT 4 LEFT
INPUT 1 RIGHT
INPUT 2 RIGHT
INPUT 3 RIGHT
INPUT 4 RIGHT
IN1
22
7
14
LEFT CHANNEL
OUTPUT
IN2
+
V
OUTL
10µF
+
10µF
+
10µF
+
10µF
+
10µF
+
10µF
N3
I
RIGHT CHANNEL
OUTPUT
15
3
V
OUTR
20
9
D ual-Supply O per ation
IN4
IN5
T he SSM2163 will also operate from dual supplies, ranging
from ±4 V to ±7 V. (See Figure 22a.) In this case, input signals
can be referenced to power supply ground. T he ACOM output
(Pin 13) is left open (no connection) for dual supply operation.
DATA OUT
NC
18
11
16
IN6
IN7
IN8
SSM2163
6
V
V
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
8
19
21
+
Supply D ecoupling
Optimizing the performance of the SSM2163, or any low noise
device, requires careful attention to power supply decoupling.
Since the SSM2163 can operate from a single +5 V supply, it
seems convenient to simply tap into the digital logic power
supply. Unfortunately, the logic supply is often a switch-mode
design, which generates noise in the 20 kHz to 1 MHz range. In
addition, fast logic gates can generate glitches hundred of millivolts
in amplitude due to wiring resistances and inductances.
27
26
25
24
28
DATA IN
CLK
DATA IN
CLOCK
23
17
13
AGND
CHIP SELECT
WRITE
LD
ACOM
DGND
SYSMUTE
V
SYSTEM MUTE
V
SS
EE
+
10µF
0.1µF
2
12
1
If a separate analog power supply is not available, the SSM2163
can be powered directly from the system power supply. Separate
power and ground traces should be provided for the analog
section, if possible. T his arrangement, shown in Figure 24, will
isolate the analog section from the logic switching transients.
Even if a separate power supply trace is not available, however,
generous supply bypassing will reduce supply line induced
noise. Local supply bypassing, consisting of a 10 µF tantalum
electrolytic in parallel with a 0.1 µF ceramic capacitor, is
recommended in all applications. (See the SSM2163 Power
Supply Connections figures.)
Figure 25. An 8-Input, 2-Output Mixer
T his circuit demonstrates ac coupling of the inputs. As
previously mentioned, this eliminates level shifting concerns
from previous stages.
T he circuit of Figure 25 also demonstrates single +5 V supply
operation. T he output of the ACOM supply-splitter, Pin 13,
provides the pseudo-ground reference which is required when
operating from a single supply.
REV. 0
–12–
SSM2163
Mixing Additional Channels
T he circuit of Figure 26 illustrates dc coupling of the inputs.
DC coupling is practical with dual supplies and ground-
referenced inputs, because the dc offsets associated with single-
supply operation are reduced. However, ac coupling could also
be used, and employing both ac- and dc-coupled signals in one
mixer is also possible. In addition, this circuit illustrates the
connections for ±5 V power supplies. Note that the negative
supply, as well as the positive supply, should be bypassed to
ground.
Some mixing applications require more than four inputs for
each stereo channel. T o meet the requirements of these systems,
two or more SSM2163s can be paralleled to provide additional
channels. A typical circuit is shown in Figure 26, which combines
two SSM2163s to form a 16-input, 2-output mixer. An SSM2135
dual audio op amp sums the outputs of each of the SSM2163s.
With this system, any of the 16 inputs can be mixed into either
or both of the output channels.
Im plem enting a Softwar e-Contr olled P an-P ot
+5V
Pan and fade effects are important attributes of modern multi-
media presentations and similar applications. One way to
achieve these effects is to apply the input signal to two input
channels of the SSM2163, as shown in Figure 27. Since any
input channel can be mixed into either or both outputs,
sophisticated pan and fade effects are easily accomplished in
software. For example, Input 1 can be connected to the left
channel with 0 dB attenuation, while Input 2 is applied to the
right channel with –10 dB of attenuation. T his configuration
will produce the effect of having the audio source “located” to
the left of center line of the speakers. Another possible option
would be to attenuate the left channel while boosting the right,
which would produce an effect of movement of the audio source.
Since any input can be connected to either output, very flexible
and sophisticated effects can be produced without hardware
changes.
4
+
10
0.1µF
10µF
20k
V
V
5
DD
CC
V
V
V
V
V
V
V
V
V
V
V
V
V
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
+5V
IN1
IN2
IN3
IN4
22
7
20k
20k
0.1µF
0.1µF
14
V
OUTL
V
OUTL
15
3
V
OUTR
20
9
DATA OUT
ACOM
–5V
IN5
13
1/2 SSM2135
NC
18
11
16
V
IN6
IN7
SSM2163
#1
V
V
IN8
6
SHIELD
8
27
26
25
24
28
SHIELD
SHIELD
SHIELD
SHIELD
DATA IN
CLK
DATA IN
CLOCK
19
21
WRITE
LD
CHIP SELECT
23
17
AGND
DGND
SYSMUTE
SYSTEM MUTE
V
V
SS
EE
12
1
2
–5V
0.1µF
10µF
+
+5V
4
V
IN1
V
IN
10
+
0.1µF
10µF
V
V
5
V
DD
CC
Σ
OUTL
V
V
V
V
V
V
V
V
V
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN1
22
7
20k
20k
14
15
V
20k
IN2
V
OUTL
V
IN3
V
R
OUT
20
9
V
IN4
V
OUTR
3
V
DATA OUT
ACOM
NC
NC
IN5
1/2 SSM2135
18
11
13
V
V
IN6
IN2
V
IN7
SSM2163
#2
16
V
IN8
V
6
8
Σ
OUTR
SHIELD
SHIELD
SHIELD
SHIELD
SHIELD
27
26
25
DATA IN
CLK
19
21
WRITE
LD
23
17
24
28
AGND
TO INPUTS
SYSMUTE
V
– V
V
V
DGND
1
EE
12
IN3
IN8
SS
SSM2163
2
–5V
0.1µF
10µF
+
Figure 27. Connecting the SSM2163 for Pan-Pot
Operation
Figure 26. A 16-Input, 2-Output Mixer
T his circuit utilizes the DAT A OUT feature of the SSM2163 to
transfer data from the first SSM2163 to the second. In the
daisy-chain mode, the DAT A OUT pin of the first SSM2163 is
connected to the DAT A IN pin of the second device. T he
advantage of this “daisy chain” connection is that it allows a
3-wire serial interface, as was used in the previous 8-input
mixer, to control two or more SSM2163s.
D r iving H eadphones
A high speed, high output current amplifier, such as the OP279,
can be added to drive headphones directly. A typical connection
is shown in Figure 28. Single +5 V operation is maintained,
since the OP279 offers rail-to-rail inputs and outputs. T he
OP279’s high current output stage can drive a 48 Ω load to
4 V p-p while maintaining less than 1% T HD.
T he serial data format for the daisy chain circuit is similar to the
8-channel application, except that the SSM2163s are loaded in
tandem. After setting WRITE and LOAD low, two bytes (16 bits)
are clocked into the first SSM2163. When WRIT E and
LOAD return high, data will be latched into both SSM2163s
simultaneously.
REV. 0
–13–
SSM2163
+V +5V
DATA IN
(P3.0) RxD
(P3.1) TxD
P1.4
220µF
+
16Ω
1/2
OP279
CLK
WRITE
LD
LEFT
HEADPHONE
14
V
OUTL
50k
SSM2163
P1.2
+5V
10k
SSM2163
80C51 µC
220µF
+
16Ω
1/2
OP279
RIGHT
HEADPHONE
P1.3
SYSMUTE
15
V
OUTR
50k
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 30. Interfacing the 80C51 µC to an SSM2163 in
4-Wire Mode
Figure 28. A Single-Supply Stereo Headphone Driver
T he op amp’s input offset voltage is only 4 mV maximum, so
the SSM2163 output can be dc coupled. T he headphone output
is ac coupled through a 220 µF capacitor. T he large coupling
capacitor is required because of the low impedance of the
headphones, which can range from 32 Ω to 600 Ω. An additional
16 Ω resistor is used in series with the output capacitor to protect
the op amp’s output stage by limiting capacitor discharge current.
An 80C51 C Inter face
A typical interface between the SSM2163 and an 80C51 µC is
shown in Figure 30. T his interface uses the 80C51’s internal
serial port. T he serial port is programmed for Mode 0 operation,
which functions as a simple 8-bit shift register. The 80C51’s Port
3.0 pin functions as the serial data output, while Port 3.1 serves
as the serial clock.
Micr ocom puter Inter faces
When data is written to the serial buffer register (SBUF, at
Special Function Register location 99H), the data is
automatically converted to serial format and clocked out via
Port 3.0 and Port 3.1. After 8 bits have been transmitted, the
T ransmit Interrupt flag (SCON.1) is set and the next 8 bits
can be transmitted.
T he SSM2163 serial data input provides an easy interface to a
variety of single chip microcomputers (µCs). Many µCs have a
built-in serial data capability which can be used for
communicating with the SSM2163. In cases where no serial
port is provided, or it is being used for some other purpose
(such as an RS-232 communications interface), the SSM2163
can easily be addressed in software.
T he 80C51 transmits serial data in Least Significant Bit (LSB)-
first format. T he SSM2163, on the other hand, requires data in
MSB format. A BYT ESWAP routine swaps the order of the bits
before transmission.
T he SSM2163 can operate in either a 3-wire or 4-wire mode.
In most cases, the 3-wire mode is more practical, due to
reduced PC board traces and compatibility with µC serial
interface protocols. A typical interface, using the 80C51 µC, is
shown in Figure 29, while the interface waveforms are shown in
the T iming Diagram, 3-Wire Mode, Figure 1.
T he SSM2163 requires the Chip Select to go low at the begin-
ning of the serial data transfer. After each 8 bits (either address
or attenuation value) are transmitted, Chip Select must go high
to latch data into the appropriate register. Chip Select is controlled
by the 80C51’s port 1.4 pin.
DATA IN
(P3.0) RxD
(P3.1) TxD
P1.4
Softwar e for the 80C51 Inter face
CLK
WRITE
LD
A software routine for the SSM2163 to 80C51 interface is
shown in Listing 1. The routine transfers the 6-bit attenuation
level stored at data memory location LEVEL_VALUE to the
SSM2163 input addressed by the contents of location
INPUT _ADDR, and turns the Left and/or Right mixer channels
on/off based on bits 3 and 4 of INPUT _ADDR.
SSM2163
+5V
10k
80C51 µC
P1.3
SYSMUTE
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
Figure 29. Interfacing the 80C51 µC to an SSM2163 in
3-Wire Mode
P or t in 4-Wir e Mode
In some cases, it may be desirable to synchronize the outputs of
several SSM2163s. T he 4-wire mode, shown in Figure 30,
provides this capability. As shown in Figure 2, the T iming
Diagram, 4-Wire Mode, the input shift register is loaded with
data while the WRITE input is low. However, the data will not
be latched into the SSM2163’s internal registers until the
rising edge of the LOAD input. In this manner, any number
of SSM2163s can be loaded with data, while the amplitude and
mixer changes will not occur until the separate LOAD pulse
occurs.
REV. 0
–14–
SSM2163
Listing 1. Softwar e for the 80C51-SSM2163 Ser ial P or t Inter face
; This subroutine loads an SSM2163 mixer channel with a 6-bit
; attenuator value, and turns the Left or Right mixer switch ON or OFF.
; The attenuator value is stored at location ATTEN_VALUE
; The mixer channel address is stored at location INPUT_ADDR
;
PORT1
ATTEN_VALUE DATA
DATA
90H
40H
;SFR register for port 1
;Attenuation level (0=0dB)
;ATTEN-VALUE: B7=0, B5–B0=Attenuation Value
DATA 41H ;Mixer Channel Address
;INPUT_ADDR: B7=1, B4=L chnl, B3=R chnl, B2-B0=address
INPUT_ADDR
LOOPCOUNT
SHIFTREG
SENDBYTE
DATA
DATA
DATA
;
42H
43H
44H
;Count loops for byte swap
;Shift reg. for byte swap
;Destination reg. for byte swap
ORG
CLR
CLR
CLR
CLR
CLR
SETB
MOV
ACALL
MOV
ACALL
RET
;
100H
SCON.7
SCON.6
SCON.5
SCON.1
PORT1.3
PORT1.4
SHIFTREG,INPUT_ADDR
SEND_IT
;arbitrary starting address
;set serial
; data mode 0
LD_2163:
;Clr SM2 for mode 0
;clr the transmit flag
;Mute function off
;WRITE and LOAD High
;Get mixer channel address
; send to SSM2163
;Get the attenuation level
; send it to the SSM2163
;Done
SEND_VAL:
SHIFTREG,ATTEN_VALUE
SEND_IT
;Convert the byte to LSB-first format and send
; it to the SSM2163
SEND_IT:
BYTESWAP:
MOV
MOV
RLC
MOV
MOV
RRC
MOV
DJNZ
CLR
MOV
JNB
CLR
SETB
RET
END
LOOPCOUNT,#8
A,SHIFTREG
A
SHIFTREG,A
A,SENDBYTE
A
SENDBYTE,A
LOOPCOUNT,BYTESWAP
PORT1.4
SBUF,SENDBYTE
SCON.1,SEND_WAIT
SCON.1
;Shift 8 bits
;Get source byte
;rotate MSB to carry
;Save new source byte
;get destination byte
;Move carry into MSB
;Save
;Done?
;Set WRITE and LOAD low
;Send the byte
SEND_WAIT:
;Wait until 8 bits are send
;Clear the serial flag
;Set WRITE and LOAD high to latch
PORT1.4
;
data into the SSM2163
T he subroutine begins by setting appropriate bits in the Serial
Control register to configure the serial port for Mode 0
operation. Next the SSM2163’s Chip Select input is set low to
enable the SSM2163. T he input channel address is obtained
from memory location INPUT _ADDR, adjusted to compensate
for the 80C51’s serial data format, and moved to the serial
buffer register. At this point, serial data transmission begins
automatically. When all 8 bits have been sent, the T ransmit
Interrupt bit is set, and the Chip Select output is set high to
latch the channel address into the SSM2163. T he subroutine
then sets Chip Select low again and proceeds to send the
attenuation value stored at location LEVEL_VALUE. When
the Chip Select input is returned high, the appropriate
SSM2163 input channel will be updated with the new
attenuation value and the subroutine ends.
T he 80C51 sends data out of its shift register LSB first, while
the SSM2163 requires data MSB first. T he subroutine therefore
includes a BYT ESWAP subroutine to reformat the data. T his
routine transfers the MSB-first byte at location SHIFT REG to
an LSB-first byte at location SENDBYT E. T he routine rotates
the MSB of the first byte into the carry with a Rotate Left
Carry instruction, then rotates the carry into the MSB of the
second byte with a Rotate Right Carry instruction. After 8
loops, SENDBYT E contains the data in the proper format.
T he BYT ESWAP routine in Listing 1 is convenient because the
attenuator data can be calculated in normal LSB form. For
example, fading a channel on the SSM2163 is simply a matter
of repeatedly incrementing the LEVEL_VALUE location and
calling the SEND_VAL subroutine. (Remember, the 6-bit
REV. 0
–15–
SSM2163
number stored in LEVEL_VALUE is the attenuation value,
expressed in –dB, so larger values will decrease volume. Also,
the register must not be allowed to increment beyond 7FH
because the MSB will be set and the SSM2163 will interpret
the value as an address. T herefore, the two highest bits of
LEVEL_VALUE should be cleared by ANDing the register
with 3FH.)
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-P in P lastic D IP
(N-28)
1.565 (39.70)
1.380 (35.10)
If the µC’s hardware serial port is being user for other purposes,
the SSM2163 can be loaded by using the parallel port. A typical
parallel interface is shown in Figure 31. T he serial data is
transmitted to the SSM2163 via the 80C51’s Port 1.6 output,
while Port 1.5 acts as the serial clock.
28
15
0.580 (14.73)
0.485 (12.32)
14
1
0.060 (1.52)
0.195 (4.95)
0.125 (3.18)
0.625 (15.87)
0.600 (15.24)
PIN 1
0.015 (0.38)
0.250
(6.35)
MAX
0.150
(3.81)
MIN
DATA IN
P1.6
P1.5
P1.4
0.015 (0.381)
0.008 (0.204)
CLK
WRITE
LD
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.070
(1.77)
MAX
SEATING
PLANE
SSM2163
+5V
10k
80C51 µC
P1.3
28-P in SO IC
(R-28)
SYSMUTE
NOTE: ADDITIONAL PINS OMITTED FOR CLARITY
0.7125 (18.10)
0.6969 (17.70)
Figure 31. An SSM2163 to 80C51 µC Interface Using
Parallel Port 1
29
15
Software for the interface of Figure 31 is straightforward.
T ypically, the µC will repeatedly shift the value to be sent, for
example from register LEVEL_VALUE, into the carry bit. Port
P1.6 is then set or reset based on the carry bit, and Port P1.5 is
strobed low and then high to create a clock pulse. After eight
loops, the value will have been sent to the SSM2163. Note that
all eight bits should be sent, even though only six bits are
significant. If only six bits are shifted in, the two low order bits
of the previous value will remain in the MSBs of the shift
register. If this action results in the MSB being a one, the
SSM2163 will interpret this as an address and unpredictable
results will occur.
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
REV. 0
–16–
相关型号：
©2020 ICPDF网 联系我们和版权申明