SSM2412 [ADI]
Dual Audio Analog Switches; 双音频模拟开关
| 型号： | SSM2412 |
| 厂家： | 
ADI |
| 描述： | Dual Audio Analog Switches |
| 文件： | 总12页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Audio
a
Analog Switches
SSM2402/SSM2412
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
“Clickless” Bilateral Audio Sw itching
Guaranteed “Break-Before-Make” Sw itching
Low Distortion: 0.003% typ
Low Noise: 1 nV/ √Hz
Superb OFF-Isolation: 120 dB typ
Low ON-Resistance: 60 ⍀ typ
Wide Signal Range: VS = ؎18 V; 10 V rm s
Wide Pow er Supply Range: ؎20 V m ax
Available in Dice Form
GENERAL D ESCRIP TIO N
The SSM2402/SSM2412 are dual analog switches designed spe-
cifically for high performance audio applications. Distortion and
noise are negligible over the full audio operating range of 20 Hz to
20 kH z at signal levels of up to 10 V rms. T he SSM2402/
SSM2412 offer a monolithic integrated alternative to expensive
and noisy relays or complex discrete JFET circuits. Unlike conven-
tional general-purpose CMOS switches, the SSM2402/SSM2412
provide superb fidelity without audio “clicks” during switching.
Conventional T T L or CMOS logic can be used to control the
switch state. No external pull-up resistors are needed. A “T ”
configuration provides superb OFF-isolation and true bilateral
operation. T he analog inputs and outputs are protected against
overload and overvoltage.
P IN CO NNECTIO NS
14-P in Epoxy D IP
(P -Suffix)
An important feature is the guaranteed “break-before-make”
for all units, even IC-to-IC. In large systems with multiple
switching channels, all separate switching units must open be-
fore any switch goes into the ON-state. With the SSM2402/
SSM2412, you can be certain that multiple circuits will all
break-before-make.
T he SSM2402/SSM2412 represent a significant step forward in
audio switching technology. Distortion and switching noise are
significantly reduced in the new SSM2402/SSM2412 bipolar-
JFET switches relative to CMOS switching technology. Based
on a new circuit topology that optimizes audio performance,
the SSM2402/SSM2412 make use of a proprietary bipolar-
JFET process with thin-film resistor network capability. Nitride
capacitors, which are very area efficient, are used for the propri-
etary ramp generator that controls the switch resistance transi-
tion. Very wide bandwidth amplifiers control the gate-to-source
voltage over the full audio operating range for each switch. T he
ON-resistance remains constant with changes in signal amplitude
and frequency, thus distortion is very low, less than 0.01% max.
16-P in SO L
(S-Suffix)
T he SSM2402 is the first analog switch truly optimized for
high-performance audio applications. For broadcasting and
other switching applications which require a faster switching
time, we recommend the SSM2412—a dual analog switch with
one-third of the switching time of the SSM2402.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
SSM2402/SSM2412–SPECIFICATIONS
(@ V = ؎18 V, R = OPEN, and –40؇C ≤ T ≤ +85؇C unless otherwise noted.
ELECTRICAL CHARACTERISTICS
S
L
A
All specifications, tables, graphs, and application data apply to both the SSM2402 and SSM2412, unless otherwise noted.)
SSM2402/SSM2412
Min Typ Max Units
P aram eter
Sym bol
Conditions
POSIT IVE SUPPLY CURRENT
NEGAT IVE SUPPLY CURRENT
GROUND CURRENT
+ISY
VIL = 0.8 V, 2.0 V1
VIL = 0.8 V, 2.0 V1
VIL = 0.8 V, 2.0 V1
6.0
4.8
0.6
7.5
6.0
1.5
mA
mA
mA
V
–ISY
IGND
DIGIT AL INPUT HIGH
VINH
T A = Full T emperature Range
T A = Full T emperature Range
VIN = 0 V to 15 V2
20
DIGIT AL INPUT LOW
VINL
0.8
V
LOGIC INPUT CURRENT
ANALOG VOLT AGE RANGE3
ANALOG CURRENT RANGE3
OVERVOLT AGE INPUT CURRENT
SWIT CH ON RESIST ANCE
ILOGIC
VANALOG
IANALOG
1.0
5.0
µA
V
–14.2
–10
+14.2
+10
mA
mA
VIN = ±VSUPPLY
±40
RON
–14.2 V ≤ VA ≤ +14.2 V
IA = ±10 mA, VIL = 2.0 V
T
A = +25°C
60
85
Ω
TA = Full Temperature Range
115
Ω
T empco (∆RON/∆T )
0.2
1
Ω/°C
RON MAT CH
RON MAT CH
IS(ON)
–14.2 V ≤ VA ≤ +14.2 V
IA = ±10 mA, VIL = 2.0 V
5
%
SWIT CH ON LEAKAGE CURRENT
VIL = 2.0 V
–14.2 V ≤ VA ≤ +14.2 V
VA = 0 V
0.05 1.0
0.05 10.0
µA
nA
SWIT CH OFF LEAKAGE CURRENT IS(OFF)
VIL = 0.8 V
–14.2 V ≤ VA ≤ +14.2 V
VA = 0 V
0.05 1.0
0.05 10.0
µA
nA
T URN-ON T IME4
T URN-OFF T IME5
tON
VA = +10 V, RL = 2 kΩ
TA = +25°C, See Test Circuit
SSM2402
SSM2412
10.0
3.5
ms
ms
ms
pC
pF
pF
dB
dB
%
tOFF
VA = +10 V, RL = 2 kΩ
TA = +25°C, See Test Circuit
SSM2402
SSM2412
4.0
1.5
BREAK-BEFORE-MAKE
T IME DELAY6
tOFF–tON
Q
T A = +25°C
SSM2402
SSM2412
6.0
2.0
CHARGE INJECT ION
T A = +25°C
SSM2402
SSM2412
50
150
ON-ST ATE INPUT
CAPACIT ANCE
CS(ON)
CS(OFF)
ISO(OFF)
CT
VA = 1 V rms
f = 5 kHz, T A = +25°C
12
OFF-ST ATE INPUT
CAPACIT ANCE
VA = 1 V rms
f = 5 kHz, T A = +25°C
4
OFF ISOLAT ION
VA = 10 V rms, 20 Hz to 20 kHz
T A = +25°C, See T est Circuit
120
CHANNEL-T O-CHANNEL
CROSST ALK
VA = 10 V rms, 20 Hz to 20 kHz
T A = +25°C
96
T OT AL HARMONIC
DIST ORT ION7
T HD
0 V to 10 V rms, 20 Hz to 20 kHz
T A = +25°C, RL = 5 kΩ
0.003 0.01
SPECT RAL NOISE DENSIT Y
WIDEBAND NOISE DENSIT Y
en
20 Hz to 20 kHz, T A = +25°C
20 Hz to 20 kHz, T A = +25°C
1
nV/√Hz
µV p-p
en p-p
0.2
NOT ES
1“VIL” is the Logic Control Input.
2Current tested at VIN = 0 V. T his is the worst case condition.
3Guaranteed by RON test condition.
4T urn-ON time is measured from the time the logic input reaches the 50% point to the time the output reaches 50% of the final value.
5T urn-OFF time is measured from the time the logic input reaches the 50% point to the time the output reaches 50% of the initial value.
6Switch is guaranteed by design to provide break-before-make operation.
7T HD guaranteed by design and dynamic RON testing.
Specifications subject to change without notice.
–2–
REV. A
SSM2402/SSM2412
ABSO LUTE MAXIMUM RATINGS
O RD ERING GUID E
Operating T emperature Range . . . . . . . . . . . –40°C to +85°C
Operating Supply Voltage Range . . . . . . . . . . . . . . . . . ±20 V
Analog Input Voltage Range
Tem perature
Range
P ackage
D escription
Model
Continuous . . . . . . . . . . . . . . V– +3.5 V ≤ VA ≤ V+ –3.5 V
Maximum Current T hrough Switch . . . . . . . . . . . . . . 20 mA
Logic Input Voltage Range . . . . . . . . . . . . V+ Supply to –2 V
V+ Supply to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . +36 V
V– Supply to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 V
VA to V– Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36 V
SSM2402P
SSM2402S
–40°C to +85°C
–40°C to +85°C
14-Pin Plastic DIP
16-Pin SOL
SSM2412P
SSM2412S
–40°C to +85°C
–40°C to +85°C
14-Pin Plastic DIP
16-Pin SOL
P ackage Type
JA*
Units
JC
D ICE CH ARACTERISTICS
D ie Size 0.105 × 0.097 Inch, 10,185 sq. mils
(2.667 × 2.464 mm, 6.57 sq. mm)
14-Pin Plastic DIP (P)
16-Pin SOL (S)
76
92
33
27
°C/W
°C/W
*θJA is specified for worst case mounting conditions, i.e., θJA is specified for device
in socket for P-DIP package; θJA is specified for device soldered to printed circuit
board for SOL package.
Tim ing Diagram
WAFER TEST LIMITS
P aram eter
Sym bol
Conditions1
Lim it
Units
POSIT IVE SUPPLY CURRENT
NEGAT IVE SUPPLY CURRENT
GROUND CURRENT
+ISY
–ISY
IGND
VIL = 0.8 V
VIL = 0.8 V
VIL = 0.8 V
7.5
6.0
1.5
mA max
mA max
mA max
LOGIC INPUT CURRENT
SWIT CH ON RESIST ANCE
ILOGIC
RON
VIN = 0 V2
5.0
85
µA max
Ω max
–14.2 V ≤ VA ≤ +14.2 V
IA = ±10 mA, VIL = 2.0 V
RON MAT CH BET WEEN SWIT CHES
SWIT CH ON LEAKAGE CURRENT
RON MAT CH
–14.2 V ≤ VA ≤ +14.2 V
IA = ±10 mA, VIL = 2.0 V
5
% max
IS(ON)
–14.2 V ≤ VA ≤ +14.2 V, VIL = 2.0 V
–14.2 V ≤ VA ≤ +14.2 V, VIL = 0.8 V
1.0
1.0
µA max
µA max
SWIT CH OFF LEAKAGE CURRENT
IS(OFF)
NOT ES
1VIL = Logic Control Input; VA = Applied Analog Input Voltage; IA = Applied Analog Input Current.
2Worst Case Condition.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
REV. A
–3–
SSM2402/SSM2412–Typical Performance Characteristics
Total Harm onic Distortion vs.
Frequency
“OFF” Isolation vs. Frequency
“ON” Resistance vs. Analog Voltage
SSM2402 Switching Tim e
vs. Tem perature
SSM2412 Switching Tim e
vs. Tem perature
Channel Separation vs. Frequency
Supply Current vs. Tem perature
Overvoltage Characteristics
Leakage Current vs. Analog Voltage
–4–
REV. A
SSM2402/SSM2412
SSM2402 TON/TOFF Switching Response
TON/TOFF Switching Response Test Circuit
SSM 2412 TON/TOFF Switching Response
Switch ON/OFF Transition Test Circuit
“OFF” Isolation Test Circuit
Switching ON/OFF Transition
REV. A
–5–
SSM2402/SSM2412
Switching Tim e Test Circuit
Sim plified Schem atic
–6–
REV. A
SSM2402/SSM2412
AP P LICATIO NS INFO RMATIO N
FUNCTIO NAL SECTIO NS
Each half of the SSM2402/SSM2412 are made up of three major
functional blocks:
1. “ T” Switch
Consists of JFET switches S1 and S2 in series as the main
switches and switch S3 as a shunt.
2. Ram p Gener ator
Generates a ramp voltage on command of the Control Input
(see Figure 1). A LOW-to-HIGH T T L input at Control
Input initiates a ramp that goes from approximately –7 V to
+7 V in 12 ms. Conversely, a HIGH-to-LOW T T L transi-
tion at Control Input will cause a downward ramp from ap-
proximately +7 V to –7 V in 12 ms for the SSM2402, and
4 ms for the SSM2412. T he Ramp Generator also supplies
the +3 V and –3 V reference levels for Switch Control.
3. Switch Contr ol
Figure 1. Ram p Generator
T he ramp from the Ramp Generator section is applied to two
differential amplifiers (DA1 and DA2) in the Switch Control
block. (See Simplified Schematic). One amplifier is refer-
enced to –3 V and the other is referenced to +3 V. Switch
Control Outputs are:
—Main Switch Contr ol—Drives two 0.25 mA current
sources that control the inverting inputs of each op amp.
When ON, the current sources cause a gate-to-source volt-
age of approximately 2.5 V which is sufficient to turn off
S1 and S2. When the current sources from Main Switch
Control are OFF, each op amp acts as a unity-gain fol-
lower (VGS = 0) and both switches (S1 and S2) will be ON.
—Shunt Switch Contr ol—Controls the Shunt Switch of
the “T ” configuration.
SWITCH O P ERATIO N
Unlike conventional analog switches, the SSM2402/SSM2412
are designed to ramp on and off gradually over several millisec-
onds. T he soft transition prevents popping or clicking in audio
systems. T ransients are minimized in active filters when the
SSM2402/SSM2412 are used to switch component values.
T o see how the SSM2402/SSM2412 switches work, first con-
sider an OFF-to-ON transition. T he Control Input is initially
LOW and the Ramp Output is at approximately –7 V. T he
Main Switch Control is HIGH which drives current sources Q3
and Q4 to 0.25 mA each. T hese currents generate 2.5 V gate-
to-source back bias for each JFET switch (S1 and S2) which
holds them OFF.
Figure 2. Switch Control
When the Control Input goes from LOW to HIGH, the Ramp
Generator slews in the positive direction as shown in Figure 2.
When the ramp goes more positive than –3 V, the Shunt Switch
Control is pulled positive by differential amplifier DA2 which
thereby puts shunt switch S3 into the OFF state. Note that S1
and S2 are still OFF, so at this time all three switches in the
“T ” are OFF.
T he Shunt Switch Control is negative which holds the shunt
JFET S3 ON. Undesired feedthrough signals in the series JFET
switches S1 and S2 are shunted to the negative supply rail
through S3.
REV. A
–7–
SSM2402/SSM2412
When the Ramp Output reaches +3 V, and the drive for the
Main Switch Control output is gated OFF by differential ampli-
fier DA1, current sources Q3 and Q4 go to the OFF state and the
VGS of each main switch goes to zero. T he high speed op amp
followers provide essentially zero gate-to-source voltage over the
full audio signal range; this in turn assures a constant low im-
pedance in the ON state over the full audio signal range. T otal
time to turn on the SSM2402 switch is approximately 10.0 ms
and 3.5 ms for the SSM2412.
O VERVO LTAGE P RO TECTIO N
T he SSM2402/SSM2412 are designed to guarantee correct op-
eration with inputs of up to ±14.2 V with ±18 V supplies. T he
switch input should never be forced to go beyond the supply
rails. In the OFF condition, if the inputs exceeds +14.2 V,
there is a risk of turning the respective input pass FET “ON.”
When the input voltage rises to within 3.8 V of the positive
supply, the op amp follower saturates and will not be able to
maintain the full 2.5 V of back bias on the gate-to-source
junction. Under this condition, current will flow from the input
through the shunt FET to the negative supply. T his current is
substantial, but is limited by the FET IDSS. Although this cur-
rent will not damage the device, there is a danger of also turn-
ing on the output pass FET , especially if the output is close to
the negative rail.
In systems using a large number of separate switches, there are
advantages to having faster switching into OFF state than into
the ON state. Break-before-make can be maintained at the sys-
tem level. T o see how the SSM2402/SSM2412 guarantee
break-before-make, consider the ON-to-OFF transition.
A Control Input LOW initiates the ON-to-OFF transition. T he
Ramp Generator integrates down from approximately +7 V to-
wards –7 V. As the ramp goes through +3 V, the comparator
controlling the Main Switches (S1 and S2) goes HIGH and turns
on current sources Q3 and Q4 which thereby puts S1 and S2 into
the OFF state. At this time, all switches in the “T ” are OFF.
When the ramp integrates down to –3 V, the Shunt Switch Con-
trol changes state and pulls shunt switch S3 into the ON state.
T his completes the ON-to-OFF transition; S1 and S2 are OFF,
and S3 is ON to shunt away any undesired feedthrough. Note
though that the ON-to-OFF time for main switches S1 and S2 is
only the time interval required for the ramp to go from +7 V to
+3 V, about 4 ms for the SSM2402, and 1.5 ms for the
SSM2412. T he time to turn on is about 2.5 times as long as the
time to turn off.
T his risk of signal “breakthrough” for inputs above +14.2 V can
be eliminated by using a source resistor of 100 Ω–500 Ω in series
with the analog input to provide additional current limiting.
Near the negative supply, transistors Q3 and Q4 saturate and
can no longer keep the switch OFF. Signal breakthrough can-
not happen, but the danger here is latch-up via a path to V–
through the shunt FET . Additional circuitry (not shown) has
been incorporated to turn OFF the shunt FET under these
conditions, and the potential for latch-up is thereby eliminated.
Typical Configuration
T he SSM2402/SSM2412 are much more than simple single
solid state switches. T he “T ” configuration provides superb
OFF-isolation through shunting of feedthrough via shunt switch
S3. Break-before-make is inherent in the design. T he ramp pro-
vides a controlled gating action that softens the ON/OFF transi-
tions. Distortion is minimized by holding zero gate-to-source
voltage for the two main FET switches, S1 and S2, using the two
op amp followers. Figure 3 shows a distortion comparison be-
tween the SSM2402 and a typical CMOS switch. In summary,
the SSM2402/SSM2412 are designed specifically for high per-
formance audio system usage.
Figure 3. Com parison of the SSM2402 and
Typical CMOS Switch for Distortion
–8–
REV. A
SSM2402/SSM2412
D IGITALLY-CO NTRO LLED ATTENUATO R
H IGH P ERFO RMANCE STEREO RO UTING SWITCH ER
T he SSM2402 Dual Audio Switch comprises the nucleus for
this 16 channels-to-one high performance stereo audio routing
switcher, which features negligible noise and low distortion over
the frequency range of 20 Hz to 20 kHz. T his performance is
achieved even while driving 600 Ω loads at signal levels up to
+30 dBu.
Figure 4 shows the usual approach to digitally-controlled at-
tenuation. With S1 closed, the signal passes unattenuated to the
output. With S1 open and S2 closed, the signal is attenuated by
R1 and R2. T he advantage of this configuration is that the at-
tenuator current does not have to flow through the switches.
T he disadvantage is that the output is undefined during the
switching period, which can be several milliseconds.
T he SSM2402 affords a much simplified electrical design and
printed circuit board layout, along with reduced manufacturing
cost, when compared with discrete JFET circuits of similar per-
formance. T he electrical performance of the design described is
vastly superior to CMOS switch designs, which are more prone
to failure resulting from electrical static discharge.
T he low distortion characteristics of the SSM2402/SSM2412
enable the alternate arrangement of Figure 5 to be used. Now
only one switch is required to change between two gains, and
there is always a signal path to the output. Values for R2 will
typically be in the low kilohm range.
For more gain steps and higher attenuation, the ladder arrange-
ment of Figure 6 can be used. T his enables a wide dynamic
range to be achieved without the need for large value resistors,
which would result in degradation of the noise performance.
T he switching control of the SSM2402 may be activated by
conventional mechanical switches or 5 volt T T L or CMOS logic
circuits. T he application shown utilizes a simple mechanical
control switch for illustration purposes only. Many diverse X/Y
control schemes, destination control, or computer controlled
designs can be utilized.
T he “T ” configuration of the SSM2402 switch provides excel-
lent ON-OFF isolation. T he SSM2402 also features ms ramped
turn on and ms ramped turn off for click-free switching. Addi-
tionally, the switch has a break-before-make switching sequence.
Both features become significant in large audio switching sys-
tems where the audio path can pass through multiple switching
elements. Such controlled switching is very important in large
systems used in broadcast program switching or in production
work.
Figure 4.
T he application circuit design also employs the SSM2015 bal-
anced input amplifier (Figure 7). T he input impedance is high
(≈100 kΩ), balanced or unbalanced. T he input circuit incorpo-
rates a single pole RFI filter with a cutoff frequency set at
145 kHz. In addition, the input circuit attenuates the signal by
25 dB and extends the common-mode input voltage range to
±98 volts peak, with common-mode rejection greater than
70 dB from 20 Hz to 20 kHz. T he SSM2015 is set to produce a
15 dB gain. T he signal drive level into the SSM2402 switch is
then +10 dBu with a +20 dBu input level and +14 dBu peak,
well within ideal operating range. Good signal-to-noise is main-
tained, with generous head-room available by electing to use
±18 V dc power supply voltages.
Figure 5.
Figure 6.
REV. A
–9–
SSM2402/SSM2412
Figure 7. Switcher Schem atic
–10–
REV. A
SSM2402/SSM2412
Figure 8. Switcher Functional Block Diagram
Overall performance of the 16 × 1 stereo switcher is noteworthy.
Input-to-output frequency response is flat to within 1 dB over a
10 Hz to 50 kHz band. T otal harmonic distortion plus noise is
less than 0.03%, from 20 Hz to 20 kHz. SMPT E intermodula-
tion distortion is less than 0.02%. T he use of ±18 V dc power
supplies produces a +30 dBm clip level, even when driving
600 Ω loads.
T he routing switcher bus carries high level unbalanced audio,
but is driven with low impedance sources. With the output im-
pedance of the SSM2015 at virtually 0 Ω and the SSM2402
switch ON, resistance is typically 60 Ω. Bus-to-bus crosstalk is
exceptionally low. For example, assuming 14 pF coupling be-
tween buses and 20 kHz signal, the crosstalk (isolation) exceeds
80 dB. T he 14 pF would be representative for the 16 × 1 stereo
design shown. Shielding of the buses with a printed circuit
board ground plane and physically isolating the input and out-
put circuits will reduce the crosstalk even further. T he “T ” con-
figuration of the SSM2402 switch virtually eliminates crosstalk
between the various input signal sources.
Table I. Circuit P erform ance Specifications
Max Input Level
Input Impedance, Unbalanced
Input Impedance, Balanced
+30 dBu
100 kΩ
200 kΩ
Common-Mode Rejection (20 Hz to 20 kHz) >70 dB
T he output amplifier incorporates a buffer amplifier that pro-
vides 4 dB of gain (nominally), with adjustable output level trim
control. T he buffer also isolates the switching bus from the bal-
anced output amplifier circuit. T he balanced output is designed
to drive 600 Ω loads and utilizes two SSM2134 IC amplifiers.
T he differential design increases drive capability, yet increases
the heat dissipation surface area, and keeps IC package tem-
perature well within safe operating limits, even when driving
600 Ω loads. T he SSM2134 is recommended due to its low
noise, wide frequency response, and output drive current
capabilities.
Common-Mode Voltage Limit
Max Output Level
Output Impedance
±98 V Peak
+30 dBu/dBm
67 Ω
Gain Control Range
±2 dB
Output Voltage Slew Rate
6 V/µs
Frequency Response (±0.05 dB)
Frequency Response (±0.5 dB)
T HD + Noise (20 Hz to 20 kHz, +8 dBu)
T HD + Noise (20 Hz to 20 kHz, +24 dBu)
20 Hz to 20 kHz
10 Hz to 50 kHz
0.005%
0.03%
IMD (SMPTE 60 Hz & 4 kHz, 4:1, +24 dBu) 0.02%
Crosstalk (20 Hz to 20 kHz)
S/N Ratio @ 0 dB Gain
>80 dB
135 dB
REV. A
–11–
SSM2402/SSM2412
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
14-P in Epoxy D IP
(P -Suffix)
0.795 (20.19)
0.725 (18.42)
14
1
8
0.280 (7.11)
0.240 (6.10)
7
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.100 0.070 (1.77)
(2.54)
BSC
0.045 (1.15)
16-P in SO L
(S-Suffix)
0.4133 (10.50)
0.3977 (10.00)
16
9
1
8
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
PIN 1
x 45°
0.0118 (0.30)
0.0040 (0.10)
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
–12–
REV. A
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