SSM2529_技术文档

Digital Input, Mono 2 W,

Class-D Audio Power Amplifier

SSM2529

This unique architecture enables extremely low real-world power

consumption from digital audio sources with excellent audio

performance. The SSM2529 is ideal for power sensitive applications,

such as mobile phones and portable media players, where system

noise can the corrupt small analog signals that are sent to an

analog input audio amplifier.

Data Sheet

FEATURES

Filterless mono, digital input Class-D amplifier

I²C control interface

Serial digital audio interface supports common formats

(I²S, PCM, LJ, RJ, TDM1-16, PDM)

Supports wide range of sample rates: 8.0 kHz to 96.0 kHz

MCLK and BCLK can be provided by built-in phase-locked

loop (PLL)

Supports single power supply mode; DVDD can be provided

by built-in low dropout (LDO) regulator

2.5 V to 5.5 V SPKVDD operating supply voltage

1.08 V to 1.98 V DVDD operating supply voltage

Support off-chip volume control without I²C

2.4 W into 4 Ω and 1.4 W into 8 Ω at 5 V supply with <1% THD + N

Available in a 16-ball, 1.92 mm × 1.94 mm, 0.4 mm pitchWLCSP

Efficiency 95% at full scale into 8 Ω

Using the SSM2529, audio data can be transmitted to the amplifier

over a standard digital audio serial interface, thereby significantly

reducing the effect of noise sources such as GSM interference or

other digital signals on the transmitted audio. The closed-loop

digital input design retains the benefits of an all-digital amplifier, yet

enables very good PSRR and audio performance. The three-level,

Σ-Δ Class-D modulator is designed to provide the least amount of

EMI, the lowest quiescent power dissipation, and the highest

audio efficiency without sacrificing audio quality.

The audio input is provided via a serial audio interface that can be

programmed to accept all common audio formats, including I²S,

TDM, and PDM. Control of the IC is provided via an I²C control

interface. An alternative to I²C control is standalone operation

mode, which allows several settings that are adjusted by off-chip

external resistors. The SSM2529 can accept a variety of input MCLK

frequencies and can use BCLK as the clock source in some

configurations. An integrated PLL can also provide the device

master clock.

Signal-to-noise ratio (SNR): 103 dB, A-weighted

Power supply rejection ratio (PSRR): >80 dB at 217 Hz

Digital volume control: −70 dB to +24 dB in 0.375 dB steps

Ultralow idle current

Autosample rate detection

Pop-and-click suppression

Short-circuit and thermal protection with programmable

autorecovery

Supports smart power-down when no input signal is detected

Power-on reset and UVLO voltage monitoring

Selectable ultralow EMI emission mode

Supports SPKVDD voltage monitor

The integrated DSP includes soft digital volume control circuits; a

de-emphasis, high-pass filter; a seven-band programmable equalizer;

and a programmable digital dynamic range compressor. In addition,

the part includes a feedforward speaker temperature prediction

module to protect the loudspeaker.

Digital audio processing

7-band programmable equalizer

Programmable dynamic range compression (DRC) with

noise gate, expander, compressor, and limiter

The SSM2529 supports single-supply mode, where DVDD is

provided by the on-chip LDO regulator, eliminating the need for an

external digital core supply.

APPLICATIONS

The digital interface is very flexible and convenient. It can offer a

better system solution for other products whose sole audio source

is digital, such as wireless speakers, laptop PCs, portable digital

televisions, and navigation systems.

Mobile phones

Portable media players

Laptop PCs

Wireless speakers

Portable gaming

Navigation systems

The SSM2529 is specified over the industrial temperature range of

−40°C to +85°C. It has built-in thermal shutdown and output short-

circuit protection. It is available in a 16-ball, 1.92 mm × 1.94 mm

wafer level chip scale package (WLCSP).

GENERAL DESCRIPTION

The SSM2529 is a digital input, Class-D power amplifier that combines

a digital-to-analog converter (DAC), a low power audio specific

digital signal processor, and a sigma-delta (Σ-Δ) Class-D modulator.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

SSM2529

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Serial Audio Interface and Sample Rate Control (SAI_FMT1)

Register ........................................................................................ 28

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Performance Specifications......................................................... 5

Power Supply Requirements ....................................................... 6

Digital Input/Output.................................................................... 6

Digital Interpolation Filter.......................................................... 6

Digital Timing............................................................................... 6

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 14

Overview...................................................................................... 14

Master Clock ............................................................................... 14

Internal Clock Generator .......................................................... 14

Digital Input Serial Audio Interface......................................... 14

PDM Mode Setup and Control................................................. 15

High-Pass Filter .......................................................................... 15

Fully Programmable Seven-Band Equalizer............................... 15

Dynamic Range Control............................................................ 18

DRC Mode Control.................................................................... 18

Gain Ripple Remove .................................................................. 21

Speaker Protection ..................................................................... 21

Power Supplies ............................................................................ 21

Power Control............................................................................. 21

Power-On Reset/Voltage Supervisor........................................ 22

Standalone Mode........................................................................ 22

I²C Port......................................................................................... 22

Register Summary .......................................................................... 24

Register Details ............................................................................... 27

Serial Audio Interface Control (SAI_FMT2) Register .......... 29

Channel Mapping Control Register......................................... 30

Volume Control Before FDSP (VOL_BF_FDSP) Register ... 31

Volume Control After FDSP (VOL_AF_FDSP) Register ..... 31

Volume and Mute Control Register......................................... 31

DPLL_CTRL Register................................................................ 32

APLL_CTRL1 Register.............................................................. 32

APLL_CTRL2 Register.............................................................. 32

APLL_CTRL3 Register.............................................................. 32

APLL_CTRL4 Register.............................................................. 32

APLL_CTRL5 Register.............................................................. 33

APLL_CTRL6 Register.............................................................. 33

FAULT_CTRL1 Register ........................................................... 34

FAULT_CTRL2 Register ........................................................... 34

DEEMP_CTRL Register............................................................ 34

HPF_CTRL Register .................................................................. 35

EQ1_COEF0_HI Register......................................................... 35

EQ1_COEF0_LO Register ........................................................ 35

EQ1_COEF1_HI Register......................................................... 35

EQ1_COEF1_LO Register ........................................................ 35

EQ1_COEF2_HI Register......................................................... 36

EQ1_COEF2_LO Register ........................................................ 36

EQ1_COEF3_HI Register......................................................... 36

EQ1_COEF3_LO Register ........................................................ 36

EQ1_COEF4_HI Register......................................................... 36

EQ1_COEF4_LO Register ........................................................ 36

EQ2_COEF0_HI Register......................................................... 36

EQ2_COEF0_LO Register ........................................................ 36

EQ2_COEF1_HI Register......................................................... 36

EQ2_COEF1_LO Register ........................................................ 36

EQ2_COEF2_HI Register......................................................... 37

EQ2_COEF2_LO Register ........................................................ 37

EQ2_COEF3_HI Register......................................................... 37

EQ2_COEF3_LO Register ........................................................ 37

EQ2_COEF4_HI Register......................................................... 37

EQ2_COEF4_LO Register ........................................................ 37

EQ3_COEF0_HI Register......................................................... 37

EQ3_COEF0_LO Register ........................................................ 37

Software Reset and Master Software Power-Down Control

(PWR_CTRL) Register.............................................................. 27

MCLK Ratio and Frequency ..................................................... 27

Edge Speed and Clocking Control (SYS_CTRL) Register.... 28

Rev. 0 | Page 2 of 52

Data Sheet

SSM2529

EQ3_COEF1_HI Register..........................................................37

EQ3_COEF1_LO Register.........................................................37

EQ3_COEF2_HI Register..........................................................38

EQ3_COEF2_LO Register.........................................................38

EQ3_COEF3_HI Register..........................................................38

EQ3_COEF3_LO Register.........................................................38

EQ3_COEF4_HI Register..........................................................38

EQ3_COEF4_LO Register.........................................................38

EQ4_COEF0_HI Register..........................................................38

EQ4_COEF0_LO Register.........................................................38

EQ4_COEF1_HI Register..........................................................38

EQ4_COEF1_LO Register.........................................................38

EQ4_COEF2_HI Register..........................................................39

EQ4_COEF2_LO Register.........................................................39

EQ4_COEF3_HI Register..........................................................39

EQ4_COEF3_LO Register.........................................................39

EQ4_COEF4_HI Register..........................................................39

EQ4_COEF4_LO Register.........................................................39

EQ5_COEF0_HI Register..........................................................39

EQ5_COEF0_LO Register.........................................................39

EQ5_COEF1_HI Register..........................................................39

EQ5_COEF1_LO Register.........................................................39

EQ5_COEF2_HI Register..........................................................40

EQ5_COEF2_LO Register.........................................................40

EQ5_COEF3_HI Register..........................................................40

EQ5_COEF3_LO Register.........................................................40

EQ5_COEF4_HI Register..........................................................40

EQ5_COEF4_LO Register.........................................................40

EQ6_COEF0_HI Register..........................................................40

EQ6_COEF0_LO Register.........................................................40

EQ6_COEF1_HI Register..........................................................40

EQ6_COEF1_LO Register.........................................................40

EQ6_COEF2_HI Register..........................................................41

EQ6_COEF2_LO Register.........................................................41

EQ7_COEF0_HI Register..........................................................41

EQ7_COEF0_LO Register.........................................................41

EQ7_COEF1_HI Register..........................................................41

EQ7_COEF1_LO Register.........................................................41

EQ7_COEF2_HI Register..........................................................41

EQ7_COEF2_LO Register.........................................................41

EQ_CTRL1 Register...................................................................42

EQ_CTRL2 Register...................................................................42

DRC_CTRL1 Register................................................................43

DRC_CTRL2 Register................................................................43

DRC_CTRL3 Register................................................................44

DRC_CURVE1 Register.............................................................44

DRC_CURVE2 Register.............................................................45

DRC_CURVE3 Register.............................................................45

DRC_CURVE4 Register.............................................................45

DRC_CURVE5 Register.............................................................45

DRC_HOLD_TIME Register....................................................46

DRC_RIPPLE_CTRL Register..................................................46

DRC Mode Control Register.....................................................46

FDSP_EN Register......................................................................47

SPK_PROT_EN Register ...........................................................47

TEMP_AMBIENT Register.......................................................47

SPKR_DCR Register...................................................................47

SPKR_TC Register......................................................................47

SP_CF1_H Register ....................................................................47

SP_CF1_L Register .....................................................................47

SP_CF2_H Register ....................................................................47

SP_CF2_L Register .....................................................................48

SP_CF3_H Register ....................................................................48

SP_CF3_L Register .....................................................................48

SP_CF4_H Register ....................................................................48

SP_CF4_L Register .....................................................................48

SPKR_TEMP Register................................................................48

SPKR_TEMP_MAG Register....................................................48

MAX_SPKR_TEMP Register....................................................48

SPK_GAIN Register ...................................................................49

SOFT_RST Register....................................................................49

Applications Information...............................................................50

Outline Dimensions........................................................................51

Ordering Guide ...........................................................................51

REVISION HISTORY

7/12—Revision 0: Initial Version

Rev. 0 | Page 3 of 52

SSM2529

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

SCL/

SDA/

VOLUME

SPKGND

SPKVDD LDO_OUT

SDATA LRCLK BCLK

CONTROL A CONTROL B

SUPPLY DETECTOR

LDO

2

I S

PLL

I C

VOLUME

CONTROL

A

DIGITAL

FILTERS

VOLUME

CONTROL

B

MONO

IDAC

Σ-Δ

FULL BRIDGE

POWER

OUTP

OUTN

CLASS-D

MODULATOR

(MONO)

STAGE

DVDD

GND

EQ (7B)

HPF

3 + 2 + 2

(STEREO)

–70dB

TO

+24dB

–70dB

TO

+24dB

DRC

SPEAKER

TEMPERATURE

ESTIMATION

POWER-ON

CLOCKING

CONTROL

POP-AND-CLICK

SUPPRESSION

RESET

MCLK

SSM2529

AND UVLO

STDBN

ADDR/PDM

SA_MODE

Figure 1.

Rev. 0 | Page 4 of 52

Data Sheet

SSM2529

SPECIFICATIONS

Standard test condition: SPKVDD = 4.2 V; DVDD = 1.8 V; f_S= 48 kHz; MCLK = 128 × f_S; T_A= 25°C; R_L= 8 Ω + 33 µH; LP_MODE = 0;

0 dB volume control setting, unless otherwise noted.

PERFORMANCE SPECIFICATIONS

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min Typ Max Unit

DEVICE CHARACTERISTICS

Output Power

P_OUT

f = 1 kHz, BW = 20 kHz

R_L= 4 Ω, THD = 1%, SPKVDD = 5.0 V

R_L= 4 Ω, THD = 10%, SPKVDD = 5.0 V

R_L= 8 Ω, THD = 1%, SPKVDD = 5.0 V

R_L= 8 Ω, THD = 10%, SPKVDD = 5.0 V

R_L= 4 Ω, THD = 1%, SPKVDD = 4.2 V

R_L= 4 Ω, THD = 10%, SPKVDD = 4.2 V

R_L= 8 Ω, THD = 1%, SPKVDD = 4.2 V

R_L= 8 Ω, THD = 10%, SPKVDD = 4.2 V

R_L= 4 Ω, THD = 1%, SPKVDD = 3.6 V

R_L= 4 Ω, THD = 10%, SPKVDD = 3.6 V

R_L= 8 Ω, THD = 1%, SPKVDD = 3.6 V

R_L= 8 Ω, THD = 10%, SPKVDD = 3.6 V

R_L= 4 Ω, THD = 1%, SPKVDD = 2.5 V

R_L= 4 Ω, THD = 10%, SPKVDD = 2.5 V

R_L= 8 Ω, THD = 1%, SPKVDD = 2.5 V

R_L= 8 Ω, THD = 10%, SPKVDD = 2.5 V

P_OUT= 2 W into 4 Ω, SPKVDD = 5.0 V

P_OUT= 1.4 W into 8 Ω, SPKVDD = 5.0 V, normal operation

P_OUT= 1.4 W into 8 Ω, SPKVDD = 5.0 V, ultralow EMI operation

P_OUT= 1 W into 8 Ω, f = 1 kHz, SPKVDD = 5.0V

2.4

3.1

1.4

1.8

1.7

2.2

0.95

1.2

1.6

0.7

0.9

0.55

0.72

0.32

0.42

91

W

%

Efficiency

η

95

86

0.03

Total Harmonic Distortion Plus

Noise

THD + N

P_OUT= 0.7 W into 8 Ω, f = 1 kHz, SPKVDD = 4.2 V

P_OUT= 0.5 W into 8 Ω, f = 1 kHz, SPKVDD = 3.6 V

0.03

280

2.0

%

kHz

mV

Average Switching Frequency

f_SW

Differential Output Offset

Voltage

V_OOS

Power Supply Rejection Ratio

PSRR (DC) SPKVDD = 2.5 V to 5.0 V

70

80

dB

PSRR_GSM

I_SPKVDD

V_RIPPLE= 100 mV rms at 217 Hz, dither input

80

dB

Supply Current

Dither input, SPKVDD = 5.0 V

Dither input, SPKVDD = 4.2 V

Dither input, SPKVDD = 3.6 V

Dither input, SPKVDD = 2.5 V

Power-down

Dither input, DVDD = 1.8 V

Dither input, DVDD = 1.08 V

Power-down

3.0

2.8

2.7

2.4

100

0.6

0.3

2

mA

nA

mA

µA

µV

Supply Current

I_DVDD

Output Voltage Noise

Signal-to-Noise Ratio

Mute Attenuation

e_n

SNR

f = 20 Hz to 20 kHz, dither input

A-weighted reference to 0 dBFS, SPKVDD = 4.2 V

Soft mute on

22

103

dB

100

Rev. 0 | Page 5 of 52

SSM2529

Data Sheet

POWER SUPPLY REQUIREMENTS

Table 2.

Parameter

SPKVDD

DVDD

Min

2.5

1.08

Typ

4.2

1.8

Max

5.5

1.98

Unit

V

DIGITAL INPUT/OUTPUT

Table 3.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Input Voltage, High

Input Voltage, Low

V_IH

V_IL

I_IH

I_IL

I_IH

I_IL

0.7 × DVDD

−0.3

3.6

V

+0.3 × DVDD

Input Leakage Current, High

Input Leakage Current, Low

MCLK Input Leakage, High

MCLK Input Leakage, Low

Input Capacitance

Excluding MCLK

Excluding MCLK and bidirectional pins

1

3

5

µA

pF

DIGITAL INTERPOLATION FILTER

Table 4.

Parameter

Mode

Factor

Min

Typ

Max

Unit

kHz

dB

kHz

dB

Pass Band (−3 dB)

Pass-Band Ripple

Transition Band

Stop Band

Stop Band Attenuation

Group Delay

48 kHz mode, typical at 48 kHz

0.423 f_S

0.5 f_S

20

0.03

24

28

0.582 f_S

14/f_S

60

292

µs

DIGITAL TIMING

All timing specifications are given for the default setting (I²S mode) of the serial input port.

Table 5.

Limit

Parameter

T_MIN

T_MAX

Unit

Description

MASTER CLOCK (See Figure 2)

t_BP

74

148

136

271

ns

MCLK period, 256 f_Smode

MCLK period, 128 f_Smode

SERIAL PORT (See Figure 2)

t_BIL

t_BIH

t_LIS

t_LIH

t_SIS

t_SIH

40

10

ns

BCLK low pulse width

BCLK high pulse width

LRCLK setup; time to BCLK rising

LRCLK hold; time from BCLK rising

SDATA setup; time to BCLK rising

SDATA hold; time from BCLK rising

Rev. 0 | Page 6 of 52

Data Sheet

SSM2529

Limit

Parameter

I²C PORT (See Figure 3)

T_MIN

T_MAX

Unit

Description

f_SCL

t_SCLH

t_SCLL

t_SCS

t_SCH

t_DS

t_SCR

t_SCF

t_SDR

t_SDF

t_BFT

400

kHz

µs

ns

µs

SCL frequency (not shown in Figure 3)

SCL high

SCL low

Setup time, relevant for repeated start condition

Hold time; after this period, the first clock is generated

Data setup time

SCL rise time

SCL fall time

SDA rise time (not shown in Figure 3)

SDA fall time (not shown in Figure 3)

Bus-free time; time between stop and start

0.6

1.3

0.6

100

300

0.6

t_BIH

t_BP

BCLK

t_BIL

t_LIS

t_LIH

LRCLK

t_SIS

SDATA

LEFT-JUSTIFIED

MODE

MSB

MSB – 1

t_SIH

t_SIS

SDATA

2

I S-JUSTIFIED

MSB

MODE

t_SIH

t_SIS

SDATA

RIGHT-JUSTIFIED

MODE

MSB

LSB

t_SIH

Figure 2. Serial Input Port Timing

t_DS

t_SCH

SDA

SCL

t_SCLH

t_SCS

t_SCR

t_SCLL

t_SCF

t_BFT

START

CONDITION

STOP

CONDITION

Figure 3. I²C Port Timing

Rev. 0 | Page 7 of 52

SSM2529

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 6.

Parameter

Rating

SPKVDD Supply Voltage

DVDD Supply Voltage

Input Voltage (Signal Source)

ESD Susceptibility

−0.3 V to +5.5 V

−0.3 V to +1.98 V

−0.3 V to +3.6 V

4 kV

Table 7. Thermal Resistance

Package Type

θ_JA

Unit

16-Ball, 1.92 mm × 1.94 mm WLCSP

56.1

°C/W

Storage Temperature Range

Operating Temperature Range

Junction Temperature Range

Lead Temperature (Soldering, 60 sec)

−65°C to +150°C

−40°C to +85°C

−65°C to +165°C

300°C

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 8 of 52

Data Sheet

SSM2529

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1

INDICATOR

1

2

3

4

SCL/

SDA/

VOLUME

CONTROL A CONTROL B

SPKVDD

OUTP

A

B

STDBN

DVDD

MCLK

SA_MODE ADDR/PDM

OUTN

SPKGND

LRCLK

LDO_OUT

SDATA

GND

C

D

BCLK

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

(SOLDER BALLS ON OPPOSITE SIDE)

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

Pin Number

Mnemonic

SCL/VOLUME CONTROL A

SDA/VOLUME CONTROL B

SPKVDD

OUTP

STDBN

SA_MODE

ADDR/PDM

OUTN

DVDD

LDO_OUT

GND

Function

Input

Input/Output

Power

Output

Input

Description

A1

A2

A3

A4

B1

B2

B3

B4

C1

C2

C3

C4

D1

D2

D3

D4

I²C Clock in I²C Mode/Volume Controller A in Standalone Mode

I²C Data in I²C Mode/Volume Controller B in Standalone Mode

2.5 V to 5.5 V Amplifier Power

Positive Output

Power-Down Control; Active Low

Standalone and Hardware Selection; 1 = Standalone Mode

I²C Chip Address Select/Input Interface Select in Standalone Mode

Negative Output

Digital Power

LDO Output

Input

Output

Power

Input

Digital and Analog Ground

Amplifier Ground

SPKGND

MCLK

SDATA

BCLK

Serial Audio Interface Master Clock and I²S/TDM/PDM Channel Select

I²S Serial Data/PDM Data

I²S Bit Clock/PDM Clock

I²S Left-Right Frame Clock

LRCLK

Rev. 0 | Page 9 of 52

SSM2529

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

100

10

8Ω + 33µH

4Ω + 15µH

10

1

2.5V

1

2.5V

0.1

3.6V

5V

3.6V

0.1

5V

0.01

0.001

0.0001

0.001

0.01

0.1

(W)

1

10

0.001

0.01

0.1

P (W)

OUT

1

10

P

OUT

Figure 5. THD + N vs. Output Power into 8 Ω, 5.0 V Gain Setting

Figure 8. THD + N vs. Output Power into 4 Ω, 3.6 V Gain Setting

100

1

4Ω + 15µH

8Ω + 33µH

10

0.1

2.5V

1

3.6V

1W

5V

500mW

0.1

0.01

250mW

0.01

0.001

0.01

0.001

0.01

0.1

(W)

1

10

0.1

1

10

100

P

FREQUENCY (kHz)

OUT

Figure 6. THD + N vs. Output Power into 4 Ω, 5.0 V Gain Setting

Figure 9. THD + N vs. Frequency into 8 Ω, SPKVDD = 5.0 V

100

8Ω + 33µH

4Ω + 15µH

10

1

2.5V

1

2W

3.6V

0.1

1W

500mW

5V

0.01

0.001

0.01

0.1

(W)

1

10

0.01

0.1

1

10

100

P

FREQUENCY (kHz)

OUT

Figure 7. THD + N vs. Output Power into 8 Ω, 3.6 V Gain Setting

Figure 10. THD + N vs. Frequency into 4 Ω, SPVKDD = 5.0 V

Rev. 0 | Page 10 of 52

Data Sheet

SSM2529

1

100

10

8Ω + 33µH

4Ω + 15µH

0.1

1

500mW

250mW

500mW

125mW

250mW

0.1

0.01

125mW

0.001

0.01

0.001

0.1

1

10

100

0.01

0.1

1

10

100

FREQUENCY (kHz)

Figure 11. THD + N vs. Frequency into 8 Ω, SPVKDD = 3.6 V

Figure 14. THD + N vs. Frequency into 4 Ω, SPVKDD = 2.5 V

100

3.4

4Ω + 15µH

10

1

3.2

3.0

2.8

2.6

2.4

1W

4Ω

NO LOAD

0.1

8Ω

500mW

250mW

0.01

0.001

0.01

0.1

1

10

100

2.5

3.0

3.5

4.0

4.5

5.0

FREQUENCY (kHz)

SPKVDD (V)

Figure 12. THD + N vs. Frequency into 4 Ω, SPVKDD = 3.6 V

Figure 15. Quiescent Current (Power Stage) vs. Supply Voltage

100

800

700

600

500

8Ω + 33µH

10

1

400

48kHz

0.1

300

250mW

125mW

24kHz

200

0.01

62.5mW

100

8kHz

0.001

0

1.08 1.18 1.28 1.38 1.48 1.58 1.68 1.78 1.88 1.98

0.01

0.1

1

10

100

FREQUENCY (kHz)

DVDD (V)

Figure 13. THD + N vs. Frequency into 8 Ω, SPKVDD = 2.5 V

Figure 16. Quiescent Current (Digital Core) vs. Supply Voltage

Rev. 0 | Page 11 of 52

SSM2529

Data Sheet

2.0

100

80

60

40

20

0

f

R

= 1kHz

= 8Ω + 33µH

4Ω + 15µH

IN

5V

L

2.5V

1.5

1.0

0.5

0

3.6V

THD+N = 10%

THD+N = 1%

2.5

3.0

3.5

4.0

4.5

5.0

0

0.4

0.8

1.2

P

1.6

(W)

2.0

2.4

2.8

SPKVDD (V)

OUT

Figure 20. Efficiency vs. Output Power into 4 Ω

Figure 17. Maximum Output Power vs. Supply Voltage, R_L= 8 Ω

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

3.0

8Ω + 33µH

f

R

= 1kHz

= 4Ω + 15µH

IN

L

2.5

2.0

1.5

1.0

0.5

0

5V

3.6V

2.5V

THD+N = 10%

THD+N = 1%

0

0.2

0.4

0.6

0.8

(W)

1.0

1.2

1.4

1.6

2.5

3.0

3.5

4.0

4.5

5.0

P

SPKVDD (V)

OUT

Figure 21. Power Supply Current vs. Output Power, R_L= 8 Ω

Figure 18. Maximum Output Power vs. Supply Voltage, R_L= 4 Ω

0.7

100

4Ω + 15µH

2.5V

3.6V

0.6

0.5

0.4

0.3

0.2

0.1

0

80

5V

3.6V

5V

60

40

20

2.5V

8Ω + 33µH

0

0.5

1.0

1.5

(W)

2.0

2.5

3.0

0

0.3

0.6

0.9

1.2

1.5

P

(W)

OUT

Figure 22. Power Supply Current vs. Output Power, R_L= 4 Ω

Figure 19. Efficiency vs. Output Power into 8 Ω

Rev. 0 | Page 12 of 52

Data Sheet

SSM2529

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

5V

3.6V

2.5V

8Ω + 33µH

–20

–40

–60

–80

SPKVDD = 2.5V

–100

–120

–140

–160

SPKVDD = 5V

SPKVDD = 3.6V

0.1

–180

0.01

1

10

100

0.1

1

10

100

FREQUENCY (kHz)

Figure 23. Output Spectrum vs. Frequency

(FFT with 100 mW Output Power into 8 Ω Load)

Figure 24. PSRR vs. Frequency

Rev. 0 | Page 13 of 52

SSM2529

Data Sheet

THEORY OF OPERATION

OVERVIEW

INTERNAL CLOCK GENERATOR

The SSM2529 is a fully integrated, mono, digital switching audio

amplifier. The SSM2529 receives digital audio inputs and produces

the PDM differential switching outputs using the internal power

stage. The part has built-in protections for overtemperature and

overcurrent conditions. The SSM2529 also has built-in soft

turn-on and soft turn-off for pop-and-click suppression. The part

has programmable register control via the I²C port.

The digital core clock can be derived directly from the external

clock, or it can be generated using the PLL. Clocks for the DSPs,

the serial ports, and the converters are derived from the core clock.

The core clock rate is always an integer multiple of the sample

rate used for the part.

The clock generation block is composed of a digital PLL and an

analog PLL. The analog PLL can accept input frequencies in the

8 MHz to 27 MHz range. To support lower frequencies (8 kHz

to 8 MHz), the chip provides a digital PLL. It can boost the

input clock frequency by 2^N, where N = 1 to 10.

MASTER CLOCK

In master mode, the built-in PLL can provide the master clock. In

slave mode, the SSM2529 receives an external clock at the

MCLK or BCLK input pin. The external clock must be fully

synchronous with the incoming digital audio on the serial

interface. The internal clock for the SSM2529 always runs at

5.6448 MHz to 8.192 MHz, depending on the input sample rate.

The three options for providing the master clock to the part are as

follows:

Figure 25 shows the clock generation block diagram.

For the digital PLL, the source clock is selected by the

DPLL_REF_SEL bits (Register 0x08), and the frequency

relationship between the DPLL input and the output clock is

defined by the DPLL_NDIV bit.

The frequency relationship between the APLL input and output is

•

Using the clock generated by the built-in PLL

Using the BCLK pin

Using the MCLK pin

f_PLL= f_IN×(R + (N/M))/X

where R, N, M, and X are defined by the corresponding PLL

registers (Register 0x09 to Register 0x0D).

The MCLK option can use the built-in PLL or the BCLK pin to

generate the internal clock as long as the clock is provided at the

same rate that is required by the MCLK pin. By setting the PLLEN

bit in Register 0x0E, this is enabled. In this case, there is no need to

provide the master clock to the MCLK pin, which in turn saves a

pin connection from the audio source. If using the MCLK pin,

various multiples of the sample frequency can be used for MCLK.

See Table 48 for all available options and settings. When the

SSM2529 enters its power-down state, it is possible to gate this

clock to further conserve system power. However, an MCLK

must be present for the audio amplifier to operate. The input

MCLK rate is determined by setting the MCS bits in Register 0x00.

For more information, see Table 48.

DIGITAL INPUT SERIAL AUDIO INTERFACE

The SSM2529 includes a standard serial audio interface that is

slave only. The interface is capable of receiving I²S, left justified,

right justified, PCM/TDM, or PDM input formats. The number

of data bits must be set when in right-justified mode only.

CLOCK HIGHER

THAN 8MHz

44.4kHz × 1024/

48kHz × 1024

APLL

÷X

×(R + N/M)

CLK_IN

N

×2

LRCLK/BCLK

ANALOG PLL

DIGITAL PLL

N = 1 TO 10

N

CLK_IN × 2

Figure 25. Clock Generation Block Diagram

Rev. 0 | Page 14 of 52

Data Sheet

SSM2529

sampling rate is 48 kHz. In application mode, the 3 dB cutoff

frequency varies from 50 Hz to 750 Hz, which is selected by using

the HPFCUT bits (Register 0x15, Bits[5:2]).

PDM MODE SETUP AND CONTROL

If the ADDR pin is tied to DVDD while in standalone mode, or

the PDM_MODE bit (Register 0x01, Bit 7) is set to 1 while in I²C

mode, the SSM2529 operates in PDM mode. In PDM mode, the

SDATA pin receives the 1-bit PDM input to the DAC, and the

BCLK pin provides the system clock for registering the input data.

The PDM data input is registered directly on each clock edge.

10

0

–10

–20

–30

–40

–50

–60

The left or right data can be registered on either the rising or falling

BCLK edge in both standalone mode or in I²C mode by setting

the BCLK_EDGE bit (Register 0x03, Bit 0).

When the part is in standalone mode and the PDM interface is

selected, pull the MCLK pin to logic level low to register the left

channel data (L data) on the rising BCLK edge, and the right

channel data (R data) on the falling BCLK edge. When the

MCLK pin is connected to logic high, the R data is registered

on the rising BCLK edge, and the L data is registered on the

falling BCLK edge.

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (kHz)

Figure 27. High-Pass Filter Response from HPFCUT Adjustment

When this part is in I²C PDM mode, if BCLK_EDGE = 0, the L

data is registered on the rising BCLK edge and the R data is

registered on the falling BCLK edge. If BCLK_EDGE = 1, the L

data is registered on the falling BCLK edge, and the R data is

registered on the rising BCLK edge.

Table 10. HPF_CTRL Register

D7

D6

D5 D4 D3 D2 D1

D0

Reserved

HPFCUT HPFOR

HPFEN

Table 11. Bit Description of HPF_CTRL Register

Bit Name

HPFCUT[3:0] HPF cut-off

frequency selection

Description

Settings

Table 9. PDM Timing Parameters

See the Table 66

Limit

Parameter

t_FALL

T_MIN

T_MAX

10

Unit

ns

Description

HPFOR

HPF mode selection 0: audio mode (cutoff

frequency is 3.7 Hz)

Clock fall time

Clock rise time

Data setup time

Data hold time

t_RISE

10

ns

1: application mode (cut-

off frequency selectable)

t_SETUP

t_HOLD

10

7

ns

HPFEN

HPF enable

0: disable

1: enable

BCLK

t_SETUP

FULLY PROGRAMMABLE SEVEN-BAND EQUALIZER

t_HOLD

SDATA

The programmable seven-band equalizer comprises five biquad

filters (Band 1 to Band 5) and two first-order IIR filters (Band 6

and Band 7). Figure 28 shows the system block diagram.

L

R

L

R

DATA

Figure 26. PDM Input Format

All filter coefficients are programmable via the corresponding

registers. When not all five midfrequency bands are needed, the

filter bank can be configured as other filters, such as de-emphasis

and notch filters.

HIGH-PASS FILTER

The audio processing block contains a configurable first-order,

high-pass filter. When the high-pass filter is enabled, the dc

values are continuously calculated and subtracted from the

input signal. By setting HPFOR (Register 0x15, Bit 1), the last

calculated dc value is stored. When the high-pass filter is

disabled, the stored value is still subtracted from the input

signal until the HPFOR is cleared to 0.

To operate as a seven-band equalizer, the two first-order IIR filters

are usually configured as one low-pass shelving filter and one high-

pass shelving filter, and the biquad filters are configured as peak

filters. By using the coefficient registers, the cutoff frequencies

and peak gains of the shelving filters and the center frequencies and

bandwidths of the peak filters are programmable. For frequency

bands lower than 200 Hz, the low-pass shelving filter is suggested.

The high-pass filter can work in audio mode or application

mode, as configured by the HPF_CTRL register. In audio mode,

the high-pass filter’s 3 dB cutoff frequency is 3.7 Hz when the

FIRST ORDER

IIR 1

FIRST ORDER

IIR 1

BIQUAD1

BIQUAD2

BIQUAD3

BIQUAD4

BIQUAD5

SEVEN-BAND EQUALIZER

Figure 28. System Block Diagram

Rev. 0 | Page 15 of 52

SSM2529

Data Sheet

The common biquad filter transfer function is

Table 14. Bit Description of EQ_CTRL1 Register

Bit Name

Description

Settings

P0 + P1× Z⁻¹+ P2× Z⁻²

H(z) =

EQ_RESERVED

EQ_UPDING

Reserved

1− D1× Z⁻¹− D2× Z⁻²

EQ coefficient

updating flag

0: EQ coefficients

updating

The first-order IIR filter transfer function is

P0 + P1× Z⁻¹

1: None

H(z) =

1− D1× Z⁻¹

EQ_UPD_CLR

EQ coefficient update

clear

0: normal operation

1: interrupt

In normal mode, the supported coefficients range from −4 to

approximately +4. For equalizer mode, this range means that

the cutoff and center frequencies can vary from 40 Hz to

12 kHz when the input sampling rate is 48 kHz, and the peak

gain varies from −18 dB to +18 dB.

coefficient update

EQ_FORMAT

EQ_UPD

EQ coefficient format

selection

0: normal

1: large gain

EQ coefficient registers 1: update

update flag

0: none

The EQ_FORMAT bit in Register 0x54 defines the coefficient

format. The default value is 0, and the corresponding format is

Q3.13. Setting this bit to 1 achieves a larger coefficient range (from

−8 to approximately +8), which enables a larger gain boost or

decreases the range.

Table 15. EQ_CTRL2 Register

D7

D6

D5

D4

D3

D2

D1

D0

EQEN EQBP7 EQBP6 EQBP5 EQBP4 EQBP3 EQBP2 EQBP1

Table 16. Bit Description of EQ_CTRL2 Register

Online coefficient update is supported. If the filter bank

coefficients are updated when the EQ is operating, set the

EQ_UPD bit after the coefficient is written. The coefficient

update procedure requires approximately 0.05 ms to complete.

The read only bit, EQ_UPDING, in the EQ_CTRL1 register

represents the coefficient update status. If the system clock is

removed during this period, the update procedure cannot be

finished, and the EQ_UPD_CLR bit must be set to cancel this

update.

Bit Name

Description

Settings

EQEN

EQ enabled

0: EQ disabled

1: EQ enabled

EQBP7

EQBP6

EQBP5

EQBP4

EQBP3

EQBP2

EQBP1

EQ Band 7 bypass

when EQ enabled

0: no bypass

1: bypass EQ Band 7

0: no bypass

1: bypass EQ Band 6

0: no bypass

1: bypass EQ Band 5

0: no bypass

1: bypass EQ Band 4

0: no bypass

1: bypass EQ Band 3

0: no bypass

1: bypass EQ Band 2

0: no bypass

1: bypass EQ Band 1

EQ Band 6 bypass

when EQ enabled

EQ Band 5 bypass

when EQ enabled

The filter bank can be disabled, and all seven bands can be

bypassed separately to save power. The corresponding bits are

EQEN and EQBP1 to EQBP7 in Register 0x55.

EQ Band 4 bypass

when EQ enabled

EQ Band 3 bypass

when EQ enabled

Table 12. EQ Coefficients Registers

EQ Band 2 bypass

when EQ enabled

Register

Address Register Name

Description

EQ Band 1 bypass

when EQ enabled

0x16

0x17

0x18

0x19

0x1A

0x1B

...

EQ1_COEF0_HI[15:8] EQ Band 1, Coefficient 0 MSB

EQ1_COEF0_LO[7:0] EQ Band 1, Coefficient 0 LSB

EQ1_COEF1_HI[15:8] EQ Band 1, Coefficient 1 MSB

EQ1_COEF1_LO[7:0] EQ Band 1, Coefficient 1 LSB

EQ1_COEF2_HI[15:8] EQ Band 1, Coefficient 2 MSB

EQ1_COEF2_LO[7:0] EQ Band 1, Coefficient 2 LSB

The typical characteristic of each EQ band is shown in Figure 29 to

Figure 36.

15

10

5

...

0x52

0x53

EQ7_COEF2_HI[15:8] EQ Band 7, Coefficient 2 MSB

EQ7_COEF2_LO[7:0] EQ Band 7, Coefficient 2 LSB

Table 13. EQ_CTRL1 Register

0

D7 D6 D5 D4 D3

D2

D1

D0

EQ_RESERVED

EQ_

UPDING CLR

EQ_UPD_ EQ_

EQ_

–5

–10

–15

FORMAT UPD

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 29. Low-Pass Shelving Filter Frequency Response Across Bandwidth

Settings

Rev. 0 | Page 16 of 52

Data Sheet

SSM2529

15

10

5

15

10

5

0

–5

–10

–15

–5

–10

–15

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 30. Low-Pass Shelving Filter Frequency Response Across Gain Settings

Figure 33. Peak Filter Frequency Response Across Gain Settings

15

20

10

0

10

5

–10

–20

–30

–40

–50

–60

0

–5

–10

–15

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 34. Notch Filter Response (A0 = +1982 to +2048, A1 = −2041 to +2048,

Bandwidth = 251 Hz, Center Frequency = 631 Hz)

Figure 31. Peak Filter Frequency Response with Different Center Frequencies

15

10

5

15

10

5

0

–5

–10

–15

–5

–10

–15

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 35. Treble Band Frequency Response Across Bandwidth Settings

Figure 32. Peak Filter Frequency Response Across Bandwidth Settings

Rev. 0 | Page 17 of 52

SSM2529

Data Sheet

15

10

5

The overall DRC characteristics are illustrated in Figure 37. A

number of threshold levels (referred to the input) are used, which

are defined as the limiter threshold (LT), compressor threshold

(CT), expander threshold (ET), noise gate threshold (NT),

maximum output signal amplitude (SMAX), and minimum output

signal amplitude (SMIN). The corresponding bits are DRC_LT,

DRC_CT, DRC_ET, DRC_NT, DRC_SMAX, and DRC_SMIN

and can be found in Register 0x59 to Register 0x5D.

0

–5

–10

NT

ET

CT

LT

POINT1

(LT, SMAX)

SMAX

–15

1k

LINEAR

POINT2 (CT, CT)

10k

100k

1M

10M

100M

FREQUENCY (Hz)

LIMITER

COMPRESSOR

Figure 36. Treble Band Frequency Response Across Gain Settings

DYNAMIC RANGE CONTROL

POINT3 (ET, ET)

The dynamic range control function is used to alter (usually

reduce) the dynamic range of the audio signal so that a loud

signal can be heard without disturbing the hearing perception,

and a weak signal can still be heard. In addition, very large signals

and very weak signals are usually treated with different methods

to ensure the overall sound quality. The DRC functions include the

following:

EXPANDER

NOISE GATE

SMIN

POINT4 (NT, SMIN)

INPUT

WITHOUT DRC

WITH DRC

Figure 37. DRC Input/Output Relationship

•

Limiter

DRC MODE CONTROL

Compressor

Expander

Noise Gate

The DRC_EN bits in Register 0x60 control the DRC. The noise

gating function can be disabled by setting the NG_EN bit in

Register 0x60.

The dynamic range is not altered when the signal level is in the

middle. These functions can be enabled or disabled individually.

Table 17. DRC Mode Control Register

D7

VBAT_ LIM_ LIM_ COMP_ EXP_EN NG_EN DRC_EN

EN SRC EN EN

D6

D5

D4

D3

D2

D1 D0

Limiter

If the input audio samples are large, the output is clipped at a

predefined level so that the speakers are not overdriven.

Table 18. Bit Description of DRC Mode Control Register

If the ADC power tracking function is enabled, the maximum

output level is set automatically to correspond to the speaker

SPKVDD power.

Bit Name

Description

Settings

0: disable

1: enable

0: peak

VBAT_EN

VBAT tracking enabled

LIM_SRC

LIM_EN

COMP_EN

EXP_EN

NG_EN

Limiter source selection

Limiter enabled

Compressor

1: RMS

The compressor is used to reduce the signal dynamic range

when the input level is large and within predefined boundaries.

This helps reduce the loudness when the signal level is high.

0: disable

1: enable

0: disable

1: enable

0: disable

1: enable

0: disable

1: enable

0: disable

1: enable

Compressor disabled

Expander enabled

Noise gating enabled

DRC enabled

Expander

The expander is used to increase the signal dynamic range when

the input signal level is small and within predefined upper and

lower boundaries. This helps increase the loudness when the

signal is weak.

Noise Gate

DRC_EN

When the signal level is lower than a predefined threshold level,

it is treated as noise. Under this condition, the output is set to zero.

Rev. 0 | Page 18 of 52

Data Sheet

SSM2529

Figure 38 shows a high level system block diagram of the DRC

function.

Static Curve

The static curve is the DRC core function used to define the

targeted input and output relationship. The role for the DRC

block is to find the appropriate gain values with the various signal

levels. To change the dynamic range of the original audio signal,

the gain values vary with the input signal level.

x

(n)

y (n)

R

DELAY

LEVEL

MEASUREMENT

STATIC

CURVE

GAIN

SMOOTH

An example of such a static curve is given in Figure 39, which

shows the input and output signal levels. The blue line shows a

linear relationship where the output dynamic range is identical

to the input dynamic range. The red line shows a different output

dynamic range from the input. Furthermore, this curve indicates

that the signal dynamic range is larger when the input signal is low.

x (n)

y (n)

L

DELAY

Figure 38. DRC Block Diagram

Level Measurement

RELATIONSHIP BETWEEN INPUT AND OUTPUT WITHOUT DRC

The DRC level measurement includes the peak and rms value

measurements. The parameters that affect the peak measurement

are attack time and release time (AT and RT). The parameter that

affects the rms measurement is average time (T_AV). The attack time

can vary from 0 ms to 1.536 sec; the release time and average

time can vary from 0 ms to 24.576 sec. The corresponding bits

are PEAK_ATT, PEAK_REL, and DRCLELTAV and can be found

in Register 0x56 and Register 0x57.

RELATIONSHIP BETWEEN INPUT AND OUTPUT WITH DRC

0

–10

S

MAX

–20

–30

–40

–50

–60

–70

–80

–90

–100

CT

ET

Table 19. DRC_CTRL1 Register

D7

D6

D5

D4

D3

D2

D1

D0

S

MIN

Reserved

DRCLELTAV[3:0]

Table 20. Bit Description of DRC_CTRL1 Register

NT

ET

CT

LT

Bit Name

Description

Settings

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

INPUT (dBFS)

DRCLELTAV[3:0] DRC rms detector

average time

0000: 0 ms

0001: 0.075 ms

Figure 39. DRC Output vs. Input

0011: 0.30 ms (default)

1111: 24.576 sec

Figure 40 shows the gain values at various input signal levels.

0

–10

Table 21. DRC_CTRL2 Register

DRC GAIN

–20

–30

–40

–50

–60

–70

–80

–90

D7

D6

D5

D4

D3

D2

D1

D0

PEAK_ATT[3:0]

PEAK_REL[3:0]

Table 22. Bit Description of DRC_CTRL2 Register

Bit Name

PEAK_ATT[3:0]

Description

Settings

DRC peak detector

attack time

0000: 0 ms

0001: 0.09 ms

0010: 0.19 ms

0011: 0.37 ms

0100: 0.75 ms

0101: 1.5 ms

0110: 3.0 ms

0111: 6.0 ms

…

NT

ET

CT

LT

–100

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

INPUT (dBFS)

Figure 40. DRC Gain vs. Input

DRC Static Curve Function

1111: 1.536 sec

0000: 0 ms

0001: 1.5 ms

0010: 3 ms

0011: 6 ms

0100: 12 ms

…

A number of threshold levels (referred to the input) are used in

Figure 39 and Figure 40; these levels are defined as the limiter

threshold (LT), compressor threshold (CT), expander threshold

(ET), noise gate threshold (NT), maximum output signal amplitude

(SMAX), and minimum output signal amplitude (SMIN). The

corresponding bits, DRC_LT, DRC_CT, DRC_ET, DRC_NT,

DRC_SMAX, DRC_SMIN, can be found in Register 0x59 to

Register 0x5D.

PEAK_REL[3:0]

DRC peak detector

decay time

1111: 24.576 sec

Rev. 0 | Page 19 of 52

SSM2529

Data Sheet

Table 23. DRC_CURVE1 Register

Table 31. DRC_CURVE5 Register

D7 D6 D5 D4 D3

Reserved

D7

D6

D5

D4

D3

D2

D1

D0

D2

D1

D0

Reserved

DRC_LT[6:0]

DRC_SMIN[3:0]

Table 24. Bit Description of DRC_CURVE1 Register

Bit Name Description Settings

Table 32. Bit Description of DRC_CURVE5 Register

Bit Name

Description

Settings

DRC_LT[6:0] DRC limiter threshold 0000000: +6 dB

0000001: +5.5 dB

DRC_SMIN[3:0] DRC minimum output signal

level

0000: −51 dB

0001: −54 dB

−0.5 dB step to

1010000: −35 dB

−3 dB step to

1111: −96 dB

Table 25. DRC_CURVE2 Register

DRC Gain Smooth

D7

D6

D5

D4

D3

D2

D1

D0

Before the gain calculated by the static curve function multiplies

with the input signal, smooth it to ensure that it does not change

rapidly for this can lead to noise.

Reserved

DRC_CT[6:0]

Table 26. Bit Description of DRC_CURVE2 Register

Bit Name

Description

Settings

The gain smooth is affected by its attack and decay time

parameters. The attack time can vary from 0 ms to 1.536 sec,

while the decay time can vary from 0 ms to 24.576 sec. The

corresponding bits are DRC_ATT and DRC_DEC and can be

found in Register 0x58.

DRC_CT[6:0] DRC compressor

threshold

0000000: +6 dB

0000001: +5.5 dB

−0.5 dB step to

1010000: −35 dB

Table 27. DRC_CURVE3 Register

D7

Table 33. DRC_CTRL3 Register

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

DRC_SMAX[6:0]

DRC_ATT[3:0]

DRC_DEC[3:0]

Table 28. Bit Description of DRC_CURVE3 Register

Table 34. Bit Description of DRC_CTRL3 Register

Bit Name

Description

Settings

Bit Name

Description

Settings

DRC_SMAX[6:0]

DRC maximum output

signal amplitude

0000000: +6 dB

0000001: +5.5 dB

−0.5 dB step to

1010000: −35 dB

DRC_ATT[3:0] DRC attack time

0000: 0 ms

0001: 0.1 ms

0010: 0.19 ms

0011: 0.37 ms

0100: 0.75 ms

0101: 1.5 ms

0110: 3 ms

0111: 6 ms

…

Table 29. DRC_CURVE4 Register

D7 D6 D5 D4 D3

DRC_NT[3:0]

D2

D1

D0

DRC_ET[3:0]

Table 30. Bit Description of DRC_CURVE4 Register

Bit Name

Description

Settings

1111: 1.536 sec

0000: 0 ms

0001: 1.5 ms

0010: 3 ms

0011: 6 ms

0100: 12 ms

…

DRC_NT[3:0]

DRC noise gating threshold

0000: −51 dB

0001: −54 dB

−3 dB step to

1111: −96 dB

DRC_DEC[3:0] DRC decay time

DRC_ET[3:0]

DRC expander threshold

0000: −36 dB

0001: −39 dB

−3 dB step to

1111: −81 dB

1111: 24.576 sec

Rev. 0 | Page 20 of 52

Data Sheet

SSM2529

DRC Hold Time

of the loudspeaker. The temperature prediction method is based

on the general thermal model of the loudspeaker.

Two types of hold time are used in the DRC. One is used in normal

mode to prevent the calculated gain from increasing too quickly,

and the other is used during DRC transiting from expander

mode to noise gating mode to prevent the DRC from entering

noise gating too quickly. The DRCHTNOR and DRCHTNG bits

in Register 0x5E set which type is used.

In this thermal model, R1, R2, C1, and C2 are temperature

coefficients derived by measuring loudspeaker characteristics.

They are set by the I²C control registers, Register 0x84 to

Register 0x8B (SP_CF1_H, SP_CF1_L, SP_CF2_H, SP_CF2_L,

SP_CF3_H, SP_CF3_L, SP_CF4_H and SP_CF4_L).

Other critical parameters needed include ambient temperature,

dc resistance of the loudspeaker, and temperature coefficient of

the voice coil material. These parameters are set by Register 0x81 to

Register 0x83 (TEMP_AMBIENT, SPKR_DCR, and SPKR_TC).

Table 35. DRC_HOLD_TIME Register

D7

D6

D5

D4

D3

D2

D1

D0

DRCHTNG[3:0]

DRCHTNOR[3:0]

Table 36. Bit Description of DRC_HOLD_TIME Register

After running the thermal model by setting the speaker protection

enable bit (SP_EN, Register 0x80), the speaker voice coil temperature

status and speaker magnet temperature status can be obtained

by an I²C reading of the SPKR_TEMP register (Register 0x8C)

and the SPKR_TEMP_MAG register (Register 0x8D). The user

sets the voice coil temperature threshold (maximum speaker

voice coil temperature before gain reduction occurs) by using

the MAX_SPKR_TEMP register (Register 0x8E). If this threshold

is crossed, the output volume is reduced according to the speed

set by the SP_AR bits (speaker protection gain reduction attack

rate, Register 0x8F, Bits[7:4]) and the SP_RR bits (speaker

protection gain reduction release rate, Register 0x8F, Bits[3:0]).

Bit Name

Description

Settings

DRCHTNG[3:0]

DRC hold time for

noise gating

0000: 0 ms

0001: 0.67 ms

xxxx: double time

0111: 42.67 ms (default)

1111: 43.7 sec

0000: 0 ms

0001: 0.67 ms

0010: 1.33 ms

0011: 2.67 ms

0100: 5.33 ms

….

DRCHTNOR[3:0] DRC hold time for

normal operation

POWER SUPPLIES

1111: 43.7 sec

The SSM2529 has two internal power supplies that must be

provided: SPKVDD and DVDD. The SPKVDD supply powers

to the full bridge power stage of the MOSFET and its associated

drive, control, and protection circuitry. SPKVDD can operate

from 2.5 V to 5.5 V and must be present to obtain audio output.

Lowering the SPKVDD supply results in lower output power

and correspondingly lower power consumption, and it does not

affect audio performance.

GAIN RIPPLE REMOVE

Due to the swing of the peak/rms value detected by the level

measurement, the gain to apply to the input signal has a little

ripple, which leads to the modulation of the output signal. The

ripple remove function suppresses this effect. The ripple

threshold is defined by the DRCRRH bit in Register 0x5F.

Table 37. DRC_RIPPLE_CTRL Register

DVDD provides power to the digital logic and analog components.

DVDD can operate from 1.08 V to 1.98 V, and it must be provided

to write to the I²C or to obtain audio output. Lowering the supply

voltage results in lower power consumption; however, it also

results in lower audio performance.

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

DRCRRH[1:0]

Table 38. Bit Description of DRC_RIPPLE_CTRL Register

Bit Name

Description

Settings

DRCRRH[1:0]

DRC ripple

remove threshold

00: 0 dB

POWER CONTROL

01: 0.28 dB

10: 0.47 dB

11: 0.75 dB (default)

The SSM2529 includes various programmable power-down modes

that are contained in the first I²C register (Register 0x00), power/

reset control. By default, the IC is set in software power-down,

which is the I²C programmable master power-down. Only I²C

functionality operates when in software power-down mode.

SPEAKER PROTECTION

The IC includes a speaker temperature prediction module to

protect the loudspeaker. Loudspeakers can be damaged when the

voice coil overheats due to operation higher than the rated

power. Typically, the thermal time constants of the loudspeakers

are long, approximately 1 sec for voice coil and 60 sec for core.

They can handle momentary power spikes without overheating;

however, they cannot handle sustained high power. The speaker

protection method used in the IC can reduce the volume when

the temperature of the loudspeaker exceeds the temperature

threshold set by the user while preserving the maximum power

The SSM2529 also contains a smart power-down feature that,

when enabled, looks at the incoming digital audio. In addition,

if the audio is zero for 1024 consecutive samples, regardless of

sample rate, it puts the IC in a smart power-down state. In this

state, all circuitry, except the I²S and I²C ports, are placed in a

low power state. After a single nonzero input is received, the

SSM2529 leaves this state and resumes normal operation.

Rev. 0 | Page 21 of 52

SSM2529

Data Sheet

Both SDA and SCL must have a 2.2 kΩ pull-up resistor on the lines

connected to them. The voltage on these signal lines must not

be more than 3.6 V.

POWER-ON RESET/VOLTAGE SUPERVISOR

The SSM2529 includes an internal power-on reset and voltage

supervisor circuit. This circuit provides an internal reset to all

circuitry during initial power-up. It also monitors the power

supplies to the IC, and it mutes the outputs and issues a reset

when the voltages are lower than the minimum operating range.

This ensures that no damage due to low voltage operation occurs

and that no pops can occur under nearly any power removal

conditions.

Table 40. I²C Address Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

0

1

0

1

0

R/W

Addressing

Initially, each device on the I²C bus is in an idle state, monitoring

the SDA and SCL lines for a start condition and the proper address.

The I²C master initiates a data transfer by establishing a start

condition, defined by a high-to-low transition on SDA, while

SCL remains high. This indicates that an address/data stream

follows. All devices on the bus respond to the start condition

STANDALONE MODE

When the SA_MODE pin is pulled high, the SSM2529 can operate

without any I²C control. In this mode, the automatic sample rate

detection and smart power-down are always enabled. Volume

Control A and Volume Control B can be controlled via the SCL

and SDA pins.

W

and shift the next eight bits (the 7-bit address plus the R/ bit)

MSB first. The device that recognizes the transmitted address

responds by pulling the data line low during the ninth clock

pulse. The device address for the SSM2529 is 0x34. The ninth bit

is known as the acknowledge bit. All other devices withdraw from

the bus at this point and return to the idle condition.

In standalone mode, the DRC function is disabled. The EQ and

HPF are also disabled. When ADDR = 1, the input interface is

PDM. Otherwise, I²S and TDM serial interface formats can be

selected via MCLK. In standalone mode, the working clock is

generated by the internal PLL.

W

The R/ bit determines the direction of the data. A Logic 0 on the

Table 39. Standalone Mode Pin Configuration

LSB of the first byte means that the master writes information to

the peripheral, whereas a Logic 1 means that the master reads

information from the peripheral after writing the subaddress and

repeating the start address. A data transfer takes place until a

stop condition is encountered. A stop condition occurs when

SDA transitions from low to high while SCL is held high. The

timing for the I²C port is shown in Figure 3.

Conventional

Operation Pin

SA_MODE = 1

SCL

Volume Control A

SDA

Volume Control B

STDBN

0: shutdown/mute

1: normal operation

ADDR

BCLK

1: PDM

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, the SSM2529 immediately

jumps to the idle condition. During an SCL high period, issue only

one start condition, one stop condition, or a single stop condition

followed by a single start condition. If an invalid subaddress is

issued, the SSM2529 does not issue an acknowledge and returns to

the idle condition. If the highest subaddress is exceeded while in

auto-increment mode, one of two actions is taken. In read mode,

the SSM2529 outputs the highest subaddress register contents

until the master device issues a no acknowledge, indicating the

end of the read. When the SDA line is not pulled low on the

ninth clock pulse of SCL, a no acknowledge occurs. If the

highest subaddress location is reached while in write mode, the

data for the invalid byte is not loaded into any subaddress

register, a no acknowledge is issued by the SSM2529, and the

part returns to the idle condition.

0: I²S/TDM

0: 16 BCLK cycles provided by PLL

1: 32 BCLK cycles provided by PLL

Clock: 32 BCLK cycles provided off chip

0: I²S (ADDR = 0) or PDM L channel (ADDR = 1)

1: TDM (ADDR = 0) or PDM R channel (ADDR = 1)

MCLK

I²C PORT

The SSM2529 supports a 2-wire serial (I²C-compatible) micro-

processor bus driving multiple peripherals. Two pins, serial data

(SDA) and serial clock (SCL), carry information between the

SSM2529 and the system I²C master controller. The SSM2529 is

always a slave on the bus, meaning that it cannot initiate a data

transfer. Each slave device is recognized by a unique address. The

address byte format is shown in Table 40. The address resides in

the first seven bits of the I²C write. The LSB of this byte either

sets a read or write operation. Logic Level 1 corresponds to a read

operation, and Logic Level 0 corresponds to a write operation The

full byte addresses are shown in Figure 41, where the subaddresses

are automatically incremented at word boundaries, and can be

used for writing large amounts of data to contiguous memory

locations. This increment happens automatically after a single-

word write unless a stop condition is encountered. A data

transfer is always terminated by a stop condition.

Rev. 0 | Page 22 of 52

Data Sheet

SSM2529

I²C Read and Write Operations

W

followed by the chip address byte with the R/ bit set to 1 (read).

This causes the SSM2529 SDA to reverse and begin driving data

back to the master. The master then responds every ninth pulse

with an acknowledge pulse to the SSM2529.

Table 42 shows the timing of a single-word write operation.

Every ninth clock, the SSM2529 issues an acknowledge by

pulling SDA low.

Table 42 to Table 45 use the abbreviations shown in Table 41.

Table 43 shows the timing of a burst mode write sequence as an

example where the target destination registers are two bytes. The

SSM2529 knows to increment its subaddress register every byte

because the requested subaddress corresponds to a register or

memory area with a byte word length.

Table 41. Symbols for Table 42 to Table 45

Symbol

Meaning

S

Start bit

P

Stop bit

The timing of a single-word read operation is shown in Table 44.

A_M

A_S

Acknowledge by master

Acknowledge by slave

W

Note that the first R/ bit is 0, indicating a write operation. This

is because the subaddress still needs to be written to set up the

internal address. After the SSM2529 acknowledges the receipt of

the subaddress, the master must issue a repeated start command

SCK

SDA

R/W

ACK

START BY

MASTER

FRAME 2

SUBADDRESS BYTE

FRAME 1

CHIP ADDRESS BYTE

SCK

(CONTINUED)

SDA

(CONTINUED)

ACK

STOP BY

MASTER

FRAME 3

DATA BYTE 1

FRAME 4

DATA BYTE 2

Figure 41. I²C Read and Write Timing

Table 42. Single-Word I²C Write Format

IC Address (7 Bits) R/ = 0

S

A_S

Subaddress (8 bits)

A_S

Data Byte 1 (8 Bits)

P

W

Table 43. Burst Mode I²C Write Format

Chip address, R/ = 0 A_S

S

Subaddress

A_S

Data-Word 1

A_S

Data-Word 2

A_S

…

P

W

Table 44. Single-Word I²C Read Format

Chip address, R/ = 0 A_SSubaddress

S

A_S

S

Chip address, R/ = 1

A_SData Byte 1

A_MData Byte N

P

W

Table 45. Burst Mode I²C Read Format

Chip address, R/ = 0 A_SSubaddress

S

A_S

S

Chip address, R/ = 1

A_S

Data-Word 1

A_M

…

P

W

Rev. 0 | Page 23 of 52

SSM2529

Data Sheet

REGISTER SUMMARY

The SSM2529 contains eighteen 8-bit registers that can be accessed via the I²C port. See Table 46 for the control register mapping. The

register settings are described in detail in Table 47 through Table 159.

Table 46.

Hex Name

Bits Bit 7

Bit 6

APWDN_ANA APWDN_EN

PDM_FS PDB_ADC

Bit 5

Bit 4

Bit 3

Bit 2

MCS

Bit 1

EDGE

Bit 0

Reset RW

0x23 RW

0x20 RW

0x02 RW

00 PWR_CTRL

01 SYS_CTRL

02 SAI_FMT1

03 SAI_FMT2

[7:0] SYS_RST

[7:0] PDM_MODE

LP_MODE

BCLK_RATE

SAI

SPWDN

ASR

BCLK_GEN

[7:0]

SDATA_FMT

SR

[7:0] LPST

LR_SEL

CH_SEL_R

LRCLK_MODE LRCLK_POL

SAI_MSB

BCLK_TDMC BCLK_EDGE 0x00 RW

04 Channel mapping [7:0]

control

CH_SEL_L

0x10 RW

05 VOL_BF_FDSP

06 VOL_AF_FDSP

[7:0]

DIG_VOL

PDP_VOL

Reserved

0x40 RW

0x20 RW

07 Volume and mute [7:0] CLK_LOSS_DET

control

SR_AUTO

DPLL_REF_SEL

PDP_VOL_

FORCE

DIG_VOL_

FORCE

ANA_GAIN

08 DPLL_CTRL

09 APLL_CTRL1

0A APLL_CTRL2

0B APLL_CTRL3

0C APLL_CTRL4

0D APLL_CTRL5

0E APLL_CTRL6

0F FAULT_CTRL1

10 FAULT_CTRL2

14 DEEMP_CTRL

15 HPF_CTRL

[7:0] Reserved

DPLL_NDIV

0x00 RW

0x30 RW

0x000 RW

0x4C RW

[7:0]

M_HI

M_LO

N_HI

[7:0]

N_LO

[7:0] Reserved

R

X

Type

COREN

OT

[7:0]

FSYS_DPLL

Reserved

AR_TIME

Reserved

DPLL_BYPASS APLL_BYPASS DPLL_LOCK

APLL_LOCK

CLK_LOSS

PLLEN

OC

[7:0]

PDB_LINE

MRCV

PDB_ZC

[7:0] Reserved

MAX_AR

ARCV

[7:0]

DEEMP_FS

HPFOR

DEEMP_EN 0x00 RW

HPFEN

Reserved

HPFCUT

0x00 RW

16 EQ1_COEF0_HI

EQ1_COEF0_HI

EQ1_COEF0_LO

EQ1_COEF1_HI

EQ1_COEF1_LO

EQ1_COEF2_HI

EQ1_COEF2_LO

EQ1_COEF3_HI

EQ1_COEF3_LO

EQ1_COEF4_HI

EQ1_COEF4_LO

EQ2_COEF0_HI

EQ2_COEF0_LO

EQ2_COEF1_HI

EQ2_COEF1_LO

EQ2_COEF2_HI

EQ2_COEF2_LO

EQ2_COEF3_HI

EQ2_COEF3_LO

EQ2_COEF4_HI

EQ2_COEF4_LO

EQ3_COEF0_HI

EQ3_COEF0_LO

EQ3_COEF1_HI

EQ3_COEF1_LO

EQ3_COEF2_HI

EQ3_COEF2_LO

EQ3_COEF3_HI

EQ3_COEF3_LO

EQ3_COEF4_HI

EQ3_COEF4_LO

EQ4_COEF0_HI

EQ4_COEF0_LO

EQ4_COEF1_HI

17 EQ1_COEF0_LO [7:0]

18 EQ1_COEF1_HI [7:0]

19 EQ1_COEF1_LO [7:0]

1A EQ1_COEF2_HI [7:0]

1B EQ1_COEF2_LO [7:0]

1C EQ1_COEF3_HI [7:0]

1D EQ1_COEF3_LO [7:0]

1E EQ1_COEF4_HI [7:0]

1F EQ1_COEF4_LO [7:0]

20 EQ2_COEF0_HI [7:0]

21 EQ2_COEF0_LO [7:0]

22 EQ2_COEF1_HI [7:0]

23 EQ2_COEF1_LO [7:0]

24 EQ2_COEF2_HI [7:0]

25 EQ2_COEF2_LO [7:0]

26 EQ2_COEF3_HI [7:0]

27 EQ2_COEF3_LO [7:0]

28 EQ2_COEF4_HI [7:0]

29 EQ2_COEF4_LO [7:0]

2A EQ3_COEF0_HI [7:0]

2B EQ3_COEF0_LO [7:0]

2C EQ3_COEF1_HI [7:0]

2D EQ3_COEF1_LO [7:0]

2E EQ3_COEF2_HI [7:0]

2F EQ3_COEF2_LO [7:0]

30 EQ3_COEF3_HI [7:0]

31 EQ3_COEF3_LO [7:0]

32 EQ3_COEF4_HI [7:0]

33 EQ3_COEF4_LO [7:0]

34 EQ4_COEF0_HI [7:0]

35 EQ4_COEF0_LO [7:0]

36 EQ4_COEF1_HI [7:0]

Rev. 0 | Page 24 of 52

Data Sheet

SSM2529

Hex Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset RW

0x00 RW

0x88 RW

0x00 RW

0x3C RW

0x00 RW

0x19 RW

0x40 RW

0x08 RW

0x3F RW

0x81 RW

0x00 RW

0x55 RW

0x01 RW

0x22 RW

0x02 RW

0x09 RW

37 EQ4_COEF1_LO [7:0]

38 EQ4_COEF2_HI [7:0]

39 EQ4_COEF2_LO [7:0]

3A EQ4_COEF3_HI [7:0]

3B EQ4_COEF3_LO [7:0]

3C EQ4_COEF4_HI [7:0]

3D EQ4_COEF4_LO [7:0]

3E EQ5_COEF0_HI [7:0]

3F EQ5_COEF0_LO [7:0]

40 EQ5_COEF1_HI [7:0]

41 EQ5_COEF1_LO [7:0]

42 EQ5_COEF2_HI [7:0]

43 EQ5_COEF2_LO [7:0]

44 EQ5_COEF3_HI [7:0]

45 EQ5_COEF3_LO [7:0]

46 EQ5_COEF4_HI [7:0]

47 EQ5_COEF4_LO [7:0]

48 EQ6_COEF0_HI [7:0]

49 EQ6_COEF0_LO [7:0]

4A EQ6_COEF1_HI [7:0]

4B EQ6_COEF1_LO [7:0]

4C EQ6_COEF2_HI [7:0]

4D EQ6_COEF2_LO [7:0]

4E EQ7_COEF0_HI [7:0]

4F EQ7_COEF0_LO [7:0]

50 EQ7_COEF1_HI [7:0]

51 EQ7_COEF1_LO [7:0]

52 EQ7_COEF2_HI [7:0]

53 EQ7_COEF2_LO [7:0]

EQ4_COEF1_LO

EQ4_COEF2_HI

EQ4_COEF2_LO

EQ4_COEF3_HI

EQ4_COEF3_LO

EQ4_COEF4_HI

EQ4_COEF4_LO

EQ5_COEF0_HI

EQ5_COEF0_LO

EQ5_COEF1_HI

EQ5_COEF1_LO

EQ5_COEF2_HI

EQ5_COEF2_LO

EQ5_COEF3_HI

EQ5_COEF3_LO

EQ5_COEF4_HI

EQ5_COEF4_LO

EQ6_COEF0_HI

EQ6_COEF0_LO

EQ6_COEF1_HI

EQ6_COEF1_LO

EQ6_COEF2_HI

EQ6_COEF2_LO

EQ7_COEF0_HI

EQ7_COEF0_LO

EQ7_COEF1_HI

EQ7_COEF1_LO

EQ7_COEF2_HI

EQ7_COEF2_LO

54 EQ_CTRL1

[7:0]

EQ_RESERVED

EQBP6

EQ_UPDING

EQBP4

EQ_UPD_CLR EQ_FORMAT EQ_UPD

EQBP3 EQBP2 EQBP1

DRCLELTAV

55 EQ_CTRL2

[7:0] EQEN

[7:0]

EQBP7

EQBP5

56 DRC_CTRL1

57 DRC_CTRL2

58 DRC_CTRL3

59 DRC_CURVE1

5A DRC_CURVE2

5B DRC_CURVE3

5C DRC_CURVE4

5D DRC_CURVE5

Reserved

PEAK_ATT

DRC_ATT

[7:0]

PEAK_REL

DRC_DEC

[7:0]

[7:0] Reserved

[7:0]

DRC_LT

DRC_CT

DRC_SMAX

DRC_NT

RESERVED

DRCHTNG

DRC_ET

DRC_SMIN

DRCHTNOR

[7:0]

5E DRC_HOLD_TIME [7:0]

5F DRC_RIPPLE_CTRL [7:0]

Reserved

DRCRRH

DRC_EN

FDSP_EN

SP_EN

60 DRC mode control [7:0] VBAT_EN

LIM_SRC

LIM_EN

COMP_EN

Reserved

EXP_EN

NG_EN

61 FDSP_EN

[7:0]

80 SPK_PROT_EN

81 TEMP_AMBIENT [7:0]

TEMP_AMBIENT

82 SPKR_DCR

83 SPKR_TC

84 SP_CF1_H

85 SP_CF1_L

86 SP_CF2_H

87 SP_CF2_L

88 SP_CF3_H

89 SP_CF3_L

8A SP_CF4_H

8B SP_CF4_L

[7:0]

SPKR_DCR

SPKR_TC

SP_CF1_H

SP_CF1_L

SP_CF2_H

SP_CF2_L

SP_CF3_H

SP_CF3_L

SP_CF4_H

SP_CF4_L

Rev. 0 | Page 25 of 52

SSM2529

Data Sheet

Hex Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

SPKR_TEMP

Bit 2

Bit 1

Bit 0

Reset RW

8C SPKR_TEMP

[7:0]

0x00

R

8D SPKR_TEMP_MAG [7:0]

8E MAX_SPKR_TEMP [7:0]

SPKR_TEMP_MAG

MAX_SPKR_TEMP

0x64 RW

0x44 RW

8F SPK_GAIN

FF SOFT_RST

[7:0]

SP_RR

SP_AR

SOFT_RST

0x00 W

Rev. 0 | Page 26 of 52

Data Sheet

SSM2529

REGISTER DETAILS

SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL (PWR_CTRL) REGISTER

Table 47. Address: 0x00, Reset: 0x23, Name: PWR_CTRL

Bits Bit Name

Settings Description

Reset Access

7

6

5

4

SYS_RST

Software reset

Normal operation

Software reset

0x0

0x1

0x0

0x1

RW

0

1

APWDN_ANA

APWDN_EN

LP_MODE

Auto power-down mode

Only digital

0

1

Both analog and digital

Auto power-down enable

Auto power-down disabled

Auto power-down enabled

Low power mode

0

1

0

1

Normal operation

Low power operation mode; DAC runs at half speed

Master clock rate selection

Refer to Table 48

Not applicable

[3:1] MCS

000

001

010

011

100

101

110

111

Not applicable

0

SPWDN

Master software power-down

Normal operation

Software master power-down

0x1

RW

0

1

Table 48 shows the MCS bit settings available with the possible input sample rates vs. the required master clock frequency, as well as the

master clock to bit clock ratio. The b110 thru b111 settings are reserved and not available to the user.

MCLK RATIO AND FREQUENCY

Table 48. MCS Bit Field Setting—MCLK Ratio and Frequency (N/A = Not Applicable)

Setting 6

b110 thru

b111

Input Sample

Frequency, f_S(kHz)

Setting 0

b000

Setting 1

b001

Setting 2

b010

Setting 3

b011

Setting 4

b100

Setting 5

b101

8

Ratio

MCLK 6.144 MHz

768 f_S

1024 f_S

8.192 MHz

512 f_S

1536 f_S

12.288 MHz

1024 f_S

2048 f_S

16.384 MHz

1536 f_S

3072 f_S

24.576 MHz

2048 f_S

4096 f_S

32.768 MHz

3072 f_S

Reserved

11.025

12

Ratio

MCLK

Ratio

MCLK

Ratio

N/A

5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz

N/A

512 f_S

6.144 MHz

512 f_S

8.192 MHz

256 f_S

1024 f_S

12.288 MHz

768 f_S

12.288 MHz

512 f_S

1536 f_S

18.432 MHz

1024 f_S

16.384 MHz

768 f_S

2048 f_S

24.576 MHz

1536 f_S

24.576 MHz

1024 f_S

3072 f_S

38.864 MHz

2048 f_S

32.768 MHz

1536 f_S

16

384 f_S

MCLK 6.144 MHz

22.05

24

Ratio

MCLK

Ratio

MCLK

Ratio

N/A

5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz

N/A

256 f_S

6.144 MHz

256 f_S

8.192 MHz

128 f_S

512 f_S

12.288 MHz

384 f_S

12.288 MHz

256 f_S

768 f_S

18.432 MHz

512 f_S

16.384 MHz

384 f_S

1024 f_S

24.576 MHz

768 f_S

24.576 MHz

512 f_S

1536 f_S

38.864 MHz

1024 f_S

32.768 MHz

768 f_S

32

192 f_S

MCLK 6.144 MHz

44.1

Ratio

N/A

MCLK

5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz

Rev. 0 | Page 27 of 52

SSM2529

Data Sheet

Setting 6

b110 thru

b111

Input Sample

Frequency, f_S(kHz)

Setting 0

b000

Setting 1

b001

Setting 2

b010

Setting 3

b011

Setting 4

b100

Setting 5

b101

48

Ratio

MCLK

Ratio

MCLK

Ratio

MCLK

N/A

128 f_S

6.144 MHz

64 f_S

256 f_S

12.288 MHz

128 f_S

384 f_S

18.432 MHz

192 f_S

512 f_S

24.576 MHz

256 f_S

768 f_S

36.864 MHz

384 f_S

Reserved

88.2

96

5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz 33.8688 MHz

64 f_S

6.144 MHz

128 f_S

12.288 MHz

192 f_S

18.432 MHz

256 f_S

24.576 MHz

384 f_S

36.864 MHz

When using MCS = 0/64f_Smode, the chip automatically operates in low power mode.

EDGE SPEED AND CLOCKING CONTROL (SYS_CTRL) REGISTER

Table 49. Address: 0x01, Reset: 0x20, Name: SYS_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

7

PDM_MODE

PDM input enable

Disable PDM input

Enable PDM input

PDM input sample rate

About 3 MHz sample rate

About 6 MHz sample rate

ADC power down

Power down

0x0

RW

0

1

6

5

4

3

PDM_FS

0x0

0x1

0x0

RW

0

1

PDB_ADC

BCLK_RATE

BCLK_GEN

0

1

Power on

BCLK cycles per channel frame

32 cycles per channel

16 cycles per channel

Generate BCLK internally

Disabled

0

1

0

1

Enabled

[2:1] EDGE

Edge rate control

Normal operation

Low EMI mode operation

Auto sample rate

00

01

0

ASR

0

1

Sample rate setting determined by MCS register (Register 0x00, Bits[3:1])

Automatic sample rate detection

SERIAL AUDIO INTERFACE AND SAMPLE RATE CONTROL (SAI_FMT1) REGISTER

Table 50. Address: 0x02, Reset: 0x02, Name: SAI_FMT1

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

SDATA_FMT

Serial data format

I²S, BCLK delay by 1

Left justified

Right justified, 24-bit data

Right justified, 16-bit data

Serial audio interface format

Stereo I²S, left justified, right justified

TDM2

TDM4

TDM8

TDM16

Mono PCM

0x0

RW

00

01

10

11

[5:3]

SAI

0x0

RW

000

001

010

011

100

101

110

111

Reserved

Rev. 0 | Page 28 of 52

Data Sheet

SSM2529

Bits

Bit Name

Settings

Description

Sample rate selection

11.025 kHz, 12 kHz

22.05 kHz, 24 kHz

44.1 kHz, 48 kHz

96 kHz

8 kHz

16 kHz

32 kHz

Reserved

Reset

Access

[2:0]

SR

0x2

RW

000

001

010

011

100

101

110

111

SERIAL AUDIO INTERFACE CONTROL (SAI_FMT2) REGISTER

Table 51. Address: 0x03, Reset: 0x00, Name: SAI_FMT2

Bits

Bit Name

Settings

Description

Reset

Access

7

LPST

Small power stage enable

Disabled

Enabled

0x0

RW

0

1

[6:5]

LR_SEL

L/R channel selector

Select left channel

0x0

RW

00

01

10

11

Select right channel

Select (left + right)/2

Select (left − right)/2

LRCLK mode selection for TDM operation

50% duty cycle LRCLK

Pulse mode LRCLK

4

3

2

1

0

LRCLK_MODE

LRCLK_POL

SAI_MSB

0x0

RW

0

1

LRCLK polarity control

Normal LRCLK operation

Inverted LRCLK operation

SDATA bit stream order

MSB first SDATA

0

1

0

1

LSB first SDATA

BCLK_TDMC

BCLK_EDGE

BCLK cycles per frame in TDM modes select

32 BCLK cycles per slot

16 BCLK cycles per slot

BCLK active edge select

0

1

0

1

Rising BCLK edge used (if PDM_MODE = 1, L data is registered on the

rising edge, and R data is registered on the falling edge)

Falling BCLK edge used (if PDM_MODE = 1, R data is registered on the

rising edge, and L data is registered on the falling edge)

Rev. 0 | Page 29 of 52

SSM2529

Data Sheet

CHANNEL MAPPING CONTROL REGISTER

Table 52. Address: 0x04, Reset: 0x10, Name: Channel Mapping Control

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

CH_SEL_R

Right channel mapping select

0x1

RW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Channel 0 from SAI to right output

Channel 1 from SAI to right output

Channel 2 from SAI to right output

Channel 3 from SAI to right output

Channel 4 from SAI to right output

Channel 5 from SAI to right output

Channel 6 from SAI to right output

Channel 7 from SAI to right output

Channel 8 from SAI to right output

Channel 9 from SAI to right output

Channel 10 from SAI to right output

Channel 11 from SAI to right output

Channel 12 from SAI to right output

Channel 13 from SAI to right output

Channel 14 from SAI to right output

Channel 15 from SAI to right output

Left channel mapping select

[3:0]

CH_SEL_L

0x0

RW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Channel 0 from SAI to left output

Channel 1 from SAI to left output

Channel 2 from SAI to left output

Channel 3 from SAI to left output

Channel 4 from SAI to left output

Channel 5 from SAI to left output

Channel 6 from SAI to left output

Channel 7 from SAI to left output

Channel 8 from SAI to left output

Channel 9 from SAI to left output

Channel 10 from SAI to left output

Channel 11 from SAI to left output

Channel 12 from SAI to left output

Channel 13 from SAI to left output

Channel 14 from SAI to left output

Channel 15 from SAI to left output

Rev. 0 | Page 30 of 52

Data Sheet

SSM2529

VOLUME CONTROL BEFORE FDSP (VOL_BF_FDSP) REGISTER

Table 53. Address: 0x05, Reset: 0x40, Name: VOL_BF_FDSP

Bits

Bit Name

Settings

Description

Volume control before FDSP

+24 dB

+23.625 dB

+23.35 dB

+22.875 dB

+22.5 dB

...

+0.375 dB

0 dB

−0.375 dB

...

Reset

Access

[7:0]

DIG_VOL

0x40

RW

00000000

00000001

00000010

00000011

00000100

00000101

00111111

01000000

01000001

01000010

11111101

11111110

11111111

−70.875 dB

−71.25 dB

Mute

VOLUME CONTROL AFTER FDSP (VOL_AF_FDSP) REGISTER

Table 54. Address: 0x06, Reset: 0x40, Name: VOL_AF_FDSP

Bits

Bit Name

Settings

Description

Volume control after FDSP

+24 dB

+23.625 dB

+23.35 dB

+22.875 dB

+22.5 dB

...

+0.375 dB

0 dB

−0.375 dB

...

Reset

Access

[7:0]

PDP_VOL

0x40

RW

00000000

00000001

00000010

00000011

00000100

00000101

00111111

01000000

01000001

01000010

11111101

11111110

11111111

−70.875 dB

−71.25 dB

Mute

VOLUME AND MUTE CONTROL REGISTER

Table 55. Address: 0x07, Reset: 0x20, Name: Volume and Mute Control

Bits Bit Name

Settings Description

Reset Access

7

CLK_LOSS_DET

Clock loss detect enable

0x0

RW

0

1

Clock loss detect disabled

Clock loss detect enabled

Auto detected sample rate

11.025 kHz/12 kHz

22.05 kHz/24 kHz

44.1 kHz/48 kHz

96 kHz

8 kHz

16 kHz

32 kHz

Wrong sample rate

Reserved

[6:4] SR_AUTO

0x2

R

000

001

010

011

100

101

110

111

3

Reserved

0x0

RW

Rev. 0 | Page 31 of 52

SSM2529

Data Sheet

Bits Bit Name

Settings Description

PDP volume fade enable

Soft (default)

Reset Access

2

1

0

PDP_VOL_FORCE

0x0

RW

0

1

Force

DIG_VOL_FORCE

ANA_GAIN

DIG volume fade enable

Soft (default)

Force

0

1

Analog gain control

3.6 V gain

5 V gain

0

1

DPLL_CTRL REGISTER

Table 56. Address: 0x08, Reset: 0x00, Name: DPLL_CTRL

Bits

Bit Name

Settings

Description

Reset

0x0

Access

RW

7

Reserved

[6:4]

DPLL_REF_SEL

DPLL source clock selection

0x0

RW

000

001

010

Select MCLK as DPLL reference clock

Select BCLK as DPLL reference clock

Select LRCLK as DPLL reference clock

DPLL output clock frequency

[3:0]

DPLL_NDIV

0x0

RW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

Reference clock frequency × 1

Reference clock frequency × 1024

Reference clock frequency × 512

Reference clock frequency × 256

Reference clock frequency × 128

Reference clock frequency × 64

Reference clock frequency × 32

Reference clock frequency × 16

Reference clock frequency × 8

Reference clock frequency × 4

Reference clock frequency × 2

APLL_CTRL1 REGISTER

Table 57. Address: 0x09, Reset: 0x00, Name: APLL_CTRL1

Bits

Bit Name

Description

Reset

Access

[7:0]

M_HI

Denominator (M) of the fractional APLL upper byte

0x00

RW

APLL_CTRL2 REGISTER

Table 58. Address: 0x0A, Reset: 0x00, Name: APLL_CTRL2

Bits

Bit Name

Description

Reset

Access

[7:0]

M_LO

Denominator (M) of the fractional APLL lower byte

0x00

RW

APLL_CTRL3 REGISTER

Table 59. Address: 0x0B, Reset: 0x00, Name: APLL_CTRL3

Bits

Bit Name

Description

Reset

Access

[7:0]

N_HI

Numerator (N) of the fractional APLL upper byte

0x00

RW

APLL_CTRL4 REGISTER

Table 60. Address: 0x0C, Reset: 0x00, Name: APLL_CTRL4

Bits

Bit Name

Description

Reset

Access

[7:0]

N_LO

Numerator (N) of the fractional APLL lower byte

0x00

RW

Rev. 0 | Page 32 of 52

Data Sheet

SSM2529

APLL_CTRL5 REGISTER

Table 61. Address: 0x0D, Reset: 0x00, Name: APLL_CTRL5

Bits

Bit Name

Reserved

R

Settings

Description

Reset

Access

RW

7

Reserved

0x0

[6:3]

Integer part of APLL

RW

0010

0011

0100

0101

0110

0111

1000

R = 2

R = 3

R = 4

R = 5

R = 6

R = 7

R = 8

[2:1]

X

APLL input clock divider

X = 1

X = 2

X = 3

0x0

RW

00

01

10

11

X = 4

0

Type

APLL operation mode

Integer

Fractional

0

1

APLL_CTRL6 REGISTER

Table 62. Address: 0x0E, Reset: 0x30, Name: APLL_CTRL6

Bits Bit Name Settings Description

[7:6] FSYS_DPLL

Reset Access

0x0

RW

00

01

10

11

Analog OSC Clock Rate 1

Analog OSC Clock Rate 2

Analog OSC Clock Rate 3

Analog OSC Clock Rate 4

5

4

3

2

1

0

DPLL_BYPASS

APLL_BYPASS

DPLL_LOCK

APLL_LOCK

PLLEN

0x1

0x0

RW

R

0

1

Enable DPLL

Bypass DPLL (default)

0

1

Enable APLL

Bypass APLL (default)

0

1

DPLL not locked

DPLL locked

R

0

1

APLL not locked

APLL locked

RW

0

1

Disable internal PLL (default)

Enable internal PLL

COREN

Core clock enable

0

1

Core clock disable (default)

Core clock enable

Rev. 0 | Page 33 of 52

SSM2529

Data Sheet

FAULT_CTRL1 REGISTER

Table 63. Address: 0x0F, Reset: 0x00, Name: FAULT_CTRL1

Bits

Bit Name

Settings

Description

Reset Access

[7:5] Reserved

0x0

RW

4

3

2

1

0

PDB_LINE

PDB_ZC

CLK_LOSS

OC

Single end lineout enable

Disabled

Enabled

0

1

Lineout calibration enable

Disabled

Enabled

0x0

RW

R

0

1

Clock for DAC and Class-D lost

Normal operation

Loss of clock signal

Right channel overcurrent fault

Normal operation

Right channel overcurrent fault

Overtemperture fault status

Normal operation

0

1

R

0

1

OT

R

0

1

Overtemperature fault

FAULT_CTRL2 REGISTER

Table 64. Address: 0x10, Reset: 0x4C, Name: FAULT_CTRL2

Bits

Bit Name

Reserved

AR_TIME

Settings

Description

Reset

0x0

Access

RW

7

[6:5]

Auto recovery time

0x2

RW

00

01

10

11

10 ms auto fault recovery delay

20 ms auto fault recovery delay

40 ms auto fault recovery delay

80 ms auto fault recovery delay

Manual fault recovery

4

MRCV

0x0

0x3

RW

1

Writing of 1 causes a manual fault recovery attempt when ARCV = 11

Maximum fault recovery attempts

[3:2]

MAX_AR

00

01

10

11

1 auto recovery attempt

3 auto recovery attempts

7 auto recovery attempts

Unlimited auto recovery attempts

[1:0]

ARCV

Auto fault recovery control

0x0

RW

00

01

10

11

Auto fault recovery for overtemperature and overcurrent faults

Auto fault recovery for overtemperature fault only

Auto fault recovery for overcurrent fault only

No auto fault recovery

DEEMP_CTRL REGISTER

Table 65. Address: 0x14, Reset: 0x00, Name: DEEMP_CTRL

Bits

[7:3]

[2:1]

Bit Name

Reserved

DEEMP_FS

Settings

Description

Reset

0x00

0x0

Access

RW

De-emphasis sample rate selection

Set coefficients to all zero

48 kHz

44.1 kHz

32 kHz

RW

00

01

10

11

0

DEEMP_EN

De-emphasis enable

De-emphasis filter enable

De-emphasis filter disable

Rev. 0 | Page 34 of 52

0x0

RW

1

0

Data Sheet

SSM2529

HPF_CTRL REGISTER

Table 66. Address: 0x15, Reset: 0x00, Name: HPF_CTRL

Bits

[7:6]

[5:2]

Bit Name

Reserved

HPFCUT

Settings

Description

Reset

Access

RW

0x0

High-pass filter 3 dB cutoff frequency

0x00

RW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

3.7 Hz (default)

50 Hz

100 Hz

150 Hz

200 Hz

250 Hz

300 Hz

350 Hz

400 Hz

450 Hz

500 Hz

550 Hz

600 Hz

650 Hz

700 Hz

750 Hz

1

0

HPFOR

HPFEN

Store/clear high-pass filter dc value when HPF disabled

Clear dc value

Store dc value

0x0

RW

0

1

High-pass filter enabled

HPF disabled (default)

HPF enabled

0

1

EQ1_COEF0_HI REGISTER

Table 67. Address: 0x16, Reset: 0x00, Name: EQ1_COEF0_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF0_HI

EQ coefficient

0x00

RW

EQ1_COEF0_LO REGISTER

Table 68. Address: 0x17, Reset: 0x00, Name: EQ1_COEF0_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF0_LO

EQ coefficient

0x00

RW

EQ1_COEF1_HI REGISTER

Table 69. Address: 0x18, Reset: 0x00, Name: EQ1_COEF1_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF1_HI

EQ coefficient

0x00

RW

EQ1_COEF1_LO REGISTER

Table 70. Address: 0x19, Reset: 0x00, Name: EQ1_COEF1_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF1_LO

EQ coefficient

0x00

RW

Rev. 0 | Page 35 of 52

SSM2529

Data Sheet

EQ1_COEF2_HI REGISTER

Table 71. Address: 0x1A, Reset: 0x00, Name: EQ1_COEF2_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF2_HI

EQ coefficient

0x00

RW

EQ1_COEF2_LO REGISTER

Table 72. Address: 0x1B, Reset: 0x00, Name: EQ1_COEF2_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF2_LO

EQ coefficient

0x00

RW

EQ1_COEF3_HI REGISTER

Table 73. Address: 0x1C, Reset: 0x00, Name: EQ1_COEF3_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF3_HI

EQ coefficient

0x00

RW

EQ1_COEF3_LO REGISTER

Table 74. Address: 0x1D, Reset: 0x00, Name: EQ1_COEF3_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF3_LO

EQ coefficient

0x00

RW

EQ1_COEF4_HI REGISTER

Table 75. Address: 0x1E, Reset: 0x00, Name: EQ1_COEF4_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF4_HI

EQ coefficient

0x00

RW

EQ1_COEF4_LO REGISTER

Table 76. Address: 0x1F, Reset: 0x00, Name: EQ1_COEF4_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ1_COEF4_LO

EQ coefficient

0x00

RW

EQ2_COEF0_HI REGISTER

Table 77. Address: 0x20, Reset: 0x00, Name: EQ2_COEF0_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF0_HI

EQ coefficient

0x00

RW

EQ2_COEF0_LO REGISTER

Table 78. Address: 0x21, Reset: 0x00, Name: EQ2_COEF0_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF0_LO

EQ coefficient

0x00

RW

EQ2_COEF1_HI REGISTER

Table 79. Address: 0x22, Reset: 0x00, Name: EQ2_COEF1_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF1_HI

EQ coefficient

0x00

RW

EQ2_COEF1_LO REGISTER

Table 80. Address: 0x23, Reset: 0x00, Name: EQ2_COEF1_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF1_LO

EQ coefficient

0x00

RW

Rev. 0 | Page 36 of 52

Data Sheet

SSM2529

EQ2_COEF2_HI REGISTER

Table 81. Address: 0x24, Reset: 0x00, Name: EQ2_COEF2_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF2_HI

EQ coefficient

0x00

RW

EQ2_COEF2_LO REGISTER

Table 82. Address: 0x25, Reset: 0x00, Name: EQ2_COEF2_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF2_LO

EQ coefficient

0x00

RW

EQ2_COEF3_HI REGISTER

Table 83. Address: 0x26, Reset: 0x00, Name: EQ2_COEF3_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF3_HI

EQ coefficient

0x00

RW

EQ2_COEF3_LO REGISTER

Table 84. Address: 0x27, Reset: 0x00, Name: EQ2_COEF3_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF3_LO

EQ coefficient

0x00

RW

EQ2_COEF4_HI REGISTER

Table 85. Address: 0x28, Reset: 0x00, Name: EQ2_COEF4_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF4_HI

EQ coefficient

0x00

RW

EQ2_COEF4_LO REGISTER

Table 86. Address: 0x29, Reset: 0x00, Name: EQ2_COEF4_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ2_COEF4_LO

EQ coefficient

0x00

RW

EQ3_COEF0_HI REGISTER

Table 87. Address: 0x2A, Reset: 0x00, Name: EQ3_COEF0_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF0_HI

EQ coefficient

0x00

RW

EQ3_COEF0_LO REGISTER

Table 88. Address: 0x2B, Reset: 0x00, Name: EQ3_COEF0_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF0_LO

EQ coefficient

0x00

RW

EQ3_COEF1_HI REGISTER

Table 89. Address: 0x2C, Reset: 0x00, Name: EQ3_COEF1_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF1_HI

EQ coefficient

0x00

RW

EQ3_COEF1_LO REGISTER

Table 90. Address: 0x2D, Reset: 0x00, Name: EQ3_COEF1_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF1_LO

EQ coefficient

0x00

RW

Rev. 0 | Page 37 of 52

SSM2529

Data Sheet

EQ3_COEF2_HI REGISTER

Table 91. Address: 0x2E, Reset: 0x00, Name: EQ3_COEF2_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF2_HI

EQ coefficient

0x00

RW

EQ3_COEF2_LO REGISTER

Table 92. Address: 0x2F, Reset: 0x00, Name: EQ3_COEF2_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF2_LO

EQ coefficient

0x00

RW

EQ3_COEF3_HI REGISTER

Table 93. Address: 0x30, Reset: 0x00, Name: EQ3_COEF3_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF3_HI

EQ coefficient

0x00

RW

EQ3_COEF3_LO REGISTER

Table 94. Address: 0x31, Reset: 0x00, Name: EQ3_COEF3_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF3_LO

EQ coefficient

0x00

RW

EQ3_COEF4_HI REGISTER

Table 95. Address: 0x32, Reset: 0x00, Name: EQ3_COEF4_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF4_HI

EQ coefficient

0x00

RW

EQ3_COEF4_LO REGISTER

Table 96. Address: 0x33, Reset: 0x00, Name: EQ3_COEF4_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ3_COEF4_LO

EQ coefficient

0x00

RW

EQ4_COEF0_HI REGISTER

Table 97. Address: 0x34, Reset: 0x00, Name: EQ4_COEF0_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF0_HI

EQ coefficient

0x00

RW

EQ4_COEF0_LO REGISTER

Table 98. Address: 0x35, Reset: 0x00, Name: EQ4_COEF0_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF0_LO

EQ coefficient

0x00

RW

EQ4_COEF1_HI REGISTER

Table 99. Address: 0x36, Reset: 0x00, Name: EQ4_COEF1_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF1_HI

EQ coefficient

0x00

RW

EQ4_COEF1_LO REGISTER

Table 100. Address: 0x37, Reset: 0x00, Name: EQ4_COEF1_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF1_LO

EQ coefficient

0x00

RW

Rev. 0 | Page 38 of 52

Data Sheet

SSM2529

EQ4_COEF2_HI REGISTER

Table 101. Address: 0x38, Reset: 0x00, Name: EQ4_COEF2_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF2_HI

EQ coefficient

0x00

RW

EQ4_COEF2_LO REGISTER

Table 102. Address: 0x39, Reset: 0x00, Name: EQ4_COEF2_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF2_LO

EQ coefficient

0x00

RW

EQ4_COEF3_HI REGISTER

Table 103. Address: 0x3A, Reset: 0x00, Name: EQ4_COEF3_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF3_HI

EQ coefficient

0x00

RW

EQ4_COEF3_LO REGISTER

Table 104. Address: 0x3B, Reset: 0x00, Name: EQ4_COEF3_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF3_LO

EQ coefficient

0x00

RW

EQ4_COEF4_HI REGISTER

Table 105. Address: 0x3C, Reset: 0x00, Name: EQ4_COEF4_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF4_HI

EQ coefficient

0x00

RW

EQ4_COEF4_LO REGISTER

Table 106. Address: 0x3D, Reset: 0x00, Name: EQ4_COEF4_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ4_COEF4_LO

EQ coefficient

0x00

RW

EQ5_COEF0_HI REGISTER

Table 107. Address: 0x3E, Reset: 0x00, Name: EQ5_COEF0_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF0_HI

EQ coefficient

0x00

RW

EQ5_COEF0_LO REGISTER

Table 108. Address: 0x3F, Reset: 0x00, Name: EQ5_COEF0_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF0_LO

EQ coefficient

0x00

RW

EQ5_COEF1_HI REGISTER

Table 109. Address: 0x40, Reset: 0x00, Name: EQ5_COEF1_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF1_HI

EQ coefficient

0x00

RW

EQ5_COEF1_LO REGISTER

Table 110. Address: 0x41, Reset: 0x00, Name: EQ5_COEF1_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF1_LO

EQ coefficient

0x00

RW

Rev. 0 | Page 39 of 52

SSM2529

Data Sheet

EQ5_COEF2_HI REGISTER

Table 111. Address: 0x42, Reset: 0x00, Name: EQ5_COEF2_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF2_HI

EQ coefficient

0x00

RW

EQ5_COEF2_LO REGISTER

Table 112. Address: 0x43, Reset: 0x00, Name: EQ5_COEF2_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF2_LO

EQ coefficient

0x00

RW

EQ5_COEF3_HI REGISTER

Table 113. Address: 0x44, Reset: 0x00, Name: EQ5_COEF3_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF3_HI

EQ coefficient

0x00

RW

EQ5_COEF3_LO REGISTER

Table 114. Address: 0x45, Reset: 0x00, Name: EQ5_COEF3_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF3_LO

EQ coefficient

0x00

RW

EQ5_COEF4_HI REGISTER

Table 115. Address: 0x46, Reset: 0x00, Name: EQ5_COEF4_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF4_HI

EQ coefficient

0x00

RW

EQ5_COEF4_LO REGISTER

Table 116. Address: 0x47, Reset: 0x00, Name: EQ5_COEF4_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ5_COEF4_LO

EQ coefficient

0x00

RW

EQ6_COEF0_HI REGISTER

Table 117. Address: 0x48, Reset: 0x00, Name: EQ6_COEF0_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ6_COEF0_HI

EQ coefficient

0x00

RW

EQ6_COEF0_LO REGISTER

Table 118. Address: 0x49, Reset: 0x00, Name: EQ6_COEF0_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ6_COEF0_LO

EQ coefficient

0x00

RW

EQ6_COEF1_HI REGISTER

Table 119. Address: 0x4A, Reset: 0x00, Name: EQ6_COEF1_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ6_COEF1_HI

EQ coefficient

0x00

RW

EQ6_COEF1_LO REGISTER

Table 120. Address: 0x4B, Reset: 0x00, Name: EQ6_COEF1_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ6_COEF1_LO

EQ coefficient

0x00

RW

Rev. 0 | Page 40 of 52

Data Sheet

SSM2529

EQ6_COEF2_HI REGISTER

Table 121. Address: 0x4C, Reset: 0x00, Name: EQ6_COEF2_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ6_COEF2_HI

EQ coefficient

0x00

RW

EQ6_COEF2_LO REGISTER

Table 122. Address: 0x4D, Reset: 0x00, Name: EQ6_COEF2_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ6_COEF2_LO

EQ coefficient

0x00

RW

EQ7_COEF0_HI REGISTER

Table 123. Address: 0x4E, Reset: 0x00, Name: EQ7_COEF0_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ7_COEF0_HI

EQ coefficient

0x00

RW

EQ7_COEF0_LO REGISTER

Table 124. Address: 0x4F, Reset: 0x00, Name: EQ7_COEF0_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ7_COEF0_LO

EQ coefficient

0x00

RW

EQ7_COEF1_HI REGISTER

Table 125. Address: 0x50, Reset: 0x00, Name: EQ7_COEF1_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ7_COEF1_HI

EQ coefficient

0x00

RW

EQ7_COEF1_LO REGISTER

Table 126. Address: 0x51, Reset: 0x00, Name: EQ7_COEF1_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ7_COEF1_LO

EQ coefficient

0x00

RW

EQ7_COEF2_HI REGISTER

Table 127. Address: 0x52, Reset: 0x00, Name: EQ7_COEF2_HI

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ7_COEF2_HI

EQ coefficient

0x00

RW

EQ7_COEF2_LO REGISTER

Table 128. Address: 0x53, Reset: 0x00, Name: EQ7_COEF2_LO

Bits

Bit Name

Description

Reset

Access

[7:0]

EQ7_COEF2_LO

EQ coefficient

0x00

RW

Rev. 0 | Page 41 of 52

SSM2529

Data Sheet

EQ_CTRL1 REGISTER

Table 129. Address: 0x54, Reset: 0x00, Name: EQ_CTRL1

Bits

[7:4]

3

Bit Name

Settings

Description

Reset

0x0

Access

RW

EQ_RESERVED

EQ_UPDING

Reserved

EQ coefficient updating flag

None

0x0

R

0

1

EQ coefficients updating

EQ coefficient update clear

Normal operation

Interrupt coefficient update

EQ coefficient format selection

Normal

2

1

0

EQ_UPD_CLR

EQ_FORMAT

EQ_UPD

0x0

W

RW

R

0

1

0

1

Large gain

EQ coefficient registers update flag

Update

None

1

0

EQ_CTRL2 REGISTER

Table 130. Address: 0x55, Reset: 0x00, Name: EQ_CTRL2

Bits

Bit Name

Settings

Description

EQ enable

EQ disable

EQ enable

Reset

Access

7

EQEN

0x0

RW

0

1

6

5

4

3

2

1

0

EQBP7

EQBP6

EQBP5

EQBP4

EQBP3

EQBP2

EQBP1

EQ Band 7 bypass when EQ enabled

No bypass

Bypass EQ Band 7

0x0

RW

0

1

EQ Band 6 bypass when EQ enabled

No bypass

Bypass EQ Band 6

0

1

EQ Band 5 bypass when EQ enabled

No bypass

Bypass EQ Band 5

0

1

EQ Band 4 bypass when EQ enabled

No bypass

Bypass EQ Band 4

0

1

EQ Band 3 bypass when EQ enabled

No bypass

Bypass EQ Band 3

0

1

EQ Band 2 bypass when EQ enabled

No bypass

Bypass EQ Band 2

0

1

EQ Band 1 bypass when EQ enabled

No bypass

Bypass EQ Band 1

0

1

Rev. 0 | Page 42 of 52

Data Sheet

SSM2529

DRC_CTRL1 REGISTER

Table 131. Address: 0x56, Reset: 0x00, Name: DRC_CTRL1

Bits

[7:4]

[3:0]

Bit Name

Reserved

DRCLELTAV

Settings

Description

Reset

0x0

Access

RW

DRC rms detector average time

0 ms(default)

0.075 ms

0.30 ms

24.576 sec

0x0

RW

0000

0001

0011

1111

DRC_CTRL2 REGISTER

Table 132. Address: 0x57, Reset: 0x00, Name: DRC_CTRL2

Bits

Bit Name

Settings

Description

Reset

0x0

Access

[7:4]

PEAK_ATT

DRC peak detector attack time setting; 16 possible values

RW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0 ms

0.09 ms

0.19 ms

0.37 ms

0.75 ms

1.5 ms

3 ms

6 ms

12 ms

24 ms

48 ms

96 ms

192 ms

384 ms

768 ms

1.536 sec

[3:0]

PEAK_REL

DRC peak detector decay time setting; 16 possible values

0x0

RW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0 ms

1.5 ms

3 ms

6 ms

12 ms

24 ms

48 ms

96 ms

192 ms

384 ms

768 ms

1.536 sec

3.072 sec

6.144 sec

12.288 sec

24.576 sec

Rev. 0 | Page 43 of 52

SSM2529

Data Sheet

DRC_CTRL3 REGISTER

Table 133. Address: 0x58, Reset: 0x00, Name: DRC_CTRL3

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

DRC_ATT

DRC attack time setting; 16 possible settings

0x0

RW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0 ms

0.1 ms

0.19 ms

0.37 ms

0.75 ms

1.5 ms

3 ms

6 ms

12 ms

24 ms

48 ms

96 ms

192 ms

384 ms

768 ms

1.536 sec

[3:0]

DRC_DEC

DRC decay time setting; 16 possible settings

0x0

RW

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0 ms

1.5 ms

3 ms

6 ms

12 ms

24 ms

48 ms

96 ms

192 ms

384 ms

768 ms

1.536 sec

3.072 sec

6.144 sec

12.288 sec

24.576 sec

DRC_CURVE1 REGISTER

Table 134. Address: 0x59, Reset: 0x00, Name: DRC_CURVE1

Bits

Bit Name

Reserved

DRC_LT

Settings

Description

Reset

0x0

Access

RW

7

[6:0]

DRC limiter threshold setting, relative to input, in 0.5 dB steps

0x00

RW

0000000

0000001

xxxxxxx

1010000

+6 dB

+5.5 dB

−0.5 dB step

−35 dB

Rev. 0 | Page 44 of 52

Data Sheet

SSM2529

DRC_CURVE2 REGISTER

Table 135. Address: 0x5A, Reset: 0x00, Name: DRC_CURVE2

Bits

Bit Name

Reserved

DRC_CT

Settings

Description

Reset

Access

RW

7

0x0

[6:0]

DRC compressor threshold setting, relative to input in 0.5 dB steps

0x00

RW

0000000

0000001

xxxxxxx

1010000

+6 dB

+5.5 dB

−0.5 dB step

−35 dB

DRC_CURVE3 REGISTER

Table 136. Address: 0x5B, Reset: 0x00, Name: DRC_CURVE3

Bits Bit Name Settings Description

Reserved

[6:0] DRC_SMAX

Reset Access

7

0x0

RW

This is the DRC maximum output signal amplitude setting. This is the maximum output

0x00

level produced by the DRC and is used to indicate the upper compressor threshold. The

possible settings are in 0.5 dB steps.

0000000 +6 dB

0000001 +5.5 dB

xxxxxxx

−0.5 dB step

1010000 −35 dB

DRC_CURVE4 REGISTER

Table 137. Address: 0x5C, Reset: 0x88, Name: DRC_CURVE4

Bits Bit Name Settings Description

Reset Access

[7:4] DRC_NT

DRC noise gating threshold setting, relative to input; 16 possible values in 3 dB steps

0x8

RW

0000

0001

xxxx

1111

−51 dB

−54 dB

−3 dB step

−96 dB

[3:0] DRC_ET

DRC expander threshold setting, relative to input; 16 possible values in 3 dB steps

0x8

RW

0000

0001

xxxx

1111

−36 dB

−39 dB

−3 dB step

−81 dB

DRC_CURVE5 REGISTER

Table 138. Address: 0x5D, Reset: 0x00, Name: DRC_CURVE5

Bits

[7:4]

[3:0]

Bit Name

Reserved

DRC_SMIN

Settings

Description

Reset

0x0

Access

RW

DRC minimum output signal level

0x0

0000

0001

xxxx

1011

1111

−51 dB(default)

−54 dB

−3 dB step

−84 dB

−96 dB

Rev. 0 | Page 45 of 52

SSM2529

Data Sheet

DRC_HOLD_TIME REGISTER

Table 139. Address: 0x5E, Reset: 0x00, Name: DRC_HOLD_TIME

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

DRCHTNG

DRC hold time for noise gating

0 ms(default)

0.67 ms

Double time

42.67 ms

0x0

RW

0000

0001

xxxx

0111

1111

43.7 sec

[3:0]

DRCHTNOR

DRC hold time for normal operation

0 ms(default)

0.67 ms

Double time

42.67 ms

0x0

RW

0000

0001

xxxx

0111

1111

43.7 sec

DRC_RIPPLE_CTRL REGISTER

Table 140. Address: 0x5F, Reset: 0x00, Name: DRC_RIPPLE_CTRL

Bits

[7:2]

[1:0]

Bit Name

Reserved

DRCRRH

Settings

Description

Reset

0x0

Access

RW

DRC ripple remove threshold

0x0

RW

00

01

10

11

0 dB (default)

0.28 dB

0.47 dB

0.75 dB

DRC MODE CONTROL REGISTER

Table 141. Address: 0x60, Reset: 0x3C, Name: DRC Mode Control

Bits

Bit Name

Settings

Description

Reset

Access

7

VBAT_EN

VBAT tracking enable

VBAT tracking disable

VBAT tracking enable

Limiter source selection

RMS

0x0

RW

0

1

6

LIM_SRC

LIM_EN

COMP_EN

EXP_EN

NG_EN

0x0

0x1

0x0

RW

0

1

Peak

5

Limiter enable

0

1

Limiter function disabled

Limiter function enabled

Compressor enable

Compressor function disabled

Compressor function enabled

Expander enable

Expander function disabled

Expander function enabled

Noise gate enable

4

0

1

3

0

1

2

0

1

Noise gate function disabled

Noise gate function enabled

DRC enable

[1:0]

DRC_EN

0

1

DRC disabled

DRC enabled

Rev. 0 | Page 46 of 52

Data Sheet

SSM2529

FDSP_EN REGISTER

Table 142. Address: 0x61, Reset: 0x00, Name: FDSP_EN

Bits

[7:1]

0

Bit Name

Reserved

FDSP_EN

Settings

Description

Reset

Access

RW

0x00

0x0

FDSP enable

Disable FDSP

Enable FDSP

RW

0

1

SPK_PROT_EN REGISTER

Table 143. Address: 0x80, Reset: 0x00, Name: SPK_PROT_EN

Bits

[7:1]

0

Bit Name

Reserved

SP_EN

Settings

Description

Reset

0x00

0x0

Access

RW

Speaker protection enable

RW

0

1

Speaker protection disabled (default)

Speaker protection enabled

TEMP_AMBIENT REGISTER

Table 144. Address: 0x81, Reset: 0x19, Name: TEMP_AMBIENT

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

TEMP_AMBIENT

Ambient temperature in degrees Celsius (8.0 integer format)

0x19

RW

0x19

0x20

25°C (default)

32°C

SPKR_DCR REGISTER

Table 145. Address: 0x82, Reset: 0x40, Name: SPKR_DCR

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SPKR_DCR

Nominal speaker dc resistance in ohms (5.3 unsigned format)

0x40

RW

0x34

0x40

6.5 Ω

8 Ω (default)

SPKR_TC REGISTER

Table 146. Address: 0x83, Reset: 0x08, Name: SPKR_TC

Bits Bit Name Settings Description

Reset Access

[7:0] SPKR_TC

Nominal speaker temperature coefficient, rise in ohms per degrees Celsius (0.8 fractional 0x08

RW

format).

0x08

0x0A

0.033 Ω/°C (default)

0.04 Ω/°C

SP_CF1_H REGISTER

Table 147. Address: 0x84, Reset: 0x3F, Name: SP_CF1_H

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SP_CF1_H

Default

Speaker Temperature Model Coefficient 1, Bits[15:8] in 0.8 fractional format

0x3F

RW

SP_CF1_L REGISTER

Table 148. Address: 0x85, Reset: 0x81, Name: SP_CF1_L

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SP_CF1_L

Default

Speaker Temperature Model Coefficient 1, Bits[7:0] in 0.8 fractional format

0x81

RW

SP_CF2_H REGISTER

Table 149. Address: 0x86, Reset: 0x00, Name: SP_CF2_H

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SP_CF2_H

Default

Speaker Temperature Model Coefficient 2, Bits[15:8] in 0.8 fractional format

Rev. 0 | Page 47 of 52

0x00

RW

SSM2529

Data Sheet

SP_CF2_L REGISTER

Table 150. Address: 0x87, Reset: 0x55, Name: SP_CF2_L

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SP_CF2_L

Default

Speaker Temperature Model Coefficient 2, Bits[7:0] in 0.8 fractional format

0x55

RW

SP_CF3_H REGISTER

Table 151. Address: 0x88, Reset: 0x01, Name: SP_CF3_H

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SP_CF3_H

Default

Speaker Temperature Model Coefficient 3, Bits[15:8] in 0.8 fractional format

0x01

RW

SP_CF3_L REGISTER

Table 152. Address: 0x89, Reset: 0x22, Name: SP_CF3_L

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SP_CF3_L

Default

Speaker Temperature Model Coefficient 3, Bits[7:0] in 0.8 fractional format 0x22

RW

SP_CF4_H REGISTER

Table 153. Address: 0x8A, Reset: 0x02, Name: SP_CF4_H

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SP_CF4_H

Default

Speaker Temperature Model Coefficient 4, Bits[15:8] in 0.8 fractional format

0x02

RW

SP_CF4_L REGISTER

Table 154. Address: 0x8B, Reset: 0x09, Name: SP_CF4_L

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SP_CF4_L

Default

Speaker Temperature Model Coefficient 4, Bits[7:0] in 0.8 fractional format

0x09

RW

SPKR_TEMP REGISTER

Table 155. Address: 0x8C, Reset: 0x00, Name: SPKR_TEMP

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SPKR_TEMP

Speaker voice coil temperature status (8.0 integer format)

32°C

0x00

R

0x20

SPKR_TEMP_MAG REGISTER

Table 156. Address: 0x8D, Reset: 0x00, Name: SPKR_TEMP_MAG

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SPKR_TEMP_MAG

Speaker magnet temperature status (8.0 integer format)

32°C

0x00

R

0x20

MAX_SPKR_TEMP REGISTER

Table 157. Address: 0x8E, Reset: 0x64, Name: MAX_SPKR_TEMP

Bits

Bit Name

Settings Description

Reset

Access

[7:0]

MAX_SPKR_TEMP

Maximum speaker voice coil temperature before gain reduction occurs,

0x64

RW

8.0 integer format

100°C

0x64

Rev. 0 | Page 48 of 52

Data Sheet

SSM2529

SPK_GAIN REGISTER

Table 158. Address: 0x8F, Reset: 0x44, Name: SPK_GAIN

Bits

Bit Name

Settings

Description

Reset

0x4

Access

[7:4]

SP_RR

Speaker protection gain reduction release rate

RW

0000

0001

0010

0011

0100

0101

0110

0111

0.549 dB/s

0.275 dB/s

0.137 dB/s

0.092 dB/s

0.069 dB/s (default)

0.034 dB/s

0.017 dB/s

0.008 dB/s

[3:0]

SP_AR

Speaker protection gain reduction attack rate

0.070 dB/ms

0.035 dB/ms

0.017 dB/ms

0.012 dB/ms

0.009 dB/ms (default)

0.006 dB/ms

0.004 dB/ms

0x4

RW

0000

0001

0010

0011

0100

0101

0110

0111

0.003 dB/ms

SOFT_RST REGISTER

Table 159. Address: 0xFF, Reset: 0x00, Name: SOFT_RST

Bits

Bit Name

Description

Reset

Access

[7:0]

SOFT_RST

Write 0x00 to reset all registers

0x00

W

Rev. 0 | Page 49 of 52

SSM2529

Data Sheet

APPLICATIONS INFORMATION

LDO_OUT

(1.8V)

DVDD

SPKVDD

(1.08V TO 1.98V) (2.5V TO 5.5V)

1µF

100nF

10µF

100nF

BCLK

LRCLK

SDATA

MCLK

AUDIO

PROCESSOR

OUTP

OUTN

IOVDD

(1.8V TO 3.6V)

SSM2529

2.2kΩ 2.2kΩ

SCL

SYSTEM

CONTROLLER

SDA

STDBN

ADDR

SA_MODE

GND

SPKGND

Figure 42. Software Mode (with I²C Interface)

LDO_OUT

(1.8V)

DVDD

SPKVDD

(1.08V TO 1.98V) (2.5V TO 5.5V)

1µF

100nF

10µF

100nF

BCLK

LRCLK

SDATA

MCLK

OUTP

SSM2529

OUTN

SCL

SDA

STDBN

ADDR

SA_MODE

GND

SPKGND

SPKVDD

Figure 43. Hardware Standalone Mode

Rev. 0 | Page 50 of 52

Data Sheet

SSM2529

OUTLINE DIMENSIONS

1.960

1.920

1.880

4

3

2

1

A

B

C

D

BALL A1

IDENTIFIER

1.980

1.940

1.900

1.20

REF

0.40

REF

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

0.560

0.500

0.440

SIDE VIEW

COPLANARITY

0.05

0.300

0.260

0.220

SEATING

PLANE

0.230

0.200

0.170

Figure 44. 16-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-16-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range Package Description

Package Option Branding

SSM2529ACBZ-RL

SSM2529ACBZ-R7

EVAL-SSM2529Z

−40°C to +85°C

16-Ball Wafer Level Chip Scale Package [WLCSP]

Evaluation Board

CB-16-12

Y4D

¹Z = RoHS Compliant Part.

Rev. 0 | Page 51 of 52

SSM2529

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D10749-0-7/12(0)

Rev. 0 | Page 52 of 52


型号：	SSM2529
厂家：	ADI
描述：	Digital Input, Mono 2 W, Class-D Audio Power Amplifier
文件：	总52页 (文件大小：811K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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