SSM3525 [ADI]
30 W, Filterless, Class D, Output Sensing Audio Amplifier;
| 型号： | SSM3525 |
| 厂家： | 
ADI |
| 描述： | 30 W, Filterless, Class D, Output Sensing Audio Amplifier |
| 文件： | 总60页 (文件大小：934K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
30 W, Filterless, Class D, Output Sensing
Audio Amplifier
Data Sheet
SSM3525
FEATURES
GENERAL DESCRIPTION
Filterless digital input, mono Class D amplifier with Σ-Δ
modulation
Digitized output of output voltage, output current, and PVDD
supply voltage
Operates from 4.5 V to 17 V supply, such as a 2-cell or 3-cell
battery
Input/output supply operation from 1.1 V to 1.98 V
30.2 W output power, 17 V supply and 4 Ω load at 1% THD + N
37.5 μV rms noise, 107 dB A weighted signal-to-noise ratio
I2C control with up to 4 pin-selectable addresses
Multiple serial data formats
TDM, I2S, or left justified slave
PDM input/output operating from 2.048 MHz to
6.144 MHz
Support sample rates from 8 kHz to 192 kHz
Flexible digital and analog gain adjustment
AGC with battery voltage-based limiter
74 dB SNR on output current sensing and 85 dB SNR on
voltage sensing
6.62 mA quiescent current at 12 V PVDD supply
Temperature sensor with 1°C readout
Short-circuit, thermal protection, and thermal warning
23-ball, 2.26 mm × 2.38 mm, 0.4 mm pitch WLCSP
Pop and click suppression
The SSM3525 is a fully integrated, high efficiency, mono Class D
audio amplifier with digital input and digitized output of output
voltage, output current, and PVDD supply. The application
circuit requires few external components and can operate from
4.5 V to 17 V (PVDD) and 1.8 V (IOVDD) supplies. It is capable of
delivering 8.3 W of continuous output power into an 8 Ω load (or
15.3 W into 4 Ω) with <1% total harmonic distortion + noise (THD
+ N) from a 12 V supply, or 30.2 W into an 4 Ω load from a 17 V
power supply, all with <1% THD + N.
The SSM3525 features a high efficiency, low noise modulation
scheme that requires no external inductor/capacitor (LC) output
filters. This scheme continues to provide high efficiency even at
low output power. It operates with 92% efficiency at 9 W into an
8 Ω load, 12V or 89% efficiency at 20 W into 4 Ω from a 17 V
supply, and it has an signal-to-noise ratio (SNR) of 107 dB,
A weighted.
Spread spectrum pulse density modulation provides lower
electromagnetic interference (EMI) radiated emissions compared
with other Class D architectures, particularly above 100 MHz.
The digital input eliminates the need of an external digital-to-
analog converter (DAC). The SSM3525 has a micropower
shutdown mode with a typical shutdown current of 90 nA at
12 V PVDD supply. Individual sense blocks can be powered
down to save power when sense is not needed.
User-selectable ultralow EMI emissions mode
Power-on reset
The device also includes pop and click suppression circuitry
that minimizes voltage glitches at the output during turn on and
turn off.
APPLICATIONS
Mobile computing
Portable electronics
Current sensing is accomplished using an integrated analog-to-
digital converter (ADC) and internal sense resistor. The
digitized voltage and current information can be returned in
various serial audio formats, including I2S, time division
multiplexing (TDM) and pulse density modulation (PDM).
The SSM3525 includes an integrated regulator to generate the
required 5 V analog supply. Alternatively, if an external 5 V rail
from a dc-to-dc converter is available, it can improve system
efficiency.
The SSM3525 is designed to operate with an I2C control interface
and specified over the temperature range of −40°C to +85°C. It has
built-in thermal shutdown and output short-circuit protection. It is
available in a halide free, 23-ball, 2.26 mm × 2.38 mm wafer-level
chip scale package (WLCSP).
Rev. A
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SSM3525
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SSM3525 I2C Mode Register Map (SSM3525_I2C_Regmap)
Register Summary .......................................................................... 36
SSM3525 I2C Mode Register Map (SSM3525_I2C_REGMAP)
Register Details ............................................................................... 37
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
Timing Specifications .................................................................. 7
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Theory of Operation ...................................................................... 23
Overview...................................................................................... 23
Power Supplies ............................................................................ 23
Pin Setup and Control ............................................................... 23
Power-Down Modes .................................................................. 24
Output Current Sensing ............................................................ 24
Output Voltage Sensing ............................................................. 24
Temperature Sensor ................................................................... 24
PCM Digital Audio Serial Interface......................................... 24
Stereo (I2S/Left Justified) Operating Mode............................. 24
TDM Operating Mode............................................................... 25
Serial Data Placement................................................................ 25
PDM Operating Mode............................................................... 26
Analog and Digital Gain............................................................ 27
PVDD (VBAT) Sensing............................................................. 27
Faults and Limiter Status Reporting ........................................ 27
Limiter and Battery Tracking Threshold Control.................. 27
Pop and Click Suppression........................................................ 30
High Frequency Clipper ............................................................ 30
EMI Noise.................................................................................... 30
Output Modulation Description .............................................. 30
Bootstrap Capacitors.................................................................. 32
Power Supply Decoupling ......................................................... 32
Output EMI Filtering................................................................. 32
PCB Component Placement ..................................................... 32
Layout........................................................................................... 33
I2C Control .................................................................................. 33
Applications Information .............................................................. 35
ADI Vendor ID Register............................................................ 37
Device ID 1 Register .................................................................. 37
Device ID 1 Register .................................................................. 37
Revision ID Register .................................................................. 37
Regulator Enable and IOVDD Selection Register ................. 38
Amplifier Gain, Edge Control, and Sense Sample Rate
Register ........................................................................................ 38
DAC Control Register................................................................ 39
DAC Volume Control Register................................................. 40
Audio Limiter Control 1 Register ............................................ 41
Audio Limiter Control 2 Register ............................................ 42
Audio Limiter Control 3 Register ............................................ 43
VBAT Limiter Control 1 Register ............................................ 43
VBAT Limiter Control 2 Register ............................................ 44
VBAT Limiter Control 3 Register ............................................ 44
Limiter Link Control Register .................................................. 45
DAC Clip Point Control Register............................................. 45
Fault Control Register................................................................ 46
Chip Status Register ................................................................... 47
Temperature Sensor Value Register ......................................... 47
VBAT/PVDD ADC Value Register.......................................... 48
Master and Block Power Control Register.............................. 48
PDM Control Register............................................................... 49
Serial Interface Control 1 Register........................................... 49
Serial Interface Control 2 Register........................................... 50
Serial Interface Placement Control 1 Register........................ 51
Serial Interface Placement Control 2 Register........................ 52
Serial Interface Placement Control 3 Register........................ 52
Serial Interface Placement Control 4 Register........................ 53
Serial Interface Placement Control 5 Register........................ 54
Serial Interface Placement Control 6 Register........................ 54
AGC_GAIN1 Input Data Placement Register........................ 55
AGC_GAIN2 Input Data Placement Register........................ 56
AGC_GAIN3 Input Data Placement Register........................ 57
AGC_GAIN4 Input Data Placement Register........................ 58
Software Reset Register ............................................................. 59
Ordering Guide .......................................................................... 60
Rev. A | Page 2 of 60
Data Sheet
SSM3525
REVISION HISTORY
5/2018—Rev. 0 to Rev. A
Changes to Figure 1...........................................................................4
Changes to Figure 20 to Figure 23 ...............................................14
Changes to Figure 24 to Figure 27 ................................................15
Changes to Figure 62 and Figure 63 Caption ..............................21
Changes to SNS_HPF_BP Description, Table 27........................38
1/2018—Revision 0: Initial Version
Rev. A |Page 3 of 60
SSM3525
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
5V
1.8V
4.5V TO 17V
VREG/AVDD
IOVDD
PVDD/VBAT
ADDR
PVDD (VBAT)
ADC
TEMPERATURE
SENSOR
SCL
2
PVDD
I C
SDA
OUTPUT
VOLTAGE
SENSE
Σ-Δ
ADC
DIGITAL
DECIMATION
FILTERING
OUTPUT
CURRENT
SENSE
Σ-Δ
ADC
BST+
DIGITAL
SDATAO
BCLK
OUT+
TDM
Σ-Δ
FILTERING
FULL BRIDGE
POWER
STAGE
2
I S
DAC
CLASS D
PDM
I/O
FSYNC
SDATAI
MODULATOR
VOLUME/
GAIN
OUT–
BST–
AGND
PGND
Figure 1. SSM3525 Block Diagram
Rev. A | Page 4 of 60
Data Sheet
SSM3525
SPECIFICATIONS
PVDD = 12 V, AVDD = 5 V (internal), IOVDD = 1.8 V (external), RL = 8 Ω + 33 μH, BCLK = 3.072 MHz, FSYNC = 48 kHz, −40°C to +85°C,
unless otherwise noted. The measurements are taken with a 20 kHz AES17 low-pass filter. The other load impedances used are 4 Ω + 15 μH
and 3 Ω +10 μH. The sine wave output powers above 20 W in 4 Ω cannot be continuous and might invoke the thermal limit indicator
based on the power dissipation capability of the printed circuit board (PCB).
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
DEVICE CHARACTERISTICS
Output Power/Channel
RL = 8 Ω
POUT
Frequency (f) = 1 kHz
THD + N = 1%, PVDD = 17 V
THD + N = 1%, PVDD = 12 V
THD + N = 1%, PVDD = 7 V
15.2
8.3
2.8
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
%
%
%
%
%
THD + N = 1%, PVDD = 5 V
1.4
THD + N = 10%, PVDD = 17 V
THD + N = 10%, PVDD = 12 V
THD + N = 10%, PVDD = 7 V
THD + N = 10%, PVDD = 5 V
THD + N = 1%, PVDD = 17 V
THD + N = 1%, PVDD = 12 V
THD + N = 1%, PVDD = 7 V
18.7
10.4
3.5
1.8
RL = 4 Ω
30.2
15.3
5.2
THD + N = 1%, PVDD = 5 V
2.7
THD + N = 10%, PVDD = 17 V
THD + N = 10%, PVDD = 12 V
THD + N = 10%, PVDD = 7 V
THD + N = 10%, PVDD = 5 V
POUT = 9 W, RL = 8 Ω, PVDD = 12 V
POUT = 9 W, RL = 8 Ω, PVDD = 12 V (low EMI mode)
POUT = 20 W, RL = 4 Ω, PVDD = 17 V
POUT = 20 W, RL = 4 Ω, PVDD = 17 V (low EMI mode)
37.2
19.1
6.6
3.3
92.1
92
89
88.8
0.004
Efficiency
η
Total Harmonic
THD + N
POUT = 5 W, RL = 8 Ω, f = 1 kHz, PVDD = 16 V
0.01
Distortion + Noise
Load Inductance
Output FET On Resistance RON
OverCurrent Protection
Trip Point
Average Switching
Frequency
5
6
μH
mΩ
APEAK
110
300
IOC
fSW
kHz
mV
Differential Output Offset
Voltage
VOOS
Gain = 8.9V/V
5.0
POWER SUPPLIES
Supply Voltage Range
PVDD
AVDD
IOVDD
PSRRAC
Guaranteed from PSRR test
4.5
4.5
1.1
17
V
V
V
dB
5.0
1.80
87
5.5
1.98
73
I2S/TDM operation
VRIPPLE = 1 V rms at 1 kHz
Power Supply Rejection
Ratio (AC)
GAIN CONTROL
Output Voltage Peak
Measured with 0 dBFS input at 1 kHz, no load
Analog gain setting = 6.3 V/V with PVDD = 6.3 V
Analog gain setting = 8.9 V/V with PVDD = 8.9 V
Analog gain setting = 12.6 V/V with PVDD = 12.6 V
Analog gain setting = 16.0 V/V with PVDD = 16 V
PDM input density for full-scale output
6.3
8.9
12.6
16
VPEAK
VPEAK
VPEAK
VPEAK
FS
PDM Input Gain
0.5
Rev. A |Page 5 of 60
SSM3525
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
SHUTDOWN CONTROL
Turn-On Time
Turn-Off Time
tWU
tSD
I2S mode
10
500
ms
µs
Output Impedance
NOISE PERFORMANCE1
Output Voltage Noise
ZOUT
100
kΩ
en
f = 20 Hz to 20 kHz, A weighted, PVDD = 12 V
f = 20 Hz to 20 kHz, A weighted, PVDD = 17 V
POUT = 8.2 W, RL= 8 Ω, A weighted, PVDD = 12 V
POUT = 31 W, RL= 4 Ω, A weighted, PVDD = 17 V
37.5
48
107
107
µV rms
µV rms
dB
Signal-to-Noise Ratio
SNR
dB
OUTPUT SENSING
Output Sampling Rate
(TDM)
PDM Gain Mapping
fs
FSYNC pulse rate
8
192
KHz
FS
Voltage to current (V/I) sense PDM output with full-scale
input
0.71
85
Voltage Sense Signal-to-
Noise Ratio
Voltage Sense Full-Scale
Voltage Sense Absolute
Accuracy
SNRV
VFS
dB
Output voltage at 0 dBFS output from ADC
Temperature = 0°C to 70° C, output >−40 dBFS
18
1.5
VPEAK
%
Voltage Sense Gain Drift
Current Sense SNR
Current Sense Full-Scale
Current Sense Absolute
Accuracy
Temperature = 0°C to 70° C, output >−40 dBFS
0.5
74
6.96
2
%
SNRI
ISENSE,FS
dB
APEAK
%
Peak current with 0 dBFS output from ADC
Temperature = 0°C to 70° C, output >−40 dBFS
Current Sense Gain Drift
Voltage Sense over Current
Sense Ratio Drift
Temperature = 0°C to 70° C, output >−40 dBFS
Temperature = 0°C to 70° C, output >−40 dBFS
0.5
0.5
%
%
PVDD Sense Full-Scale
Range
PVDD Sense Absolute
Accuracy
Current and Voltage
Sense Linearity
PVFS
PVDD with full-scale ADC output
Temperature = 0°C to 70°C
From −40 dBr to 0 dBr
4
18
V
3
LSBs
dB
0.5
1 The noise performance minimum and maximum limits are based on the bench data for −40°C to +85°C.
Rev. A | Page 6 of 60
Data Sheet
SSM3525
Software master power-down indicates the clocks are turned off. Auto power-down indicates there is no dither or zero input signal with
clocks on; the device enters soft power-down after 2048 cycles of zero input values. Quiescent indicates triangular dither with zero input
signal. All specifications are typical, with a 48 kHz sample rate, unless otherwise noted.
Table 2. Power Supply Current Consumption1
No Load
IPVDD IIOVDD IAVDD
5 V 12 V 17 V 1.8 V 5 V 5 V 12 V 17 V 1.8 V 5 V 5 V 12 V 17 V 1.8 V 5 V
Software master power-down 0.09 0.09 0.09 8.01 3.24 0.09 0.09 0.09 8.01 3.24 0.09 0.09 0.09 8.01 3.24 μA
4 Ω + 15 μH
8 Ω +33 μH
Edge Rate
Control
Mode
IPVDD IIOVDD IAVDD
IPVDD IIOVDD AVDD
Register REG_EN Bit Test Conditions
Unit
Normal
0
1
0
1
Quiescent (all ADCs on)
Quiescent (all ADCs off)
1.73 3.43 4.49 0.992 5.14 1.96 3.55 4.61 0.994 5.26 1.67 3.29 4.49 0.995 5.14 mA
1.74 3.44 4.51 0.817 3.28 1.96 3.54 4.61 0.816 3.44 1.67 3.29 4.49 0.82 3.34 mA
Software master power-down 0.09 0.09 0.09 8.01 N/A 0.09 0.09 0.09 8.01 N/A 0.09 0.09 0.09 8.01 N/A μA
Quiescent (all ADCs on)
Quiescent (all ADCs off)
6.86 8.56 9.65 0.995 N/A 6.81 8.61 10.21 0.998 N/A 6.83 8.51 9.79 0.996 N/A mA
5.04 6.73 7.86 0.821 N/A 4.98 6.75 8.44 0.766 N/A 5.01 6.69 7.96 0.817 N/A mA
Low EMI
Software master power-down 0.09 0.09 0.09 8.01 3.24 0.09 0.09 0.09 8.01 3.24 0.09 0.09 0.09 8.01 3.24 μA
Quiescent (all ADCs on)
Quiescent (all ADCs off)
1.663 3.35 4.48 0.991 5.08 1.6 3.35 4.68 0.994 5.21 1.59 3.28 4.48 0.996 5.09 mA
1.663 3.35 4.58 0.823 3.28 1.6 3.37 4.71 0.819 3.41 1.59 3.25 4.48 0.819 3.27 mA
Software master power-down 0.09 0.09 0.09 8.01 N/A 0.09 0.09 0.09 8.01 N/A 0.09 0.09 0.09 8.01 N/A μA
Quiescent (all ADCs on)
Quiescent (all ADCs off)
6.73 8.46 9.8 0.998 N/A 6.71 8.56 10.02 0.995 N/A 6.72 8.45 9.61 0.992 N/A mA
4.91 6.62 7.97 0.823 N/A 4.89 6.74 8.19 0.816 N/A 4.89 6.58 7.81 0.821 N/A mA
1 N/A means not applicable.
Table 3. Digital Input/Output
Parameter
Min
Typ
Max
Unit
HIGH INPUT VOLTAGE (VIH)
BCLK, FSYNC, SDATAI, and SDATAO
SCL and SDA
0.7 × IOVDD
0.7 × IOVDD
1.98
5.5
V
V
LOW INPUT VOLTAGE (VIL)
BCLK, FSYNC, SDATAI, SDATAO, SDA, SCL
ADDR
−0.3
−0.3
0.3 × IOVDD
IOVDD + 0.3
V
V
INPUT LEAKAGE
HIGH (IIH)
LOW (IIL)
1
1
5
µA
µA
pF
INPUT CAPACITANCE
OUTPUT DRIVE STRENGTH (SDATAO)
3
mA
TIMING SPECIFICATIONS
Table 4. I2C Port Timing
Parameter
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tBFT
Min
Max
Unit
Description
1
MHz
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
SCL frequency
SCL high
SCL low
Setup time; relevant for repeated start condition
Hold time; after this period, the first clock is generated
Data setup time
SCL rise time
SCL fall time
SDA rise time
SDA fall time
0.26
0.5
0.26
0.26
50
120
120
120
120
0.5
Bus-free time (time between stop and start)
Rev. A |Page 7 of 60
SSM3525
Data Sheet
Table 5. Serial Port Digital Input Timing (I2S/TDM Operation Modes Only)
Parameter
Min
Max
Unit
Description
SERIAL PORT
tBIL
tBIH
tSIS
tSIH
tLIS
tLIH
tBP
8
8
4
4
5
5
20
ns
ns
ns
ns
ns
ns
ns
BCLK low pulse width
BCLK high pulse width
SDATAI setup time to BCLK rising edge
SDATA hold time from BCLK rising edge
FSYNC setup time to BCLK rising edge
FSYNC hold time to BCLK rising edge
Minimum BCLK period
Table 6. Serial Port Digital Output Timing (I2S/TDM Operation Modes Only)
Parameter
Min
Max
Unit
Description
SERIAL PORT
tBIL
tBIH
tSIS
tSIH
tLIS
tLIH
tBP
8
8
4
4
5
5
20
ns
ns
ns
ns
ns
ns
ns
BCLK low pulse width.
BCLK high pulse width.
SDATAO setup time to BCLK rising edge
SDATA hold time from BCLK rising edge
FSYNC setup time to BCLK rising edge
FSYNC hold time to BCLK rising edge
Minimum BCLK period
Table 7. PDM Timing Parameters
Limit
Max
Parameter
Min
Unit
Description
PDM Clock Frequency
tFALL
2.048
6.144
10
MHz
ns
Clock fall time
Clock rise time
Data setup time
Data hold time
tRISE
tSETUP
tHOLD
10
ns
ns
ns
10
7
Digital Timing Diagrams
t
SCH
t
t
SCH
DS
SDA
SCL
t
t
t
SCS
SCR
SCLH
t
BFT
t
t
SCF
SCLL
START
CONDITION
STOP
CONDITION
Figure 2. I2C Port Timing
Rev. A | Page 8 of 60
Data Sheet
SSM3525
t
t
BP
BIH
BCLK
t
BIL
t
t
LIH
LIS
LRCLK
t
SIS
SDATA
LEFT–JUSTIFIED
MODE
MSB
MSB–1
t
SIH
t
SIS
SDATA
MSB
2
I C–JUSTIFIED
MODE
t
SIH
t
t
SIS
SIS
SDATA
RIGHT–JUSTIFIED
MODE
MSB
LSB
t
t
SIH
SIH
Figure 3. Serial Port SDATAI and SDATAO Timing
BCLK
t
t
HOLD
SETUP
SDATAI
L DATA
L DATA
R DATA
L DATA
R DATA
R DATA
SDATAO
R DATA
L DATA
Figure 4. PDM Input/Output Format
Rev. A |Page 9 of 60
SSM3525
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required. θJA and θJB are determined according to
JESD51-9 on a 4-layer PCB with natural convection cooling.
Table 8.
Parameter
Rating
PVDD Supply Voltage
IOVDD Supply Voltage
AVDD Supply Voltage
PGND and AGND Differential
BCLK, FSYNC, ADDR, SDATAI Input
Voltage
−0.3 V to +18 V
−0.3 V to +1.98 V
−0.3 V to +5.5 V
0.3 V
Table 9. Thermal Resistance
Package Type
1
1
θJA
θJB
Unit
−0.3 V to +1.98 V
23-ball, 2.22 mm × 2.34 mm WLCSP
64.6 21.9
°C/W
1 Thermal impedance simulated values are based on JEDEC2S2P thermal
test board with two thermal vias. See JEDEC JESD51.
SCL and SDA Input Voltage
−0.3 V to +5.5 V
1.5 kV
Electrostatic Discharge (ESD)
Susceptibility, HBM 1.5 kΩ, 100 pF,
JEDEC JS-001-2014
ESD CAUTION
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature Range
(Soldering, 60 sec)
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 10 of 60
Data Sheet
SSM3525
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
1
2
3
4
5
A
B
BST–
OUT–
PVDD/VBAT
OUT+
BST+
PGND
PGND
OUT–
OUT+
PGND
PVDD/VBAT
PVDD/VBAT
ADDR
C
D
PGND
FSYNC
BCLK
VREG/
AVDD
AGND
SDA
IOVDD
E
SCL
SDATAI
SDATAO
Figure 5. Ball Configuration (Top Side View)
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Type1
AIN
Description
A1
BST−
Bootstrap Capacitor, Inverting Output.
Inverting Output.
Power Stage Supply/Battery Supply.
Noninverting Output.
Bootstrap Capacitor, Noninverting Output.
Power Stage Ground.
Inverting Output.
Noninverting Output.
Analog Input/Output. 5 V regulator output/AVDD input.
Analog Ground.
Address Selection.
Input/Output and Digital Supply.
A2
A3, B3, C3
A4
A5
OUT−
PVDD/VBAT
OUT+
BST+
PGND
AOUT
PWR
AOUT
AIN
PWR
AOUT
AOUT
AIO
PWR
DIN
PWR
DIN
DIN
DIO
DIN
DOUT
DIN
B1, B5, C1, C5
B2
B4
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
OUT−
OUT+
VREG/AVDD
AGND
ADDR
IOVDD
FSYNC
SCL
Frame Sync Input.
I2C Clock.
SDA
I2C Data.
SDATAI
SDATAO
BCLK
I2S/TDM Serial Data Input or PDM Data Input.
I2S/TDM Serial Data Output or PDM Data Output.
TDM/I2S Bit Clock Input, PDM Clock Input
1 AOUT is analog output, PWR is power supply or ground pin, AIN is analog input, DIN is digital input, DOUT is digital output, and DIO is digital input/output.
Rev. A |Page 11 of 60
SSM3525
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
20
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Fast Fourier Transform (FFT), −60 dBFS Input,
Analog Gain = 6.3, RL = 4 Ω
Figure 9. FFT, −60 dBFS Input, Analog Gain = 16, RL = 4 Ω
20
0
20
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. FFT, −60 dBFS Input, Analog Gain = 8.9, RL= 4 Ω
Figure 10. FFT, No Signal, Analog Gain = 6.3, RL = 4 Ω
20
20
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. FFT, −60 dBFS Input, Analog Gain = 12.6, RL = 4 Ω
Figure 11. FFT, No Signal, Analog Gain = 8.9, RL = 4 Ω
Rev. A | Page 12 of 60
Data Sheet
SSM3525
20
1.0
0.1
0
5W
1W
100mW
–20
–40
–60
–80
–100
–120
–140
–160
0.01
0.001
–180
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. FFT, No Signal, Analog Gain = 12.6, RL = 4 Ω
Figure 15. THD + N vs. Frequency into RL = 4 Ω, PVDD = 12 V
20
0
1.0
10W
–20
1W
100mW
–40
0.1
0.01
–60
–80
–100
–120
–140
–160
–180
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. FFT, No Signal, Analog Gain = 16, RL = 4 Ω
Figure 16. THD + N vs. Frequency into RL = 4 Ω, PVDD = 17 V
1.0
0.1
1.0
100mW
1W
100mW
500mW
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. THD + N vs. Frequency into RL = 4 Ω, PVDD = 4.5 V
Figure 17. THD + N vs. Frequency into RL = 8 Ω, PVDD = 4.5 V
Rev. A |Page 13 of 60
SSM3525
Data Sheet
1.0
10
1.0
PVDD = 17V
PVDD = 12V
PVDD = 4.5V
5W
1W
100mW
0.1
0.1
0.01
0.01
0.001
20
0.001
100
1k
10k 20k
10µ
100µ
1m
10m
100m
1
10
50
FREQUENCY (Hz)
POWER (W)
Figure 18. THD + N vs. Frequency into RL = 8 Ω, PVDD = 12 V
Figure 21. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 8.9
1.0
10
PVDD = 17V
PVDD = 12V
PVDD = 4.5V
10W
1W
100mW
1.0
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1k
10k 20k
10µ
100µ
1m
10m
100m
1
10
50
FREQUENCY (Hz)
POWER (W)
Figure 19. THD + N vs. Frequency into RL = 8 Ω, PVDD = 17 V
Figure 22. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 12.6
10
10
PVDD = 17V
PVDD = 7V
PVDD = 4.5V
PVDD = 17V
PVDD = 12V
PVDD = 4.5V
1.0
0.1
1.0
0.1
0.01
0.01
0.001
0.001
10µ
100µ
1m
10m
100m
1
10
50
10µ
100µ
1m
10m
100m
1
10
50
POWER (W)
POWER (W)
Figure 20. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 6.3
Figure 23. THD + N vs. Output Power, RL = 4 Ω, Analog Gain = 16
Rev. A | Page 14 of 60
Data Sheet
SSM3525
10
10
1.0
PVDD = 17V
PVDD = 17V
PVDD = 12V
PVDD = 4.5V
PVDD = 7V
PVDD = 4.5V
1.0
0.1
0.1
0.01
0.01
0.001
0.001
10µ
100µ
1m
10m
100m
1
10
50
10µ
100µ
1m
10m
100m
1
10
50
POWER (W)
POWER (W)
Figure 24. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 6.3
Figure 27. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 16
10
7
6
5
4
3
PVDD = 17V
PVDD = 12V
PVDD = 4.5V
1.0
0.1
1% THD + N
10% THD + N
2
0.01
1
0
0.001
10µ
100µ
1m
10m
100m
1
10
50
5
7
9
11
PV (V)
13
15
17
POWER (W)
DD
Figure 25. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 8.9
Figure 28. Output Power vs. PVDD, RL = 4 Ω, Analog Gain = 6.3
10
14
13
12
11
10
9
PVDD = 17V
PVDD = 12V
PVDD = 4.5V
1.0
0.1
8
7
6
5
1% THD + N
10% THD + N
4
0.01
3
2
1
0
0.001
10µ
100µ
1m
10m
100m
1
10
50
5
6
7
8
9
10 11 12 13 14 15 16 17
PV (V)
POWER (W)
DD
Figure 26. THD + N vs. Output Power, RL = 8 Ω, Analog Gain = 12.6
Figure 29. Output Power vs. PVDD Supply Voltage, RL = 4Ω, Analog Gain = 8.9
Rev. A |Page 15 of 60
SSM3525
Data Sheet
30
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
1% THD + N
10% THD + N
NORMAL EMI
LOW EMI
0
5
7
9
11
PV (V)
13
15
17
0
1
2
3
4
5
6
7
OUTPUT POWER (W)
DD
Figure 33. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)
and 220pF Capacitor, PVDD = 7 V, Analog Gain = 8.9
Figure 30. Output Power vs. PVDD, RL = 4 Ω, Analog Gain = 12.6
100
90
80
70
60
50
40
40
35
30
25
20
15
NORMAL EMI
LOW EMI
30
20
10
0
1% THD + N
10% THD + N
10
5
0
0
2
4
6
8
10
12
14
16
18
20
5
7
9
11
PV (V)
13
15
17
OUTPUT POWER (W)
DD
Figure 34. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)
and 220 pF Capacitor, PVDD = 12 V, Analog Gain = 12.6
Figure 31. Output Power vs. PVDD, RL = 4 Ω,
Analog Gain = 16
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
30
20
10
0
NORMAL EMI
LOW EMI
0
5
10
15
20
25
30
35
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 35. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)
and 220 pF Capacitor, PVDD = 17 V, Analog Gain = 16
Figure 32. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)
and 220 pF Capacitor, PVDD = 5 V, Analog Gain = 6.3
Rev. A | Page 16 of 60
Data Sheet
SSM3525
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
5
10
15
20
25
30
35
40
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 36. Efficiency vs. Output Power (POUT), RL = 4 Ω, FB and 220 pF
Capacitor, PVDD = 5 V, Analog Gain = 6.3
Figure 39. Efficiency vs. Output Power (POUT), RL = 4 Ω, FB and 220 pF
Capacitor, PVDD = 17 V, Analog Gain = 16
100
90
80
70
60
50
40
8
7
6
5
4
3
NORMAL EMI
LOW EMI
NORMAL MODE
30
20
10
0
LOW EMI MODE
2
1
0
0
1
2
3
4
5
6
7
5
7
9
11
13
15
17
19
OUTPUT POWER (W)
PV (V)
DD
Figure 37. Efficiency vs. Output Power (POUT), RL = 4 Ω, FB and 220 pF
Capacitor, PVDD = 7 V, Analog Gain = 8.9
Figure 40. Quiescent Current, RL = 4 Ω, No FB and 220 pF Capacitor,
Analog Gain = 12.6
100
90
80
70
60
50
40
10
9
8
7
6
5
4
NORMAL EMI
LOW EMI
30
20
10
0
NORMAL MODE
LOW EMI MODE
3
2
1
0
0
5
10
15
20
5
7
9
11
13
15
17
19
OUTPUT POWER (W)
PV (V)
DD
Figure 38. Efficiency vs. Output Power (POUT), RL = 4 Ω, FB and 220 pF
Capacitor, PVDD = 12 V, Analog Gain = 12
Figure 41. Quiescent Current, RL = 4 Ω, FB and 220 pF Capacitor, Analog
Gain = 12.6
Rev. A |Page 17 of 60
SSM3525
Data Sheet
3.5
3.0
2.5
2.0
1.5
1.0
0.5
25
20
15
10
5
1% THD + N
10% THD + N
1% THD + N
10% THD + N
0
5
0
7
9
11
PV (V)
13
15
17
5
7
9
11
PV (V)
13
15
17
DD
DD
Figure 42. Output Power vs. PVDD Supply Voltage (PVDD), RL = 8 Ω,
Analog Gain = 6.3
Figure 45. Output Power vs. PVDD Supply Voltage (PVDD), RL = 8 Ω,
Analog Gain = 16
7
6
5
4
3
100
90
80
70
60
50
40
1% THD + N
10% THD + N
NORMAL EMI
LOW EMI
30
20
10
0
2
1
0
5
7
9
11
PV (V)
13
15
17
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
OUTPUT POWER (W)
DD
Figure 46. Efficiency vs. Output Power (POUT), RL = 8 Ω, No FB and 220 pF
Capacitor, PVDD = 5 V, Analog Gain = 6.3
Figure 43. Output Power vs. PVDD Supply Voltage (PVDD), RL = 8 Ω,
Analog Gain = 8.9
100
90
80
70
60
50
40
14
12
10
8
6
NORMAL EMI
LOW EMI
30
20
10
0
1% THD + N
4
10% THD + N
2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
5
7
9
11
PV (V)
13
15
17
OUTPUT POWER (W)
DD
Figure 47. Efficiency vs. Output Power (POUT), RL = 8 Ω, No FB and 220 pF
Capacitor, PVDD = 7 V, Analog Gain = 8.9
Figure 44. Output Power vs. PVDD Supply Voltage (PVDD), RL = 8 Ω,
Analog Gain = 12.6
Rev. A | Page 18 of 60
Data Sheet
SSM3525
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
0
2
4
6
8
10
12
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 48. Efficiency vs. Output Power (POUT), RL = 8 Ω, No FB and 220 pF
Capacitor, PVDD = 12 V, Analog Gain = 12.6
Figure 51. Efficiency vs. Output Power (POUT), RL = 8 Ω, FB and 220 pF
Capacitor, PVDD = 7 V, Analog Gain = 8.9
100
90
80
70
60
50
40
100
90
80
70
60
50
40
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
30
20
10
0
30
20
10
0
0
5
10
15
20
25
0
2
4
6
8
10
12
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 49. Efficiency vs. Output Power (POUT), RL = 8 Ω, No FB and 220 pF
Capacitor, PVDD = 17 V, Analog Gain = 16
Figure 52. Efficiency vs. Output Power (POUT), RL = 8 Ω, FB and 220 pF
Capacitor, PVDD = 12 V, Analog Gain = 12.6
100
90
80
70
60
50
40
100
90
80
70
60
50
40
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
30
20
10
0
30
20
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
5
10
15
20
25
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 50. Efficiency vs. Output Power (POUT), RL = 8 Ω, FB and 220 pF
Capacitor, PVDD = 5 V, Analog Gain = 6.3
Figure 53. Efficiency vs. Output Power (POUT), RL = 8 Ω, FB and 220 pF
Capacitor, PVDD = 17 V, Analog Gain = 16
Rev. A |Page 19 of 60
SSM3525
Data Sheet
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
5
10
15
20
25
30
35
40
45
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 54. Efficiency vs. Output Power (POUT), RL = 3 Ω, No FB and 220 pF
Capacitor, PVDD = 5 V, Analog Gain = 6.3
Figure 56. Efficiency vs. Output Power (POUT), RL = 3 Ω, No FB and 220 pF
Capacitor, PVDD = 17 V, Analog Gain = 16
100
90
80
70
60
50
40
5
4
3
2
1
0
–1
NORMAL EMI
LOW EMI
CURRENT SENSE
VOLTAGE SENSE
30
20
10
0
–2
–3
–4
–5
0
1
2
3
4
5
6
7
8
9
20
100
1k
10k 20k
OUTPUT POWER (W)
FREQUENCY (Hz)
Figure. Efficiency vs. Output Power (POUT), RL = 3 Ω, No FB and 220 pF
Capacitor, PVDD = 7 V, Analog Gain = 8.9
Figure 57. Current Voltage (I/V) Sense Frequency Response, −20 dBFS
Input Signal, PVDD = 12 V, Analog Gain = 12.6
90
80
70
60
50
40
0
–10
–20
–30
–40
–50
–60
–70
–80
CURRENT SENSE
VOLTAGE SENSE
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
30
NORMAL EMI
LOW EMI
20
10
0
0
5
10
15
20
25
20
100
1k
10k 20k
OUTPUT POWER (W)
FREQUENCY (Hz)
Figure 55. Efficiency vs. Output Power (POUT), RL = 3 Ω, No FB and 220 pF
Capacitor, PVDD = 12 V, Analog Gain = 12.6
Figure 58. I/V Sense FFT, No Signal, PVDD = 12 V, Analog Gain = 12.6
Rev. A | Page 20 of 60
Data Sheet
SSM3525
0
–10
–20
–30
–40
–50
–60
–70
–80
9
8
7
6
5
4
3
2
1
0
V
V
SENSE
OUT
CURRENT SENSE
VOLTAGE SENSE
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
20
100
1k
10k 20k
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
FREQUENCY (Hz)
DIGITAL INPUT (dBFS)
Figure 59. I/V Sense Output FFT, −60 dBFS Input, PVDD = 12 V,
Analog Gain = 12.6
Figure 62. Voltage Sense Output vs. Amplifier Output VRMS, PVDD = 12 V,
Analog Gain = 12.6
0
2.5
–10
I
I
–20
–30
SENSE
OUT
2.0
1.5
1.0
0.5
0
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
CURRENT SENSE
VOLTAGE SENSE
20
100
1k
10k 20k
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
FREQUENCY (Hz)
DIGITAL INPUT (dBFS)
Figure 60. I/V Sense Output FFT, −1 dBFS Input, PVDD = 12 V,
Analog Gain = 12.6
Figure 63. Current Sense Output vs. Amplifier Output Current Arms,
PVDD = 12 V, Analog Gain = 12.6
2.0
1.8
1.6
CURRENT SENSE
VOLTAGE SENSE
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
20
100
1k
10k 20k
FREQUENCY (Hz)
Figure 61. I/V Sense Linearity, −20 dBFS Input, PVDD = 12 V,
Analog Gain = 12.6
Rev. A |Page 21 of 60
SSM3525
Data Sheet
TYPICAL APPLICATION CIRCUITS
+5V (AVDD)
+1.8V (DVDD)
+1.8V
PVDD
+4.5V TO +17V
C1
2.2µF
C2
0.1uF
C3
1µF
C4
C5
10µF
C6
470µF
0.1µF
R1
2.2kΩ
R2
2.2kΩ
VREG/AVDD
SSM3525
IOVDD
PVDD
BST+
SCL
SDA
PVDD
DAC
2
I C
REG
AVDD
2
I C
OPTIONAL
C5
0.22µF
FB1
BCLK
FSYNC
FULL
Σ-Δ
OUT+
OUT–
TDM
BRIDGE
POWER
STAGE
FB2
VOLUME
4Ω/8Ω
2
CLASS-D
I S/TDM
2
I S
MODULATOR
INPUT/
OUTPUT
SDATAI
SDATAO
C7
220pF
C8
220pF
C6
0.22µF
I
BST–
SENSE
V
SENSE
FB1/FB2: MURATA FERRITE BEAD NFZ2MSM181
ADDR
AGND
PGND
SEE THE ADDR PIN SETUP AND CONTROL SECTION
Figure 64. Typical Application Circuit
Rev. A | Page 22 of 60
Data Sheet
SSM3525
THEORY OF OPERATION
The SSM3525 supports two main modes of operation with
OVERVIEW
control and data supplied through the I2C and TDM/I2S ports
(see Table 12).
The SSM3525 Class D audio amplifier features a filterless
modulation scheme that reduces the external component count,
conserving board space and reducing system cost. The SSM3525
does not require an output filter; it relies on the inherent
inductance of the speaker coil and the natural filtering of the
speaker and human ear to recover the audio component of the
square wave output. Most Class D amplifiers use some variation
of pulse-width modulation (PWM), but the SSM3525 uses sigma-
delta (Σ-Δ) modulation to determine the switching pattern of
the output devices, resulting in a number of important benefits:
Σ-Δ modulators do not produce a sharp peak with many
harmonics in the amplitude modulation (AM) broadcast band,
as PWMs often do. Σ-Δ modulation reduces the amplitude of
spectral components at high frequencies, reducing EMI
emission that can otherwise be radiated by speakers and long
cable traces. Due to the inherent spread spectrum nature of Σ-Δ
modulation, the need for oscillator synchronization is eliminated
for designs incorporating multiple SSM3525 amplifiers.
POWER SUPPLIES
The power supply pins on the SSM3525 are as follows:
•
•
PVDD, the power supply, is used for the output stage.
AVDD is the analog supply used for the input stage,
modulator, power stage gate drive, and other blocks. It can
be generated internally by the integrated linear regulator.
Alternatively, if higher system efficiency is needed, connect
the AVDD pin to an external 5 V supply in the system.
If the REG_EN control register is set to 1, the internal
regulator is enabled; otherwise, an external 5 V supply is
required.
•
•
I
OVDD is the digital supply voltage for the serial audio
interface and internal digital circuitry. It must be supplied
externally.
ADDR PIN SETUP AND CONTROL
The SSM3525 also integrates overcurrent and temperature
protection and a thermal warning with optional programmable
gain reduction.
The SSM3525 supports I2C control. The ADDR pin can be set
to four different levels: pulled to GND, pulled up to IOVDD via a
47 kΩ resistor, pulled down to ground via a 47 kΩ resistor, or
left open. The state of the ADDR pin determines the I2C device
address. By default in I2C mode, the device uses the BCLK, FSYNC,
SDATAI, and SDATAO pins for TDM/I2S data. Alternatively, the
device can be set to receive and transmit PDM data by setting
the PDM_MODE register bit field. See Table 12 for setting up the
desired mode.
The SSM3525 contains output voltage and current sensing with
digitization. It also has a temperature sensor and a supply voltage
sensor for the PVDD pin. The PVDD pin is typically connected to
the battery or power supply in the system.
Table 11. I2C Address Selection
ADDR Pin Connection
Control Port Mode
IOVDD Range (V)
1.2 to 1.8
1.2 to 1.8
1.2 to 1.8
1.2 to 1.8
I2C Address
0x24
0x25
0x26
0x27
Not applicable
GND
Pull Down
Open
Pull Up
IOVDD
I2C
I2C
I2C
I2C
Reserved
Not applicable
Table 12. Serial Port Mode Setup for I2S, TDM, and PDM
Pin Usage
BCLK Pin SDATAO Pin FSYNC Pin
Serial Port
Mode
I2S/TDM
IOVDD Range
Description
Sets the part into default I2S/TDM mode
SDATAI Pin
1.2 V to 1.8 V
Bit clock
input
Sense data
output
Frame clock
input
Data input
I2S/TDM
format
I2S/TDM
format
PDM
1.2 V to 1.8 V
Set the PDM_MODE bit to 1 in Register 0x21,
PDM clock Sense data
GND (left
Data input
use FSYNC pin for setting the left/right channel input
output PDM channel) and PDM format
format
IOVDD (right
channel)
Rev. A |Page 23 of 60
SSM3525
Data Sheet
The ADC input range is fixed internally from −60°C to +195°C.
To convert the hexadecimal value to the temperature (Celsius)
value, use the following steps:
POWER-DOWN MODES
The SSM3525 can be powered down by several methods.
Setting the SPWDN bit to 1 in Register 0x20 fully powers down
the device except for the I2C interface. Individual blocks can
also be powered on or off via the block level power-down
controls.
1. Convert the hexadecimal value to decimal and then
subtract 60. For example, if the hexadecimal value is 0x54,
the decimal value is 84.
2. Calculate the temperature using the following equation:
For lowest power shutdown, the SSM3525 also contains a clock
loss detection circuit that monitors the BCLK input clock.
When no BCLK is present, the device automatically powers
down all internal circuitry to its lowest power state. When
BCLK returns, the device automatically powers up following its
usual power sequence.
Temperature = Decimal Value − 60
3. With a decimal value of 84, Temperature = 84 − 60 = 24°C
PCM DIGITAL AUDIO SERIAL INTERFACE
The SSM3525 includes a standard serial audio interface that is
slave only and used when in I2C mode. The interface is capable
of receiving and transmitting I2S, left justified, pulse code
modulated (PCM), or TDM formatted data.
There is an optional auto power-down feature when using
I2S/TDM: the device enters a lower power state when 2048
consecutive zero input samples are received. The device auto-
matically powers back up from this state once a single nonzero
value sample is received. Only the I2C and digital audio input
blocks are active.
There is an input interface for sending audio to the DAC and
amplifier and an output interface for the sense, temperature,
and automatic gain control (AGC) gain data. These interfaces
share the same FSYNC and BCLK signals.
OUTPUT CURRENT SENSING
Provide a BCLK signal to the SSM3525 for correct operation. The
BCLK signal must have a minimum frequency of 2.048 MHz.
The BCLK signal internally clocks the device. The BCLK rate is
auto detected, but the sampling frequency must be known to
the device. At the 32 kHz to 48 kHz sample rate, the supported
BCLK rates are 50, 64, 100, 128, 150, 192, 200, 250, 256, 384,
400, 500, 512, 768, 800, and 1024 times the sample rate.
The SSM3525 uses an integrated sense resistor (50 mΩ typical)
to determine the output current flowing to the load. The voltage
across this sense resistor is proportional to the load current and
sent to a 1-bit ADC running nominally at 128 × fs. The sense
voltage can be output in I2S/TDM format in I2S/TDM mode or via
the PDM interface in PDM mode. The output of this ADC can
also be downsampled using digital filtering. The data is 16 bits,
twos complement and in signed fraction format. This
The serial interfaces have three main operating modes. Stereo
modes, typically I2S or left justified, are used when there are one
or two chips on the interface bus. TDM modes are more flexible
and can support up to 32 chips on the bus. These mode selections
can be set via the I2C interface with the SAI_MODE bit.
downsampled signal is at an 8 kHz to 192 kHz sample rate. It
can be output on the SDATAO pin.
To set a different sample rate for both current and voltage
sensing, use the SNS_FS bit in Register 0x05.
The SAI_DRV bit setting determines the state of the SDATAO
pin during the unused bit clock cycles. When the SAI_DRV bit
is set to 1, the SDATAO pin is driven to logic low or not driven
(high-Z) when set to 0. If using multiple chips on the serial
interface bus, SAI_DRV bit must be set to 0.
OUTPUT VOLTAGE SENSING
The output voltage level is monitored at the OUT pins and
sent to a 1-bit analog to digital converter running nominally at
128 × fs. This can be output in PDM format in PDM mode or
via the PDM interface in PDM mode. The output of this ADC is
can also be downsampled using digital filtering. This
downsampled signal at 8 kHz to 192 kHz sample rate is output
on the digital audio interface. The data is 16 bits twos
complement and in signed fraction format. It can be output on
the SDATAO pin.
STEREO (I2S/LEFT JUSTIFIED) OPERATING MODE
Stereo modes use both edges of the FSYNC signal to determine
placement of data. Stereo mode is enabled when SAI_MODE =
0 and the I2S or left justified format is determined by the
SDATA_FMT bit.
The I2S or left justified formats accepts any number of BCLK
cycles per FSYNC cycle.
TEMPERATURE SENSOR
The SSM3525 contains an 8-bit ADC that measures the die
temperature of the device and is enabled via the TEMP_PWDN bit
in Register 0x20. After the sensor is enabled, the temperature
sense value can be read via the I2C in Register 0x12 in an 8-bit,
unsigned format.
The six placement control registers (Address 0x24 to Address 0x29)
determine placement of input and output data. Odd numbered
placement control registers determine the order on the left channel
and even number on the right channel.
Sample rates from 8 kHz to 192 kHz are accepted.
Rev. A | Page 24 of 60
Data Sheet
SSM3525
Up to four placements can be on the input stream and up to six
placements can be on the output stream. Figure 65 shows a
basic timing diagram of the placements in TDM mode.
TDM OPERATING MODE
The TDM operating mode allows multiple chips to use a single
serial interface bus.
When the serial port is operating in I2S mode, placements
start directly after the FSYNC falling clock edge, signaling the
beginning of a new frame. The first placement is referred to as P1,
the second placement is referred to as P2, for example, increasing
sequentially. The odd numbered placements (P1, P3, and P5)
appear sequentially in the left channel, when the FSYNC signal
is low (assuming FSYNC_MODE = 0), and the even numbered
placements (P2, P4, and P6) appear sequentially in the right
channel, when the FSYNC signal is high (assuming FSYNC_
MODE = 0). Up to four placements can be on the input stream
and up to six placements can be on the output stream. Figure 66
shows a basic timing diagram of the placements in I2S mode.
The FSYNC signal operates at the desired sample rate. A rising
edge of the FSYNC signal indicates the start of a new frame. For
proper operation, this signal must be one BCLK cycle wide,
transitioning on a falling BCLK edge. The MSB of the data
presents on the SDATAO signal one BCLK cycle later. The
SDATAO signal must be latched on a rising edge of BCLK.
Each chip on the TDM bus can occupy 16, 24, 32, 48, or 64
BCLK cycles. This is set with the TDM_BCLKS bit in Register 0x22
and all chips on the bus must have the same setting. Up to 32
SSM3525 chips can be used on a single TDM bus, but only four
unique I2C device addresses are available. The SSM3525 auto-
matically determines how many possible chips can be placed on
the bus from the BCLK rate. There is no limit to the total number
of BCLK cycles per FSYNC pulse, except for the maximum
50 MHz frequency of BCLK.
The corresponding registers (Address 0x22 to Address 0x29)
allow configuration of each data placement. An input placement
(Px_DAC) can carry 24-bit audio data, 16-bit audio data, or 8 zero
bits that are used as padding and ignored. A sense placement
(Px_SNS) can contain 16-bit voltage output data, 16-bit current
output data, 8-bit battery voltage data, 8-bit temperature data,
alternating 16-bit voltage and current data, 8-bit status data, 8-bit
V/I marker and status data, or 8 zero bits.
For standard I2S mode, the serial input is configured to receive
mono audio data and the serial output is configured to send
voltage, current, and battery data back to the host device. The
default register settings correspond to the timing diagram in
Figure 67.
The chip slot of multiple SSM3525 devices used are determined
by the TDM_SLOT bits.
The six placement control registers determine placement of input
and output data within each chip slot. For input data to the DAC,
either 16-bit or 24-bit data can be selected. For output data, there
are multiple options available for placing the voltage sense, current
sense, temperature sense, and PVDD voltage information. See
Bits Px_SNS in Register 0x24 to Register 0x29.
SERIAL DATA PLACEMENT
When the 8-bit status output is selected, that 8-bit placement
area outputs the same bits that are found in the read only
STATUS register. The format can be seen in Table 13. When the
8-bit V/I marker and status output placement is selected, the
MSB indicates whether voltage sense or current sense is being
output on that sample frame, and the 7 LSBs correspond to the
STATUS register, the formatting for can be seen in Figure 14.
The SSM3525 is flexible in where within a frame it places output
data and where it looks for input data. There are four control
bits (Px_DAC) for when input data is expected and six control
bits (Px_SNS) for when output data is driven.
A single data frame is broken up into individual fields, referred
to as placements. Each placement can be 8 bits, 16 bits, or 24 bits in
length. A single frame on the TDM or I2S data stream can contain
several data placements of varying length.
When the serial port is operating in TDM mode, placements start
directly after the FSYNC pulse. The first placement is referred
to as P1, and the second placement is referred to as P2, for
example, increasing sequentially. These placements appear in
sequential order on the serial data signal.
BCLK
FSYNC
DAC_SDATAI
P1
P2
Px
8 BITS/16 BITS/24 BITS
Figure 65. Basic Timing Diagram of Placements in TDM Stream
Rev. A |Page 25 of 60
SSM3525
Data Sheet
BCLK
FSYNC
DAC_SDATAI
P1
P3
P2
P4
8 BITS/16 BITS/24 BITS
Figure 66. Basic Timing Diagram of Placements in I2S Stream
BCLK
FSYNC
DAC_SDATAI
DAC_SDATAO
DAC INPUT
VOLTAGE
16 BCLKs
BATTERY
8 BCLKs
CURRENT
16 BCLKs
Figure 67. Standard I2S Data Placement Timing Diagram
BCLK
FSYNC
32 BCLKS
24
DAC DATA 1
DAC DATA 2
DAC_SDATAI
DAC_SDATAO
16
16
1
I
1
V
I
2
SENSE
SENSE
Figure 68. TDM Serial Interface Format
Table 13. 8-Bit Status Sense Output Format (STATUS Register)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
UVLO_VREG
UVLO_PVDD
LIM_EG
CLIP
AMP_OC
OTF
OTW
BAT_WARN
Table 14. 8-Bit V/I Marker and Status Sense Output Format (STATUS Register)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1 = VSENSE, 0 = ISENSE
UVLO_PVDD
LIM_EG
CLIP
AMP_OC
OTF
OTW
BAT_WARN
BCLK
FSYNC
SDATA
I
V
I
V
I
V
I
V
I
V
I
V
I
Figure 69. SDATA Output in PDM Mode
PDM OPERATING MODE
Table 15. FSYNC Settings for PDM Mode
By setting the PDM_MODE bit in Register 0x21 to 1, the 1-bit
PDM data from the sense ADCs can be output directly on
SDATAO, and the DAC can be driven with 1-bit PDM data on
SDATAI. In this case, a 2.048 MHz to 6.144MHz CLK must be
provided on the BCLK pin.
SDATA Input
FSYNC Pin Configuration
Use L Channel Data
Use R Channel Data
Connect to IOVDD
Connect to GND
PDM data is output on both edges of the clock. The current
sense ADC data is output when BCLK is high, and the voltage
sense ADC data is output when BCLK is low. Refer to Table 12
and Figure 69.
PDM input data is latched on both edges of the clock. The
FSYNC pin state determines which channel (left or right) is
sent to the DAC.
Rev. A | Page 26 of 60
Data Sheet
SSM3525
Table 17. Register 0x10 Fault Recovery
ANALOG AND DIGITAL GAIN
Status Reported
Register
There are several selectable settings for the analog gain of the
system via the ANA_GAIN bits. These bits are designed to
provide optimal gain staging at various PVDD supply voltages.
Fault Type
Flag Set Condition
OTW
The amount of gain
reduction applied if
there is an OTW
Register 0x10, Bits[7:6],
OTW_GAIN
There is also a digital gain/volume control in the DAC_VOL
register that provides fine control in 0.375 dB steps from −70 dB
to +24 dB.
Manual
Recovery
Use to attempt manual Register 0x10, Bit 5,
recovery in case of a
fault event
MRCV
Autorecovery
Attempts
When autorecovery
from faults is used, set
the number of attempts
using this bit
Recovery can be
automatic or manual
Recovery can be
automatic or manual
Recovery can be
automatic or manual
Register 0x10, Bits[4:3],
MAX_AR
PVDD (VBAT) SENSING
The SSM3525 contains an 8-bit ADC that measures the voltage of
the battery voltage (VBAT) supply. The battery voltage information is
stored in Register 0x13 as an 8-bit unsigned format. The ADC
input range is fixed internally as 4 V to 18 V. To convert the
hexidecimal value to the voltage value, use the following steps:
UV
Register 0x10, Bit 2,
ARCV_UV
Register 0x10, Bit 1,
ARCV_OT
Register 0x10, Bit 0,
ARCV_OC
Die OT
OC
1. Convert the hex value to decimal. For example, if the
hexadecimal value is 0xA9, the decimal value is 169.
2. Calculate the voltage using the following equation:
When the automatic recovery mode is set, the device attempts
to recover itself after the fault event and, in case the fault
persists, the device sets the fault again. This process repeats
until the fault is resolved.
Voltage = 4 V + 14 V × Decimal Value/255
With a decimal value of 169,
Voltage = 4 V + 14 V × 169/255 = 13.278 V
When using the manual recovery mode, the device shuts down
and the recovery must be attempted using the system
microcontroller.
This data can be output on the SDATAO pin along with V/I
sense data or read via the VBAT register over the control
interface, as previously mentioned.
LIMITER AND BATTERY TRACKING THRESHOLD
CONTROL
FAULTS AND LIMITER STATUS REPORTING
The SSM3525 offers comprehensive protections against the
faults at the outputs and reporting to help with system design.
The faults listed in Table 16 are reported using the status registers.
The SSM3525 contains an output limiter that can limit the peak
output voltage of the amplifier. The limiter works on the rms
and peak value of the signal. The limiter threshold, slope, attack
rate, and release rate are programmable using Register 0x08,
Register 0x09, and Register 0x0A. The limiter can be enabled or
disabled using LIM_EN, Bits[1:0] in Register 0x08.
Table 16. Register 0x11 Faults
Flag Set
Condition
Status Reported
Register
Fault Type
5 V Regulator or AVDD 5 V regulator
Undervoltage (UV) voltage at VREG/
AVDD < 3.6 V
Register 0x11, Bit 7,
UVLO_VREG
The threshold at which the output starts limiting is determined
by the LIM_THRES register setting, in Register 0x09, Bits[7:3].
When the ouput signal level exceeds the set threshold level, the
limiter activates and limits the signal level to the set limit. Below
the set threshold, the output level is not affected. The limiter
PVDD Undervoltage
When PVDD < 3.6V Register 0x11, Bit 6,
UVLO_PVDD
Limiter/Gain Reduction Limiter engaged
Engage
Register 0x11,
Bit 5, LIM_EG
threshold can be set from 2 VPEAK to 16 VPEAK
.
Clipping
DAC clipping
Register 0x11,
Bit 4, CLIP
The limiter threshold can be set above the maximum output
voltage of the amplifier. In this case, the limiter allows maximum
peak output; the output can clip depending on the power supply
voltage and not the limiter.
Output Overcurrent
(OC)
Die Overtemperature Die temperature > Register 0x11,
(OT) 145°C Bit 2, OTF
Die Overtemperature Die temperature > Register 0x11,
Warning (OTW)
Battery Voltage >
VBAT_INF
Output current > Register 0x11,
6 A peak Bit 3, AMP_OC
The limiter threshold can be set as fixed or to vary with the
battery voltage via the VBAT_TRACK bit (Register 0x08, Bit 2).
When set to fixed, the limiter threshold is fixed and does not
vary with battery voltage. The threshold can be set from 2 VPEAK to
16 VPEAK using the LIM_THRES bit (see Figure 71).
117°C
Battery voltage
PVDD > VBAT_INF
Bit 4, OTW
Register 0x11,
Bit 0, BAT_WARN
When set to a variable threshold, the SSM3525 monitors the
VBAT supply and automatically adjusts the limiter threshold
based on the VBAT supply voltage.
The faults listed in Table 16 are reported in Register 0x11 and
can be read via I2C by the microcontroller in the system.
In the event of a fault occurrence, how the device reacts to the
faults can be controlled by using Register 0x10.
Rev. A |Page 27 of 60
SSM3525
Data Sheet
The VBAT supply voltage at which the limiter threshold level
begins to decrease the output level is determined by the VBAT
inflection point, the VBAT_INF bits (Register 0x0A, Bits[7:0]).
The limiter, when active, reduces the gain of the amplifier. The rate
of gain reduction or attack rate is determined by the LIM_ATR bits
(Register 0x08, Bits[5:4]). Similarly, when the signal level drops
below the limiter threshold, the gain is restored. The gain release
rate is determined by the LIM_RRT bits (Register 0x08, Bits[7:6]).
The VBAT_INF point is defined as the battery voltage at which
the limiter either activates or deactivates depending on the
LIM_EN mode (see Table 18). When the battery voltage is
greater than VBAT_INF, the limiter is not active. When the
battery voltage is less than VBAT_INF, the limiter is activated.
The VBAT_INF bits can be set from 4 V to 18 V. The 8-bit value
for the voltage can be calculated using the following equation:
LIM_EN = 00
VBAT_TRACK = 0
AMPLIFIER CLIPPING LEVEL
Voltage = 4 + 14 × Decimal Value/255
Convert the decimal value to an 8-bit hexadecimal value and
use it to set the VBAT_INF bits.
The rate at which the limiter threshold is lowered relative to
the amount of change in VBAT below the VBAT_INF point is
determined by the slope bits (Register 0x09, Bits[1:0]).
INPUT LEVEL
The slope is the ratio of the limiter threshold reduction to the
VBAT voltage reduction.
Figure 70. Limiter Example (LIM_EN = 0b00, VBAT_TRACK = 0bx)
Slope = ∆Limiter Threshold/∆VBAT
LIMITER THRESHOLD FIXEDAT SET VALUE
AND DOES NOT TRACK VBAT
The slope ratio can be set from 1:1 to 4:1. This function is useful
to prevent early shutdown under low battery conditions. As the
LIM_THRES
V
BAT voltage falls, the limiter threshold is lowered. The limiter
reduces the output level, therefore helping reduce the current
drawn from the battery and preventing early shutdown due to low
VBAT.
The limiter offers various active modes, which can be set using the
LIM_EN bits (Register 0x08, Bits[1:0]) and the VBAT_TRACK bit,
as shown in Table 18.
VBAT
When LIM_EN = 01, the limiter is enabled. When LIM_EN = 10,
the limiter mutes the output if VBAT falls below VBAT_INF. When
LIM_EN = 11, the limiter engages only when the battery voltage
is lower than VBAT_INF.
Figure 71. Limiter Fixed (LIM_EN = 0b01, VBAT_TRACK = 0b0)
When VBAT is above VBAT_INF, no limiting occurs. There is
hysteresis around VBAT_INF for the limiter disengaging.
Table 18. Limiter Modes
LIM_EN
VBAT_TRACK
Limiter
No
VBAT < VBAT_INF
Not applicable
VBAT > VBAT_INF
Not applicable
Comments
00
0 or 1
See Figure 70
01
01
10
11
0
1
Fixed
Variable
Fixed
Fixed
Variable
Use the set threshold
Lowers the threshold
Mutes the output
Use the set threshold
Lowers the threshold
Use the set threshold
Use the set threshold
Use the set threshold
No limiting
See Figure 71
See Figure 72 and Figure 73
Not applicable
See Figure 74 and Figure 75
See Figure 76 and Figure 77
0 or 1
0
1
11
No limiting
Rev. A | Page 28 of 60
Data Sheet
SSM3525
LIM_EN = 01
VBAT_TRACK = 1
LIMITER THRESHOLD FIXEDAT SET VALUE
AND DOES NOT TRACK VBAT
LIM_THRES
VBAT > VBAT_INF LIMITER
LIMITER THRESHOLD SETTING
LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF
CHANGE IN LIM THRESHOLD = N × (VBAT_INF – VBAT)
WHERE N = 1 TO 4, SET USING SLOPE BIT IN REG 0x09
VBAT
INPUT LEVEL
Figure 72. Limiter Fixed (LIM_EN = 0b01, VBAT_TRACK = 0b1)
Figure 75. Limiter Fixed (LIM_EN = 0b11, VBAT_TRACK = 0b0)
LIM_EN = 11
VBAT_TRACK = 1
LIMITER THRESHOLD STAYS AT
THE SET VALUE FOR VBAT > VBAT_INF
VBAT > VBAT_INF LIMITER IS NOTACTIVE
AMPLIFIER CLIPPING LEVEL
VBAT_INF
LIM_THRES
LIMITER THRESHOLD SETTING
LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF
SLOPE
LIMITER THRESHOLD LOWERS
FOR VBAT < VBAT_INF
CHANGE IN LIM THRESHOLD = N × (VBAT_INF – VBAT)
WHERE N = 1 TO 4, SET USING SLOPE BIT IN REG 0x09
INPUT LEVEL
VBAT
Figure 73. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN = 0b01,
VBAT_TRACK = 0b1)
Figure 76. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0b1)
LIMITER THRESHOLD INACTIVE FOR VBAT > VBAT_INF
LIM_EN = 11
VBAT_TRACK = 0
VBAT_INF
SET LIM_THRES
AMPLIFIER CLIPPING LEVEL
LIMITER THRESHOLD SETTING
NO CHANGE IN LIM THRESHOLD PER VBAT
SLOPE
LIMITER THRESHOLD LOWERS
FOR VBAT < VBAT_INF
VBAT
Figure 77. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN = 0b11,
VBAT_TRACK = 0b1)
INPUT LEVEL
Figure 74. Limiter Example (LIM_EN = 0b11, VBAT_TRACK = 0)
Rev. A |Page 29 of 60
SSM3525
Data Sheet
Linking Limiters of Multiple SSM3525 Devices
HIGH FREQUENCY CLIPPER
If multiple SSM3525 devices are used in a system, the gain
adjustment from the limiters of all or some of the devices can be
linked. The device internally generates the gain adjustment
value (AGC_GAIN) based on the limiter settings. When
limiters of multiple devices on the bus are linked, the device
uses the highest (most gain reduction) gain adjustment value
(AGC_GAIN) of all devices. Up to four SSM3525 devices can
be linked in this manner.
The high frequency clipper can be controlled via the
DAC_CLIP bits (Register 0x0F, Bits[7:0]).
These bits determine the clipper threshold, relative to full scale.
When enabled, the clipper digitally clips the signal after the
DAC interpolation.
EMI NOISE
The SSM3525 uses a proprietary modulation and spread
spectrum technology to minimize EMI emissions from the
device. The SSM3525 passes FCC Class B emissions testing with
an unshielded 20 inch cable using ferrite bead-based filtering.
For applications that have difficulty passing FCC Class B
emission tests, the SSM3525 includes an ultralow EMI
emissions mode that significantly reduces the radiated emissions at
the Class D outputs, particularly above 100 MHz. Reducing the
supply voltage greatly reduces radiated emissions.
To link the AGC_GAIN to other chips, the LIM_LINKx bits
must be set in the LIM_LINK register, 0x0E.
When using I2S/TDM, for every chip that is linked, the placement
of its respective AGC_GAIN value within the TDM stream must
be given. The AGC_GAIN data for a respective device is made
available at the assigned slot using the AGC_GAINx_SLOT bits.
The AGC_GAIN data is eight bits wide and in an assigned slot,
these bits can be placed in any one of eight places in a 64-bit
frame. This setting is available in the AGC_GAINx_PLACE
register. These values can be set in Register 0x2A through Register
0x2D.
OUTPUT MODULATION DESCRIPTION
The SSM3525 uses three-level, Σ-Δ output modulation. Each
output can swing from ground to PVDD, and vice versa. Ideally,
when no input signal is present, the output differential voltage is
0 V because there is no need to generate a pulse. In a real-world
situation, noise sources are always present.
The audio signal is not affected by the AGC function unless the
peak audio output voltage exceeds the limiter threshold level.
POP AND CLICK SUPPRESSION
Due to this constant presence of noise, a differential pulse is
occasionally generated in response to this stimulus. A small
amount of current flows into the inductive load when the
differential pulse is generated. However, typically, the output
differential voltage is 0 V. This feature ensures the current flowing
through the inductive load is small.
Voltage transients at the output of audio amplifiers can occur
when shutdown is activated or deactivated. Voltage transients
as small as 10 mV can be heard as an audible pop in a speaker.
Clicks and pops are defined as undesirable audible transients,
generated by the amplifier system, that do not come from the
system input signal.
When the user sends an input signal, an output pulse is generated
to follow the input voltage. The differential pulse density is
increased by raising the input signal level. Figure 78 depicts
three-level, Σ-Δ output modulation with and without input
stimulus.
Such transients can be generated when the amplifier system
changes its operating mode. For example, system power-up and
power-down can be sources of audible transients.
The SSM3525 has a pop and click suppression architecture that
reduces these output transients, resulting in noiseless activation and
deactivation.
Set either mute or power-down before the BCLK signal is
removed to ensure a pop free power-down.
Rev. A | Page 30 of 60
Data Sheet
SSM3525
OUTPUT = 0V
+5V
OUT+
OUT–
0V
+5V
0V
+5V
VOUT
0V
OUTPUT > 0V
+5V
OUT+
OUT–
VOUT
0V
+5V
0V
+5V
0V
OUTPUT < 0V
+5V
OUT+
OUT–
VOUT
0V
+5V
0V
+5V
0V
Figure 78. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
Rev. A |Page 31 of 60
SSM3525
Data Sheet
BOOTSTRAP CAPACITORS
OUTPUT EMI FILTERING
The output stage of the SSM3525 uses a high-side N-channel
metal-oxide semiconductor (NMOS) driver, rather than a
P-channel metal-oxide semiconductor (PMOS) driver. To generate
the gate drive voltage for the high-side NMOS, a bootstrap
capacitor for each output terminal acts as a floating power supply
for the switching cycle. Use 0.22 μF capacitors to connect the
appropriate output pin (OUT ) to the bootstrap pin (BST ). For
example, connect a 0.22 μF capacitor between OUT+ and BST+
for bootstrapping the OUT+ pin. Similarly, connect another 0.22
μF capacitor between the OUT− and BST− pins for the OUT−
pin.
Additional EMI filtering may be required when the speaker
traces and cables are long and present a significant capacitive
load that can create additional draw from the amplifier. Typical
power ferrites present a significant magnetic hysteresis cycle
that affects THD performance and are not recommended for
high performance designs. The NFZ series ferrite beads from
Murata are recommended. These ferrite beads provide a closed
hysteresis loop similar to an air coil with minimum impact on
performance. The ferrite beads with output current rating ≥4 A
rms, are recommended for this application. A 220 pF capacitor
can be added between the output of the filter and ground to
further attenuate high frequencies. Ensure the capacitor is
properly sized so as not to affect idle power consumption or
efficiency.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low THD, and high PSRR, proper
power supply decoupling is necessary. Noise transients on the
power supply lines are short duration voltage spikes. These spikes
can contain frequency components that extend into the hundreds
of megahertz. The power supply input must be decoupled with
a low equivalent series inductance (ESL) and a low equivalent
series resistance (ESR) bulk capacitor larger than 220 µF. For high
frequency decoupling, place 1 µF capacitors as close as possible to
the PVDD pins of the device.
PCB COMPONENT PLACEMENT
Component selection and placement have great influence on
system performance, both measured and subjective. Proper
PVDD layout and decoupling is necessary to reach the specified
level of performance, particularly at the highest power levels.
The placement shown in Figure 79 ensures proper output stage
decoupling for each channel, for minimum supply noise and
maximum separation between channels. Additional bulk de-
coupling is necessary to reduce current ripple at low frequencies,
and can be shared between several amplifiers in a multichannel
solution.
PVDD DECOUPLING CAPACITOR
BST+ 0.22µF CAPACITOR
BST+ 0.22µF CAPACITOR
IOVDD DECOUPLING CAPACITOR
AVDD DECOUPLING CAPACITOR
Figure 79. Recommended Component Placement {should PVDD, AVDD, and IOVDD be AVDD, PVDD, IOVDD
?
Rev. A | Page 32 of 60
Data Sheet
SSM3525
Addressing
LAYOUT
Initially, each device on the I2C bus is in an idle state, monitoring
the SDA and SCL lines for a start condition and the proper
address. The I2C master initiates a data transfer by establishing a
start condition, defined by a high to low transition on SDA while
SCL remains high. This transition indicates that an address or
data stream follows. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus the
As output power increases, take care to lay out PCB traces and
wires properly among the amplifier, load, and power supply; a
poor layout increases voltage drops, consequently decreasing
efficiency. A good practice is to use short, wide PCB tracks to
decrease voltage drops and minimize inductance. For the lowest
dc resistance (DCR) and minimum inductance, ensure that
trace widths for the speaker outputs are at least 200 mil for
every inch of length and use 1 oz or 2 oz copper.
W
R/ bit) MSB first. The device that recognizes the transmitted
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is an acknowledge bit. All other
devices withdraw from the bus at this point and return to the
idle condition. The device address for the SSM3525 is
determined by the state of the ADDR pin. See Table 20 for four
available addresses.
To maintain high output swing and high peak output power, the
PCB traces that connect the output pins to the load and supply
pins must be as wide as possible. In addition, good PCB layout
isolates critical analog paths from sources of high interference.
Separate high frequency circuits (analog and digital) from low
frequency circuits.
W
The R/ bit determines the direction of the data. A Logic 0 on
PVDD and PGND carry most of the device current, and must
be properly decoupled with multiple capacitors close to the
device power supply and ground pins. To minimize ground
bounce, use independent power planes to carry PVDD and
PGND to the power supply. Proper grounding guidelines help
improve audio performance, minimize crosstalk between
channels, and prevent switching noise from coupling into the
audio signal.
the LSB of the first byte means the master writes information to
the peripheral, whereas a Logic 1 means the master reads
information from the peripheral after writing the subaddress
and repeating the start address. A data transfer occurs until a
stop condition is encountered. A stop condition occurs when
SDA transitions from low to high while SCL is held high. The
timing for the I2C port is shown in Figure 80.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the SSM3525 immediately
jumps to the idle condition. During a given SCL high period,
the user must issue only one start condition, one stop condition, or
a single stop condition followed by a single start condition. If
the user issues an invalid subaddress, the SSM3525 does not
issue an acknowledge and returns to the idle condition. If the
user exceeds the highest subaddress while in auto-increment mode,
one of two actions is taken.
Properly designed multilayer PCBs can reduce electromagnetic
emission and improve radio frequency (RF) immunity, compared
with double-sided boards. A multilayer board allows a complete
layer to be used for the ground plane, whereas the ground plane
side of a double-sided board is often disrupted by signal traces.
If the system has separate analog and digital ground and power
planes, the analog ground plane must be directly beneath the
analog power plane, and, similarly, the digital ground plane must
be directly beneath the digital power plane. There must be no
overlap between the analog and digital ground planes or between
the analog and digital power planes.
In read mode, the SSM3525 outputs the highest subaddress register
contents until the master device issues a no acknowledge, indi-
cating the end of a read. A no acknowledge condition is when the
SDA line is not pulled low on the ninth clock pulse on SCL. If the
highest subaddress location is reached while in write mode, the
data for the invalid byte is not loaded into any subaddress register,
a no acknowledge is issued by the SSM3525, and the device
returns to the idle condition.
I2C CONTROL
The SSM3525 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the SSM3525 and the system I2C master controller. The
SSM3525 is always a slave on the bus, meaning it cannot initiate
a data transfer. Each slave device is recognized by a unique address.
Using the ADDR pin provides the four device addresses, which are
listed in Table 20. The address byte format is shown in Table 19.
The address resides in the first seven bits of the I2C write. The
LSB of this byte sets either a read or write operation. Logic Level 1
corresponds to a read operation, and Logic Level 0 corresponds
to a write operation.
I2C Read and Write Operations
Figure 81 shows the timing of a single-word write operation.
Every ninth clock, the SSM3525 issues an acknowledge (ACK)
by pulling SDA low.
Figure 82 shows the timing of a burst mode write sequence. This
figure shows an example in which the target destination registers
are two bytes. The SSM3525 increments its subaddress register
every byte because the requested subaddress corresponds to a
register or memory area with a byte word length.
Connect 2.2 kΩ pull-up resistors on the lines connected to the
SDA and SCL pins. The voltage on these signal lines must not
be more than 5 V.
Rev. A |Page 33 of 60
SSM3525
Data Sheet
The timing of a single word read operation is shown in Figure 83.
Figure 81 through Figure 84 use the following abbreviations:
W
The first R/ bit is 0, indicating a write operation followed by
•
•
•
•
S is the start bit
P is the stop bit
AM is the acknowledge by master
AS is the acknowledge by slave
the subaddress of the register to be read. After the SSM3525
acknowledges the receipt of the subaddress, the master must issue
a repeated start command followed by the chip address byte with
W
the R/ set to 1 (read). The SSM3525 acknowledges and puts
8-bit data on the SDA pin. The master then responds every
ninth pulse with an acknowledge pulse to the SSM3525.
Table 19. I2C Device Address Byte Format Using the ADDR Pin1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
1
X
X
R/W
1 X means don’t care.
Table 20. ADDR Pin to I2C Device Address Mapping
ADDR Pin
ADDR Voltage
I2C Address Bit 2
I2C Address Bit 1
GND
GND
0
0
Pull-Down 47 kΩ Resistor
Open
Pull-Up 47 kΩ Resistor
IOVDD
0.25 × IOVDD
0.5 × IOVDD
0.75 × IOVDD
IOVDD
0
1
1
1
0
1
Not applicable
Not applicable
SCK
SDA
R/W
ACK
ACK
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE
START BY
MASTER
SCK
(CONTINUED)
SDA
(CONTINUED)
ACK
ACK
FRAME 3
DATA BYTE 1
FRAME 4
DATA BYTE 2
STOP BY
MASTER
Figure 80. I2C Read/Write Timing
2
START
BIT
I C ADDRESS
(7 BITS)
ACK BY
SLAVE
SUBADDRESS
(8 BITS)
ACK BY
SLAVE
DATA BYTE 1
(8 BITS)
STOP
BIT
R/W= 0
Figure 81. Single Word I2C Write Format
CHIP ADDRESS,
DATA
WORD 1
DATA
WORD 2
S
A
SUBADDRESS
A
A
A
S
P
S
S
S
R/W = 0
Figure 82. Burst Mode I2C Write Format
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
DATA
BYTE 1
DATA
BYTE N
S
A
SUBADDRESS
A
S
A
A
M
P
S
S
S
R/W = 1
Figure 83. Single Word I2C Read Format
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
DATA
WORD 1
S
A
SUBADDRESS
A
S
A
A
M
P
S
S
S
R/W = 1
Figure 84. Burst Mode I2C Read Format
Rev. A | Page 34 of 60
Data Sheet
SSM3525
APPLICATIONS INFORMATION
Figure 64 shows typical application for a single channel using
I2S/TDM input and I2C control. In a typical application, the
PVDD and IOVDD are supplied externally. AVDD can be generated
using an internal regulator by setting the REG_EN bit in Register
0x04 to 1. Alternately, AVDD can be provided externally and
disabling the REG_EN bit. By default, the AVDD regulator is
disabled. The IOVDD by default is set to 1.8 V and can be
changed to 1.2 V by using the IOVDD_SEL bit in Register 0x20.
The slew rate for the output can be set to low EMI mode in
Register 0x05. By default, the slew rate is set to normal mode. In
low EMI mode, the output slew rate is reduced to lower the
radiated emissions at the speaker output.
The device can be reset to default settings by writing 1 to the
S_RST bit in Register 0x2E. This bit must be cleared by writing
0 to bring the device out of reset.
The PVDD (VBAT) sense cannot be powered down and is enabled
by default. By default, the high pass filter is enabled and it is
recommended to keep it enabled to block the dc from
appearing at the speaker outputs.
During power up, turn the PVDD supply on first, followed by
IOVDD. While powering off, turn off the IOVDD supply first,
followed by PVDD. The IOVDD must be stable before I2C
commands are sent to the device. The digital input data can be
2-channel I2S or multichannel TDM format, and the desired
format must be selected in the SAI control registers. Refer to the
PCM Digital Audio Serial Interface section.
The fault status register, 0x11, can be read to check for any fault
conditions during operation.
FB1, FB2, C7, and C8 (see Figure 64) are recommended for
filtering the switching noise and must be placed closer to the
amplifier outputs to be effective.
On power-up, the device stays in power-down; to enable the
amplifier, the SPWDN bit in Register 0x20 must be set to 0.
Once this bit is set to 0, the amplifier turns on and the output
starts switching.
Rev. A | Page 35 of 60
SSM3525
Data Sheet
SSM3525 I2C MODE REGISTER MAP (SSM3525_I2C_REGMAP) REGISTER SUMMARY
Table 21. SSM3525_I2C_REGMAP Register Summary
Reg
Name
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
VENDOR
Bit 2
Bit 1
Bit 0
Reset RW
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
VENDOR_ID
DEVICE_ID1
DEVICE_ID2
REVISION_ID
REG_ENABLE
AMP_CTRL
DAC_CTRL
DAC_VOL
0x41
0x35
0x25
0x01
0x00
0x22
0x32
0x40
0xA4
0x51
0x22
R
DEVICE1
DEVICE2
REVISION
R
R
R
RESERVED
REG_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
[7:0] SNS_HPF_BP
[7:0] DAC_HV
[7:0]
SNS_FS
DAC_HPF
RESERVED
DAC_POL
EDGE
ANA_GAIN
DAC_FS
DAC_MUTE
DAC_LPM
VOL
RESERVED
LIM_CTRL1
LIM_CTRL2
LIM_CTRL3
[7:0]
[7:0]
[7:0]
LIM_RRT
LIM_ATR
LIM_THRES
VBAT_TRACK
RESERVED
LIM_EN
SLOPE
VBAT_INF
VBAT_LIM_CTRL1 [7:0]
VBAT_LIM_CTRL2 [7:0]
VBAT_LIM_RRT
VBAT_LIM_ATR
RESERVED
VBAT_LIM_EN 0xA0
VBAT_THRES
0x22
0x65
0x0D VBAT_LIM_CTRL3 [7:0]
VBAT_LIM_MAX_ATTN
RESERVED
VBAT_LIM_HOLD
0x0E
0x0F
0x10
0x11
0x12
0x13
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
LIM_LINK
[7:0]
LIM_LINK4 LIM_LINK3
LIM_LINK2
LIM_LINK1
0x00
0xFF
0x18
0x00
0x00
0x00
0x05
0x00
0x21
0x00
0x01
0x21
0x21
0x21
0x01
0x01
0x00
0x00
0x00
0x00
0x00
DAC_CLIP
FAULT_CTRL
STATUS
[7:0]
DAC_CLIP
MAX_AR
[7:0]
OTW_GAIN
MRCV
ARCV_UV
OTF
ARCV_OT
OTW
ARCV_OC
[7:0] UVLO_VREG
UVLO_PVDD LIM_EG
CLIP
AMP_OC
BAT_WARN
TEMP
[7:0]
[7:0]
TEMP
VBAT
R
VBAT
R
PWR_CTRL
PDM_CTRL
SAI_CTRL1
SAI_CTRL2
SAI_PLACE1
SAI_PLACE2
SAI_PLACE3
SAI_PLACE4
SAI_PLACE5
SAI_PLACE6
AGC_PLACE1
AGC_PLACE2
AGC_PLACE3
[7:0]
RESERVED
VSNS_PWDN ISNS_PWDN RESERVED
PDM_FS
TEMP_PWDN
RESERVED
IOVDD_SEL
SPWDN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
[7:0]
RESERVED
PDM_MODE
[7:0] SAI_DRV
[7:0]
TDM_BCLKS
BCLK_POL FSYNC_MODE SDATA_FMT SAI_MODE
RESERVED
TDM_SLOT
P1_SNS
[7:0]
RESERVED
P1_DAC
[7:0]
RESERVED
RESERVED
RESERVED
P2_DAC
P3_DAC
P4_DAC
P2_SNS
[7:0]
P3_SNS
[7:0]
P4_SNS
[7:0]
RESERVED
RESERVED
P5_SNS
[7:0]
P6_SNS
[7:0]
AGC_GAIN1_PLACE
AGC_GAIN1_SLOT
AGC_GAIN2_SLOT
AGC_GAIN3_SLOT
AGC_GAIN4_SLOT
S_RST
[7:0]
AGC_GAIN2_PLACE
AGC_GAIN3_PLACE
AGC_GAIN4_PLACE
[7:0]
0x2D AGC_PLACE4
0x2E SOFT_RESET
[7:0]
[7:0]
RESERVED
Rev. A | Page 36 of 60
Data Sheet
SSM3525
SSM3525 I2C MODE REGISTER MAP (SSM3525_I2C_REGMAP) REGISTER DETAILS
ADI VENDOR ID REGISTER
Address: 0x00, Reset: 0x41, Name: VENDOR_ID
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
1
[7:0] VENDOR (R)
ADI Vendor ID
Table 22. Bit Descriptions for VENDOR_ID
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VENDOR
ADI Vendor ID
0x41
R
DEVICE ID 1 REGISTER
Address: 0x01, Reset: 0x35, Name: DEVICE_ID1
7
6
5
4
3
2
1
0
0
0
1
1
0
1
0
1
[7:0] DEVICE1 (R)
SSM3525 Device ID 1
Table 23. Bit Descriptions for DEVICE_ID1
Bits
[7:0]
Bit Name
DEVICE1
Settings
Description
SSM3525 Device ID 1
Reset
0x35
Access
R
DEVICE ID 1 REGISTER
Address: 0x02, Reset: 0x25, Name: DEVICE_ID2
7
6
5
4
3
2
1
0
0
0
1
0
0
1
0
1
[7:0] DEVICE2 (R)
SSM3525 Device ID 2
Table 24. Bit Descriptions for DEVICE_ID2
Bits
[7:0]
Bit Name
DEVICE2
Settings
Description
SSM3525 Device ID 2
Reset
0x25
Access
R
REVISION ID REGISTER
Address: 0x03, Reset: 0x01, Name: REVISION_ID
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] REVISION (R)
Revision ID
Table 25. Bit Descriptions for REVISION_ID
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
REVISION
Revision ID
0x1
R
Rev. A | Page 37 of 60
SSM3525
Data Sheet
REGULATOR ENABLE AND IOVDD SELECTION REGISTER
Address: 0x04, Reset: 0x00, Name: REG_ENABLE
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] REG_EN (R/W)
Internal Regulator Enable
0: Never enable internal regulator.
1: Normal operation. Internal regulator
turns on if VREG is not applied externally.
Table 26. Bit Descriptions for REG_ENABLE
Bits
[7:1]
0
Bit Name
RESERVED
REG_EN
Settings
Description
Reserved.
Reset
0x0
0x0
Access
R
R/W
Internal Regulator Enable
Never enable internal regulator.
Normal operation. Internal regulator turns on if VREG is not applied externally.
0
1
AMPLIFIER GAIN, EDGE CONTROL, AND SENSE SAMPLE RATE REGISTER
Address: 0x05, Reset: 0x22, Name: AMP_CTRL
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
0
[7] SNS_HPF_BP (R/W)
I/V Sense High Pass Filter On/Off
0: I/V sense high pass filter on.
1: I/V sense high pass filter off.
[1:0] ANA_GAIN (R/W)
Amplifier Analog Gain Select
0: +13 dB (6.3x)
1: +16 dB (8.9x)
10: +19 dB (12.6x)
11: +21 dB (16x)
[6:4] SNS_FS (R/W)
Sense Sample Rate
00: 8 kHz to 12 kHz I and V sense sample
[2] EDGE (R/W)
rate.
Edge Rate Control
01: 16 kHz to 24 kHz I and V sense sample
0: Normal operation.
1: Low EMI mode operation.
rate.
10: 32 kHz to 48 kHz I and V sense sample
rate.
11: 64 kHz to 96 kHz I and V sense sample
rate.
100: 128 kHz to 192 kHz I and V sense
sample rate.
[3] RESERVED
Table 27. Bit Descriptions for AMP_CTRL
Bits
Bit Name
Settings Description
Reset Access
7
SNS_HPF_BP
I/V Sense High Pass Filter On/Off
I/V sense high pass filter on.
I/V sense high pass filter off.
0x0
R/W
0
1
[6:4] SNS_FS
Sense Sample Rate. The sense output sample rate can be set at a lower rate than
the DAC sample rate. When the sense sample rate is less than the DAC sample rate,
sense ADC samples repeat. The number of times the sample repeats is equal to the
ratio of the DAC sample rate/sense sample rate.
0x2
R/W
00 8 kHz to 12 kHz I and V sense sample rate.
01 16 kHz to 24 kHz I and V sense sample rate.
10 32 kHz to 48 kHz I and V sense sample rate.
11 64 kHz to 96 kHz I and V sense sample rate.
100 128 kHz to 192 kHz I and V sense sample rate.
Reserved.
3
2
RESERVED
EDGE
0x0
0x0
R
R/W
Edge Rate Control. This controls the edge speed of the power stage. The low EMI
operation mode reduces the edge speed, lowering EMI and power efficiency
0
1
Normal operation.
Low EMI mode operation.
Rev. A | Page 38 of 60
Data Sheet
SSM3525
Bits
Bit Name
Settings Description
Amplifier Analog Gain Select
+13 dB (6.3x)
+16 dB (8.9x)
Reset Access
[1:0] ANA_GAIN
0x2
R/W
0
1
10 +19 dB (12.6x)
11 +21 dB (16x)
DAC CONTROL REGISTER
Address: 0x06, Reset: 0x32, Name: DAC_CTRL
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
0
[7] DAC_HV (R/W)
[2:0] DAC_FS (R/W)
DAC Hard Volume
0: Soft volume ramping.
1: Hard/immediate volume change.
DAC Sample Rate Selection
000: 8 kHz to 12 kHz sample rate.
001: 16 kHz to 24 kHz sample rate.
010: 32 kHz to 48 kHz sample rate.
011: 64 kHz to 96 kHz sample rate.
100: 128 kHz to 192 kHz sample rate.
101: Reserved.
[6] DAC_MUTE (R/W)
DAC Mute Control
0: DAC unmuted.
1: DAC muted.
110: Reserved.
111: Reserved.
[5] DAC_HPF (R/W)
DAC High Pass Filter Enable
0: DAC high pass filter off.
1: DAC high pass filter on.
[3] DAC_POL (R/W)
DAC Output Polarity control
0: Normal behavior.
1: Invert the DAC output.
[4] DAC_LPM (R/W)
DAC Low Power Mode Enable
0: DAC low power mode off.
1: DAC low power mode on.
Table 28. Bit Descriptions for DAC_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
DAC_HV
DAC Hard Volume
Soft volume ramping.
Hard/immediate volume change.
DAC Mute Control
DAC unmuted.
DAC muted.
DAC High Pass Filter Enable
DAC high pass filter off.
DAC high pass filter on.
DAC Low Power Mode Enable
DAC low power mode off.
DAC low power mode on.
DAC Output Polarity control
Normal behavior.
0x0
R/W
0
1
6
DAC_MUTE
DAC_HPF
DAC_LPM
DAC_POL
DAC_FS
0x0
0x1
0x1
0x0
0x2
R/W
R/W
R/W
R/W
R/W
0
1
5
0
1
4
0
1
3
0
1
Invert the DAC output.
DAC Sample Rate Selection
[2:0]
000 8 kHz to 12 kHz sample rate.
001 16 kHz to 24 kHz sample rate.
010 32 kHz to 48 kHz sample rate.
011 64 kHz to 96 kHz sample rate.
100 128 kHz to 192 kHz sample rate.
101 Reserved.
110 Reserved.
111 Reserved.
Rev. A | Page 39 of 60
SSM3525
Data Sheet
DAC VOLUME CONTROL REGISTER
Address: 0x07, Reset: 0x40, Name: DAC_VOL
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
[7:0] VOL (R/W)
Volume Control
00000000: +24 dB.
00000001: +23.625 dB.
00000010: +23.35 dB.
...
11111101: -70.875 dB.
11111110: -71.25 dB.
11111111:Mute.
Table 29. Bit Descriptions for DAC_VOL
Bits
[7:0]
Bit Name
VOL
Settings
Description
Volume Control
Reset
0x40
Access
R/W
00000000 +24 dB.
00000001 +23.625 dB.
00000010 +23.35 dB.
00000011 +22.875 dB.
00000100 +22.5 dB.
00000101 ...
00111111 +0.375 dB.
01000000 0.
01000001 −0.375 dB.
01000010 ...
11111101 −70.875 dB.
11111110 −71.25 dB.
11111111 Mute.
Rev. A | Page 40 of 60
Data Sheet
SSM3525
AUDIO LIMITER CONTROL 1 REGISTER
Address: 0x08, Reset: 0xA4, Name: LIM_CTRL1
7
6
5
4
3
2
1
0
1
0
1
0
0
1
0
0
[7:6] LIM_RRT (R/W)
[1:0] LIM_EN (R/W)
Audio Limiter Release Rate
00: 3200 ms/dB.
01: 1600 ms/dB.
10: 1200 ms/dB.
11: 800 ms/dB.
Limiter or Mute Mode Enable
00: Limiter and mute mode off.
01: Limiter on.
10: Output mutes if VBAT is below VBAT_INF
11: Limiter on but only engages if VBAT
is below VBAT_INF.
[5:4] LIM_ATR (R/W)
Audio Limiter Attack Rate
00: 120 µs/dB.
01: 60 µs/dB.
10: 30 µs/dB.
[2] VBAT_TRACK (R/W)
Threshold Battery Tracking Enable
0: Limiter attack threshold fixed.
1: Limiter attack threshold varies or
gain reduction with battery voltage.
11: 20 µs/dB.
[3] RESERVED
Table 30. Bit Descriptions for LIM_CTRL1
Bits
[7:6]
Bit Name
LIM_RRT
Settings
Description
Audio Limiter Release Rate
00 3200 ms/dB.
Reset
0x2
Access
R/W
01 1600 ms/dB.
10 1200 ms/dB.
11 800 ms/dB.
[5:4]
LIM_ATR
Audio Limiter Attack Rate
0x2
R/W
00 120 µs/dB.
01 60 µs/dB.
10 30 µs/dB.
11 20 µs/dB.
Reserved.
3
2
RESERVED
VBAT_TRACK
0x0
0x1
R
R/W
Threshold Battery Tracking Enable
0
1
Limiter attack threshold fixed.
Limiter attack threshold varies or gain reduction with battery voltage.
Limiter or Mute Mode Enable
[1:0]
LIM_EN
0x0
R/W
00 Limiter and mute mode off.
01 Limiter on.
10 Output mutes if VBAT is below VBAT_INF.
11 Limiter on but only engages if VBAT is below VBAT_INF.
Rev. A | Page 41 of 60
SSM3525
Data Sheet
AUDIO LIMITER CONTROL 2 REGISTER
Address: 0x09, Reset: 0x51, Name: LIM_CTRL2
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
1
[7:3] LIM_THRES (R/W)
Limiter Attack Threshold
0: 16 V peak.
1: 15.5 V peak.
2: 15 V peak.
...
29: 3 V peak.
30: 2.5 V peak.
31: 2 V peak.
[1:0] SLOPE (R/W)
Slope of threshold reduction/battery
voltage change
00: 1:1 threshold/battery reduction.
01: 2:1 threshold/battery reduction.
10: 3:1 threshold/battery reduction.
11: 4:1 threshold/battery reduction.
[2] RESERVED
Table 31. Bit Descriptions for LIM_CTRL2
Bits
[7:3]
Bit Name
LIM_THRES
Settings
Description
Limiter Attack Threshold
16 VPEAK
15.5 VPEAK
15 VPEAK
14.5 VPEAK
14 VPEAK
13.5 VPEAK
13 VPEAK
12.5 VPEAK
12 VPEAK
11.5 VPEAK
Reset
0xA
Access
R/W
0
1
2
3
4
5
6
7
8
9
.
.
.
.
.
.
.
.
.
.
.
10 11 VPEAK
11 10.5 VPEAK
12 10 VPEAK
13 9.5 VPEAK
14 9.25 VPEAK
15 9 VPEAK
16 8.75 VPEAK
17 8.5 VPEAK
18 8.25 VPEAK
19 8 VPEAK
20 7.5 VPEAK
21 7 VPEAK
22 6.5 VPEAK
23 6 VPEAK
24 5.5 VPEAK
25 5 VPEAK
26 4.5 VPEAK
27 4 VPEAK
28 3.5 VPEAK
29 3 VPEAK
30 2.5 VPEAK
31 2 VPEAK
Reserved.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
2
[1:0]
RESERVED
SLOPE
0x0
0x1
R
R/W
Slope of Threshold Reduction/Battery Voltage Change
00 1:1 threshold/battery reduction.
01 2:1 threshold/battery reduction.
10 3:1 threshold/battery reduction.
11 4:1 threshold/battery reduction.
Rev. A | Page 42 of 60
Data Sheet
SSM3525
AUDIO LIMITER CONTROL 3 REGISTER
Address: 0x0A, Reset: 0x22, Name: LIM_CTRL3
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
0
[7:0] VBAT_INF (R/W)
Audio Limiter Battery Voltage Inflection
Point
Table 32. Bit Descriptions for LIM_CTRL3
Bits
Bit Name Settings Description
Reset Access
[7:0] VBAT_INF
Audio Limiter Battery Voltage Inflection Point. The hexadecimal value corresponds to
the battery or PVDD voltage at which the limiter either activates or starts reducing the
limiter threshold. To convert the hexadecimal value to the corresponding battery
voltage, see the PVDD (VBAT ) Sensing section.
0x22
R/W
VBAT LIMITER CONTROL 1 REGISTER
Address: 0x0B, Reset: 0xA0, Name: VBAT_LIM_CTRL1
7
6
5
4
3
2
1
0
1
0
1
0
0
0
0
0
[7:6] VBAT_LIM_RRT (R/W)
VBAT Limiter Release Rate
00: 3200 ms/dB.
[0] VBAT_LIM_EN (R/W)
VBAT Limiter Enable
0: VBAT limiter disabled.
1: VBAT limiter enabled.
01: 1600 ms/dB.
10: 1200 ms/dB.
11: 800 ms/dB.
[3:1] RESERVED
[5:4] VBAT_LIM_ATR (R/W)
VBAT Limiter Attack Rate
00: 120 µs/dB.
01: 60 µs/dB.
10: 30 µs/dB.
11: 20 µs/dB.
Table 33. Bit Descriptions for VBAT_LIM_CTRL1
Bits
[7:6]
Bit Name
VBAT_LIM_RRT
Settings
Description
VBAT Limiter Release Rate
00 3200 ms/dB.
Reset
0x2
Access
R/W
01 1600 ms/dB.
10 1200 ms/dB.
11 800 ms/dB.
[5:4]
VBAT_LIM_ATR
VBAT Limiter Attack Rate
0x2
R/W
00 120 µs/dB.
01 60 µs/dB.
10 30 µs/dB.
11 20 µs/dB.
Reserved.
[3:1]
0
RESERVED
0x0
0x0
R
VBAT_LIM_EN
VBAT Limiter Enable
R/W
0
1
VBAT limiter disabled.
VBAT limiter enabled.
Rev. A | Page 43 of 60
SSM3525
Data Sheet
VBAT LIMITER CONTROL 2 REGISTER
Address: 0x0C, Reset: 0x22, Name: VBAT_LIM_CTRL2
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
0
[7:0] VBAT_THRES (R/W)
VBAT Limiter Battery Voltage Threshold
Table 34. Bit Descriptions for VBAT_LIM_CTRL2
Bits Bit Name Settings Description
[7:0] VBAT_THRES
Reset Access
VBAT Limiter Battery Voltage Threshold. This is the threshold value in hexadecimal
at which the VBAT limiter starts reducing the gain. To convert the hexadecimal
value to the corresponding battery voltage refer to VBAT sensing section.
0x22
R/W
VBAT LIMITER CONTROL 3 REGISTER
Address: 0x0D, Reset: 0x65, Name: VBAT_LIM_CTRL3
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
[7:4] VBAT_LIM_MAX_ATTN (R/W)
VBAT Limiter Maximum Attenuation
[3:0] VBAT_LIM_HOLD (R/W)
VBAT Limiter Hold-Off Time
0: No hold off.
1: 200 ms.
0: 0.75 dB maximum attenuation.
1: 1.5 dB maximum attenuation.
10: 2.25 dB maximum attenuation.
...
10: 400 ms.
...
1101: 10.5 dB maximum attenuation.
1110: 11.25 dB maximum attenuation.
1111: 12 dB maximum attenuation.
1101: 4000 ms.
1110: 5000 ms.
1111: 6000 ms.
Table 35. Bit Descriptions for VBAT_LIM_CTRL3
Bits Bit Name Settings Description
[7:4] VBAT_LIM_MAX_ATTN
Reset
0x6
Access
R/W
VBAT Limiter Maximum Attenuation
0.75 dB maximum attenuation.
1.5 dB maximum attenuation.
0
1
10 2.25 dB maximum attenuation.
11 3 dB maximum attenuation.
100 3.75 dB maximum attenuation.
101 4.5 dB maximum attenuation.
110 5.25 dB maximum attenuation.
111 6 dB maximum attenuation.
1000 6.75 dB maximum attenuation.
1001 7.5 dB maximum attenuation.
1010 8.25 dB maximum attenuation.
1011 9 dB maximum attenuation.
1100 9.75 dB maximum attenuation.
1101 10.5 dB maximum attenuation.
1110 11.25 dB maximum attenuation.
1111 12 dB maximum attenuation.
VBAT Limiter Hold-Off Time'
[3:0] VBAT_LIM_HOLD
0x5
R/W
0
1
No hold off.
200 ms.
10 400 ms.
11 600 ms.
100 800 ms.
101 1000 ms.
110 1200 ms.
111 1400 ms.
1000 1600 ms.
1001 1800 ms.
Rev. A | Page 44 of 60
Data Sheet
SSM3525
Bits
Bit Name
Settings Description
1010 2000 ms.
1011 2500 ms.
1100 3000 ms.
1101 4000 ms.
1110 5000 ms.
1111 6000 ms.
Reset
Access
LIMITER LINK CONTROL REGISTER
Address: 0x0E, Reset: 0x00, Name: LIM_LINK
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] RESERVED
[0] LIM_LINK1 (R/W)
Limiter Gain Link with AGC_GAIN1
Input
0: Limiter gain not linked.
1: Limiter gain linked.
[3] LIM_LINK4 (R/W)
Limiter Gain Link with AGC_GAIN4
Input
0: Limiter gain not linked.
1: Limiter gain linked.
[1] LIM_LINK2 (R/W)
Limiter Gain Link with AGC_GAIN2
Input
0: Limiter gain not linked.
1: Limiter gain linked.
[2] LIM_LINK3 (R/W)
Limiter Gain Link with AGC_GAIN3
Input
0: Limiter gain not linked.
1: Limiter gain linked.
Table 36. Bit Descriptions for LIM_LINK
Bits
[7:4]
3
Bit Name
RESERVED
LIM_LINK4
Settings
Description
Reserved.
Limiter Gain Link with AGC_GAIN4 Input
Limiter gain not linked.
Limiter gain linked.
Reset
0x0
0x0
Access
R
R/W
0
1
2
1
0
LIM_LINK3
LIM_LINK2
LIM_LINK1
Limiter Gain Link with AGC_GAIN3 Input
Limiter gain not linked.
Limiter gain linked.
Limiter Gain Link with AGC_GAIN2 Input
Limiter gain not linked.
Limiter gain linked.
Limiter Gain Link with AGC_GAIN1 Input
Limiter gain not linked.
Limiter gain linked.
0x0
0x0
0x0
R/W
R/W
R/W
0
1
0
1
0
1
DAC CLIP POINT CONTROL REGISTER
Address: 0x0F, Reset: 0xFF, Name: DAC_CLIP
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
[7:0] DAC_CLIP (R/W)
DAC High Frequency Clip Value
0xFF: Clip to 256/256 or 0 dB.
0xFE: Clip to 255/256 or −0.034 dB.
0xFD: Clip to 254/256 or −0.068 dB.
0xFC: ...
0x00: Clip to 1/256 or −48.16 dB.
Table 37. Bit Descriptions for DAC_CLIP
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DAC_CLIP
DAC High Frequency Clip Value
0xFF
R/W
0xFF Clip to 256/256 or 0 dB.
0xFE Clip to 255/256 or −0.034 dB.
0xFD Clip to 254/256 or −0.068 dB.
0xFC ...
0x00 Clip to 1/256 or −48.16 dB.
Rev. A | Page 45 of 60
SSM3525
Data Sheet
FAULT CONTROL REGISTER
Address: 0x10, Reset: 0x18, Name: FAULT_CTRL
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
[7:6] OTW_GAIN (R/W)
[0] ARCV_OC (R/W)
Overtemperature Warning Gain Reduction
00: No gain reduction in thermal warning.
Over Current Auto Fault Recovery
Control
01: 1.5 dB gain reduction in thermal warning.
10: 3 dB gain reduction in thermal warning.
11: 5.625 dB gain reduction in thermal
warning.
0: Auto fault recovery for over current
fault.
1: Manual fault recovery for over current
fault.
[5] MRCV (W1)
[1] ARCV_OT (R/W)
Manual Fault Recovery
0: Normal operation.
Overtemperature Auto Fault Recovery
Control
1: Writing of 1 causes a manual fault
recovery attempt when ARCV_x bits
are set to 1.
0: Auto fault recovery for over temperature
fault.
1: Manual fault recovery for over temperature
fault.
[4:3] MAX_AR (R/W)
Maximum Fault Recovery Attempts
00: 1 auto recovery attempt.
01: 3 auto recovery attempts.
10: 7 auto recovery attempts.
11: Unlimited auto recovery attempts.
[2] ARCV_UV (R/W)
Undervoltage Auto Fault Recovery
Control
0: Auto fault recovery for under voltage
fault.
1: Manual fault recovery for under voltage
fault.
Table 38. Bit Descriptions for FAULT_CTRL
Bits Bit Name Settings Description
[7:6] OTW_GAIN
Reset
0x0
Access
R/W
Overtemperature Warning Gain Reduction
00 No gain reduction in thermal warning.
01 1.5 dB gain reduction in thermal warning.
10 3 dB gain reduction in thermal warning.
11 5.625 dB gain reduction in thermal warning.
Manual Fault Recovery
5
MRCV
0x0
0x3
W1
0
1
Normal operation.
Writing 1 causes a manual fault recovery attempt when ARCV_x bits are set to 1.
[4:3] MAX_AR
Maximum Fault recovery Attempts. The maximum auto recovery register
determines how many attempts at auto recovery are performed.
R/W
00 1 auto recovery attempt.
01 3 auto recovery attempts.
10 7 auto recovery attempts.
11 Unlimited auto recovery attempts.
Undervoltage Auto Fault Recovery Control
2
1
0
ARCV_UV
ARCV_OT
ARCV_OC
0x0
0x0
0x0
R/W
R/W
R/W
0
1
Auto fault recovery for undervoltage fault.
Manual fault recovery for undervoltage fault.
Overtemperature Auto Fault Recovery Control
Auto fault recovery for overtemperature fault.
Manual fault recovery for overtemperature fault.
Over Current Auto Fault Recovery Control
Auto fault recovery for over current fault.
Manual fault recovery for over current fault.
0
1
0
1
Rev. A | Page 46 of 60
Data Sheet
SSM3525
CHIP STATUS REGISTER
Address: 0x11, Reset: 0x00, Name: STATUS
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] UVLO_VREG (R)
[0] BAT_WARN (R)
Regulator Undervoltage Fault Status
0: Normal operation.
1: Voltage regulator fault condition.
Battery Voltage Warning
0: Battery voltage above VBAT_INF.
1: Battery voltage at or below VBAT_INF.
[6] UVLO_PVDD (R)
[1] OTW (R)
PVDD Undervoltage Fault Condition
Overtemperature Warning Status
0: Normal operation.
1: Over temperature warning condition.
[5] LIM_EG (R)
Limiter/Gain Reduction Engaged
0: Normal operation.
[2] OTF (R)
1: Limiter or gain reduction has reduced
gain.
Overtemperature Fault Status
0: Normal operation.
1: Over temperature fault condition.
[4] CLIP (R)
Clip Detector
[3] AMP_OC (R)
0: Normal operation.
1: DAC clipping detected.
Amplifier Over Current Fault Status
0: Normal operation.
1: Amplifier over current fault condition.
Table 39. Bit Descriptions for STATUS
Bits
Bit Name
Settings
Description
Reset
Access
7
UVLO_VREG
Regulator Undervoltage Fault Status
Normal operation.
Voltage regulator fault condition.
PVDD Undervoltage Fault Condition
Limiter/Gain Reduction Engaged
Normal operation.
Limiter or gain reduction has reduced gain.
Clip Detector
Normal operation.
DAC clipping detected.
Amplifier Over Current Fault Status
Normal operation.
Amplifier over current fault condition.
Overtemperature Fault Status
Normal operation.
Overtemperature fault condition.
Overtemperature Warning Status
Normal operation.
0x0
R
0
1
6
5
UVLO_PVDD
LIM_EG
0x0
0x0
R
R
0
1
4
3
2
1
0
CLIP
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
0
1
AMP_OC
OTF
0
1
0
1
OTW
0
1
Overtemperature warning condition.
Battery Voltage Warning
BAT_WARN
0
1
Battery voltage above VBAT_INF.
Battery voltage at or below VBAT_INF.
TEMPERATURE SENSOR VALUE REGISTER
Address: 0x12, Reset: 0x00, Name: TEMP
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] TEMP (R)
Temperature Sensor Readout
Table 40. Bit Descriptions for TEMP
Bits
[7:0] TEMP
Bit Name Settings Description
Reset
0x0
Access
R
Temperature Sensor Readout. To calculate actual temperature in degrees Celsius,
convert the TEMP hexadecimal value to decimal and then subtract 60.
Rev. A | Page 47 of 60
SSM3525
Data Sheet
PVDD/VBAT ADC VALUE REGISTER
Address: 0x13, Reset: 0x00, Name: VBAT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VBAT (R)
8-Bit Unsigned Battery Voltage Readback
Table 41. Bit Descriptions for VBAT
Bits
Bit Name Settings Description
Reset
Access
[7:0] VBAT
8-Bit Unsigned Battery Voltage Readback. To calculate this value in volts. Convert the
hexadecimal value to decimal, and then voltage = 4 + 14 × decimal value/255.
0x0
R
MASTER AND BLOCK POWER CONTROL REGISTER
Address: 0x20, Reset: 0x05, Name: PWR_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
1
[7:6] RESERVED
[0] SPWDN (R/W)
Master Software Power-Down
0: Normal operation.
1: Software master power-down.
[5] VSNS_PWDN (R/W)
Voltage Sense Power-Down
0: Voltage sense powered on.
1: Voltage sense powered off.
[1] IOVDD_SEL (R/W)
IOVDD Voltage Selection
0: IOVDD is 1.8V.
[4] ISNS_PWDN (R/W)
Current Sense Power-Down
0: Current sense powered on.
1: Current sense powered off.
1: IOVDD is 1.2V.
[2] TEMP_PWDN (R/W)
Temperature Sensor Power-Down
0: Temperature sensor on.
[3] RESERVED
1: Temperature sensor powered down.
Table 42. Bit Descriptions for PWR_CTRL
Bits Bit Name Settings Description
[7:6] RESERVED Reserved.
Reset
0x0
Access
R
5
VSNS_PWDN
Voltage Sense Power-Down
Voltage sense powered on.
Voltage sense powered off.
Current Sense Power-Down
Current sense powered on.
Current sense powered off.
Reserved.
Temperature Sensor Power-Down
Temperature sensor on.
Temperature sensor powered down.
IOVDD Voltage Selection
IOVDD is 1.8 V.
0x0
R/W
0
1
4
ISNS_PWDN
0x0
R/W
0
1
3
2
RESERVED
TEMP_PWDN
0x0
0x1
R
R/W
0
1
1
0
IOVDD_SEL
SPWDN
0x0
0x1
R/W
R/W
0
1
IOVDD is 1.2 V.
Master Software Power-Down. Software power-down puts all blocks except the
I2C interface in a low power state.
0
1
Normal operation.
Software master power-down.
Rev. A | Page 48 of 60
Data Sheet
SSM3525
PDM CONTROL REGISTER
Address: 0x21, Reset: 0x00, Name: PDM_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] RESERVED
[0] PDM_MODE (R/W)
PDM Input and Output Mode
0: Normal I2S/TDM operation.
1: PDM used for input and output.
[4] PDM_FS (R/W)
PDM Sample Rate Selection
0: 4 MHz to 6 MHz clock in PDM mode.
1: 2 MHz to 3 MHz clock in PDM mode.
[3:1] RESERVED
Table 43. Bit Descriptions for PDM_CTRL
Bits
[7:5]
4
Bit Name
RESERVED
PDM_FS
Settings
Description
Reserved.
Reset
0x0
0x0
Access
R
PDM Sample Rate Selection
R/W
0
1
4 MHz to 6 MHz clock in PDM mode.
2 MHz to 3 MHz clock in PDM mode.
Reserved.
[3:1]
0
RESERVED
PDM_MODE
0x0
0x0
R
R/W
PDM Input and Output Mode
Normal I2S/TDM operation.
PDM used for input and output.
0
1
SERIAL INTERFACE CONTROL 1 REGISTER
Address: 0x22, Reset: 0x21, Name: SAI_CTRL1
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
1
[7] SAI_DRV (R/W)
[0] SAI_MODE (R/W)
Drive Control for Unused BCLK Cycles
0: Unused BCLK cycles on SDATAO
are not driven (high-Z)
Serial Interface Mode Selection
0: Stereo modes (I2S or left justified)
1: TDM/PCM modes.
1: Unused BCLK cycles on SDATAO
are driven low.
[1] SDATA_FMT (R/W)
Serial Data Format
[6:4] TDM_BCLKS (R/W)
Number of Bit Clocks per Chip in
TDM Mode
000: 16 BCLKs per Chip in TDM.
001: 24 BCLKs per Chip in TDM.
010: 32 BCLKs per Chip in TDM.
011: 48 BCLKs per Chip in TDM.
100: 64 BCLKs per Chip in TDM.
0: I2S/delay by one bit clock from FSYNC
edge.
1: Left Justified/no delay from FSYNC
edge.
[2] FSYNC_MODE (R/W)
FSYNC Mode Control
0: Low FSYNC is left channel in stereo
modes or pulsed FSYNC mode in
TDM modes.
[3] BCLK_POL (R/W)
BCLK Polarity Control
0: Rising edge of BCLK registers SDATA.
1: Falling edge of BCLK registers SDATA.
1: High FSYNC is left channel in stereo
modes or 50% FSYNC mode in TDM
modes.
Table 44. Bit Descriptions for SAI_CTRL1
Bits
Bit Name
Settings Description
Reset Access
7
SAI_DRV
Drive Control for Unused BCLK Cycles
0x0
R/W
0
1
Unused BCLK cycles on SDATAO are not driven (high-Z).
Unused BCLK cycles on SDATAO are driven low.
[6:4] TDM_BCLKS
Number of Bit Clocks per Chip in TDM Mode. Any number of bit clock cycles per
FSYNC can be used in stereo modes (I2S or left justified) or in TDM mode with only
one chip. When in TDM mode and having multiple chips on the TDM bus, the
number of bit clocks per chip must be defined.
0x2
R/W
000 16 BCLKs per chip in TDM.
001 24 BCLKs per chip in TDM.
010 32 BCLKs per chip in TDM.
011 48 BCLKs per chip in TDM.
100 64 BCLKs per chip in TDM.
BCLK Polarity Control
3
BCLK_POL
0x0
R/W
0
1
Rising edge of BCLK registers SDATA.
Falling edge of BCLK registers SDATA.
Rev. A | Page 49 of 60
SSM3525
Data Sheet
Bits
2
Bit Name
Settings Description
FSYNC Mode Control
Reset Access
FSYNC_MODE
SDATA_FMT
SAI_MODE
0x0
0x0
0x1
R/W
R/W
R/W
0
1
Low FSYNC is left channel in stereo modes or pulsed FSYNC mode in TDM modes.
High FSYNC is left channel in stereo modes or 50% FSYNC mode in TDM modes.
Serial Data Format
1
0
0
1
I2S/delay by one bit clock from FSYNC edge.
Left Justified/no delay from FSYNC edge.
Serial Interface Mode Selection
0
1
Stereo modes (I2S or left justified)
TDM/PCM modes.
SERIAL INTERFACE CONTROL 2 REGISTER
Address: 0x23, Reset: 0x00, Name: SAI_CTRL2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] RESERVED
[4:0] TDM_SLOT (R/W)
TDM Slot Selection
0000: Chip Slot 1 used.
0001: Chip Slot 2 used.
0010: Chip Slot 3 used.
...
11101: Chip Slot 30 used.
11110: Chip Slot 31 used.
11111: Chip Slot 32 used.
Table 45. Bit Descriptions for SAI_CTRL2
Bits
[7:5]
[4:0]
Bit Name
RESERVED
TDM_SLOT
Settings
Description
Reserved.
Reset
0x0
0x0
Access
R
TDM Slot Selection
R/W
0000 Chip Slot 1 used.
0001 Chip Slot 2 used.
0010 Chip Slot 3 used.
0011 Chip Slot 4 used.
0100 Chip Slot 5 used.
0101 Chip Slot 6 used.
0110 Chip Slot 7 used.
0111 Chip Slot 8 used.
1000 Chip Slot 9 used.
1001 Chip Slot 10 used.
1010 Chip Slot 11 used.
1011 Chip Slot 12 used.
1100 Chip Slot 13 used.
1101 Chip Slot 14 used.
1110 Chip Slot 15 used.
1111 Chip Slot 16 used.
10000 Chip Slot 17 used.
10001 Chip Slot 18 used.
10010 Chip Slot 19 used.
10011 Chip Slot 20 used.
10100 Chip Slot 21 used.
10101 Chip Slot 22 used.
10110 Chip Slot 23 used.
10111 Chip Slot 24 used.
11000 Chip Slot 25 used.
11001 Chip Slot 26 used.
11010 Chip Slot 27 used.
Rev. A | Page 50 of 60
Data Sheet
SSM3525
Bits
Bit Name
Settings
Description
Reset
Access
11011 Chip Slot 28 used.
11100 Chip Slot 29 used.
11101 Chip Slot 30 used.
11110 Chip Slot 31 used.
11111 Chip Slot 32 used.
SERIAL INTERFACE PLACEMENT CONTROL 1 REGISTER
Address: 0x24, Reset: 0x01, Name: SAI_PLACE1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:6] RESERVED
[3:0] P1_SNS (R/W)
Placement 1 or L1 Control for Sense
Output
1000: Blank 8-bits.
0100: Alternating 16-bit voltage and current.
0000: 16-bit voltage output.
...
0101: 8-bit status output.
0010: 8-bit battery voltage output unsigned.
0011: 8-bit AGC_GAIN output.
[5:4] P1_DAC (R/W)
Placement 1 or L1 Control for DAC
Input
00: 24-Bit DAC input.
01: 16-Bit DAC input.
10: Unused 8-bits.
11: Unused 8-bits.
Table 46. Bit Descriptions for SAI_PLACE1
Bits
[7:6]
[5:4]
Bit Name
RESERVED
P1_DAC
Settings
Description
Reserved.
Reset
0x0
Access
R
Placement 1 or L1 Control for DAC Input
0x0
R/W
00 24-bit DAC input.
01 16-bit DAC input.
10 Unused 8-bits.
11 Unused 8-bits.
[3:0]
P1_SNS
Placement 1 or L1 Control for Sense Output
1000 Blank 8-bits.
0x1
R/W
0100 Alternating 16-bit voltage and current.
0000 16-bit voltage output.
0001 16-bit current output.
0110 8-bit V/I marker and status.
0111 8-bit temperature output.
0101 8-bit status output.
0010 8-bit battery voltage output unsigned.
0011 8-bit AGC_GAIN output.
Rev. A | Page 51 of 60
SSM3525
Data Sheet
SERIAL INTERFACE PLACEMENT CONTROL 2 REGISTER
Address: 0x25, Reset: 0x21, Name: SAI_PLACE2
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
1
[7:6] RESERVED
[3:0] P2_SNS (R/W)
Placement 2 or R1 Control for Sense
Output
0000: 16-bit voltage output.
0001: 16-bit current output.
0010: 8-bit battery voltage output unsigned.
...
0110: 8-bit V/I marker and status.
0111: 8-bit temperature output.
1000: Blank 8-bits.
[5:4] P2_DAC (R/W)
Placement 2 or R1 Control for DAC
Input
00: 24-bit DAC input.
01: 16-bit DAC input.
10: Unused 8-bits.
11: Unused 8-bits.
Table 47. Bit Descriptions for SAI_PLACE2
Bits
[7:6]
[5:4]
Bit Name
RESERVED
P2_DAC
Settings
Description
Reserved.
Placement 2 or R1 Control for DAC Input
Reset
0x0
0x2
Access
R
R/W
00 24-bit DAC input.
01 16-bit DAC input.
10 Unused 8-bits.
11 Unused 8-bits.
[3:0]
P2_SNS
Placement 2 or R1 Control for Sense Output
0000 16-bit voltage output.
0001 16-bit current output.
0010 8-bit battery voltage output unsigned.
0011 8-bit AGC_GAIN output.
0100 Alternating 16-bit voltage and current.
0101 8-bit status output.
0x1
R/W
0110 8-bit V/I marker and status.
0111 8-bit temperature output.
1000 Blank 8-bits.
SERIAL INTERFACE PLACEMENT CONTROL 3 REGISTER
Address: 0x26, Reset: 0x21, Name: SAI_PLACE3
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
1
[7:6] RESERVED
[3:0] P3_SNS (R/W)
Placement 3 or L2 Control for Sense
Output
0000: 16-bit voltage output.
0001: 16-bit current output.
0010: 8-bit battery voltage output unsigned.
...
0110: 8-bit V/I marker and status.
0111: 8-bit temperature output.
1000: Blank 8-bits.
[5:4] P3_DAC (R/W)
Placement 3 or L2 Control for DAC
Input
00: 24-bit DAC input.
01: 16-bit DAC input.
10: Unused 8-bits.
11: Unused 8-bits.
Table 48. Bit Descriptions for SAI_PLACE3
Bits
[7:6]
[5:4]
Bit Name
RESERVED
P3_DAC
Settings
Description
Reserved.
Placement 3 or L2 Control for DAC Input
Reset
0x0
0x2
Access
R
R/W
00 24-bit DAC input.
01 16-bit DAC input.
10 Unused 8-bits.
11 Unused 8-bits.
Rev. A | Page 52 of 60
Data Sheet
SSM3525
Bits
Bit Name
Settings
Description
Reset
Access
[3:0]
P3_SNS
Placement 3 or L2 Control for Sense Output
0x1
R/W
0000 16-bit voltage output.
0001 16-bit current output.
0010 8-bit battery voltage output unsigned.
0011 8-bit AGC_GAIN output.
0100 Alternating 16-bit voltage and current.
0101 8-bit status output.
0110 8-bit V/I marker and status.
0111 8-bit temperature output.
1000 Blank 8-bits.
SERIAL INTERFACE PLACEMENT CONTROL 4 REGISTER
Address: 0x27, Reset: 0x21, Name: SAI_PLACE4
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
1
[7:6] RESERVED
[3:0] P4_SNS (R/W)
Placement 4 or R2 Control for Sense
Output
0000: 16-bit voltage output.
0001: 16-bit current output.
0010: 8-bit battery voltage output unsigned.
...
0110: 8-bit V/I marker and status.
0111: 8-bit temperature output.
1000: Blank 8-bits.
[5:4] P4_DAC (R/W)
Placement 4 or R2 Control for DAC
Input
00: 24-bit DAC input.
01: 16-bit DAC input.
10: Unused 8-bits.
11: Unused 8-bits.
Table 49. Bit Descriptions for SAI_PLACE4
Bits
[7:6]
[5:4]
Bit Name
RESERVED
P4_DAC
Settings
Description
Reserved.
Placement 4 or R2 Control for DAC Input
Reset
0x0
0x2
Access
R
R/W
00 24-bit DAC input.
01 16-bit DAC input.
10 Unused 8-bits.
11 Unused 8-bits.
[3:0]
P4_SNS
Placement 4 or R2 Control for Sense Output
0000 16-bit voltage output.
0001 16-bit current output.
0010 8-bit battery voltage output unsigned.
0011 8-bit AGC_GAIN output.
0100 Alternating 16-bit voltage and current.
0101 8-bit status output.
0x1
R/W
0110 8-bit V/I marker and status.
0111 8-bit temperature output.
1000 Blank 8-bits.
Rev. A | Page 53 of 60
SSM3525
Data Sheet
SERIAL INTERFACE PLACEMENT CONTROL 5 REGISTER
Address: 0x28, Reset: 0x01, Name: SAI_PLACE5
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:4] RESERVED
[3:0] P5_SNS (R/W)
Placement 5 or L3 Control for Sense
Output
0000: 16-bit voltage output.
0001: 16-bit current output.
0010: 8-bit battery voltage output unsigned.
...
0110: 8-bit V/I marker and status.
0111: 8-bit temperature output.
1000: Blank 8-bits.
Table 50. Bit Descriptions for SAI_PLACE5
Bits
[7:4]
[3:0]
Bit Name
RESERVED
P5_SNS
Settings
Description
Reserved.
Placement 5 or L3 Control for Sense Output
0000 16-bit voltage output.
Reset
0x0
0x1
Access
R
R/W
0001 16-bit current output.
0010 8-bit battery voltage output unsigned.
0011 8-bit AGC_GAIN output.
0100 Alternating 16-bit voltage and current.
0101 8-bit status output.
0110 8-bit V/I marker and status.
0111 8-bit temperature output.
1000 Blank 8-bits.
SERIAL INTERFACE PLACEMENT CONTROL 6 REGISTER
Address: 0x29, Reset: 0x01, Name: SAI_PLACE6
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:4] RESERVED
[3:0] P6_SNS (R/W)
Placement 6 or R3 Control for Sense
Output
0000: 16-bit voltage output.
0001: 16-bit current output.
0010: 8-bit battery voltage output unsigned.
...
0110: 8-bit V/I marker and status.
0111: 8-bit temperature output.
1000: Blank 8-bits.
Table 51. Bit Descriptions for SAI_PLACE6
Bits
[7:4]
[3:0]
Bit Name
RESERVED
P6_SNS
Settings
Description
Reserved.
Placement 6 or R3 Control for Sense Output
0000 16-bit voltage output.
Reset
0x0
0x1
Access
R
R/W
0001 16-bit current output.
0010 8-bit battery voltage output unsigned.
0011 8-bit AGC_GAIN output.
0100 Alternating 16-bit voltage and current.
0101 8-bit status output.
0110 8-bit V/I marker and status.
0111 8-bit temperature output.
1000 Blank 8-bits.
Rev. A | Page 54 of 60
Data Sheet
SSM3525
AGC_GAIN1 INPUT DATA PLACEMENT REGISTER
Address: 0x2A, Reset: 0x00, Name: AGC_PLACE1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] AGC_GAIN1_PLACE (R/W)
[4:0] AGC_GAIN1_SLOT (R/W)
Placement Within Slot for AGC_GAIN1
Data
Slot Used for Limiter Linking AGC_GAIN1
0: AGC_GAIN data placed in Slot 1.
1: AGC_GAIN data placed in Slot 2.
10: AGC_GAIN data placed in Slot 3.
...
1101: AGC_GAIN data placed in Slot 14.
1110: AGC_GAIN data placed in Slot 15.
1111: AGC_GAIN data placed in Slot 16.
0: AGC_GAIN1 data starts at Bit 0 within
assigned slot.
1: AGC_GAIN1 data starts at Bit 8 within
assigned slot.
10: AGC_GAIN1 data starts at Bit 16 within
assigned slot.
11: AGC_GAIN1 data starts at Bit 24 within
assigned slot.
100: AGC_GAIN1 data starts at Bit 32 within
assigned slot.
101: AGC_GAIN1 data starts at Bit 40 within
assigned slot.
110: AGC_GAIN1 data starts at Bit 48 within
assigned slot.
111: AGC_GAIN1 data starts at Bit 54 within
assigned slot.
Table 52. Bit Descriptions for AGC_PLACE1
Bits
[7:5]
Bit Name
AGC_GAIN1_PLACE
Settings
Description
Placement Within Slot for AGC_GAIN1 Data
Reset
0x0
Access
R/W
0
1
AGC_GAIN1 data starts at Bit 0 within assigned slot.
AGC_GAIN1 data starts at Bit 8 within assigned slot.
10 AGC_GAIN1 data starts at Bit 16 within assigned slot.
11 AGC_GAIN1 data starts at Bit 24 within assigned slot.
100 AGC_GAIN1 data starts at Bit 32 within assigned slot.
101 AGC_GAIN1 data starts at Bit 40 within assigned slot.
110 AGC_GAIN1 data starts at Bit 48 within assigned slot.
111 AGC_GAIN1 data starts at Bit 54 within assigned slot.
Slot Used for Limiter Linking AGC_GAIN1
[4:0]
AGC_GAIN1_SLOT
0x0
R/W
0
1
AGC_GAIN data placed in Slot 1.
AGC_GAIN data placed in Slot 2.
10 AGC_GAIN data placed in Slot 3.
11 AGC_GAIN data placed in Slot 4.
100 AGC_GAIN data placed in Slot 5.
101 AGC_GAIN data placed in Slot 6.
110 AGC_GAIN data placed in Slot 7.
111 AGC_GAIN data placed in Slot 8.
1000 AGC_GAIN data placed in Slot 9.
1001 AGC_GAIN data placed in Slot 10.
1010 AGC_GAIN data placed in Slot 11.
1011 AGC_GAIN data placed in Slot 12.
1100 AGC_GAIN data placed in Slot 13.
1101 AGC_GAIN data placed in Slot 14.
1110 AGC_GAIN data placed in Slot 15.
1111 AGC_GAIN data placed in Slot 16.
Rev. A | Page 55 of 60
SSM3525
Data Sheet
AGC_GAIN2 INPUT DATA PLACEMENT REGISTER
Address: 0x2B, Reset: 0x00, Name: AGC_PLACE2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] AGC_GAIN2_PLACE (R/W)
[4:0] AGC_GAIN2_SLOT (R/W)
Placement Within Slot for AGC_GAIN2
Data
Slot Used for Limiter Linking AGC_GAIN2
0: AGC_GAIN data placed in Slot 1.
1: AGC_GAIN data placed in Slot 2.
10: AGC_GAIN data placed in Slot 3.
...
1101: AGC_GAIN data placed in Slot 14.
1110: AGC_GAIN data placed in Slot 15.
1111: AGC_GAIN data placed in Slot 16.
0: AGC_GAIN2 data starts at Bit 0 within
assigned slot.
1: AGC_GAIN2 data starts at Bit 8 within
assigned slot.
10: AGC_GAIN2 data starts at Bit 16 within
assigned slot.
11: AGC_GAIN2 data starts at Bit 24 within
assigned slot.
100: AGC_GAIN2 data starts at Bit 32 within
assigned slot.
101: AGC_GAIN2 data starts at Bit 40 within
assigned slot.
110: AGC_GAIN2 data starts at Bit 48 within
assigned slot.
111: AGC_GAIN2 data starts at Bit 54 within
assigned slot.
Table 53. Bit Descriptions for AGC_PLACE2
Bits
Bit Name
Settings
Description
Reset
Access
[7:5]
AGC_GAIN2_PLACE
Placement Within Slot for AGC_GAIN2 Data
0x0
R/W
0
1
AGC_GAIN2 data starts at Bit 0 within assigned slot.
AGC_GAIN2 data starts at Bit 8 within assigned slot.
10 AGC_GAIN2 data starts at Bit 16 within assigned slot.
11 AGC_GAIN2 data starts at Bit 24 within assigned slot.
100 AGC_GAIN2 data starts at Bit 32 within assigned slot.
101 AGC_GAIN2 data starts at Bit 40 within assigned slot.
110 AGC_GAIN2 data starts at Bit 48 within assigned slot.
111 AGC_GAIN2 data starts at Bit 54 within assigned slot.
Slot Used for Limiter Linking AGC_GAIN2
[4:0]
AGC_GAIN2_SLOT
0x0
R/W
0
1
AGC_GAIN data placed in Slot 1.
AGC_GAIN data placed in Slot 2.
10 AGC_GAIN data placed in Slot 3.
11 AGC_GAIN data placed in Slot 4.
100 AGC_GAIN data placed in Slot 5.
101 AGC_GAIN data placed in Slot 6.
110 AGC_GAIN data placed in Slot 7.
111 AGC_GAIN data placed in Slot 8.
1000 AGC_GAIN data placed in Slot 9.
1001 AGC_GAIN data placed in Slot 10.
1010 AGC_GAIN data placed in Slot 11.
1011 AGC_GAIN data placed in Slot 12.
1100 AGC_GAIN data placed in Slot 13.
1101 AGC_GAIN data placed in Slot 14.
1110 AGC_GAIN data placed in Slot 15.
1111 AGC_GAIN data placed in Slot 16.
Rev. A | Page 56 of 60
Data Sheet
SSM3525
AGC_GAIN3 INPUT DATA PLACEMENT REGISTER
Address: 0x2C, Reset: 0x00, Name: AGC_PLACE3
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] AGC_GAIN3_PLACE (R/W)
[4:0] AGC_GAIN3_SLOT (R/W)
Placement Within Slot for AGC_GAIN3
Data
Slot Used for Limiter Linking AGC_GAIN3
0: AGC_GAIN data placed in Slot 1.
1: AGC_GAIN data placed in Slot 2.
10: AGC_GAIN data placed in Slot 3.
...
1101: AGC_GAIN data placed in Slot 14.
1110: AGC_GAIN data placed in Slot 15.
1111: AGC_GAIN data placed in Slot 16.
0: AGC_GAIN3 data starts at Bit 0 within
assigned Slot.
1: AGC_GAIN3 data starts at Bit 8 within
assigned Slot.
10: AGC_GAIN3 data starts at Bit 16 within
assigned Slot.
11: AGC_GAIN3 data starts at Bit 24 within
assigned Slot.
100: AGC_GAIN3 data starts at Bit 32 within
assigned Slot.
101: AGC_GAIN3 data starts at Bit 40 within
assigned Slot.
110: AGC_GAIN3 data starts at Bit 48 within
assigned Slot.
111: AGC_GAIN3 data starts at Bit 54 within
assigned Slot.
Table 54. Bit Descriptions for AGC_PLACE3
Bits
[7:5]
Bit Name
AGC_GAIN3_PLACE
Settings
Description
Placement within slot for AGC_GAIN3 data
Reset
0x0
Access
R/W
0
1
AGC_GAIN3 data starts at Bit 0 within assigned slot.
AGC_GAIN3 data starts at Bit 8 within assigned slot.
10 AGC_GAIN3 data starts at Bit 16 within assigned slot.
11 AGC_GAIN3 data starts at Bit 24 within assigned slot.
100 AGC_GAIN3 data starts at Bit 32 within assigned slot.
101 AGC_GAIN3 data starts at Bit 40 within assigned slot.
110 AGC_GAIN3 data starts at Bit 48 within assigned slot.
111 AGC_GAIN3 data starts at Bit 54 within assigned slot.
Slot Used for Limiter Linking AGC_GAIN3
[4:0]
AGC_GAIN3_SLOT
0x0
R/W
0
1
AGC_GAIN data placed in Slot 1.
AGC_GAIN data placed in Slot 2.
10 AGC_GAIN data placed in Slot 3.
11 AGC_GAIN data placed in Slot 4.
100 AGC_GAIN data placed in Slot 5.
101 AGC_GAIN data placed in Slot 6.
110 AGC_GAIN data placed in Slot 7.
111 AGC_GAIN data placed in Slot 8.
1000 AGC_GAIN data placed in Slot 9.
1001 AGC_GAIN data placed in Slot 10.
1010 AGC_GAIN data placed in Slot 11.
1011 AGC_GAIN data placed in Slot 12.
1100 AGC_GAIN data placed in Slot 13.
1101 AGC_GAIN data placed in Slot 14.
1110 AGC_GAIN data placed in Slot 15.
1111 AGC_GAIN data placed in Slot 16.
Rev. A | Page 57 of 60
SSM3525
Data Sheet
AGC_GAIN4 INPUT DATA PLACEMENT REGISTER
Address: 0x2D, Reset: 0x00, Name: AGC_PLACE4
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] AGC_GAIN4_PLACE (R/W)
[4:0] AGC_GAIN4_SLOT (R/W)
Placement Within Slot for AGC_GAIN4
Data
Slot Used for Limiter Linking AGC_GAIN4
0: AGC_GAIN data placed in Slot 1.
1: AGC_GAIN data placed in Slot 2.
10: AGC_GAIN data placed in Slot 3.
...
1101: AGC_GAIN data placed in Slot 14.
1110: AGC_GAIN data placed in Slot 15.
1111: AGC_GAIN data placed in Slot 16.
0: AGC_GAIN4 data starts at Bit 0 within
assigned slot.
1: AGC_GAIN4 data starts at Bit 8 within
assigned slot.
10: AGC_GAIN4 data starts at Bit 16 within
assigned slot.
11: AGC_GAIN4 data starts at Bit 24 within
assigned slot.
100: AGC_GAIN4 data starts at Bit 32 within
assigned slot.
101: AGC_GAIN4 data starts at Bit 40
within assigned slot.
110: AGC_GAIN4 data starts at Bit 48 within
assigned slot.
111: AGC_GAIN4 data starts at Bit 54 within
assigned slot.
Table 55. Bit Descriptions for AGC_PLACE4
Bits
Bit Name
Settings
Description
Reset
Access
[7:5]
AGC_GAIN4_PLACE
Placement Within Slot for AGC_GAIN4 Data
0x0
R/W
0
1
AGC_GAIN4 data starts at Bit 0 within assigned slot.
AGC_GAIN4 data starts at Bit 8 within assigned slot.
10 AGC_GAIN4 data starts at Bit 16 within assigned slot.
11 AGC_GAIN4 data starts at Bit 24 within assigned slot.
100 AGC_GAIN4 data starts at Bit 32 within assigned slot.
101 AGC_GAIN4 data starts at Bit 40 within assigned slot.
110 AGC_GAIN4 data starts at Bit 48 within assigned slot.
111 AGC_GAIN4 data starts at Bit 54 within assigned slot.
Slot Used for Limiter Linking AGC_GAIN4
[4:0]
AGC_GAIN4_SLOT
0x0
R/W
0
1
AGC_GAIN data placed in Slot 1.
AGC_GAIN data placed in Slot 2.
10 AGC_GAIN data placed in Slot 3.
11 AGC_GAIN data placed in Slot 4.
100 AGC_GAIN data placed in Slot 5.
101 AGC_GAIN data placed in Slot 6.
110 AGC_GAIN data placed in Slot 7.
111 AGC_GAIN data placed in Slot 8.
1000 AGC_GAIN data placed in Slot 9.
1001 AGC_GAIN data placed in Slot 10.
1010 AGC_GAIN data placed in Slot 11.
1011 AGC_GAIN data placed in Slot 12.
1100 AGC_GAIN data placed in Slot 13.
1101 AGC_GAIN data placed in Slot 14.
1110 AGC_GAIN data placed in Slot 15.
1111 AGC_GAIN data placed in Slot 16.
Rev. A | Page 58 of 60
Data Sheet
SSM3525
SOFTWARE RESET REGISTER
Address: 0x2E, Reset: 0x00, Name: SOFT_RESET
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] S_RST (W)
Full Software Reset
0: Normal operation.
1: Reset all blocks and I2C registers.
Table 56. Bit Descriptions for SOFT_RESET
Bits
[7:1]
0
Bit Name
RESERVED
S_RST
Settings
Description
Reserved.
Full Software Reset
Normal operation.
Reset all blocks and I2C registers.
Reset
0x0
0x0
Access
R
W
0
1
Rev. A | Page 59 of 60
SSM3525
Data Sheet
OUTLINE DIMENSIONS
2.260
2.220
2.180
0.37
REF
5
4
3
2
1
A
B
C
D
E
BALL A1
IDENTIFIER
2.380
2.340
2.300
1.60
REF
0.40
BSC
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.31
REF
0.330
0.560
0.500
0.440
0.300
0.270
END VIEW
COPLANARITY
0.04
SEATING
PLANE
0.300
0.260
0.220
0.230
0.200
0.170
Figure 85. 23-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-23-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
SSM3525BCBZRL
EVAL-SSM3525Z
−40°C to +85°C
23-Ball Wafer Level Chip Scale Package [WLCSP]
SSM3525 Evaluation Board
CB-23-2
1 Z = RoHs Compliant Part.
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registered trademarks are the property of their respective owners.
D16190-0-5/18(A)
Rev. A | Page 60 of 60
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