SSM3582BCPZ [ADI]
2Ã, 31.76 W, Digital Input, Filterless Stereo Class-D Audio Amplifier;
| 型号： | SSM3582BCPZ |
| 厂家： | 
ADI |
| 描述： | 2Ã, 31.76 W, Digital Input, Filterless Stereo Class-D Audio Amplifier |
| 文件： | 总59页 (文件大小：751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2×, 31.76 W, Digital Input,
Filterless Stereo Class-D Audio Amplifier
SSM3582
Data Sheet
Supported sample rates from 8 kHz to 192 kHz; 24-bit
FEATURES
resolution
Digital input stereo, high efficiency Class-D amplifier
Operates from a single 4.5 V to 16 V supply
State-of-the-art, proprietary, filterless Σ-Δ modulation
106.5 dB signal-to-noise ratio
0.004% total harmonic distortion plus noise (THD + N)
at 5 W into 8 Ω
Multiple PCM audio serial data formats
TDM slave with support for up to 16 devices on a single bus
I2S or left justified slave
Adjustable full-scale output tailored for many PVDD sources
2- and 3-cell Li-Ion batteries
Digital volume control with selectable smooth ramp
Automatic power-down function
38.5 μV rms A weighted output noise
Pop/clickless on/off sequence
Supply monitoring automatic gain control (AGC) function
reduces system brownout
Standalone operational mode without I2C
Temperature sensor with 1°C step readout via I2C
Short-circuit, undervoltage, and thermal protection
Thermal early warning
2× 14.67 W output at 12 V supply to 4 Ω loads at <1% THD + N
2× 14.4 W output at 16 V supply to 8 Ω loads at <1% THD + N
Mono mode for increased maximum output power
1× 49.69 W output at 16 V supply to 2 Ω loads at <1% THD + N
Support for low impedance loads
As low as 3 Ω/5 ꢀH in stereo mode
As low as 2 Ω/5 ꢀH in mono mode
High power efficiency
93.8% efficiency into an 8 Ω load
Power-on reset
PVDD sensing ADC
40-lead, 6 mm × 6 mm LFCSP with thermal pad
90.6% efficiency into a 4 Ω load
APPLICATIONS
12.34 mA quiescent current with single 12 V PVDD supply
Single supply operation with internal LDOs or option to use
an external 5 V and 1.8 V supply for lowest power
consumption
I2C control and hardware modes with up to 16 pin-selectable
slots/addresses
Mobile computing
All in one computers
Portable electronics
Wireless speakers
Televisions
FUNCTIONAL BLOCK DIAGRAM
DVDD
DVDD_EN
AVDD AVDD_EN
PVDD
SDA
SCL
ADDR0
ADDR1
DVDD
1.8V LDO
AVDD
2
PVDD
ADC
TEMPERATURE
SENSOR
I C
CONTROL
5V LDO
OUTL+
THREE-LEVEL
BSTL+
BSTL–
FULL BRIDGE
Σ-∆
DAC
DAC
POWER STAGE
MODULATOR
OUTL–
VOLUME
BLCK
FSYNC
SDATA
2
I S
TDM
INTERFACE
BATTERY
AGC
OUTR+
THREE-LEVEL
Σ-∆
MODULATOR
BSTR+
BSTR–
FULL BRIDGE
POWER STAGE
OUTR–
SSM3582
AGND
PGND
Figure 1.
Rev. 0
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Technical Support
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SSM3582
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Mono Mode................................................................................. 31
Analog and Digital Gain ........................................................... 31
Pop and Click Suppression........................................................ 31
Temperature Sensor ................................................................... 31
Faults and Limiter Status Reporting ........................................ 32
VBAT (PVDD) Sensing................................................................ 32
Limiter and Battery Tracking Threshold Control.................. 32
High Frequency Clipper............................................................ 35
EMI Noise.................................................................................... 35
Output Modulation Description .............................................. 35
Bootstrap Capacitors.................................................................. 36
Power Supply Decoupling ......................................................... 36
Output EMI Filtering................................................................. 36
PCB Placement ........................................................................... 36
Layout .......................................................................................... 37
Register Summary .......................................................................... 38
Register Details ............................................................................... 39
Typical Application Circuit........................................................... 57
Outline Dimensions....................................................................... 59
Ordering Guide .......................................................................... 59
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Digital Input/Output Specifications........................................... 8
Digital Timing Specifications ..................................................... 8
Digital Input Timing Specifications........................................... 8
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 14
Theory of Operation ...................................................................... 25
Overview...................................................................................... 25
Power Supplies ............................................................................ 25
Power-Up Sequence ................................................................... 26
Power-Down Operation ............................................................ 26
Clocking....................................................................................... 26
Digital Audio Serial Interface ................................................... 26
Standalone Operation................................................................ 30
REVISION HISTORY
4/16—Revision 0: Initial Version
Rev. 0| Page 2 of 59
Data Sheet
SSM3582
GENERAL DESCRIPTION
The SSM3582 is a fully integrated, high efficiency, digital input
stereo Class-D audio amplifier. It can operate from a single supply,
and requires only a few external components, significantly
reducing the circuit bill of materials.
The pulse code modulation (PCM) audio serial port supports
most common protocols, such as I2S, left justified, and time
division multiplexing (TDM), and can address up to 16 devices
on a single interface, for up to 32 audio playback channels.
A proprietary, spread spectrum Σ-Δ modulation scheme
enables direct connection to the speaker, and ensures state-of-
the-art analog performance while lowering radiated emissions
compared to other Class-D architectures. An optional ultralow
electromagnetic interference (EMI) mode significantly reduces
radiated emissions above 100 MHz, enabling longer speaker
cable lengths. Audio is transmitted digitally to the amplifier,
minimizing the possibility of signal corruption in digital
environments. The amplifier provides outstanding analog
performance, with an over 106 dB signal-to-noise ratio and a
vanishingly low 0.004% THD + N.
IC operation is controlled through a dedicated I2C interface.
The two ADDRx pins (2×, 5-level) define up to 16 individual
addresses in I2C and standalone modes, and automatically set
the default TDM slots attribution.
A micropower shutdown mode is triggered by removing the
digital audio interface clock, with a typical current of <1 ꢀA.
A software power-down mode is also available.
An automatic power-down feature shuts down the amplifier
and the digital-to-analog converter (DAC) when no signal is
present at the input, minimizing power consumption during
digital silence. The device restarts when nonzero data is present at
the input. Mute and unmute transitions are pop/click free.
The SSM3582 operates from a single 4.5 V to 16 V supply, and
is capable of delivering 2 × 15 W rms continuously into 8 Ω and
4 Ω loads at <1% total harmonic distortion (THD). The
efficient modulation scheme maintains excellent power
efficiency over a wide range of impedances: 93% into an 8 Ω
load and 90% into a 4 Ω load. Optimization of the output pulse
maintains performance at impedances as low as 3 Ω/5 μH,
enabling its use with extended bandwidth tweeters.
The SSM3582 is specified over the commercial temperature range
of −40C to +85C. The device has built-in thermal shutdown and
output short-circuit protection, as well as an early thermal warning
with programmable gain limiting to maintain operation.
The SSM3582 is available in a 40-lead, 6 mm × 6 mm lead
frame chip scale package (LFCSP), with a thermal pad to
improve heat dissipation.
Rev. 0| Page 3 of 59
SSM3582
Data Sheet
SPECIFICATIONS
PVDD = 12 V, AVDD = 5 V (external), DVDD = 1.8 V (external), RL = 8 ꢁ + 33 μH, BCLK = 3.072 MHz, FSYNC = 48 kHz, TA = −40°C to
+85°C, unless otherwise noted. The measurements are taken with a 20 kHz AES17 low-pass filter. The other load impedances used are
4 ꢁ + 15 μH and 3 ꢁ + 10 μH. Measurements are taken with a 20 kHz AES17 low-pass filter, unless otherwise noted.
Table 1.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
DEVICE CHARACTERISTICS
Output Power Per Channel
Stereo Mode
PO
f = 1 kHz, both channels driven
RL = 8 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V
14.4
8.1
2.76
1.41
18
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
RL = 8 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 8 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 8 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V
RL = 8 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V
RL = 8 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 8 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 8 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V
RL = 4 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V
RL = 4 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 4 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 4 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V
RL = 4 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V
RL = 4 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 4 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 4 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V
f = 1 kHz
10
3.43
1.75
25.6
14.67
5.06
2.6
31.76
18.31
6.3
3.21
Mono Mode
RL = 3 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V
RL = 3 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 3 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 3 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V
RL = 3 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V
RL = 3 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 3 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 3 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V
RL = 2 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V
RL = 2 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 2 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 2 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V
RL = 2 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V
RL = 2 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
RL = 2 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
RL = 2 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V
Speaker inductance
36.11
20.46
7
3.58
44.96
25.49
8.7
4.43
49.69
28.55
9.85
5
62.4
35.5
12.22
6.22
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
μH
Minimal Load Inductance
Efficiency
5
η
Stereo Mode
Both channels driven
PO = 10 W, RL = 8 Ω, PVDD = 12 V
PO = 10 W, RL = 8 Ω, PVDD = 12 V (low EMI mode)
PO = 18 W, RL = 4 Ω, PVDD = 12 V
94
%
%
%
%
93.8
90.6
89.5
PO = 15 W, RL = 4 Ω, PVDD = 12 V (low EMI mode)
Mono Mode
PO = 25 W, RL = 3 Ω, PVDD = 12 V
PO = 25 W, RL = 3 Ω, PVDD = 12 V (low EMI mode)
PO = 35 W, RL = 2 Ω, PVDD = 12 V
PO = 35 W, RL = 2 Ω, PVDD = 12 V (low EMI mode)
Rev. 0| Page 4 of 59
92.3
92.1
89.9
89.7
%
%
%
%
Data Sheet
SSM3582
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
Total Harmonic Distortion +
Noise
THD + N PO = 5 W into 8 Ω, f = 1 kHz, PVDD = 12 V
0.004
%
Output Stage On Resistance RON
100
6
mΩ
A peak
Overcurrent Protection
Trip Point
IOC
Average Switching
Frequency
Differential Output Offset
Voltage
Crosstalk between Left and
Right
fSW
300
1
kHz
mV
dB
VOOS
AV = 19 dB
Measured at 1 kHz with regards to full-scale output
100
POWER SUPPLIES
Supply Voltage Range
PVDD
AVDD
DVDD
PSRR
4.5
4.5
1.62
16
5.5
1.98
V
V
V
5.0
1.8
Power Supply Rejection
Ratio
AC
PSRRAC
AV
VRIPPLE =100 mV rms at 1 kHz
VRIPPLE =1 V rms at 1 kHz
Measured with 0 dBFS input at 1 kHz
PVDD ≥ 6.3 V
PVDD ≥ 9 V
PVDD ≥ 12.6 V
86
88
dB
dB
ANALOG GAIN
Gain = 00
Gain = 01
Gain = 10
Gain = 11
6.2
V peak
V peak
V peak
V peak
8.75
12.5
15.5
PVDD = 16 V
SHUTDOWN CONTROL1
Turn On Time, Volume
Ramp Disabled
tWU
Time from SPWDN = 0 to output switching, DAC_HV = 1 or
DAC_MUTE_x = 1, tWU = 4 FSYNC cycles to 7 FSYNC cycles +
7.68 ms
fS = 12 kHz
fS = 24 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
8.01
7.84
7.76
7.72
7.70
8.27
7.98
7.83
7.76
7.72
ms
ms
ms
ms
ms
Turn On Time, Volume
Ramp Enabled
tWUR
Time from SPWDN = 0 to full volume output switching,
DAC_HV = 0 and DAC_MUTE_x = 0, VOL_x = 0x40
fS = 12 kHz
fS = 24 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
tWUR = tWU + 15.83 ms
tWUR = tWU + 15.83 ms
tWUR = tWU + 15.83 ms
tWUR = tWU + 7.92 ms
tWUR = tWU + 0.99 ms
23.84
23.67
23.59
15.64
8.69
24.10 ms
23.81 ms
23.66 ms
15.68 ms
8.71
ms
μs
Turn Off Time, Volume
Ramp Disabled
tSD
Time from SPWDN = 1 to full power-down, DAC_HV = 1 or
DAC_MUTE_x = 1
100
Turn Off Time, Volume
Ramp Enabled
tSDR
Time from SPWDN = 1 to full power-down, DAC_HV = 0 and
DAC_MUTE_x = 0, VOL_x = 0x40
fS = 12 kHz
fS = 24 kHz
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
Output Impedance
tSDR = tSD + 15.83 ms
tSDR = tSD + 15.83 ms
tSDR = tSD + 15.83 ms
tSDR = tSD + 7.92 ms
tSDR = tSD + 0.99 ms
15.932
15.932
15.932
8.016
1.09
ms
ms
ms
ms
ms
kΩ
ZOUT
100
Rev. 0| Page 5 of 59
SSM3582
Data Sheet
Parameter
NOISE PERFORMANCE2
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
Stereo mode
Output Voltage Noise
en
f = 20 Hz to 20 kHz, A weighted, PVDD = 12 V, 8 Ω
37.8
38.5
36.8
36.3
106.5
108.9
106.3
108.9
ꢀV rms
ꢀV rms
ꢀV rms
ꢀV rms
dB
dB
dB
dB
f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 8 Ω
f = 20 Hz to 20 kHz, A weighted, PVDD = 12 V, 4 Ω
f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 4 Ω
PO = 8.1 W, RL = 8 Ω, AV = 19 dB, PVDD = 12 V, A weighted
PO = 14.4 W, RL = 8 Ω, AV = 21 dB, PVDD = 16 V, A weighted
PO = 14.67 W, RL = 4 Ω, AV = 19 dB, PVDD = 12 V, A weighted
PO = 25.58 W, RL = 4 Ω, AV = 21 dB, PVDD = 16 V, A weighted
Signal-to-Noise Ratio
SNR
PVDD ADC PERFORMANCE
PVDD Sense Full-Scale
Range
PVDD Sense Absolute
Accuracy
PVDD with full-scale ADC output
PVDD = 15 V
3.8
−8
−6
16.2
+8
V
LSB
PVDD = 5 V
Unsigned 8-bit output with 3.8 V offset
+6
LSB
Bits
Resolution
Temperature Sense ADC
Temperature Sense Range
Temperature Sense
Accuracy
8
5
−60
+160 °C
°C
DIE TEMPERATURE
Overtemperature Warning
Overtemperature Protection
UNDERVOLTAGE FAULT
AVDD
117
145
°C
°C
3.6
3.6
V
V
PVDD
1 Guaranteed by design.
2 Noise performance is based on the bench data for TA = −40°C to +85°C.
Software master power-down indicates that the clocks are turned off. Automatic power-down indicates that there is no dither or zero
input signal with clocks on; the device enters soft power-down after 2048 cycles of zero input values. Quiescent indicates triangular dither
with zero input signal. All specifications are typical, with a 48 kHz sample rate, in stereo mode, unless otherwise noted.
Table 2. Power Supply Current Consumption, No Load1
Edge Rate
Control
Mode
IPVDD
IDVDD
IAVDD
Internal
Regulator Test Conditions
PVDD = 5 V PVDD = 12 V PVDD = 16 V PVDD = 1.8 V PVDD = 5 V Unit
Normal
Disabled
Enabled
Disabled
Enabled
Software master power-down 0.065
0.065
0.065
4.94
0.065
0.065
6.25
2.68
43.72
0.945
N/A
N/A
N/A
7.542
7.542
6.335
N/A
N/A
N/A
ꢀA
ꢀA
mA
ꢀA
ꢀA
mA
ꢀA
ꢀA
mA
ꢀA
ꢀA
mA
Automatic power-down
Quiescent
0.065
2.54
Software master power-down 0.065
0.065
286
12.38
0.065
0.065
5.01
0.065
329
14.05
0.065
0.065
6.31
Automatic power-down
Quiescent
209
9.78
Low EMI
Software master power-down 0.065
2.68
43.72
0.945
N/A
N/A
N/A
7.542
7.542
6.171
N/A
N/A
N/A
Automatic power-down
Quiescent
0.065
2.56
Software master power-down 0.065
0.065
286
12.09
0.065
329
13.74
Automatic power-down
Quiescent
209
9.69
1 N/A means not applicable.
Rev. 0| Page 6 of 59
Data Sheet
SSM3582
Table 3. Power Supply Current Consumption, 4 Ω + 15 μH1
Edge Rate
Control
Mode
IPVDD
IDVDD
IAVDD
Internal
Regulator Test Conditions
PVDD = 5 V PVDD = 12 V PVDD = 16 V PVDD = 1.8 V PVDD = 5 V Unit
Normal
Disabled
Enabled
Disabled
Enabled
Software master power-down 0.065
0.065
0.065
4.93
0.065
0.065
6.25
2.68
43.72
0.945
N/A
N/A
N/A
7.542
7.542
6.477
N/A
N/A
N/A
ꢀA
ꢀA
mA
ꢀA
ꢀA
mA
ꢀA
ꢀA
mA
ꢀA
ꢀA
mA
Automatic power-down
Quiescent
0.065
2.6
Software master power-down 0.065
0.065
286
12.34
0.065
0.065
4.62
0.065
329
13.58
0.065
0.065
5.6
Automatic power-down
Quiescent
209
9.83
Low EMI
Software master power-down 0.065
2.68
43.72
0.945
N/A
N/A
N/A
7.542
7.542
6.182
N/A
N/A
N/A
Automatic power-down
Quiescent
0.065
2.51
Software master power-down 0.065
0.065
286
11.86
0.065
329
12.87
Automatic power-down
Quiescent
209
9.64
1 N/A means not applicable.
Table 4. Power Supply Current Consumption, 8 Ω + 33 μH1
Edge Rate
Control
IPVDD
IDVDD
IAVDD
Internal
Mode
Regulator Test Conditions
PVDD = 5 V PVDD = 12 V PVDD = 16 V PVDD = 1.8 V PVDD = 5 V Unit
Normal
Disabled
Enabled
Disabled
Enabled
Software master power-down 0.065
0.065
0.065
5.02
0.065
0.065
6.31
2.68
43.72
0.942
N/A
N/A
N/A
7.542
7.542
6.432
N/A
N/A
N/A
ꢀA
ꢀA
mA
ꢀA
ꢀA
mA
ꢀA
ꢀA
mA
ꢀA
ꢀA
mA
Automatic power-down
Quiescent
0.065
2.59
Software master power-down 0.065
0.065
286
12.39
0.065
0.065
4.86
0.065
329
13.73
0.065
0.065
6.02
Automatic power-down
Quiescent
209
9.82
Low EMI
Software master power-down 0.065
2.68
43.72
0.942
N/A
N/A
N/A
7.542
7.542
6.232
N/A
N/A
N/A
Automatic power-down
Quiescent
0.065
2.57
Software master power-down 0.065
0.065
286
12.02
0.065
329
13.18
Automatic power-down
Quiescent
209
9.65
1 N/A means not applicable.
Table 5. Power-Down Current
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
POWER-DOWN CURRENT
External AVDD = 5 V and DVDD = 1.8 V, software
master power-down, no BCLK/FSYNC
IPVDD
PVDD = 5 V
PVDD = 12 V
PVDD = 16 V
AVDD = 5 V external
DVDD = 1.8 V external
65
65
65
7.542
2.7
nA
nA
nA
μA
μA
IAVDD
IDVDD
Rev. 0| Page 7 of 59
SSM3582
Data Sheet
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 6.
Parameter
INPUT VOLTAGE1
Min
Typ
Max
Unit
Test Conditions/Comments
BCLK, FSYNC, SDATA, SCL, and SDA Pins
High (VIH)
Low (VIL)
0.7 × DVDD
−0.3
5.5
+0.3 × DVDD
V
V
INPUT LEAKAGE
BCLK, FSYNC, SDATA, ADDRx, SCL, and SDA Pins
High (IIH)
Low (IIL)
1
1
5
ꢀA
ꢀA
pF
INPUT CAPACITANCE
OUTPUT DRIVE STRENGTH1
SDA
3
8
5
mA
kHz
SAMPLE RATE (FSYNC FREQUENCY)
192
1 The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 kΩ.
DIGITAL TIMING SPECIFICATIONS
All timing specifications are given for the default setting (I2S mode) of the serial input port.
Table 7.
Limit
Parameter
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tDH
tSCR
tSCF
tSDR
tSDF
Min
Max
Unit
Description
400
kHz
ꢀs
ꢀs
ꢀs
ꢀs
ns
ꢀs
ns
ns
ns
ns
ꢀs
SCL frequency
SCL high
SCL low
Setup time; relevant for repeated start condition
Hold time; after this period, the first clock is generated
Data setup time
Data hold time
SCL rise time
SCL fall time
SDA rise time
SDA fall time
Bus free time (time between stop and start)
0.26
0.5
0.26
0.26
50
0.14
120
120
120
120
tBFT
0.5
DIGITAL INPUT TIMING SPECIFICATIONS
Table 8.
Limit
Parameter
TMIN
TMAX
Unit
Description
SERIAL PORT
tBIL
tBIH
tSIS
tSIH
tLIS
tLIH
tBP
10
10
4
4
5
ns
ns
ns
ns
ns
ns
ns
BCLK low pulse width
BCLK high pulse width
SDATA setup; time to BCLK rising
SDATA hold; time from BCLK rising
FSYNC setup time to BCLK rising
FSYNC hold time to BCLK rising
Minimum BCLK period
5
20
Rev. 0| Page 8 of 59
Data Sheet
SSM3582
Digital Timing Diagrams
tSDR
tDS
tSCH
tSCH
SDA
SCL
tSDF
tSCS
tDH
tSCR
tSCLH
tSCLL
tSCF
tBFT
START
CONDITION
STOP
CONDITION
Figure 2. I2C Port Timing
tBIH
tBP
BCLK
tBIL
tLIS
tLIH
FSYNC
tSIS
SDATA
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
tSIH
tSIS
SDATA
2
I C-JUSTIFIED
MSB
MODE
tSIH
tSIS
tSIS
SDATA
RIGHT-JUSTIFIED
MODE
MSB
LSB
tSIH
tSIH
Figure 3. Serial Input Port Timing
PVDD
tWU
PVDD/2
OUTPUT
0V
2
I C POWER-UP COMMAND
Figure 4. Turn On Time, Hard Volume
Rev. 0| Page 9 of 59
SSM3582
Data Sheet
tSD
PVDD
OUTPUT
0V
2
I C POWER-DOWN COMMAND
Figure 5. Turn Off Time, Hard Volume
Rev. 0| Page 10 of 59
Data Sheet
SSM3582
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA (junction to air) is specified for the worst case conditions,
that is, a device soldered in a circuit board for surface-mount
packages. θJA and θJB are determined according to JESD51-9 on
a 4-layer (2s2p) printed circuit board (PCB) with natural
convection cooling.
Table 9.
Parameter
Rating
PVDD Supply Voltage
DVDD Supply Voltage
AVDD Supply Voltage
PGND and AGND Differential
Digital Input Pins
−0.3 V to +17 V
−0.3 V to +1.98 V
−0.3 V to +5.5 V
0.3 V
Table 10. Thermal Resistance
Package Type
θJA
θJC
Unit
FSYNC, BCLK, SDATA, SCL, SDA
Analog Input Pins
−0.3 V to +5.5 V
40-Lead, 6 mm × 6 mm LFCSP
27
1.1
°C/W
ADDRx
AVDD_EN
DVDD_EN
−0.3 V to +1.98 V
−0.3 V to +17 V
−0.3 V to +5.5 V
ESD CAUTION
ESD Susceptibility
Human Body Model
Charged Device Model
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
2 kV
1 kV
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0| Page 11 of 59
SSM3582
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PGND
30
PGND
PGND
1
2
3
4
5
6
7
8
9
29 PGND
28 DVDD
27 ADDR1
26 ADDR0
25 AGND
24 AVDD
AVDD_EN
SCL
SSM3582
TOP VIEW
(Not to Scale)
SDA
FSYNC
SDATA
BCLK
23 DVDD_EN
22 PGND
21 PGND
PGND
PGND 10
NOTES
1. USE MULTIPLE VIAS TO CONNECT THE EXPOSED PAD
TO THE GROUND PLANE ON THE PCB.
Figure 6. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1
2
3
PGND
PGND
AVDD_EN
PWR
PWR
AIN
Left Channel Power Stage Ground.
Left Channel Power Stage Ground.
5 V AVDD Regulator Enable. Connect this pin to PVDD to enable the AVDD regulator or connect to AGND
to disable the regulator. When this pin is connected to PVDD, the regulator is enabled. When this pin is
connected to AGND, the regulator is disabled.
I2C Clock Input.
I2C Data.
I2S/TDM Frame Sync (FSYNC) Input.
I2S/TDM Serial Data (SDATA) Input.
I2S/TDM Bit Clock (BCLK) Input.
Right Channel Power Stage Ground.
Right Channel Power Stage Ground.
Bootstrap Input, Right Channel Noninverting.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
SCL
SDA
FSYNC
SDATA
BCLK
DIN
DIO
DIN
DIN
DIN
PWR
PWR
AIN
PGND
PGND
BSTR+
OUTR+
OUTR+
PVDD
PVDD
PVDD
PVDD
OUTR−
OUTR−
BSTR−
PGND
PGND
DVDD_EN
AOUT Right Channel Noninverting Output.
AOUT Right Channel Noninverting Output.
PWR
PWR
PWR
PWR
AOUT Right Channel Inverting Output.
AOUT Right Channel Inverting Output.
AIN
Right Channel Power Stage Supply.
Right Channel Power Stage Supply.
Right Channel Power Stage Supply.
Right Channel Power Stage Supply.
Bootstrap Input, Right Channel Inverting.
Right Channel Power Stage Ground.
Right Channel Power Stage Ground.
1.8 V DVDD Regulator Enable. Connect this pin to AVDD to enable the DVDD regulator or connect to
AGND to disable the regulator. When this pin is connected to AVDD, the regulator is enabled. When this
pin is connected to AGND, the regulator is disabled.
PWR
PWR
AIN
24
25
26
27
28
29
30
31
AVDD
AGND
ADDR0
ADDR1
DVDD
PGND
PGND
BSTL−
PWR
PWR
AIN
Analog Supply 5 V Regulator Output/External 5 V Input.
Analog Ground.
Address Select 0 (See Table 14).
AIN
Address Select 1 (See Table 14).
PWR
PWR
PWR
AIN
Digital Supply 1.8 V Regulator Output/External 1.8 V Input.
Left Channel Power Stage Ground.
Left Channel Power Stage Ground.
Bootstrap Input, Left Channel Inverting.
Rev. 0| Page 12 of 59
Data Sheet
SSM3582
Pin No. Mnemonic Type1 Description
32
33
34
35
36
37
38
39
40
OUTL−
OUTL−
PVDD
PVDD
PVDD
PVDD
OUTL+
OUTL+
BSTL+
EPAD
AOUT Left Channel Inverting Output.
AOUT Left Channel Inverting Output.
PWR
PWR
PWR
PWR
Left Channel Power Stage Supply.
Left Channel Power Stage Supply.
Left Channel Power Stage Supply.
Left Channel Power Stage Supply.
AOUT Left Channel Noninverting Output.
AOUT Left Channel Noninverting Output.
AIN
Bootstrap Input, Left Channel Noninverting.
Exposed Pad. Use multiple vias to connect the exposed pad to the ground plane on the PCB.
1 PWR is power supply or ground pin, AIN is analog input, DIN is digital input, DIO is digital input/output, and AOUT is analog output.
Rev. 0| Page 13 of 59
SSM3582
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
10
20
10
0
60dBFS INPUT
60dBFS INPUT
ANALOG GAIN = 6.3V peak
ANALOG GAIN = 16V peak
0
R
= 4Ω (LOW EMI)
R = 4Ω (LOW EMI)
L
L
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–100
–110
–120
–130
–140
–150
–160
–170
–180
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 6.3 V peak
Figure 10. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 16 V peak
20
20
10
0
–10
10
0
–10
60dBFS INPUT
NO SIGNAL
ANALOG GAIN = 8.9V peak
ANALOG GAIN = 6.3V peak
R
= 4Ω (LOW EMI)
R = 4Ω (LOW EMI)
L
L
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–100
–110
–120
–130
–140
–150
–160
–170
–180
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 8.9 V peak
Figure 11. Amplitude vs. Frequency, No Signal, Analog Gain = 6.3 V peak
20
20
10
0
–10
10
0
–10
60dBFS INPUT
NO SIGNAL
ANALOG GAIN = 12.6V peak
ANALOG GAIN = 8.9V peak
R
= 4Ω (LOW EMI)
R = 4Ω (LOW EMI)
L
L
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–100
–110
–120
–130
–140
–150
–160
–170
–180
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 12.6 V peak
Figure 12. Amplitude vs. Frequency, No Signal, Analog Gain = 8.9 V peak
Rev. 0| Page 14 of 59
Data Sheet
SSM3582
20
10
0
–10
1.000
0.500
NO SIGNAL
R
= 4Ω
L
ANALOG GAIN = 12.6V peak
PV = 12V
DD
R
= 4Ω (LOW EMI)
L
–20
–30
–40
–50
–60
–70
0.200
0.100
0.050
–80
–90
0.020
0.010
–100
–110
–120
–130
–140
–150
–160
–170
–180
100mW
1W
5W
0.005
0.002
0.001
20
50
100 200
500
1k
2k
5k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. THD + N vs. Frequency, RL = 4 Ω, PVDD = 12 V
Figure 13. Amplitude vs. Frequency, No Signal, Analog Gain = 12.6 V peak
1.000
0.500
20
10
0
–10
NO SIGNAL
R
= 4Ω
L
ANALOG GAIN = 16V peak
PV = 16V
DD
R
= 4Ω (LOW EMI)
L
–20
–30
–40
–50
–60
–70
0.200
0.100
0.050
–80
–90
0.020
0.010
–100
–110
–120
–130
–140
–150
–160
–170
–180
100mW
1W
0.005
10W
0.002
0.001
20
50
100 200
500
1k
2k
5k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. THD + N vs. Frequency, RL = 4 Ω, PVDD = 16 V
Figure 14. Amplitude vs. Frequency, No Signal, Analog Gain = 16 V peak
1.000
0.500
1.000
R
= 8Ω
R
= 4Ω
L
L
PV = 4.5V
0.500
PV = 4.5V peak
DD
DD
0.200
0.100
0.050
0.200
0.100
0.050
0.020
0.010
0.020
0.010
100mW
100mW
500mW
0.005
0.005
1W
0.002
0.001
0.002
0.001
20
50
100 200
500
1k
2k
5k
10k 20k
20
50
100 200
500
1k
2k
5k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. THD + N vs. Frequency, RL = 8 Ω, PVDD = 4.5 V
Figure 15. THD + N vs. Frequency, RL = 4 Ω, PVDD = 4.5 V peak
Rev. 0| Page 15 of 59
SSM3582
Data Sheet
1.000
10
5
R
= 8Ω
R = 4Ω
L
ANALOG GAIN = 8.9V peak
L
0.500
PV = 12V
DD
2
0.200
0.100
0.050
1.000
0.500
4.5V
12.0V
0.200
0.100
16.0V (3dB GAIN ADDED)
0.020
0.010
0.050
100mW
0.020
0.010
0.005
0.005
1W
5W
0.002
0.001
0.002
0.001
20
50
100 200
500
1k
2k
5k
10k 20k
FREQUENCY (Hz)
POWER (W)
Figure 19. THD + N vs. Frequency, RL = 8 Ω, PVDD = 12 V
Figure 22. THD + N vs. Power, RL = 4 Ω, Analog Gain = 8.9 V peak
1.000
0.500
10
R
= 8Ω
R = 4Ω
L
ANALOG GAIN = 12.6V peak
L
5
2
PV = 16V
DD
1.000
0.500
0.200
0.100
4.5V
12.0V
16.0V
0.200
0.100
0.050
0.020
0.010
0.050
100mW
1W
0.020
0.010
0.005
0.005
0.002
0.001
5W
0.002
0.001
20
50
100 200
500
1k
2k
5k
10k 20k
FREQUENCY (Hz)
POWER (W)
Figure 23. THD + N vs. Power, RL = 4 Ω, Analog Gain = 12.6 V peak
Figure 20. THD + N vs. Frequency, RL = 8 Ω, PVDD = 16 V
10
10
5
R
= 4Ω
R
= 4Ω
L
L
5
2
ANALOG GAIN = 16V peak
ANALOG GAIN = 6.3V peak
2
1.000
0.500
1.000
0.500
4.5V
4.5V
12.0V
16.0V
7.0V
16.0V
0.200
0.100
0.200
0.100
0.050
0.050
0.020
0.010
0.005
0.020
0.010
0.005
0.002
0.001
0.002
0.001
POWER (W)
POWER (W)
Figure 24. THD + N vs. Power, RL = 4 Ω, Analog Gain = 16 V peak
Figure 21. THD + N vs. Power, RL = 4 Ω, Analog Gain = 6.3 V peak
Rev. 0| Page 16 of 59
Data Sheet
SSM3582
10
10
5
R
= 8Ω
R = 8Ω
L
ANALOG GAIN = 16V peak
L
5
2
ANALOG GAIN = 6.3V peak
2
1.000
0.500
1.000
0.500
4.5V
4.5V
7.0V
16.0V
12.0V
16.0V
0.200
0.100
0.200
0.100
0.050
0.050
0.020
0.010
0.005
0.020
0.010
0.005
0.002
0.001
0.002
0.001
POWER (W)
POWER (W)
Figure 25. THD + N vs. Power, RL = 8 Ω, Analog Gain = 6.3 V peak
Figure 28. THD + N vs. Power, RL = 8 Ω, Analog Gain = 16 V peak
10
7
ANALOG GAIN = 6.3V peak
L
R
= 8Ω
L
P
P
= 10%
= 1%
OUT
5
2
R
= 4Ω
ANALOG GAIN = 8.9V peak
6
5
4
3
2
1
0
1.000
0.500
OUT
4.5V
12.0V
16.0V
0.200
0.100
0.050
0.020
0.010
0.005
0.002
0.001
5
6
7
8
9
10
11
12
PV (V)
DD
POWER (W)
Figure 29. Power vs. PVDD, RL = 4 Ω, Analog Gain = 6.3 V peak
Figure 26. THD + N vs. Power, RL = 8 Ω, Analog Gain = 8.9 V peak
14
10
ANALOG GAIN = 8.9V peak
= 4Ω
R
= 8Ω
L
P
= 10%
= 1%
OUT
5
2
R
L
ANALOG GAIN = 12.6V peak
12
10
8
P
1.000
0.500
OUT
4.5V
12.0V
16.0V
0.200
0.100
0.050
6
0.020
0.010
0.005
4
2
0.002
0.001
0
7
8
9
10
11
12
PV (V)
DD
POWER (W)
Figure 27. THD + N vs. Power, RL = 8 Ω, Analog Gain = 12. 6 V peak
Figure 30. Power vs. PVDD, RL = 4 Ω, Analog Gain = 8.9 V peak
Rev. 0| Page 17 of 59
SSM3582
Data Sheet
30
100
90
80
70
60
50
40
30
20
10
0
ANALOG GAIN = 12.6V peak
= 4Ω
R
L
P
= 10%
OUT
25
20
15
10
5
NORMAL EMI
LOW EMI
P
= 1%
OUT
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 8.9V peak
R
= 4Ω
L
PV
= 7V
DD
0
7
9
11
PV (V)
13
15
0
1
2
3
4
5
6
7
P
(W)
DD
OUT
Figure 31. Power vs. PVDD, RL = 4 Ω, Analog Gain = 12.6 V peak
Figure 34. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 4 Ω, PVDD = 7 V
35
100
90
ANALOG GAIN = 16V peak
L
R
= 4Ω
30
25
20
15
10
5
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 12.6V peak
P
= 10%
OUT
R
PV
= 4Ω
L
= 12V
DD
P
= 1%
OUT
0
0
2.5
5.0
7.5
10.0
(W)
OUT
12.5
15.0
17.5
20.0
7
9
11
PV (V)
13
15
P
DD
Figure 32. Power vs. PVDD, RL = 4 Ω, Analog Gain = 16 V peak
Figure 35. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 4 Ω, PVDD = 12 V
100
100
90
90
80
70
60
50
40
30
20
10
0
80
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
70
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 16V peak
60
50
40
30
20
10
0
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 6.3V peak
R
= 4Ω
L
R
PV
= 4Ω
L
PV
= 16V
DD
= 5V
DD
0
0.5
1.0
1.5
P
2.0
(W)
2.5
3.0
3.5
0
5
10
15
20
(W)
25
30
35
P
OUT
OUT
Figure 33. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 4 Ω, PVDD = 5 V
Figure 36. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak,
RL = 4 Ω, PVDD = 16 V
Rev. 0| Page 18 of 59
Data Sheet
SSM3582
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 16V peak
FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 6.3V peak
R
PV
= 4Ω
L
R
PV
= 4Ω
L
= 16V
DD
= 5V
DD
0
0.5
1.0
1.5
P
2.0
(W)
2.5
3.0
3.5
0
5
10
15
20
(W)
25
30
35
P
OUT
OUT
Figure 37. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 4 Ω, PVDD = 5 V
Figure 40. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 16 V peak,
RL = 4 Ω, PVDD = 16 V
100
90
0.010
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 12.6V peak
R
= 4Ω
L
80
70
60
50
40
30
20
10
0
0.008
0.006
0.004
0.002
0
NORMAL EMI
LOW EMI
FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 8.9V peak
R
PV
= 4Ω
L
NORMAL EMI
= 7V
DD
LOW EMI
0
1
2
3
4
5
6
7
5
7
9
11
(V)
13
15
P
(W)
P
VDD
OUT
Figure 38. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 4 Ω, PVDD = 7 V
Figure 41. IPVDD vs. PVDD, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 4 Ω
100
90
0.010
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 12.6V peak
R
= 4Ω
L
80
70
60
50
40
30
20
10
0
0.008
0.006
0.004
0.002
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 12V peak
R
PV
= 4Ω
L
= 12V
DD
0
5
10
15
20
5
7
9
11
13
15
P
(W)
P
(V)
OUT
VDD
Figure 39. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 12 V peak,
RL = 4 Ω, PVDD = 12 V
Figure 42. IPVDD vs. PVDD, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 4 Ω
Rev. 0| Page 19 of 59
SSM3582
Data Sheet
3.5
20
18
16
14
12
10
8
ANALOG GAIN = 6.3V peak
L
ANALOG GAIN = 16V peak
L
P
P
= 10%
= 1%
OUT
OUT
R
= 8Ω
R
= 8Ω
3.0
2.5
2.0
1.5
1.0
0.5
0
P
= 10%
OUT
P
= 1%
OUT
6
4
2
0
7
8
9
10
11
PV
12
(V)
13
14
15
16
5
6
7
8
9
10
11
12
PV (V)
DD
DD
Figure 43. Power vs. PVDD, Analog Gain = 6.3 V peak, RL = 8 Ω
Figure 46. Power vs. PVDD, Analog Gain = 16 V peak, RL = 8 Ω
7
100
ANALOG GAIN = 8.9V peak
= 8Ω
P
P
= 10%
= 1%
OUT
OUT
R
L
90
80
70
60
50
40
30
20
10
0
6
5
4
3
2
1
0
NORMAL EMI
LOW EMI
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 6.3V peak
R
= 8Ω
L
PV
= 5V
DD
0
0.5
1.0
(W)
1.5
2.0
7
8
9
10
11
12
P
PV (V)
OUT
DD
Figure 44. Power vs. PVDD, Analog Gain = 8.9 V peak, RL = 8 Ω
Figure 47. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 8 Ω, PVDD = 5 V
14
100
90
ANALOG GAIN = 12.6V peak
L
P
P
= 10%
= 1%
OUT
OUT
R
= 8Ω
12
10
8
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 8.9V peak
R
= 8Ω
L
PV
= 7V
DD
6
4
2
0
7
8
9
10
11
12
13
14
15
16
0
0.5
1.0
1.5
2.0
P (W)
OUT
2.5
3.0
3.5
4.0
PV
(V)
DD
Figure 45. Power vs. PVDD, Analog Gain = 12.6 V peak, RL = 8 Ω
Figure 48. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 8 Ω, PVDD = 7 V
Rev. 0| Page 20 of 59
Data Sheet
SSM3582
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 12.6V peak
FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 8.9V peak
R
= 8Ω
R = 8Ω
PV = 7V
DD
L
L
PV = 12V
DD
0
2
4
6
8
10
12
0
0.5
1.0
1.5
2.0
P (W)
OUT
2.5
3.0
3.5
4.0
P
(W)
OUT
Figure 49. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 8 Ω, PVDD = 12 V
Figure 52. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 8 Ω, PVDD = 7 V
100
90
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 16V peak
FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 12.6V peak
R
PV
= 8Ω
L
R
= 8Ω
= 16V
L
DD
PV = 12V
DD
0
5
10
15
20
0
2.5
5.0
7.5
10.0
12.5
P
(W)
P
(W)
OUT
OUT
Figure 50. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak,
RL = 8 Ω, PVDD = 16 V
Figure 53. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 8 Ω, PVDD = 12 V
100
90
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 6.3V peak
FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 16V peak
R
PV
= 8Ω
R = 8Ω
PV = 16V
DD
L
L
= 5V
DD
0
0.25
0.50
0.75
1.00
(W)
1.25
1.50
1.75
2.00
0
2.5
5.0
7.5
10.0
P (W)
OUT
12.5
15.0
17.5
20.0
P
OUT
Figure 51. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 8 Ω, PVDD = 5 V
Figure 54. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 16 V peak,
RL = 8 Ω, PVDD = 16 V
Rev. 0| Page 21 of 59
SSM3582
Data Sheet
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 6.3V peak (MONO)
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 16V peak (MONO)
R
PV
= 2Ω
L
R
PV
= 2Ω
L
= 5V
DD
= 16V
DD
0
0
1
2
3
4
5
6
7
0
10
20
30
40
(W)
50
60
70
P
(W)
P
OUT
OUT
Figure 55. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 2 Ω, PVDD = 5 V
Figure 58. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak,
RL = 2 Ω, PVDD = 16 V
100
90
100
90
80
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
70
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 6.3V peak (MONO)
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 8.9V peak (MONO)
60
50
40
30
20
10
0
R
PV
= 3Ω
L
R
PV
= 2Ω
L
= 5V
DD
= 7V
DD
0
0.5
1.0
1.5
2.0
2.5
P (W)
OUT
3.0
3.5
4.0
4.5
5.0
0
2
4
6
8
10
12
14
P
(W)
OUT
Figure 56. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 2 Ω, PVDD = 7 V
Figure 59. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 3 Ω, PVDD = 5 V
100
90
100
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
NORMAL EMI
LOW EMI
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 12.6V peak (MONO)
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 8.9V peak (MONO)
R
PV
= 2Ω
R = 3Ω
PV = 7V
DD
L
L
= 12.6V
DD
0
5
10
15
20
25
30
35
40
0
1
2
3
4
5
6
7
8
9
10
P
(W)
P
(W)
OUT
OUT
Figure 57. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 2 Ω, PVDD = 12.6 V
Figure 60. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 3 Ω, PVDD = 7 V
Rev. 0| Page 22 of 59
Data Sheet
SSM3582
100
90
80
70
60
50
40
30
20
10
0
30
25
20
15
10
5
ANALOG GAIN = 8.9V peak (MONO)
= 2Ω
R
L
NORMAL EMI
LOW EMI
P
P
= 10%
= 1%
OUT
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 12.6V peak (MONO)
OUT
R
PV
= 3Ω
L
= 12V
DD
0
0
5
10
15
20
25
30
7
8
9
10
11
12
P
(W)
PV (V)
DD
OUT
Figure 61. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 3 Ω, PVDD = 12 V
Figure 64. Power vs. PVDD, Analog Gain = 8.9 V peak, RL = 2 Ω
100
90
60
ANALOG GAIN = 12.6V peak (MONO)
L
R
= 2Ω
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
NORMAL EMI
LOW EMI
P
P
= 10%
= 1%
OUT
NO FERRITE BEAD, 220pF CAPACITOR
ANALOG GAIN = 16V peak (MONO)
OUT
R
PV
= 3Ω
L
= 16V
DD
0
5
10
15
20
25
30
35
40
45
50
7
8
9
10
11
12
13
14
15
16
P
(W)
PV (V)
OUT
DD
Figure 62. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak,
RL = 3 Ω, PVDD = 16 V
Figure 65. Power vs. PVDD, Analog Gain = 12.6 V peak, RL = 2 Ω
14
70
ANALOG GAIN = 8.9V peak (MONO)
L
ANALOG GAIN = 16V peak MONO)
L
R
= 4Ω
R
= 2Ω
12
10
8
60
50
40
30
20
10
0
P
P
= 10%
= 1%
OUT
P
= 10%
OUT
OUT
P
= 1%
OUT
6
4
2
0
7
8
9
10
11
12
13
14
15
16
5
6
7
8
9
10
11
12
PV (V)
DD
PV (V)
DD
Figure 63. Power vs. PVDD, Analog Gain = 8.9 V p-p, RL = 4 Ω
Figure 66. Power vs. PVDD, Analog Gain = 16 V peak, RL = 2 Ω
Rev. 0| Page 23 of 59
SSM3582
Data Sheet
9
35
30
25
20
15
10
5
ANALOG GAIN = 6.3V peak (MONO)
L
ANALOG GAIN = 12.6V peak (MONO)
L
P
P
= 10%
= 1%
OUT
R
= 4Ω
R
= 3Ω
8
7
6
5
4
3
2
1
0
OUT
P
= 10%
OUT
P
= 1%
OUT
0
7
8
9
10
11
12
13
14
15
16
5
6
7
8
9
10
11
12
PV (V)
DD
PV (V)
DD
Figure 67. Power vs. PVDD, Analog Gain = 6.3 V peak, RL = 4 Ω
Figure 69. Power vs. PVDD, Analog Gain = 12.6 V peak, RL = 3 Ω
18
50
ANALOG GAIN = 8.9V peak (MONO)
= 3Ω
ANALOG GAIN = 16V peak (MONO)
L
P
P
= 10%
= 1%
OUT
OUT
R
R
= 3Ω
L
45
40
35
30
25
20
15
10
5
16
14
12
10
8
P
= 10%
OUT
P
= 1%
OUT
6
4
2
0
0
7
8
9
10
11
12
7
8
9
10
11
12
13
14
15
16
PV (V)
DD
PV (V)
DD
Figure 68. Power vs. PVDD, Analog Gain = 8.9 V peak RL = 3 Ω
Figure 70. Power vs. PVDD, Analog Gain = 16 V peak, RL = 3 Ω
Rev. 0| Page 24 of 59
Data Sheet
SSM3582
THEORY OF OPERATION
OVERVIEW
POWER SUPPLIES
PVDD
The SSM3582 is a stereo, Class-D audio amplifier with a filterless
modulation scheme that greatly reduces external component count,
conserving board space and reducing system cost. The SSM3582
does not require an output filter; it relies on the inherent induc-
tance of the speaker coil and the natural filtering of the speaker
and human ear to recover the audio component of the square
wave output. Most Class-D amplifiers use some variation of pulse-
width modulation (PWM) to generate the output switching
pattern, whereas the SSM3582 uses Σ-Δ modulation, resulting
in important benefits. Σ-Δ modulators do not produce a sharp
peak with many harmonics in the AM broadcast band, as pulse-
width modulators often do. Σ-Δ modulation reduces the amplitude
of spectral components at high frequencies, reducing EMI emission
that may otherwise radiate from speakers and long cable traces.
Due to the inherent spread spectrum nature of Σ-Δ modulation,
the need for oscillator synchronization is eliminated for designs
incorporating multiple SSM3582 amplifiers. The SSM3582 uses
less power in quiescent conditions, which helps conserve the power
drawn from the battery or power supply.
PVDD supplies the output power stages, as well as the low
dropout (LDO) regulator for AVDD and DVDD.
AVDD
AVDD is the analog supply used for the modulator, power stage
driver, and other analog blocks.
When the AVDD_EN pin = PVDD, the internal regulator
generates 5 V and the AVDD pin is used for decoupling only.
When the AVDD_EN pin = AGND, 5 V must be provided to
the AVDD pin from an external system source, minimizing
power losses.
DVDD
DVDD supplies the digital circuitry. The current in this node is
very low, below 1 mA.
When the DVDD_EN pin = AVDD, the internal regulator
generates 1.8 V and the DVDD pin is used for decoupling only.
When the DVDD_EN pin = AGND, 1.8 V must be provided to
the DVDD pin from an external system source, minimizing
power losses.
The SSM3582 integrates overcurrent and temperature protection
and a thermal warning with optional programmable automatic
gain reduction.
Table 12 summarizes the power dissipation in various supply
configurations, operating modes, and load characteristics.
Table 12. Typical Power Supply Current Consumption for fS = 48 kHz1
PVDD (V)
5
12
16
Total
Power
(mW)
Total
Power
(mW)
AVDD_
EN Pin
Test
Conditions
AVDD
Pin
IAVDD
(mA)
IDVDD
(mA)
Total Power
(mW)
Load
IPVDD (mA)
IPVDD (mA)
0.000065
0.000065
IPVDD (mA)
0.000065
0.000065
Low
No load
SPWDN = 1
External 0.007542 0.00268 0.000065
External 0.007542 0.04372 0.000065
0.042859
0.116731
0.043314
0.117186
0.043574
0.117446
Automatic
power-down
Dither input
SPWDN = 1
External 6.335
0.945
N/A
2.54
46.076
0.000325
1.045
4.94
92.656
0.00078
3.432
6.25
133.376
0.00104
5.264
PVDD
Low
No load
Internal
Internal
N/A
N/A
0.000065
0.209
0.000065
0.286
0.000065
0.329
Automatic
power-down
N/A
Dither input
SPWDN = 1
Internal
N/A
N/A
9.78
48.9
12.38
148.56
14.05
224.8
8 Ω + 33 ꢀH
8 Ω + 33 ꢀH
External 0.007542 0.00268 0.000065
External 0.007542 0.04372 0.000065
0.042859
0.116731
0.000065
0.000065
0.043314
0.117186
0.000065
0.000065
0.043574
0.117446
Automatic
power-down
Dither input
SPWDN = 1
External 6.432
0.942
N/A
2.59
46.8056
0.000325
1.045
5.02
94.0956
0.00078
3.432
6.31
134.8156
0.00104
5.264
PVDD
Internal
Internal
N/A
N/A
0.000065
0.209
0.000065
0.286
0.000065
0.329
Automatic
N/A
power-down
Dither input
Internal
N/A
N/A
9.82
49.1
12.39
148.68
13.73
219.68
1 N/A means not applicable.
Rev. 0| Page 25 of 59
SSM3582
Data Sheet
POWER-UP SEQUENCE
CLOCKING
Using Only PVDD as a Source
A BCLK signal must be provided to the SSM3582 for correct
operation. The BCLK signal must have a minimum frequency
of 2.048 MHz. The BCLK rate is autodetected, but the sampling
frequency must be indicated. The BCLK rates supported at
32 kHz to 48 kHz are 50, 64, 100, 128, 192, 200, 256, 384, 400,
512, 768, 800, and 1024 times the sample rate.
When SSM3582 is used in single-supply mode, all internal rails are
generated from PVDD. The internal AVDD (5 V) and DVDD
(1.8 V) regulators can be enabled by pulling the AVDD_EN and
DVDD_EN pins high. AVDD_EN is pulled to PVDD, and
DVDD_EN is pulled to AVDD. The amplifier is operational and
responds to I2C writes 10 ms after applying PVDD ≥ 5 V.
DIGITAL AUDIO SERIAL INTERFACE
Using PVDD and External AVDD
The SSM3582 includes a standard serial audio interface that is
slave only. The interface is capable of receiving I2S, left justified,
PCM, or TDM formatted data.
Take care when an external 5 V is supplied to AVDD. The internal
5 V LDO must be disabled by pulling the AVDD_EN pin low. In
this case, DVDD (1.8 V) is generated from PVDD. It is important
to maintain PVDD > AVDD to prevent the back powering of
PVDD.
The serial interfaces have three main operating modes. The
stereo modes, typically I2S or left justified, are used when there
is a single chip on the interface bus. TDM mode is more flexible
and offers the ability to have multiple chips on the bus.
Using PVDD and External AVDD and DVDD
Stereo Operating Modes—I2S, Left Justified
If using an external AVDD and DVDD source, both the
AVDD_EN and DVDD_EN pins must be pulled low. It is
important to maintain PVDD > AVDD/DVDD to prevent
back powering PVDD.
DVDD must be present for the device to respond to I2C
commands. The device becomes operational ~10 ms after
DVDD is present. PVDD must be at least 5 V for the output
stage to turn on, and must be 6 V for optimal performance.
Stereo modes use both edges of FSYNC to determine the
placement of data. Stereo mode is enabled when SAI_MODE = 0,
and the I2S or left justified format is determined by the SDATA_
FMT register setting.
The I2S or left justified interface formats supports various
BCLK/FSYNC ratios (see Table 13). Sample rates from 8 kHz to
192 kHz are accepted.
POWER-DOWN OPERATION
TDM Operating Mode
The SSM3582 offers several power-down options via the I2C.
Register 0x04 provides multiple options for setting the various
power-down modes.
The TDM operating mode allows multiple chips to connect to a
single serial interface.
The FSYNC signal operates at the desired sample rate. A rising
edge of the FSYNC signal indicates the start of a new frame. For
proper operation, this signal must be one BCLK cycle wide, trans-
itioning on a falling BCLK edge. The MSB of data is present on the
SDATA signal one BCLK cycle later. The SDATA signal is
latched on a rising edge of BCLK.
When set to 1, the SPWDN bit fully powers down the device. In
this case, only the I2C and 1.8 V regulator blocks, if enabled via
the DVDD_EN pin, are kept active.
The SSM3582 monitors both the BCLK and FSYNC pins for
clock presence. When no BCLK is present, the device
automatically powers down all internal circuitry to its lowest
power state. When BCLK returns, the device automatically
powers up following its usual power sequence. To guarantee
click/pop free shutdown, power down the device via the
SPDWN control before clock removal.
Each chip on the TDM bus can occupy 16, 24, 32, 48, or
64 BCLK cycles, set via the TDM_BCLKS control bits. The
maximum number of devices connected to a single TDM bus
depends on the sample rate and number of bits per channel.
The supported combinations of sample rates and bit depths are
described in Table 13.
If enabled, the APWDN_EN bit activates a low power state after
2048 consecutive zero input samples are received. Only the I2C
and digital audio input blocks are kept active.
The maximum bit clock frequency is 49.152 MHz. Using the
TDM16 format, up to eight devices (16 channels) can be connected
to a single TDM interface, and can operate at up to a 96k sample
rate and at 32 bits per channel. See Table 13 for the supported
options at the 48 kHz, 96 kHz, and 192 kHz sample rates. Note
that the interface is slave only, with the bit clock, frame sync,
and data provided to the device.
Individual channels can be powered down using Bits[3:2] in
Register 0x04.
The temperature sense ADC can be powered down using Bit 5
in Register 0x04.
ADDRx pin settings dictate the default TDM slots for each
device, and can be modified using the TDM_SLOT control
register.
Rev. 0| Page 26 of 59
Data Sheet
SSM3582
Table 13. Supported BCLK Rates in MHz1
BCLK/FSYNC Ratio
50
64
100
128
192
200 256
384
512
768
800 1024
2048
4096
Sample
Rate (kHz)
BCLK (MHz)2
8 to 12
N/A
N/A
Yes
Yes
Yes
N/A
N/A
Yes
Yes
Yes
N/A
Yes
Yes
Yes
Yes
N/A
Yes
Yes
Yes
Yes
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
N/A
Yes
Yes
Yes
Yes
N/A
Yes
Yes
Yes
N/A
N/A
Yes
Yes
Yes
N/A N/A
N/A N/A
Yes
Yes
Yes
Yes
Yes
N/A
N/A
N/A
Yes
16 to 24
32 to 48
64 to 96
128 to 192
Yes
Yes
Yes
Yes
N/A
N/A
N/A
N/A
1 Yes means that the specified rate is supported and N/A means not applicable.
2 BCLK = (BCLK/FSYNC ratio) × sample rate.
I2C Control
is encountered. A stop condition occurs when SDA transitions
from low to high while SCL is held high. The timing for the I2C
port is shown in Figure 71.
The SSM3582 supports an I2C-compatible, 2-wire serial bus,
shared across multiple peripherals. Two signals, serial data
(SDA) and serial clock (SCL), carry information between the
SSM3582 and the system I2C master controller. The SSM3582 is
always a slave on the bus, and cannot initiate a data transfer.
Each slave device is identified by a unique address. The address
byte format is shown in Table 14. The address resides in the first
seven bits of the I2C write. The LSB of this byte sets either a read
or write operation. Logic Level 1 corresponds to a read operation,
and Logic Level 0 corresponds to a write operation. For device
address settings, see Table 16.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the SSM3582 immediately
jumps to the idle condition. During a given SCL high period,
issue only one start condition, one stop condition, or a single stop
condition followed by a single start condition. If an invalid sub-
address is issued, the SSM3582 does not issue an acknowledge and
returns to the idle condition. If the user exceeds the highest sub-
address while in automatic-increment mode, one of two actions is
taken.
Table 14. I2C Device Address Byte Format
In read mode, the SSM3582 outputs the highest subaddress register
contents until the master device issues a no acknowledge,
indicating the end of a read. A no acknowledge condition is a
condition in which the SDA line is not pulled low on the ninth
clock pulse on SCL. If the highest subaddress location is reached
while in write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by the
SSM3582, and the device returns to the idle condition.
Bit 7 Bit 6 Bit 5 Bit 4 Bit3
Bit 2
Bit 1
Bit 0
0
0
1
Bit 3 Bit 2 ADDR0 ADDR1 R/W
Both SDA and SCL are open drain, and require pull-up resistors to
the input/output voltage. The SSM3582 operates within the I2C
voltage range of 1.6 V to 3.6 V.
Addressing
Initially, each device on the I2C bus is in an idle state, monitoring
the SDA and SCL lines for a start condition and the proper
address. The I2C master initiates a data transfer by establishing a
start condition, defined by a high to low transition on SDA while
SCL remains high. This start condition indicates that an address/
data stream follows. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus the
Device Address Setting
The device can be set at 16 different I2C addresses using the
ADDR1 and ADDR0 pins, as well as 16 hardware modes.
ADDR1 and ADDR0 are sampled during the start-up procedure.
These pins set the appropriate operating mode, the I2C address,
and the default TDM slots. The ADDRx pins can be set to five
different voltage levels, as defined in Table 15. The ADDRx pins
are referenced to the DVDD rail of the device; connect pull-up
resistors to the internally generated DVDD rail if the regulator
is used.
W
R/ bit), MSB first. The device that recognizes the transmitted
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition. The device address for the SSM3582 is
determined by the state of the ADDRx pins. See the Device
Address Setting section for more details.
Table 15. ADDRx Pin Input Level Mapping
ADDRx State
Level (V)
0
Connected to Ground
W
The R/ bit determines the direction of the data. A Logic 0 on
Connected to Ground Using a 47 kΩ Resistor
Left Floating
Connected to DVDD Using a 47 kΩ Resistor
Connected to DVDD
0.45
0.9
1.35
1.8
the LSB of the first byte means the master writes information to the
peripheral, whereas a Logic 1 means the master reads information
from the peripheral after writing the subaddress and repeating
the start address. A data transfer takes place until a stop condition
Rev. 0| Page 27 of 59
SSM3582
Data Sheet
Table 16. ADDRx Pins to I2C Device Address and TDM Slot Mapping
ADDRx Pin State1
Default TDM Slot
MONO = 1
ADDR0
ADDR1
Device Address
0x10
MONO = 0
1, 2
0
0
1
0
1
0x11
3, 4
2
1
0
0x12
5, 6
3
1
1
0x13
7, 8
4
0
0
1
1
Pull-down
Pull-up
Pull-down
Pull-up
0
1
0
1
Pull-down
Pull-up
Pull-down
Pull-up
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
9, 10
5
6
7
8
11, 12
13, 15
15, 16
17, 18
19, 20
21, 22
23, 24
25, 26
27, 28
29, 30
31, 32
Pull-down
Pull-down
Pull-up
Pull-up
Pull-down
Pull-down
Pull-up
Pull-up
9
10
11
12
13
14
15
16
0x1D
0x1E
0x1F
1 0 = connect to ground, 1 = connect to DVDD. In the case of a pull-down state, connect to ground via a 47 kΩ resistor. In the case of a pull-up state, connect to DVDD
via a 47 kΩ resistor.
I2C Read and Write Operations
W
command, followed by the chip address byte with the R/ set
to 1 (read). This repeated command causes the SSM3582 SDA
to reverse and to begin driving data back to the master. The master
then responds every ninth pulse with an acknowledge pulse to
the SSM3582. Refer to Table 17 for a list of abbreviations in
Figure 72 through Figure 75.
Figure 72 shows the timing of a single-word write operation.
Every ninth clock, the SSM3582 issues an acknowledge by
pulling SDA low.
Figure 73 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The SSM3582 knows to increment its
subaddress register every byte because the requested subaddress
corresponds to a register or memory area with a byte word
length.
Table 17. Abbreviations for Figure 72 Through Figure 75
Symbol
Meaning
Start bit
Stop bit
S
P
AM
Acknowledge (ACK used in Figure 72 through
Figure 75) by master
Acknowledge (ACK used in Figure 72 through
Figure 75) by slave
The timing of a single-word read operation is shown in
W
Figure 74. Note that the first R/ bit is 0, indicating a write
AS
operation, because the subaddress must still be written to set up
the internal address. After the SSM3582 acknowledges the
receipt of the subaddress, the master must issue a repeated start
Rev. 0| Page 28 of 59
Data Sheet
SSM3582
SCL
ACK
ACK
SDA
R/W
START BY
MASTER
FRAME 2
FRAME1
SUBADDRESS BYTE
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
ACK
ACK
STOP BY
MASTER
FRAME 3
FRAME 4
DATA BYTE 1
DATA BYTE 2
Figure 71. I2C Read/Write Timing
START
BIT
IC ADDRESS
(7 BITS)
R/W
= 0
ACK BY
SLAVE
SUBADDRESS
(8 BITS)
ACK BY
SLAVE
DATA BYTE 1
(8 BITS)
STOP
BIT
Figure 72. Single-Word I2C Write Format
S
CHIP ADDRESS,
R/W = 0
A
SUBADDRESS
A
DATA-
WORD 1
A
DATA-
WORD 2
A
S
…
P
S
S
S
Figure 73. Burst Mode I2C Write Format
CHIP
ADDRESS,
R/W = 0
CHIP
ADDRESS,
R/W = 1
S
S
A
SUBADDRESS
SUBADDRESS
A
S
A
DATA
BYTE 1
A
M
DATA
BYTE N
P
S
S
S
Figure 74. Single-Word I2C Read Format
CHIP
ADDRESS,
R/W = 0
CHIP
ADDRESS,
R/W = 1
A
A
S
A
DATA-
WORD 1
A
M
...
P
S
S
S
Figure 75. Burst Mode I2C Read Format
Rev. 0| Page 29 of 59
SSM3582
Data Sheet
slot/sample rate of the device (see Table 18). In this case, the
ANA_GAIN bits are set to 11 and SPWDN is set to 0 by default.
STANDALONE OPERATION
The SSM3582 can be operated in a standalone hardware control
mode without any I2C control. The same ADDRx pins used to
set the I2C device address are used to set the functionality of the
device. In standalone mode, the I2C pins (SCL and SDA) are
inputs and are shorted to DVDD or AGND to set the TDM
In standalone mode, TDM slot selection, mono mode operation,
and sample rate are selected via different pin settings. The
device looks at the FSYNC signal and, if it is a 50% duty cycle,
uses I2S settings. If the FYSNC signal is a pulse, the device uses
TDM settings.
Table 18. Standalone Mode Pin Settings and Functionality
Pin States
Sample Rate
ADDR0
0
1
ADDR1
SDA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCL
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
TDM Slot(s)
MONO
32 kHz to 48 kHz
Open
Open
Open
Open
0
1, 2
3, 4
5, 6
7, 8
9, 10
11, 12
13, 14
15, 16
1, 2
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Pull-down
Pull-up
Open
Open
Open
Open
Open
0
1
Pull-down
Pull-up
Open
Open
Open
Open
Open
0
8 kHz to 12 kHz
32 kHz to 48 kHz
1
Pull-down
Pull-up
Open
Open
Open
Open
Open
0
1
Pull-down
Pull-up
Open
Open
Open
Open
Open
0
8 kHz to 12 kHz
64 kHz to 96 kHz
1, 2
1, 2
3, 4
5, 6
7, 8
9, 10
11, 12
13, 14
15, 16
1, 2
1
2
3
4
5
6
7
8
1
Pull-down
Pull-up
Open
Open
Open
Open
Open
0
1
Pull-down
Pull-up
Open
Open
Open
Open
Open
0
16 kHz to 24 kHz
64 kHz to 96 kHz
1
Pull-down
Pull-up
Open
Open
Open
Open
Open
1
Pull-down
Pull-up
Open
128 kHz to 192 kHz
1, 2
Rev. 0| Page 30 of 59
Data Sheet
SSM3582
MONO MODE
Table 19. Analog Gain Settings and Drive Characteristics
ANA_GAIN[1:0] VOUT
The SSM3582 can be operated in mono mode for driving low
impedance loads. In mono mode, the left and right power stages
can be connected in parallel, as shown in Figure 87. Use caution
when setting up mono mode. For proper operation, any hardware
changes are required along with setting the register. For mono
mode operation, set MONO (Register 0x04, Bit 4) to 1. By default,
this bit is set to 0 for stereo mode. After the bit is set for mono
mode, only the left channel modulator is active and it feeds both
the left and right channel power stages. The OUTL+ and OUTR+
pins are in phase. The OUTL− and OUTR− pins are also in phase.
For mono mode, OUTL+ must be shorted to OUTR+; similarly,
OUTL− must be shorted to OUTR−.
1
0
Gain,
1 V rms (dB)
RMS
(V rms)
Peak-to-Peak (V)
0
0
1
1
0
1
0
1
13
16
19
21
4.47
6.31
8.91
11.20
6.32
8.92
12.60
15.87
POP AND CLICK SUPPRESSION
Pops and clicks are undesirable audible transients generated by
the amplifier system that do not come from the system input
signal. Voltage transients as small as 10 mV can be heard as an
audible pop in the speaker. Voltage transients at the output of audio
amplifiers often occur when shutdown is activated or deactivated.
The SSM3582 has a pop and click suppression architecture that
reduces these output transients, resulting in noiseless activation
and deactivation. Set either mute or power-down before BCLK
is removed to ensure a pop free experience.
In standalone mode, the ADDR0, ADDR1, SCL, and SDA pins
determine the TDM slot. See the Table 18 for the possible TDM
slot configurations in mono mode.
ANALOG AND DIGITAL GAIN
Four different gain settings are available to optimize the dynamic
range of the amplifier in relation to the PVDD supply voltage.
In software mode, the initial 19 dB gain setting can be updated
through the control interface. In standalone mode, the I2C interface
pins set the gain of the device. Table 19 summarizes the gain
settings and load drive characteristics of the amplifier.
TEMPERATURE SENSOR
The SSM3582 contains an 8-bit ADC that measures the die
temperature of the device and is enabled via the TEMP_PWDN bit
in Register 0x04. After the sensor is enabled, the temperature
can be read via the I2C in the TEMP register, Register 0x1B. The
temperature information is stored in Register 0x1B in an 8-bit,
unsigned format. The ADC input range is fixed internally from
−60°C to +195°C. To convert the hexadecimal value to the
temperature (Celsius) value, use the following steps:
The amplifier analog gain is set prior to enabling the device
outputs and must not be changed during operation; a proper
mute/unmute sequence is required to prevent audible transients
between gain settings.
Finer level control is available in the digital domain, with a very
flexible −70 dB to +24 dB, 0.375 dB/step ramp volume control
and selectable nonaliasing clipping point. The digital volume
control also includes a playback level limiter that can be set in
tandem with the battery voltage monitor to prevent the amplifier
from browning out the system when battery level is critically low.
1. Convert the hexadecimal value to decimal and then
subtract 60. For example, if the hexadecimal value is 0x54,
the decimal value is 84.
2. Calculate the temperature using the following equation:
Temperature = Decimal Value − 60
With a decimal value of 84,
Temperature = 84 − 60 = 24°C
Rev. 0| Page 31 of 59
SSM3582
Data Sheet
Table 20. Fault Reporting Registers
Fault Type
Flag Set Condition
Status Reported Register
PVDD Undervoltage (UV)
5 V Regulator UV
Limiter/Gain Reduction Engage
PVDD below <3.6 V
Register 0x18, Bit 7, UVLO_PVDD
Register 0x18, Bit 6, UVLO_VREG
Register 0x19, Bit 3, LIM_EG_L
Register 0x19, Bit 7, LIM_EG_R
Register 0x19, Bit 2, CLIP_L
5 V regulator voltage at AVDD < 3.6 V
Left channel limiter engaged
Right channel limiter engaged
Left channel DAC clipping
Right channel DAC clipping
Left channel output current > 6 A peak
Right channel output current > 6 A peak
Die temperature > 145°C
Clipping, Left Channel
Clipping, Right Channel
Output Overcurrent (OC)
Register 0x19, Bit 6, CLIP_R
Register 0x19, Bit 1, AMP_OC_L
Register 0x19, Bit 5, AMP_OC_R
Register 0x18, Bit 1, OTF
Die Overtemperature (OT)
Die Overtemperature Warning (OTW)
Battery Voltage > VBAT_INF_x
Die temperature > 117°C
Battery voltage PVDD > VBAT_INF_L
Battery voltage PVDD > VBAT_INF_R
Register 0x18, Bit 0, OTW
Register 0x19, Bit 0, BAT_WARN_L
Register 0x19, Bit 4, BAT_WARN_R
When the manual recovery mode is used, the device shuts down
and the recovery must be attempted using the system micro-
controller.
FAULTS AND LIMITER STATUS REPORTING
The SSM3582 offers comprehensive protections against the
faults at the outputs and reporting to help with system design.
The faults listed in Table 20 are reported using the status registers.
VBAT (PVDD) SENSING
The faults listed in Table 20 are reported in Register 0x18 and
Register 0x19 and can be read via I2C by the microcontroller in
the system.
The SSM3582 contains an 8-bit ADC that measures the voltage
of the battery voltage (VBAT/PVDD) supply. The battery voltage
information is stored in Register 0x1A as an 8-bit unsigned
format. The ADC input range is fixed internally at 3.8 V to
16.2 V. To convert the hexadecimal value to the voltage value,
use the following steps:
In the event of a fault occurrence, use Register 0x0B to control
how the device reacts to the faults.
Table 21. Register 0x16, Register 0x17, Fault Recovery
Convert the hexadecimal value to decimal. For example, if the
hexadecimal value is 0xA9, the decimal value is 169.
Status Reported
Register
Fault Type
Flag Set Condition
Calculate the voltage using the following equation:
OTW
The amount of gain
reduction applied if there
is an OTW for left channel
Register 0x16,
Bits[1:0], OTW_
GAIN_L
Voltage = 3.8 V + 12.4 V × Decimal Value/255
With a decimal value of 169,
The amount of gain
reduction applied if there
is an OTW for the right
channel
Register 0x16,
Bits[5:4], OTW_
GAIN_R
Voltage = 3.8 V + 12.4 V × 169/255 = 12.02 V
LIMITER AND BATTERY TRACKING THRESHOLD
CONTROL
Manual
Recovery
Use to attempt manual
recovery in case of a fault
event
Register 0x17,
Bit 7, MRCV
The SSM3582 contains an output limiter that can be used to
limit the peak output voltage of the amplifier. The limiter works
on the rms and peak value of the signal. The limiter threshold,
slope, attack rate, and release rate are programmable using
Register 0x0E, Register 0x0F, and Register 0x10 for the left
channel and Register 0x11, Register 0x12, Register 0x13 for the
right channel. The limiter can be enabled or disabled using
LIM_EN_L, Bits[1:0] in Register 0x0E, Bits[1:0] for the left
channel and the LIM_EN_R bits, Bits[1:0] in Register 0x11, for
the right channel.
Autorecovery
Attempts
When autorecovery from
faults is used, set the
number of attempts using
this bit
Register 0x17,
Bits[5:4], MAX_AR
UV
Recovery can be automatic Register 0x17,
or manual Bit 2, ARCV_UV
Recovery can be automatic Register 0x17,
or manual Bit 1, ARCV_OT
Recovery can be automatic Register 0x17,
or manual Bit 0, ARCV_OC
Die OT
OC
The threshold at which the output is limited is determined by
the LIM_THRES_L bits setting, Bits[7:3] in Register 0x0F for
the left channel, and the LIM_THRES_R bits setting, Bits[7:3]
in Register 0x12 for the right channel. When the ouput signal
level exceeds the set threshold level, the limiter activates and
limits the signal level to the set limit. Below the set threshold,
the output level is not affected.
When the automatic recovery mode is set, the device attempts
to recover itself after the fault event and, in case the fault
persists, then the device sets the fault again. This process
repeats until the fault is resolved.
Rev. 0| Page 32 of 59
Data Sheet
SSM3582
The limiter threshold can be set above the maximum output
voltage of the amplifier. In this case, the limiter allows maximum
peak output; in other words, the output may clip depending on
the power supply voltage and not the limiter.
The limiter offers various active modes that can be set using the
LIM_EN_x bits (Register 0x0E and Register 0x11, Bits[1:0]) and
the VBAT_TRACK_x bit, as shown in Table 22.
When LIM_EN_x = 01, the limiter is enabled. When LIM_EN_x =
10, the limiter mutes the output if VBAT falls below VBAT_INF_x.
When LIM_EN_x = 11, the limiter engages only when the battery
voltage is lower than VBAT_INF_x. When VBAT is greater than
VBAT_INF_x, no limiting occurs. Note that there is hysteresis on
VBAT_INF_x for the limiter disengaging.
The limiter threshold can be set as fixed or to vary with the
battery voltage via the VBAT_TRACK_L bit (Register 0x0E, Bit 2)
for the left channel and VBAT_TRACK_R bit (Register 0x11, Bit 2)
for right channel. When set to fixed, the limiter threshold is fixed
and does not vary with battery voltage. The threshold can be set
from 2 V peak to 16 V peak using the LIM_THRES_x bit (see
Figure 77).
The limiter, when active, reduces the gain of the amplifier. The rate
of gain reduction or attack rate is determined by the LIM_ATR_
x bits (Register 0x0E and Register 0x11, Bits[5:4]). Similarly, when
the signal level drops below the limiter threshold, the gain is
restored. The gain release rate is determined by the LIM_RRT bits
(Register 0x0E and Register 0x11, Bits[7:6]).
When set to a variable threshold, the SSM3582 monitors the
VBAT supply and automatically adjusts the limiter threshold
based on the VBAT supply voltage.
The VBAT supply voltage at which the limiter begins to decrease
the output level is determined by the VBAT inflection point (the
VBAT_INF _L bits (Register 0x10, Bits[7:0]) for the left channel
and VBAT_INF_R bits (Register 0x13, Bits[7:0]) for the right
channel).
LIM_EN_x = 00
VBAT_TRACK_x = 0
AMPLIFIER CLIPPING LEVEL
The VBAT_INF_x point is defined as the battery voltage at
which the limiter either activates or deactivates depending on
the LIM_EN_x mode (see Table 22). When the battery voltage
is greater than VBAT_INF_x, the limiter is not active. When the
battery voltage is less than VBAT_INF_X, the limiter is activated.
The VBAT_INF_x bits can be set from 3.8 V to 16.2 V. The 8-bit
value for the voltage can be calculated using the following
equation:
INPUT LEVEL
Voltage = 3.8 + 12.4 × Decimal Value/255
Figure 76. Limiter Example (LIM_EN_x = 0b0, VBAT_TRACK_x = 0bX)
Convert the decimal value to an 8-bit hexadecimal value and
use it to set the VBAT_INF_x bits.
LIMITER THRESHOLD FIXEDAT SET VALUE
AND DOES NOT TRACK VBAT
The slope bits (Register 0x0F and Register 0x12, Bits[1:0])
determine the rate at which the limiter threshold is lowered
relative to the amount of change in VBAT below the
VBAT_INF_x point.
LIM_THRES_x
The slope is the ratio of the limiter threshold reduction to the
VBAT voltage reduction.
Slope = ꢂLimiter Threshold/ꢂVBAT
The slope ratio can be set from 1:1 to 4:1. This function is useful
to prevent early shutdown under low battery conditions. As the
VBAT voltage falls, the limiter threshold is lowered. This lower
threshold results in the lower output level and therefore helps to
reduce the current drawn from the battery and in turn helps
prevent early shutdown due to low VBAT.
VBAT
Figure 77. Limiter Fixed (LIM_EN_x = 0b01, VBAT_TRACK_x = 0b0)
Table 22. Limiter Modes
LIM_EN_x
VBAT_TRACK_x
Limiter
No
VBAT < VBAT_INF_x
Not applicable
VBAT > VBAT_INF_x
Not applicable
Comments
00
01
01
10
11
11
0 or 1
See Figure 76
0
Fixed
Use the set threshold
Lowers the threshold
Mutes the output
Use the set threshold
Use the set threshold
Use the set threshold
No limiting
See Figure 77
1
Variable
Fixed
See Figure 78 and Figure 79
Not shown
0 or 1
0
1
Fixed
Use the set threshold
Lowers the threshold
See Figure 80 and Figure 81
See Figure 82 and Figure 83
Variable
No limiting
Rev. 0| Page 33 of 59
SSM3582
Data Sheet
LIM_EN_x = 01
VBAT_TRACK_x = 1
LIMITER THRESHOLD FIXEDAT SET VALUE
AND DOES NOT TRACK VBAT
LIM_THRES_x
VBAT > VBAT_INF_x LIMITER
LIMITER THRESHOLD SETTING
LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF_x
CHANGE IN LIM THRESHOLD = N × (VBAT_INF_x – VBAT)
WHERE N = 1 TO 4, SET USING SLOPE BITS IN REG 0x0F, REG 0x12
VBAT
INPUT LEVEL
Figure 81. Limiter Fixed (LIM_EN_x = 0b11, VBAT_TRACK_x = 0b0)
Figure 78. Limiter Fixed (LIM_EN_x = 0b01, VBAT_TRACK_x = 0b1)
LIM_EN_x = 11
VBAT_TRACK_x = 1
LIMITER THRESHOLD STAYS AT
THE SET VALUE FOR VBAT > VBAT_INF_x
VBAT > VBAT_INF_x LIMITER IS NOT ACTIVE
AMPLIFIER CLIPPING LEVEL
VBAT_INF_x
LIM_THRES_x
LIMITER THRESHOLD SETTING
LIMITER THRESHOLD CHANGE FOR VBAT < VBAT_INF
SLOPE
LIMITER THRESHOLD LOWERS
FOR VBAT < VBAT_INF_x
CHANGE IN LIM THRESHOLD = N × (VBAT_INF_x – VBAT)
WHERE N = 1 TO 4, SET USING SLOPE BIT IN REG 0x0F, REG 0x12
INPUT LEVEL
VBAT
Figure 82. Limiter Example (LIM_EN_x = 0b11, VBAT_TRACK_x = 0b1)
Figure 79. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN_x = 0b01,
VBAT_TRACK_x = 0b1)
LIMITER THRESHOLD INACTIVE FOR VBAT > VBAT_INF_x
LIM_EN_x = 11
VBAT_TRACK_x = 0
VBAT_INF_x
SET LIM_THRES_x
AMPLIFIER CLIPPING LEVEL
LIMITER THRESHOLD SETTING
NO CHANGE IN LIM THRESHOLD PER VBAT
SLOPE
LIMITER THRESHOLD LOWERS
FOR VBAT < VBAT_INF_x
VBAT
Figure 83. Output Level vs. VBAT in Limiter Tracking Mode (LIM_EN_x = 0b11,
VBAT_TRACK_x = 0b1)
INPUT LEVEL
Figure 80. Limiter Example (LIM_EN_x = 0b11, VBAT_TRACK_x = 0)
Rev. 0| Page 34 of 59
Data Sheet
SSM3582
HIGH FREQUENCY CLIPPER
OUTPUT MODULATION DESCRIPTION
The SSM3582 uses three level, Σ-Δ output modulation. Each
output can swing from ground to PVDD, and vice versa. Ideally,
when no input signal is present, the output differential voltage is
0 V because there is no need to generate a pulse. In a real-world
situation, noise sources are always present.
The high frequency clipper can be controlled via the
DAC_CLIP_L bits (Register 0x14, Bits[7:0]) and the
DACL_CLIP_R bits (Register 0x15, Bits[7:0]).
These bits determine the clipper threshold, relative to full scale.
When enabled, the clipper digitally clips the signal after the
DAC interpolation.
Due to this constant presence of noise, a differential pulse is
occasionally generated in response to this stimulus. A small
amount of current flows into the inductive load when the
differential pulse is generated. However, typically, the output
differential voltage is 0 V. This feature ensures that the current
flowing through the inductive load is small.
EMI NOISE
The SSM3582 uses a proprietary modulation and spread
spectrum technology to minimize EMI emissions from the
device. The SSM3582 passes FCC Class-B emissions testing
with an unshielded 20 inch cable using ferrite bead-based
filtering. For applications that have difficulty passing FCC
Class-B emission tests, the SSM3582 includes an ultralow EMI
emissions mode that significantly reduces the radiated emissions at
the Class-D outputs, particularly above 100 MHz. Note that
reducing the supply voltage greatly reduces radiated emissions.
When the user sends an input signal, an output pulse is generated
to follow the input voltage. The differential pulse density is
increased by raising the input signal level. Figure 84 depicts
three-level, Σ-Δ output modulation with and without input
stimulus.
OUTPUT = 0V
OUTx+
+5V
0V
+5V
OUTx–
0V
+5V
V
0V
OUT
–5V
OUTPUT > 0V
+5V
OUTx+
OUTx–
0V
+5V
0V
+5V
V
OUT
0V
OUTPUT < 0V
+5V
OUTx+
OUTx–
0V
+5V
0V
0V
V
OUT
–5V
Figure 84. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
Rev. 0| Page 35 of 59
SSM3582
Data Sheet
BOOTSTRAP CAPACITORS
OUTPUT EMI FILTERING
The output stage of the SSM3582 uses a high-side NMOS driver,
rather than a PMOS driver. To generate the gate drive voltage for
the high-side NMOS, a bootstrap capacitor for each output
terminal acts as a floating power supply for the switching cycle. Use
0.22 μF capacitors to connect the appropriate output pin (OUTx )
to the bootstrap pin (BSTx ). For example, connect a 0.22 μF
capacitor between OUTL+ (a left channel, noninverting output)
and BSTL+ for bootstrapping the left channel. Similarly, connect
another 0.22 μF capacitor between the OUTL− and BSTL− pins
for the left channel inverting output.
Additional EMI filtering may be required when the speaker
traces and cables are long and present a significant capacitive
load that can create additional draw from the amplifier. Typical
power ferrites present a significant magnetic hysteresis cycle
that affects THD performance and are not recommended for
high performance designs. The NFZ filter series from Murata,
designed in close collaboration with Analog Devices, Inc.,
provides a closed hysteresis loop similar to an air coil with
minimum impact on performance. Products are available at
upwards of 4 A rms, well suited to this application. A small
capacitor can be added between the output of the filter and
ground to further attenuate very high frequencies. Take care to
ensure the capacitor is properly sized so as not to affect idle
power consumption or efficiency.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low THD, and high PSRR, proper
power supply decoupling is necessary. Noise transients on the
power supply lines are short duration voltage spikes. These spikes
can contain frequency components that extend into the hundreds
of megahertz. The power supply input must be decoupled with
a good quality, low ESL, low ESR bulk capacitor larger than 220 ꢀF.
This capacitor bypasses low frequency noise to the ground
plane. For high frequency decoupling, place 1 ꢀF capacitors
as close as possible to the PVDD pins of the device.
PCB PLACEMENT
Component selection and placement have great influence on
system performance, both measured and subjective. Proper
PVDD layout and decoupling is necessary to reach the specified
level of performance, particularly at the highest power levels.
The placement shown in Figure 85 ensures proper output stage
decoupling for each channel, for minimum supply noise and
maximum separation between channels. Additional bulk
decoupling is necessary to reduce current ripple at low
frequencies, and can be shared between several amplifiers
in a multichannel solution.
BSTL+
0.22µF CAPACITOR
BSTL–
0.22µF CAPACITOR
PVDD DECOUPLING
0.1µF CAPACITOR
DVDD DECOUPLING
0.1µF CAPACITOR
AVDD DECOUPLING
0.1µF CAPACITOR
BSTR+
BSTR–
0.22µF CAPACITOR
0.22µF CAPACITOR
PVDD DECOUPLING
0.1µF CAPACITOR
Figure 85. Recommended Component Placement
Rev. 0| Page 36 of 59
Data Sheet
SSM3582
the amount of noise the amplifier bridges inject in the circuit,
particularly if common ground impedance is significant. Proper
grounding guidelines help improve audio performance, minimize
crosstalk between channels, and prevent switching noise from
coupling into the audio signal.
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply; a poor layout increases voltage drops, consequently
decreasing efficiency. A good practice is to use short, wide PCB
tracks to decrease voltage drops and minimize inductance. For
the lowest dc resistance (DCR) and minimum inductance,
ensure that track widths for the outputs are at least 200 mil for
every inch of length and use 1 oz. or 2 oz. copper.
Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
To maintain high output swing and high peak output power, the
PCB traces that connect the output pins to the load and supply
pins must be as wide as possible; this also maintains the minimum
trace resistances. In addition, good PCB layout isolates critical
analog paths from sources of high interference. Separate high
frequency circuits (analog and digital) from low frequency circuits.
If the system has separate analog and digital ground and power
planes, the analog ground plane must be directly beneath the
analog power plane, and, similarly, the digital ground plane must
be directly beneath the digital power plane. There must be no
overlap between the analog and digital ground planes or between
the analog and digital power planes.
PVDD and PGND carry most of the device current, and must
be properly decoupled with multiple capacitors at the device
pins. To minimize ground bounce, use independent large traces
to carry PVDD and PGND to the power supply, thus reducing
Rev. 0| Page 37 of 59
SSM3582
Data Sheet
REGISTER SUMMARY
Table 23. Register Summary
Reg Name
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
VENDOR
DEVICE1
DEVICE2
REV
Bit 2
Bit 1
Bit 0
Reset RW
0x00 VENDOR_ID
0x01 DEVICE_ID1
0x02 DEVICE_ID2
0x03 REVISION
[7:0]
0x41
0x35
0x82
0x01
R
R
R
R
[7:0]
[7:0]
[7:0]
0x04 POWER_CTRL
0x05 AMP_DAC_CTRL
0x06 DAC_CTRL
0x07 VOL_LEFT_CTRL
[7:0] APWDN_EN
[7:0] DAC_LPM
[7:0] DAC_HV
[7:0]
RESERVED
RESERVED
TEMP_PWDN MONO
DAC_POL_R DAC_POL_L
R_PWDN
L_PWDN
RESERVED
SPWDN
0xA1 R/W
0x8A R/W
0x02 R/W
0x40 R/W
0x40 R/W
0x11 R/W
0x07 R/W
0x00 R/W
0x01 R/W
0xA0 R/W
0x51 R/W
0x22 R/W
0xA8 R/W
0x51 R/W
0x22 R/W
0xFF R/W
0xFF R/W
0x00 R/W
0x30 R/W
EDGE
RESERVED
ANA_GAIN
DAC_FS
DAC_MUTE_R DAC_MUTE_L DAC_HPF
RESERVED
VOL_L
VOL_R
TDM_BCLKS
0x08 VOL_RIGHT_CTRL [7:0]
0x09 SAI_CTRL1
[7:0] RESERVED
BCLK_POL
RESERVED
FSYNC_MODE
SDATA_FMT SAI_MODE
VOL_LINK AUTO_SLOT
0x0A SAI_CTRL2
[7:0] SDATA_EDGE
[7:0]
DATA_WIDTH VOL_ZC_ONLY CLIP_LINK
TDM_SLOT_L
0x0B SLOT_LEFT_CTRL
RESERVED
RESERVED
0x0C SLOT_RIGHT_CTRL [7:0]
TDM_SLOT_R
0x0E LIM_LEFT_CTRL1
0x0F LIM_LEFT_CTRL2
0x10 LIM_LEFT_CTRL3
[7:0]
[7:0]
[7:0]
LIM_RRT_L
LIM_ATR_L
LIM_THRES_L
RESERVED
VBAT_TRACK_L
RESERVED
LIM_EN_L
SLOPE_L
VBAT_INF_L
LIM_LINK
0x11 LIM_RIGHT_CTRL1 [7:0]
0x12 LIM_RIGHT_CTRL2 [7:0]
0x13 LIM_RIGHT_CTRL3 [7:0]
LIM_RRT_R
LIM_ATR_R
LIM_THRES_R
VBAT_TRACK_R
RESERVED
LIM_EN_R
SLOPE_R
VBAT_INF_R
0x14 CLIP_LEFT_CTRL
[7:0]
DAC_CLIP_L
DAC_CLIP_R
0x15 CLIP_RIGHT_CTRL [7:0]
0x16 FAULT_CTRL1
0x17 FAULT_CTRL2
0x18 STATUS1
0x19 STATUS2
0x1A VBAT
[7:0]
RESERVED
OTW_GAIN_R
MAX_AR
RESERVED
OTW_GAIN_L
[7:0] MRCV
RESERVED
RESERVED
RESERVED
ARCV_UV
ARCV_OT
ARCV_OC
OTW
[7:0] UVLO_PVDD UVLO_VREG
OTF
0x00
R
R
R
R
[7:0] LIM_EG_R
CLIP_R
AMP_OC_R
BAT_WARN_R LIM_EG_L
CLIP_L
AMP_OC_L
BAT_WARN_L 0x00
[7:0]
[7:0]
[7:0]
VBAT
TEMP
0x00
0x00
0x1B TEMP
0x1C SOFT_RESET
RESERVED
S_RST
0x00 R/W
Rev. 0| Page 38 of 59
Data Sheet
SSM3582
REGISTER DETAILS
Address: 0x00, Reset: 0x41, Name: VENDOR_ID
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
1
[7:0] VENDOR (R)
Vendor ID
Table 24. Bit Descriptions for VENDOR_ID
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VENDOR
Vendor ID
0x41
R
Address: 0x01, Reset: 0x35, Name: DEVICE_ID1
7
6
5
4
3
2
1
0
0
0
1
1
0
1
0
1
[7:0] DEVICE1 (R)
Device ID 1
Table 25. Bit Descriptions for DEVICE_ID1
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DEVICE1
Device ID 1
0x35
R
Address: 0x02, Reset: 0x82, Name: DEVICE_ID2
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
0
[7:0] DEVICE2 (R)
Device ID 2
Table 26. Bit Descriptions for DEVICE_ID2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
DEVICE2
Device ID 2
0x82
R
Address: 0x03, Reset: 0x01, Name: REVISION
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:0] REV (R)
Revision Code
Table 27. Bit Descriptions for REVISION
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
REV
Revision Code
0x1
R
Rev. 0| Page 39 of 59
SSM3582
Data Sheet
Address: 0x04, Reset: 0xA1, Name: POWER_CTRL
7
6
5
4
3
2
1
0
1
0
1
0
0
0
0
1
[7] APWDN_EN (R/W)
[0] SPWDN (R/W)
Auto Power-Down Enable
0: Auto Power-Down Feature Disabled.
1: Auto Power-Down Feature Enabled.
Software Master Power-Down
0: Normal Operation.
1: Software Master Power-Down.
[6] RESERVED
[1] RESERVED
[5] TEMP_PWDN (R/W)
[2] L_PWDN (R/W)
Temperature Sensor Power-down
0: Temperature Sensor On.
1: Temperature Sensor Powered Down.
Left Channel Power-Down
0: Left Channel Powered on.
1: Left Channel Powered Down.
[4] MONO (R/W)
[3] R_PWDN (R/W)
Mono Mode Selection
0: Mono Mode Enabled.
1: Stereo Mode Enabled.
Right Channel Power-Down
0: Right Channel Powered On.
1: Right Channel Powered Down.
Table 28. Bit Descriptions for POWER_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
APWDN_EN
Automatic Power-Down Enable.
0x1
R/W
0
1
Automatic power-down feature disabled.
Automatic power-down feature enabled.
Reserved.
6
5
RESERVED
0x0
0x1
R
TEMP_PWDN
Temperature Sensor Power-Down.
Temperature sensor on.
R/W
0
1
Temperature sensor powered down.
Mono Mode Selection.
4
3
2
MONO
0x0
0x0
0x0
R/W
R/W
R/W
0
1
Mono mode enabled.
Stereo mode enabled.
R_PWDN
L_PWDN
Left Channel Power-Down.
Right channel powered on.
Right channel powered down.
Left Channel Power-Down.
Left channel powered on.
Left channel powered down.
Reserved.
0
1
0
1
1
0
RESERVED
SPWDN
0x0
0x1
R
Software Master Power-Down
Normal operation.
R/W
0
1
Software master power-down.
Rev. 0| Page 40 of 59
Data Sheet
SSM3582
Address: 0x05, Reset: 0x8A, Name: AMP_DAC_CTRL
7
6
5
4
3
2
1
0
1
0
0
0
1
0
1
0
[7] DAC_LPM (R/W)
DAC low power mode
0: DAC Low Power Mode Disabled.
1: DAC Low Power Mode Enabled.
[1:0] ANA_GAIN (R/W)
Amplifier analog gain select
0: +13dB (6.3 V peak)
1: +16 dB (8.9 V peak)
10: +19 dB (12.6 V peak)
11: +21 dB (16 V peak)
[6] RESERVED
[5] DAC_POL_R (R/W)
Right Channel DAC output polarity
control
[2] RESERVED
[3] EDGE (R/W)
0: Normal behavior.
1: Invert the DAC output.
Edge rate control
0: Normal operation.
1: Low EMI mode operation.
[4] DAC_POL_L (R/W)
Left Channel DAC output polarity
control
0: Normal behavior.
1: Invert the DAC output.
Table 29. Bit Descriptions for AMP_DAC_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
DAC_LPM
DAC Low Power Mode.
0x1
R/W
0
1
DAC low power mode disabled.
DAC low power mode enabled.
Reserved.
6
5
RESERVED
0x0
0x0
R
DAC_POL_R
Right Channel DAC Output Polarity Control.
Normal behavior.
R/W
0
1
Invert the DAC output.
Left Channel DAC Output Polarity Control.
Normal behavior.
4
3
DAC_POL_L
EDGE
0x0
0x1
R/W
R/W
0
1
Invert the DAC output.
Edge Rate Control.
0
1
Normal operation.
Low EMI mode operation.
Reserved.
2
RESERVED
ANA_GAIN
0x0
0x2
R
[1:0]
Amplifier Analog Gain Select.
+13 dB (6.3 V peak).
R/W
0
1
+16 dB (8.9 V peak).
10 +19 dB (12.6 V peak).
11 +21 dB (16 V peak).
Rev. 0| Page 41 of 59
SSM3582
Data Sheet
Address: 0x06, Reset: 0x02, Name: DAC_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
[7] DAC_HV (R/W)
[2:0] DAC_FS (R/W)
Hard volume control
0: Soft volume ramping.
1: No volume ramping.
DAC sample rate select
0: 8kHz to 12 kHz.
1: 16kHz to 24 kHz.
10: 32kHz to 48 kHz.
11: 64kHz to 96 kHz.
100: 128kHz to 192 kHz.
101: 48kHz to 72 kHz.
[6] DAC_MUTE_R (R/W)
DAC right channel mute
0: Right channel unmuted.
1: Right channel muted.
[3] RESERVED
[5] DAC_MUTE_L (R/W)
DAC left channel mute
0: Left channel unmuted.
1: Left channel muted.
[4] DAC_HPF (R/W)
DAC high pass filter
0: DAC high pass filter disabled.
1: DAC high pass filter enabled.
Table 30. Bit Descriptions for DAC_CTRL
Bits
Bit Name
Settings
Description
Reset
Access
7
DAC_HV
Hard Volume Control.
Soft Volume Ramping.
No Volume Ramping.
0x0
0x0
0x0
0x0
R/W
0
1
6
5
4
DAC_MUTE_R
DAC_MUTE_L
DAC_HPF
DAC Right Channel Mute.
Right Channel Unmuted.
Right Channel Muted.
DAC Left Channel Mute.
Left Channel Unmuted.
Left Channel Muted.
R/W
R/W
R/W
0
1
0
1
DAC High-Pass Filter.
0
1
DAC High-Pass Filter Disabled.
DAC High-Pass Filter Enabled.
Reserved.
3
RESERVED
DAC_FS
0x0
0x2
R
[2:0]
DAC Sample Rate Select.
8 kHz to 12 kHz.
R/W
0
1
16 kHz to 24 kHz.
10 32 kHz to 48 kHz.
11 64 kHz to 96 kHz.
100 128 kHz to 192 kHz.
101 48 kHz to 72 kHz.
Rev. 0| Page 42 of 59
Data Sheet
SSM3582
Address: 0x07, Reset: 0x40, Name: VOL_LEFT_CTRL
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
[7:0] VOL_L (R/W)
Left channel volume
0x00: +24 dB.
0x01: +23.625 dB.
0x02: ...
...
0xFD: -70.875 dB.
0xFE: -71.25 dB.
0xFF: Mute.
Table 31. Bit Descriptions for VOL_LEFT_CTRL
Bits
Bit Name
Settings
Description
Left Channel Volume
0x00 +24 dB
0x01 +23.625 dB
0x02
Reset
Access
[7:0]
VOL_L
0x40
R/W
…
0x3F +0.375 dB
0x40 0 dB
0x41 −0.375 dB
0x42
…
0xFD −70.875 dB
0xFE −71.25 dB
0xFF Mute
Address: 0x08, Reset: 0x40, Name: VOL_RIGHT_CTRL
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
[7:0] VOL_R (R/W)
Right channel volume
0x00: +24 dB.
0x01: +23.625 dB.
0x02: ...
...
0xFD: -70.875 dB.
0xFE: -71.25 dB.
0xFF: Mute.
Table 32. Bit Descriptions for VOL_RIGHT_CTRL
Bits
Bit Name
Settings
Description
Right Channel Volume
0x00 +24 dB
0x01 +23.625 dB
0x02
Reset
Access
[7:0]
VOL_R
0x40
R/W
…
0x3F +0.375 dB
0x40 0 dB
0x41 −0.375 dB
0x42
…
0xFD −70.875 dB
0xFE −71.25 dB
0xFF Mute
Rev. 0| Page 43 of 59
SSM3582
Data Sheet
Address: 0x09, Reset: 0x11, Name: SAI_CTRL1
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
1
[7] RESERVED
[0] SAI_MODE (R/W)
Serial interface mode select
0: Stereo modes.
[6] BCLK_POL (R/W)
BCLK polarity control
0: Use rising edge to capture SDATA.
1: Use falling edge to capture SDATA.
1: TDM modes.
[1] SDATA_FMT (R/W)
Serial data format
0: I2S (delay by 1) Format.
1: Left Justified Format.
[5:3] TDM_BCLKS (R/W)
TDM slot width select
0: 16 bits.
1: 24 bits.
[2] FSYNC_MODE (R/W)
10: 32 bits.
FSYNC mode
11: 48 bits.
100: 64 bits.
0: Stereo: low FSYNC is left channel;
TDM: Frame start on falling edge.
1: Stereo: high FSYNC is left channel;
TDM: Frame start on rising edge.
Table 33. Bit Descriptions for SAI_CTRL1
Bits
Bit Name
RESERVED
BCLK_POL
Settings
Description
Reset
Access
R
7
Reserved.
0x0
0x0
6
BCLK Polarity Control
R/W
0
1
Use Rising Edge to Capture SDATA
Use Falling Edge to Capture SDATA
TDM Slot Width Select
16 Bits
[5:3]
TDM_BCLKS
0x2
R/W
0
1
24 Bits
10 32 Bits
11 48 Bits
100 64 Bits
2
1
0
FSYNC_MODE
SDATA_FMT
SAI_MODE
FSYNC Mode
0x0
0x0
0x1
R/W
R/W
R/W
0
1
Stereo: Low FSYNC is Left Channel; TDM: Frame Start on Falling Edge
Stereo: High FSYNC is Left Channel; TDM: Frame Start on Rising Edge
Serial Data Format
I2S (Delay by 1) Format
Left Justified Format
Serial Interface Mode Select
Stereo Modes
0
1
0
1
TDM Modes
Rev. 0| Page 44 of 59
Data Sheet
SSM3582
Address: 0x0A, Reset: 0x07, Name: SAI_CTRL2
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
[7] SDATA_EDGE (R/W)
SDATA edge delay mode
0: Normal operation.
[0] AUTO_SLOT (R/W)
Automatic TDM slot selection
0: Set TDM slots using TDM_SLOTx
Bits.
1: Half cycle delay of SDATA.
1: Set TDM slots automatically using
ADDRx pin settings.
[6:5] RESERVED
[4] DATA_WIDTH (R/W)
Audio input data width
0: 24 bits.
[1] VOL_LINK (R/W)
Channel volume link
0: Use independent VOL_L and VOL_R
controls.
1: 16 bits.
1: Link both channels to VOL_L control.
[3] VOL_ZC_ONLY (R/W)
Volume control zero-crossing detection
0: Allow volume to change at all times.
1: Only change volume when zero-crossing
is detected (may be different per-channel)
[2] CLIP_LINK (R/W)
High frequency clipper link
0: Use Independent Left and Right DAC_CLIP_x
Bits.
1: Link Both Channels to DAC_CLIP_L
Bits.
Table 34. Bit Descriptions for SAI_CTRL2
Bits Bit Name Settings Description
SDATA Edge Delay Mode
Reset
Access
7
SDATA_EDGE
0x0
R/W
0
1
Normal Operation
Half Cycle Delay of SDATA
Reserved
[6:5] RESERVED
0x0
0x0
R
4
DATA_WIDTH
Audio Input Data Width
24 Bits
R/W
0
1
16 Bits
3
VOL_ZC_ONLY
Volume Control Zero-Crossing Detection
Allow Volume to Change at All Times
0x0
R/W
0
1
Only Change Volume When Zero-Crossing is Detected (May Be Different Per
Channel)
2
1
0
CLIP_LINK
VOL_LINK
AUTO_SLOT
High Frequency Clipper Link
0x1
0x1
0x1
R/W
R/W
R/W
0
1
Use Independent Left and Right DAC_CLIP_x Bits
Link Both Channels to DAC_CLIP_L Bits
Channel Volume Link
0
1
Use Independent VOL_L and VOL_R Controls
Link Both Channels to VOL_L Control
Automatic TDM Slot Selection
0
1
Set TDM Slots Using TDM_SLOT_x Bits
Set TDM Slots Automatically Using the ADDRx Pin Settings
Rev. 0| Page 45 of 59
SSM3582
Data Sheet
Address: 0x0B, Reset: 0x00, Name: SLOT_LEFT_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:5] RESERVED
[4:0] TDM_SLOT_L (R/W)
Left channel slot selection
Table 35. Bit Descriptions for SLOT_LEFT_CTRL
Bits
[7:5]
[4:0]
Bit Name
Settings
Description
Reset
Access
R
RESERVED
TDM_SLOT_L
Reserved
0x0
0x0
Left Channel Slot Selection
R/W
Address: 0x0C, Reset: 0x01, Name: SLOT_RIGHT_CTRL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:5] RESERVED
[4:0] TDM_SLOT_R (R/W)
Right channel slot selection
Table 36. Bit Descriptions for SLOT_RIGHT_CTRL
Bits
[7:5]
[4:0]
Bit Name
Settings
Description
Reset
0x0
Access
R
RESERVED
TDM_SLOT_R
Reserved
Right Channel Slot Selection
0x1
R/W
Address: 0x0E, Reset: 0xA0, Name: LIM_LEFT_CTRL1
7
6
5
4
3
2
1
0
1
0
1
0
0
0
0
0
[7:6] LIM_RRT_L (R/W)
Left limiter release rate
0: 3200 ms/dB.
[1:0] LIM_EN_L (R/W)
Left limiter mode
0: Limiter off.
1: 1600 ms/dB.
1: Limiter on.
10: 1200 ms/dB.
11: 800 ms/dB.
10: Mute output if VBAT<VBAT_INF_L.
11: Limiter on only if VBAT<VBAT_INF_L.
[5:4] LIM_ATR_L (R/W)
Left limiter attack rate
0: 120 us/dB.
[2] VBAT_TRACK_L (R/W)
Left threshold battery tracking
0: Fixed Limiter Threshold Set by LIM_THRES_L
Bits in Register0x0F.
1: 60 us/dB.
10: 30 us/dB.
11: 20 us/dB.
1: Ramp Down Limiter Threshold when
VBAT<VBAT_INF_L using SLOPE_x
bits in Register 0x0F.
[3] RESERVED
Table 37. Bit Descriptions for LIM_LEFT_CTRL1
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
LIM_RRT_L
Left Limiter Release Rate
3200 ms/dB
0x2
R/W
0
1
1600 ms/dB
10 1200 ms/dB
11 800 ms/dB
[5:4]
LIM_ATR_L
RESERVED
Left Limiter Attack Rate
120 ꢀs/dB
60 ꢀs/dB
0x2
0x0
R/W
0
1
10 30 ꢀs/dB
11 20 ꢀs/dB
Reserved
3
R
Rev. 0| Page 46 of 59
Data Sheet
SSM3582
Bits
Bit Name
Settings
Description
Reset
Access
2
VBAT_TRACK_L
Left Threshold Battery Tracking
0x0
R/W
0
Fixed Limiter Threshold Set by LIM_THRES Bits in Register 0x0F
1
Ramp Down Limiter Threshold when VBAT < VBAT_INF_L using SLOPE_x bits
in Register 0x0F.
[1:0]
LIM_EN_L
Left Limiter Mode
Limiter Off
0x0
R/W
0
1
Limiter On
10 Mute output if VBAT < VBAT_INF_L.
11 Limiter on only if VBAT < VBAT_INF_L.
Address: 0x0F, Reset: 0x51, Name: LIM_LEFT_CTRL2
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
1
[7:3] LIM_THRES_L (R/W)
Left Limiter Threshold
0: 16 V peak.
1: 15.5 V peak.
2: 15 V peak.
...
29: 3 V peak.
30: 2.5 V peak.
31: 2 V peak.
[1:0] SLOPE_L (R/W)
Left Limiter Threshold Reduction
Slope
0: 1:1 Threshold:VBAT reduction.
1: 2:1 Threshold:VBAT reduction.
10: 3:1 Threshold:VBAT reduction.
11: 4:1 Threshold:VBAT reduction.
[2] RESERVED
Table 38. Bit Descriptions for LIM_LEFT_CTRL2
Bits
Bit Name
Settings
Description
Reset
Access
[7:3]
LIM_THRES_L
Left Limiter Threshold
16 V peak
0xA
R/W
0
1
2
3
4
5
6
7
8
9
15.5 V peak
15 V peak
14.5 V peak
14 V peak
13.5 V peak
13 V peak
12.5 V peak
12 V peak
11.5 V peak
10 11 V peak
11 10.5 V peak
12 10 V peak
13 9.5 V peak
14 9.25 V peak
15 9 V peak
16 8.75 V peak
17 8.5 V peak
18 8.25 V peak
19 8 V peak
20 7.5 V peak
Rev. 0| Page 47 of 59
SSM3582
Data Sheet
Bits
Bit Name
Settings
Description
Reset
Access
21 7 V peak
22 6.5 V peak
23 6 V peak
24 5.5 V peak
25 5 V peak
26 4.5 V peak
27 4 V peak
28 3.5 V peak
29 3 V peak
30 2.5 V peak
31 2 V peak
Reserved
2
RESERVED
SLOPE_L
0x0
0x1
R
[1:0]
Left Limiter Threshold Reduction Slope
R/W
0
1
1:1 Threshold: VBAT Reduction
2:1 Threshold: VBAT Reduction
10 3:1 Threshold: VBAT Reduction
11 4:1 Threshold: VBAT Reduction
Address: 0x10, Reset: 0x22, Name: LIM_LEFT_CTRL3
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
0
[7:0] VBAT_INF_L (R/W)
Left limiter battery voltage inflection
point
Table 39. Bit Descriptions for LIM_LEFT_CTRL3
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VBAT_INF_L
Left Limiter Battery Voltage Inflection Point
0x22
R/W
Rev. 0| Page 48 of 59
Data Sheet
SSM3582
Address: 0x11, Reset: 0xA8, Name: LIM_RIGHT_CTRL1
7
6
5
4
3
2
1
0
1
0
1
0
1
0
0
0
[7:6] LIM_RRT_R (R/W)
Right limiter release rate
0: 3200 ms/dB.
[1:0] LIM_EN_R (R/W)
Right limiter mode
0: Limiter off.
1: 1600 ms/dB.
1: Limiter on.
10: 1200 ms/dB.
11: 800 ms/dB.
10: Mute output if VBAT<VBAT_INF_R.
11: Limiter on only if VBAT<VBAT_INF_R.
[5:4] LIM_ATR_R (R/W)
Right limiter attack rate
0: 120 us/dB.
[2] VBAT_TRACK_R (R/W)
Right threshold battery tracking
0: Fixed Limiter Threshold set by LIM_THRES_R
Bits in Register 0x12.
1: 60 us/dB.
10: 30 us/dB.
11: 20 us/dB.
1: Ramp down limiter threshold when
VBAT<VBAT_INF_R using SLOPE_R
Bits in Register 0x12.
[3] LIM_LINK (R/W)
Channel limiter link
0: Use independent left and right channel
limiters.
1: Link both channels to one limiter
(use left limiter controls)
Table 40. Bit Descriptions for LIM_RIGHT_CTRL1
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
LIM_RRT_R
Right Limiter Release Rate
3200 ms/dB
0x2
R/W
0
1
1600 ms/dB
10 1200 ms/dB
11 800 ms/dB
[5:4]
LIM_ATR_R
Right Limiter Attack Rate
120 ꢀs/dB
60 ꢀs/dB
0x2
R/W
0
1
10 30 ꢀs/dB
11 20 ꢀs/dB
3
2
LIM_LINK
Channel Limiter Link
0x1
0x0
R/W
R/W
0
1
Use Independent Left and Right Channel Limiters
Link Both Channels to one Limiter (Use Left Limiter Controls)
Right Threshold Battery Tracking
VBAT_TRACK_R
0
1
Fixed Limiter Threshold set by LIM_THRES_R Bits in Register 0x12
Ramp down limiter threshold when VBAT < VBAT_INF_R using SLOPE_R Bits
in Register 0x12.
[1:0]
LIM_EN_R
Right Limiter Mode
Limiter Off
0x0
R/W
0
1
Limiter On
10 Mute output if VBAT < VBAT_INF_R.
11 Limiter on only if VBAT < VBAT_INF_R.
Rev. 0| Page 49 of 59
SSM3582
Data Sheet
Address: 0x12, Reset: 0x51, Name: LIM_RIGHT_CTRL2
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
1
[7:3] LIM_THRES_R (R/W)
Right limiter threshold
0: 16 Vp.
1: 15.5 Vp.
2: 15 Vp.
[1:0] SLOPE_R (R/W)
Right limiter threshold reduction slope
0: 1:1 Threshold:VBAT reduction.
1: 2:1 Threshold:VBAT reduction.
10: 3:1 Threshold:VBAT reduction.
11: 4:1 Threshold:VBAT reduction.
...
29: 3 Vp.
30: 2.5 Vp.
31: 2 Vp.
[2] RESERVED
Table 41. Bit Descriptions for LIM_RIGHT_CTRL2
Bits
Bit Name
Settings
Description
Reset
0xA
Access
[7:3]
LIM_THRES_R
Right Limiter Threshold
16 V p-p
R/W
0
1
2
3
4
5
6
7
8
9
15.5 V p-p
15 V p-p
14.5 V p-p
14 V p-p
13.5 V p-p
13 V p-p
12.5 V p-p
12 V p-p
11.5 V p-p
10 11 V p-p
11 10.5 V p-p
12 10 V p-p
13 9.5 V p-p
14 9.25 V p-p
15 9 V p-p
16 8.75 V p-p
17 8.5 V p-p
18 8.25 V p-p
19 8 V p-p
20 7.5 V p-p
21 7 V p-p
22 6.5 V p-p
23 6 V p-p
24 5.5 V p-p
25 5 V p-p
26 4.5 V p-p
27 4 V p-p
28 3.5 V p-p
29 3 V p-p
30 2.5 V p-p
31 2 V p-p
Rev. 0| Page 50 of 59
Data Sheet
SSM3582
Bits
2
Bit Name
RESERVED
SLOPE_R
Settings
Description
Reset
Access
R
Reserved
0x0
0x1
[1:0]
Right Limiter Threshold Reduction Slope
1:1 Threshold: VBAT Reduction
2:1 Threshold: VBAT Reduction
R/W
0
1
10 3:1 Threshold: VBAT Reduction
11 4:1 Threshold: VBAT Reduction
Address: 0x13, Reset: 0x22, Name: LIM_RIGHT_CTRL3
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
0
[7:0] VBAT_INF_R (R/W)
Right limiter battery voltage inflection
point
Table 42. Bit Descriptions for LIM_RIGHT_CTRL3
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VBAT_INF_R
Right Limiter Battery Voltage Inflection Point
0x22
R/W
Address: 0x14, Reset: 0xFF, Name: CLIP_LEFT_CTRL
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
[7:0] DAC_CLIP_L (R/W)
Left DAC high frequency clip value
0xFF: Clip to 0 dB.
0xFE: Clip to 255/256.
0xFD: Clip to 254/256.
0xFC: ...
0x00: Clip to 1/256.
Table 43. Bit Descriptions for CLIP_LEFT_CTRL
Bits
Bit Name
Settings
Description
Left DAC High Frequency Clip Value
0xFF Clip to 0 dB
Reset
Access
[7:0]
DAC_CLIP_L
0xFF
R/W
0xFE Clip to 255/256
0xFD Clip to 254/256
0xFC
…
0x00 Clip to 1/256
Rev. 0| Page 51 of 59
SSM3582
Data Sheet
Address: 0x15, Reset: 0xFF, Name: CLIP_RIGHT_CTRL
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
[7:0] DAC_CLIP_R (R/W)
Right DAC high frequency clip value
0xFF: Clip to 0 dB.
0xFE: Clip to 255/256.
0xFD: Clip to 254/256.
0xFC: ...
0x00: Clip to 1/256.
Table 44. Bit Descriptions for CLIP_RIGHT_CTRL
Bits
Bit Name
Settings
Description
Right DAC High Frequency Clip Value
0xFF Clip to 0 dB
Reset
Access
[7:0]
DAC_CLIP_R
0xFF
R/W
0xFE Clip to 255/256
0xFD Clip to 254/256
0xFC
…
0x00 Clip to 1/256
Address: 0x16, Reset: 0x00, Name: FAULT_CTRL1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[1:0] OTW_GAIN_L (R/W)
Left channel over temperature warning
gain reduction
[5:4] OTW_GAIN_R (R/W)
Right channel over temperature warning
gain reduction
0: No gain reduction.
1: 1.5 dB gain reduction.
10: 3 dB gain reduction.
11: 5.625 dB gain reduction.
0: No gain reduction.
1: 1.5 dB gain reduction.
10: 3 dB gain reduction.
11: 5.625 dB gain reduction.
[3:2] RESERVED
Table 45. Bit Descriptions for FAULT_CTRL1
Bits
[7:6]
[5:4]
Bit Name
Settings
Description
Reset
0x0
Access
R
RESERVED
OTW_GAIN_R
Reserved
Right Channel Over Temperature Warning Gain Reduction
No Gain Reduction
0x0
R/W
0
1
1.5 dB Gain Reduction
10 3 dB Gain Reduction
11 5.625 dB Gain Reduction
Reserved
[3:2]
[1:0]
RESERVED
0x0
0x0
R
OTW_GAIN_L
Left Channel Over Temperature Warning Gain Reduction
R/W
0
1
No Gain Reduction
1.5 dB Gain Reduction
10 3 dB Gain Reduction
11 5.625 dB Gain Reduction
Rev. 0| Page 52 of 59
Data Sheet
SSM3582
Address: 0x17, Reset: 0x30, Name: FAULT_CTRL2
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
[7] MRCV (W)
[0] ARCV_OC (R/W)
Engage manual fault recovery attempt
0: No manual recovery attempt.
1: One manual recovery attempt.
Overcurrent fault auto recovery control
0: Auto Recovery Enabled.
1: Manual recovery using MRCV Bit.
[6] RESERVED
[1] ARCV_OT (R/W)
Over temperature fault auto recovery
control
0: Auto Recovery Enabled.
1: Manual recovery using MRCV Bit.
[5:4] MAX_AR (R/W)
Maximum Automatic Recovery Attempts
0: 1 attempt.
1: 3 attempts.
10: 7 attempts.
[2] ARCV_UV (R/W)
11: Unlimited attempts.
Undervoltage Fault Auto Recovery
Control
0: Auto Recovery Enabled.
1: Manual recovery using MRCV Bit.
[3] RESERVED
Table 46. Bit Descriptions for FAULT_CTRL2
Bits
Bit Name
Settings
Description
Reset
Access
W
7
MRCV
Engage Manual Fault Recovery Attempt
0x0
0x0
0x3
6
RESERVED
MAX_AR
Reserved
R
[5:4]
Maximum Automatic Recovery Attempts
R/W
0
1
1 Attempt
3 Attempts
10 7 Attempts
11 Unlimited Attempts
Reserved
3
2
RESERVED
ARCV_UV
0x0
0x0
R
Undervoltage Fault Automatic Recovery Control
Automatic Recovery Enabled
R/W
0
1
Manual Recovery Using MRCV Register
Over Temperature Fault Automatic Recovery Control
Automatic Recovery Enabled
1
0
ARCV_OT
ARCV_OC
0x0
0x0
R/W
R/W
0
1
Manual Recovery Using MRCV Bit
Over Current Fault Automatic Recovery Control
Automatic Recovery Enabled
0
1
Manual Recovery Using MRCV Bit
Rev. 0| Page 53 of 59
SSM3582
Data Sheet
Address: 0x18, Reset: 0x00, Name: STATUS1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] UVLO_PVDD (R)
[0] OTW (R)
PVDD under-voltage fault condition
0: PVDD OK.
1: PVDD undervoltage fault condition.
Over temperature warning condition
0: No over temperature warning.
1: Over temperature warning.
[6] UVLO_VREG(R)
[1] OTF(R)
Regulator under-voltage fault condition
0: No undervoltage fault for AVDD regulator.
1: Undervoltage fault for AVDD regulator.
Over temperature fault condition
0: No over temperature fault.
1: Over temperature fault.
[5:2] RESERVED
Table 47. Bit Descriptions for STATUS1
Bits
Bit Name
Settings
Description
Reset
Access
7
UVLO_PVDD
PVDD Undervoltage Fault Condition
PVDD OK
0x0
R
0
1
PVDD undervoltage fault condition
6
UVLO_VREG
Regulator Undervoltage Fault Condition
No undervoltage fault for AVDD regulator
Undervoltage fault for AVDD regulator
Reserved
0x0
R
0
1
[5:2]
1
RESERVED
OTF
0x0
0x0
R
R
Over Temperature Fault Condition
No overtemperature fault
0
1
Overtemperature fault
0
OTW
Over Temperature Warning Condition
No overtemperature warning
Overtemperature warning
0x0
R
0
1
Address: 0x19, Reset: 0x00, Name: STATUS2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] LIM_EG_R (R)
[0] BAT_WARN_L (R)
Right limiter gain reduction engaged
0: Limiter Gain Reduction Right Off.
1: Limiter Gain Reduction Right On.
Battery voltage warning for left channel
(VBAT<VBAT_INF_x)
0: VBAT > VBAT_INF_L left channel.
1: VBAT < VBAT_INF_L left channel.
[6] CLIP_R (R)
Right channel DAC clipping detected
0: No clipping right channel.
1: Clipping right channel.
[1] AMP_OC_L (R)
Left channel amplifier overcurrent
condition
0: No over current left channel.
1: Over current left channel.
[5] AMP_OC_R (R)
Right channel amplifier overcurrent
condition
[2] CLIP_L (R)
0: No over current right channel.
1: Over current right channel.
Left channel DAC clipping detected
0: No clipping left channel.
1: Clipping left channel.
[4] BAT_WARN_R (R)
Battery voltage warning for right channel
(VBAT<VBAT_INF_x)
0: VBAT > VBAT_INF_R right channel.
1: VBAT < VBAT_INF_R right channel.
[3] LIM_EG_L (R)
Left limiter gain reduction engaged
0: Limiter Gain Reduction Left Off.
1: Limiter Gain Reduction Left On.
Table 48. Bit Descriptions for STATUS2
Bits
Bit Name
Settings
Description
Reset
Access
7
LIM_EG_R
Right limiter gain reduction engaged
Limiter Gain Reduction Right Off.
Limiter Gain Reduction Right On.
0x0
R
0
1
Rev. 0| Page 54 of 59
Data Sheet
SSM3582
Bits
Bit Name
Settings
Description
Reset
Access
6
CLIP_R
Right channel DAC clipping detected
No clipping right channel.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
0
1
Clipping right channel.
5
4
3
2
1
0
AMP_OC_R
BAT_WARN_R
LIM_EG_L
Right channel amplifier overcurrent condition
No overcurrent right channel.
R
R
R
R
R
R
0
1
Overcurrent right channel.
Battery voltage warning for right channel (VBAT < VBAT_INF_x)
VBAT > VBAT_INF_R right channel.
VBAT < VBAT_INF_R right channel.
Left limiter gain reduction engaged
Limiter Gain Reduction Left Off.
Limiter Gain Reduction Left On.
Left channel DAC clipping detected
No clipping left channel.
0
1
0
1
CLIP_L
0
1
Clipping left channel.
AMP_OC_L
BAT_WARN_L
Left channel amplifier overcurrent condition
No over current left channel.
0
1
Over current left channel.
Battery voltage warning for left channel (VBAT < VBAT_INF_x)
VBAT > VBAT_INF_L left channel.
VBAT < VBAT_INF_L left channel.
0
1
Address: 0x1A, Reset: 0x00, Name: VBAT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VBAT (R)
Battery voltage readback
Table 49. Bit Descriptions for VBAT
Bits
Bit Name
Settings
Description
Battery Voltage Readback
Reset
Access
[7:0]
VBAT
0x0
R
Address: 0x1B, Reset: 0x00, Name: TEMP
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] TEMP (R)
Temperature Sensor Readout
Table 50. Bit Descriptions for TEMP
Bits Bit Name Settings Description
Reset
0x0
Access
[7:0] TEMP
Temperature Sensor Readout. The actual temperature in degrees Celsius is TEMP –
60 decimal.
R
Rev. 0| Page 55 of 59
SSM3582
Data Sheet
Address: 0x1C, Reset: 0x00, Name: SOFT_RESET
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] S_RST (W)
Full software reset
0: Normal operation.
1: Perform full software reset.
Table 51. Bit Descriptions for SOFT_RESET
Bits
[7:1]
0
Bit Name
RESERVED
S_RST
Settings
Description
Reset
Access
Reserved
0x0
0x0
R
Full Software Reset
Normal Operation
W
0
1
Perform Full Software Reset
Rev. 0| Page 56 of 59
Data Sheet
SSM3582
TYPICAL APPLICATION CIRCUIT
Figure 86 shows a typical application circuit for a stereo output. Figure 87 shows a typical application circuit for a mono output.
+1.8V
(DVDD)
PVDD
+4.5V TO +16V
SEE DEVICE ADDRESS
SETTING SECTION
C9
470µF
C4
0.1µF
C5
C6
C7
C8
10µF 0.1µF
10µF 470µF
+1.8V
C1
0.1uF
C2
10µF
C3
10µF
PVDD
R2
2.2kꢀ
R1
2.2kꢀ
SCL
2
I C
REG
AVDD
REG
DVDD
2
PVDD
I C
SDA
BSTL+
OPTIONAL
C10
0.22µF
FB1
FB2
BCLK
FSYNC
SDATA
FULL
Σ-∆
2
TDM
I S/TDM
OUTL+
OUTL–
BRIDGE
POWER
STAGE
2
VOLUME
4ꢀ/8ꢀ
DAC
CLASS-D
I S
MODULATOR
INPUT
C14
220pF
C15
220pF
C11
0.22µF
BSTL–
BSTR+
PVDD
FB1/FB2: MURATA FERRITE BEAD NFZ2MSM181
OPTIONAL
FB3
C12
0.22µF
FULL
Σ-∆
OUTR+
OUTR–
BRIDGE
POWER
STAGE
FB4
4ꢀ/8ꢀ
VOLUME
DAC
CLASS-D
MODULATOR
C16
220pF
C17
220pF
C13
0.22µF
BSTR–
SSM3582
FB3/FB3: MURATA FERRITE BEAD NFZ2MSM181
AGND
PGND
ADDRx PIN SETUP OPTIONS
DVDD_EN PIN SETUP OPTIONS
DVDD_EN
OPEN
GND
ADDRx
ADDRx
DVDD_EN
AVDD
ADDRx
ADDRx
DVDD
DVDD
AVDD_EN PIN SETUP OPTIONS
AVDD_EN
47kꢀ TO GND
47kꢀ TO DVDD DVDD
47kꢀ
ADDRx
AVDD_EN
PVDD
47kꢀ
Figure 86. Typical Application Circuit for Stereo Output
Rev. 0| Page 57 of 59
SSM3582
Data Sheet
+1.8V
(DVDD)
PVDD
+4.5V TO +16V
SEE DEVICE ADDRESS
SETTING SECTION
C9
470µF
C4
0.1µF
C5
C6
C7
C8
+1.8V
10µF 0.1µF
10µF 470µF
C1
0.1uF
C2
10µF
C3
10µF
PVDD
R2
2.2kꢀ
R1
2.2kꢀ
SCL
SDA
2
I C
REG
AVDD
REG
DVDD
2
PVDD
I C
BSTL+
OPTIONAL
C10
0.22µF
FB1
FB2
BCLK
FSYNC
SDATA
FULL
Σ-∆
2
TDM
I S/TDM
OUTL+
OUTL–
BRIDGE
POWER
STAGE
2
VOLUME
2ꢀ/3ꢀ
DAC
CLASS-D
I S
MODULATOR
INPUT
C14
220pF
C15
220pF
C11
0.22µF
BSTL–
BSTR+
PVDD
FB1/FB2: MURATA FERRITE BEAD NFZ2MSM181
C12
0.22µF
FULL
Σ-∆
OUTR+
OUTR–
BRIDGE
POWER
STAGE
VOLUME
DAC
CLASS-D
MODULATOR
C13
0.22µF
BSTR–
SSM3582
AGND
PGND
ADDRx PIN SETUP OPTIONS
DVDD_EN PIN SETUP OPTIONS
DVDD_EN
OPEN
GND
ADDRx
ADDRx
DVDD_EN
AVDD
ADDRx
ADDRx
DVDD
DVDD
AVDD_EN PIN SETUP OPTIONS
AVDD_EN
47kꢀ TO GND
47kꢀ TO DVDD DVDD
47kꢀ
ADDRx
AVDD_EN
PVDD
47kꢀ
Figure 87. Typical Application Circuit for Mono Output
Rev. 0| Page 58 of 59
Data Sheet
SSM3582
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
30
40
1
0.50
BSC
*
4.70
EXPOSED
PAD
4.60 SQ
4.50
10
21
11
20
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 88. 40-Lead Lead Free Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
SSM3582BCPZ
SSM3582BCPZRL
SSM3582BCPZR7
EVAL-SSM3582Z
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
40-Lead Lead Free Chip Scale Package [LFCSP]
40-Lead Lead Free Chip Scale Package [LFCSP]
40-Lead Lead Free Chip Scale Package [LFCSP]
Evaluation Board
CP-40-7
CP-40-7
CP-40-7
1 Z = RoHs Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13399-0-4/16(0)
Rev. 0| Page 59 of 59
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