SW201-803Q [ADI]
SGL POLE SGL THROW SWITCH;
| 型号： | SW201-803Q |
| 厂家： | 
ADI |
| 描述： | SGL POLE SGL THROW SWITCH |
| 文件： | 总5页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Tuesday, Feb 26, 2008 3:28 PM /
Quad SPST JFET
Analog Switch
SW201
1.0
SCOPE
This specification documents the detail requirements for space qualified product manufactured on
Analog Devices, Inc.'s QML certified line per MIL-PRF-38535 Level V except as modified herein.
The manufacturing flow described in the STANDARD SPACE LEVEL PRODUCTS PROGRAM
brochure is to be considered a part of this specification. http://www.analog.com/aerospace
This data sheet specifically details the space grade version of this product. A more detailed
operational description and a complete data sheet for commercial product grades can be found at
www.analog.com/SW201
2.0
Part Number. The complete part number(s) of this specification follow:
Part Number
SW201-803Q
SW201-813Q
Description
Quad SPST JFET Analog Switch
Radiation Tested, Quad SPST JFET Analog Switch
2.1
Letter Descriptive designator Case Outline (Lead Finish per MIL-PRF-38535)
GDIP1-T16 16-Lead ceramic dual-in-line package (CERDIP)
Case Outline.
Q
2.1 Figure 1 - Terminal connections.
2.1.1 SW201 Logic Table:
Control Logic
Logic Input
Switch State
ON
0
ASD0011315
Rev. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license
is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of
their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2008 Analog Devices, Inc. All rights reserved.
SW201
3.0
Absolute Maximum Ratings. (TA = 25°C, unless otherwise noted)
Operating Temperature Range ................................................................... -55°C to +125°C
Storage Temperature Range....................................................................... -65°C to +150°C
Power Dissipation.....................................................................................................900mW
Lead Temperature (Soldering, 60 sec.) .....................................................................+300°C
Maximum Junction Temperature (TJ).......................................................................+150°C
V+ Supply to V- Supply..................................................................................................36V
V+ Supply to Ground......................................................................................................36V
Logic Input Voltage Range ........................................................... (-4V or V-) to V+ Supply
Analog Input Voltage
Continuous................................................................V- Supply to V+ Supply +20V
1% Duty Cycle and Driving all 4 inputs
with 500μS pulse ............................................V- Supply –15V to V+ Supply +20V
Maximum Current Through Any Pin...........................................................................30mA
3.1
4.0
Thermal Characteristics:
Thermal Resistance, Q (cerdip) Package
Junction-to-Case (ΘJC) = 29°C/W Max
Junction-to-Ambient (ΘJA) = 91°C/W Max
Electrical Table:
TABLE I
Parameter
See notes at end of table
Symbol
Conditions
VS = ±15V Unless otherwise
specified
Sub-
group
Limit Limit Units
Min
Max
Positive Supply Current
Negative Supply Current
Ground Current
I+
I-
All channels OFF or ON
All Channels OFF or ON
All Channels OFF or ON
1
2,3
1
9
13.5
6.0
8.5
4
mA
2,3
1
IG
2,3
1
6
Logic “0” Input Current
Logic “1” Input Current (Note 1)
“ON” Resistance
IIL
5
μA
2,3
1
10
5
IIH
2,3
1
10
80
110
15
15
20
RON
VA = -10V to 10V; IS = 1mA
Ω
2,3
1
%
ΔRON vs. VA
ΔRON
VA ≤ 10V, IS = 1mA
VA = 0V, ID = 100μA
RON Match Between Switches
(Note 3)
RON
(Match)
1
2,3
1
Analog Current Range (Note 2)
IA
VS = ±10V
IS = 1mA
10
7
mA
V
2,3
1,2,3
Analog Voltage Range (Note 2)
VA
±10
ASD0011315 Rev. E | Page 2 of 5
SW201
4.0
Electrical Table: (Cont’d)
Parameter
Symbol
Conditions
VS = ±15V Unless otherwise
specified
Sub-
group
Limit Limit Units
See notes at end of table
Min
Max
Source Current “OFF” Condition
Drain Current “OFF” Condition
IS(OFF)
VS = +10V, VD = -10V
VS = -10V, VD = +10V
VS = +10V, VD = -10V
VS = -10V, VD = +10V
VS = VD = ±10V
1
2
60
2
nA
2
1
2
60
2
ID(OFF)
1
2
60
2
1
2
60
2
Leakage Current “ON”
Condition
ID(ON)
+
1
2
IS(ON)
100
0.8
Logic “0” Input Voltage
Logic “1” Input Voltage
Turn-On-Time
VIL
VIH
1,2,3
1,2,3
9
V
V
2
tON
500
400
nS
VS = -5V, RL = 1KΩ, CL = 13pF
Turn-Off-Time
tOFF
9
Break-Before-Make Time
tON-tOFF
9
50
Table I notes:
1 Current Tested at VIN = 2V (worst case condition)
2 VA, VIH, VIL is verified by leakage and RON tests.
3 RON Match specified as a percentage of Raverage where Raverage = RON1 + RON2 + RON3 + RON4
4
ASD0011315 Rev. E | Page 3 of 5
SW201
4.1
Electrical Test Requirements:
Table II
Test Requirements
Subgroups (in accordance
with MIL-PRF-38535,
Table III)
Interim Electrical Parameters
Final Electrical Parameters
Group A Test Requirements
1
1, 2, 3 1/ 2/
1, 2, 3, 9
Group C end-point electrical parameters 1 2/
Group D end-point electrical parameters
Group E end-point electrical parameters
1
1
1/ PDA applies to Subgroup 1. Exclude delta's from PDA.
2/ See Table III for delta parameters. See Table I for test conditions.
4.2
Table III. Burn-in test delta limits.
Table III
TEST
TITLE
ENDPOINT
LIMIT
DELTA
LIMIT
UNITS
ohm
RON
80
±15
5.0
Life Test/Burn-In Circuit:
5.1
5.2
5.3
HTRB is not applicable for this drawing.
Burn-in is per MIL-STD-883 Method 1015 test condition C.
Steady state life test is per MIL-STD-883 Method 1005.
ASD0011315 Rev. E | Page 4 of 5
SW201
Rev
A
B
Description of Change
Date
July 12, 2000
20-Dec-01
Initiate
Update web site address. Under max ratings change TJ to TJ. For RON
conditions, change ID = 1mA to IS = 1mA. RON (Match), change
subgroups from 1,2 to 2,3. Break before make specification must a
minimum. Add subgroup 9 to Group A requirements on Table II.
Change BI circuit from condition A to Condition C.
C
Delete subgroups 4, 5, 6 from Table II, they are not used in Table I.
Change paragraph 5.2 from cond. B to Cond. C (BI circuit not changed).
Update web address. Delete burn-in circuit
Feb. 21, 2002
D
E
June 20, 2003
Feb. 22,2008
Update header/footer & add to 1.0 Scope description.
© 2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective
companies.
Printed in the U.S.A.
02/08
ASD0011315 Rev. E | Page 5 of 5
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