AD5517ABC-2 [ADI]
IC SERIAL INPUT LOADING, 14-BIT DAC, PBGA74, 12 X 12 MM, LFBGA-74, Digital to Analog Converter;
| 型号： | AD5517ABC-2 |
| 厂家： | 
ADI |
| 描述： | IC SERIAL INPUT LOADING, 14-BIT DAC, PBGA74, 12 X 12 MM, LFBGA-74, Digital to Analog Converter 输入元件 转换器 |
| 文件： | 总10页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
16-Channel 14-Bit
Voltage-Output DAC
a
Preliminary Technical Data AD5517-1/AD5517-2/AD5517-3*
FEATURES
GE NE RAL D E SC RIP TIO N
High Integration: 16-channel DAC in 12x12 m m 2 LFBGA
Guaranteed Monotonic
T he AD5517 is a 16-channel voltage-output 14-bit DAC. T he
selected DAC register is written to via the 3-wire serial inter-
face. DAC selection is accomplished via address bits A3-A0.
14-bit resolution is achieved by fine adjusment in Mode 2. T he
serial interface operates at clock rates up to 20 MHz and is
compatible with standard SPI, MICROWIRE and DSP inter-
face standards. T he output voltage range is fixed at ±2.5 V
(AD5517-1), ±5 V (AD5517-2) and ±10 V (AD5517-3). Ac-
cess to the feedback resistor in each channel is provided via
Low Pow er, SPITM, MICROWIRETM and DSP-Com patible
3-Wire Serial Interface
Output Im pedance 0.5Ω
Output Voltage Range
± 2.5 V (AD5517-1)
± 5 V (AD5517-2)
± 10V (AD5517-3)
Asynchronous RESET facility
Daisy-Chaining Option
RFB0 to RBF15 pins.
T he device is operated with AVcc = 5 V ± 5%, DVcc = 2.7 V
to 5.25 V, VSS = -4.75 V to -12 V and VDD = 4.75 V to 12 V
and requires a stable 2.5 V reference on REF_IN.
Tem perature Range -40oC to +85oC
APPLICATIONS
Level Setting
Instrum entation
P RO D UC T H IGH LIGH TS
1. 16 14-bit DACs in one package, guaranteed monotonic.
Autom atic Test Equipm ent
Optical Netw orks
Industrial Control System s
Data Acquisition
2. T he AD5517 is available in a 74-lead LFBGA package with
a body size of 12mm by 12mm.
FUNC TIO NAL BLO C K D IAGRAM
Low Cost I/ O
V
SS
V
DV
CC
AV
CC
DD
REF_IN
V
BIAS
R
FB
R
OFFS
R
0
FB
AD5517
-
V
OUT
0
DAC
DAC
+
R
OFFS
R
FB
RESET
BUSY
R
1
FB
-
V
OUT
1
+
ANALOG
CALIBRATION
LOOP
R
OFFS
R
FB
R 14
FB
DACGND
AGND
-
DAC
DAC
V
14
OUT
+
R
R
OFFS
FB
DGND
R
15
FB
-
V
15
OUT
INTERFACE
CONTROL
LOGIC
+
DCEN
MODE2
POWER-DOWN
LOGIC
7-BIT BUS
SCLK
D
IN
D
OUT
PD
SYNC
*Protected by U.S. Patent Nos. 5,684,481 and 5,969,657; other patents pending.
SP I and Q SP I are T rademarks of Motorola, Inc.
MICRO WIRE is a T rademark of National Semiconductor Corporation.
REV. PrA 2/01
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 2000
PRELIMINARY TECHNICAL DATA
AD5517-1/AD5517-2/AD5517-3 SPECIFICATIONS
(V = 4.75 V to 12 V, V = -4.75 V to -12 V; AV = 4.75 V to 5.25 V; DV = 2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V;
DD
SS
CC
CC
REF_IN = 2.5 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
Param eter1
A Version2
Units
Conditions/Com m ents
DAC DC PERFORMANCE
Resolution
14
Bits
Integral Nonlinearity (INL)
Differential Nonlinearity(DNL)
Bipolar Zero Error
Positive Fullscale Error
Negative Fullscale Error
±8
±1
TBD
TBD
TBD
LSB max
LSB max
LSB max
LSB max
LSB max
Mode1 Operation
±0.5 LSB typ, Monotonic; Mode2
VOLT AGE REFERENCE
REF_IN
Nominal Input Voltage
Input Voltage Range3
Input Current
2.5
2.375/2.625
±1
V
V min/max
µA max
< 1 nA typ
ANALOG OUT PUT S (VOUT 0-15)
Output T emperature Coefficient3,4
DC Output Impedance3
Output Range5
10
0.5
ppm/°C typ
Ω typ
AD5516-1
AD5516-2
±2.5
±5
±10
5
100
10
-70
-70
120
V typ
V typ
V typ
kΩ min
pF max
mA typ
dB typ
dB typ
µV max
100 µA output load
100 µA output load
100 µA output load
AD5516-3
Resistive Load3,6
Capacitive Load3,6
Short-Circuit Current3
DC Power-Supply Rejection Ratio3
VDD = 10 V ± 5%
VSS = -10 V ± 5%
DC Crosstalk3
DIGIT AL INPUT S3
Input Current
±10
0.8
0.4
2.4
2.0
200
10
µA max
V max
V max
V min
V min
mV typ
pF max
±5 µA typ
Input Low Voltage
DVCC = 5 V ± 5%
DVCC = 3 V ± 10%
DVCC = 5 V ± 5%
DVCC = 3 V ± 10%
Input High Voltage
Input Hysteresis (SCLK and SYNC)
Input Capacitance
3
DIGIT AL OUT PUT S (BUSY, DOUT
Output Low Voltage, DVCC = 5V
Output High Voltage, DVCC = 5V
Output Low Voltage, DVCC = 3V
Output High Voltage, DVCC = 3V
)
0.4
4.0
0.4
2.4
±1
V max
V min
V max
V min
Sinking 200 µA
Sourcing 200 µA
Sinking 200 µA
Sourcing 200 µA
DCEN = 0
High Impedance Leakage Current (D OUT only)
µA max
High Impedance Output Capacitance (D OUT only)
15
pF typ
DCEN = 0
Power-Supply Voltages
VDD
VSS
AVCC
+4.75/+12
-4.75/-12
+4.75/+5.25
+2.7/+5.25
V min/max
V min/max
V min/max
V min/max
DVCC
Power-Supply Currents7
IDD
ISS
AICC
7.5
7.5
16.5
1.5
115
mA max
mA max
mA max
mA max
mW typ
5 mA typ. All channels Fullscale
5 mA typ. All channels Fullscale
13 mA typ
1 mA typ
VDD = 5 V, VSS = -5 V
DICC
Power Dissipation7
N OT ES:
1See T erminology
2A Version: Industrial temperature range -40°C to +85°C; typical at +25°C.
3Guaranteed by design and characterization, not production tested.
4AD780 as reference for the AD5517.
5Output range is restricted from VSS + 2 V to VDD - 2 V
6Ensure that you do not exceed T j(max). See Maximum ratings.
7Outputs Unloaded.
Specifications subject to change without notice
–2–
REV. PrA
PRELIMINARY TECHNICAL DATA
AD5517-1/AD5517-2/AD5517-3
(V = 4.75V to 12V, V = -4.75V to -12V; AV = 4.75V to 5.25V; DV = 2.7V to 5.25V; AGND = DGND =
DD
SS
CC
CC
AC Characteristics
DACGND = 0V; REF_IN = 2.5 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
P aram eter1,2
A Version3
Units
Conditions/
Com m ents
Output Voltage Settling T ime4
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
20
0.85
1
5
1
µs max
100 pF, 5 kΩ Load Full Scale change
V/µs typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)1/2 typ
1 LSB change around major carry
0.2
400
Output Noise Spectral Density @ 1kHz
N OT ES:
1See T erminology
2Guaranteed by design and characterization, not production tested
3A version: Industrial temperature range -40°C to +85°C
4T imed from the end of a write sequence
Specifications subject to change without notice
(V = 4.75 V to 12 V, V = -4.75 V to -12 V; AV = 4.75 V to 5.25 V; DV = 2.7 V to 5.25 V;
AGND = DGND = DACGND = 0 V; All specifications TMIN to TMAX unless otherwise noted.)
DD
SS
CC
CC
Timing Characteristics
Lim it at TMIN, TMAX
(A Version)
P aram eter1,2,3
Units
Conditions/Com m ents
fUPDATE1
fUPDATE2
fCLKIN
t1
t2
t3
t4
t5
50
900
20
20
20
10
5
kHz max
kHz max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
DAC Update Rate (Mode 1)
DAC Update Rate (Mode 2)
SCLK Frequency
SCLK High Pulse Width
SCLK Low Pulse Width
SYNC Falling Edge to SCLK Falling Edge Setup T ime
DIN Setup T ime
5
0
DIN Hold T ime
t6
t7
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High T ime (Stand-Alone Mode)
Minimum SYNC High T ime (Daisy-Chain Mode)
BUSY Rising Edge to SYNC Falling Edge
18th SCLK Falling Edge to SYNC Falling Edge (Stand-Alone Mode)
SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
SCLK Rising Edge to DOUT Valid (Daisy-Chain Mode)
RESET Pulse Width
10
400
10
200
10
20
20
t7MODE2
t8MODE1
t9MODE2
t10
4
t11
t12
N OT ES
1See T iming Diagrams in Figures 1 and 2.
2Guaranteed by design and characterization, not production tested.
3All input signals are specified with tr = tf = 5ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2
4T his is measured with the load circuit of Figure 3.
SE RIAL INTE RFAC E TIMING D IAGRAMS
1
2
17
t1
18
SC LK
SYNC
t2
t6
t7
t3
t9
t4
M O D E 2
t5
B it0
B it17
DIN
t8
M O D E 1
B U SY
t12
R ES ET
Figure 1. Serial Interface Tim ing Diagram
–3–
REV. PrA
PRELIMINARY TECHNICAL DATA
AD5517-1/AD5517-2/AD5517-3
SCLK
t10
t2
t1
t7
MODE2
t6
t3
SYNC
t4
t5
Bit17
Bit0
Bit17'
Bit0'
D
IN
Input Word for Device N+1
Input Word for Device N
t11
Bit17
D
Bit0
OUT
t8
MODE1
UNDEFINED
Input Word for Device N
BUSY
Figure 2. Daisy-Chaining Tim ing Diagram
I
200uA
OL
TO
OUTPUT
PIN
V
V
or
OH (MIN)
OL (MAX)
C
L
50pF
I
200uA
OH
Figure 3. Load Circuit for DOUT Tim ing Specifications
ABSO LUTE MAXIMUM RATINGS*
(T A = +25°C unless other wise noted)
Operating T emperature Range
Industrial ..............................................-40°C to +85°C
Storage T emperature Range......................-65°C to +150°C
Junction T emperature (T J max)..............................+150°C
74-lead LFBGA Package, θJA T hermal Impedance....41°C/W
Reflow Soldering
Peak T emperature................................................220°C
T ime at Peak T emperature.......................10 sec to 40 sec
N OT ES:
VDD to AGND................................................-0.3 V to +17 V
VSS to AGND.................................................+0.3 V to -17 V
AVCC to AGND, DACGND.............................-0.3 V to +7 V
DVCC to DGND..............................................-0.3 V to +7 V
Digital Inputs to DGND......................-0.3 V to DVCC + 0.3 V
Digital Outputs to DGND...................-0.3 V to DVCC + 0.3 V
REF_IN to AGND, DACGND.........................-0.3 V to +7 V
VOUT 0-15 to AGND........................VSS - 0.3 V to VDD + 0.3 V
AGND to DGND........................................-0.3 V to + 0.3 V
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only, and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2T ransient currents of up to 100mA will not cause SCR latch-up
O RD ERING GUID E
Output
Voltage Span
P ackage
Option
Model
Function
AD5517ABC-1
AD5517ABC-2
AD5517ABC-3
16 DACs
16 DACs
16 DACs
±2.5 V
±5 V
±10 V
74-lead LFBGA
74-lead LFBGA
74-lead LFBGA
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5517 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. PrA
PRELIMINARY TECHNICAL DATA
AD5517-1/AD5517-2/AD5517-3
P IN C O NFIGURATIO N
3 6 8
4 5 7 9 10 11
1
2
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
K
L
K
L
2
3
4
6
8
1
5
7
9 10 11
AD 5517 74-lead LFBGA Ball Configur ation
LFBGA
Num ber
Ball
Nam e
LFBGA
Num ber
Ball
Nam e
LFBGA
Num ber
Ball
Nam e
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C6
N/C
N/C
C10
C11
D1
AVCC1
N/C
RFB0
DACGND
AVCC2
N/C
VOUT 1
N/C
AGND1
PD
VOUT 2
RFB1
AGND2
RFB14
RFB2
RFB15
VOUT 14
RFB13
VOUT 3
VOUT 15
VOUT 13
VOUT 12
RFB3
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
RFB12
RFB11
RFB4
VOUT 5
RFB5
N/C
VSS2
VSS1
VOUT 10
VOUT 9
RFB10
RFB9
VOUT 11
N/C
VOUT 6
RFB6
VOUT 7
N/C
VDD2
VDD1
RFB7
VOUT 8
RFB8
RESET
BUSY
DGND
DVCC
DOUT
DIN
SYNC
N/C
N/C
N/C
N/C
N/C
DCEN
DGND
DGND
N/C
N/C
SCLK
N/C
D2
D10
D11
E1
E2
E10
E11
F1
F2
F10
F11
G1
G2
G10
G11
H1
H2
H10
H11
J1
J2
J6
REF_IN
VOUT 0
DACGND
N/C
L10
L11
VOUT 4
N/C
N/C
–5–
REV. PrA
PRELIMINARY TECHNICAL DATA
AD5517-1/AD5517-2/AD5517-3
P IN FUNCTIO N D ESCRIP TIO N
P in
Function
AGND(1-2)
AVCC (1-2)
VDD (1-2)
VSS (1-2)
DGND
Analog GND pins.
Analog supply pins. Voltage range from 4.75 V to 5.25 V.
VDD supply pins. Voltage range from 4.75 V to 12 V.
VSS supply pins. Voltage range from -4.75 V to -12 V.
Digital GND pins.
DVCC
Digital supply pins. Voltage range from 2.7 V to 5.25 V.
DACGND
REF_IN
Reference GND supply for all 16 DACs.
Reference input voltage for all 16 DACs.
VOUT (0-15)
RFB (0-15)
Analog output voltages from the 16 DAC channels.
Feedback Resistors. Access to the inverting inputs of the 16 output amplifiers allows remote
sensing in force/sense applications. For nominal output voltage range connect each RFB to it’s
corresponding VOUT
.
SYNC
Active Low Input. T his is the Frame Synchronisation signal for the serial interface. While SYNC
is low, data is transferred in on the falling edge of SCLK.
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. T his
operates at clock speeds up to 20 MHz.
DIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
DOUT
Serial Data Output. DOUT can be used for daisy-chaining a number of devices together or for
reading back the data in the shift register for diagnostic purposes. Data is clocked out on D OUT
on the rising edge of SCLK and is valid on the falling edge of SCLK.
Active High Control Input. T his pin is tied high to enable Daisy-Chain Mode.
Active Low Control Input. T his resets all DAC registers to their mid-scale value.
Active High Control Input. All DACs go into power-down mode when this pin is high. T he
DAC outputs go into a high-impedance state and the power dissipation drops to T BD.
Active Low Output. T his signal tells the user that the analog calibration loop is active. It goes
low during conversion. T he duration of the pulse on BUSY determines the maximum DAC
DCEN1
RESET2
PD
BUSY
update rate, fUPDAT E
.
N OT ES:
1Internal Pull-down device on this logic input. T herfore it can be left floating
and will default to a logic low condition.
2Internal Pull-up device on this logic input. T herfore it can be left floating
and will default to a logic high condition.
–6–
REV. PrA
PRELIMINARY TECHNICAL DATA
AD5517-1/AD5517-2/AD5517-3
TE RMINO LO GY
Analog Cr osstalk
T his the area of the glitch transferred to the output (VOUT ) of
one DAC due to a full-scale change in the output (VOUT ) of
another DAC. T he area of the glitch is expressed in nV-secs.
Integr al Nonlinear ity (INL)
T his is a measure of the maximum deviation from a straight
line passing through the endpoints of the DAC transfer func-
tion. It is expressed in LSBs.
D igital Feeedthr ough
T his is a measure of the impulse injected into the analog out-
puts from the digital control inputs when the part is not being
written to, i.e. SYNC is high. It is specified in nV-secs and is
measured with a worst-case change on the digital input pins,
e.g. from all 0s to all 1s and vice versa.
D iffer ential Nonlinear ity (D NL)
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any
two adjacent codes. A specified DNL of ±1 LSB maximum
ensures monotonicity.
O utput Noise Spectr al D ensity
Bipolar Zer o E r r or
T his is a measure of internally generated random noise. Ran-
dom noise is characterized as a spectral density (voltage per
root Hertz). It is measured in nV/(Hz)1/2.
Bipolar zero error is the deviation of the DAC output from the
ideal midscale of 0 V. It is measured with 10...00 loaded to the
DAC. It is expressed in LSBs.
P ositive Full-Scale E r r or
T his is the error in the DAC output voltage with all 1s loaded
to the DAC. Ideally the DAC output voltage, with all 1s
loaded to the DAC registers, should be REF_IN (AD5517-1),
2 REF_IN (AD5517-2) and 4 REF_IN (AD5517-3). It is
expressed in LSBs.
Negative Full-Scale E r r or
T his is the error in the DAC output voltage with all 0s loaded
to the DAC. Ideally the DAC output voltage, with all 0s
loaded to the DAC registers, should be -REF_IN (AD5517-
1), -2 REF_IN (AD5517-2) and -4 REF_IN (AD5517-3). It is
expressed in LSBs.
O utput Tem per atur e Coefficient
T his is a measure of the change in analog output with changes
in temperature. It is expressed in ppm/°C.
D C P ower -Supply Rejection Ratio
DC Power-Supply Rejection Ratio (PSRR) is a measure of the
change in analog output for a change in supply voltage (VDD
and VSS). It is expressed in dBs. VDD and VSS are varied ± 5%.
D C Cr osstalk
T his the DC change in the output level of one DAC at mid-
scale in response to a full-scale code change (all 0s to all 1s
and vice versa) and output change of another DAC. It is ex-
pressed in µV.
O utput Settling Tim e
T his is the time taken from when the last data bit is clocked
into the DAC until the output has settled to within ± 0.5 LSB
of it’s final value.
D igital-to-Analog Glitch Im pulse
T his is the area of the glitch injected into the analog output
when the code in the DAC register changes state. It is speci-
fied as the area of the glitch in nV-secs when the digital code is
changed by 1 LSB at the major carry transition (011...11 to
100...00 or 100...00 to 011...11).
D igital Cr osstalk
T his is the glitch impulse transferred to the output of one
DAC at mid-scale while a full-scale code change (all 1s to all
0s and vice versa) is being written to another DAC. It is ex-
pressed in nV-secs.
–7–
REV. PrA
PRELIMINARY TECHNICAL DATA
Typical Performance Characteristics –
AD5517-1/AD5517-2/AD5517-3)
TPC 1. Typical DNL plot
TPC 2. Typical INL plot
TPC 3. INL Error and DNL Error vs.
Tem perature
TPC 4. Bipolar Zero Error and
Fullscale Error vs. Tem perature
TPC 5. VOUT vs. Tem perature
TPC 6. VOUT Source and Sink
Capability
TPC 7. Full-Scale Settling Tim e
TPC 8. Exiting Powerdown to
Fullscale
TPC 9. Major Code Transition Glitch
Im pulse
–8–
REV. PrA
PRELIMINARY TECHNICAL DATA
AD5517-1/AD5517-2/AD5517-3
FUNC TIO NAL D E SC RIP TIO N
D aisy-Chain Mode (D CE N = 1)
T he AD5517 consists of 16 14-bit DACs in a single package.
A single reference input pin (REF_IN) is used to provide a 2.5
V reference for all 16 DACs. T o update a DAC's output volt-
age an 18-bit word is written to the part via the 3-wire serial
interface. T his 18-bit word consists of 2 mode bits, 4 address
bits and 12 data bits as shown in Figure 4. Once the serial
write is complete the selected DAC converts the code. T he
output amplifiers translate the 0 - 2.5 V DAC output range to
In Daisy-Chain Mode the internal gating on SCLK is disabled.
T he SCLK is continuously applied to the input shift register
when SYNC is low. If more than 18 clock pulses are applied,
the data ripples out of the shift register and appears on the
DOUT line. T his data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
DIN input on the next device in the chain, a multi-device inter-
face is constructed. 18 clock pulses are required for each device
in the system. T herefore, the total number of clock cycles must
equal 18N where N is the total number of devices in the chain.
See the timing diagram in Figure 2.
give a ±5 V range at the output pins VOUT 0 to VOUT 15.
SE RIAL INTE RFAC E
DCEN (Daisy-Chain Enable) determines whether the serial
interface is in Daisy-Chain Mode or Stand-Alone Mode. In
both modes SYNC is an edge-triggered input that acts as a
frame synchronization signal and chip enable. Data can only
be transferred into the device while SYNC is low. T o start the
serial data transfer, SYNC should be taken low observing the
minimum SYNC falling to SCLK falling edge setup time, t3.
When the serial transfer to all devices is complete, SYNC
should be taken high. T his prevents any further data being
clocked into the input shift register. A burst clock containing
the exact number of clock cycles may be used and SYNC taken
high some time later. After the rising edge of SYNC, data is
automatically transferred from each device’s input shift register
to the addressed DAC. BUSY goes low indicating that conver-
sion has started. All SCLK pulses will be ignored while BUSY
is low. At the end of a conversion BUSY goes high indicating
that the update of the addressed DACs is complete. It is rec-
ommended that SCLK is not pulsed while BUSY is low.
Stand-Alone Mode (D CE N = 0)
After SYNC goes low, serial data will be shifted into the
device's input shift register on the falling edges of SCLK for 18
clock pulses. After the falling edge of the 18th SCLK pulse,
data will automatically be transferred from the input shift
register to the addressed DAC. BUSY goes low indicating that
conversion has started. All SCLK pulses will be ignored while
BUSY is low. At the end of a conversion BUSY goes high
indicating that the update of the addressed DAC is complete.
It is recommended that SCLK is not pulsed while BUSY is
low. See the timing diagram in Figure 1.
SYNC must be taken high and low again for further serial data
transfer. SYNC may be taken high after the falling edge of the
18th SCLK pulse, observing the minimum SCLK falling edge
to SYNC rising edge time, t6. If SYNC is taken high before the
18th falling edge of SCLK, the data transfer will be aborted
and the addressed DAC will not be updated.
MSB
LSB
0
0
A3 A2 A1 A0 DB11 DB10 DB9 DB8
DB0
DB7 DB6 DB5 DB4 DB3 DB2 DB1
Mode
Bits
Address
Bits
Data
Bits
Figure 4. Mode1 data form at
–9–
REV. PrA
PRELIMINARY TECHNICAL DATA
AD5517-1/AD5517-2/AD5517-3
O UTLINE D IME NSIO NS
D imensions shown in inches and (mm).
74-Lead LFBGA
(BC-74)
0.394 (10.00) BSC
0.472 (12.00) BSC
11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
A1
0.472
(12.00)
BSC
0.394
(10.00)
BSC
BOTTOM
VIEW
TOP VIEW
0.039
(1.00)
BSC
K
L
0.039 (1.00) BSC
DETAIL A
DETAIL A
0.067
(1.70)
0.033
(0.85)
MAX
0.010
MIN
(0.25)
MIN
CONTROLLING DIMENSIONS
ARE IN MILLIMETERS
0.024 (0.60)
BSC
SEATING
PLANE
BALL DIAMETER
–10–
REV. PrA
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