AD5781SRU-EP [ADI]
True 18-Bit, Voltage Output DAC ±0.5 LSB INL, ±0.5 LSB DNL;
| 型号： | AD5781SRU-EP |
| 厂家： | 
ADI |
| 描述： | True 18-Bit, Voltage Output DAC ±0.5 LSB INL, ±0.5 LSB DNL 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
True 18-Bit, Voltage Output DAC
0.5 LSB INL, 0.5 LSB DNL
Enhanced Product
AD5781-EP
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
V
V
CC
DD
REFPF REFPS
Single 18-bit DAC, 0.5 LSB INL
7.5 nV/√Hz noise spectral density
0.05 LSB long-term linearity stability
<0.05 ppm/°C temperature drift
1 µs settling time
6.8kΩ 6.8kΩ
R1
AD5781-EP
A1
R
IOV
CC
FB
R
FB
INV
SDIN
SCLK
SYNC
SDO
INPUT
SHIFT
18
18
18-BIT
DAC
DAC
REG
V
OUT
REGISTER
AND
1.4 nV-sec glitch impulse
20-lead TSSOP package
CONTROL
LOGIC
Wide power supply range of up to 16.5 V
35 MHz Schmitt triggered digital interface
1.8 V compatible digital interface
Extended automotive operating temperature range −55°C to
+125°C
6kΩ
LDAC
CLR
POWER-ON-RESET
AND CLEAR LOGIC
RESET
DGND
V
AGND
V
V
REFNF REFNS
SS
Figure 1.
ENHANCED PRODUCT FEATURES
COMPANION PRODUCTS
Supports defense and aerospace applications (AQEC standard)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
Ultra precision op amps: AD8675, AD8676
High voltage op amp: ADA4898-1
Additional companion products on the AD5781 product page
One fabrication site
Enhanced product change notification
Qualification data available on request
Table 1. Related Devices
Part No.
Description
AD5791
20-bit, 1 ppm accurate DAC
APPLICATIONS
AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
GENERAL DESCRIPTION
state and remains in this state until a valid write to the device
takes place.
The AD5781-EP1 is a single 18-bit, unbuffered voltage output DAC
that operates from a bipolar supply of up to 33 V. T he AD5781-EP
accepts a positive reference input range of 5 V to VDD − 2.5 V
and a negative reference input range of VSS + 2.5 V to 0 V. The
AD5781-EP offers a relative accuracy specification of 0.5 LSB
maximum, and operation is guaranteed monotonic with a
0.5 LSB DNL maximum specification.
The part provides an output clamp feature that places the
output in a defined load state.
The AD5781-EP is available in a compact, 20-lead TSSOP
package and operates at the extended automotive temperature
range of −55°C to +125°C. Additional application and technical
information can be found in the AD5781 data sheet.
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 35 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, and DSP interface standards. The
part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V and in a known output impedance
PRODUCT HIGHLIGHTS
1. True 18-Bit Accuracy.
2. Wide Power Supply Range of Up to 16.5 V.
3. −55°C to +125°C Operating Temperature Range.
4. Low 7.5 nV/√Hz Noise.
1 Protected by U.S. Patent No. 8,089,380, and other patents are pending.
5. Low 0.05 ppm/°C Temperature Drift.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5781-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing Characteristics .................................................................5
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Description ...............................8
Typical Performance Characteristics ..............................................9
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
Enhanced Product Features ............................................................ 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
REVISION HISTORY
7/13—Rev. 0 to Rev. A
Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5
Deleted Figure 4................................................................................ 7
2/12—Revision 0: Initial Version
Rev. A | Page 2 of 20
Enhanced Product
SPECIFICATIONS
AD5781-EP
VDD = +12.5 V to +16.5 V, VSS = −16.5 V to −12.5 V, VREFP = +10 V, VREFN = −10 V, VCC = +2.7 V to +5.5 V, IOVCC = +1.71 V to +5.5 V,
RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
STATIC PERFORMANCE2
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
Integral Nonlinearity Error (Relative
Accuracy)
18
−0.5
Bits
LSB
0.25
+0.5
VREFP = +10 V, VREFN = −10 V
−0.5
−1
−0.5
−0.5
−1
0.25
0.5
0.25
0.25
0.5
0.04
0.05
0.03
0.25
0.0ꢀ2 +2.75
0.2
0.25
+0.5
+1
+0.5
+0.5
+1
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
VREFP = +10 V, VREFN = 0 V3
VREFP = +5 V, VREFN = 0 V3
VREFP = +10 V, VREFN = −10 V
VREFP = +10 V, VREFN = 0 V
VREFP = +5 V, VREFN = 0 V
After 500 hours at TA = 125°C
After 1000 hours at TA = 125°C
After 1000 hours at TA = 100°C
VREFP = +10 V, VREFN = −10 V3
VREFP = +10 V, VREFN = 0 V3
VREFP = +5 V, VREFN = 0 V3
Differential Nonlinearity Error
Linearity Error Long-Term Stability4
Full-Scale Error
−1.75
−2.75
−5.25
−1
+1.75
+5.25
+1
VREFP = +10 V, VREFN = −10 V3,
TA = 0°C to 105°C
−1
−1.5
0.0ꢀ2 +1
LSB
LSB
VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
0.2
+1.5
Full-Scale Error Temperature Coefficient
Zero-Scale Error
0.02
0.025 +1.75
0.38
0.1ꢁ
0.025 +1
ppm FSR/°C
LSB
LSB
LSB
LSB
−1.75
−2.5
−5.25
−1
VREFP = +10 V, VREFN = −10 V3
VREFP = +10 V, VREFN = 0 V3
VREFP = +5 V, VREFN = 0 V3
VREFP = +10 V, VREFN = −10 V3,
TA = 0°C to 105°C
+2.5
+5.25
−1
−1.5
0.38
0.1ꢁ
0.04
0.3
0.4
0.4
+1
+1.5
LSB
LSB
VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
Zero-Scale Error Temperature Coefficient3
Gain Error
ppm FSR/°C
ppm FSR
ppm FSR
ppm FSR
ppm FSR/°C
%
−ꢀ
−10
−20
+ꢀ
+10
+20
VREFP = +10 V, VREFN = −10 V3
VREFP = +10 V, VREFN = 0 V3
VREFP = +5 V, VREFN = 0 V3
Gain Error Temperature Coefficient3
R1, RFB Matching
OUTPUT CHARACTERISTICS3
0.04
0.01
Output Voltage Range
VREFN
VREFP
V
Output Slew Rate
Output Voltage Settling Time
50
1
V/μs
μs
Unbuffered output, 10 MΩ||20 pF load
10 V step to 0.02%, using AD845
buffer in unity-gain mode
125 code step to 1 LSB5
1
μs
Output Noise Spectral Density
Output Voltage Noise
7.5
7.5
7.5
1.1
nV/√Hz
nV/√Hz
nV/√Hz
μV p-p
At 1 kHz, DAC code = midscale
At 10 kHz, DAC code = midscale
At 100 kHz, DAC code = midscale
DAC code = midscale, 0.1 Hz to
10 Hz bandwidthꢀ
Rev. A | Page 3 of 20
AD5781-EP
Enhanced Product
Parameter1
Midscale Glitch Impulse7
Min
Typ
3.1
1.7
1.4
9.1
3.6
1.9
45
Max
Unit
Test Conditions/Comments
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kΩ
VREFP = +10 V, VREFN = −10 V
VREFP = +10 V, VREFN = 0 V
VREFP = +5 V, VREFN = 0 V
VREFP = +10 V, VREFN = −10 V, see Figure 42
VREFP = 10 V, VREFN = 0 V, see Figure 43
VREFP = 5 V, VREFN = 0 V, see Figure 44
On removal of output ground clamp
MSB Segment Glitch Impulse7
Output Enabled Glitch Impulse
Digital Feedthrough
DC Output Impedance (Normal Mode)
DC Output Impedance (Output
Clamped to Ground)
0.4
3.4
6
kΩ
Spurious Free Dynamic Range
Total Harmonic Distortion
REFERENCE INPUTS3
100
97
dB
dB
1 kHz tone, 10 kHz sample rate
1 kHz tone, 10 kHz sample rate
VREFP Input Range
VREFN Input Range
DC Input Impedance
5
VDD − 2.5 V
0
V
VSS + 2.5 V
5
6.6
15
kΩ
pF
VREFP, VREFN, code dependent,
typical at mid-scale code
Input Capacitance
VREFP, VREFN
LOGIC INPUTS3
Input Current8
−1
+1
0.3 × IOVCC
µA
V
V
Input Low Voltage, VIL
Input High Voltage, VIH
IOVCC = 1.71 V to 5.5 V
IOVCC = 1.71 V to 5.5 V
0.7 × IOVCC
Pin Capacitance
LOGIC OUTPUT (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
5
3
pF
0.4
1
V
IOVCC = 1.71 V to 5.5 V, sinking 1 mA
IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
IOVCC − 0.5 V
µA
pF
POWER REQUIREMENTS
All digital inputs at DGND or IOVCC
VDD
VSS
VCC
7.5
VDD − 33
2.7
VSS + 33
−2.5
5.5
V
V
V
IOVCC
1.71
5.5
V
IOVCC ≤ VCC
IDD
ISS
ICC
IOICC
4.2
4
5.2
4.9
900
140
mA
mA
µA
µA
µV/V
µV/V
dB
dB
600
52
0.6
0.6
95
95
SDO disabled
VDD 10%, VSS = 15 V
VSS 10%, VDD = 15 V
VDD 200 mV, 50 Hz/60 Hz, VSS = −15 V
VSS 200 mV, 50 Hz/60 Hz, VDD = 15 V
DC Power Supply Rejection Ratio3, 9
AC Power Supply Rejection Ratio3
1 Temperature range: −55°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
2 Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.
3 Guaranteed by design and characterization; not production tested.
4 Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified.
5 AD5791-EP configured in ×2 gain mode, 25 pF compensation capacitor on AD797.
6 Includes noise contribution from AD8676BRZ voltage reference buffers.
7 The AD5781-EP is configured in the bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output
buffer, lead capacitance, and so forth).
8 Current flowing in an individual logic pin.
9 Includes PSRR of AD8676BRZ voltage reference buffers.
Rev. A | Page 4 of 20
Enhanced Product
AD5781-EP
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit1
Parameter
IOVCC = 1.71 V to 3.3 V
IOVCC = 3.3 V to 5.5 V Unit
Test Conditions/Comments
SCLK cycle time
SCLK cycle time (readback mode)
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
2
t1
40
92
15
9
28
60
10
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns min
ns typ
ns min
t2
t3
t4
5
5
t5
2
2
SCLK falling edge to SYNC rising edge hold time
Minimum SYNC high time
t6
48
8
40
6
t7
SYNC rising edge to next SCLK falling edge ignore
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
t8
t9
9
7
7
12
13
20
14
130
130
50
140
0
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
10
16
11
130
130
50
140
0
LDAC falling edge to output response time
SYNC rising edge to output response time (LDAC tied low)
CLR pulse width low
CLR pulse activation time
SYNC falling edge to first SCLK rising edge
65
62
0
60
45
0
ns max SYNC rising edge to SDO tristate (CL = 50 pF)
ns max SCLK rising edge to SDO valid (CL = 50 pF)
ns min
ns typ
ns typ
SYNC rising edge to SCLK rising edge ignore
RESET pulse width low
35
150
35
150
RESET pulse activation time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode.
Rev. A | Page 5 of 20
AD5781-EP
Enhanced Product
t1
t7
SCLK
1
2
24
t3
t2
t6
t4
t5
SYNC
SDIN
t9
t8
DB23
DB0
t12
t10
t11
LDAC
t13
V
V
OUT
OUT
t14
t15
CLR
t16
V
OUT
t21
RESET
t22
V
OUT
Figure 2. Write Mode Timing Diagram
t20
t1
t17
t7
SCLK
1
2
24
1
2
24
t3
t2
t6
t17
t5
t5
t4
SYNC
SDIN
t9
t8
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t18
t19
DB23
DB0
SDO
REGISTER CONTENTS CLOCKED OUT
Figure 3. Readback Mode Timing Diagram
Rev. A | Page 6 of 20
Enhanced Product
AD5781-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
VDD to AGND
VSS to AGND
VDD to VSS
VCC to DGND
IOVCC to DGND
Rating
−0.3 V to +34 V
−34 V to +0.3 V
−0.3 V to +34 V
−0.3 V to +7 V
−0.3 V to VCC + 3 V or +7 V
(whichever is less)
This device is a high performance integrated circuit with an ESD
rating of 1.5 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
Digital Inputs to DGND
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
ESD CAUTION
VOUT to AGND
VREFPF to AGND
VREFPS to AGND
VREFNF to AGND
VREFNS to AGND
DGND to AGND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
VSS − 0.3 V to +0.3 V
VSS − 0.3 V to +0.3 V
−0.3 V to +0.3 V
Operating Temperature Range, TA
Industrial
Storage Temperature Range
Maximum Junction Temperature,
TJ max
−55°C to + 125°C
−65°C to +150°C
150°C
Power Dissipation
TSSOP Package
(TJ max − TA)/θJA
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature
Soldering
143°C/W
45°C/W
JEDEC industry standard
J-STD-020
ESD (Human Body Model)
1.5 kV
Rev. A | Page 7 of 20
AD5781-EP
Enhanced Product
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
2
20
19
18
17
16
15
14
13
12
11
INV
OUT
R
FB
V
AGND
3
V
V
REFPS
SS
4
V
V
REFPF
REFNS
REFNF
AD5781-EP
5
V
V
DD
TOP VIEW
6
RESET
CLR
DGND
SYNC
SCLK
SDIN
SDO
(Not to Scale)
7
8
LDAC
9
V
CC
CC
10
IOV
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
INV
VOUT
VREFPS
Connection to Inverting Input of External Amplifier.
Analog Output Voltage.
Positive Reference Sense Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain amplifier
must be connected at this pin, in conjunction with the VREFPF pin.
4
5
VREFPF
VDD
Positive Reference Force Voltage Input. A voltage range of 5 V to VDD − 2.5 V can be connected. A unity gain amplifier
must be connected at these pin, in conjunction with the VREFPS pin.
Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected. VDD should be decoupled to
AGND.
6
7
Active Low Reset Logic Input Pin. Asserting this pin returns the AD5781-EP to its power-on status.
RESET
CLR
Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value and updates the DAC
output. The output value depends on the DAC register coding that is being used, either binary or twos complement.
8
Active Low Load DAC Logic Input Pin. This is used to update the DAC register and, consequently, the analog output.
When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write
cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The LDAC pin
should not be left unconnected.
LDAC
9
VCC
Digital Supply Connection. A voltage in the range of 2.7 V to 5.5 V can be connected. VCC should be decoupled to DGND.
10
IOVCC
Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage range of
1.71 V to 5.5 V can be connected. IOVCC should not be allowed to exceed VCC.
11
12
SDO
SDIN
Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input.
Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
13
14
SCLK
SYNC
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at clock rates of up to 35 MHz.
Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data. When
SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks.
The input shift register is updated on the rising edge of SYNC.
15
16
DGND
VREFNF
Ground Reference Pin for Digital Circuitry.
Negative Reference Force Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier
must be connected at this pin, in conjunction with the VREFNS pin.
17
18
VREFNS
VSS
Negative Reference Sense Voltage Input. A voltage range of VSS + 2.5 V to 0 V can be connected. A unity gain amplifier
must be connected at these pin, in conjunction with the VREFNF pin.
Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. VSS should be decoupled to
AGND.
19
20
AGND
RFB
Ground Reference Pin for Analog Circuitry.
Feedback Connection for External Amplifier.
Rev. A | Page 8 of 20
Enhanced Product
AD5781-EP
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.5
0.4
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +25°C
= –40°C
= +125°C
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
A
A
A
A
A
A
0.4
V
V
V
V
= +10V
= 0V
= +15V
REFP
REFN
0.3
0.3
DD
SS
0.2
0.2
= –15V
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
V
V
V
V
= +10V
= –10V
= +15V
= –15V
50000
REFP
REFN
DD
SS
0
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
DAC CODE
DAC CODE
Figure 5. Integral Nonlinearity Error vs. DAC Code, 10 V Span
Figure 8. Integral Nonlinearity Error vs. DAC Code, 10 V Span, ×2 Gain Mode
0.5
0.5
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
A
A
A
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
A
A
A
0.4
0.3
0.4
0.3
V
V
V
V
= +10V
= –10V
= +15V
REFP
REFN
DD
SS
0.2
0.2
= –15V
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
V
V
V
V
= +10V
= 0V
= +15V
REFP
REFN
DD
SS
= –15V
0
50000
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
DAC CODE
DAC CODE
Figure 6. Integral Nonlinearity Error vs. DAC Code, +10 V Span
Figure 9. Differential Nonlinearity Error vs. DAC Code, 10 V Span
1.0
0.5
T
T
T
= +125°C
= +25°C
= –40°C
AD8676 REFERENCE BUFFERS
0.4 AD8675 OUTPUT BUFFER
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
0.8
0.6
V
V
V
V
= +10V
= 0V
= +15V
REFP
0.3
0.2
REFN
DD
SS
0.4
= –15V
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
V
V
V
V
= +5V
= 0V
= +15V
= –15V
REFP
REFN
DD
SS
0
50000
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
DAC CODE
DAC CODE
Figure 7. Integral Nonlinearity Error vs. DAC Code, +5 V Span
Figure 10. Differential Nonlinearity Error vs. DAC Code, +10 V Span
Rev. A | Page 9 of 20
AD5781-EP
Enhanced Product
0.5
0.3
0.2
T
T
T
= +125°C
= +25°C
= –40°C
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
A
A
A
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.4
0.3
V
V
= +5V
= 0V
REFP
REFN
V
V
= +15V
= –15V
DD
SS
0.1
0
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
±10V SPAN MAX DNL
+5V SPAN MAX DNL
+10V SPAN MIN DNL
+10V SPAN MAX DNL
±10V SPAN MIN DNL
+5V SPAN MIN DNL
V
= +15V
= –15V
DD
V
SS
–55
–35
–15
5
25
45
65
85
105
125
0
50000
100000
150000
200000
250000
TEMPERATURE (°C)
DAC CODE
Figure 14. Differential Nonlinearity Error vs. Temperature
Figure 11. Differential Nonlinearity Error vs. DAC Code, +5 V Span
0.14
0.5
T
T
T
= +25°C
= –40°C
= +125°C
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
A
A
A
0.12
0.10
0.08
0.06
0.04
0.02
0
0.4
0.3
V
V
V
V
= +10V
= 0V
= +15V
REFP
REFN
INL MAX
DD
SS
0.2
= –15V
T
= 25°C
A
0.1
V
V
= +10V
= –10V
REFP
REFN
0
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.1
–0.2
–0.3
–0.4
–0.5
INL MIN
–0.02
–0.04
–0.06
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
0
50000
100000
150000
200000
250000
V
/|V | (V)
DAC CODE
DD SS
Figure 15. Integral Nonlinearity Error vs. Supply Voltage, 10 V Span
Figure 12. Differential Nonlinearity Error vs. DAC Code, 10 V Span,
×2 Gain Mode
0.4
0.5
AD8676 REFERENCE BUFFERS
0.4 AD8675 OUTPUT BUFFER
0.3
V
V
= +15V
= –15V
DD
SS
INL MAX
0.3
0.2
0.2
T
V
V
= 25°C
0.1
A
0.1
= +5V
REFP
REFN
= 0V
0
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0
–0.1
–0.2
–0.1
–0.2
–0.3
–0.4
–0.5
±10V SPAN MAX INL
+5V SPAN MAX INL
+10V SPAN MIN INL
+10V SPAN MAX INL
±10V SPAN MIN INL
+5V SPAN MIN INL
INL MIN
–0.3
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
(V)
–55
–35
–15
5
25
45
65
85
105
125
V
TEMPERATURE (°C)
DD
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
(V)
V
SS
Figure 13. Integral Nonlinearity Error vs. Temperature
Figure 16. Integral Nonlinearity Error vs. Supply Voltage, +5 V Span
Rev. A | Page 10 of 20
Enhanced Product
AD5781-EP
0.08
0.14
0.12
T
V
V
= 25°C
A
0.06
= +5V
REFP
REFN
DNL MAX
= 0V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.04
0.02
0.10
0.08
T
V
V
= 25°C
A
= +10V
REFP
REFN
0
= –10V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.06
–0.02
0.04
0.02
–0.04
–0.06
DNL MIN
0
–0.08
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
(V)
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
V
DD
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
(V)
V
/|V | (V)
DD SS
V
SS
Figure 20. Zero-Scale Error vs. Supply Voltage, +5 V Span
Figure 17. Differential Nonlinearity Error vs. Supply Voltage, 10 V Span
0.05
0.04
0.10
0.05
T
V
V
= 25°C
A
= +10V
REFP
REFN
= –10V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
DNL MAX
0.03
0.02
0.01
0
0
T
V
V
= 25°C
A
–0.05
–0.10
= +5V
REFP
REFN
= 0V
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.15
–0.20
–0.01
–0.02
DNL MIN
–0.03
–0.25
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
(V)
V
V
DD SS
/|V | (V)
DD
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
(V)
V
SS
Figure 21. Midscale Error vs. Supply Voltage, 10 V Span
Figure 18. Differential Nonlinearity Error vs. Supply Voltage, +5 V Span
0.05
0
0.14
0.12
0.10
0.08
0.06
–0.05
–0.10
–0.15
–0.20
T
V
V
= 25°C
A
T
V
V
= 25°C
0.04
0.02
= +10V
= –10V
A
REFP
REFN
= +5V
= 0V
REFP
REFN
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0
12.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
(V)
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
V
DD
V
/|V | (V)
DD SS
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
(V)
V
SS
Figure 22. Midscale Error vs. Supply Voltage, +5 V Span
Figure 19. Zero-Scale Error vs. Supply Voltage, 10 V Span
Rev. A | Page 11 of 20
AD5781-EP
Enhanced Product
–0.015
0.10
0.05
0
T
V
V
= 25°C
A
= +5V
= 0V
REFP
REFN
–0.020
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.025
–0.030
–0.035
T
V
V
= 25°C
A
= +10V
= –10V
REFP
REFN
–0.040
–0.045
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
/|V | (V)
V
(V)
DD SS
DD
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
(V)
V
SS
Figure 23. Full-Scale Error vs. Supply Voltage, 10 V Span
Figure 26. Gain Error vs. Supply Voltage, +5 V Span
0.07
0.15
0.10
0.06
0.05
INL MAX
0.04
0.03
0.02
0.01
0.05
0
T
V
V
= 25°C
= +15V
A
DD
= –15V
SS
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.05
T
= 25°C
A
V
V
= +5V
= 0V
REFP
REFN
0
–0.01
–0.02
–0.10
–0.15
INL MIN
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
7.5
8.5
9.5
10.5 11.5 12.5 13.5 14.5 15.5 16.5
(V)
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
V
V
| (V)
DD
REFP REFN
–2.5 –3.9 –5.3 –6.7 –9.1 –10.5 –12.9 –14.2 –15.5 –16.5
(V)
V
SS
Figure 24. Full-Scale Error vs. Supply Voltage, +5 V Span
Figure 27. Integral Nonlinearity Error vs. Reference Voltage
–0.30
–0.35
0.10
T
V
V
= 25°C
A
DNL MAX
= +10V
REFP
REFN
= –10V
0.05
0
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.40
–0.45
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.50
–0.55
–0.05
–0.10
–0.15
–0.60
–0.65
DNL MIN
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
16.5
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
V
/|V | (V)
V
| (V)
DD SS
REFP REFN
Figure 25. Gain Error vs. Supply Voltage, 10 V Span
Figure 28. Differential Nonlinearity Error vs. Reference Voltage
Rev. A | Page 12 of 20
Enhanced Product
AD5781-EP
0.16
0.14
0.12
0.10
–0.30
–0.35
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.40
–0.45
–0.50
–0.55
–0.60
T
V
V
= 25°C
A
0.08
0.06
0.04
= +15V
= –15V
DD
SS
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.02
0
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
V
| (V)
V
| (V)
REFP REFN
REFP REFN
Figure 32. Gain Error vs. Reference Voltage
Figure 29. Zero-Scale Error vs. Reference Voltage
0.3
0.2
0.1
0.03
0.02
0.01
0
±10V SPAN
+10V SPAN
±5V SPAN
0
–0.1
–0.01
–0.02
–0.03
–0.2
–0.3
–0.4
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
T
V
V
= 25°C
= +15V
A
DD
V
V
V
V
= +15V
= –15V
= –15V
DD
SS
SS
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
= +10V
= –15V
REFP
REFN
–0.04
–0.05
–0.5
–0.6
–55
–35
–15
5
25
45
65
85
105
125
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
TEMPERATURE (°C)
V
| (V)
REFP REFN
Figure 33. Full-Scale Error vs. Temperature
Figure 30. Mid-Scale Error vs. Reference Voltage
0.40
0.35
0.30
0.04
0.03
0.02
0.01
±10V SPAN
+10V SPAN
±5V SPAN
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
0.25
0.20
0.15
0.10
0.05
0
0
–0.01
–0.02
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
V
V
V
V
= +15V
= –15V
DD
SS
= +10V
= –15V
REFP
REFN
–0.03
–0.04
–55
–35
–15
5
25
45
65
85
105
125
5.0
5.5
6.0
6.5
7.0
7.5
/|V
8.0
8.5
9.0
9.5 10.0
TEMPERATURE (°C)
V
| (V)
REFP REFN
Figure 34. Mid-Scale Error vs. Temperature
Figure 31. Full-Scale Error vs. Reference Voltage
Rev. A | Page 13 of 20
AD5781-EP
Enhanced Product
1.2
1.0
0.8
0.6
5
4
±10V SPAN
+10V SPAN
±5V SPAN
T
= 25°C
A
I
DD
3
2
0.4
0.2
1
0
0
–1
–2
–3
–0.2
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
–0.4
V
V
V
V
= +15V
= –15V
DD
SS
–0.6
–0.8
–1.0
I
SS
= +10V
= –15V
REFP
REFN
–4
–5
–55
–35
–15
5
25
45
65
85
105
125
–20
–15
–10
–5
0
5
10
15
20
TEMPERATURE (°C)
V
, V (V)
DD SS
Figure 35. Zero-Scale Error vs. Temperature
Figure 38. Power Supply Currents vs. Power Supply Voltages
4
3
±10V SPAN
+10V SPAN
+5V SPAN
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUFFER
V
V
V
V
= +15V
= –15V
DD
SS
2
1
= +10V
= –15V
REFP
REFN
V
V
V
V
= +15V
= –15V
DD
SS
= +10V
= –10V
REFP
REFN
0
3→
AD8676 REFERENCE BUFFERS
OUTPUT UNBUFFERED
LOAD = 10MΩ||20pF
–1
–2
–3
–4
–5
4→
CH3 5V
CH4 5V
200ns
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 39. Rising Full-Scale Voltage Step
Figure 36. Gain Error vs. Temperature
900
800
700
600
500
400
300
200
100
0
IOV = 5V, LOGIC VOLTAGE
CC
INCREASING
V
V
V
V
= +15V
= –15V
DD
SS
T
= 25°C
A
IOV = 5V, LOGIC VOLTAGE
= +10V
= –10V
CC
REFP
REFN
DECREASING
IOV = 3V, LOGIC VOLTAGE
AD8676 REFERENCE BUFFERS
OUTPUT UNBUFFERED
LOAD = 10MΩ||20pF
CC
INCREASING
IOV = 3V, LOGIC VOLTAGE
CC
DECREASING
3→
4→
CH3 5V
CH4 5V
200ns
0
1
2
3
4
5
6
LOGIC INPUT VOLTAGE (V)
Figure 40. Falling Full-Scale Voltage Step
Figure 37. IOICC vs. Logic Input Voltage
Rev. A | Page 14 of 20
Enhanced Product
AD5781-EP
10.8
10.6
10.4
10.2
10.0
9.8
3.0
2.6
2.2
±10V V
REF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
5V V
REF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
NEGATIVE CODE
CHANGE
POSITIVE CODE
CHANGE
1.8
1.4
1.0
0.6
9.6
0.2
9.4
–0.2
0
1
2
3
4
5
TIME (µs)
CODE
Figure 41. 125 Code Step Settling Time
Figure 44. 6 MSB Segment Glitch Energy for 5 V VREF
10
9
40
30
5V V
±10V V
REF
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
REF
OUTPUT GAIN OF 1
NEGATIVE CODE
CHANGE
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
8
7
6
5
4
3
2
1
0
20
10
POSITIVE CODE
CHANGE
0
C
C
C
C
= 143pF + 0pF
X
X
X
X
–10
–20
= 143pF + 220pF
= 143pF + 470pF
= 143pF + 1,000pF
–1.0
–0.5
0
0.5
1.0
1.5
2.0
TIME (µs)
CODE
Figure 45. Midscale Peak-to-Peak Glitch for 10 V
Figure 42. 6 MSB Segment Glitch Energy for 10 V VREF
800
4.0
3.5
T
= 25°C
A
MID-SCALE CODE LOADED
OUTPUT UNBUFFERED
AD8676 REFERENCE BUFFERS
10V V
OUTPUT GAIN OF 1
BIAS COMPENSATION MODE
20pF COMPENSATION CAPACITOR
RC LOW-PASS FILTER
REF
V
V
V
V
= +15V
= –15V
DD
SS
600
400
= +10V
= –10V
REFP
REFN
POSITIVE CODE
CHANGE
3.0
2.5
2.0
1.5
1.0
0.5
0
NEGATIVE CODE
CHANGE
200
0
–200
–400
–600
0
1
2
3
4
5
6
7
8
9
10
TIME (Seconds)
CODE
Figure 46. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth
Figure 43. 6 MSB Segment Glitch Energy for 10 V VREF
Rev. A | Page 15 of 20
AD5781-EP
Enhanced Product
100
350
300
250
200
V
V
V
V
= +15V
= –15V
DD
SS
T
= 25°C
A
V
V
V
V
= +15V
= –15V
DD
SS
= +10V
= –10V
REFP
REFN
= +10V
= –10V
REFP
REFN
CODE = MIDSCALE
AD8675 OUTPUT BUFFER
10
150
100
50
0
–50
–1
1
0.1
0
1
2
3
4
5
6
1
10
100
1k
10k
100k
FREQUENCY (Hz)
TIME (µs)
Figure 48. Glitch Impulse on Removal of Output Clamp
Figure 47. Noise Spectral Density vs. Frequency
Rev. A | Page 16 of 20
Enhanced Product
AD5781-EP
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 50. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−55°C to +125°C
INL
0.5 LSB
Package Description
Package Option
RU-20
AD5781SRU-EP
20-Lead TSSOP
Rev. A | Page 17 of 20
AD5781-EP
NOTES
Enhanced Product
Rev. A | Page 18 of 20
Enhanced Product
NOTES
AD5781-EP
Rev. A | Page 19 of 20
AD5781-EP
NOTES
Enhanced Product
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10454-0-7/13(A)
Rev. A | Page 20 of 20
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