AD645JCHIPS [ADI]
IC OP-AMP, 1000 uV OFFSET-MAX, 2 MHz BAND WIDTH, UUC, DIE, Operational Amplifier;
| 型号： | AD645JCHIPS |
| 厂家： | 
ADI |
| 描述： | IC OP-AMP, 1000 uV OFFSET-MAX, 2 MHz BAND WIDTH, UUC, DIE, Operational Amplifier 运算放大器 |
| 文件： | 总8页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, Low Drift
FET Op Amp
a
AD645
FEATURES
CONNECTION DIAGRAMS
Improved Replacement for Burr-Brown
OPA-111 and OPA-121 Op Amp
TO-99 (H) Package
8-Pin Plastic Mini-DIP
(N) Package
CASE
LOW NOISE
2 V p-p max, 0.1 Hz to 10 Hz
10 nV/√Hz max at 10 kHz
11 fA p-p Current Noise 0.1 Hz to 10 Hz
OFFSET
NULL
OFFSET
NULL
8
1
2
3
4
8
7
6
5
NC
+V
+V
1
3
7
5
AD645
–IN
S
2
– IN
6
OUTPUT
HIGH DC ACCURACY
250 V max Offset Voltage
1 V/؇C max Drift
1.5 pA max Input Bias Current
114 dB Open-Loop Gain
Available in Plastic Mini-DIP, 8-Pin Header Packages, or
Chip Form
+IN
OUTPUT
AD645
4
OFFSET
NULL
OFFSET
NULL
+IN
TOP VIEW
–V
S
–
V
NC = NO CONNECT
NOTE: CASE IS CONNECTED
TO PIN 8
The AD645 is available in six performance grades. The AD645J
and AD645K are rated over the commercial temperature range
of 0°C to +70°C. The AD645A, AD645B, and the ultra-
precision AD645C are rated over the industrial temperature
range of –40°C to +85°C. The AD645S is rated over the military
temperature range of –55°C to +125°C and is available
processed to MIL-STD-883B.
APPLICATIONS
Low Noise Photodiode Preamps
CT Scanners
Precision I-V Converters
PRODUCT DESCRIPTION
The AD645 is available in an 8-pin plastic mini-DIP, 8-pin
header, or in die form.
The AD645 is a low noise, precision FET input op amp. It of-
fers the pico amp level input currents of a FET input device
coupled with offset drift and input voltage noise comparable to a
high performance bipolar input amplifier.
PRODUCT HIGHLIGHTS
1. Guaranteed and tested low frequency noise of 2 µV p-p max
and 20 nV/√Hz at 100 Hz makes the AD645C ideal for low
noise applications where a FET input op amp is needed.
The AD645 has been improved to offer the lowest offset drift in
a FET op amp, 1 µV/°C. Offset voltage drift is measured and
trimmed at wafer level for the lowest cost possible. An inher-
ently low noise architecture and advanced manufacturing tech-
niques result in a device with a guaranteed low input voltage
noise of 2 µV p-p, 0.1 Hz to 10 Hz. This level of dc performance
along with low input currents make the AD645 an excellent
choice for high impedance applications where stability is of
prime concern.
2. Low VOS drift of 1 µV/°C max makes the AD645C an excel-
lent choice for applications requiring ultimate stability.
3. Low input bias current and current noise (11 fA p-p 0.1 Hz to
10 Hz) allow the AD645 to be used as a high precision
preamp for current output sensors such as photodiodes, or as
a buffer for high source impedance voltage output sensors.
30
25
20
1k
100
15
10
10
5
0
1.0
–2.5 –2.0 –1.5 –1.0 –0.5
0.0
0.5
1.0
1.5
2.0
2.5
1
10
100
1k
10k
FREQUENCY – Hz
INPUT OFFSET VOLTAGE DRIFT– µV/
°C
Figure 1. AD645 Voltage Noise Spectral Density vs.
Frequency
Figure 2. Typical Distribution of Average Input Offset
Voltage Drift (196 Units)
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
(@ +25؇C, and ؎15 V dc, unless otherwise noted)
AD645–SPECIFICATIONS
Model
AD645J/A
AD645K/B
Max Min Typ Max
AD645C
Min Typ
AD645S
Min Typ
Conditions1
Min Typ
Max
Max
Units
INPUT OFFSET VOLTAGE1
Initial Offset
Offset
Drift (Average)
vs. Supply (PSRR)
vs. Supply
100
300
3
110
100
500
1000
10/5
50
100
1
110
100
250
400
5/2
50
75
0.5
110
100
250
300
1
100
500
4
110
95
500
1500
10
µV
µV
µV/°C
dB
dB
T
MIN –TMAX
90
94
90
94
90
90
86
TMIN –TMAX
VCM = 0 V
INPUT BIAS CURRENT2
Either Input
0.7/1.8 3/5
0.7/1.8 1.5/3
1.8
3
1.8
5
pA
Either Input
@ TMAX
Either Input
Offset Current
Offset Current
@ TMAX
VCM = 0 V
VCM = +10 V
16/115
0.8/1.9
0.1
16/115
0.8/1.9
0.1
115
1.9
0.1
1800
1.9
0.1
pA
pA
pA
V
CM = 0 V
1.0
0.5
0.5
1.0
VCM = 0 V
2/6
2/6
6
100
pA
INPUT VOLTAGE NOISE
0.1 to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
1.0
20
10
9
3.0
50
30
15
10
1.0
20
10
9
2.5
40
20
12
10
1
2
1.0
20
10
9
3.3
50
30
15
10
µV p-p
20
10
9
40
20
12
10
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
f = 10 kHz
8
8
8
8
INPUT CURRENT NOISE
f = 0.1 to 10 Hz
11
20
11
15
11
15
11
20
fA p-p
f = 0.1 thru 20 kHz
0.6
1.1
0.6
0.8
0.6
0.8
0.6
1.1
fA/√Hz
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
2
2
2
2
MHz
kHz
VO = 20 V p-p
RLOAD = 2 kΩ
VOUT = 20 V p-p
RLOAD = 2 kΩ
16
1
32
2
16
1
32
2
16
1
32
2
16
1
32
2
Slew Rate, Unity Gain
V/µs
SETTLING TIME3
To 0.1%
6
8
5
6
8
5
6
8
5
6
8
5
µs
µs
µs
To 0.01%
Overload Recovery4
Total Harmonic
Distortion
50% Overdrive
f = 1 kHz
RLOAD ≥ 2 kΩ
VO = 3 V rms
0.0006
0.0006
0.0006
0.0006
%
INPUT IMPEDANCE
Differential
Common-Mode
VDIFF = ±1 V
1012ʈ1
1012ʈ1
1012ʈ1
1012ʈ1
ΩʈpF
ΩʈpF
1014ʈ2.2
1014ʈ2.2
1014ʈ2.2
1014ʈ2.2
INPUT VOLTAGE RANGE
Differential5
Common-Mode Voltage
Over Max Oper. Range
Common-Mode
±20
+11, –10.4
±20
+11, –10.4
±20
+11, –10.4
±20
+11, –10.4
V
V
V
±10
±10
±10
±10
±10
±10
±10
±10
Rejection Ratio
VCM = ±10 V
TMIN–TMAX
90
110
100
94
90
110
100
94
90
110
100
90
86
110
100
dB
dB
OPEN-LOOP GAIN
VO = ±10 V
RLOAD ≥ 2 kΩ
TMIN –TMAX
114
130
120
114
130
120
114
130
114
110
130
dB
dB
OUTPUT CHARACTERISTICS
Voltage
RLOAD ≥ 2 kΩ
TMIN –TMAX
VOUT = ±10 V
Short Circuit
±10
±10
±5
±11
±10
±10
±5
±11
±10
±10
±5
±11
±10
±10
±5
±11
V
V
mA
mA
Current
±10
±15
±10
±15
±10
±15
±10
±15
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
Transistor Count
±15
±15
±18
±15
±18
±15
±18
V
V
mA
±5
±18
3.5
±5
±5
±5
3.0
62
3.0
62
3.5
3.0
62
3.5
3.0
62
3.5
# of Transistors
NOTES
1Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C.
2Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.
3Gain = –1, RLOAD = 2 kΩ.
4Defined as the time required for the amplifier’s output to return to normal operation after removal of a 50% overload from the amplifier input.
5Defined as the maximum continuous voltage between the inputs such that neither input exceeds ±10 V from ground.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. B
AD645
ABSOLUTE MAXIMUM RATINGS1
AD645A/B/C . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD645S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2 (@ TA = +25°C)
8-Pin Header Package . . . . . . . . . . . . . . . . . . . . . . 500 mW
8-Pin Mini-DIP Package . . . . . . . . . . . . . . . . . . . . 750 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (H) . . . . . . . . . –65°C to +150°C
Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C
Operating Temperature Range
(Soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2Thermal Characteristics:
8-Pin Plastic Mini-DIP Package: θJA = 100°C/Watt
8-Pin Header Package: θJA = 200°C/Watt
AD645J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD645 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
Model1
Temperature Range Package Option2
AD645JN
0°C to +70°C
N-8
AD645KN
AD645AH
AD645BH
AD645CH
AD645SH/883B
0°C to +70°C
N-8
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
H-08A
H-08A
H-08A
H-08A
NOTES
1Chips are also available.
2N = Plastic Mini-DIP; H = Metal Can.
+V
S
7
2
3
6
AD645
5
1
10k
4
V
ADJUST
OS
–V
S
Figure 3. AD645 Offset Null Configuration
25
20
15
10
5
120
110
100
90
800
700
600
500
400
300
200
100
0
80
70
60
50
40
30
20
10
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0
1.2
1.6
0.4
0.6
0.8
1.0
1.4
1.8
INPUT BIAS CURRENT – pA
INPUT OFFSET VOLTAGE – mV
INPUT VOLTAGE NOISE – µV p-p
Figure 4. Typical Distribution of Input
Offset Voltage (1855 Units)
Figure 5. Typical Distribution of Input
Bias Current (576 Units)
Figure 6. Typical Distribution of 0.1 Hz
to 10 Hz Voltage Noise (202 Units)
REV. B
–3–
(@ +25؇C, ؎15 V unless otherwise noted)
AD645–Typical Characteristics
1k
1000
100
100
RS = 10MΩ
RS = 1MΩ
100
10
RS = 100kΩ
RS = 100Ω
10
10
1.0
1
0.1
0
0.1
1.0
10
100
1k
10k
100k
1
10
100
1k
10k
100k
1
10
100
FREQUENCY – Hz
1k
10k
100k
1M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 9. Voltage Noise Spectral
Density vs. Frequency for Various
Source Resistances
Figure 7. Current Noise Spectral
Density vs. Frequency
Figure 8. Voltage Noise Spectral
Density vs. Frequency
1k
1k
25
100
f
o
= 1kHz
10
1
20
15
100
100
CURRENT NOISE
NOISE BANDWIDTH: 0.1 to 10Hz
NOISE OF AD645
AND RESISTOR
10
10
10
5
0.1
SOURCE
RESISTANCE
VOLTAGE NOISE
RESISTOR NOISE
ONLY
0.01
1.0
–
–
–
20
60 40
0
20
40
60 80 100 120 140
1.0
100
103
104
105
106
107
10 8
109
1k
10k
100k
1M
10M
100M
TEMPERATURE –
C
SOURCE RESISTANCE – Ω
SOURCE RESISTANCE – Ω
Figure 11. Voltage and Current
Noise Spectral Density vs.
Temperature
Figure 12. Voltage Noise Spectral
Density @ 1 kHz vs. Source
Resistance
Figure 10. Input Voltage Noise vs.
Source Resistance
10 –
10–
10 –
10 –
9
50
9
150
75
T
A = +25
C
VS = ±15V
10–
10
10
11
25
0
INPUT
BIAS
CURRENT
11
T
= 25°C TO T = 85°C
A
10 –
A
0
10–
10–
10 –
12
13
12
13
INPUT
OFFSET
CURRENT
–
–
25
50
–
75
10–
10–
10–14
80 100 120 140
14
–
–150
0
1
2
3
4
5
–
–
20
60 40
0
20
40
60
0
1
2
3
4
5
WARM-UP TIME – Minutes
TEMPERATURE –
C
TIME FROM THERMAL SHOCK – Minutes
Figure 14. Change in Input Offset
Voltage vs. Time from Thermal
Shock
Figure 13. Change in Input Offset
Voltage vs. Warmup Time
Figure 15. Input Bias and Offset
Currents vs. Temperature
–4–
REV. B
AD645
120
100
80
120
100
80
10
T
V
= +25°C
= ±15V
A
S
+
PSRR
H PACKAGE
–
PSRR
60
40
1.0
60
40
20
0
20
0
0.1
–20
1
10
100
1k
10k
100k
1M
10M
–
15
–
10
–
5
0
5
10
15
1
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
COMMON MODE VOLTAGE – Volts
Figure 18. Common-Mode
Rejection vs. Frequency
Figure 17. Power Supply Rejection
vs. Frequency
Figure 16. Input Bias Current vs.
Common-Mode Voltage
–
110
100
45
120
110
3.0
2.0
4.0
3.0
PHASE
80
60
–
90
100
90
SLEW RATE
GAIN
40
–
–
135
180
GAIN-BANDWIDTH
1.0
2.0
20
0
80
70
–
20
0
–
1.0
–
–
–
5
15
10
0
5
10
15
10
100
1k
10k
100k
1M
10M
–
–
20
20
TEMPERATURE – ؇C
60 40
0
40
60 80 100 120 140
FREQUENCY – Hz
COMMON MODE VOLTAGE – Volts
Figure 19. Common-Mode
Rejection vs. Input Common-Mode
Voltage
Figure 20. Open-Loop Gain and
Phase Shift vs. Frequency
Figure 21. Gain-Bandwidth Product
and Slew Rate vs. Temperature
4.0
160
35
30
25
20
VS= ±15V
VO= ±10V
RL = 2kΩ
4.0
150
3.0
140
3.0
SLEW RATE
130
120
15
10
2.0
GAIN-BANDWIDTH
2.0
110
100
5
0
1.0
0
5
10
15
20
–
–
–
60 40 20
0
20 40
60 80 100 120 140
SUPPLY VOLTAGE – ±Volts
1k
10k
100k
1M
TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 23. Open-Loop Gain vs.
Temperature
Figure 24. Large Signal Frequency
Response
Figure 22. Gain-Bandwidth and
Slew Rate vs. Supply Voltage
REV. B
–5–
AD645–Typical Characteristics
4
3
10
100
90
80
8
6
FOR 10V STEP
4
2
0
70
60
50
40
30
20
0.1%
0.01%
0.01%
ERROR
2
0.1%
–
2
4
6
8
0.1%
0.01%
–
–
–
1
0
10
0
–
10
1.0
1
10
100
1k
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
–60 –40 –20
0
20
40
60
80
100 120 140
CLOSED-LOOP VOLTAGE GAIN (V/V)
SETTLING TIME – µs
TEMPERATURE – ؇C
Figure 26. Settling Time vs. Closed-
Loop Voltage Gain
Figure 27. Supply Current vs.
Temperature
Figure 25. Output Swing and Error
vs. Settling Time
0.1µF
+
VS
7
2
VOUT
AD645
6
V
IN
3
4
0.1µF
RL
CL
2kΩ
10pF
–
VS
Figure 28c. Unity-Gain Follower
Small Signal Pulse Response
Figure 28a. Unity-Gain Follower
Figure 28b. Unity-Gain Follower
Large Signal Pulse Response
5kΩ
0.1µF
+
VS
V
IN
5kΩ
7
2
VOUT
6
AD645
3
4
0.1µF
CL
RL
10pF
2kΩ
–
VS
Figure 29a. Unity-Gain Inverter
Figure 29c. Unity-Gain Inverter
Small Signal Pulse Response
Figure 29b. Unity-Gain Inverter
Large Signal Pulse Response
–6–
REV. B
AD645
10pF
Sources of noise in a typical preamp are shown in Figure 32.
The total noise contribution is defined as:
109
Ω
2
2
Rf
Rf
1 + s (Cd ) Rd
Rd 1 + s (Cf ) Rf
2
en
2
2
2
i
i
i
V
=
+
+
s
+
1 +
GUARD
n
f
OUT
1 + s (Cf ) Rf
2
OUTPUT
AD645
6
Figure 33, a spectral density versus frequency plot of each
source’s noise contribution, shows that the bandwidth of the
3
8
PHOTODIODE
amplifier’s input voltage noise contribution is much greater than
its signal bandwidth. In addition, capacitance at the summing
junction results in a “peaking” of noise gain in this configura-
tion. This effect can be substantial when large photodiodes with
large shunt capacitances are used. Capacitor Cf sets the signal
bandwidth and also limits the peak in the noise gain. Each
source’s rms or root-sum-square contribution to noise is ob-
tained by integrating the sum of the squares of all the noise
sources and then by obtaining the square root of this sum. Mini-
mizing the total area under these curves will optimize the
preamplifier’s overall noise performance.
FILTERED
OUTPUT
OPTIONAL 26Hz
FILTER
Figure 30. The AD645 Used as a Sensitive Preamplifier
Preamplifier Applications
The low input current and offset voltage levels of the AD645 to-
gether with its low voltage noise make this amplifier an excellent
choice for preamplifiers used in sensitive photodiode applica-
tions. In a typical preamp circuit, shown in Figure 30, the out-
put of the amplifier is equal to:
Cf
10pF
Rf
109
Ω
V
OUT = ID (Rf) = Rp (P) Rf
where:
PHOTODIODE
en
ID = photodiode signal current (Amps)
i
f
i
Rp = photodiode sensitivity (Amp/Watt)
n
Rd
iS
iS
Cd
50pF
OUTPUT
Rf = the value of the feedback resistor, in ohms.
P = light power incident to photodiode surface, in watts.
An equivalent model for a photodiode and its dc error sources is
shown in Figure 31. The amplifier’s input current, IB, will con-
tribute an output voltage error which will be proportional to the
value of the feedback resistor. The offset voltage error, VOS, will
cause a “dark” current error due to the photodiode’s finite
shunt resistance, Rd. The resulting output voltage error, VE, is
equal to:
Figure 32. Noise Contributions of Various Sources
10µV
i
& i
f
s
SIGNAL BANDWIDTH
1µV
i
n
WITH FILTER
NO FILTER
VE = (1 + Rf/Rd) VOS + Rf IB
A shunt resistance on the order of 109 ohms is typical for a
small photodiode. Resistance Rd is a junction resistance which
will typically drop by a factor of two for every 10°C rise in tem-
perature. In the AD645, both the offset voltage and drift are
low, this helps minimize these errors.
100nV
e
n
en
10nV
1
10
100
1k
10k
100k
FREQUENCY – Hz
Cf
10pF
Figure 33. Voltage Noise Spectral Density of the Circuit of
Figure 32 With and Without an Output Filter
Rf
109
Ω
PHOTODIODE
VOS
An output filter with a passband close to that of the signal can
greatly improve the preamplifier’s signal to noise ratio. The pho-
todiode preamplifier shown in Figure 32—without a bandpass
filter—has a total output noise of 50 µV rms. Using a 26 Hz
single pole output filter, the total output noise drops to 23 µV
rms, a factor of 2 improvement with no loss in signal bandwidth.
IB
OUTPUT
Cd
50pF
Rd
ID
Figure 31. A Photodiode Model Showing DC Error
Sources
Using a “T” Network
A “T” network, shown in Figure 34, can be used to boost the ef-
fective transimpedance of an I to V converter, for a given feed-
back resistor value. Unfortunately, amplifier noise and offset
voltage contributions are also amplified by the “T” network
gain. A low noise, low offset voltage amplifier, such as the
AD645, is needed for this type of application.
Minimizing Noise Contributions
The noise level limits the resolution obtainable from any pream-
plifier. The total output voltage noise divided by the feedback
resistance of the op amp defines the minimum detectable signal
current. The minimum detectable current divided by the photo-
diode sensitivity is the minimum detectable light power.
REV. B
–7–
AD645
10pF
Guarding the input lines by completely surrounding them with a
metal conductor biased near the input lines’ potential has two
major benefits. First, parasitic leakage from the signal line is
reduced, since the voltage between the input line and the guard
is very low. Second, stray capacitance at the input terminal is
minimized which in turn increases signal bandwidth. In the
header or can package, the case of the AD645 is connected to
Pin 8 so that it may be tied to the input potential (when operat-
ing as a follower) or tied to ground (when operating as an in-
verter). The AD645’s positive input (Pin 3) is located next to
the negative supply voltage pin (Pin 4). The negative input (Pin
2) is next to the balance adjust pin (Pin 1) which is biased at a
potential close to that of the negative supply voltage. Note that
any guard traces should be placed on both sides of the board. In
addition, the input trace should be guarded along both of its
edges, along its entire length.
RG
10kΩ
Rf
Ri
108Ω
1.1kΩ
VOUT
AD645
PHOTODIODE
RG
)
Ri
f
R (1
+
VOUT = ID
Figure 34. A Photodiode Preamp Employing a “T”
Network for Added Gain
A pH Probe Buffer Amplifier
A typical pH probe requires a buffer amplifier to isolate its 106
to 109 Ω source resistance from external circuitry. Just such an
amplifier is shown in Figure 35. The low input current of the
AD645 allows the voltage error produced by the bias current
and electrode resistance to be minimal. The use of guarding,
shielding, high insulation resistance standoffs, and other such
standard methods used to minimize leakage are all needed to
maintain the accuracy of this circuit.
Contaminants such as solder flux, on the board’s surface and on
the amplifier’s package, can greatly reduce the insulation resis-
tance and also increase the sensitivity to atmospheric humidity.
Both the package and the board must be kept clean and dry. An
effective cleaning procedure is to: first, swab the surface with
high grade isopropyl alcohol, then rinse it with deionized water,
and finally, bake it at 80°C for 1 hour. Note that if either poly-
styrene or polypropylene capacitors are used on the printed cir-
cuit board that a baking temperature of 70°C is safer, since both
of these plastic compounds begin to melt at approximately
+85°C.
The slope of the pH probe transfer function, 50 mV per pH unit
at room temperature, has a +3300 ppm/°C temperature coeffi-
cient. The buffer of Figure 35 provides an output voltage equal
to 1 volt/pH unit. Temperature compensation is provided by
resistor RT which is a special temperature compensation resis-
tor, part number Q81, 1 kΩ, 1%, +3500 ppm/°C, available from
Tel Labs Inc.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
TO-99 Header (H) Package
REFERENCE PLANE
0.750 (19.05)
+15V
V
OS ADJUST
100kΩ
+VS
–VS
0.1µF
0.1µF
0.500 (12.70)
0.185 (4.70)
0.165 (4.19)
COM
–15V
0.250 (6.35)
MIN
0.050
(1.27)
MAX
0.100
(2.54)
BSC
–
VS
0.160 (4.06)
0.110 (2.79)
1
GUARD
4
5
3
2
OUTPUT
1VOLT/pH UNIT
5
6
8
4
2
0.335 (8.51)
0.305 (7.75)
6
AD645
0.045 (1.14)
0.027 (0.69)
0.200
(5.08)
BSC
7
7
3
pH
PROBE
0.370 (9.40)
0.335 (8.51)
8
19.6kΩ
+
VS
1
0.100
(2.54)
BSC
0.019 (0.48)
0.016 (0.41)
0.040 (1.02) MAX
RT
1kΩ
+3500ppm/°C
0.034 (0.86)
0.027 (0.69)
0.045 (1.14)
0.010 (0.25)
0.021 (0.53)
0.016 (0.41)
BASE & SEATING PLANE
45
°
BSC
Plastic Mini-DIP (N) Package
Figure 35. A pH Probe Amplifier
Circuit Board Notes
8
5
The AD645 is designed for through hole mount into PC boards.
Maintaining picoampere level resolution in that environment
requires a lot of care. Since both the printed circuit board and
the amplifier’s package have a finite resistance, the voltage dif-
ference between the amplifier’s input pin and other pins (or
traces on the PC board) will cause parasitic currents to flow into
(or out of) the signal path. These currents can easily exceed the
1.5 pA input current level of the AD645 unless special precau-
tions are taken. Two successful methods for minimizing leakage
are: guarding the AD645’s input lines and maintaining adequate
insulation resistance.
0.280 (7.11)
0.240 (6.10)
PIN 1
1
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
SEATING
PLANE
0.100
(2.54)
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
BSC
–8–
REV. B
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