AD7643 [ADI]
16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC; 16位750 kSPS时，单极/双极性可编程输入的PulSAR ADC
| 型号： | AD7643 |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC |
| 文件： | 总32页 (文件大小：829K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 750 kSPS, Unipolar/Bipolar
Programmable Input PulSAR® ADC
AD7612
FEATURES
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND
Multiple pins/software programmable input ranges:
5 V, 10 V, 5 V, 10 V
Pins or serial SPI®-compatible input ranges/mode selection
Throughput
750 kSPS (warp mode)
600 kSPS (normal mode)
OVDD
AGND
AD7612
REF
OGND
AVDD
PDREF
PDBUF
IN+
AMP
SERIAL DATA
PORT
REF
SERIAL
CONFIGURATION
PORT
16
SWITCHED
CAP DAC
D[15:0]
SER/PAR
BYTESWAP
OB/2C
BUSY
500 kSPS (impulse mode)
IN–
INL: 0.75 LSB typical, 1.5 LSB maximum ( 23 ppm of FSR)
16-bit resolution with no missing codes
SNR: 92 minimum (5 V) @ 2 kHz, 94 dB typical ( 10 V) @ 2 kHz
THD: −107 dB typical
PARALLEL
INTERFACE
CLOCK
CNVST
PD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
RD
RESET
CS
iCMOS™ process technology
5 V internal reference: typical drift 3 ppm/°C; TEMP output
No pipeline delay (SAR architecture)
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V interface
SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Power dissipation: 190 mW @ 750 kSPS
Pb-free, 48-lead LQFP and LFCSP (7 mm × 7 mm) packages
WARP IMPULSE BIPOLAR TEN
Figure 1.
Table 1. 48-Lead 14-/16-/18-Bit PulSAR Selection
100 kSPS to
250 kSPS
500 kSPS to
570 kSPS
800 kSPS to
1000 kSPS
>1000
kSPS
Type
Pseudo
AD7651
AD7660
AD7661
AD7650
AD7652
AD7664
AD7666
AD7653
AD7667
Differential
APPLICATIONS
Process control
Medical instruments
High speed data acquisition
Digital signal processing
Instrumentation
True Bipolar
AD7663
AD7675
AD7665
AD7612
AD7671
True
AD7676
AD7677
AD7621
AD7622
AD7623
Differential
Spectrum analysis
ATE
18-Bit, True
Differential
AD7678
AD7679
AD7674
AD7641
AD7643
Multichannel/
Simultaneous
AD7654
AD7655
GENERAL DESCRIPTION
The AD7612 is a 16-bit charge redistribution successive
approximation register (SAR), architecture analog-to-digital
converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS
high voltage process. The device is configured through hardware or
via a dedicated write only serial configuration port for input
range and operating mode. The AD7612 contains a high speed
16-bit sampling ADC, an internal conversion clock, an internal
reference (and buffer), error correction circuits, and both serial
PRODUCT HIGHLIGHTS
1. Programmable input range and mode selection.
Pins or serial port for selecting input range/mode select.
2. Fast throughput.
In warp mode, the AD7612 is 750 kSPS.
3. Superior Linearity.
No missing 16-bit code. 1.5 LSB max INL.
CNVST
and parallel system interface ports. A falling edge on
4. Internal Reference.
samples the analog input on IN+ with respect to a ground
sense, IN−. The AD7612 features four different analog input
ranges and three different sampling modes: warp mode for the
fastest throughput, normal mode for the fastest asynchronous
throughput, and impulse mode where power consumption is
scaled linearly with throughput. Operation is specified from
−40°C to +85°C.
5 V internal reference with a typical drift of 3 ppm/°C
and an on-chip temperature sensor.
5. Serial or Parallel Interface.
Versatile parallel (16- or 8-bit bus) or 2-wire serial interface
arrangement compatible with 3.3 V or 5 V logic.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD7612
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Inputs ............................................................................. 20
Driver Amplifier Choice ........................................................... 21
Voltage Reference Input/Output .............................................. 21
Power Supplies............................................................................ 22
Conversion Control ................................................................... 23
Interfaces.......................................................................................... 24
Digital Interface.......................................................................... 24
Parallel Interface......................................................................... 24
Serial Interface............................................................................ 25
Master Serial Interface............................................................... 25
Slave Serial Interface .................................................................. 27
Hardware Configuration........................................................... 29
Software Configuration............................................................. 29
Microprocessor Interfacing....................................................... 30
Application Information................................................................ 31
Layout Guidelines....................................................................... 31
Evaluating Performance ............................................................ 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Overview...................................................................................... 17
Converter Operation.................................................................. 17
Modes of Operation ................................................................... 18
Transfer Functions...................................................................... 18
Typical Connection Diagram ................................................... 19
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7612
SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range, VIN
VIN+ − VIN− = 0 V to 5 V
VIN+ − VIN− = 0V to 10 V
−0.1
−0.1
−5.1
−10.1
−0.1
+5.1
+10.1
+5.1
+10.1
+0.1
V
V
V
V
V
dB
μA
VIN+ − VIN−
VIN+ − VIN−
=
=
5 V
10 V
VIN− to AGND
fIN = 100 kHz
VIN = 5 V, 10 V @ 750 kSPS
See Analog Inputs section
Analog Input CMRR
Input Current
Input Impedance
75
2201
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time Between Conversions
Complete Cycle
Throughput Rate
In warp mode
In warp mode
In warp mode
In normal mode
In normal mode
In impulse mode
In impulse mode
1.33
7502
1
1.67
600
2
ꢀs
kSPS
ms
ꢀs
kSPS
ꢀs
1
0
0
Complete Cycle
Throughput Rate
500
kSPS
DC ACCURACY
Integral Linearity Error3
No Missing Codes3
−1.5
16
−1
0.75
+1.5
+1.5
+35
LSB4
Bits
LSB
LSB
LSB
ppm/°C
LSB
LSB
ppm/°C
LSB
Differential Linearity Error3
Transition Noise
0.55
1
Zero Error (Unipolar or Bipolar)
Zero Error Temperature Drift
Bipolar Full-Scale Error
Unipolar Full-Scale Error
Full-Scale Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
−35
−50
−70
+50
+70
1
3
AVDD = 5 V 5ꢁ
Dynamic Range
VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB
VIN = 0 V to 10 V, 5 V, fIN = 2 kHz, −60 dB
VIN = 10 V, fIN = 2 kHz, −60 dB
VIN = 0 V to 5 V, 0 V to 10 V, fIN = 2 kHz
VIN = 5 V, 10 V, fIN = 2 kHz
VIN = 5 V, fIN = 2 kHz
VIN = 0 V to 10 V, 5 V, fIN = 2 kHz
VIN = 10 V, fIN = 2 kHz
fIN = 2 kHz
92.5
92
93.5
94
94.5
93
94
92.5
93
93.5
−107
107
45
dB5
dB
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise Ratio
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion
Spurious-Free Dynamic Range
–3 dB Input Bandwidth
Aperture Delay
fIN = 2 kHz
VIN = 0 V to 5 V
dB
MHz
ns
2
Aperture Jitter
5
ps rms
ns
Transient Response
INTERNAL REFERENCE
Output Voltage
Temperature Drift
Line Regulation
Full-scale step
PDREF = PDBUF = low
REF @ 25°C
–40°C to +85°C
AVDD = 5 V 5ꢁ
1000 hours
500
4.965
5.000
3
5.035
V
ppm/°C
ppm/V
ppm
ms
15
Long-Term Drift
Turn-On Settling Time
50
10
CREF = 22 μF
Rev. 0 | Page 3 of 32
AD7612
Parameter
REFERENCE BUFFER
REFBUFIN Input Voltage Range
Conditions/Comments
PDREF = high
Min
2.4
Typ
Max
Unit
2.5
2.6
V
EXTERNAL REFERENCE
Voltage Range
PDREF = PDBUF = high
REF
4.75
5
AVDD + 0.1
V
Current Drain
750 kSPS throughput
250
μA
TEMPERATURE PIN
Voltage Output
Temperature Sensitivity
Output Resistance
@ 25°C
311
1
4.33
mV
mV/°C
kΩ
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
−0.3
2.1
−1
+0.6
OVDD + 0.3
+1
+1
V
V
μA
μA
−1
DIGITAL OUTPUTS
Data Format
Pipeline Delay6
Parallel or serial 16-bit
VOL
VOH
ISINK = 500 μA
ISOURCE = –500 μA
0.4
V
V
OVDD − 0.6
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
4.757
4.75
2.7
5
5
5.25
5.25
5.25
15.75
0
V
V
V
V
V
VCC
7
15
−15
VEE
−15.75
Operating Current8, 9
@ 750 kSPS throughput
AVDD
With Internal Reference
With Internal Reference Disabled
DVDD
OVDD
VCC
19.5
18
6.5
0.5
3
mA
mA
mA
mA
mA
mA
mA
VCC = 15 V, with internal reference buffer
VCC = 15 V
VEE = −15 V
2.3
2
VEE
Power Dissipation
@ 750 kSPS throughput
PDREF = PDBUF = low
PDREF = PDBUF = high
PD = high
With Internal Reference
With Internal Reference Disabled
In Power-Down Mode10
TEMPERATURE RANGE11
Specified Performance
205
190
10
230
210
mW
mW
μW
TMIN to TMAX
−40
+85
°C
1 With VIN = 0 V to 5 V or 0 V to 10 V ranges, the input current is typically 70 ꢀA. In all input ranges, the input current scales with throughput. See the Analog Inputs section.
2 All specified performance is guaranteed up to 750 kSPS throughout, however throughputs up to 900 kSPS can be used with some linearity performance degradation.
3 Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.
4 LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.
5 All specifications in decibels are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
6 Conversion results are available immediately after completed conversion.
7 4.75 V or VREF – 0.1 V, whichever is larger.
8 Tested in parallel reading mode.
9 With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.
10 With all digital inputs forced to OVDD.
11 Consult sales for extended temperature range.
Rev. 0 | Page 4 of 32
AD7612
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol Min
Typ
Max
Unit
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width
Time Between Conversions
t1
t2
10
ns
Warp Mode/Normal Mode/Impulse Mode1
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Warp Mode/Normal Mode/Impulse Mode
Aperture Delay
1.33/1.67/2
μs
ns
t3
t4
35
950/1250/1450 ns
t5
t6
t7
2
ns
ns
End of Conversion to BUSY Low Delay
Conversion Time
10
Warp Mode/Normal Mode/Impulse Mode
Acquisition Time
950/1250/1450 ns
t8
Warp Mode/Normal Mode/Impulse Mode
RESET Pulse Width
380
10
ns
ns
t9
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay
Warp Mode/Normal Mode/Impulse Mode
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
t10
910/1160/1410 ns
ns
t11
t12
t13
20
2
40
15
ns
ns
MASTER SERIAL INTERFACE MODES2 (See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay2
t14
t15
t16
t17
10
10
10
ns
ns
ns
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Asserted to SDCLK First Edge Delay
Internal SDCLK Period3
65/315/560
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
3
30
15
10
4
5
5
45
Internal SDCLK High3
Internal SDCLK Low3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SDCLK Last Edge to SYNC Delay3
CS High to SYNC HI-Z
10
10
10
CS High to Internal SDCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read After Convert3
CNVST Low to SYNC Delay, Read After Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Deasserted to BUSY Low Delay
See Table 4
t29
t30
830/1070/1310
25
ns
ns
Rev. 0 | Page 5 of 32
AD7612
Parameter
Symbol Min
Typ
Max
Unit
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2 (See Figure 42,
Figure 43, and Figure 45)
External SDCLK, SCCLK Setup Time
External SDCLK Active Edge to SDOUT Delay
SDIN/SCIN Setup Time
t31
t32
t33
t34
t35
t36
t37
5
2
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
SDIN/SCIN Hold Time
External SDCLK/SCCLK Period
External SDCLK/SCCLK High
External SDCLK/SCCLK Low
1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
2 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3 In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
t18
t19
t19
t20
t21
t22
t23
t24
0
1
0
1
Unit
SYNC to SDCLK First Edge Delay Minimum
Internal SDCLK Period Minimum
Internal SDCLK Period Maximum
Internal SDCLK High Minimum
Internal SDCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SDCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
Warp Mode
3
20
60
90
30
25
20
8
20
120
180
60
55
20
35
35
20
ns
ns
ns
ns
ns
ns
ns
ns
30
45
15
10
4
240
360
120
115
20
5
5
90
90
7
t28
1.65
1.9
2.15
2.35
2.6
2.85
3.75
4.00
4.25
6.53
6.78
7.03
μs
μs
μs
Normal Mode
Impulse Mode
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
2V
C
L
60pF
0.8V
tDELAY
tDELAY
500µA
I
OH
2V
2V
NOTES
0.8V
0.8V
1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD
C
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
L
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
Figure 3. Voltage Reference Levels for Timing
Rev. 0 | Page 6 of 32
AD7612
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
Analog Inputs/Outputs
IN+1, IN−1 to AGND
REF, REFBUFIN, TEMP,
REFGND to AGND
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
AVDD, DVDD, OVDD
AVDD to DVDD, AVDD to OVDD
DVDD to OVDD
VEE − 0.3 V to VCC + 0.3 V
AVDD + 0.3 V to
AGND − 0.3 V
0.3 V
ESD CAUTION
−0.3 V to +7 V
7 V
7 V
VCC to AGND, DGND
VEE to GND
Digital Inputs
PDREF, PDBUF2
–0.3 V to +16.5
+0.3 V to −16.5
−0.3 V to OVDD + 0 .3 V
20 mA
Internal Power Dissipation3
Internal Power Dissipation4
Junction Temperature
Storage Temperature Range
700 mW
2.5 W
125°C
−65°C to +125°C
1 See the Analog Inputs section.
2 See the Voltage Reference Input section.
3 Specification is for the device in free air: 48-Lead LFQP; θJA = 91°C/W,
θJC = 30°C/W.
4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.
Rev. 0 | Page 7 of 32
AD7612
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
AGND
BIPOLAR
CNVST
PD
PIN 1
2
3
AVDD
AGND
4
BYTESWAP
OB/2C
RESET
CS
5
AD7612
TOP VIEW
(Not to Scale)
6
WARP
RD
7
IMPULSE
SER/PAR
TEN
8
BUSY
9
D15/SCCS
D14/SCCLK
D13/SCIN
D12/HW/SW
D0
D1
10
11
12
D2/DIVSCLK[0]
D3/DIVSCLK[1]
13 14 15 16 17 18 19 20 21 22 23 24
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic
Type1 Description
1, 3, 42 AGND
P
Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be
referenced to AGND and should be connected to the analog ground plane of the system. In addition,
the AGND, DGND, and OGND voltages should be at the same potential.
2, 44
4
AVDD
BYTESWAP
P
DI
Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
6
OB/2C
WARP
DI2
DI2
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary.
When low, the MSB is inverted resulting in a twos complement output from its internal shift register.
Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following:
Conversion Mode WARP
IMPULSE
Low
High
Low
High
Normal
Impulse
Warp
Low
Low
High
High
Normal
See the Modes of Operation section for a more detailed description.
Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the
Modes of Operation section for a more detailed description.
7
8
IMPULSE
SER/PAR
DI2
DI
Serial/Parallel Selection Input.
When SER/PAR = low, the parallel mode is selected.
When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port
and the remaining data bits are high impedance outputs.
9, 10
D[0:1]
DO
Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the
state of SER/PAR.
11, 12
D[2:3] or
DI/O
In parallel mode, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
DIVSCLK[0:1]
Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high, EXT/INT
= low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data
clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
Rev. 0 | Page 8 of 32
AD7612
Pin No. Mnemonic
Type1 Description
13
D4 or
DI/O
In parallel mode, this output is used as Bit 4 of the parallel port data output bus.
EXT/INT
Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated
(master) or external (slave) serial data clock for the AD7612 output data.
When EXT/INT = low, master mode; the internal serial data clock is selected on SDCLK output.
When EXT/INT = high, slave mode; the output data is synchronized to an external clock signal (gated by CS)
connected to the SDCLK input.
14
D5 or
INVSYNC
DI/O
In parallel mode, this output is used as Bit 5 of the parallel port data output bus.
Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low). This input is used
to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15
16
D6 or
INVSCLK
DI/O
DI/O
In parallel mode, this output is used as Bit 6 of the parallel port data output bus.
In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.
In parallel mode, this output is used as Bit 7 of the parallel port data output bus.
D7 or
RDC or
Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low) RDC is used to
select the read mode. Refer to the Master Serial Interface section.
When RDC = low, the current result is read after conversion. Note the maximum throughput is not
attainable in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
SDIN
Serial Data In. In serial slave mode (SER/PAR = high EXT/INT = high) SDIN can be used as a data input to
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.
17
18
19
20
21
OGND
OVDD
DVDD
DGND
P
Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be
connected to the system digital ground ideally at the same potential as AGND and DGND.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors.
Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can be
supplied from AVDD.
Digital Power Ground. Ground reference point for digital outputs. Should be connected to system
digital ground ideally at the same potential as AGND and OGND.
P
P
P
D8 or
DO
In parallel mode, this output is used as Bit 8 of the parallel port data output bus.
SDOUT
Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK.
Conversion results are stored in an on-chip register. The AD7612 provides the conversion result, MSB
first, from its internal shift register. The data format is determined by the logic level of OB/2C.
When EXT/INT = low, (master mode) SDOUT is valid on both edges of SDCLK.
When EXT/INT = high, (slave mode).
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.
22
23
D9 or
SDCLK
DI/O
DO
In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent
on the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on
the logic state of the INVSCLK pin.
D10 or
SYNC
In parallel mode, this output is used as Bit 10 of the parallel port data output bus.
Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this output
is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while the
SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the
SDOUT output is valid.
Rev. 0 | Page 9 of 32
AD7612
Pin No. Mnemonic
Type1 Description
24
D11 or
DO
In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
RDERROR
Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an
incomplete data read error flag. If a data read is started and not completed when the current
conversion is complete, the current data is lost and RDERROR is pulsed high.
25
D12 or
DI/O
In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
HW/SW
Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure
the AD7612 by hardware or software. See the Hardware Configuration section and Software
Configuration section.
When HW/SW = low, the AD7612 is configured through software using the serial configuration register.
When HW/SW = high, the AD7612 is configured through dedicated hardware input pins.
In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low)
this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the Software Configuration section.
26
27
D13 or
SCIN
DI/O
DI/O
D14 or
SCCLK
In parallel mode, this output is used as Bit 14 of the parallel port data output bus.
Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this
input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on
the logic state of the INVSCLK pin. See the Software Configuration section.
28
29
D15 or
SCCS
DI/O
DO
In parallel mode, this output is used as Bit 15 of the parallel port data output bus.
Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low)
this input enables the serial configuration port. See the Software Configuration section.
Busy Output. Transitions high when a conversion is started, and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC = low) the busy time changes according to Table 4.
BUSY
30
TEN
DI2
Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range BIPOLAR TEN
0 V to 5 V
0 V to 10 V
5 V
Low
Low
High
High
Low
High
Low
High
10 V
31
32
RD
CS
DI
DI
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock in slave serial mode (not used for serial programmable port).
33
34
35
RESET
PD
DI
Reset Input. When high, reset the AD7612. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zero’s (with OB/2C = high) and clears the configuration register.
See the Digital Interface section. If not used, this pin can be tied to OGND.
Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power down.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
Input Range Select. See description for Pin 30.
DI2
CNVST
DI
36
37
BIPOLAR
REF
DI2
AI/O
Reference Input/Output.
When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally
supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or
without the internal reference and buffer. See the Reference Decoupling section.
38
39
40
41
REFGND
IN−
VCC
AI
AI
P
Reference Input Analog Ground. Connected to analog ground plane.
Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.
High Voltage Positive Supply. Normally +7 V to +15 V.
VEE
P
High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges).
Rev. 0 | Page 10 of 32
AD7612
Pin No. Mnemonic
Type1 Description
43
45
46
IN+
TEMP
REFBUFIN
AI
AO
AI
Analog Input. Referenced to IN−.
Temperature Sensor Analog Output.
Reference Buffer Input. When using an external reference with the internal reference buffer (PDBUF =
low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the Voltage Reference
Input section.
47
48
PDREF
PDBUF
DI
DI
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down, and an external reference must be used.
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
2
PAR
In serial configuration mode (SER/
SW
= high, HW/
= low), this input is programmed with the serial configuration register and this pin is a don’t care. See the
Hardware Configuration section and Software Configuration section.
Rev. 0 | Page 11 of 32
AD7612
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; TA = 25°C.
1.5
1.5
1.0
0.5
0
1.0
0.5
0
–0.5
–1.0
–1.5
–0.5
–1.0
0
16384
32768
CODE
49152
65536
0
16384
32768
CODE
49152
65536
Figure 5. Integral Nonlinearity vs. Code
Figure 8. Differential Nonlinearity vs. Code
180
160
140
120
100
80
180
160
140
120
100
80
NEGATIVE INL
POSITIVE INL
NEGATIVE DNL
POSITIVE DNL
60
60
40
40
20
20
0
0
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
–1.0 –0.8 –0.6 –0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
INL DISTRIBUTION (LSB)
DNL DISTRIBUTION (LSB)
Figure 6. Integral Nonlinearity Distribution (239 Devices)
Figure 9. Differential Nonlinearity Distribution (239 Devices)
200k
140k
130570
128400
σ = 0.55
σ = 0.52
181942
180k
160k
140k
120k
100k
80k
120k
100k
80k
60k
40k
20k
0
60k
47749
40k
31321
20k
1232
917
0
0
15
93
0
0
0
0
0
1
0
0
0
7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
CODE IN HEX
7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006 8007
CODE IN HEX
Figure 7. Histogram of 261,120 Conversions of a DC Input
at the Code Center
Figure 10. Histogram of 261,120 Conversions of a DC Input
at the Code Transition
Rev. 0 | Page 12 of 32
AD7612
0
–20
95.0
94.5
94.0
93.5
93.0
fS = 750kSPS
fIN = 19.99kHz
SNR = 93.23dB
THD = –107.5dB
SFDR = 113.9dB
SINAD = 93.1dB
±10V
±5V
SNR
SINAD
0V TO +10V
0V TO +5V
–40
–60
–80
–100
–120
–140
–160
–180
0
125
250
375
–60
–50
–40
–30
–20
–10
0
FREQUENCY (kHz)
INPUT LEVEL (dB)
Figure 11. FFT 20 kHz
Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale)
96
94
92
90
88
86
84
82
80
16.0
15.8
15.6
15.4
15.2
15.0
14.8
14.6
14.4
–70
120
110
100
90
SNR
SFDR
–80
–90
SINAD
80
ENOB
–100
–110
–120
–130
70
THD
60
THIRD
HARMONIC
50
40
SECOND
HARMONIC
30
20
100
1
10
100
1
10
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 15. THD, Harmonics, and SFDR vs. Frequency
Figure 12. SNR, SINAD, and ENOB vs. Frequency
96
96
95
94
93
92
91
90
±10V
±5V
0V TO +10V
0V TO +5V
±10V
±5V
0V TO +10V
0V TO +5V
95
94
93
92
91
90
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. SINAD vs. Temperature
Figure 13. SNR vs. Temperature
Rev. 0 | Page 13 of 32
AD7612
–96
–98
124
122
120
118
116
114
112
110
108
106
±10V
0V TO +10V
±5V
±5V
0V TO +10V
0V TO +5V
±10V
0V TO +5V
–100
–102
–104
–106
–108
–110
–112
–114
–116
–118
–120
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. THD vs. Temperature
Figure 20. SFDR vs. Temperature (Excludes Harmonics)
5
4
3
5.002
5.001
5.000
4.999
4.998
4.997
4.996
4.995
POSITIVE
FULL SCALE ERROR
2
1
ZERO
ERROR
0
NEGATIVE
FULL SCALE ERROR
–1
–2
–3
–4
–5
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature
Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices)
60
100000
10000
1000
100
50
40
30
20
10
0
10
1
AVDD, WARP/NORMAL
DVDD, ALL MODES
AVDD, IMPULSE
VCC +15V, VEE –15V,
ALL MODES
0.1
0.01
OVDD, ALL MODES
PDREF = PDBUF = HIGH
100 1000
SAMPLING RATE (SPS)
0.001
0
1
2
3
4
5
6
7
8
10
10000
100000
1000000
REFERENCE DRIFT (ppm/°C)
Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices)
Figure 22. Operating Currents vs. Sample Rate
Rev. 0 | Page 14 of 32
AD7612
50
45
40
35
30
25
20
15
10
5
700
600
500
400
300
200
100
0
PD = PDBUF = PDREF = HIGH
OVDD = 2.7V @ 85°C
OVDD = 2.7V @ 25°C
VEE, –15V
VCC, +15V
DVDD
OVDD = 5V @ 85°C
OVDD
AVDD
OVDD = 5V @ 25°C
0
0
50
100
(pF)
150
200
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
C
L
Figure 23. Power-Down Operating Currents vs. Temperature
Figure 24. Typical Delay vs. Load Capacitance CL
Rev. 0 | Page 15 of 32
AD7612
TERMINOLOGY
Least Significant Bit (LSB)
Total Harmonic Distortion (THD)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For an analog-to-digital con-
verter with N bits of resolution, the LSB expressed in volts is
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
VINp-p
LSB(V) =
2N
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full-scale through positive full-
scale. The point used as negative full-scale occurs a ½ LSB before
the first code transition. Positive full-scale is defined as a level
1½ LSBs beyond the last code transition. The deviation is meas-
ured from the middle of each code to the true straight line.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD and is expressed in bits by
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
ENOB = [(SINADdB − 1.76)/6.02]
Aperture Delay
Aperture delay is a measure of the acquisition performance
Bipolar Zero Error
The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.
CNVST
measured from the falling edge of the
input to when
the input signal is held for a conversion.
Transient Response
Unipolar Offset Error
The time required for the AD7612 to achieve its rated accuracy
after a full-scale step function is applied to its input.
The first transition should occur at a level ½ LSB above analog
ground. The unipolar offset error is the deviation of the actual
transition from that point.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF) meas-
ured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as
Full-Scale Error
The last transition (from 111…10 to 111…11) should occur for
an analog voltage 1½ LSB below the nominal full-scale. The full-
scale error is the deviation in LSB (or % of full-scale range) of
the actual level of the last transition from the ideal level and
includes the effect of the offset error. Closely related is the gain
error (also in LSB or % of full-scale range), which does not
include the effects of the offset error.
VREF (Max)–VREF (Min)
TCVREF (ppm/°C) =
where:
×106
VREF (25°C) × (TMAX –TMIN
)
V
V
V
REF (Max) = maximum VREF at TMIN, T(25°C), or TMAX.
Dynamic Range
REF (Min) = minimum VREF at TMIN, T(25°C), or TMAX
.
Dynamic range is the ratio of the rms value of the full-scale to
the rms noise measured for an input typically at −60 dB. The
value for dynamic range is expressed in decibels.
REF (25°C) = VREF at 25°C.
TMAX = +85°C.
MIN = –40°C.
T
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Rev. 0 | Page 16 of 32
AD7612
THEORY OF OPERATION
IN+
REF
REFGND
SWITCHES
CONTROL
SW
MSB
32,768C 16,384C
LSB
A
4C
2C
C
C
BUSY
CONTROL
LOGIC
COMP
IN–
OUTPUT
CODE
65,536C
SW
B
CNVST
Figure 25. ADC Simplified Schematic
OVERVIEW
CONVERTER OPERATION
The AD7612 is a very fast, low power, precise, 16-bit analog-to-
digital converter (ADC) using successive approximation capacitive
digital-to-analog (CDAC) architecture.
The AD7612 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The CDAC consists of two identical
arrays of 16 binary weighted capacitors, which are connected
to the two comparator inputs.
The AD7612 can be configured at any time for one of four input
ranges and conversion mode with inputs in parallel and serial
hardware modes or by a dedicated write only, SPI-compatible
interface via a configuration register in serial software mode.
The AD7612 uses Analog Device’s patented iCMOS high voltage
process to accommodate 0 to 5 V, 0 to 10 V, 5 V, and 10 V
input ranges without the use of conventional thin films. Only
one acquisition cycle, t8, is required for the inputs to latch to the
correct configuration. Resetting or power cycling is not
required for reconfiguring the ADC.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN− inputs. A conversion
phase is initiated once the acquisition phase is complete and the
CNVST
input goes low. When the conversion phase begins, SW+
and SW− are opened first. The two capacitor arrays are then
disconnected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between the inputs
(IN+ and IN−) captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND and REF, the comparator input varies
The AD7612 features different modes to optimize performance
according to the applications. It is capable of converting 750,000
samples per second (750 kSPS) in warp mode, 600 kSPS in normal
mode, and 500 kSPS in impulse mode.
The AD7612 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
by binary weighted voltage steps (VREF/2, VREF/4 through VREF
/
65536). The control logic toggles these switches, starting with
the MSB first, in order to bring the comparator back into a
balanced condition.
For unipolar input ranges, the AD7612 typically requires three
supplies; VCC, AVDD (which can supply DVDD), and OVDD
which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic.
For bipolar input ranges, the AD7612 requires the use of the
additional VEE supply.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output low.
The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP
7 mm × 7 mm packages that combine space savings with flexi-
bility. In addition, the AD7612 can be configured as either a
parallel or serial SPI-compatible interface.
Rev. 0 | Page 17 of 32
AD7612
Impulse Mode
MODES OF OPERATION
Setting WARP = low and IMPULSE = high uses the lowest power
dissipation mode and allows power saving between conversions.
The maximum throughput in this mode is 500 kSPS and in this
mode, the ADC powers down circuits after conversion making
the AD7612 ideal for battery-powered applications.
The AD7612 features three modes of operation: warp, normal,
and impulse. Each of these modes is more suitable to specific
applications. The mode is configured with the input pins, WARP
and IMPULSE, or via the configuration register. See Table 6 for
the pin details and the Hardware Configuration section and
Software Configuration section for programming the mode
selection with either pins or configuration register. Note that
when using the configuration register, the WARP and IMPULSE
inputs are don’t cares and should be tied to either high or low.
TRANSFER FUNCTIONS
2C
Using the OB/ digital input or via the configuration register,
the AD7612 offers two output codings: straight binary and twos
complement. See Figure 26 and Table 7 for the ideal transfer char-
acteristic and digital output codes for the different analog input
ranges, VIN. Note that when using the configuration register, the
Warp Mode
Setting WARP = high and IMPULSE = low allow the fastest con-
version rate up to 750 kSPS. However, in this mode, the full
specified accuracy is guaranteed only when the time between
conversions does not exceed 1 ms. If the time between two
consecutive conversions is longer than 1 ms (after power-up),
the first conversion result should be ignored since in warp mode,
the ADC performs a background calibration during the SAR
conversion process. This calibration can drift if the time between
conversions exceeds 1 ms thus causing the first conversion to
appear offset. This mode makes the AD7612 ideal for applications
where both high accuracy and fast sample rate are required. In
addition, the AD7612 can run up to 900 kSPS throughput with
some performance degradation, mainly dc linearity.
2C
OB/ input is a don’t care and should be tied to either high or low.
111...111
111...110
111...101
000...010
000...001
000...000
–FSR + 1 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
–FSR
Normal Mode
–FSR + 0.5 LSB
Setting WARP = IMPULSE = low or WARP = IMPULSE = high
allows the fastest mode (600 kSPS) without any limitation on
time between conversions. This mode makes the AD7612 ideal
for asynchronous applications such as data acquisition systems,
where both high accuracy and fast sample rate are required.
Figure 26. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
VREF = 5 V
Digital Output Code
Straight Binary Twos Complement
Description
FSR − 1 LSB
FSR − 2 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
VIN = 5 V
4.999924 V
4.999847 V
2.500076 V
2.5 V
2.499924 V
76.3 μV
0 V
VIN = 10 V
9.999847 V
9.999695 V
5.000153 V
5.000000 V
4.999847 V
152.6 μV
VIN
=
5 V
VIN = 10 V
+4.999847 V
+4.999695 V
+152.6 μV
0 V
−152.6 μV
−4.999847 V
−5 V
+9.999695 V
+9.999390 V
+305.2 μV
0 V
−305.2 μV
−9.999695 V
−10 V
0xFFFF1
0xFFFE
0x8001
0x8000
0x7FFF
0x0001
0x00002
0x7FFF1
0x7FFE
0x0001
0x0000
0xFFFF
0x8001
0x80002
0 V
1 This is also the code for overrange analog input (VIN+ − VIN− above VREF − VREFGND).
2 This is also the code for overrange analog input (VIN+ − VIN− below VREF − VREFGND).
Rev. 0 | Page 18 of 32
AD7612
TYPICAL CONNECTION DIAGRAM
Figure 27 shows a typical connection diagram for the AD7612 using the internal reference, serial data interface, and serial configuration
port. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections.
DIGITAL
SUPPLY (5V)
NOTE 5
DIGITAL
INTERFACE
SUPPLY
(2.5V, 3.3V, or 5V)
ANALOG
SUPPLY (5V)
100nF
10µF
10µF
100nF
100nF
10µF
AVDD AGND DGND
VCC
DVDD
OVDD
OGND
+7V TO +15.75V
SUPPLY
MICROCONVERTER/
MICROPROCESSOR/
DSP
BUSY
100nF
10µF
10µF
SDCLK
SDOUT
SERIAL
PORT 1
100nF
SCCLK
–7V TO –15.75V
SUPPLY
SERIAL
PORT 2
VEE
REF
SCIN
NOTE 6
NOTE 3
SCCS
C
REF
22µF
REFBUFIN
REFGND
NOTE 7
D
NOTE 4
100nF
CNVST
AD7612
OB/2C
NOTE 2
U1
OVDD
SER/PAR
IN+
HW/SW
ANALOG
INPUT +
BIPOLAR
C
2.7nF
C
TEN
WARP
CLOCK
ANALOG
INPUT–
IMPULSE
IN–
NOTE 3
PDREF PDBUF
NOTE 1
PD
RD
CS RESET
NOTES
1. SEE ANALOG INPUT SECTION. ANALOG INPUT(–) IS REFERENCED TO AGND ±0.1V.
2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION.
4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ4YB1A226M).
SEE VOLTAGE REFERENCE INPUT SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
6. THE VCC AND VEE SUPPLIES SHOULD BE VCC = [VIN(MAX) +2V] and VEE = [VIN(MIN) –2V] FOR BIPOLAR INPUT RANGES.
FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.
Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port
Rev. 0 | Page 19 of 32
AD7612
For instance, by using IN− to sense a remote signal ground,
ground potential differences between the sensor and the local
ADC ground are eliminated.
ANALOG INPUTS
Input Range Selection
In parallel mode and serial hardware mode, the input range is
selected by using the BIPOLAR (bipolar) and TEN (10 Volt range)
inputs. See Table 6 for pin details and the Hardware Configuration
section and Software Configuration section for programming
the mode selection with either pins or configuration register. Note
that when using the configuration register, the BIPOLAR and
TEN inputs are don’t cares and should be tied to either high or low.
100
90
80
70
60
50
40
30
20
10
0
Input Structure
Figure 28 shows an equivalent circuit for the input structure of
the AD7612.
0 TO 5V
RANGE ONLY
AVDD
VCC
1
10
100
1000
10000
FREQUENCY (kHz)
D1
D2
D3
D4
C
R
IN
IN
IN+ OR IN–
VEE
Figure 29. Analog Input CMRR vs. Frequency
C
PIN
During the acquisition phase for ac signals, the impedance of
the analog inputs, IN+ and IN−, can be modeled as a parallel
combination of Capacitor CPIN and the network formed by the
series connection of RIN and CIN. CPIN is primarily the pin capac-
itance. RIN is typically 70 Ω and is a lumped component comprised
of serial resistors and the on resistance of the switches. CIN is pri-
marily the ADC sampling capacitor and depending on the input
range selected is typically 48 pF in the 0 V to 5 V range, typically
24 pF in the 0 V to 10 V and 5 V ranges and typically 12 pF in
the 10 V range. During the conversion phase, when the switches
AGND
Figure 28. AD7612 Simplified Analog Input
The four diodes, D1 to D4, provide ESD protection for the analog
inputs, IN+ and IN−. Care must be taken to ensure that the analog
input signal never exceeds the supply rails by more than 0.3 V,
because this causes the diodes to become forward-biased and to
start conducting current. These diodes can handle a forward-
biased current of 120 mA maximum. For instance, these conditions
could eventually occur when the input buffer’s U1 supplies are
different from AVDD, VCC, and VEE. In such a case, an input
buffer with a short-circuit current limitation can be used to protect
the part although most op amps’ short circuit current is <100 mA.
Note that D3 and D4 are only used in the 0 V to 5 V range to
allow for additional protection in applications that are switching
from the higher voltage ranges.
are opened, the input impedance is limited to CPIN
.
Since the input impedance of the AD7612 is very high, it can be
directly driven by a low impedance source without gain error. To
further improve the noise filtering achieved by the AD7612 analog
input circuit, an external, one-pole RC filter between the ampli-
fier’s outputs and the ADC analog inputs can be used, as shown
in Figure 27. However, large source impedances significantly
affect the ac performance, especially total harmonic distortion
(THD). The maximum source impedance depends on the amount
of THD that can be tolerated. The THD degrades as a function
of the source impedance and the maximum input frequency.
This analog input structure allows the sampling of the differential
signal between IN+ and IN−. By using this differential input,
small signals common to both inputs are rejected as shown in
Figure 29, which represents the typical CMRR over frequency.
Rev. 0 | Page 20 of 32
AD7612
The AD8021 meets these requirements and is appropriate for
DRIVER AMPLIFIER CHOICE
almost all applications. The AD8021 needs a 10 pF external
compensation capacitor that should have good linearity as an
NPO ceramic or mica type. Moreover, the use of a noninverting
+1 gain arrangement is recommended and helps to obtain the
best signal-to-noise ratio.
Although the AD7612 is easy to drive, the driver amplifier must
meet the following requirements:
•
For multichannel, multiplexed applications, the driver
amplifier and the AD7612 analog input circuit must be
able to settle for a full-scale step of the capacitor array at
a 16-bit level (0.0015%). For the amplifier, settling at 0.1%
to 0.01% is more commonly specified. This differs signifi-
cantly from the settling time at a 16-bit level and should
be verified prior to driver selection. The AD8021 op amp
combines ultra-low noise and high gain bandwidth and
meets this settling time requirement even when used with
gains of up to 13.
The AD8022 can also be used when a dual version is needed
and a gain of 1 is present. The AD829 is an alternative in appli-
cations where high frequency (above 100 kHz) performance is not
required. In applications with a gain of 1, an 82 pF compensation
capacitor is required. The AD8610 is an option when low bias
current is needed in low frequency applications.
Since the AD7612 uses a large geometry, high voltage input
switch, the best linearity performance is obtained when using
the amplifier at its maximum full power bandwidth. Gaining
the amplifier to make use of the more dynamic range of the
ADC results in increased linearity errors. For applications
requiring more resolution, the use of an additional amplifier
with gain should precede a unity follower driving the AD7612.
See Table 8 for a list of recommended op amps.
•
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7612. The noise coming from
the driver is filtered by the external 1-pole low-pass filter
as shown in Figure 27. The SNR degradation due to the
amplifier is
⎛
⎜
⎞
⎟
Table 8. Recommended Driver Amplifiers
VNADC
⎜
⎜
⎟
⎟
Amplifier
Typical Application
SNRLOSS = 20log
π
2
2
⎜
⎜
⎟
⎟
VNADC
+
f−3dB
(NeN
)
ADA4841-x
12 V supply, very low noise, low distortion,
low power, low frequency
2
⎝
⎠
AD829
AD8021
AD8022
15 V supplies, very low noise, low frequency
12 V supplies, very low noise, high frequency
12 V supplies, very low noise, high
frequency, dual
where:
V
NADC is the noise of the ADC, which is:
VINp-p
2 2
AD8610/AD8620
13 V supplies, low bias current, low
frequency, single/dual
VNADC
=
SNR
20
10
VOLTAGE REFERENCE INPUT/OUTPUT
f
–3dB is the cutoff frequency of the input filter (3.9 MHz).
The AD7612 allows the choice of either a very low temperature
drift internal voltage reference, an external reference or an external
buffered reference.
N is the noise factor of the amplifier (+1 in buffer
configuration).
eN is the equivalent input voltage noise density of the op
amp, in nV/√Hz.
The internal reference of the AD7612 provides excellent perfor-
mance and can be used in almost all applications. However, the
linearity performance is guaranteed only with an external reference.
•
The driver needs to have a THD performance suitable to
that of the AD7612. Figure 15 shows the THD vs. frequency
that the driver should exceed.
Rev. 0 | Page 21 of 32
AD7612
Temperature Sensor
Internal Reference (REF = 5 V)
(PDREF = Low, PDBUF = Low)
The TEMP pin measures the temperature of the AD7612. To
improve the calibration accuracy over the temperature range, the
output of the TEMP pin is applied to one of the inputs of the
analog switch (such as ADG779), and the ADC itself is used to
measure its own temperature. This configuration is shown
in Figure 30.
To use the internal reference, the PDREF and PDBUF inputs
must be low. This enables the on-chip band gap reference, buffer,
and TEMP sensor resulting in a 5.00 V reference on the REF pin.
The internal reference is temperature-compensated to 5.000 V
35 mV. The reference is trimmed to provide a typical drift of
3 ppm/°C. This typical drift characteristic is shown in Figure 19.
TEMP
ADG779
AD8021
External 2.5 V Reference and Internal Buffer (REF = 5 V)
(PDREF = High, PDBUF = Low)
TEMPERATURE
IN+
ANALOG INPUT
(UNIPOLAR)
SENSOR
AD7612
C
C
To use an external reference with the internal buffer, PDREF
should be high and PDBUF should be low. This powers down
the internal reference and allows the 2.5 V reference to be applied
to REFBUFIN producing 5 V on the REF pin. The internal ref-
erence buffer is useful in multiconverter applications since a
buffer is typically required in these applications.
Figure 30. Use of the Temperature Sensor
POWER SUPPLIES
The AD7612 uses five sets of power supply pins:
•
•
•
•
•
AVDD: analog 5 V core supply
External 5 V Reference (PDREF = High, PDBUF = High)
VCC: analog high voltage positive supply
VEE: high voltage negative supply
DVDD: digital 5 V core supply
To use an external reference directly on the REF pin, PDREF
and PDBUF should both be high. PDREF and PDBUF power
down the internal reference and the internal reference buffer,
respectively. For improved drift performance, an external ref-
erence such as the ADR445 or ADR435 is recommended.
OVDD: digital input/output interface supply
Reference Decoupling
Core Supplies
Whether using an internal or external reference, the AD7612
voltage reference input (REF) has a dynamic input impedance;
therefore, it should be driven by a low impedance source with
efficient decoupling between the REF and REFGND inputs. This
decoupling depends on the choice of the voltage reference, but
usually consists of a low ESR capacitor connected to REF and
REFGND with minimum parasitic inductance. A 22 μF (X5R,
1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor)
is appropriate when using either the internal reference or the
ADR445/ADR435 external reference.
The AVDD and DVDD supply the AD7612 analog and digital
cores respectively. Sufficient decoupling of these supplies is
required consisting of at least a 10 ꢀF capacitor and 100 nF on
each supply. The 100 nF capacitors should be placed as close as
possible to the AD7612. To reduce the number of supplies needed,
the DVDD can be supplied through a simple RC filter from the
analog supply, as shown in Figure 27.
High Voltage Supplies
The high voltage bipolar supplies, VCC and VEE are required
and must be at least 2 V larger than the maximum input, VIN.
For example, if using the bipolar 10 V range, the supplies should
be 12 V minimum. Sufficient decoupling of these supplies is
also required consisting of at least a 10 ꢀF capacitor and 100 nF
on each supply. For unipolar operation, the VEE supply can be
grounded with some slight THD performance degradation.
The placement of the reference decoupling is also important to
the performance of the AD7612. The decoupling capacitor should
be mounted on the same side as the ADC right at the REF pin
with a thick PCB trace. The REFGND should also connect to
the reference decoupling capacitor with the shortest distance
and to the analog ground plane with several vias.
For applications that use multiple AD7612 or other PulSAR
devices, it is more effective to use the internal reference buffer
to buffer the external 2.5 V reference voltage.
Digital Output Supply
The OVDD supplies the digital outputs and allows direct interface
with any logic working between 2.3 V and 5.25 V. OVDD should
be set to the same level as the system interface. Sufficient decou-
pling is required consisting of at least a 10 ꢀF capacitor and 100 nF
with the 100 nF placed as close as possible to the AD7612.
The voltage reference temperature coefficient (TC) directly impacts
full scale; therefore, in applications where full-scale accuracy
matters, care must be taken with the TC. For instance, a
15 ppm/°C TC of the reference changes full-scale by 1 LSB/°C.
Rev. 0 | Page 22 of 32
AD7612
Power Down
Power Sequencing
Setting PD = high powers down the AD7612, thus reducing
supply currents to their minimums as shown in Figure 23. When
the ADC is in power down, the current conversion (if any) is
completed and the digital bus remains active. To further reduce
the digital supply currents, drive the inputs to OVDD or OGND.
The AD7612 is independent of power supply sequencing and is
very insensitive to power supply variations on AVDD over a wide
frequency range as shown in Figure 31.
80
EXT REF
75
INT REF
70
Power down can also be programmed with the configuration
register. See the Software Configuration section for details. Note
that when using the configuration register, the PD input is a
don’t care and should be tied to either high or low.
65
60
55
50
45
40
35
30
CONVERSION CONTROL
CNVST
The AD7612 is controlled by the
input. A falling edge
CNVST
on
is all that is necessary to initiate a conversion. Detailed
timing diagrams of the conversion process are shown in Figure 33.
Once initiated, it cannot be restarted or aborted, even by the
power-down input, PD, until the conversion is complete. The
1
10000
10
100
1000
CNVST
CS
RD
signal operates independently of
and signals.
FREQUENCY (kHz)
Figure 31. AVDD PSRR vs. Frequency
t2
t1
Power Dissipation vs. Throughput
CNVST
BUSY
In impulse mode, the AD7612 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows
a significant power savings when the conversion rate is reduced
(see Figure 32). This feature makes the AD7612 ideal for very
low power, battery-operated applications.
t4
t3
t6
t5
MODE
ACQUIRE
CONVERT
t7
ACQUIRE
t8
CONVERT
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital supply
currents even further, drive the digital inputs close to the power
rails (that is, OVDD and OGND).
Figure 33. Basic Conversion Timing
CNVST
Although
is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot, undershoot, or ringing.
1000
PDREF = PDBUF = HIGH
CNVST
The
trace should be shielded with ground and a low value
(such as 50 Ω) serial resistor termination should be added close
to the output of the component that drives this line.
WARP MODE POWER
100
10
1
CNVST
For applications where SNR is critical, the
have very low jitter. This can be achieved by using a dedicated
CNVST CNVST
with a
signal should
oscillator for
generation, or by clocking
IMPULSE MODE POWER
high frequency, low jitter clock, as shown in Figure 27.
1
10
100
1000
SAMPLING RATE (kSPS)
Figure 32. Power Dissipation vs. Sample Rate
Rev. 0 | Page 23 of 32
AD7612
INTERFACES
CS = RD = 0
CNVST
DIGITAL INTERFACE
t1
The AD7612 has a versatile digital interface that can be set up
as either a serial or a parallel interface with the host system. The
serial interface is multiplexed on the parallel data bus. The AD7612
digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In
most applications, the OVDD supply pin is connected to the host
system interface 2.5 V to 5.25 V digital supply. Finally, by using
t10
BUSY
t4
t3
t11
DATA
BUS
PREVIOUS CONVERSION DATA
NEW DATA
2C
the OB/ input pin, both twos complement or straight binary
coding can be used.
Figure 35. Master Parallel Data Timing for Reading (Continuous Read)
CS
Two signals, and
RD
, control the interface. When at least one of
Slave Parallel Interface
these signals is high, the interface outputs are in high impedance.
CS
In slave parallel reading mode, the data can be read either after
each conversion, which is during the next acquisition phase, or
during the following conversion, as shown in Figure 36 and
Figure 37, respectively. When the data is read during the conver-
sion, it is recommended that it is read only during the first half
of the conversion phase. This avoids any potential feedthrough
between voltage transients on the digital interface and the most
critical analog conversion circuitry.
Usually,
allows the selection of each AD7612 in multi-circuit
RD
applications and is held low in a single AD7612 design.
is gen-
erally used to enable the conversion result on the data bus.
RESET
The RESET input is used to reset the AD7612. A rising edge on
RESET aborts the current conversion (if any) and tristates the
data bus. The falling edge of RESET resets the AD7612 and clears
the data bus and configuration register. See Figure 34 for the
RESET timing details.
CS
t9
RESET
RD
BUSY
BUSY
DATA
BUS
t8
DATA
BUS
CURRENT
CONVERSION
CNVST
t12
t13
Figure 34. RESET Timing
Figure 36. Slave Parallel Data Timing for Reading (Read After Convert)
PARALLEL INTERFACE
The AD7612 is configured to use the parallel interface when
CS = 0
PAR
SER/
is held low.
CNVST,
t1
RD
Master Parallel Interface
CS
RD
low, thus
Data can be continuously read by tying
and
requiring minimal microprocessor connections. However, in
this mode, the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 35 details the timing for this mode.
BUSY
t4
t3
DATA
BUS
PREVIOUS
CONVERSION
t12
t13
Figure 37. Slave Parallel Data Timing for Reading (Read During Convert)
Rev. 0 | Page 24 of 32
AD7612
MASTER SERIAL INTERFACE
8-Bit Interface (Master or Slave)
The pins multiplexed on D[10:2] and used for master serial inter-
INT
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 38, when BYTESWAP is low, the LSB byte is
output on D[7:0] and the MSB is output on D[15:8]. When
BYTESWAP is high, the LSB and MSB bytes are swapped; the
LSB is output on D[15:8] and the MSB is output on D[7:0]. By
connecting BYTESWAP to an address line, the 16-bit data can
be read in two bytes on either D[15:8] or D[7:0]. This interface
can be used in both master and slave parallel reading modes.
face are DIVSCLK[0], DIVSCLK[1], EXT/
INVSCLK, RDC, SDOUT, SDCLK and SYNC.
, INVSYNC,
PAR
INT
= Low)
Internal Clock (SER/
= high, EXT/
The AD7612 is configured to generate and provide the serial
INT
data clock, SDCLK, when the EXT/
pin is held low. The
AD7612 also generates a SYNC signal to indicate to the host
when the serial data is valid. The SDCLK, and the SYNC sig-
nals can be inverted, if desired using the INVSCLK and INVSYNC
inputs, respectively. Depending on the input, RDC, the data can
be read during the following conversion or after each conver-
sion. Figure 39 and Figure 40 show detailed timing diagrams of
these two modes.
CS
RD
BYTESWAP
Read During Convert (RDC = High)
Setting RDC = high allows the master read (previous conversion
result) during conversion mode. Usually, because the AD7612 is
used with a fast throughput, this mode is the most recommended
serial mode. In this mode, the serial clock and data toggle at appro-
priate instances, minimizing potential feed through between digital
activity and critical conversion decisions. In this mode, the SDCLK
period changes since the LSBs require more time to settle and
the SDCLK is derived from the SAR conversion cycle. In this
mode, the AD7612 generates a discontinuous SDCLK of two
different periods and the host should use an SPI interface.
HI-Z
HI-Z
HI-Z
HI-Z
PINS D[15:8]
PINS D[7:0]
HIGH BYTE
LOW BYTE
t12
LOW BYTE
t12
t13
HIGH BYTE
Figure 38. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7612 has a serial interface (SPI-compatible) multiplexed
on the data pins D[15:2]. The AD7612 is configured to use the
PAR
serial interface when SER/
is held high.
Read During Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3])
Setting RDC = low allows the read after conversion mode. Unlike
the other serial modes, the BUSY signal returns low after the 16
data bits are pulsed out and not at the end of the conversion phase,
resulting in a longer BUSY width (refer to Table 4 for BUSY timing
specifications). The DIVSCLK[1:0] inputs control the SDCLK
period and SDOUT data rate. As a result, the maximum through-
put cannot be achieved in this mode. In this mode, the AD7612
also generates a discontinuous SDCLK however, a fixed period and
hosts supporting both SPI and serial ports can also be used.
Data Interface
The AD7612 outputs 16 bits of data, MSB first, on the SDOUT
pin. This data is synchronized with the 16 clock pulses provided
on the SDCLK pin. The output data is valid on both the rising
and falling edge of the data clock.
Serial Configuration Interface
The AD7612 can be configured through the serial configuration
register only in serial mode as the serial configuration pins are
also multiplexed on the data pins D[15:12]. Refer to the Hardware
Configuration section and Software Configuration section for
more information.
Rev. 0 | Page 25 of 32
AD7612
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
EXT/INT = 0
CS, RD
CNVST
t3
t28
BUSY
SYNC
t30
t29
t25
t18
t19
t14
t24
t20
t21
2
t26
1
3
14
15
16
SDCLK
SDOUT
t15
t27
D15
D14
t23
D2
D1
D0
X
t16
t22
Figure 39. Master Serial Data Timing for Reading (Read After Convert)
EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0
CS, RD
t1
CNVST
BUSY
t3
t17
t25
SYNC
t19
t14
t20 t21
t24
t26
t15
SDCLK
SDOUT
1
2
3
14
15
16
t18
t27
X
D15
D14
t23
D2
D1
D0
t16
t22
Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
Rev. 0 | Page 26 of 32
AD7612
edge of SDCLK used to shift out the data on SDOUT (SDCLK
falling edge when INVSCLK = low). Therefore, the MSB of the
upstream converter follows the LSB of the downstream con-
verter on the next SDCLK cycle. In this mode, the 40 MHz
SDCLK rate cannot be used since the SDIN to SDCLK setup
time, t33, is less than the minimum time specified. (SDCLK to
SDOUT delay, t32, is the same for all converters when simul-
taneously sampled). For proper operation, the SDCLK edge for
latching SDIN (or ½ period of SDCLK) needs to be:
SLAVE SERIAL INTERFACE
The pins multiplexed on D[11:4] used for slave serial
INT
interface are: EXT/
, INVSCLK, SDIN, SDOUT,
SDCLK and RDERROR.
PAR
INT
= High, EXT/
External Clock (SER/
= High)
INT
Setting the EXT/
= high allows the AD7612 to accept an
externally supplied serial data clock on the SDCLK pin. In this
mode, several methods can be used to read the data. The exter-
t1/ 2SDCLK = t32 + t33
CS
CS
RD
nal serial clock is gated by . When
and are both low,
Or the max SDCLK frequency needs to be:
1
the data can be read after each conversion or during the following
conversion. A clock can be either normally high or normally low
when inactive. For detailed timing diagrams, see Figure 42 and
Figure 43.
fSDCLK
=
2(t32 +t33 )
If not using the daisy-chain feature, the SDIN input should be
tied either high or low.
While the AD7612 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins,
or degradation of the conversion result may occur. This is par-
ticularly important during the last 475 ns of the conversion phase
because the AD7612 provides error correction circuitry that can
correct for an improper bit decision made during the first part
of the conversion phase. For this reason, it is recommended that
any external clock provided, is a discontinuous clock that transi-
tions only when BUSY is low, or, more importantly, that it does not
transition during the last 475 ns of BUSY high.
BUSY
OUT
BUSY
BUSY
AD7612
AD7612
#2
#1
(UPSTREAM)
(DOWNSTREAM)
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
CNVST
CS
CNVST
CS
SCLK
SCLK
External Discontinuous Clock Data Read After
Conversion
SCLK IN
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 42 shows the detailed timing diagrams for this method.
After a conversion is complete, indicated by BUSY returning low,
CS IN
CNVST IN
Figure 41. Two AD7612 Devices in a Daisy-Chain Configuration
External Clock Data Read During Previous Conversion
CS
RD
the conversion result can be read while both
and
are low.
Figure 43 shows the detailed timing diagrams for this method.
During a conversion, while both
Data is shifted out MSB first with 16 clock pulses and, depending
on the SDCLK frequency, can be valid on the falling and rising
edges of the clock.
CS
RD
and
are low, the result
of the previous conversion can be read. Data is shifted out MSB
first with 16 clock pulses and, depending on the SDCLK frequency,
can be valid on the falling and rising edges of the clock. The
16 bits have to be read before the current conversion is complete;
otherwise, RDERROR is pulsed high and can be used to interrupt
the host interface to prevent incomplete data reading.
One advantage of this method is that conversion performance is
not degraded because there are no voltage transients on the digital
interface during the conversion process. Another advantage is
the ability to read the data at any speed up to 40 MHz, which
accommodates both the slow digital host interface and the fastest
serial reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 40 MHz is recommended to ensure
that all the bits are read during the first half of the SAR
conversion phase.
Daisy-Chain Feature
Also in the read after convert mode, the AD7612 provides a daisy-
chain feature for cascading multiple converters together using
the serial data input, SDIN, pin. This feature is useful for reduce-
ing component count and wiring connections when desired, for
instance, in isolated multiconverter applications. See Figure 42
for the timing details.
The daisy-chain feature should not be used in this mode since
digital activity occurs during the second half of the SAR
conversion phase likely resulting in performance degradation.
An example of the concatenation of two devices is shown in
Figure 41. Simultaneous sampling is possible by using a common
CNVST
signal. Note that the SDIN input is latched on the opposite
Rev. 0 | Page 27 of 32
AD7612
discontinuous SDCLK whenever possible to minimize potential
incorrect bit decisions. For the different modes, the use of a slower
SDCLK such as 20 MHz in warp mode, 15 MHz in normal mode
and 13 MHz in impulse mode can be used.
External Clock Data Read After/During Conversion
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion has been
initiated. This method allows the full throughput and the use of
a slower SDCLK frequency. Again, it is recommended to use a
SER/PAR = 1 EXT/INT = 1 INVSCLK = 0 RD = 0
CS
BUSY
t31
t35
t36
t31
SDCLK
X*
1
2
3
4
14
15
16
17
18
19
t32
t37
SDOUT
SDIN
D15
X15
X15
Y15
X14
Y14
D14
X14
D13
D2
X2
D1
X1
D0
X0
t16
X13
t33
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
t34
Figure 42. Slave Serial Data Timing for Reading (Read After Convert)
SER/PAR = 1 EXT/INT = 1 INVSCLK = 0
RD = 0
CS
CNVST
BUSY
t35
t36
16
t31
t31
SDCLK
X*
X*
X*
X*
X*
X*
1
2
3
15
t32
t37
D1
DATA = SDIN
t27
SDOUT
D15
D0
D14
t16
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
Figure 43. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
Rev. 0 | Page 28 of 32
AD7612
recommended to write to the SCP during the last 475 ns of con-
version (BUSY = high) or performance degradation can result.
In addition, the SCP can be accessed in both serial master and
serial slave read during and read after convert modes.
HARDWARE CONFIGURATION
The AD7612 can be configured at any time with the dedicated
hardware pins WARP, IMPULSE, BIPOLAR, TEN, OB/ , and
2C
PAR
PD for parallel mode (SER/
= low) or serial hardware mode
PAR SW
(SER/
= high, HW/
= high). Programming the AD7612
Note that at power up, the configuration register is undefined.
The RESET input clears the configuration register (sets all bits
to 0), thus placing the configuration to 0 V to 5 V input, normal
mode, and twos complemented output.
for mode selection and input range configuration can be done
before or during conversion. Like the RESET input, the ADC
requires at least one acquisition time to settle as indicated in
Figure 44. See Table 6 for pin descriptions. Note that these inputs
are high impedance when using the software configuration mode.
Table 9. Configuration Register Description
Bit Name
Description
8
START
SCCS
START bit. With the SCP enabled ( = low),
SOFTWARE CONFIGURATION
when START is high, the first rising edge of SCCLK
(INVSCLK = low) begins to load the register with
the new configuration.
Input Range Select. Used in conjunction with
Bit 6, TEN, per the following:
The pins multiplexed on D[15:12] used for software configura-
SW
SCCS
tion are: HW/ , SCIN, SCCLK, and
. The AD7612 is
7
BIPOLAR
programmed using the dedicated write-only serial configurable
port (SCP) for conversion mode, input range selection, output
coding, and power-down using the serial configuration register.
See Table 9 for details of each bit in the configuration register.
The SCP can only be used in serial software mode selected with
Input Range
0 V to 5 V
0 V to 10 V
5 V
BIPOLAR
Low
Low
High
Low
TEN
Low
High
Low
High
PAR
SER/
SW
= high and HW/
= low since the port is multiplexed
10 V
on the parallel interface.
6
5
TEN
PD
Input Range Select. See Bit 7, BIPOLAR.
Power Down.
PD = Low, normal operation.
SCCS
The SCP is accessed by asserting the port’s chip select,
,
and then writing SCIN synchronized with SCCLK, which (like
SDCLK) is edge sensitive depending on the state of INVSCLK.
See Figure 45 for timing details. SCIN is clocked into the con-
figuration register MSB first. The configuration register is an
internal shift register that begins with Bit 8, the start bit. The 9th
SPPCLK edge updates the register and allows the new settings to be
used. As indicated in the timing diagram, at least one acquisition
time is required from the 9th SCCLK edge. Bits [1:0] are reserved
bits and are not written to while the SCP is being updated.
PD = High, power down the ADC. The SCP is accessi-
ble while in power down. To power up the ADC,
write PD = low on the next configuration setting.
4
IMPULSE Mode Select. Used in conjunction with Bit 3,
WARP per the following:
Mode
WARP
Low
Low
High
High
IMPULSE
Low
High
Low
High
Normal
Impulse
Warp
Normal
3
2
WARP
Mode Select. See Bit 4, IMPULSE.
Output Coding
2C
OB/ = Low, use twos complement output.
The SCP can be written to at any time, up to 40 MHz, and it is
recommended to write to while the AD7612 is not busy convert-
ing, as detailed in Figure 45. In this mode, the full 750 kSPS is not
attainable because the time required for SCP access is (t31 + 8 × 1/
SCCLK +t8) minimum. If the full throughput is required, the
SCP can be written to during conversion, however it is not
2C
OB/
2C
OB/ = High, use straight binary output.
1
0
RSV
RSV
Reserved.
Reserved.
HW/SW = 0
PD = 0
SER/PAR = 0, 1
t8
t8
CNVST
BUSY
BIPOLAR,
TEN
WARP,
IMPULSE
Figure 44. Hardware Configuration Timing
Rev. 0 | Page 29 of 32
AD7612
SER/PAR = 1 INVSCLK = 0
WARP = 0 OR 1
BIP = 0 OR 1
TEN = 0 OR 1
t8
HW/SW = 0
PD = 0
IMPULSE = 0 OR 1
CNVST
BUSY
t31
SCCS
t31
t35
t36
5
SCCLK
1
2
3
4
6
7
8
9
t37
t34
SCIN
X
IMPULSE
OB/2C
BIPOLAR
TEN
PD
WARP
START
X
t33
Figure 45. Serial Configuration Port Timing
the DSP. The serial peripheral interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable
(TIMOD) = 0 by writing to the SPI control register (SPICLTx).
MICROPROCESSOR INTERFACING
The AD7612 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal processing
applications interfacing to a digital signal processor. The AD7612
is designed to interface with a parallel 8-bit or 16-bit wide
interface, or with a general-purpose serial port or I/O ports on a
microcontroller. A variety of external buffers can be used with
the AD7612 to prevent digital noise from coupling into the ADC.
It should be noted that to meet all timing requirements, the SPI
clock should be limited to 17 Mbps allowing it to read an ADC
result in less than 1 μs. When a higher sampling rate is desired,
use one of the parallel interface modes.
SPI Interface
DVDD
AD76121
1
ADSP-219x
The AD7612 is compatible with SPI and QSPI digital hosts and
DSPs such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x.
Figure 46 shows an interface diagram between the AD7612 and
the SPI-equipped ADSP-219x. To accommodate the slower speed
of the DSP, the AD7612 acts as a slave device, and data must be
read after conversion. This mode also allows the daisy-chain
feature. The convert command could be initiated in response to
an internal timer interrupt.
SER/PAR
BUSY
CS
PFx
EXT/INT
SPIxSEL (PFx)
MISOx
SDOUT
SCLK
CNVST
RD
SCKx
PFx OR TFSx
INVSCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. Interfacing the AD7612 to SPI Interface
The reading process can be initiated in response to the end-of-
conversion signal (BUSY going low) using an interrupt line of
Rev. 0 | Page 30 of 32
AD7612
APPLICATION INFORMATION
The DVDD supply of the AD7612 can be either a separate supply
or come from the analog supply, AVDD, or from the digital inter-
face supply, OVDD. When the system digital supply is noisy, or
fast switching digital signals are present, and no separate supply is
available, it is recommended to connect the DVDD digital supply
to the analog supply AVDD through an RC filter, and to connect
the system supply to the interface digital supply OVDD and the
remaining digital circuitry. See Figure 27 for an example of this
configuration. When DVDD is powered from the system supply,
it is useful to insert a bead to further reduce high frequency spikes.
LAYOUT GUIDELINES
While the AD7612 has very good immunity to noise on the
power supplies, exercise care with the grounding layout. To facil-
itate the use of ground planes that can be easily separated, design
the printed circuit board that houses the AD7612 so that the
analog and digital sections are separated and confined to certain
areas of the board. Digital and analog ground planes should be
joined in only one place, preferably underneath the AD7612, or
as close as possible to the AD7612. If the AD7612 is in a system
where multiple devices require analog-to-digital ground connec-
tions, the connections should still be made at one point only, a
star ground point, established as close as possible to the AD7612.
The AD7612 has four different ground pins: REFGND, AGND,
DGND, and OGND.
To prevent coupling noise onto the die, avoid radiating noise,
and to reduce feedthrough:
•
REFGND senses the reference voltage and, because it carries
pulsed currents, should be a low impedance return to the
reference.
• Do not run digital lines under the device.
•
AGND is the ground to which most internal ADC analog
signals are referenced; it must be connected with the least
resistance to the analog ground plane.
• Do run the analog ground plane under the AD7612.
CNVST
• Do shield fast switching signals, like
or clocks, with
digital ground to avoid radiating noise to other sections of
the board, and never run them near analog signal paths.
•
•
DGND must be tied to the analog or digital ground plane
depending on the configuration.
• Avoid crossover of digital and analog signals.
OGND is connected to the digital system ground.
• Run traces on different but close layers of the board, at right
angles to each other, to reduce the effect of feedthrough through
the board.
The layout of the decoupling of the reference voltage is important.
To minimize parasitic inductances, place the decoupling capacitor
close to the ADC and connect it with short, thick traces.
The power supply lines to the AD7612 should use as large a trace
as possible to provide low impedance paths and reduce the effect
of glitches on the power supply lines. Good decoupling is also
important to lower the impedance of the supplies presented to
the AD7612, and to reduce the magnitude of the supply spikes.
Decoupled ceramic capacitors, typically 100 nF, should be placed
on each of the power supplies pins, AVDD, DVDD, and OVDD,
VCC, and VEE. The capacitors should be placed close to, and
ideally right up against, these pins and their corresponding ground
pins. Additionally, low ESR 10 μF capacitors should be located
in the vicinity of the ADC to further reduce low frequency ripple.
EVALUATING PERFORMANCE
A recommended layout for the AD7612 is outlined in the EVAL-
AD7612CB evaluation board documentation. The evaluation
board package includes a fully assembled and tested evaluation
board, documentation, and software for controlling the board
from a PC via the EVAL-CONTROL BRD3.
Rev. 0 | Page 31 of 32
AD7612
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.60
MAX
37
48
36
1
PIN 1
7.20
TOP VIEW
(PINS DOWN)
7.00 SQ
6.80
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
25
12
0.15
0.05
13
24
SEATING
PLANE
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 47. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
PADDLE CONNECTED TO VEE.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
ELECTRICAL PERFORMANCES.
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-48-1
CP-48-1
ST-48
ST-48
AD7612BCPZ1
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
Evaluation Board
AD7612BCPZ-RL1
AD7612BSTZ1
AD7612BSTZ-RL1
EVAL-AD7612CB2
EVAL-CONTROL BRD33
Controller Board
1 Z = Pb-free part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices. evaluation boards ending with the CB designators.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06265-0-10/06(0)
Rev. 0 | Page 32 of 32
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