AD8305ACP-REEL7 [ADI]
100 dB Range (10 nA to 1 mA) Logarithmic Converter; 百分贝范围（ 10 nA的为1 mA）的对数转换器
| 型号： | AD8305ACP-REEL7 |
| 厂家： | 
ADI |
| 描述： | 100 dB Range (10 nA to 1 mA) Logarithmic Converter |
| 文件： | 总20页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
100 dB Range (10 nA to 1 mA)
Logarithmic Converter
AD8305*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Optimized for Fiber Optic Photodiode Interfacing
Measures Current over 5 Decades
Law Conformance 0.1 dB from 10 nA to 1 mA
Single- or Dual-Supply Operation (3 V to 12 V Total)
Full Log-Ratio Capabilities
Nominal Slope of 10 mV/dB (200 mV/Decade)
Nominal Intercept of 1 nA (Set by External Resistor)
Optional Adjustment of Slope and Intercept
Complete and Temperature Stable
Rapid Response Time for a Given Current Level
Miniature 16-Lead Chip Scale Package
(LFCSP 3 mm
؋
3 mm) I
V
PD
P
0.20 log
10( )
1nA
VPOS
2.5V
VRDZ
VREF
VOUT
80k⍀
BIAS
GENERATOR
200k⍀
20k⍀
COMM
0.5V
SCAL
BFIN
IREF
V
14.2k⍀
BE2
V
I
BIAS
LOG
451⍀
Q2
Q1
–
+
TEMPERATURE
COMPENSATION
VLOG
I
PD
Low Power: ~5 mA Quiescent Current
V
BE1
6.69k⍀
COMM
INPT
APPLICATIONS
Optical Power Measurement
Wide Range Baseband Logarithmic Compression
Measurement of Current and Voltage Ratios
Optical Absorbance Measurement
0.5V
VSUM
COMM
VNEG
GENERAL DESCRIPTION
8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other values of
the logarithmic slope can be provided using a simple external
resistor network.
The AD8305 is an inexpensive microminiature logarithmic
converter optimized for determining optical power in fiber optic
systems. It uses an advanced implementation of a classic trans-
linear (junction based) technique to provide a large dynamic
range in a versatile and easily used form. A single-supply voltage of
between 3 V and 12 V is adequate; dual supplies may optionally
be used. The low quiescent current (typically 5 mA) permits use
in battery-operated applications.
The logarithmic intercept (also known as the reference current)
is nominally positioned at 1 nA by the use of the externally
generated current, IREF, of 10 mA, provided by a 200 kW resistor
connected between VREF, at 2.5 V, and the reference input
IREF, at 0.5 V. The intercept can be adjusted over a wide range
by varying this resistor. The AD8305 can also operate in a log-
ratio mode, with the numerator current applied to INPT and
the denominator current applied to IREF.
The input current, IPD, of 10 nA to 1 mA applied to the INPT
pin is the collector current of an optimally scaled NPN transis-
tor, which converts this current to a voltage (VBE) with a precise
logarithmic relationship. A second such converter is used to
handle the reference current (IREF) applied to pin IREF. These
input nodes are biased slightly above ground (0.5 V). This is gen-
erally acceptable for photodiode applications where the anode
does not need to be grounded. Similarly, this bias voltage is
easily accounted for in generating IREF. The output of the loga-
rithmic front end is available at Pin VLOG.
A buffer amplifier is provided for driving a substantial load, for
use in raising the basic slope of 10 mV/dB to higher values, as a
precision comparator (threshold detector), or in implementing
low-pass filters. Its rail-to-rail output stage can swing to within
100 mV of the positive and negative supply rails, and its peak
current sourcing capacity is 25 mA.
It is a fundamental aspect of translinear logarithmic converters
that the small signal bandwidth falls as the current level dimin-
ishes, and the low frequency noise-spectral density increases. At
the 10 nA level, the bandwidth of the AD8305 is about 50 kHz,
and increases in proportion to IPD up to a maximum value of
about 15 MHz. Using the buffer amplifier, the increase in noise
level at low currents can be addressed by using it to realize low-
pass filters of up to three poles.
The basic logarithmic slope at this output is nominally 200 mV/
decade (10 mV/dB). Thus, a 100 dB range corresponds to an
output change of 1 V. When this voltage (or the buffer output)
is applied to an ADC that permits an external reference voltage
to be employed, the AD8305’s voltage reference output of 2.5 V
at Pin VREF can be used to improve the scaling accuracy. Suit-
able ADCs include the AD7810 (serial 10-bit), AD7823 (serial
The AD8305 is available in a 16-lead LFCSP package and is
specified for operation from –40∞C to +85∞C.
*Protected by U.S. Patent No. 4,604,532 and 5,519,308; other patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(VP = 5 V, VN = 0 V, TA = 25ꢀC, RREF = 200 kꢁ, and VRDZ connected to VREF, unless
AD8305–SPECIFICATIONS otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
INPUT INTERFACE
Pin 4, INPT, Pin 3, IREF
Flows toward INPT Pin
Flows toward INPT Pin
Flows toward IREF Pin
Internally Preset; May be Altered by User
–40∞C < TA < +85∞C
Specified Current Range, IPD
Input Current Min/Max Limits
Reference Current, IREF, Range
Summing Node Voltage
Temperature Drift
10 n
1 m
10 m
1 m
A
A
A
V
10 n
0.46
0.5
0.015
0.54
mV/∞C
mV
Input Offset Voltage
VINPT – VSUM, VIREF – VSUM
–20
+20
LOGARITHMIC OUTPUT
Logarithmic Slope
Pin 9, VLOG
190
185
0.3
0.1
200
1
210
215
1.7
2.5
0.4
mV/dec
mV/dec
nA
nA
dB
mV÷Hz
MHz
V
V
kW
–40∞C < TA < +85∞C
Logarithmic Intercept1
–40∞C < TA < +85∞C
10 nA < IPD < 1 mA
IPD > 1 mA
Law Conformance Error
Wideband Noise2
0.1
0.7
0.7
1.7
0.01
5
Small Signal Bandwidth2
Maximum Output Voltage
Minimum Output Voltage
Output Resistance
IPD > 1 mA
Limited by VN = 0 V
Pin 2, VREF
4.375
5.625
REFERENCE OUTPUT
Voltage wrt Ground
2.435
2.4
2.5
2.565
2.6
V
V
–40∞C < TA < +85∞C
Maximum Output Current
Incremental Output Resistance
Sourcing (Grounded Load)
Load Current < 10 mA
20
2
mA
W
OUTPUT BUFFER
Input Offset Voltage
Input Bias Current
Incremental Input Resistance
Output Range
Incremental Output Resistance
Peak Source/Sink Current
Small Signal Bandwidth
Slew Rate
Pin 10, BFIN; Pin 11, SCAL; Pin 12, VOUT
–20
+20
mV
mA
MW
V
Flowing out of Pin 10 or 11
0.4
35
VP – 0.1
0.5
25
15
15
RL = 1 kW to ground
Load Current < 10 mA
W
mA
MHz
V/ms
GAIN = 1
0.2 V to 4.8 V Output Swing
POWER SUPPLY
Positive Supply Voltage
Quiescent Current
Pin 8, VPOS; Pin 6 and Pin 7, VNEG
(VP – VN) £ 12 V
3
5
5.4
0
12
6.5
V
mA
V
Negative Supply Voltage (Optional)
(VP – VN) £ 12 V
–5.5
NOTES
1Other values of logarithmic intercept can be achieved by adjusting RREF
.
2Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN = 1.
–2–
REV. A
AD8305
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage VP – VN . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Temperature
Range
Package
Description
Package
Option
Model
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 500 mW
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30∞C/W
JA
AD8305ACP
–40∞C to +85∞C
16-Lead LFCSP CP-16
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C
Operating Temperature Range . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C
AD8305ACP-REEL7 7" Tape and Reel
AD8305-EVAL Evaluation Board
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 With package die paddle soldered to thermal pad containing nine vias connected
to inner and bottom layers.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8305 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
PIN 1
12 VOUT
11 SCAL
10 BFIN
9 VLOG
VRDZ 1
VREF 2
IREF 3
INPT 4
INDICATOR
AD8305
TOP VIEW
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
VRDZ
Top of a Resistive Divider Network that Offsets VLOG to Position the Intercept. Normally connected
to VREF; may also be connected to ground when bipolar outputs are to be provided.
2
3
4
VREF
IREF
INPT
Reference Output Voltage of 2.5 V.
Accepts (Sinks) Reference Current, IREF.
Accepts (Sinks) Photodiode Current, IPD. Usually connected to photodiode anode such that photo
current flows into INPT.
5
VSUM
Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF
node potential.
6, 7
8
VNEG
VPOS
VLOG
BFIN
Optional Negative Supply, VN. (This pin is usually grounded; for details of usage, see the Applications section).
Positive Supply, (VP – VN ) £ 12 V.
Output of the Logarithmic Front End.
Buffer Amplifier Noninverting Input.
Buffer Amplifier Inverting Input.
Buffer Output.
9
10
11
SCAL
VOUT
COMM
12
13–16
Analog Ground.
REV. A
–3–
(VP = 5 V, VN = 0 V, RREF = 200 kꢁ, TA = 25ꢀC, unless
AD8305–Typical Performance Characteristics otherwise noted.)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0
T
V
= –40ꢀC, 0ꢀC, +25ꢀC, +70ꢀC, +85ꢀC
= 0V
A
T
V
= –40ꢀC, 0ꢀC, +25ꢀC, +70ꢀC, +85ꢀC
= 0V
A
N
1.5
N
1.0
+85ꢀC
+70ꢀC
–40ꢀC
+25ꢀC
+85ꢀC
0.5
0
–0.5
–1.0
–1.5
–2.0
+25ꢀC
0ꢀC
–40ꢀC
0ꢀC
+70ꢀC
1n
10n
100n
1ꢂ
I
10ꢂ
– A
100ꢂ
1m
10m
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
I
PD
PD
TPC 1. VLOG vs. IPD for Multiple Temperatures
TPC 4. Law Conformance Error vs. IPD (at IREF = 10 mA)
for Multiple Temperatures, Normalized to 25∞C
1.8
2.0
T
V
= –40ꢀC, 0ꢀC, +25ꢀC, +70ꢀC, +85ꢀC
= 0V
T
V
= –40ꢀC, 0ꢀC, +25ꢀC, +70ꢀC, +85ꢀC
= 0V
–40ꢀC
A
A
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
N
1.5
1.0
N
0ꢀC
+70ꢀC
+85ꢀC
+70ꢀC
0.5
+25ꢀC
+85ꢀC
0
–0.5
–1.0
–1.5
–2.0
+25ꢀC
0ꢀC
–40ꢀC
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
I
REF
I
REF
TPC 2. VLOG vs. IREF for Multiple Temperatures
TPC 5. Law Conformance Error vs. IREF (at IPD = 10 mA)
for Multiple Temperatures, Normalized to 25
∞
C
1.8
1.6
1.4
1.2
0.5
0.4
0.3
10ꢂA
100ꢂA 1mA
0.2
0.1
1.0
10nA
0
100nA
1ꢂA
10ꢂA
100ꢂA
0.8
0.6
0.4
0.2
0
–0.1
–0.2
–0.3
–0.4
–0.5
1ꢂA
10nA 100nA
1mA
1n
10n
100n
1ꢂ
I
10ꢂ
– A
100ꢂ
1m
10m
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
PD
I
PD
TPC 3. VLOG vs. IPD for Multiple Values of IREF
(Decade Steps from 10 nA to 1 mA)
TPC 6. Law Conformance Error vs. IPD for Multiple
Values of IREF (Decade Steps from 10 nA to 1 mA)
–4–
REV. A
AD8305
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.5
0.4
1ꢂA
10nA
100nA
0.3
10ꢂA
0.2
0.1
0
1mA
100ꢂA
10ꢂA
1ꢂA
100nA
10nA
–0.1
–0.2
–0.3
–0.4
–0.5
1mA
100n
100ꢂA
1n
10n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
I
I
REF
REF
TPC 7. VLOG vs. IREF for Multiple Values of IPD
(Decade Steps from 10 nA to 1 mA)
TPC 10. Law Conformance Error vs. IREF for Multiple
Values of IPD (Decade Steps from 10 nA to 1 mA)
0.5
1.4
+3V, 0V
0.4
+5V, 0V
+9V, 0V
+12V, 0V
1.2
100ꢂATO 1mA:T-RISE = <1ꢂs,
T- FA LL = < 1ꢂs
0.3
0.2
1.0
10ꢂATO 10ꢂA:T-RISE = <1ꢂs,
T- FA LL = < 1ꢂs
0.1
0.8
1ꢂATO 10ꢂA:T-RISE = 1ꢂs,
T- FA LL = 5ꢂs
0
0.6
–0.1
–0.2
–0.3
–0.4
–0.5
100nATO 1ꢂA: T-RISE = 5ꢂs,
T- FA LL = 20ꢂs
+3V, –0.5V
+5V, –5V
0.4
10nATO 100nA:T-RISE = 20ꢂs,
T- FA LL = 30ꢂs
0.2
0
–20
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
0
20
40
60
80
100 120 140 160 180
I
TIME – ꢂs
PD
TPC 8. Law Conformance Error vs. IPD for Various
Supply Conditions (see Annotations)
TPC 11. Pulse Response – IPD to VOUT (G = 1)
0.4
0.3
1.6
1.4
10nATO 100nA:T-RISE = 30ꢂs,
T- FA LL = 20ꢂs
1.2
0.2
100nATO 1ꢂA: T-RISE = 30ꢂs,
T- FA LL = 5ꢂs
1.0
0.1
1ꢂA TO 10ꢂA:T-RISE = 5ꢂs,
T- FA LL = < 1ꢂs
0.8
0
10ꢂATO 100ꢂA: T-RISE = 1ꢂs,
T- FA LL = < 1ꢂs
–0.1
–0.2
–0.3
–0.4
0.6
100ꢂATO 1mA: T-RISE=<1ꢂs,
T- FA LL = < 1ꢂs
0.4
0.2
0
–20
0
20
40
60
80
100 120 140 160 180
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
TIME – ꢂs
I
PD
TPC 12. Pulse Response – IREF to VOUT (G = 1)
TPC 9. VINPT – VSUM vs. IPD
REV. A
–5–
AD8305
10
3
0
10nA
100nA
10ꢂA
0
–10
–20
–30
–40
100ꢂA
A
= 1
V
–3
A
= 2
V
A
= 5
V
1mA
–6
–9
1ꢂA
A
= 2.5
V
–50
100
–12
10k
1k
10k
100k
1M
10M
100M
100k
1M
FREQUENCY – Hz
10M
100M
FREQUENCY – Hz
TPC 13. Small Signal AC Response (5% Sine
Modulation), from IPD to VOUT (G = 1) for IPD in
Decade Steps from 10 nA to 1 mA, IREF = 10 mA
TPC 16. Small Signal AC Response of the Buffer for
Various Closed-Loop Gains (RL = 1 kW CL < 2 pF)
10
2.0
1.5
10nA 100nA
10ꢂA
0
–10
–20
–30
100ꢂA
1.0
MEAN + 3ꢃ
0.5
0
1mA
–0.5
MEAN – 3ꢃ
1ꢂA
–1.0
–40
–50
–1.5
–2.0
100
1k
10k
100k
1M
10M
100M
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
FREQUENCY – Hz
TEMPERATURE – ꢀC
TPC 14. Small Signal AC Response (5% Sine
Modulation), from IREF to VOUT (G = 1) for IREF in
Decade Steps from 10 nA to 1 mA, IPD = 10 mA
TPC 17. Buffer Input Offset Drift vs. Temperature
(3 to Either Side of Mean)
100
6
5
4
3
2
1
0
10nA
10
100nA
1
1ꢂA
10ꢂA
0.1
100ꢂA
0.01
100
1k
10k
100k
1M
10M
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
FREQUENCY – Hz
I
PD
TPC 15. Spot Noise Spectral Density at VOUT
(G = 1) vs. Frequency for IPD in Decade Steps from
10 nA to 1 mA
TPC 18. Total Wideband Noise Voltage
at VOUT vs. IPD (G = 1)
–6–
REV. A
AD8305
20
15
2.0
1.5
T
= 25ꢀC
A
10
1.0
MEAN + 3ꢃ
MEAN – 3ꢃ
5
0.5
MEAN + 3ꢃ
MEAN – 3ꢃ
0
0
–5
–0.5
–1.0
–1.5
–2.0
–10
–15
–20
–25
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
I
TEMPERATURE – ꢀC
PD
TPC 19. Law Conformance Error Distribution
TPC 22. VREF Drift vs. Temperature (3 to Either
(3 to Either Side of Mean)
Side of Mean)
2.0
1.5
20
15
10
T
= 0ꢀC, 70ꢀC
A
MEAN + 3ꢃ @ 70ꢀC
1.0
0.5
MEAN + 3ꢃ
5
0
0
MEAN ꢄ 3ꢃ @ 0ꢀC
MEAN – 3ꢃ @ 70ꢀC
–0.5
–1.0
–1.5
–2.0
–5
MEAN – 3ꢃ
–10
–15
–20
1n
10n
100n
1ꢂ
10ꢂ
100ꢂ
1m
10m
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
I
– A
TEMPERATURE – ꢀC
PD
TPC 20. Law Conformance Error Distribution
TPC 23. VREF – VIREF Drift vs. Temperature
(3 to Either Side of Mean)
(3 to Either Side of Mean)
4
5
4
3
2
T
= –40ꢀC, +85ꢀC
A
3
2
MEAN + 3ꢃ @ –40ꢀC
1
1
MEAN 3ꢃ @ +85ꢀC
MEAN + 3ꢃ
0
0
–1
–1
–2
–3
–4
–2
–3
–4
–5
MEAN – 3ꢃ
MEAN – 3ꢃ @ –40ꢀC
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE – ꢀC
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
I
PD
TPC 21. Law Conformance Error Distribution
TPC 24. VINPT Drift vs. Temperature (3 to Either
(3 to Either Side of Mean)
Side of Mean)
REV. A
–7–
AD8305
10
4000
3500
8
6
3000
2500
2000
1500
4
MEAN + 3ꢃ
MEAN – 3ꢃ
2
0
–2
–4
–6
–8
–10
1000
500
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE – ꢀC
0.4
0.6
0.8
1.0
1.2
1.4
1.6
INTERCEPT – nA
TPC 28. Distribution of Logarithmic Intercept (Nominally
TPC 25. Slope Drift vs. Temperature (3 to Either
1 nA when RREF = 200 kW ± 0.1%) Sample >22,000
Side of Mean of 200 mV/decade)
350
7000
6000
5000
4000
3000
2000
250
MEAN + 3ꢃ
150
50
–50
–150
MEAN – 3ꢃ
1000
0
–250
–350
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 85 90
TEMPERATURE – ꢀC
2.44
2.46
2.48
2.50
V –V
REF
2.52
2.54
2.56
TPC 26. Intercept Drift vs. Temperature (3 to
Either Side of Mean of 1 nA)
TPC 29. Distribution of VREF (RL = 100 kW) Sample >22,000
6000
5000
4000
6000
5000
4000
3000
2000
1000
3000
2000
1000
0
190
0
195
200
205
210
–0.015 –0.010
–0.005
0.0
0.005
0.010
0.015
SLOPE – mV/dec
V
–V
SUM
VOLTAGE –V
INPT
TPC 30. Distribution of Offset Voltage (VINPT – VSUM
Sample >22,000
)
TPC 27. Distribution of Logarithmic Slope
(Nominally 200 mV/decade) Sample >22,000
–8–
REV. A
AD8305
GENERAL STRUCTURE
billion between –35∞C and +85∞C. Thus, to make use of the
BJT as an accurate logarithmic element, both of these tempera-
ture dependencies must be eliminated.
The AD8305 addresses a wide variety of interfacing conditions
to meet the needs of fiber optic supervisory systems, and will
also be useful in many nonoptical applications. These notes
explain the structure of this unique style of translinear log amp.
Figure 1 is a simplified schematic showing the key elements.
The difference between the base-emitter voltages of a matched pair
of BJTs, one operating at the photodiode current IPD and the second
operating at a reference current IREF, can be written as:
V
BE1 –VBE2 = kT/q In I /I – kT/q In IREF /IS
(
)
(
)
C
S
BIAS
GENERATOR
V
BE1
= In 10 kT/qlog
I
PD /IREF
IREF
(
)
(
)
TEMPERATURE
COMPENSATION
(SUBTRACT AND
DIVIDE BY T ꢆ K
10
(2)
PHOTODIODE
INPUT CURRENT
2.5V
80kꢁ
0.5V
VREF
I
REF
V
= 59.5mV log10
I
PD /IREF T = 300 K
(
)(
)
BE2
20kꢁ
I
COMM
0.5V
PD
The uncertain and temperature dependent saturation current IS,
which appears in Equation 1, has thus been eliminated. To
eliminate the temperature variation of kT/q, this difference voltage
is processed by what is essentially an analog divider. Effectively, it
puts a variable under Equation 2. The output of this process,
which also involves a conversion from voltage-mode to current-
mode, is an intermediate, temperature-corrected current:
VSUM
44ꢂA/dec
INPT
14.2kꢁ
6.69kꢁ
451ꢁ
VRDZ
VLOG
0.5V
Q1
V
Q2
V
BE1
BE2
ILOG = IY log10
I
PD /IREF
(3)
(
)
COMM
VNEG (NORMALLY GROUNDED)
where IY is an accurate, temperature-stable scaling current that
determines the slope of the function (the change in current per
decade). For the AD8305, IY is 44 mA, resulting in a temperature-
Figure 1. Simplified Schematic
The photodiode current IPD is received at Pin INPT. The
voltage at this node is essentially equal to those on the two
independent slope of 44 mA/decade, for all values of IPD and IREF
This current is subsequently converted back to a voltage-mode
output, VLOG, scaled 200 mV/decade.
.
adjacent guard pins, VSUM and IREF, due to the low offset
voltage of the JFET op amp. Transistor Q1 converts the input
current IPD to a corresponding logarithmic voltage, as shown in
Equation 1. A finite positive value of VSUM is needed to bias
the collector of Q1 for the usual case of a single-supply voltage.
This is internally set to 0.5 V, that is, one fifth of the reference
voltage of 2.5 V appearing on Pin VREF. The resistance at the
VSUM pin is nominally 16 kW; this voltage is not intended as
a general bias source.
It is apparent that this output should be zero for IPD = IREF, and
would need to swing negative for smaller values of input current.
To avoid this, IREF would need to be as small as the smallest
value of IPD. However, it is impractical to use such a small refer-
ence current as 1 nA. Accordingly, an offset voltage is added to
VLOG to shift it upward by 0.8 V when Pin VRDZ is directly
connected to VREF. This has the effect of moving the intercept
to the left by four decades, from 10 mA to 1 nA:
The AD8305 also supports the use of an optional negative supply
voltage, VN, at Pin VNEG. When VN is –0.5 V or more negative,
VSUM may be connected to ground; thus INPT and IREF
assume this potential. This allows operation as a voltage-input
logarithmic converter by the inclusion of a series resistor at either
or both inputs. Note that the resistor setting IREF will need to be
adjusted to maintain the intercept value. It should also be noted
that the collector-emitter voltages of Q1 and Q2 are now the full
VN, and effects due to self-heating will cause errors at large
input currents.
ILOG = IY log10
I
PD /IINTC
(4)
(
)
where IINTC is the operational value of the intercept current. To
disable this offset, Pin VRDZ should be grounded, then the
intercept IINTC is simply IREF. Since values of IPD < IINTC result in
a negative VLOG, a negative supply of sufficient value is required
to accommodate this situation (discussed later).
The voltage VLOG is generated by applying ILOG to an internal
resistance of 4.55 kW, formed by the parallel combination of a
6.69 kW resistor to ground and the 14.2 kW resistor to the VRDZ
pin. When the VLOG pin is unloaded and the intercept reposi-
tioning is disabled by grounding VRDZ, the output current ILOG
generates a voltage at the VLOG pin of:
The input dependent VBE1 of Q1 is compared with the reference
VBE2 of a second transistor, Q2, operating at IREF. This is gener-
ated externally, to a recommended value of 10 mA. However,
other values over a several-decade range can be used with a
slight degradation in law conformance (TPC 1).
VLOG = ILOG ¥ 4.55 k W
= 44 mA¥ 4.55 k W ¥ log10
I
PD/IREF
(
)
(5)
Theory
=VY log10
I
PD/IREF
(
)
The base-emitter voltage of a BJT (bipolar junction transistor)
can be expressed by Equation 1, which immediately shows its
basic logarithmic nature:
where VY = 200 mV/decade, or 10 mV/dB. Note that any resistive
loading on VLOG will lower this slope and also result in an
overall scaling uncertainty due to the variability of the on-chip
resistors. Consequently, this practice is not recommended.
VBE = kT/qIn I /I
(1)
(
)
C
S
where IC is its collector current, IS is a scaling current, typically
only 10–17 A, and kT/q is the thermal voltage, proportional to
absolute temperature (PTAT) and is 25.85 mV at 300 K. The
current, IS, is never precisely defined and exhibits an even stron-
ger temperature dependence, varying by a factor of roughly a
V
LOG may also swing below ground when dual supplies (VP and
VN) are used. When VN = –0.5 V or larger, the input pins INPT
and IREF may now be positioned at ground level by simply
grounding VSUM.
REV. A
–9–
AD8305
Managing Intercept and Slope
When using a single supply, VRDZ should be directly connected
to VREF to allow operation over the entire five-decade input
current range. As noted previously, this introduces an accurate
offset voltage of 0.8 V at the VLOG pin, equivalent to four decades,
resulting in a logarithmic transfer function that can be written as:
I
PD
+5V
VPOS
0.5 log
10( )
1nA
VRDZ
VREF
VOUT
BIAS
GENERATOR
12kꢁ
80kꢁ 2.5V
200kꢁ
20kꢁ
COMM
8kꢁ
0.5V
SCAL
BFIN
IREF
VLOG =VY log10 104 ¥ IPD/IREF
BE2
V
14.2kꢁ
(
(
)
1kꢁ
I
V
(6)
LOG
451ꢁ
BIAS
Q2
Q1
–
TEMPERATURE
COMPENSATION
1nF
=VY log10
IPD/IINTC
)
VLOG
+
C
10nF
I
INPT
FLT
PD
where IINTC = IREF/104
Thus, the effective intercept current IINTC is only one ten-
thousandth of IREF, corresponding to 1 nA when using the
recommended value of IREF = 10 mA.
V
BE1
6.69kꢁ
COMM
VSUM
1nF
1kꢁ
0.5V
1nF
VNEG
COMM
The slope can be reduced by attaching a resistor to the VLOG
pin. This is strongly discouraged, in view of the fact that the
on-chip resistors will not ratio correctly to the added resistance.
Also, it is rare that one would want to lower the basic slope of
10 mV/dB; if this is needed, it should be effected at the low
impedance output of the buffer, which is provided to avoid such
miscalibration and also allow higher slopes to be used.
Figure 2. Basic Connections for Fixed Intercept Use
The 2 V difference in voltage between the VREF and INPT pins
in conjunction with the external 200 kW resistor RREF provide a
reference current IREF of 10 mA into Pin IREF. Connecting pin
VRDZ to VREF raises the voltage at VLOG by 0.8 V, effectively
lowering the intercept current IINTC by a factor of 104 to position
it at 1 nA. A wide range of other values for IREF, from under
100 nA to over 1 mA, may be used. The effect of such changes
is shown in TPC 3.
The AD8305 buffer is essentially an uncommitted op amp with
rail-to-rail output swing, good load-driving capabilities and a
unity-gain bandwidth of >12 MHz. In addition to allowing the
introduction of gain, using standard feedback networks and
thereby increasing the slope voltage VY, the buffer can be used
to implement multipole low-pass filters, threshold detectors,
and a variety of other functions. Further details of these can be
found in the AD8304 data sheet.
Any temperature variation in RREF must be taken into account
when estimating the stability of the intercept. Also, the overall
noise will increase when using very low values of IREF. In fixed-
intercept applications, there is little benefit in using a large
reference current, since this only compresses the low current
end of the dynamic range when operated from a single supply,
here shown as 5 V. The capacitor between VSUM and ground
is recommended to minimize the noise on this node and to help
provide a clean reference current.
Response Time and Noise Considerations
The response time and output noise of the AD8305 are funda-
mentally a function of the signal current IPD. For small currents,
the bandwidth is proportional to IPD, as shown in TPC 13. The
output low frequency voltage-noise spectral-density is a function
Since the basic scaling at VLOG is 0.2 V/decade, and thus a swing
of 4 V at the buffer output would correspond to 20 decades, it will
often be useful to raise the slope to make better use of the rail-
to-rail voltage range. For illustrative purposes, the circuit in
Figure 2 provides an overall slope of 0.5 V/decade (25 mV/dB).
Thus, using IREF = 10 mA, VLOG runs from 0.2 V at IPD = 10 nA
to 1.4 V at IPD = 1 mA while the buffer output runs from 0.5 V to
3.5 V, corresponding to a dynamic range of 120 dB (electrical,
that is, 60 dB optical power).
of IPD (TPC 15) and also increases for small values of IREF
.
Details of the noise and bandwidth performance of translinear
log amps can be found in the AD8304 Data Sheet.
APPLICATIONS
The AD8305 is easy to use in optical supervisory systems and in
similar situations where a wide ranging current is to be converted
to its logarithmic equivalent, which is represented in decibel
terms. Basic connections for measuring a single-current input are
shown in Figure 2, which also includes various nonessential com-
ponents, as will be explained.
The optional capacitor from VLOG to ground forms a single-pole
low-pass filter in combination with the 4.55 kW resistance at this
pin. For example, using a CFLT of 10 nF, the –3 dB corner
frequency is 3.5 kHz. Such filtering is useful in minimizing the
output noise, particularly when IPD is small. Multipole filters are
more effective in reducing the total noise; examples are provided
in the AD8304 data sheet.
–10–
REV. A
AD8305
The dynamic response of this overall input system is influenced by
the external RC networks connected from the two inputs (INPT,
IREF) to ground. These are required to stabilize the input systems
over the full current range. The bandwidth changes with the
input current due to the widely varying pole frequency. The RC
network adds a zero to the input system to ensure stability over the
full range of input current levels. The network values shown in
Figure 2 will usually suffice, but some experimentation may be
necessary when the photodiode capacitance is high.
The Uncalibrated Error line in Figure 3 was generated assuming
that the slope of the measured output was 200 mV/decade when
in fact it was actually 194 mV/decade. Correcting for this dis-
crepancy decreased measurement error up to 3 dB.
USING A NEGATIVE SUPPLY
Most applications of the AD8305 require only a single supply of
3.0 V to 5.5 V. However, to provide further versatility, dual
supplies may be employed, as illustrated in Figure 4.
Although the two current inputs are similar, some care is needed
to operate the reference input at extremes of current (<100 nA)
and temperature (<0∞C). Modifying the RC network to 4.7 nF
and 2 kW will allow operation to –40∞C at 10 nA. By inspecting
the transient response to perturbations in IREF at representative
current levels, the capacitor value can be adjusted to provide fast
rise and fall times with acceptable settling. To fine tune the net-
work zero, the resistor value should be adjusted.
I
PD
5V
0.5 log
10
(1nA )
VPOS
VRDZ
VOUT
BIAS
VREF
12kꢁ
8kꢁ
GENERATOR
80kꢁ
2.5V
RREF
20kꢁ
COMM
200kꢁ
0.5V
SCAL
BFIN
IREF
V
BE2
14.2kꢁ
1kꢁ
I
CALIBRATION
V
LOG
BIAS
Q2
Q1
–
TEMPERATURE
COMPENSATION
1nF
+
VLOG
The AD8305 has a nominal slope and intercept of 200 mV/decade
and 1 nA, respectively. These values are untrimmed and the
slope alone may vary as much as 7.5% over temperature. For
this reason, it is recommended that a simple calibration be done
to achieve increased accuracy.
451ꢁ
I
C
INPT
PD
FLT
V
BE1
10nF
6.69kꢁ
COMM
VSUM
1kꢁ
1nF
0.5V
+
VNEG
REF
COMM
V
F
I
+ I
SIG
q
–
1.4
1.2
1.0
0.8
0.6
0.4
0.2
4
3
V
£ –0.5V
NEG
I
= I + I
PD
UNCALIBRATED ERROR
SIG
V
– V
R
N
F
S
C1
R
£
S
I
+ I
SIGMAX
q
V
N
2
1
Figure 4. Negative Supply Application
MEASURED OUTPUT
The use of a negative supply, VN, allows the summing node to
be placed at ground level whenever the input transistor (Q1 in
Figure 1) has a sufficiently negative bias on its emitter. When
VNEG = –0.5 V, the VCE of Q1 and Q2 will be the same as for
the default case when VSUM is grounded. This bias need not
be accurate, and a poorly defined source can be used. The
source does however need to be able to support the quiescent
current as well as the INPT and IREF signal current. For example,
it may be convenient to utilize a forward-biased junction voltage
of about 0.7 V or a Schottky barrier voltage of a little over 0.5 V.
The effect of supply on the dynamic range and accuracy can be
seen in TPC 8.
0
CALIBRATED ERROR
–1
IDEAL OUTPUT
–2
–3
0
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
I
PD
Figure 3. Using Two-Point Calibration to Increase
Measurement Accuracy
With the summing node at ground, the AD8305 may now be
used as a voltage-input log amp at either the numerator input,
INPT, or the denominator input, IREF, by inserting a suitably
scaled resistor from the voltage source to the relevant pin. The
overall accuracy for small input voltages is limited by the voltage
offset at the inputs of the JFET op amps.
Figure 3 shows the improvement in accuracy when using a two-
point calibration method. To perform this calibration, apply two
known currents, I1 and I2, in the linear operating range between
10 nA and 1 mA. Measure the resulting output, V1 and V2,
respectively, and calculate the slope m and intercept b.
m = V –V / log
I
– log
I
(7)
(
)
(
)
(
)
[
]
1
2
10
1
10 2
The use of a negative supply also allows the output to swing
below ground, thereby allowing the intercept to correspond to a
midrange value of IPD. However, the voltage VLOG remains
referenced to the ACOM pin, and while it does not swing nega-
tive for default operating conditions, it is free to do so. Thus,
adding a resistor from VLOG to the negative supply lowers
all values of VLOG, which raises the intercept. The disadvan-
tage of this method is that the slope is reduced by the shunting
of the external resistor, and the poorly defined ratio of on-
chip and off-chip resistances causes errors in both the slope
and the intercept.
b =V1 – m ¥ log10
I
(8)
(
)
1
The same calibration could be performed with two known opti-
cal powers, P1 and P2. This allows for calibration of the entire
measurement system while providing a simplified relationship
between the incident optical power and VLOG voltage.
m = V –V / P – P
2 ) (
(9)
(
)
1
1
2
b =V1 – m ¥ P
(10)
1
REV. A
–11–
AD8305
+5V
VPOS
VRDZ
VREF
VOUT
I
PD
80kꢁ
2.5 V
0.5 log
10
+ 2
BIAS
GENERATOR
(I )
REF
44.2kꢁ
P
REF
18nF
20kꢁ
COMM
28.0kꢁ
REFERENCE
DETECTOR
0.5V
SCAL
BFIN
33nF
IREF
V
14.2kꢁ
BE2
I
REF
1kꢁ
I
LOG
12.1kꢁ
451ꢁ
Q2
Q1
–
TEMPERATURE
COMPENSATION
+5V
1nF
+
VLOG
I
PD
V
BE1
6.69kꢁ
COMM
INPT
1kꢁ
SIGNAL
DETECTOR
0.5V
VSUM
1nF
P
SIG
VNEG
COMM
Figure 5. Optical Absorbance Measurement
LOG-RATIO APPLICATIONS
exactly to the external resistor, which may slightly alter the Q of
the filter, the effect on pulse response will be negligible for most
purposes. Note that the gain of the buffer (ϫ2.5) is an integral
part of this illustrative filter design; in general, the filter may be
redesigned for other closed-loop gains.
It is often desirable to determine the ratio of two currents, for
example, in absorbance measurements. These are commonly used
to assess the attenuation of a passive optical component, such as
an optical filter or variable optical attenuator. In these situations,
a reference detector is used to measure the incident power enter-
ing the component. The exiting power is then measured using a
second detector and the ratio is calculated to determine the
attenuation factor. Since the AD8305 is fundamentally a ratiometric
device, having nearly identical logging systems for both numerator
and denominator (IPD and IREF, respectively), it can greatly
simplify such measurements.
The transfer characteristics can be expressed in terms of optical
power. If we assume that the two detectors have equal responsivities,
the relationship is
VOUT = 0.5V log10 104 ¥ PSIG /PREF
(11)
(
)
Using the identity log10(AB) = log10A + log10B and defining the
attenuation as –10 ϫ log10(PSIG/ PREF), the overall transfer char-
acteristic can be written as
Figure 5 illustrates the AD8305’s log-ratio capabilities in optical
absorbance measurements. Here a reference detector diode is used
to provide the reference current, IREF, proportional to the optical
reference power level. A second detector measures the transmitted
signal power, proportional to IPD. The AD8305 calculates the
logarithm of the ratio of these two currents, as shown in
Equation 11, and which is reformulated in power terms in
Equation 12. Both of these equations include the internal factor
of 10,000 introduced by the output offset applied to VLOG via pin
VRDZ. If the true (nonoffset) log ratio shown in Equation 4 is
preferred, VRDZ should be grounded to remove the offset. As
already noted, the use of a negative supply at Pin VNEG will
allow both VLOG and the buffer output to swing below ground,
and also allow the input pins INPT and IREF to be set to
ground potential. Thus, the AD8305 may also be used to deter-
mine the log ratio of two voltages.
(12)
VOUT = 2 – 50 mV dB ¥ a
where
a = –10 ¥ log10(PSIG PREF
)
Figure 6 illustrates the linear-in-dB relationship between the
absorbance and the output of the circuit in Figure 5.
2.5
2.0
1.5
1.0
Figure 5 also illustrates how a second order Sallen-Key low-pass
filter can be realized using two external capacitors and one
resistor. Here, the corner frequency is set to 1 kHz and the filter
Q is chosen to provide an optimally flat (overshoot-free) pulse
response. To scale this frequency either up or down, simply
scale the capacitors by the appropriate factor. Note that one of
the resistors needed to realize this filter is the output resistance
of 4.55 kW present at Pin VLOG. While this will not ratio
0.5
0
0
5
10
15
20
25
30
35
40
45
50
ATTENUATION – dB
Figure 6. Example of an Absorbance Transfer Function
–12–
REV. A
AD8305
REVERSING THE INPUT POLARITY
These measures are needed to minimize the risk of leakage
current paths. With 0.5 V as the nominal bias on the INPT pin,
a leakage-path resistance of 1 GW to ground would subtract
0.5 nA from the input, which amounts to an error of –0.44 dB for
a source current of 10 nA. Additionally, the very high output
resistance at the input pins and the long cables commonly needed
during characterization allow 60 Hz and RF emissions to introduce
substantial measurement errors. Careful guarding techniques
are essential to reduce the pickup of these spurious signals.
Some applications may require interfacing to a circuit that
sources current rather than sinks current, such as connecting to
the cathode side of a photodiode. Figure 7 shows the use of a
current mirror circuit. This allows for simultaneous monitoring
of the optical power at the cathode, and a data recovery path
using a transimpedance amplifier at the anode. The modified
Wilson mirror provides a current gain very close to unity and a
high output resistance. Figure 8 shows measured transfer function
and law conformance performance of the AD8305 in conjunc-
tion with this current mirror interface.
VREF
VNEG
VPOS
VOUT
KEITHLEY 236
KEITHLEY 236
IREF
5V
AD8305
0.1ꢂF
V
= 0.2 ꢆ
CHARACTERIZATION BFIN
OUT
BOARD
log (I /1nA)
16
15
14
13
10 PD
VLOG
INPT
COMM COMM COMM COMM
VRDZ VOUT
OUTPUT
12
VSUM
MAT03
1
2.5V
0V
11
10
9
VREF
IREF
INPT
SCAL
BFIN
2
3
4
TRIAX CONNECTORS
(SIGNAL – INPT AND IREF
GUARD – VSUM
MAT03
AD8305
DC MATRIX/DC SUPPLIES/DMM
200kꢁ
SHIELD – GROUND)
1nF
0V
Figure 9. Primary Characterization Setup
VLOG
I
ϷI
IN PD
10nA TO 1mA
I
The primary characterization setup shown in Figure 9 is used to
measure VREF, the static (dc) performance, logarithmic conform-
ance, slope and intercept, the voltages appearing at pins VSUM,
INPT and IREF, and the buffer offset and VREF drift with temper-
ature. To ensure stable operation over the full current range of
IREF and temperature extremes, filter components of C1 = 4.7 nF
and R13 = 2 kW are used at pin to IREF ground. In some cases,
a fixed resistor between pins VREF and IREF was used in place
of a precision current source. For the dynamic tests, including
noise and bandwidth measurements, more specialized setups
are required.
1kꢁ
PD
VSUM VNEG VNEG VPOS
1nF
5
6
7
8
0.1ꢂF
5V
DATA PATH
TIA
Figure 7. Wilson Current Mirror for Cathode Interfacing
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.00
0.75
0.50
0.25
0
HP 3577A
NETWORK ANALYZER
OUTPUT
INPUT R
INPUT A
INPUT B
+5V
+3V
–0.25
–0.50
–0.75
–1.00
5V
AD8138
B
+IN
EVALUATION
+3V +5V
16
15
14
13
BNC-T
BOARD
A
COMM COMM COMM COMM
5V
AD8138
PROVIDES DC OFFSET
12
1n
10n
100n
1ꢂ
10ꢂ
– A
100ꢂ
1m
10m
VRDZ
VOUT
SCAL
BFIN
1
I
PD
11
10
9
VREF
IREF
INPT
2
3
4
Figure 8. Log Output and Error Using Current
Mirror with Various Supplies
AD8305
CHARACTERIZATION METHODS
VLOG
During the characterization of the AD8305, the device was
treated as a precision current-input logarithmic converter, since
it is not practical for several reasons to generate accurate photo-
currents by illuminating a photodiode. The test currents were
generated either by using well calibrated current sources, such
as the Keithley 236, or by using a high value resistor from a
voltage source to the input pin. Great care is needed when using
very small input currents. For example, the triax output connec-
tion from the current generator was used with the guard tied to
VSUM. The input trace on the PC board was guarded by con-
necting adjacent traces to VSUM.
VSUM VNEG VNEG VPOS
5
6
7
8
+V
S
0.1ꢂF
Figure 10. Configuration for Buffer Amplifier
Bandwidth Measurement
Figure 10 shows the configuration used to measure the buffer
amplifier bandwidth. The AD8138 evaluation board includes
REV. A
–13–
AD8305
provisions to offset VLOG at the buffer input, allowing measure-
ments over the full range of IPD using a single supply. The network
analyzer input impedances were set to 1 MW.
The configuration in Figure 12 is used to measure the noise
performance. Batteries provide both the supply voltage and the
input current in order to minimize the introduction of spurious
noise and ground loop effects. The entire evaluation system,
including the current setting resistors, is mounted in a closed
aluminum enclosure to provide additional shielding to external
noise sources.
HP 3577A
NETWORK ANALYZER
OUTPUT
INPUT R
INPUT A
INPUT B
LECROY 9210
CH A
9213
TDS5104
CH1
POWER
16
15
14
13
SPLITTER
COMM COMM COMM COMM
12
VRDZ
VOUT
SCAL
BFIN
1
11
10
9
VREF
IREF
INPT
2
3
4
16
15
14
13
AD8305
R2
1nF
COMM COMM COMM COMM
B
+IN AD8138
EVALUATION
BOARD
1kꢁ
R1
12
VOUT
VRDZ
VREF
IREF
INPT
1
VLOG
A
SCAL 11
VSUM VNEG VNEG VPOS
2
3
4
1kꢁ
AD8305
200kꢁ
1kꢁ
5
6
7
8
1nF
10
BFIN
+V
1nF
S
R1
0.1ꢂF
9
VLOG
VSUM VNEG VNEG VPOS
1kꢁ
Figure 11. Configuration for Logarithmic
Amplifier Bandwidth Measurement
5
6
7
8
1nF
+V
S
The setup shown in Figure 11 was used for frequency response
measurements of the logarithmic amplifier section. The AD8138
output is offset to 1.5 V dc and modulated to a depth of 5% at
frequency. R1 is chosen (over a wide range of values up to
1.0 GW) to provide IPD. The buffer was used to deload VLOG
from the measurement system.
0.1ꢂF
Figure 13. Configuration for Logarithmic
Amplifier Pulse Response Measurement
Figure 13 shows the setup used to make the pulse response
measurements. As with the bandwidth measurement, the VLOG
is connected directly to BFIN and the buffer amplifier is config-
ured for unity gain. The buffer’s output is connected through a
short cable to the TDS5104 scope with input impedance set to
1 MW. The LeCroy’s output is offset to create the initial pedestal
current for a given value of R1, the pulse then creates one-decade
current step.
HP 89410A
SOURCE
TRIGGER CHANNEL 1 CHANNEL 2
EVALUATION BOARD
An evaluation board is available for the AD8305, the schematic
for which is shown in Figure 16. It can be configured for a wide
variety of experiments. The buffer gain is factory-set to unity,
providing a slope of 200 mV/decade, and the intercept is set to 1 nA.
Table I describes the various configuration options.
16
15
14
13
COMM COMM COMM COMM
12
VOUT
VRDZ
VREF
IREF
INPT
1
SCAL 11
2
3
4
AD8305
200kꢁ
1kꢁ
1nF
10
BFIN
ALKALINE
“D” CELL
R1
9
VLOG
+
–
VSUM VNEG VNEG VPOS
1kꢁ
5
6
7
8
ALKALINE
“D” CELL
1nF
+
–
0.1ꢂF
+
–
+
–
Figure 12. Configuration for Noise Spectral
Density Measurement
–14–
REV. A
AD8305
Table I. Evaluation Board Configuration Options
Component
Function
Default Condition
P1
Supply Interface. Provides access to supply pins, VNEG, COMM, and VPOS. P1 = Installed
P2, R8, R9, R10,
R11, R17, R18
Monitor Interface. By adding 0 W resistors to R8, R9, R10, R11, R17, and R18, P2 = Not Installed
the VRDZ, VREF, VSUM, VOUT, and VLOG pin voltages can be monitored R8 = R9 = R10 = Open (Size 0603)
using a high impedance probe.
R17 = R18 = Open (Size 0603)
R2, R3, R4, R6, R14, Buffer Amplifier/Output Interface. The logarithmic slope of the AD8305
R2 = R6 = 0 W (Size 0603)
R3 = R4 = Open (Size 0603)
R11 = R14 = 0 W (Size 0603)
C2 = C7 = Open (Size 0603)
C9 = C10 = Open (Size 0603)
VLOG = VOUT = Installed
C2, C7, C9, C10
R1, R7, R19, R20
can be altered using the buffer’s gain-setting resistors, R2 and R3. R4, R14,
and C2 allow variation in the buffer loading. R6, C7, C9, and C10 are
provided for a variety of filtering applications.
Intercept Adjustment. The voltage dropped across resistor R1 determines the R1 = 200 kW (Size 0603)
intercept reference current, nominally set to 10 mA using a 200 kW 1% resistor. R7 = R19 = 0 W (Size 0603)
R7 and R19 can be used to adjust the output-offset voltage at the VLOG output. R20 = Open (Size 0603)
R12, R15, C3,
C4, C5, C6
Supply Decoupling.
C3 = C4 = 0.01 F
(Size 0603)
C5 = C6 = 0.1 F (Size 0603)
R12 = R15 = 0 W (Size 0603)
C11
VSUM Decoupling Capacitor.
Input Compensation. Provides essential HF compensation at the input pins,
INPT and IREF.
C11 = 1 nF (Size 0603)
R13 = R16 = 1 kW (Size 0603)
C1 = C8 = 1 nF (Size 0603)
R13, R16, C1, C8
IREF, INPT, PD,
LK1, R5
Input Interface. The test board is configured to accept a current through the IREF = INPT = Installed
SMA connector labeled INPT. An SC-style packaged photodiode can be
used in place of the INPT SMA for optical interfacing. By removing R1 and
PD = Not Installed
LK1 = Installed
adding a 0 W short for R5, a second current can be applied to the IREF input R5 = Open (Size 0603)
(also SMA) for evaluating the AD8305 in log-ratio applications.
J1
SC-Style Photodiode. Allows for direct mounting of SC style photodiodes.
J1 = Not Installed
REV. A
–15–
AD8305
Figure 14. Component Side Layout
Figure 15. Component Side Silkscreen
–16–
REV. A
AD8305
R10
16
15
14
13
VOUT
OPEN
COMM COMM COMM COMM
R20
OPEN
R14
R17
OPEN
VOUT 12
VOUT
1
2
3
4
VRDZ
VREF
VRDZ
VREF
IREF
INPT
0ꢁ
OPEN
C2
R4
R7
R2
OPEN
0ꢁ
0ꢁ
R3
R18
OPEN
R19
0ꢁ
C9
SCAL
BFIN
11
10
OPEN
OPEN
R1
AD8305
200kꢁ
1%
I
R8
REF
R6
0ꢁ
R5
OPEN
VLOG
IREF
C10
OPEN
R13 1kꢁ
OPEN
I
PD
R11
VLOG
9
VLOG
1
2
3
0ꢁ
C1 1nF
C7
VSUM VNEG
6
VNEG
7
VPOS
OPEN
SC-STYLE
PD
5
8
VRDZ
1
INPT
AGND
VOUT
VREF
2
3
C4
C3
0.01ꢂF
0.01ꢂF
LK1
R16 1kꢁ
R15
R12
R9
OPEN
C11 1nF
0ꢁ
0ꢁ
1nF
C8
C5
4
5
C6
VSUM
0.1ꢂF
0.1ꢂF
AGND
2
VSUM
VLOG
VNEG
VPOS
1
3
P1
6
P2
Figure 16. Evaluation Board Schematic
REV. A
–17–
AD8305
OUTLINE DIMENSIONS
16-Lead Leadframe Chip-Scale Package [LFCSP]
3 mm ꢆ 3 mm Body
(CP-16)
Dimensions shown in millimeters
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1 INDICATOR
1
2
0.45
PIN 1
INDICATOR
1.45
1.30 SQ
1.15
2.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
0.50
BSC
0.25 MIN
1.50 REF
0.80 MAX
12ꢀ MAX
0.65 NOM
1.00
0.90
0.80
0.05 MAX
0.01 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANTTO JEDEC STANDARDS MO-220-VEED-2
–18–
REV. A
AD8305
Revision History
Location
Page
3/03—Data Sheet changed from REV. 0 to REV. A.
Changes to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to TPC 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REV. A
–19–
–20–
相关型号：
AD8306ARU
IC LOG OR ANTILOG AMPLIFIER, 350 MHz BAND WIDTH, PDSO16, TSSOP-16, Analog Computational Function
ADI
AD8306ARZ-REEL
<span class="noTransform">5 MHz TO 400 MHz, 100 dB</span> High Precision Limiting - Logarithmic Amplifier Package: 16 ld SOIC; No of Pins: 16; Temperature Range: INDUSTRIAL; Container: 2500/Reel
ADI
©2020 ICPDF网 联系我们和版权申明