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AD8402ARZ10-REEL [ADI]

1-/2-/4-Channel Digital Potentiometers; 单/双/四通道数字电位器
AD8402ARZ10-REEL
型号： AD8402ARZ10-REEL
厂家： ADI    ADI
描述：

1-/2-/4-Channel Digital Potentiometers
单/双/四通道数字电位器

转换器 电位器 数字电位计 电阻器 光电二极管
文件： 总32页 (文件大小：610K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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1-/2-/4-Channel  
Digital Potentiometers  
AD8400/AD8402/AD8403  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
256-position variable resistance device  
Replaces 1, 2, or 4 potentiometers  
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ  
RDAC1  
A1  
W1  
B1  
AGND1  
8
8
8
8
AD8403  
8-BIT  
V
LATCH  
DD  
DAC  
CK RS  
SELECT  
DGND  
SHDN  
Power shutdown—less than 5 μA  
3-wire,SPI-compatible serial data input  
10 MHz update data loading rate  
2.7 V to 5.5 V single-supply operation  
Qualified for automotive applications  
1
2
RDAC2  
A2  
W2  
B2  
8-BIT  
LATCH  
3
4
A1, A0  
2
CK RS  
SHDN  
AGND2  
10-BIT  
SERIAL  
LATCH  
RDAC3  
A3  
8
8-BIT  
LATCH  
W3  
B3  
AGND3  
SDI  
APPLICATIONS  
D
CK RS  
SHDN  
CK Q RS  
Mechanical potentiometer replacement  
Programmable filters, delays, time constants  
Volume control, panning  
Line impedance matching  
Power supply adjustment  
CLK  
CS  
RDAC4  
A4  
W4  
B4  
AGND4  
8-BIT  
LATCH  
CK RS  
SHDN  
SHDN  
SDO  
RS  
Figure 1.  
GENERAL DESCRIPTION  
The AD8400/AD8402/AD8403 provide a single-, dual-, or  
quad-channel, 256-position, digitally controlled variable resistor  
(VR) device.1 These devices perform the same electronic adjust-  
ment function as a mechanical potentiometer or variable  
resistor. The AD8400 contains a single variable resistor in the  
compact SOIC-8 package. The AD8402 contains two independent  
variable resistors in space-saving SOIC-14 surface-mount  
packages. The AD8403 contains four independent variable  
resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each  
part contains a fixed resistor with a wiper contact that taps the  
fixed resistor value at a point determined by the digital code  
loaded into the controlling serial input register. The resistance  
between the wiper and either endpoint of the fixed resistor  
varies linearly with respect to the digital code transferred into  
the VR latch. Each variable resistor offers a completely  
programmable value of resistance between the A terminal and  
the wiper or the B terminal and the wiper. The fixed A-to-B  
terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a 1%  
channel-to-channel matching tolerance with a nominal  
temperature coefficient of 500 ppm/°C. A unique switching  
circuit minimizes the high glitch inherent in traditional  
switched resistor designs, avoiding any make-before-break  
or break-before-make operation.  
100  
R
R
WB  
WA  
75  
50  
25  
0
0
64  
128  
CODE (Decimal)  
192  
255  
Figure 2. RWA and RWB vs. Code  
(continued on Page 3)  
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.  
Rev. E  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2010 Analog Devices, Inc. All rights reserved.  
 
 
 
 
AD8400/AD8402/AD8403  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
ESD Caution................................................................................ 11  
Pin Configurations and Function Descriptions......................... 12  
Typical Performance Characteristics ........................................... 14  
Test Circuits..................................................................................... 19  
Theory of Operation ...................................................................... 20  
Programming the Variable Resistor......................................... 20  
Programming the Potentiometer Divider............................... 21  
Digital Interfacing ...................................................................... 21  
Applications..................................................................................... 24  
Active Filter................................................................................. 24  
Outline Dimensions....................................................................... 26  
Ordering Guide .......................................................................... 30  
Automotive Products................................................................. 31  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 4  
Electrical Characteristics—10 kΩ Version................................ 4  
Electrical Characteristics—50 kΩ and 100 kΩ Versions......... 6  
Electrical Characteristics—1 kΩ Version.................................. 8  
Electrical Characteristics—All Versions ................................. 10  
Timing Diagrams........................................................................ 10  
Absolute Maximum Ratings.......................................................... 11  
Serial Data-Word Format.......................................................... 11  
REVISION HISTORY  
7/10—Rev. D to Rev. E  
11/01—Rev. B to Rev. C  
Changes to Features Section ............................................................1  
Changes to IAB Continuous Current Parameter (Table 5) .........11  
Updated Outline Dimensions........................................................26  
Changes to Ordering Guide...........................................................30  
Added Automotive Products Section...........................................31  
Addition of new Figure.....................................................................1  
Edits to Specifications.......................................................................2  
Edits to Absolute Maximum Ratings..............................................6  
Edits to TPCs 1, 8, 12, 16, 20, 24, 35 ...............................................9  
Edits to  
the Programming the Variable Resistor Section..........................13  
10/05—Rev. C to Rev. D  
Updated Format.................................................................. Universal  
Changes to Features...........................................................................1  
Changes to Table 1.............................................................................4  
Changes to Table 2.............................................................................6  
Changes to Table 3.............................................................................8  
Changes to Table 5...........................................................................11  
Added Figure 36...............................................................................18  
Replaced Figure 37 ..........................................................................19  
Changes to Theory of Operation Section.....................................20  
Changes to Applications Section...................................................24  
Updated Outline Dimensions........................................................26  
Changes to Ordering Guide ...........................................................28  
Rev. E | Page 2 of 32  
 
AD8400/AD8402/AD8403  
GENERAL DESCRIPTION  
(continued from Page 1)  
Each VR has its own VR latch that holds its programmed  
resistance value. These VR latches are updated from an SPI-  
compatible, serial-to-parallel shift register that is loaded from  
a standard 3-wire, serial-input digital interface. Ten data bits  
make up the data-word clocked into the serial input register.  
The AD8400 is available in the SOIC-8 surface mount. The  
AD8402 is available in both surface-mount (SOIC-14) and  
14-lead PDIP packages, while the AD8403 is available in a  
narrow-body, 24-lead PDIP and a 24-lead, surface-mount  
package. The AD8402/AD8403 are also offered in the 1.1 mm  
thin TSSOP-14/TSSOP-24 packages for PCMCIA applications.  
All parts are guaranteed to operate over the extended industrial  
temperature range of −40°C to +125°C.  
The data-word is decoded where the first two bits determine  
the address of the VR latch to be loaded, and the last eight bits  
are the data. A serial data output pin at the opposite end of the  
serial register allows simple daisy chaining in multiple VR  
applications without additional external decoding logic.  
RS  
The reset ( ) pin forces the wiper to midscale by loading 80H  
SHDN  
into the VR latch. The  
pin forces the resistor to an end-  
to-end open-circuit condition on the A terminal and shorts the  
wiper to the B terminal, achieving a microwatt power shutdown  
SHDN  
state. When  
is returned to logic high, the previous latch  
settings put the wiper in the same resistance setting prior to  
shutdown. The digital interface is still active in shutdown so  
that code changes can be made that will produce new wiper  
positions when the device is taken out of shutdown.  
Rev. E | Page 3 of 32  
AD8400/AD8402/AD8403  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS—10 KΩ VERSION  
VDD = 3 V 10% or 5 V 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.  
Table 1.  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)  
Resistor Differential NL2  
Resistor Nonlinearity2  
Nominal Resistance3  
Resistance Tempco  
Wiper Resistance  
R-DNL  
R-INL  
RAB  
ΔRABꢀΔT  
RW  
RWB, VA = no connect  
RWB, VA = no connect  
TA = 25°C, model: AD840XYY10  
VAB = VDD, wiper = no connect  
VDD = 5V, IW = VDDꢀRAB  
−1  
−2  
8
1ꢀ4  
1ꢀ2  
10  
500  
50  
+1  
+2  
12  
LSB  
LSB  
kΩ  
ppmꢀ°C  
Ω
100  
1
RW  
ΔRꢀRAB  
VDD = 3V, IW = VDDꢀRAB  
CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C  
200  
0.2  
Ω
%
Nominal Resistance Match  
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)  
Resolution  
N
8
Bits  
Integral Nonlinearity4  
Differential Nonlinearity4  
INL  
−2  
−1  
−1  
−1.5  
1ꢀ2  
1ꢀ4  
1ꢀ4  
1ꢀ2  
15  
+2  
+1  
+1  
+1.5  
LSB  
LSB  
LSB  
LSB  
ppmꢀ°C  
LSB  
LSB  
DNL  
DNL  
DNL  
ΔVWꢀΔT  
VWFSE  
VWZSE  
VDD = 5 V  
VDD = 3 V, TA = 25°C  
VDD = 3 V, TA = −40°C to +85°C  
Code = 80H  
Code = FFH  
Code = 00H  
Voltage Divider Tempco  
Full-Scale Error  
Zero-Scale Error  
−4  
0
−2.8  
1.3  
0
2
RESISTOR TERMINALS  
Voltage Range5  
VA, B, W  
0
VDD  
V
Capacitance6 Ax, Capacitance Bx CA, B  
f = 1 MHz, measured to GND, code = 80H  
f = 1 MHz, measured to GND, code = 80H  
SHDN  
75  
pF  
pF  
μA  
Ω
Capacitance6 Wx  
Shutdown Current7  
CW  
IA_SD  
RW_SD  
120  
0.01  
100  
5
VA = VDD, VB = 0 V,  
VA = VDD, VB = 0 V,  
= 0  
Shutdown Wiper Resistance  
SHDN  
200  
= 0, VDD = 5 V  
DIGITAL INPUTS AND OUTPUTS  
Input Logic High  
Input Logic Low  
Input Logic High  
Input Logic Low  
Output Logic High  
Output Logic Low  
Input Current  
Input Capacitance6  
VIH  
VIL  
VIH  
VIL  
VOH  
VOL  
IIL  
VDD = 5 V  
VDD = 5 V  
VDD = 3 V  
VDD = 3 V  
RL = 2.2 kΩ to VDD  
IOL = 1.6 mA, VDD = 5 V  
VIN = 0 V or 5 V, VDD = 5 V  
2.4  
V
V
V
V
V
V
μA  
pF  
0.8  
0.6  
2.1  
VDD − 0.1  
0.4  
1
CIL  
5
POWER SUPPLIES  
Power Supply Range  
Supply Current (CMOS)  
Supply Current (TTL)8  
Power Dissipation (CMOS)9  
Power Supply Sensitivity  
VDD range  
IDD  
IDD  
PDISS  
PSS  
PSS  
2.7  
5.5  
5
4
27.5  
0.001  
0.03  
V
μA  
mA  
μW  
%ꢀ%  
%ꢀ%  
VIH = VDD or VIL = 0 V  
0.01  
0.9  
VIH = 2.4 V or 0.8 V, VDD = 5.5 V  
VIH = VDD or VIL = 0 V, VDD = 5.5 V  
VDD = 5 V 10%  
0.0002  
0.006  
VDD = 3 V 10%  
Rev. E | Page 4 of 32  
 
 
AD8400/AD8402/AD8403  
Parameter  
DYNAMIC CHARACTERISTICS6, 10  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
Bandwidth −3 dB  
Total Harmonic Distortion  
VW Settling Time  
BW_10 K  
THDW  
tS  
R = 10 kΩ  
600  
0.003  
2
kHz  
%
μs  
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz  
VA = VDD, VB = 0 V, 1% error band  
Resistor Noise Voltage  
Crosstalk11  
eNWB  
CT  
RS  
WB = 5 kΩ, f = 1 kHz, = 0  
VA = VDD, VB = 0 V  
9
nVꢀ√Hz  
dB  
R
−65  
1 Typical represents average readings at 25°C and VDD = 5 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.  
I
W = 50 μA for VDD = 3 V and IW = 400 μA for VDD = 5 V for the 10 kΩ versions.  
3 VAB = VDD, wiper (VW) = no connect.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DꢀA converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.  
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining  
resistor terminals are left open circuit.  
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.  
8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.  
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
10 All dynamic characteristics use VDD = 5 V.  
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.  
Rev. E | Page 5 of 32  
AD8400/AD8402/AD8403  
ELECTRICAL CHARACTERISTICS—50 KΩ AND 100 KΩ VERSIONS  
VDD = 3 V 10% or 5 V 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.  
Table 2.  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)  
Resistor Differential NL2  
Resistor Nonlinearity2  
Nominal Resistance3  
R-DNL  
R-INL  
RAB  
RAB  
ΔRABꢀΔT  
RW  
RWB, VA = No Connect  
RWB, VA = No Connect  
TA = 25°C, Model: AD840XYY50  
TA = 25°C, Model: AD840XYY100  
VAB = VDD, Wiper = No Connect  
VDD = 5V, IW = VDDꢀRAB  
−1  
−2  
35  
70  
1ꢀ4  
1ꢀ2  
50  
100  
500  
50  
+1  
+2  
65  
LSB  
LSB  
kΩ  
kΩ  
ppmꢀ°C  
Ω
130  
Resistance Tempco  
Wiper Resistance  
100  
1
RW  
ΔRꢀRAB  
VDD = 3V, IW = VDDꢀRAB  
CH 1 to CH 2, CH 3, or CH 4, VAB = VDD, TA = 25°C  
200  
0.2  
Ω
%
Nominal Resistance Match  
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)  
Resolution  
N
8
Bits  
Integral Nonlinearity4  
Differential Nonlinearity4  
INL  
−4  
−1  
−1  
−1.5  
1
+4  
+1  
+1  
+1.5  
LSB  
LSB  
LSB  
LSB  
ppmꢀ°C  
LSB  
LSB  
DNL  
DNL  
DNL  
ΔVWꢀΔT  
VWFSE  
VWZSE  
VDD = 5 V  
1ꢀ4  
1ꢀ4  
1ꢀ2  
15  
−0.25  
+0.1  
VDD = 3 V, TA = 25°C  
VDD = 3 V, TA = −40°C to +85°C  
Code = 80H  
Code = FFH  
Code = 00H  
Voltage Divider Tempco  
Full-Scale Error  
Zero-Scale Error  
−1  
0
0
+1  
RESISTOR TERMINALS  
Voltage Range5  
Capacitance6 Ax, Bx  
Capacitance6 Wx  
Shutdown Current7  
VA, VB, VW  
CA, CB  
CW  
0
VDD  
V
f = 1 MHz, measured to GND, code = 80H  
f = 1 MHz, measured to GND, code = 80H  
SHDN  
15  
80  
0.01  
100  
pF  
pF  
μA  
Ω
IA_SD  
5
VA = VDD, VB = 0 V,  
VA = VDD, VB = 0 V,  
= 0  
Shutdown Wiper Resistance  
RW_SD  
SHDN  
200  
= 0, VDD = 5 V  
DIGITAL INPUTS AND OUTPUTS  
Input Logic High  
Input Logic Low  
Input Logic High  
Input Logic Low  
Output Logic High  
Output Logic Low  
Input Current  
Input Capacitance6  
VIH  
VIL  
VIH  
VIL  
VOH  
VOL  
IIL  
VDD = 5 V  
VDD = 5 V  
VDD = 3 V  
VDD = 3 V  
RL = 2.2 kΩ to VDD  
IOL = 1.6 mA, VDD = 5 V  
VIN = 0 V or 5 V, VDD = 5 V  
2.4  
V
V
V
V
V
V
μA  
pF  
0.8  
0.6  
2.1  
VDD − 0.1  
0.4  
1
CIL  
5
POWER SUPPLIES  
Power Supply Range  
Supply Current (CMOS)  
Supply Current (TTL)8  
Power Dissipation (CMOS)9  
Power Supply Sensitivity  
VDD range  
IDD  
IDD  
PDISS  
PSS  
PSS  
2.7  
5.5  
5
4
V
VIH = VDD or VIL = 0 V  
0.01  
0.9  
μA  
mA  
μW  
VIH = 2.4 V or 0.8 V, VDD = 5.5 V  
VIH = VDD or VIL = 0 V, VDD = 5.5 V  
VDD = 5 V 10%  
27.5  
0.0002 0.001 %ꢀ%  
0.006 0.03 %ꢀ%  
VDD = 3 V 10%  
Rev. E | Page 6 of 32  
 
AD8400/AD8402/AD8403  
Parameter  
DYNAMIC CHARACTERISTICS6, 10  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
Bandwidth −3 dB  
BW_50 K  
BW_100 K  
THDW  
R = 50 kΩ  
R = 100 kΩ  
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz  
VA = VDD, VB = 0 V, 1% error band  
VA = VDD, VB = 0 V, 1% error band  
125  
71  
0.003  
9
18  
20  
kHz  
kHz  
%
μs  
μs  
nVꢀ√Hz  
nVꢀ√Hz  
dB  
Total Harmonic Distortion  
VW Settling Time  
tS_50 K  
tS_100 K  
eNWB_50 K  
eNWB_100 K  
CT  
Resistor Noise Voltage  
Crosstalk11  
RS  
RWB = 25 kΩ, f = 1 kHz, = 0  
RS  
29  
RWB = 50 kΩ, f = 1 kHz, = 0  
VA = VDD, VB = 0 V  
−65  
1 Typicals represent average readings at 25°C and VDD = 5 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.  
IW = VDDꢀR for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions.  
3 VAB = VDD, wiper (VW) = no connect.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DꢀA converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.  
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining  
resistor terminals are left open circuit.  
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.  
8 Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.  
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
10 All dynamic characteristics use VDD = 5 V.  
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.  
Rev. E | Page 7 of 32  
AD8400/AD8402/AD8403  
ELECTRICAL CHARACTERISTICS—1 KΩ VERSION  
VDD = 3 V 10% or 5 V 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.  
Table 3.  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)  
Resistor Differential NL2  
Resistor Nonlinearity2  
Nominal Resistance3  
Resistance Tempco  
Wiper Resistance  
R-DNL  
R-INL  
RAB  
ΔRABꢀΔT  
RW  
RWB, VA = no connect  
RWB, VA = no connect  
TA = 25°C, model: AD840XYY1  
VAB = VDD, wiper = no connect  
VDD = 5V, IW = VDDꢀRAB  
−5  
−4  
0.8  
−1  
+3  
+4  
1.6  
LSB  
LSB  
kΩ  
ppmꢀ°C  
Ω
1.5  
1.2  
700  
53  
200  
0.75  
100  
2
RW  
ΔRꢀRAB  
VDD = 3V, IW = VDDꢀRAB  
CH 1 to CH 2, VAB = VDD, TA = 25°C  
Ω
%
Nominal Resistance Match  
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)  
Resolution  
N
8
Bits  
Integral Nonlinearity4  
Differential Nonlinearity4  
INL  
DNL  
DNL  
−6  
−4  
−5  
2
−1.5  
−2  
25  
−12  
6
+6  
+2  
+5  
LSB  
LSB  
LSB  
ppmꢀ°C  
LSB  
VDD = 5 V  
VDD = 3 V, TA = 25°C  
Code = 80H  
Code = FFH  
Voltage Divider Temperature Coefficient ΔVWꢀΔT  
Full-Scale Error  
Zero-Scale Error  
VWFSE  
VWZSE  
−20  
0
0
10  
Code = 00H  
LSB  
RESISTOR TERMINALS  
Voltage Range5  
Capacitance6 Ax, Bx  
Capacitance6 Wx  
Shutdown Supply Current7  
VA, VB, VW  
CA, CB  
CW  
0
VDD  
V
f = 1 MHz, measured to GND, code = 80H  
f = 1 MHz, measured to GND, code = 80H  
SHDN  
75  
pF  
pF  
μA  
Ω
120  
0.01  
50  
IA_SD  
5
VA = VDD, VB = 0 V,  
VA = VDD, VB = 0 V,  
= 0  
Shutdown Wiper Resistance  
RW_SD  
SHDN  
100  
= 0, VDD = 5 V  
DIGITAL INPUTS AND OUTPUTS  
Input Logic High  
Input Logic Low  
Input Logic High  
Input Logic Low  
Output Logic High  
Output Logic Low  
Input Current  
Input Capacitance6  
VIH  
VIL  
VIH  
VIL  
VOH  
VOL  
IIL  
VDD = 5 V  
VDD = 5 V  
VDD = 3 V  
VDD = 3 V  
RL = 2.2 kΩ to VDD  
IOL = 1.6 mA, VDD = 5 V  
VIN = 0 V or 5 V, VDD = 5 V  
2.4  
V
V
V
V
V
V
μA  
pF  
0.8  
0.6  
2.1  
VDD − 0.1  
0.4  
1
CIL  
5
POWER SUPPLIES  
Power Supply Range  
Supply Current (CMOS)  
Supply Current (TTL)8  
Power Dissipation (CMOS)9  
Power Supply Sensitivity  
VDD range  
IDD  
IDD  
PDISS  
PSS  
PSS  
2.7  
5.5  
5
4
V
VIH = VDD or VIL = 0 V  
0.01  
0.9  
μA  
mA  
μW  
VIH = 2.4 V or 0.8 V, VDD = 5.5 V  
VIH = VDD or VIL = 0 V, VDD = 5.5 V  
ΔVDD = 5 V 10%  
27.5  
0.0035 0.008 %ꢀ%  
0.05 0.13 %ꢀ%  
ΔVDD = 3 V 10%  
Rev. E | Page 8 of 32  
 
AD8400/AD8402/AD8403  
Parameter  
DYNAMIC CHARACTERISTICS6, 10  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
Bandwidth −3 dB  
Total Harmonic Distortion  
VW Settling Time  
BW_1 K  
THDW  
tS  
R = 1 kΩ  
5,000  
0.015  
0.5  
kHz  
%
μs  
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz  
VA = VDD, VB = 0 V, 1% error band  
Resistor Noise Voltage  
Crosstalk11  
eNWB  
CT  
RS  
WB = 500 Ω, f = 1 kHz, = 0  
VA = VDD, VB = 0 V  
3
nVꢀ√Hz  
dB  
R
−65  
1 Typicals represent average readings at 25°C and VDD = 5 V.  
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper  
positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in Figure 38. IW = 500 μA for VDD = 3 V and  
IW = 2.5 mA for VDD = 5 V for 1 kΩ version.  
3 VAB = VDD, wiper (VW) = no connect.  
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DꢀA converter. VA = VDD and VB = 0 V.  
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.  
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.  
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.  
The remaining resistor terminals are left open circuit.  
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.  
8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.  
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.  
10 All dynamic characteristics use VDD = 5 V.  
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.  
Rev. E | Page 9 of 32  
AD8400/AD8402/AD8403  
ELECTRICAL CHARACTERISTICS—ALL VERSIONS  
VDD = 3 V 10% or 5 V 10%, VA = VDD, VB = 0 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted.  
Table 4.  
Parameter  
Symbol  
Conditions  
Min  
Typ1  
Max  
Unit  
SWITCHING CHARACTERISTICS2, 3  
Input Clock Pulse Width  
Data Setup Time  
Data Hold Time  
CLK to SDO Propagation Delay4  
tCH, tCL  
tDS  
tDH  
Clock level high or low  
10  
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPD  
RL = 1 kΩ to 5 V, CL ≤ 20 pF  
1
25  
CS  
CS  
tCSS  
tCSW  
tRS  
tCSH  
tCS1  
10  
10  
50  
0
Setup Time  
High Pulse Width  
Reset Pulse Width  
CS  
CLK Fall to  
Rise Hold Time  
Rise to Clock Rise Setup  
CS  
10  
1 Typicals represent average readings at 25°C and VDD = 5 V.  
2 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.  
The remaining resistor terminals are left open circuit.  
3 See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and  
timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate  
of 1 Vꢀμs should be maintained.  
4 Propagation delay depends on the value of VDD, RL, and CL (see the Applications section).  
TIMING DIAGRAMS  
1
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0  
SDI  
0
1
CLK  
tRS  
0
1
0
RS  
DAC REGISTER LOAD  
1
0
CS  
tS  
V
DD  
V
OUT  
±1%  
V
DD  
V
V
/2  
OUT  
DD  
±1% ERROR BAND  
0V  
Figure 5. Reset Timing Diagram  
Figure 3. Timing Diagram  
1
0
SDI  
(DATA IN)  
Ax OR Dx  
Ax OR Dx  
tDS  
tDH  
1
0
SDO  
(DATA OUT)  
A'x OR D'x  
tPD_MIN  
A'x OR D'x  
tPD_MAX  
tCS1  
tCH  
1
0
1
0
CLK  
CS  
tCL  
tCSS  
tCSH  
tCSW  
tS  
V
DD  
±1%  
V
OUT  
0V  
±1% ERROR BAND  
Figure 4. Detailed Timing Diagram  
Rev. E | Page 10 of 32  
 
 
 
 
 
AD8400/AD8402/AD8403  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted.  
Table 5.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Parameter  
Rating  
VDD to GND  
VA, VB, VW to GND  
−0.3 V, +8 V  
0 V, VDD  
Maximum Current  
IWB, IWA Pulsed  
IWB Continuous (RWB ≤ 1 kΩ, A Open)1  
IWA Continuous (RWA ≤ 1 kΩ, B Open)1  
20 mA  
5 mA  
5 mA  
IAB Continuous (RAB = 1 kΩꢀ10 kΩꢀ  
50 kΩꢀ100 kΩ)1  
Digital Input and Output Voltage  
to GND  
2.1 mAꢀ 2.1 mAꢀ  
540 ꢁAꢀ 540 ꢁA  
0 V, 7 V  
SERIAL DATA-WORD FORMAT  
Table 6.  
ADDR  
B8  
A0  
DATA  
Operating Temperature Range  
Maximum Junction Temperature  
(TJ Maximum)  
−40°C to +125°C  
150°C  
B9  
A1  
B7  
D7  
B6 B5 B4 B3 B2 B1 B0  
D6 D5 D4 D3 D2 D1 D0  
Storage Temperature  
Lead Temperature (Soldering, 10 sec)  
Package Power Dissipation  
Thermal Resistance (θJA)  
SOIC (R-8)  
PDIP (N-14)  
PDIP (N-24)  
SOIC (R-14)  
SOIC (R-24)  
−65°C to +150°C  
300°C  
(TJ max − TA)ꢀθJA  
MSB LSB MSB  
29 28 27  
LSB  
20  
158°CꢀW  
83°CꢀW  
63°CꢀW  
120°CꢀW  
70°CꢀW  
180°CꢀW  
143°CꢀW  
TSSOP-14 (RU-14)  
TSSOP-24 (RU-24)  
1 Maximum terminal current is bounded by the maximum applied voltage  
across any two of the A, B, and W terminals at a given resistance, the maximum  
current handling of the switches, and the maximum power dissipation of the  
package; VDD = 5 V.  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the  
human body and test equipment and can discharge without detection. Although this product features  
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy  
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
Rev. E | Page 11 of 32  
 
 
 
 
 
AD8400/AD8402/AD8403  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
B1  
GND  
CS  
1
2
3
4
8
7
6
5
A1  
AGND2  
B2  
1
2
3
4
5
6
7
8
9
24 B1  
1
2
3
4
5
6
7
AGND  
14  
13  
12  
11  
B1  
A1  
W1  
AD8400  
TOP VIEW  
(Not to Scale)  
W1  
23 A1  
B2  
A2  
22 W1  
21 AGND1  
20 B3  
V
DD  
A2  
AD8402  
TOP VIEW  
W2  
SDI  
CLK  
W2  
V
DD  
(Not to Scale)  
AD8403  
TOP VIEW  
(Not to Scale)  
AGND4  
B4  
DGND  
SHDN  
CS  
10 RS  
Figure 6. AD8400 Pin Configuration  
19 A3  
9
8
CLK  
SDI  
18  
W3  
17 AGND3  
16  
A4  
W4  
V
DGND  
DD  
Figure 7. AD8402 Pin Configuration  
15 RS  
SHDN 10  
CS 11  
14 CLK  
13 SDO  
SDI 12  
Figure 8. AD8403 Pin Configuration  
Table 7. AD8400 Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
Terminal B RDAC.  
Ground.  
1
2
3
B1  
GND  
CS  
CS  
Chip Select Input, Active Low. When returns high, data in the serial input register is decoded,  
based on the address bits, and loaded into the target DAC register.  
4
5
6
7
8
SDI  
CLK  
VDD  
W1  
A1  
Serial Data Input.  
Serial Clock Input, Positive Edge Triggered.  
Positive Power Supply. Specified for operation at both 3 V and 5 V.  
Wiper RDAC, Addr = 002.  
Terminal A RDAC.  
Table 8. AD8402 Pin Function Descriptions  
Pin No.  
Mnemonic  
AGND  
B2  
A2  
W2  
DGND  
SHDN  
CS  
Description  
1
2
3
4
5
6
7
Analog Ground.1  
Terminal B RDAC 2.  
Terminal A RDAC 2.  
Wiper RDAC 2, Addr = 012.  
Digital Ground.1  
Terminal A Open Circuit. Shutdown controls Variable Resistor 1 and Variable Resistor 2.  
CS  
Chip Select Input, Active Low. When returns high, data in the serial input register is decoded,  
based on the address bits, and loaded into the target DAC register.  
8
9
SDI  
CLK  
RS  
Serial Data Input.  
Serial Clock Input, Positive Edge Triggered.  
Active Low Reset to Midscale. Sets RDAC registers to 80H.  
Positive Power Supply. Specified for operation at both 3 V and 5 V  
Wiper RDAC 1, Addr = 002.  
Terminal A RDAC 1.  
Terminal B RDAC 1.  
10  
11  
12  
13  
14  
VDD  
W1  
A1  
B1  
1 All AGND pins must be connected to DGND.  
Rev. E | Page 12 of 32  
 
 
AD8400/AD8402/AD8403  
Table 9. AD8403 Pin Function Descriptions  
Pin No. Mnemonic  
Description  
1
2
AGND2  
B2  
Analog Ground 2.1  
Terminal B RDAC 2.  
Terminal A RDAC 2.  
Wiper RDAC 2, Addr = 012.  
Analog Ground 4.1  
Terminal B RDAC 4.  
Terminal A RDAC 4.  
Wiper RDAC 4, Addr = 112.  
Digital Ground.1  
3
A2  
4
W2  
5
6
AGND4  
B4  
7
A4  
8
W4  
9
10  
11  
DGND  
SHDN  
CS  
Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistor 1 through Variable Resistor 4.  
CS  
Chip Select Input, Active Low. When returns high, data in the serial input register is decoded,  
based on the address bits, and loaded into the target DAC register.  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
SDI  
Serial Data Input.  
SDO  
CLK  
RS  
Serial Data Output. Open drain transistor requires a pull-up resistor.  
Serial Clock Input, Positive Edge Triggered.  
Active Low Reset to Midscale. Sets RDAC registers to 80H.  
Positive Power Supply. Specified for operation at both 3 V and 5 V.  
Analog Ground 3.1  
Wiper RDAC 3, Addr = 102.  
Terminal A RDAC 3.  
Terminal B RDAC 3.  
Analog Ground 1.1  
VDD  
AGND3  
W3  
A3  
B3  
AGND1  
W1  
A1  
Wiper RDAC 1, Addr = 002.  
Terminal A RDAC 1.  
Terminal B RDAC 1.  
B1  
1 All AGND pins must be connected to DGND.  
Rev. E | Page 13 of 32  
 
AD8400/AD8402/AD8403  
TYPICAL PERFORMANCE CHARACTERISTICS  
10  
60  
48  
36  
24  
12  
0
SS = 1205 UNITS  
= 4.5V  
V
= 3V OR 5V  
DD  
V
R
= 10kΩ  
DD  
= 25°C  
AB  
T
A
8
6
4
2
0
R
R
WB  
WA  
0
32  
64  
96  
128  
160  
192  
224  
256  
40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0  
CODE (Decimal)  
WIPER RESISTANCE (Ω)  
Figure 9. Wiper to End Terminal Resistance vs. Code  
Figure 12. 10 kΩ Wiper-Contact-Resistance Histogram  
5
1.0  
0.5  
0
80  
H
V
= 5V  
DD  
FF  
H
4
3
2
1
0
40  
H
20  
H
T
= +25°C  
A
T
= –40°C  
A
CODE = 10  
H
–0.5  
T
= +85°C  
A
05  
H
T
V
= 25°C  
A
= 5V  
DD  
–1.0  
0
32  
64  
96  
128  
160  
192  
224  
256  
0
1
2
3
4
5
6
7
I
CURRENT (mA)  
DIGITAL INPUT CODE (Decimal)  
WB  
Figure 13. Potentiometer Divider Nonlinearity Error vs. Code  
Figure 10. Resistance Linearity vs. Conduction Current  
60  
1.0  
0.5  
0
SS = 184 UNITS  
V
= 5V  
DD  
V
= 4.5V  
DD  
T
= 25°C  
A
48  
36  
24  
12  
0
T
= +85°C  
A
T
= –40°C  
A
T
= +25°C  
A
–0.5  
–1.0  
0
32  
64  
96  
128  
160  
192  
224  
256  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
DIGITAL INPUT CODE (Decimal)  
WIPER RESISTANCE (Ω)  
Figure 11. Resistance Step Position Nonlinearity Error vs. Code  
Figure 14. 50 kΩ Wiper-Contact-Resistance Histogram  
Rev. E | Page 14 of 32  
 
AD8400/AD8402/AD8403  
60  
48  
36  
24  
12  
0
700  
600  
500  
400  
300  
200  
100  
0
SS = 184 UNITS  
V
T
V
= 5V  
DD  
V
T
= 4.5V  
= –40°C/+85°C  
= NO CONNECT  
MEASURED  
DD  
= 25°C  
A
A
A
R
WB  
–100  
40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0  
0
32  
64  
96  
128  
160  
192  
224  
256  
WIPER RESISTANCE (Ω)  
CODE (Decimal)  
Figure 15. 100 kΩ Wiper-Contact-Resistance Histogram  
Figure 18. ΔRWB/ΔT Rheostat Mode Tempco  
10  
8
20mV  
R
(END-TO-END)  
AB  
R
W
(20mV/DIV)  
6
R
(WIPER-TO-END)  
WB  
4
CODE = 80  
H
CS  
(5V/DIV)  
2
R
= 10kΩ  
AB  
5V  
500ns  
0
–75  
–50  
–25  
0
25  
50  
75  
100  
125  
TIME 500ns/DIV  
TEMPERATURE (°C)  
Figure 19. One Position Step Change at Half-Scale (Code 7FH to 80H)  
Figure 16. Nominal Resistance vs. Temperature  
6
70  
60  
50  
40  
30  
20  
10  
0
CODE = FF  
80  
V
= 5V  
= –40°C/+85°C  
= 2V  
DD  
0
–6  
T
A
V
V
A
B
= 0V  
40  
–12  
20  
–18  
10  
–24  
08  
–30  
–36  
–42  
04  
02  
01  
–48  
T
= 25°C  
A
–54  
–10  
10  
100  
1k  
10k  
100k  
1M  
0
32  
64  
96  
128  
160  
192  
224  
256  
FREQUENCY (Hz)  
CODE (Decimal)  
Figure 20. 10 kΩ Gain vs. Frequency vs. Code  
(See Figure 43)  
Figure 17. ΔVWB/ΔT Potentiometer Mode Tempco  
Rev. E | Page 15 of 32  
 
 
AD8400/AD8402/AD8403  
10  
1
0.75  
CODE = 80  
FILTER = 22kHz  
V = 5V  
H
V
= 5V  
DD  
SS = 158 UNITS  
DD  
= 25°C  
T
A
0.50  
0.25  
0
AVERAGE + 2 SIGMA  
AVERAGE  
0.1  
–0.25  
–0.50  
–0.75  
AVERAGE – 2 SIGMA  
0.01  
0.001  
10  
100  
1k  
10k  
100k  
0
100  
200  
300  
400  
500  
600  
HOURS OF OPERATION AT 150°C  
FREQUENCY (Hz)  
Figure 21. Long-Term Drift Accelerated by Burn-In  
Figure 24. Total Harmonic Distortion Plus Noise vs. Frequency  
(See Figure 41 and Figure 42)  
2V  
45.25μs  
OUTPUT  
V
OUT  
(50mV/DIV)  
INPUT  
50mV  
200ns  
5V  
5μs  
TIME 200ns/DIV  
TIME 500μs/DIV  
Figure 25. Digital Feedthrough vs. Time  
Figure 22. Large Signal Settling Time  
6
0
6
0
CODE = FF  
CODE = FF  
H
H
80  
40  
H
H
–6  
–6  
80  
40  
20  
H
H
–12  
–12  
20  
10  
08  
04  
02  
01  
H
H
H
H
H
H
–18  
–24  
–18  
–24  
–30  
H
10  
08  
H
H
–30  
–36  
–42  
–36  
–42  
04  
H
02  
01  
H
H
–48  
–54  
–48  
–54  
1k  
10k  
100k  
FREQUENCY (Hz)  
1M  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
Figure 26. 100 kΩ Gain vs. Frequency vs. Code  
Figure 23. 50 kΩ Gain vs. Frequency vs. Code  
Rev. E | Page 16 of 32  
AD8400/AD8402/AD8403  
12  
CODE = 80  
H
V
T
= 5V  
DD  
= 25°C  
ꢁ
6
0
f
= 700kHz, R = 10k  
Ω
–3dB  
A
–6  
= 71kHz, R = 100kΩ  
f
R = 10kΩ  
–3dB  
–12  
–18  
–24  
–30  
–36  
–42  
f
= 125kHz, R = 50kΩ  
–3dB  
R = 50kΩ  
V
V
R
= 100mV rms  
IN  
R = 100kΩ  
= 5V  
DD  
= 1MΩ  
L
10  
100  
1k  
10k  
100k  
1M  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 27. Normalized Gain Flatness vs. Frequency  
(See Figure 43)  
Figure 30. −3 dB Bandwidths  
10  
1200  
1000  
800  
600  
400  
200  
0
T
A
= 25°C  
A: V = 5.5V  
DD  
T
= 25°C  
A
CODE = 55  
H
H
B: V = 3.3V  
DD  
CODE = 55  
C: V = 5.5V  
DD  
CODE = FF  
H
1
D: V = 3.3V  
DD  
CODE = FF  
H
V
= 5V  
DD  
0.1  
B
A
C
D
V
= 3V  
DD  
0.01  
0
1
2
3
4
5
1k  
10k  
100k  
1M  
10M  
DIGITAL INPUT VOLTAGE (V)  
FREQUENCY (Hz)  
Figure 28. Supply Current vs. Digital Input Voltage  
Figure 31. Supply Current vs. Clock Frequency  
80  
60  
40  
160  
140  
120  
100  
80  
V
= +5V DC ±1V p-p AC  
DD  
= 25°C  
T
= 25°C  
A
T
A
CODE = 80  
C
V
H
V
= 2.7V  
= 10pF  
DD  
L
= 4V, V = 0V  
A
B
V
= 5.5V  
DD  
60  
20  
40  
20  
0
0
100  
1k  
10k  
100k  
1M  
0
1
2
3
4
5
6
FREQUENCY (Hz)  
V
(V)  
BIAS  
Figure 29. Power Supply Rejection Ratio vs. Frequency  
(See Figure 40)  
Figure 32. AD8403 Incremental Wiper On Resistance vs. VDD  
(See Figure 39)  
Rev. E | Page 17 of 32  
 
 
AD8400/AD8402/AD8403  
1
LOGIC INPUT  
VOLTAGE = 0, V  
0
–10  
–20  
DD  
0.1  
0
–45  
–90  
V
= 5.5V  
DD  
0.01  
V
= 5V  
DD  
= 25°C  
T
A
WIPER SET AT  
V
= 3.3V  
85  
DD  
HALF-SCALE 80  
H
0.001  
100k  
200k  
400k  
1M  
2M  
4M 6M  
10M  
–55  
–35  
–15  
5
25  
45  
65  
105  
125  
FREQUENCY (Hz)  
TEMPERATURE (°C)  
Figure 35. Supply Current vs. Temperature  
Figure 33. 1 kΩ Gain and Phase vs. Frequency  
100  
6
5
4
3
2
1
0
V
= 5V  
DD  
R
= 1kΩ  
AB  
V
T
= V = OPEN  
B
= 25°C  
A
A
10  
R
= 10kΩ  
AB  
R
= 50kΩ  
AB  
R
= 100kΩ  
AB  
1
–55  
–35  
–15  
5
25  
45  
65  
85  
105  
125  
0
32  
64  
96  
128  
160  
192  
224  
256  
TEMPERATURE (°C)  
CODE (Decimal)  
Figure 34. Shutdown Current vs. Temperature  
Figure 36. IWB_MAX vs. Code  
Rev. E | Page 18 of 32  
 
AD8400/AD8402/AD8403  
TEST CIRCUITS  
A
B
DUT  
IN  
DUT  
V+ = V  
1LSB = V+/256  
DD  
5V  
OP279  
W
V
A
V
OUT  
~
W
V+  
OFFSET  
GND  
B
V
MS  
2.5V DC  
Figure 37. Potentiometer Divider Nonlinearity Error (INL, DNL)  
Figure 41. Inverting Programmable Gain  
5V  
NO CONNECT  
DUT  
V
OUT  
OP279  
B
I
W
V
IN  
A
W
~
W
B
A
OFFSET  
GND  
V
DUT  
MS  
2.5V  
Figure 38. Resistor Position Nonlinearity Error  
(Rheostat Operations; R-INL, R-DNL)  
Figure 42. Noninverting Programmable Gain  
A
B
DUT  
+15V  
I
= V /R  
DD NOMINAL  
W
W
V
A
W
V
~
IN  
DUT  
W
V
MS2  
V
OP42  
OUT  
OFFSET  
GND  
B
R
= [V  
MS1  
– V ]/I  
MS2 W  
V
W
MS1  
2.5V  
–15V  
Figure 39. Wiper Resistance  
Figure 43. Gain vs. Frequency  
0.1V  
R
=
SW  
DUT  
I
SW  
V
A
CODE =  
H
W
A
V
DD  
V+ = V ± 10%  
DD  
+
V+  
W
~
B
0.1V  
I
ΔV  
SW  
MS  
DD  
–
PSRR (dB) = 20LOG  
(
)
B
ΔV  
V
MS  
ΔV  
ΔV  
%
MS  
V
A = NC  
PSS (%/%) =  
BIAS  
%
DD  
Figure 40. Power Supply Sensitivity (PSS, PSRR)  
Figure 44. Incremental On Resistance  
Rev. E | Page 19 of 32  
 
 
 
 
 
 
 
 
AD8400/AD8402/AD8403  
THEORY OF OPERATION  
The AD8400/AD8402/AD8403 provide a single, dual, and quad  
channel, 256-position, digitally controlled variable resistor (VR)  
device. Changing the programmed VR setting is accomplished  
by clocking in a 10-bit serial data-word into the SDI (Serial  
Data Input) pin. The format of this data-word is two address  
bits, MSB first, followed by eight data bits, also MSB first.  
Table 6 provides the serial register data-word format. The  
AD8400/AD8402/AD8403 have the following address assign-  
ments for the ADDR decoder, which determines the location  
of the VR latch receiving the serial register data in Bit B7 to  
Bit B0:  
PROGRAMMING THE VARIABLE RESISTOR  
Rheostat Operation  
The nominal resistance of the VR (RDAC) between Terminal A  
and Terminal B is available with values of 1 kΩ, 10 kΩ, 50 kΩ,  
and 100 kΩ. The final digits of the part number determine the  
nominal resistance value; that is, 10 kΩ = 10; 100 kΩ = 100.  
The nominal resistance (RAB) of the VR has 256 contact points  
accessible by the wiper terminal, and the resulting resistance  
can be measured either across the wiper and B terminals (RWB  
)
or across the wiper and A terminals (RWA). The 8-bit data-word  
loaded into the RDAC latch is decoded to select one of the  
256 possible settings. The wiper’s first connection starts at the  
B terminal for data 00H. This B terminal connection has a wiper  
contact resistance of 50 Ω. The second connection (for the 10 kΩ  
part) is the first tap point located at 89 Ω = [RAB (nominal  
resistance) + RW = 39 Ω + 50 Ω] for data 01H. The third  
connection is the next tap point representing 78 Ω + 50 Ω =  
128 Ω for data 02H. Each LSB data value increase moves the  
wiper up the resistor ladder until the last tap point is reached at  
10,011 Ω. Note that the wiper does not directly connect to the  
B terminal even for data 00H. See Figure 45 for a simplified  
diagram of the equivalent RDAC circuit.  
VR# = A1 × 2 + A0 + 1  
(1)  
The single-channel AD8400 requires A1 = A0 = 0. The dual-  
channel AD8402 requires A1 = 0. VR settings can be changed  
one at a time in random sequence. A serial clock running at  
10 MHz makes it possible to load all four VRs under 4 μs  
(10 × 4 × 100 ns) for AD8403. The exact timing requirements  
are shown in Figure 3, Figure 4, and Figure 5.  
The AD8400/AD8402/AD8403 do not have power-on midscale  
preset, so the wiper can be at any random position at power-up.  
However, the AD8402/AD8403 can be reset to midscale by  
RS  
asserting the pin, simplifying initial conditions at power-up.  
The AD8400 contains one RDAC, the AD8402 contains  
two independent RDACs, and the AD8403 contains four  
independent RDACs. The general transfer equation that  
determines the digitally programmed output resistance  
between Wx and Bx is  
SHDN  
Both parts have a power shutdown  
pin that places the  
VR in a zero-power-consumption state where Terminal Ax is  
open-circuited and the Wiper Wx is connected to Terminal Bx,  
resulting in the consumption of only the leakage current in the  
VR. In shutdown mode, the VR latch settings are maintained  
so that upon returning to the operational mode, the VR settings  
return to the previous resistance values. The digital interface is  
still active in shutdown, except that SDO is deactivated. Code  
changes in the registers can be made during shutdown that will  
produce new wiper positions when the device is taken out of  
shutdown.  
D
(2)  
RWB  
(
D
)
=
× R AB + RW  
256  
where D, in decimal, is the data loaded into the 8-bit RDAC#  
latch, and RAB is the nominal end-to-end resistance.  
For example, when the A terminal is either open-circuited or  
tied to the Wiper W, the following RDAC latch codes result in  
the following RWB (for the 10 kΩ version):  
Ax  
R
S
SHDN  
Table 10.  
D (Dec)  
R
S
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Output State  
RWB (Ω)  
10,011  
5,050  
89  
255  
128  
1
Full scale  
R
S
RS  
Midscale ( = 0 condition)  
1 LSB  
Wx  
0
50  
Zero-scale (wiper contact resistance)  
Note that in the zero-scale condition, a finite wiper resistance of  
50 Ω is present. Care should be taken to limit the current flow  
between W and B in this state to a maximum value of 5 mA to  
avoid degradation or possible destruction of the internal switch  
contact.  
RDAC  
LATCH  
AND  
R
S
Bx  
DECODER  
R
= R /256  
NOMINAL  
S
Figure 45. AD8402/AD8403 Equivalent VR (RDAC) Circuit  
Rev. E | Page 20 of 32  
 
 
 
AD8400/AD8402/AD8403  
Like a mechanical potentiometer, RDAC is symmetrical. The  
resistance between the Wiper W and Terminal A also produces  
a digitally controlled complementary resistance, RWA. When  
these terminals are used, the B terminal can be tied to the wiper  
or left floating. RWA starts at the maximum and decreases as the  
data loaded into the RDAC latch increases. The general transfer  
equation for this RWA is  
Here the output voltage is dependent on the ratio of the internal  
resistors, not the absolute value; therefore, the temperature drift  
improves to 15 ppm/°C.  
At the lower wiper position settings, the potentiometer divider  
temperature coefficient increases because the contribution of  
the CMOS switch wiper resistance becomes an appreciable  
portion of the total resistance from the B terminal to the  
Wiper W. See Figure 17 for a plot of potentiometer tempco  
performance vs. code setting.  
256− D  
(3)  
RWA  
(
D
)
=
× RAB + RW  
256  
where D is the data loaded into the 8-bit RDAC# latch, and RAB  
is the nominal end-to-end resistance.  
DIGITAL INTERFACING  
The AD8400/AD8402/AD8403 contain a standard SPI-  
compatible, 3-wire, serial input control interface. The three  
inputs are clock (CLK), chip select ( ), and serial data input  
(SDI). The positive-edge sensitive CLK input requires clean  
transitions to avoid clocking incorrect data into the serial input  
register. For the best result, use logic transitions faster than  
1 V/μs. Standard logic families work well. If mechanical switches  
are used for product evaluation, they should be debounced by  
a flip-flop or other suitable means. The block diagrams in  
Figure 46, Figure 47, and Figure 48 show the internal digital  
For example, when the B terminal is either open-circuited or  
tied to the Wiper W, the following RDAC latch codes result in  
the following RWA (for the 10 kΩ version):  
CS  
Table 11.  
D (Dec)  
Output State  
R
WA (Ω)  
255  
128  
1
89  
Full-Scale  
5,050  
10,011  
10,050  
RS  
Midscale ( = 0 Condition)  
1 LSB  
Zero-Scale  
0
CS  
circuitry in more detail. When  
is taken active low, the clock  
loads data into the 10-bit serial register on each positive clock  
edge (see Table 12).  
The typical distribution of RAB from channel to channel  
matches within 1%. However, device-to-device matching  
is process lot dependent and has a 20% variation. The tem-  
perature coefficient, or the change in RAB with temperature,  
is 500 ppm/°C.  
V
CS  
DD  
A1  
W1  
B1  
CLK  
D7  
D0  
EN  
RDAC  
LATCH  
NO. 1  
ADDR  
DEC  
A1  
A0  
The wiper-to-end-terminal resistance temperature coefficient  
has the best performance over the 10% to 100% of adjustment  
range where the internal wiper contact switches do not con-  
tribute any significant temperature related errors. The graph in  
Figure 18 shows the performance of RWB tempco vs. code. Using  
the potentiometer with codes below 32 results in the larger  
temperature coefficients plotted.  
D7  
10-BIT  
SER  
REG  
AD8400  
SDI  
DI D0  
8
GND  
PROGRAMMING THE POTENTIOMETER DIVIDER  
Figure 46. AD8400 Block Diagram  
Voltage Output Operation  
The digital potentiometer easily generates an output voltage  
proportional to the input voltage applied to a given terminal.  
V
CS  
AD8402  
DD  
A1  
W1  
B1  
CLK  
D7  
RDAC  
LATCH  
NO. 1  
EN  
For example, connecting the A terminal to 5 V and the B termi-  
nal to ground produces an output voltage at the wiper starting  
at 0 V up to 1 LSB less than 5 V. Each LSB is equal to the voltage  
applied across the A to B terminals divided by the 256-position  
resolution of the potentiometer divider. The general equation  
defining the output voltage with respect to ground for any given  
input voltage applied to the A to B terminals is  
ADDR  
DEC  
R
D0  
A1  
A0  
D7  
A4  
10-BIT  
SER  
REG  
D7  
D0  
RDAC  
LATCH  
NO. 2  
R
W4  
B4  
SDI  
DI D0  
8
D
SHDN  
(4)  
VW  
=
×VAB +VB  
256  
DGND  
AGND  
RS  
Operation of the digital potentiometer in the voltage divider  
mode results in more accurate operation over temperature.  
Figure 47. AD8402 Block Diagram  
Rev. E | Page 21 of 32  
 
 
 
 
AD8400/AD8402/AD8403  
If two AD8403 RDACs are daisy-chained, it requires 20 bits  
of address and data in the format shown in Table 6. During  
V
CS  
DD  
A1  
W1  
B1  
CLK  
D7  
D0  
SHDN  
shutdown (  
= logic low), the SDO output pin is forced  
EN  
RDAC  
LATCH  
NO. 1  
R
to the off (logic high) state to disable power dissipation in the  
pull-up resistor. See Figure 50 for equivalent SDO output circuit  
schematic.  
ADDR  
DEC  
A1  
A0  
D7  
DO  
SDO  
The data setup and hold times in the specification table deter-  
mine the data valid time requirements. The last 10 bits of the  
SER  
REG  
AD8403  
CS  
data-word entered into the serial register are held when  
A4  
W4  
B4  
CS  
returns high. At the same time  
goes high it gates the address  
decoder, which enables one of the two (AD8402) or four (AD8403)  
positive edge-triggered RDAC latches. See Figure 49 and Table 13.  
D7  
D0  
SDI  
DI  
D0  
RDAC  
LATCH  
NO. 4  
R
8
Table 13. Address Decode Table  
A1  
A0  
Latch Decoded  
SHDN  
0
0
1
1
0
1
0
1
RDAC#1  
RDAC#2  
RDAC#3 AD8403 Only  
RDAC#4 AD8403 Only  
DGND  
AGND  
RS  
Figure 48. AD8403 Block Diagram  
1
Table 12. Input Logic Control Truth Table  
CLK CS RS SHDN Register Activity  
AD8403  
RDAC 1  
RDAC 2  
L
P
L
L
H
H
H
H
No SR effect; enables SDO pin  
CS  
ADDR  
DECODE  
Shift one bit in from the SDI pin. The  
10th previously entered bit is shifted  
out of the SDO pin.  
RDAC 4  
CLK  
SDI  
SERIAL  
REGISTER  
X
P
H
H
Load SR data into RDAC latch based  
on A1, A0 decode (Table 13).  
Figure 49. Equivalent Input Control Logic  
X
X
H
X
H
L
H
H
No operation  
Sets all RDAC latches to midscale,  
wiper centered, and SDO latch  
cleared  
The target RDAC latch is loaded with the last eight bits of the  
serial data-word completing one RDAC update. In the case of  
AD8403, four separate 10-bit data-words must be clocked in to  
change all four VR settings.  
X
X
H
H
P
H
H
L
Latches all RDAC latches to 80H  
Open-circuits all Resistor A terminals,  
connects W to B, turns off SDO  
output transistor.  
SHDN  
1 P = positive edge, X = don’t care, SR = shift register  
CS  
SDO  
SERIAL  
REGISTER  
D
Q
SDI  
The serial data output (SDO) pin, which exists only on the  
AD8403 and not on the AD8400 or AD8402, contains an  
open-drain, n-channel FET that requires a pull-up resistor to  
transfer data to the SDI pin of the next package. The pull-up  
resistor termination voltage may be larger than the VDD supply  
(but less than the max VDD of 8 V) of the AD8403 SDO output  
device. For example, the AD8403 could operate at VDD = 3.3 V,  
and the pull-up for interface to the next device could be set at 5 V.  
This allows for daisy-chaining several RDACs from a single proc-  
essor serial data line. The clock period needs to be increased  
when using a pull-up resistor to the SDI pin of the following  
device in the series. Capacitive loading at the daisy-chain node  
SDO to SDI between devices must be accounted for in order to  
CK RS  
CLK  
RS  
Figure 50. Detailed SDO Output Schematic of the AD8403  
All digital pins are protected with a series input resistor and  
parallel Zener ESD structure shown in Figure 51. This structure  
applies to digital pins , SDI, SDO,  
digital input ESD protection allows for mixed power supply  
applications where 5 V CMOS logic can be used to drive an  
AD8400, AD8402, or AD8403 operating from a 3 V power  
supply. Analog Pin A, Pin B, and Pin W are protected with a  
20 Ω series resistor and parallel Zener diode (see Figure 52).  
CS  
RS SHDN  
, , and CLK. The  
transfer data successfully. When daisy chain is used,  
should  
CS  
be kept low until all the bits of every package are clocked into  
their respective serial registers and the address and data bits are  
in the proper decoding location.  
Rev. E | Page 22 of 32  
 
 
 
 
 
 
AD8400/AD8402/AD8403  
1kΩ  
DIGITAL  
PINS  
Listing I. Macro Model Net List for RDAC  
LOGIC  
.PARAM DW=255, RDAC=10E3  
Figure 51. Equivalent ESD Protection Circuits  
*
.SUBCKT DPOT (A,W,)  
*
20  
Ω
CA A 0 {DW/256*90.4E-12+30E-12}  
RAW A W {(1-DW/256)*RDAC+50}  
CW W 0 120E-12  
A, B, W  
RBW W B {DW/256*RDAC+50}  
CB B 0 {(1-DW/256)*90.4E-12+30E-12}  
*
Figure 52. Equivalent ESD Protection Circuit (Analog Pins)  
.ENDS DPOT  
RDAC  
10kΩ  
A
B
The total harmonic distortion plus noise (THD + N), shown in  
Figure 41, is measured at 0.003% in an inverting op amp circuit  
using an offset ground and a rail-to-rail OP279 amplifier.  
Thermal noise is primarily Johnson noise, typically 9 nV/√Hz  
for the 10 kΩ version at f = 1 kHz. For the 100 kΩ device,  
thermal noise becomes 29 nV/√Hz. Channel-to-channel  
crosstalk measures less than −65 dB at f = 100 kHz. To achieve  
this isolation, the extra ground pins provided on the package to  
segregate the individual RDACs must be connected to circuit  
ground. AGND and DGND pins should be at the same voltage  
potential. Any unused potentiometers in a package should be  
connected to ground. Power supply rejection is typically −35 dB  
at 10 kHz. Care is needed to minimize power supply ripple in  
high accuracy applications.  
C
C
B
A
C
120pF  
W
W
C
= 90.4pF (DW/256) + 30pF  
C = 90.4pF [1 – (DW/256)] + 30pF  
B
A
Figure 53. RDAC Circuit Simulation Model for RDAC = 10 kΩ  
The AC characteristics of the RDAC are dominated by the  
internal parasitic capacitances and the external capacitive loads.  
The −3 dB bandwidth of the AD8403AN10 (10 kΩ resistor)  
measures 600 kHz at half scale as a potentiometer divider.  
Figure 30 provides the large signal Bode plot characteristics  
of the three available resistor versions 10 kΩ, 50 kΩ, and 100 kΩ.  
The gain flatness vs. frequency graph of the 1 kΩ version predicts  
filter applications performance (see Figure 33). A parasitic  
simulation model has been developed and is shown in Figure 53.  
Listing I provides a macro model net list for the 10 kΩ RDAC.  
Rev. E | Page 23 of 32  
 
 
 
AD8400/AD8402/AD8403  
APPLICATIONS  
256  
224  
192  
160  
128  
96  
The digital potentiometer (RDAC) allows many of the applica-  
tions of a mechanical potentiometer to be replaced by a solid-  
state solution offering compact size and freedom from vibration,  
shock, and open contact problems encountered in hostile  
environments. A major advantage of the digital potentiometer  
is its programmability. Any settings can be saved for later recall  
in system memory.  
The two major configurations of the RDAC include the  
potentiometer divider (basic 3-terminal application) and  
the rheostat (2-terminal configuration) connections shown  
in Figure 37 and Figure 38.  
64  
32  
0
0.1  
1
10  
Certain boundary conditions must be satisfied for proper  
AD8400/AD8402/AD8403 operation. First, all analog signals  
must remain within the GND to VDD range used to operate the  
single-supply AD8400/AD8402/AD8403. For standard  
potentiometer divider applications, the wiper output can be  
used directly. For low resistance loads, buffer the wiper with  
a suitable rail-to-rail op amp such as the OP291 or the OP279.  
Second, for ac signals and bipolar dc adjustment applications,  
a virtual ground is generally needed. Whichever method is used  
to create the virtual ground, the result must provide the necessary  
sink and source current for all connected loads, including  
adequate bypass capacitance. Figure 41 shows one channel of  
the AD8402 connected in an inverting programmable gain  
amplifier circuit. The virtual ground is set at 2.5 V, which allows  
the circuit output to span a 2.5 V range with respect to virtual  
ground. The rail-to-rail amplifier capability is necessary for the  
widest output swing. As the wiper is adjusted from its midscale  
reset position (80H) toward the A terminal (code FFH), the  
voltage gain of the circuit is increased in successively larger  
increments. Alternatively, as the wiper is adjusted toward the B  
terminal (code 00H), the signal becomes attenuated. The plot in  
Figure 54 shows the wiper settings for a 100:1 range of voltage  
gain (V/V). Note the 10 dB of pseudologarithmic gain around  
0 dB (1 V/V). This circuit is mainly useful for gain adjustments  
in the range of 0.14 V/V to 4 V/V; beyond this range the step  
sizes become very large, and the resistance of the driving circuit  
can become a significant term in the gain equation.  
INVERTING GAIN (V/V)  
Figure 54. Inverting Programmable Gain Plot  
ACTIVE FILTER  
The state variable active filter is one of the standard circuits  
used to generate a low-pass, high-pass, or band-pass filter.  
The digital potentiometer allows full programmability of the  
frequency, gain, and Q of the filter outputs. Figure 55 shows  
the filter circuit using a 2.5 V virtual ground, which allows a  
2.5 VP input and output swing. RDAC2 and RDAC3 set the  
LP, HP, and BP cutoff and center frequencies, respectively.  
These variable resistors should be programmed with the same  
data (as with ganged potentiometers) to maintain the best  
Circuit Q. Figure 56 shows the measured filter response at the  
band-pass output as a function of the RDAC2 and RDAC3  
settings that produce a range of center frequencies from 2 kHz  
to 20 kHz. The filter gain response at the band-pass output is  
shown in Figure 57. At a center frequency of 2 kHz, the gain is  
adjusted over a −20 dB to +20 dB range determined by RDAC1.  
Circuit Q is adjusted by RDAC4. For more detailed reading on  
the state variable active filter, see Analog Devices’ application  
note AN-318.  
10kΩ  
10kΩ  
RDAC4  
B
0.01μF  
0.01μF  
V
IN  
A1  
B
RDAC1  
B
A2  
LOW-  
PASS  
B
RDAC2  
A3  
RDAC3  
A4  
BAND-  
PASS  
OP279 × 2  
HIGH-  
PASS  
Figure 55. Programmable State Variable Active Filter  
Rev. E | Page 24 of 32  
 
 
 
 
 
AD8400/AD8402/AD8403  
40  
20  
40  
20  
–0.16  
20.0000 k  
–19.01  
2.00000 k  
0
0
–20  
–40  
–60  
–80  
–20  
–40  
–60  
–80  
20  
100  
1k  
FREQUENCY (Hz)  
10k  
100k 200k  
20  
100  
1k  
10k  
100k 200k  
FREQUENCY (Hz)  
Figure 56. Programmed Center Frequency Band-Pass Response  
Figure 57. Programmed Amplitude Band-Pass Response  
Rev. E | Page 25 of 32  
 
AD8400/AD8402/AD8403  
OUTLINE DIMENSIONS  
5.00 (0.1968)  
4.80 (0.1890)  
8
1
5
4
6.20 (0.2441)  
5.80 (0.2284)  
4.00 (0.1574)  
3.80 (0.1497)  
0.50 (0.0196)  
0.25 (0.0099)  
1.27 (0.0500)  
BSC  
45°  
1.75 (0.0688)  
1.35 (0.0532)  
0.25 (0.0098)  
0.10 (0.0040)  
8°  
0°  
0.51 (0.0201)  
0.31 (0.0122)  
COPLANARITY  
0.10  
1.27 (0.0500)  
0.40 (0.0157)  
0.25 (0.0098)  
0.17 (0.0067)  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MS-012-AA  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
Figure 58. 8-Lead Standard Small outline package [SOIC_N]  
Narrow Body (R-8)  
Dimensions shown in millimeters and (inches)  
0.775 (19.69)  
0.750 (19.05)  
0.735 (18.67)  
14  
1
8
7
0.280 (7.11)  
0.250 (6.35)  
0.240 (6.10)  
0.325 (8.26)  
0.310 (7.87)  
0.300 (7.62)  
0.100 (2.54)  
BSC  
0.060 (1.52)  
MAX  
0.195 (4.95)  
0.130 (3.30)  
0.115 (2.92)  
0.210 (5.33)  
MAX  
0.015  
(0.38)  
MIN  
0.150 (3.81)  
0.130 (3.30)  
0.110 (2.79)  
0.015 (0.38)  
GAUGE  
0.014 (0.36)  
0.010 (0.25)  
0.008 (0.20)  
PLANE  
SEATING  
PLANE  
0.022 (0.56)  
0.018 (0.46)  
0.014 (0.36)  
0.430 (10.92)  
MAX  
0.005 (0.13)  
MIN  
0.070 (1.78)  
0.050 (1.27)  
0.045 (1.14)  
COMPLIANT TO JEDEC STANDARDS MS-001  
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.  
Figure 59. 14-Lead Plastic Dual-In-Line Package [PDIP]  
Narrow Body (N-14)  
Dimensions shown in inches and (millimeters)  
Rev. E | Page 26 of 32  
 
AD8400/AD8402/AD8403  
8.75 (0.3445)  
8.55 (0.3366)  
8
7
14  
1
6.20 (0.2441)  
5.80 (0.2283)  
4.00 (0.1575)  
3.80 (0.1496)  
1.27 (0.0500)  
BSC  
0.50 (0.0197)  
0.25 (0.0098)  
45°  
1.75 (0.0689)  
1.35 (0.0531)  
0.25 (0.0098)  
0.10 (0.0039)  
8°  
0°  
COPLANARITY  
0.10  
SEATING  
PLANE  
1.27 (0.0500)  
0.40 (0.0157)  
0.51 (0.0201)  
0.31 (0.0122)  
0.25 (0.0098)  
0.17 (0.0067)  
COMPLIANT TO JEDEC STANDARDS MS-012-AB  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
Figure 60. 14-Lead Standard Small Outline Package [SOIC_N]  
Narrow Body (R-14)  
Dimensions shown in millimeters and (inches)  
5.10  
5.00  
4.90  
14  
8
7
4.50  
4.40  
4.30  
6.40  
BSC  
1
PIN 1  
0.65 BSC  
1.05  
1.00  
0.80  
1.20  
MAX  
0.20  
0.09  
0.75  
0.60  
0.45  
8°  
0°  
0.15  
0.05  
COPLANARITY  
0.10  
SEATING  
PLANE  
0.30  
0.19  
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1  
Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-14)  
Dimensions shown in millimeters  
Rev. E | Page 27 of 32  
AD8400/AD8402/AD8403  
1.280 (32.51)  
1.250 (31.75)  
1.230 (31.24)  
24  
13  
12  
0.280 (7.11)  
0.250 (6.35)  
0.240 (6.10)  
1
0.325 (8.26)  
0.310 (7.87)  
0.300 (7.62)  
0.100 (2.54)  
BSC  
0.060 (1.52)  
MAX  
0.195 (4.95)  
0.130 (3.30)  
0.115 (2.92)  
0.210 (5.33)  
MAX  
0.015  
(0.38)  
MIN  
0.150 (3.81)  
0.130 (3.30)  
0.115 (2.92)  
0.015 (0.38)  
GAUGE  
0.014 (0.36)  
0.010 (0.25)  
0.008 (0.20)  
PLANE  
SEATING  
PLANE  
0.022 (0.56)  
0.018 (0.46)  
0.014 (0.36)  
0.430 (10.92)  
MAX  
0.005 (0.13)  
MIN  
0.070 (1.78)  
0.060 (1.52)  
0.045 (1.14)  
COMPLIANT TO JEDEC STANDARDS MS-001  
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.  
Figure 62. 24-Lead Plastic Dual-In-Line Package [PDIP]  
Narrow Body (N-24-1)  
Dimensions shown in inches and (millimeters)  
15.60 (0.6142)  
15.20 (0.5984)  
24  
1
13  
12  
7.60 (0.2992)  
7.40 (0.2913)  
10.65 (0.4193)  
10.00 (0.3937)  
0.75 (0.0295)  
0.25 (0.0  
098)  
45°  
2.65 (0.1043)  
2.35 (0.0925)  
0.30 (0.0118)  
0.10 (0.0039)  
8°  
0°  
COPLANARITY  
0.10  
SEATING  
PLANE  
0.51 (0.0201)  
0.31 (0.0122)  
1.27 (0.0500)ꢁ  
BSC  
1.27 (0.0500)  
0.40 (0.0157)  
0.33 (0.0130)  
0.20 (0.0079)  
COMPLIANT TO JEDEC STANDARDS MS-013-AD  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
Figure 63. 24-Lead Standard Small Outline Package [SOIC_W]  
Wide Body (RW-24)  
Dimensions shown in millimeters and (inches)  
Rev. E | Page 28 of 32  
AD8400/AD8402/AD8403  
7.90  
7.80  
7.70  
24  
13  
12  
4.50  
4.40  
4.30  
6.40 BSC  
1
PIN 1  
0.65  
BSC  
1.20  
MAX  
0.15  
0.05  
0.75  
0.60  
0.45  
8°  
0°  
0.30  
0.19  
0.20  
0.09  
SEATING  
PLANE  
0.10 COPLANARITY  
COMPLIANT TO JEDEC STANDARDS MO-153-AD  
Figure 64. 24-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-24)  
Dimensions shown in millimeters  
Rev. E | Page 29 of 32  
AD8400/AD8402/AD8403  
ORDERING GUIDE  
Number of End-to-End Temperature Package  
Package Ordering  
Model1, 2, 3  
Channels  
RAB (kΩ)  
10  
10  
10  
10  
50  
50  
50  
50  
100  
100  
100  
100  
1
Range (°C)  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
Description  
Option  
Quantity Branding Information  
AD8400AR10  
AD8400AR10-REEL  
AD8400ARZ10  
AD8400ARZ10-REEL  
AD8400AR50  
AD8400AR50-REEL  
AD8400ARZ50  
AD8400ARZ50-REEL  
AD8400AR100  
AD8400AR100-REEL  
AD8400ARZ100  
AD8400ARZ100-REEL  
AD8400AR1  
AD8400AR1-REEL  
AD8400ARZ1  
AD8400ARZ1-REEL  
AD8402AN10  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
8-Lead SOIC_N  
14-Lead PDIP  
R-8  
98  
AD8400A10  
AD8400A10  
AD8400A10  
AD8400A10  
AD8400A50  
AD8400A50  
AD8400A50  
AD8400A50  
AD8400AC  
AD8400AC  
AD8400AC  
AD8400AC  
AD8400A1  
AD8400A1  
AD8400A1  
AD8400A1  
AD8402A10  
AD8402A10  
AD8402A10  
AD8402A10  
8402A10  
8402A10  
8402A10  
8402A10  
AD8402A10  
AD8402A10  
AD8402A50  
AD8402A50  
8402A50  
8402A50  
8402A50  
8402A50  
AD8402A50  
AD8402A50  
AD8402AC  
AD8402AC  
8402A-C  
R-8  
R-8  
2,500  
98  
R-8  
R-8  
2,500  
98  
R-8  
R-8  
2,500  
98  
R-8  
R-8  
2,500  
98  
R-8  
R-8  
2,500  
98  
R-8  
R-8  
2,500  
98  
1
1
1
R-8  
R-8  
2,500  
98  
R-8  
2,500  
25  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
50  
50  
50  
50  
50  
50  
50  
50  
100  
100  
100  
100  
100  
100  
100  
100  
1
N-14  
N-14  
R-14  
R-14  
RU-14  
RU-14  
RU-14  
RU-14  
R-14  
R-14  
R-14  
R-14  
RU-14  
RU-14  
RU-14  
RU-14  
R-14  
R-14  
R-14  
R-14  
RU-14  
RU-14  
RU-14  
RU-14  
R-14  
R-14  
R-14  
R-14  
RU-14  
RU-14  
RU-14  
R-14  
R-14  
AD8402ANZ10  
AD8402AR10  
14-Lead PDIP  
25  
56  
2,500  
96  
2,500  
96  
2,500  
96  
2,500  
56  
2,500  
96  
2,500  
96  
2,500  
96  
2,500  
56  
2,500  
96  
2,500  
96  
2,500  
96  
2,500  
56  
2,500  
96  
96  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead SOIC_N  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead TSSOP  
14-Lead SOIC_N  
14-Lead SOIC_N  
AD8402AR10-REEL  
AD8402ARU10  
AD8402ARU10-REEL  
AD8402ARUZ10  
AD8402ARUZ10-REEL  
AD8402ARZ10  
AD8402ARZ10-REEL  
AD8402AR50  
AD8402AR50-REEL  
AD8402ARU50  
AD8402ARU50-REEL  
AD8402ARUZ50  
AD8402ARUZ50-REEL  
AD8402ARZ50  
AD8402ARZ50-REEL  
AD8402AR100  
AD8402AR100-REEL  
AD8402ARU100  
AD8402ARU100-REEL  
AD8402ARUZ100  
AD8402ARUZ100-REEL  
AD8402ARZ100  
AD8402ARZ100-REEL  
AD8402AR1  
8402A-C  
8402A-C  
8402A-C  
AD8402AC  
AD8402AC  
AD8402A1  
AD8402A1  
8402A1  
AD8402A1  
AD8402A1  
AD8402A1  
AD8402A1  
AD8402AR1-REEL  
AD8402ARU1  
AD8402ARUZ1  
AD8402ARUZ1-REEL  
AD8402ARZ1  
AD8402ARZ1-REEL  
1
1
1
1
1
1
2,500  
56  
2,500  
Rev. E | Page 30 of 32  
 
AD8400/AD8402/AD8403  
Number of End-to-End Temperature Package  
Package Ordering  
Model1, 2, 3  
Channels  
RAB (kΩ)  
10  
10  
10  
10  
10  
10  
10  
10  
10  
50  
50  
50  
50  
50  
50  
50  
50  
100  
100  
100  
100  
100  
100  
100  
100  
1
Range (°C)  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
−40 to +125  
Description  
Option  
Quantity Branding Information  
AD8403AN10  
AD8403AR10  
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
24-Lead PDIP  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead PDIP  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead TSSOP  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
24-Lead SOIC_W RW-24  
Evaluation Board  
N-24-1  
15  
31  
1,000  
63  
2,500  
63  
2,500  
63  
2,500  
15  
31  
1,000  
63  
2,500  
2,500  
63  
2,500  
31  
1,000  
63  
2,500  
63  
2,500  
63  
2,500  
31  
1,000  
63  
2,500  
63  
AD8403A10  
AD8403A10  
AD8403A10  
8403A10  
8403A10  
8403A10  
AD8403AR10-REEL  
AD8403ARU10  
AD8403ARU10-REEL  
AD8403ARUZ10  
AD8403ARUZ10-REEL  
AD8403ARZ10  
AD8403ARZ10-REEL  
AD8403AN50  
AD8403AR50  
AD8403AR50-REEL  
AD8403ARU50  
AD8403ARUZ50  
AD8403ARUZ50-REEL  
AD8403ARZ50  
RU-24  
RU-24  
RU-24  
RU-24  
8403A10  
AD8403A10  
AD8403A10  
AD8403A50  
AD8403A50  
AD8403A50  
8403A50  
N-24-1  
RU-24  
RU-24  
RU-24  
8403A50  
8403A50  
AD8403A50  
AD8403A50  
AD8403A100  
AD8403A100  
8403A100  
8403A100  
8403A100  
8403A100  
AD8403A100  
AD8403A100  
AD8403A1  
AD8403A1  
8403A1  
AD8403ARZ50-REEL  
AD8403AR100  
AD8403AR100-REEL  
AD8403ARU100  
AD8403ARU100-REEL  
AD8403ARUZ100  
AD8403ARUZ100-REEL  
AD8403ARZ100  
AD8403ARZ100-REEL  
AD8403AR1  
AD8403AR1-REEL  
AD8403ARU1  
AD8403ARU1-REEL  
AD8403ARUZ1  
AD8403ARUZ1-REEL  
AD8403ARZ1  
AD8403ARZ1-REEL  
AD8403WARZ50-REEL  
EVAL-AD8403SDZ  
RU-24  
RU-24  
RU-24  
RU-24  
1
1
1
1
1
1
1
50  
RU-24  
RU-24  
RU-24  
RU-24  
8403A1  
8403A1  
8403A1  
AD8403A1  
AD8403A1  
2,500  
63  
2,500  
2,500  
1 Non-lead-free parts have date codes in the format of either YWW or YYWW, and lead-free parts have date codes in the format of #YWW, where Y/YY is the year of  
production and WW is the work week. For example, a non-lead-free part manufactured in the 30th work week of 2005 has the date code of either 530 or 0530, while a  
lead-free part has the date code of #530.  
2 Z = RoHS Compliant Part.  
3 W = Qualified for Automotive Applications.  
AUTOMOTIVE PRODUCTS  
The AD8403W models are available with controlled manufacturing to support the quality and reliability requirements of automotive  
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers  
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in  
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to  
obtain the specific Automotive Reliability reports for these models.  
Rev. E | Page 31 of 32  
 
AD8400/AD8402/AD8403  
NOTES  
©
2010 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D01092-0-7/10(E)  
Rev. E | Page 32 of 32  

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