AD8572ARZ-REEL7 [ADI]
Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers; 零漂移，单电源，轨到轨输入/输出运算放大器
| 型号： | AD8572ARZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers |
| 文件： | 总24页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Zero-Drift, Single-Supply, Rail-to-Rail
Input/Output Operational Amplifiers
AD8571/AD8572/AD8574
FEATURES
PIN CONFIGURATIONS
Low offset voltage: 1 μV
1
2
3
4
8
7
6
5
NC
–IN A
+IN A
V–
NC
NC
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
NC
AD8571
Input offset drift: 0.005 μV/°C
Rail-to-rail input and output swing
5 V/2.7 V single-supply operation
High gain, CMRR, PSRR: 130 dB
Ultralow input bias current: 20 pA
Low supply current: 750 μA/op amp
Overload recovery time: 50 μs
No external capacitors required
V+
V+
AD8571
TOP VIEW
OUT A
NC
OUT A
NC
TOP VIEW
(Not to Scale)
(Not to Scale)
NC = NO CONNECT
NC = NO CONNECT
Figure 1. 8-Lead MSOP
(RM Suffix)
Figure 2. 8-Lead SOIC
(R Suffix)
1
2
3
4
8
7
6
5
OUT A
–IN A
+IN A
V–
V+
1
2
3
4
8
7
6
5
OUT A
–IN A
+IN A
V–
V+
AD8572
TOP VIEW
(Not to Scale)
AD8572
TOP VIEW
(Not to Scale)
OUT B
–IN B
+IN B
OUT B
–IN B
+IN B
APPLICATIONS
Temperature sensors
Pressure sensors
Precision current sensing
Strain gage amplifiers
Medical instrumentation
Thermocouple amplifiers
Figure 3. 8-Lead TSSOP
(RU Suffix)
Figure 4. 8-Lead SOIC
(R Suffix)
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
OUT A
–IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 –IN D
12 +IN D
11 V–
13 –IN D
12 +IN D
11 V–
AD8574
TOP VIEW
(Not to Scale)
AD8574
TOP VIEW
(Not to Scale)
GENERAL DESCRIPTION
+IN B
–IN B
OUT B
10 +IN C
+IN B
–IN B
OUT B
10 +IN C
This family of amplifiers has ultralow offset, drift, and bias
current. The AD8571, AD8572, and AD8574 are single, dual,
and quad amplifiers, respectively, featuring rail-to-rail input
and output swings. All are guaranteed to operate from 2.7 V to
5 V single supply.
9
8
–IN C
9
8
–IN C
OUT C
OUT C
Figure 5. 14-Lead TSSOP
(RU Suffix)
Figure 6. 14-Lead SOIC
(R Suffix)
The AD857x family provides benefits previously found only in
expensive auto-zeroing or chopper-stabilized amplifiers. Using
Analog Devices, Inc. topology, these zero-drift amplifiers
combine low cost with high accuracy. (No external capacitors
are required.) Using a patented spread-spectrum auto-zero
technique, the AD857x family eliminates the intermodulation
effects from interaction of the chopping function with the
signal frequency in ac applications.
The AD857x family is specified for the extended industrial/
automotive (−40°C to +125°C) temperature range. The AD8571
single amplifier is available in 8-lead MSOP and narrow 8-lead
SOIC packages. The AD8572 dual amplifier is available in
8-lead narrow SOIC and 8-lead TSSOP surface mount packages.
The AD8574 quad amplifier is available in narrow 14-lead SOIC
and 14-lead TSSOP packages.
With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the
AD857x family is perfectly suited for applications where error
sources cannot be tolerated. Position and pressure sensors,
medical equipment, and strain gage amplifiers benefit greatly
from nearly zero drift over their operating temperature range.
Many more systems require the rail-to-rail input and output
swings provided by the AD857x family.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8571/AD8572/AD8574
TABLE OF CONTENTS
Features .............................................................................................. 1
1/f Noise Characteristics ........................................................... 17
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Electrical Characteristics...................................................... 3
2.7 V Electrical Characteristics................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Functional Description.................................................................. 14
Amplifier Architecture .............................................................. 14
Basic Auto-Zero Amplifier Theory.......................................... 14
Auto-Zero Phase......................................................................... 14
Amplification Phase................................................................... 15
High Gain, CMRR, PSRR.......................................................... 16
Maximizing Performance Through Proper Layout ................ 16
Random Auto-Zero Correction Eliminates Intermodulation
Distortion .................................................................................... 17
Broadband and External Resistor Noise Considerations.......... 18
Output Overdrive Recovery...................................................... 18
Input Overvoltage Protection................................................... 18
Output Phase Reversal............................................................... 18
Capacitive Load Drive ............................................................... 19
Power-Up Behavior.................................................................... 19
Applications..................................................................................... 20
5 V Precision Strain Gage Circuit ............................................ 20
3 V Instrumentation Amplifier ................................................ 20
High Accuracy Thermocouple Amplifier............................... 20
Precision Current Meter............................................................ 21
Precision Voltage Comparator.................................................. 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 23
REVISION HISTORY
09/06—Rev. A to Rev. B
07/03—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Renumbered Figures ..........................................................Universal
Changes to Figure 50...................................................................... 14
Changes to Figure 51...................................................................... 15
Changes to Figure 66...................................................................... 21
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 23
Renumbered Figures..........................................................Universal
Changes to Ordering Guide.............................................................4
Change to Figure 15. ...................................................................... 16
Updated Outline Dimensions....................................................... 19
10/99—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD8571/AD8572/AD8574
SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
1
5
μV
μV
pA
nA
pA
pA
V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
10
50
1.5
70
200
5
Input Bias Current
10
1.0
20
Input Offset Current
IOS
150
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 5 V
120
115
125
120
140
130
145
135
0.005
dB
dB
dB
dB
μV/°C
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 0.3 V to 4.7 V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain1
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
∆VOS/∆T
VOH
0.04
RL = 100 kΩ to GND
−40°C to +125°C
RL = 10 kΩ to GND
−40°C to +125°C
RL = 100 kΩ to V+
−40°C to +125°C
RL = 10 kΩ to V+
−40°C to +125°C
4.99
4.99
4.95
4.95
4.998
4.997
4.98
4.975
1
2
10
15
50
V
V
V
V
mV
mV
mV
mV
mA
mA
mA
mA
Output Voltage Low
VOL
10
10
30
30
Short-Circuit Limit
Output Current
ISC
IO
25
−40°C to +125°C
−40°C to +125°C
40
30
15
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 5.5 V
−40°C ≤ TA ≤ +125°C
VO = 0 V
120
115
130
130
850
1000
dB
dB
μA
μA
Supply Current/Amplifier
975
1075
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Overload Recovery Time
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise
SR
RL = 10 kΩ
0.4
0.05
1.5
V/μs
ms
MHz
0.3
GBP
en p-p
en p-p
en
0 Hz to 10 Hz
0 Hz to 1 Hz
f = 1 kHz
1.3
0.41
51
μV p-p
μV p-p
nV/√Hz
fA/√Hz
Voltage Noise Density
Current Noise Density
in
f = 10 Hz
2
1 Gain testing is dependent upon test bandwidth.
Rev. B | Page 3 of 24
AD8571/AD8572/AD8574
2.7 V ELECTRICAL CHARACTERISTICS
VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
1
5
μV
μV
pA
nA
pA
pA
V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
10
50
1.5
50
200
2.7
Input Bias Current
10
1.0
10
Input Offset Current
IOS
150
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 2.7 V
115
110
110
105
130
130
140
130
0.005
dB
dB
dB
dB
μV/°C
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 0.3 V to 2.4 V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Large Signal Voltage Gain1
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
∆VOS/∆T
VOH
0.04
RL = 100 kΩ to GND
−40°C to +125°C
RL = 10 kΩ to GND
−40°C to +125°C
RL = 100 kΩ to V+
−40°C to +125°C
RL = 10 kΩ to V+
−40°C to +125°C
2.685
2.685
2.67
2.697
2.696
2.68
2.675
1
2
10
15
15
V
V
V
V
mV
mV
mV
mV
mA
mA
mA
mA
2.67
Output Voltage Low
VOL
10
10
20
20
Short-Circuit Limit
Output Current
ISC
IO
10
−40°C to +125°C
−40°C to +125°C
10
10
5
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.7 V to 5.5 V
−40°C ≤ TA ≤ +125°C
VO = 0 V
120
115
130
130
750
950
dB
dB
μA
μA
Supply Current/Amplifier
900
1000
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Overload Recovery Time
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise
SR
RL = 10 kΩ
0.5
0.05
1
V/μs
ms
MHz
GBP
en p-p
en
in
0 Hz to 10 Hz
f = 1 kHz
f = 10 Hz
2.0
94
2
μV p-p
nV/√Hz
fA/√Hz
Voltage Noise Density
Current Noise Density
1 Gain testing is dependent upon test bandwidth.
Rev. B | Page 4 of 24
AD8571/AD8572/AD8574
ABSOLUTE MAXIMUM RATINGS
Table 3.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in a circuit board for SOIC and
TSSOP packages.
Parameter
Rating
Supply Voltage
Input Voltage
6 V
GND to VS + 0.3 V
5.0 V
2000 V
Differential Input Voltage1
ESD (Human Body Model)
Output Short-Circuit Duration to GND
Storage Temperature Range
RM, RU, and R Packages
Operating Temperature Range
AD8571A/AD8572A/AD8574A
Junction Temperature Range
RM, RU, and R Packages
Lead Temperature Range (Soldering, 60 sec)
Table 4. Thermal Resistance
Package Type
θJA
θJC
44
43
43
36
36
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
Indefinite
8-Lead MSOP (RM)
8-Lead TSSOP (RU)
8-Lead SOIC (R)
14-Lead TSSOP (RU)
14-Lead SOIC (R)
190
240
158
180
120
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
ESD CAUTION
1 Differential input voltage is limited to 5.0 V or the supply voltage,
whichever is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 5 of 24
AD8571/AD8572/AD8574
TYPICAL PERFORMANCE CHARACTERISTICS
180
160
140
120
100
80
180
V
V
T
= 5V
CM
= 25°C
V
V
T
= 2.7V
CM
= 25°C
S
S
160
140
120
100
80
= 2.5V
= 1.35V
A
A
60
60
40
40
20
20
0
–2.5
0
–2.5
–1.5
–0.5
0.5
1.5
2.5
–1.5
–0.5
0.5
1.5
2.5
OFFSET VOLTAGE (µV)
OFFSET VOLTAGE (µV)
Figure 10. Input Offset Voltage Distribution at 5 V
Figure 7. Input Offset Voltage Distribution at 2.7 V
50
40
12
10
8
V
= 5V
S
A
V
V
= 5V
T
= –40°C, +25°C, +85°C
S
= 2.5V
CM
= –40°C TO +125°C
T
A
30
+85°C
20
10
6
+25°C
–40°C
0
4
–10
–20
–30
2
0
0
1
2
3
4
5
0
1
2
3
4
5
6
INPUT COMMON-MODE VOLTAGE (V)
INPUT OFFSET DRIFT (nV/°C)
Figure 8. Input Bias Current vs. Common-Mode Voltage
Figure 11. Input Offset Voltage Drift Distribution at 5 V
10k
1k
1500
1000
V
= 5V
= 125°C
S
A
V
= 5V
= 25°C
S
A
T
T
500
0
100
10
SOURCE
–500
SINK
–1000
1
–1500
–2000
0.1
0.0001
0.001
0.01
0.1
1
10
100
0
1
2
3
4
5
LOAD CURRENT (mA)
COMMON-MODE VOLTAGE (V)
Figure 12. Output Voltage to Supply Rail vs. Output Current at 5 V
Figure 9. Input Bias Current vs. Common-Mode Voltage
Rev. B | Page 6 of 24
AD8571/AD8572/AD8574
10k
1k
800
700
600
500
400
300
200
100
0
V
= 2.7V
= 25°C
S
A
T
= 25°C
A
T
100
10
SINK
SOURCE
1
0.1
0.0001
0.001
0.01
0.1
1
10
100
0
1
2
3
4
5
6
LOAD CURRENT (mA)
SUPPLY VOLTAGE (V)
Figure 13. Output Voltage to Supply Rail vs. Output Current at 2.7 V
Figure 16. Supply Current vs. Supply Voltage
1000
60
50
V
= 2.7V
S
L
L
V
V
= 2.5V
CM
= 5V
C
R
= 0pF
S
=
∞
40
0
750
500
250
0
30
45
90
20
10
135
180
225
270
0
–10
–20
–30
–40
–75
–50
–25
0
25
50
75
100
125
150
10k
100k
1M
10M
100M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 17. Open-Loop Gain and Phase Shift vs. Frequency at 2.7 V
Figure 14. Bias Current vs. Temperature
60
1.0
0.8
0.6
V
= 5V
S
L
L
C
R
= 0pF
50
40
5V
=
∞
0
30
2.7V
45
90
20
10
135
180
225
270
0
0.4
0.2
–10
–20
–30
–40
0
–75
–50
–25
0
25
50
75
100
125
150
10k
100k
1M
10M
100M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 15. Supply Current vs. Temperature
Figure 18. Open-Loop Gain and Phase Shift vs. Frequency at 5 V
Rev. B | Page 7 of 24
AD8571/AD8572/AD8574
60
300
270
240
210
180
150
120
90
V
= 2.7V
= 0pF
= 2kΩ
S
L
L
V
= 5V
S
50
40
C
R
A
A
= –100
= –10
V
V
30
20
10
0
A
= 100
V
A
= +1
V
–10
–20
–30
–40
A
= 10
V
60
30
A
= 1
V
0
100
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Closed-Loop Gain vs. Frequency at 2.7 V
Figure 22. Output Impedance vs. Frequency at 5 V
60
50
V
= 2.7V
= 300pF
= 2kΩ
= 1
V
= 5V
= 0pF
= 2kΩ
S
S
L
L
C
R
A
C
R
L
L
V
40
30
A
A
= –100
= –10
V
20
V
10
0
A
= +1
V
–10
–20
–30
–40
2µs
500mV
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 23. Large Signal Transient Response at 2.7 V
Figure 20. Closed-Loop Gain vs. Frequency at 5 V
300
270
240
210
180
150
120
90
V
= 5V
S
V
= 2.7V
C
R
A
= 300pF
= 2kΩ
= 1
S
L
L
V
A
= 100
V
A
= 10
V
60
30
A
= 1
5µs
1V
V
0
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 24. Large Signal Transient Response at 5 V
Figure 21. Output Impedance vs. Frequency at 2.7 V
Rev. B | Page 8 of 24
AD8571/AD8572/AD8574
45
V
= ±1.35V
= 50pF
V
= ±2.5V
= 2kΩ
= 25°C
S
S
L
C
R
A
R
T
L
L
V
40
35
30
25
20
15
10
5
=
∞
A
= 1
+OS
–OS
5µs
50mV
0
10
100
1k
10k
CAPACITANCE (pF)
Figure 25. Small Signal Transient Response at 2.7 V
Figure 28. Small Signal Overshoot vs. Load Capacitance at 5 V
V
= ±2.5V
= 50pF
S
L
L
V
C
R
A
0V
=
∞
V
V
= ±2.5V
S
= 1
= –200mV p-p
(RET TO GND)
= 0pF
V
IN
IN
C
R
A
L
L
V
= 10kΩ
= –100
V
OUT
0V
20µs
1V
5µs
50mV
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
Figure 26. Small Signal Transient Response at 5 V
Figure 29. Positive Overvoltage Recovery
50
45
40
35
30
25
20
15
10
5
V
= ±1.35V
= 2kΩ
= 25°C
S
L
V
IN
R
T
A
0V
V
V
= ±2.5V
S
= 200mV p-p
(RET TO GND)
= 0pF
IN
C
R
A
L
L
V
+OS
= 10kΩ
= –100
0V
–OS
V
OUT
20µs
1V
0
10
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
100
1k
10k
CAPACITANCE (pF)
Figure 27. Small Signal Overshoot vs. Load Capacitance at 2.7 V
Figure 30. Negative Overvoltage Recovery
Rev. B | Page 9 of 24
AD8571/AD8572/AD8574
140
120
100
80
V
= ±2.5V
= 2kΩ
S
L
V
V
= ±1.35V
S
R
A
= –100
V
= 60mV p-p
IN
60
40
–PSRR
+PSRR
20
0
200µs
1V
100
1k
10k
100k
1M
10M
10M
1M
FREQUENCY (Hz)
Figure 31. No Phase Reversal
Figure 34. PSRR vs. Frequency at 1.35 V
140
120
100
80
140
120
100
80
V
= ±2.5V
S
V
= 2.7V
S
+PSRR
60
60
–PSRR
40
40
20
20
0
0
100
1k
10k
100k
1M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. CMRR vs. Frequency at 2.7 V
Figure 35. PSRR vs. Frequency at 2.5 V
140
120
100
80
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
S
V
= ±1.35V
= 2kΩ
= 1
THD + N < 1%
= 25°C
S
L
V
R
A
T
A
60
40
20
0
100
1k
10k
100k
1M
10M
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 33. CMRR vs. Frequency at 5 V
Figure 36. Maximum Output Swing vs. Frequency at 2.7 V
Rev. B | Page 10 of 24
AD8571/AD8572/AD8574
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
R
A
= ±2.5V
= 2kΩ
= 1
S
L
V
V
R
= 2.7V
= 0Ω
S
364
S
THD + N < 1%
T
= 25°C
A
312
260
208
156
104
52
0
0.5
1.0
1.5
2.0
2.5
100
1k
10k
100k
1M
FREQUENCY (kHz)
FREQUENCY (Hz)
Figure 37. Maximum Output Swing vs. Frequency at 5 V
Figure 40. Voltage Noise Density at 2.7 V from 0 Hz to 2.5 kHz
V
A
= ±1.35V
= 120,000
S
V
R
= 2.7V
= 0Ω
S
112
V
S
96
80
64
48
0V
32
16
50mV
1s
0
5
10
15
20
25
FREQUENCY (kHz)
Figure 38. 0.1 Hz to 10 Hz Noise at 2.7 V
Figure 41. Voltage Noise Density at 2.7 V from 0 Hz to 25 kHz
V
A
= ±2.5V
= 120,000
V
R
= 5V
= 0Ω
S
S
182
V
S
156
130
104
78
52
26
50mV
1s
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (kHz)
Figure 39. 0.1 Hz to 10 Hz Noise at 5 V
Figure 42. Voltage Noise Density at 5 V from 0 Hz to 2.5 kHz
Rev. B | Page 11 of 24
AD8571/AD8572/AD8574
150
145
140
135
130
125
V
R
= 5V
= 0Ω
S
V
= 2.7V TO 5.5V
112
S
S
96
80
64
48
32
16
0
5
10
15
20
25
–75
–50
–25
0
25
50
75
100
125
150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 43. Voltage Noise Density at 5 V from 0 Hz to 25 kHz
Figure 45. Power Supply Rejection vs. Temperature
50
40
V
R
= 5V
= 0Ω
S
V
= 2.7V
210
S
S
30
180
150
I
SC–
20
10
120
90
0
–10
–20
–30
–40
–50
I
SC+
60
30
0
5
10
–75
–50
–25
0
25
50
75
100
125
150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 44. Voltage Noise Density at 5 V from 0 Hz to 10 Hz
Figure 46. Output Short-Circuit Current vs. Temperature
Rev. B | Page 12 of 24
AD8571/AD8572/AD8574
100
80
250
225
200
V
= 5V
V
= 5V
S
S
60
I
SC–
40
175
150
125
R
= 1kΩ
L
20
0
100
75
50
25
0
–20
–40
–60
–80
–100
I
SC+
R
= 10kΩ
L
R
= 100kΩ
L
–75
–50
–25
0
25
50
75
100
125
150
–75
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 49. Output Voltage to Supply Rail vs. Temperature
Figure 47. Output Short-Circuit Current vs. Temperature
250
225
200
V
= 5V
S
175
150
125
R
= 1kΩ
L
100
75
50
25
0
R
0
= 10kΩ
L
R
= 100kΩ
L
–75
–50
–25
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 48. Output Voltage to Supply Rail vs. Temperature
Rev. B | Page 13 of 24
AD8571/AD8572/AD8574
FUNCTIONAL DESCRIPTION
The AD8571/AD8572/AD8574 are CMOS amplifiers that
achieve their high degree of precision through random
frequency auto-zero stabilization. The autocorrection topology
allows the AD857x to maintain its low offset voltage over a wide
temperature range, and the randomized auto-zero clock
eliminates any intermodulation distortion (IMD) errors at the
amplifier output.
BASIC AUTO-ZERO AMPLIFIER THEORY
Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for more than 15 years and
some improvements have been made over time. The AD857x
design offers a number of significant performance improve-
ments over older versions while attaining a very substantial
reduction in device cost. This section offers a simplified
explanation of how the AD857x is able to offer extremely low
offset voltages and high open-loop gains.
The AD857x can be run from a single-supply voltage as low as
2.7 V. The extremely low offset voltage of 1 μV and no IMD
products allows the amplifier to be easily configured for high
gains without risk of excessive output voltage errors. This makes
the AD857x an ideal amplifier for applications requiring both
dc precision and low distortion for ac signals. The extremely
small temperature drift of 5 nV/°C ensures a minimum of offset
voltage error over its entire temperature range of −40°C to
+125°C. These combined features make the AD857x an
excellent choice for a variety of sensitive measurement and
automotive applications.
As noted in the Amplifier Architecture section, each AD857x
op amp contains two internal amplifiers. One is used as the
primary amplifier, the other as an autocorrection, or nulling,
amplifier. Each amplifier has an associated input offset voltage
that can be modeled as a dc voltage source in series with the
noninverting input. In Figure 50 and Figure 51, these are
labeled as VOSX, where X denotes the amplifier associated
with the offset: A for the nulling amplifier, B for the primary
amplifier. The open-loop gain for the +IN and −IN inputs of
each amplifier is given as AX. Both amplifiers also have a third
voltage input with an associated open-loop gain of BX.
AMPLIFIER ARCHITECTURE
Each AD857x op amp consists of two amplifiers: a main amplifier
and a secondary amplifier that is used to correct the offset
voltage of the main amplifier. Both consist of a rail-to-rail input
stage, allowing the input common-mode voltage range to reach
both supply rails. The input stage consists of an NMOS
differential pair operating concurrently with a parallel PMOS
differential pair. The outputs from the differential input stages
are combined in another gain stage whose output is used to
drive a rail-to-rail output stage.
There are two modes of operation determined by the action of
two sets of switches in the amplifier: an auto-zero phase and an
amplification phase.
AUTO-ZERO PHASE
In this phase, all φA switches are closed and all φB switches are
opened. Here, the nulling amplifier is taken out of the gain loop
by shorting its two inputs together. Of course, there is a degree
of offset voltage, shown as VOSA, inherent in the nulling amplifier
that maintains a potential difference between the +IN and −IN
inputs. The nulling amplifier feedback loop is closed through
φA2 and VOSA appears at the output of the nulling amp and on
CM1, an internal capacitor in the AD857x. Mathematically, we
can express this in the time domain as
The wide voltage swing of the amplifier is achieved by using two
output transistors in a common-source configuration. The
output voltage range is limited by the drain-to-source resistance
of these transistors. As the amplifier is required to source or sink
more output current, the voltage drop across these transistors
increases due to their on resistance (rds). Simply put, the output
voltage does not swing as close to the rail under heavy output
current conditions as it does with light output current. This is a
characteristic of all rail-to-rail output amplifiers. Figure 12 and
Figure 13 show how close the output voltage can get to the rails
with a given output current. The output of the AD857x is short-
circuit protected to approximately 50 mA of current.
V
OA [t] = AAVOSA [t] − BAVOA [t]
(1)
this also can be expressed as
AAVOSA
[t]
VOA [t] =
(2)
1 + BA
This shows that the offset voltage of the nulling amplifier times
a gain factor appears at the output of the nulling amplifier and
thus on the CM1 capacitor.
The AD857x amplifiers have exceptional gain, yielding greater
than 120 dB of open-loop gain with a load of 2 kΩ. Because the
output transistors are configured in a common-source configura-
tion, the gain of the output stage, and thus the open-loop gain of
the amplifier, is dependent on the load resistance. Open-loop
gain decreases with smaller load resistances. This is another
characteristic of rail-to-rail output amplifiers.
Rev. B | Page 14 of 24
AD8571/AD8572/AD8574
V
OSB
+
long-term wear time, both of which are much slower than the
auto-zero clock frequency of the AD857x. This effectively
makes the VOS time invariant, and Equation 5 can be rewritten as
V
V
IN+
IN–
A
V
OUT
B
B
B
ΦB
V
OA
AA 1 + BA VOSA − AABAVOSA
C
M2
V
ΦB
OSA
+
VOA
[
t
]
= AAVIN
[
t
]
+
(6)
(7)
ΦA
1 + BA
A
A
V
NB
or
–B
A
ΦA
C
M1
⎛
⎜
⎞
⎟
VOSA
VOA
[
t
]
= AA VIN
[
t
]
+
V
NA
⎜
⎝
⎟
⎠
1 + BA
Figure 50. Auto-Zero Phase of the Amplifier
Here, the auto-zeroing becomes apparent. Note that the VOS
AMPLIFICATION PHASE
term is reduced by a 1 + BA factor. This shows how the nulling
amplifier has greatly reduced its own offset voltage error even
before correcting the primary amplifier. Thus, the primary
amplifier output voltage is the voltage at the output of the
AD857x amplifier. It is equal to
When the φB switches close and the φA switches open for the
amplification phase, this offset voltage remains on CM1 and
essentially corrects any error from the nulling amplifier. The
voltage across CM1 is designated as VNA. The potential difference
between the two inputs to the primary amplifier is designated as
VIN, or VIN = (VIN+ − VIN–). The output of the nulling amplifier
can then be expressed as
VOUT
[t
]
= AB
VIN
[t
]
+ VOSB
+ BBVNB
(8)
In the amplification phase, VOA = VNB, so this can be rewritten as
VOA
[t
]
= AA (VIN
[t
]
− VOSA
[t
]
− BAVNA
[
t
]
(3)
⎡
⎤
⎥
⎦
⎛
⎞
⎟
⎟
⎠
VOSA
V
OSB
⎜
VOUT
[t
]
= ABVIN
[t
]
+ ABVOSB + BB ⎢AA VIN [t] +
+
⎜
⎢
1 + BA
V
V
⎥
IN+
IN–
⎝
⎣
A
V
OUT
B
(9)
B
B
ΦB
V
OA
C
M2
combining terms yields
VOUT = VIN AB + AA BB
V
ΦB
ΦA
ΦA
OSA
+
AA BBVOSA
A
A
V
NB
[t
]
[t
]
(
)
+
+ ABVOSB
1 + BA
–B
A
C
M1
(10)
V
NA
The AD857x architecture is optimized in such a way that
Figure 51. Output Phase of the Amplifier
AA = AB and BA = BB and BA >> 1. In addition, the gain product
to AABB is much greater than AB. Thus, Equation 10 can be
simplified to
Because φA is now open and there is no place for CM1 to
discharge, the voltage (VNA) at the present time (t) is equal to
the voltage at the output of the nulling amp (VOA) at the time
when φA was closed. If the period of the autocorrection
switching frequency is designated as TS, then the amplifier
switches between phases every 0.5 × TS. Therefore, in the
amplification phase
VOUT
[t
]
= VIN
[t
]AA BA + AA (VOSA + VOSB
)
(11)
Most obvious is the gain product of both the primary and
nulling amplifiers. This AABA term is what gives the AD857x its
extremely high open-loop gain. To understand how VOSA and
VOSB relate to the overall effective input offset voltage of the
⎡
⎣
1
2
⎤
complete amplifier, set up the generic amplifier equation of
VNA
[t
]
= VNA t − TS
(4)
(5)
⎢
⎥
⎦
VOUT = k × (VIN + VOS,EFF
)
(12)
and substituting Equation 4 and Equation 2 into Equation 3
yields
where k is the open-loop gain of an amplifier and VOS, EFF is its
effective offset voltage. Putting Equation 12 into the form of
Equation 11 gives
1
⎡
⎣
⎤
AABAVOSA t − TS
⎢
⎥
⎦
2
VOUT
[t
]
= VIN
[t
]AA BA + VOS,EFF AA BA
(13)
VOA [t] = AAVIN [t] + AAVOSA [t] −
1 + BA
Therefore
For the sake of simplification, it can be assumed that the
VOSA + VOSB
autocorrection frequency is much faster than any potential
change in VOSA or VOSB. This is a good assumption since changes
in offset voltage are a function of temperature variation or
VOS,EFF
≈
(14)
BA
Rev. B | Page 15 of 24
AD8571/AD8572/AD8574
V+
Thus, the offset voltages of both the primary and nulling
amplifiers are reduced by the Gain Factor BA. This takes a typical
input offset voltage from several millivolts down to an effective
input offset voltage of submicrovolts. This autocorrection
scheme makes the AD857x family of amplifiers extremely
precise.
R1
R2
AD8572
R2
R1
V
IN1
V
IN2
GUARD
RING
GUARD
RING
V
REF
V
REF
V–
HIGH GAIN, CMRR, PSRR
Figure 53. Top View of AD8572 SOIC Layout with Guard Rings
Common-mode and power supply rejection are indications of
the amount of offset voltage an amplifier has as a result of a
change in its input common-mode or power supply voltages. As
shown in the Amplification Phase section, the autocorrection
architecture of the AD857x allows it to effectively minimize
offset voltages. The technique also corrects for offset errors
caused by common-mode voltage swings and power supply
variations. This results in superb CMRR and PSRR figures in
excess of 130 dB. Because the autocorrection occurs continu-
ously, these figures can be maintained across the entire
temperature range of the device, from −40°C to +125°C.
Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the temperature of the junction. The most
common metallic junctions on a circuit board are solder-to-
board trace and solder-to-component lead. Figure 54 shows a
cross-section view of the thermal voltage error sources. When
the temperature of the PC board at one end of the component
(TA1) differs from the temperature at the other end (TA2), the
Seebeck voltages are not equal, resulting in a thermal voltage error.
MAXIMIZING PERFORMANCE THROUGH
PROPER LAYOUT
This thermocouple error can be reduced by using dummy
components to match the thermoelectric error source. Placing
the dummy component as close as possible to its partner ensures
both Seebeck voltages are equal, thus canceling the thermocouple
error. Maintaining a constant ambient temperature on the
circuit board further reduces this error. The use of a ground
plane helps distribute heat throughout the board and also
reduces EMI noise pickup.
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD857x, care
should be taken in the circuit board layout. The PC board
surface must remain clean and free of moisture to avoid leakage
currents between adjacent traces. Surface coating of the circuit
board reduces surface moisture and provides a humidity barrier,
reducing parasitic resistance on the board. The use of guard rings
around the amplifier inputs further reduces leakage currents.
Figure 52 shows how the guard ring should be configured and
Figure 53 shows the top view of how a surface mount layout can
be arranged. The guard ring does not need to be a specific width,
but it should form a continuous loop around both inputs. By
setting the guard ring voltage equal to the voltage at the nonin-
verting input, parasitic capacitance is minimized as well. For
further reduction of leakage currents, components can be
mounted to the PC board using Teflon® standoff insulators.
COMPONENT
LEAD
SOLDER
V
V
SC1
SC2
+
SURFACE MOUNT
COMPONENT
+
–
–
V
V
TS2
TS1
–
+
+
–
PC BOARD
T
T
A2
A1
COPPER
TRACE
IF T ≠ T , THEN
A1 A2
V
V
≠ V
V
TS1 + SC1
TS2 + SC2
Figure 54. Mismatch in Seebeck Voltages Causes
a Thermoelectric Voltage Error
V
V
OUT
OUT
V
IN
V
R
F
IN
AD8572
AD8572
R1
V
OUT
V
IN
V
IN
V
AD8571/AD8572/
AD8574
OUT
R
= R1
S
AD8572
A
= 1 + (R /R1)
F
V
Figure 55. Using Dummy Components to Cancel
Thermoelectric Voltage Errors
Figure 52. Guard Ring Layout and Connections to Reduce
PC Board Leakage Currents
Rev. B | Page 16 of 24
AD8571/AD8572/AD8574
0
–20
1/f NOISE CHARACTERISTICS
V
A
= 5V
S
V
= 60dB
Another advantage of auto-zero amplifiers is their ability to
cancel flicker noise. Flicker noise, also known as 1/f noise, is
noise inherent in the physics of semiconductor devices and
increases 3 dB for every octave decrease in frequency. The 1/f
corner frequency of an amplifier is the frequency at which the
flicker noise is equal to the broadband noise of the amplifier. At
lower frequencies, flicker noise dominates, causing higher
degrees of error for sub-Hertz frequencies or dc precision
applications.
–40
–60
–80
–100
–120
Because the AD857x amplifiers are self-correcting op amps,
they do not have increasing flicker noise at lower frequencies. In
essence, low frequency noise is treated as a slowly varying offset
error and is greatly reduced as a result of autocorrection. The
correction becomes more effective as the noise frequency
approaches dc, offsetting the tendency of the noise to increase
exponentially as frequency decreases. This allows the AD857x
to have lower noise near dc than standard low noise amplifiers
that are susceptible to 1/f noise.
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (kHz)
Figure 57. Spectral Analysis of AD857x Output with 60 dB Gain
Figure 58 shows the spectral output of an AD8572 configured in
a high gain (60 dB) with a 1 mV input signal applied. Note the
absence of any IMD products in the spectrum. The signal-to-
noise (SNR) ratio of the output signal is better than 60 dB,
or 0.1%.
0
RANDOM AUTO-ZERO CORRECTION ELIMINATES
INTERMODULATION DISTORTION
V
A
= 5V
S
V
= 60dB
–20
–40
The AD857x can be used as a conventional op amp for gains up
to 1 MHz. The auto-zero correction frequency of the device
continuously varies, based on a pseudorandom generator with a
uniform distribution from 2 kHz to 4 kHz. The randomization
of the autocorrection clock creates a continuous randomization
of intermodulation distortion (IMD) products that show up as
simple broadband noise at the output of the amplifier. This
noise naturally combines with the amplifier voltage noise in a
root-squared-sum fashion, resulting in an output free of IMD.
Figure 56 shows the spectral output of an AD8572 with the
amplifier configured for unity gain and the input grounded.
Figure 57 shows the spectral output with the amplifier
configured for a gain of 60 dB.
–60
–80
–100
–120
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (kHz)
Figure 58. Spectral Analysis of AD857x in High Gain with an Input Signal
0
V
= 5V
= 0dB
–20
–40
S
V
A
–60
–80
–100
–120
–140
–160
1
2
3
4
5
6
7
8
9
10
FREQUENCY (kHz)
Figure 56. Spectral Analysis of AD857x Output in Unity Gain Configuration
Rev. B | Page 17 of 24
AD8571/AD8572/AD8574
BROADBAND AND EXTERNAL RESISTOR NOISE CONSIDERATIONS
The total broadband noise output from any amplifier is
primarily a function of three types of noise: input voltage noise
from the amplifier, input current noise from the amplifier, and
Johnson noise from the external resistors used around the
amplifier. Input voltage noise, or en, is strictly a function of the
amplifier used. The Johnson noise from a resistor is a function
of the resistance and the temperature. Input current noise, or in,
creates an equivalent voltage noise proportional to the resistors
used around the amplifier. These noise sources are not correlated
with each other and their combined noise sums in a root-
squared-sum fashion. The full equation is given as
amplifier in a high gain configuration with an input signal that
forces the output voltage to the supply rail. The input voltage is
then stepped down to the linear region of the amplifier, usually
to halfway between the supplies. The time from the input signal
step-down to the output settling to within 100 ꢀV of its final
value is the overdrive recovery time. Many competitors’ auto-
correction amplifiers require a number of auto-zero clock cycles
to recover from output overdrive and some can take several
milliseconds for the output to settle properly.
INPUT OVERVOLTAGE PROTECTION
Although the AD857x is a rail-to-rail input amplifier, care
should be taken to ensure that the potential difference between
the inputs does not exceed 5 V. Under normal operating condi-
tions, the amplifier corrects its output to ensure the two inputs
are at the same voltage. However, if the device is configured as a
comparator, or is under some unusual operating condition, the
input voltages may be forced to different potentials. This could
cause excessive current to flow through internal diodes in the
AD857x used to protect the input stage against overvoltage.
en,TOTAL = [en + 4kTrs + (inrs )2 ]1/2
(15)
2
where:
en = input voltage noise of the amplifier.
in = input current noise of the amplifier.
rs = source resistance connected to the noninverting terminal.
k = Boltzmann’s constant (1.38 × 10−23 J/K).
T = ambient temperature in Kelvin (K = 273.15 + °C).
The input voltage noise density, en, of the AD857x is
51 nV/√Hz, and the input noise, in, is 2 fA/√Hz. The en, TOTAL is
dominated by input voltage noise provided the source resistance
is less than 172 kΩ. With source resistance greater than 172 kΩ,
the overall noise of the system is dominated by the Johnson
noise of the resistor itself.
If either input exceeds either supply rail by more than 0.3 V,
large amounts of current begin to flow through the ESD
protection diodes in the amplifier. These diodes are connected
between the inputs and each supply rail to protect the input
transistors against an electrostatic discharge event and are
normally reverse-biased. However, if the input voltage exceeds
the supply voltage, these ESD diodes become forward-biased.
Without current-limiting, excessive amounts of current can
flow through these diodes causing permanent damage to the
device. If inputs are subject to overvoltage, appropriate series
resistors should be inserted to limit the diode current to less
than 2 mA.
Because the input current noise of the AD857x is very small, in
does not become a dominant term unless rS is greater than
4 GΩ, which is an impractical value of source resistance.
The total noise, en, TOTAL, is expressed in volts-per-square-root
Hertz, and the equivalent rms noise over a certain bandwidth
can be found as
OUTPUT PHASE REVERSAL
en = en,TOTAL
×
BW
(16)
Output phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. As common-mode
voltage is moved outside of the common-mode range, the
outputs of these amplifiers suddenly jump in the opposite
direction to the supply rail. This is the result of the differential
input pair shutting down, causing a radical shifting of internal
voltages that results in the erratic output behavior.
where BW is the bandwidth of interest in Hertz.
OUTPUT OVERDRIVE RECOVERY
The AD857x amplifiers have an excellent overdrive recovery of
only 200 ꢀs from either supply rail. This characteristic is par-
ticularly difficult for autocorrection amplifiers, because the
nulling amplifier requires a substantial amount of time to error
correct the main amplifier back to a valid output. Figure 29 and
Figure 30 show the positive and negative overdrive recovery
time for the AD857x.
The AD857x amplifier has been carefully designed to prevent
any output phase reversal, provided both inputs are maintained
within the supply voltages. If one or both inputs could exceed
either supply voltage, a resistor should be placed in series with
the input to limit the current to less than 2 mA to ensure the
output does not reverse its phase.
The output overdrive recovery for an autocorrection amplifier is
defined as the time it takes for the output to correct to its final
voltage from an overload state. It is measured by placing the
Rev. B | Page 18 of 24
AD8571/AD8572/AD8574
CAPACITIVE LOAD DRIVE
Table 5. Snubber Network Values for Driving Capacitive Loads
The AD857x has excellent capacitive load driving capabilities
and can safely drive up to 10 nF from a single 5 V supply.
Although the device is stable, capacitive loading limits the
bandwidth of the amplifier. Capacitive loads also increase the
amount of overshoot and ringing at the output. An RC snubber
network, shown in Figure 59, can be used to compensate the
amplifier against capacitive load ringing and overshoot.
CLOAD
Rx
Cx
1 nF
4.7 nF
10 nF
200 Ω
60 Ω
20 Ω
1 nF
0.47 μF
10 μF
POWER-UP BEHAVIOR
On power-up, the AD857x settles to a valid output within
5 ꢀs. Figure 61 shows an oscilloscope photo of the output of the
amplifier along with the power supply voltage, and Figure 62
shows the test circuit. With the amplifier configured for unity
gain, the device takes approximately 5 ꢀs to settle to its final
output voltage, hundreds of microseconds faster than many
other autocorrection amplifiers.
5V
AD8571/
AD8572/
–
AD8574
V
OUT
Rx
60Ω
V
IN
+
C
L
200mV p-p
4.7nF
Cx
0.47µF
Figure 59. Snubber Network Configuration for Driving Capacitive Loads
Although the snubber does not recover the loss of amplifier
bandwidth from the load capacitance, it does allow the amplifier
to drive larger values of capacitance while maintaining a
minimum of overshoot and ringing. Figure 60 shows the output
of an AD857x driving a 1 nF capacitor with and without a
snubber network.
V
OUT
0V
V+
0V
10μs
WITH
SNUBBER
5µs
1V
BOTTOM TRACE = 2V/DIV
TOP TRACE = 1V/DIV
Figure 61. AD857x Output Behavior on Power-Up
WITHOUT
SNUBBER
V
= 0V TO 5V
SY
100kΩ
100kΩ
V
= 5V
LOAD
S
100mV
C
= 4.7nF
V
OUT
AD8571/
AD8572/
AD8574
Figure 60. Overshoot and Ringing are Substantially
Reduced Using a Snubber Network
Figure 62. AD857x Test Circuit for Turn-On Time
The optimum value for the resistor and capacitor is a function
of the load capacitance and is best determined empirically since
actual CLOAD includes stray capacitances and can differ substan-
tially from the nominal capacitive load. Table 5 shows some
snubber network values that can be used as starting points.
Rev. B | Page 19 of 24
AD8571/AD8572/AD8574
APPLICATIONS
In an ideal difference amplifier, the ratio of the resistors is set
exactly equal to
5 V PRECISION STRAIN GAGE CIRCUIT
The extremely low offset voltage of the AD8572 makes it an ideal
amplifier for any application requiring accuracy with high gains,
such as a weigh scale or strain gage. Figure 63 shows a configura-
tion for a single supply, precision strain gage measurement system.
R2 R4
R1 R3
AV
=
=
(19)
setting the output voltage of the system to
A REF192 provides a 2.5 V precision reference voltage for A2.
The A2 amplifier boosts this voltage to provide a 4.0 V reference
for the top of the strain gage resistor bridge. Q1 provides the
current drive for the 350 Ω bridge network. A1 is used to amplify
the output of the bridge with the full-scale output voltage equal to
VOUT = AV (V1 − V 2)
(20)
Due to finite component tolerance, the ratio between the four
resistors is not exactly equal, and any mismatch results in a
reduction of common-mode rejection from the system. Referring
to Figure 64, the exact common-mode rejection ratio can be
expressed as
2 × R1 + R2
(17)
RB
R1R4 + 2R2R4 + R2R3
CMRR =
(21)
where RB is the resistance of the load cell. Using the values given
in Figure 63, the output voltage linearly varies from 0 V with no
strain to 4 V under full strain.
2R1R4 − 2R2R3
In the three-op amp instrumentation amplifier configuration
shown in Figure 65, the output difference amplifier is set to
unity gain with all four resistors equal in value. If the tolerance
of the resistors used in the circuit is given as δ, the worst-case
CMRR of the instrumentation amplifier is
2
5V
3
6
2.5V
REF192
4
1kΩ
Q1
2N2222
A2
OR
AD8572-B
EQUIVALENT
12kΩ
20kΩ
1
4.0V
CMRRMIN
=
(22)
2δ
R2
R1
100Ω
17.4kΩ
40mV
FULL-SCALE
V
A1
OUT
AD8574-A
350Ω
LOAD
CELL
V2
R
0V TO 4V
AD8572-A
R
R
R
R
R4
100Ω
R3
17.4kΩ
V
NOTE:
R
OUT
G
USE 0.1% TOLERANCE RESISTORS.
AD8574-C
R
Figure 63. 5 V Precision Strain Gage Amplifier
R
TRIM
V1
3 V INSTRUMENTATION AMPLIFIER
AD8574-B
The high common-mode rejection, high open-loop gain, and
operation down to 3 V of supply voltage make the AD857x an
excellent choice of op amp for discrete single-supply instrumen-
tation amplifiers. The common-mode rejection ratio of the
AD857x is greater than 120 dB, but the CMRR of the system is
also a function of the external resistor tolerances. The gain of
the difference amplifier shown in Figure 64 is given as
2R
(V1 – V2)
V
= 1 +
OUT
R
G
Figure 65. Discrete Instrumentation Amplifier Configuration
Thus, using 1% tolerance resistors results in a worst-case system
CMRR of 0.02, or 34 dB. Therefore, either high precision
resistors or an additional trimming resistor, as shown in Figure 65,
should be used to achieve high common-mode rejection. The
value of this trimming resistor should be equal to the value of R
multiplied by its tolerance. For example, using 10 kΩ resistors
with 1% tolerance would require a series trimming resistor
equal to 100 Ω.
⎛
⎜
R4 ⎞⎛
R1 ⎞
⎛ R2 ⎞
R1
VOUT = V1
1 +
− V 2
(18)
⎟⎜
⎟
⎜
⎝
⎟
⎠
R3 + R4
R2
⎝
⎠⎝
⎠
R2
R1
R3
V2
V1
HIGH ACCURACY THERMOCOUPLE AMPLIFIER
V
OUT
AD8571/
AD8572/
AD8574
Figure 66 shows a K-type thermocouple amplifier configuration
with cold junction compensation. Even from a 5 V supply, the
AD8571 can provide enough accuracy to achieve a resolution of
better than 0.02°C from 0°C to 500°C. D1 is used as a tempera-
ture measuring device to correct the cold-junction error from
R4
R4
R2
R2
IF
=
, THEN V
=
(V1 – V2)
OUT
R3
R1
R1
Figure 64. Using the AD857x as a Difference Amplifier
Rev. B | Page 20 of 24
AD8571/AD8572/AD8574
the thermocouple and should be placed as close as possible to
the two terminating junctions. With the thermocouple measuring
tip immersed in a 0°C ice bath, R6 should be adjusted until the
output is at 0 V.
Figure 68 shows the low-side monitor equivalent. In this circuit,
the input common-mode voltage to the AD8572 is at or near
ground. Again, a 0.1 Ω resistor provides a voltage drop propor-
tional to the return current. The output voltage is given as
R2
R1
⎛
⎜
⎞
⎟
Using the values shown in Figure 66, the output voltage tracks
temperature at 10 mV/°C. For a wider range of temperature
measurement, R9 can be decreased to 62 kΩ. This creates a
5 mV/°C change at the output, allowing measurements of up to
1000°C.
VOUT = V + −
× RSENSE × IL
(24)
⎝
⎠
For the component values shown in Figure 68, the output
transfer function decreases from V at –2.5 V/A.
R
0.1Ω
SENSE
I
L
REF02EZ
5V
3V
V+
2
6
12V
3V
4
0.1µF
0.1µF
R5
40.2kΩ
R9
124kΩ
R1
100Ω
3
2
8
R1
10.7kΩ
1/2
AD8572
1
5V
1N4148
D1
10µF
4
S
G
0.1µF
M1
R2
R8
Si9433
2.74kΩ
453Ω
2
3
–
+
–
8
K-TYPE
THERMOCOUPLE
40.7µV/°C
D
1
MONITOR
OUTPUT
+
R6
200Ω
R2
AD8572
4
2.49kΩ
0V TO 5V
(0°C TO 500°C)
R4
5.62kΩ
R3
53.6kΩ
Figure 67. High-Side Load Current Monitor
Figure 66. Precision K-Type Thermocouple Amplifier
with Cold-Junction Compensation
V+
PRECISION CURRENT METER
R2
2.49kΩ
Because of its low input bias current and superb offset voltage at
single-supply voltages, the AD857x is an excellent amplifier for
precision current monitoring. Its rail-to-rail input allows the
amplifier to be used as either a high-side or a low-side current
monitor. Using both amplifiers in the AD8572 provides a simple
method to monitor both current supply and return paths for
load or fault detection.
V
OUT
Q1
V+
R1
100Ω
1/2 AD8572
R
SENSE
0.1Ω
RETURN TO
GROUND
Figure 67 shows a high-side current monitor configuration.
Here, the input common-mode voltage of the amplifier is at or
near the positive supply voltage. The rail-to-rail input of the
amplifier provides a precise measurement, even with the input
common-mode voltage at the supply voltage. The CMOS input
structure does not draw any input bias current, ensuring a
minimum of measurement error.
Figure 68. Low-Side Load Current Monitor
PRECISION VOLTAGE COMPARATOR
The AD857x can be operated open-loop and used as a precision
comparator. The AD857x has less than 50 μV of offset voltage
when run in this configuration. The slight increase of offset
voltage stems from the fact that the autocorrection architecture
operates with lowest offset in a closed-loop configuration, that
is, one with negative feedback. With 50 mV of overdrive, the
device has a propagation delay of 15 μs on the rising edge and
8 μs on the falling edge.
The 0.1 Ω resistor creates a voltage drop to the noninverting
input of the AD857x. The output of the amplifier is corrected
until this voltage appears at the inverting input. This creates a
current through R1 that in turn flows through R2. The monitor
output is given by
Care should be taken to ensure the maximum differential
voltage of the device is not exceeded. For more information,
refer to the Input Overvoltage Protection section.
R
⎛
⎜
⎞
⎟
SENSE
Monitor Output = R2 ×
× I
(23)
L
R1
⎝
⎠
Using the components shown in Figure 67, the monitor output
transfer function is 2.5 V/A.
Rev. B | Page 21 of 24
AD8571/AD8572/AD8574
OUTLINE DIMENSIONS
3.20
3.00
2.80
3.10
3.00
2.90
8
5
4
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65 BSC
PIN 1
0.95
0.85
0.75
0.65 BSC
1.10 MAX
0.15
0.05
1.20
0.80
0.60
0.40
MAX
8°
0°
0.15
0.00
8°
0°
0.38
0.22
0.23
0.08
0.75
0.60
0.45
0.30
SEATING
PLANE
COPLANARITY
0.10
0.20
0.09
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AA
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 71. 8-Lead Thin Shrink Small Outline Package [TSSOP]
Figure 69. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
(RU-8)
Dimensions shown in millimeters
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
5.10
5.00
4.90
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
14
8
7
4.50
4.40
4.30
6.40
BSC
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
1
0.25 (0.0098)
0.10 (0.0040)
8°
0°
PIN 1
0.65
BSC
1.05
1.00
0.80
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
0.20
0.09
SEATING
PLANE
1.20
MAX
0.75
0.60
0.45
8°
0°
0.15
0.05
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MS-012-AA
SEATING
PLANE
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Figure 70. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters
Dimensions shown in millimeters and inches
Rev. B | Page 22 of 24
AD8571/AD8572/AD8574
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 73. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
R-8
Model
Branding
AD8571AR
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead TSSOP
8-Lead TSSOP
8-Lead TSSOP
8-Lead TSSOP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
AD8571AR-REEL
AD8571AR-REEL7
AD8571ARZ1
R-8
R-8
R-8
R-8
AD8571ARZ-REEL1
AD8571ARZ-REEL71
AD8571ARM-R2
AD8571ARM-REEL
AD8571ARMZ-R21
AD8571ARMZ-REEL1
AD8572AR
AD8572AR-REEL
AD8572AR-REEL7
AD8572ARZ1
AD8572ARZ-REEL1
AD8572ARZ-REEL71
AD8572ARU
R-8
RM-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
AJA
AJA
AJA#
AJA #
R-8
RU-8
RU-8
RU-8
RU-8
R-14
R-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
AD8572ARU-REEL
AD8572ARUZ1
AD8572ARUZ-REEL1
AD8574AR
AD8574AR-REEL
AD8574AR-REEL7
AD8574ARZ1
AD8574ARZ-REEL1
AD8574ARZ-REEL71
AD8574ARU
AD8574ARU-REEL
AD8574ARUZ1
AD8574ARUZ-REEL1
1 Z = Pb-free part, # denote lead-free product may be top or bottom marked.
Rev. B | Page 23 of 24
AD8571/AD8572/AD8574
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01104-0-9/06(B)
Rev. B | Page 24 of 24
相关型号：
AD8574ARUZ
QUAD OP-AMP, 10 uV OFFSET-MAX, 1.5 MHz BAND WIDTH, PDSO14, ROHS COMPLIANT, MO-153AB-1, TSSOP-14
ROCHESTER
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