AD9229BCPZ-65 [ADI]
IC 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48, LEAD FREE, MO-220-VKKD-2, LFCSP-48, Analog to Digital Converter;
| 型号： | AD9229BCPZ-65 |
| 厂家： | 
ADI |
| 描述： | IC 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48, LEAD FREE, MO-220-VKKD-2, LFCSP-48, Analog to Digital Converter 转换器 |
| 文件： | 总15页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad 12-Bit, 50/65 MSPS
Serial LVDS 3V A/D Converter
AD9229
Preliminary Technical Data
FEATURES
FUNCTIONAL BLOCK DIAGRAM
· Four ADCs in one package
· Serial LVDS digital output data rates (ANSI-644)
· Data clock output provided
· On Chip Reference and SHA
· SNR = 70 dB at Fin up to Nyquist
· Excellent Linearity:
PDWN
AVDD
DRVDD
DRGND
AD9229
12
VIN+A
VIN-A
D1+A
D1-A
Serial
LVDS
Pipeline
ADC
SHA
SHA
SHA
SHA
12
VIN+B
VIN-B
-
-
DNL = ±0.3 LSB (Typical)
INL = ±0.6 LSB (Typical)
Serial
LVDS
D1+B
D1-B
Pipeline
ADC
12
12
· 500 MHz full power analog bandwidth
VIN+C
VIN-C
D1+C
D1-C
Serial
LVDS
Pipeline
ADC
· Per Channel Core Power Dissipation = 270mW at 65MSPS /
200mW at 50MSPS
VIN+D
VIN-D
Serial
LVDS
D1+D
D1-D
· 1 Vpp – 2 Vpp input voltage range
· +3.0 V supply operation
· Power down mode
Pipeline
ADC
VREF
SENSE
FCO+
FCO-
+
-
0.5 V
APPLICATIONS
REFT
REFB
Ref
Select
Data Rate
Multiplier
DCO+
DCO-
· Digital beam forming systems in ultrasound
· Wireless and wired broadband communications
· Communications test equipment
CLK
AGND
LVDSBIAS
· Radar and satellite imaging sub-systems
Figure 1. Functional Block Diagram
signal a new output byte. Power down is supported and consumes
less than 3mW when enabled.
PRODUCT DESCRIPTION
The AD9229 is a quad 12-bit monolithic sampling analog–to–
digital converter with an on–chip track–and–hold circuit and is
designed for low cost, low power, small size and ease of use. The
product operates up to a 65 MSPS conversion rate and is optimized
for outstanding dynamic performance where a small package size is
critical.
Fabricated on an advanced CMOS process, the AD9229 is available
in a 48-LFCSP package specified over the industrial temperature
range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Four analog-to-digital converters are contained in one small,
space saving package.
2. A Data Clock Output (DCO) is provided which operates up to
390 MHz.
3. The outputs of each ADC are serialized with a maximum data
output rate of 780 Mbps (12-bits x 65 MSPS).
4. The AD9229 operates from a single +3.0 V analog power
supply.
The ADC requires a single+3.0 V power supply and a TTL/CMOS
compatible sample rate clock for full performance operation. No
external reference or driver components are required for many
applications. A separate output power supply pin supports LVDS
compatible serial digital output levels.
The ADC automatically multiplies up the sample rate clock for the
appropriate LVDS serial data rate. An MSB trigger is provided to
Rev. PrF 10/06/2003
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its
use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices. Trademarks and registered trademarks are the property
of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD9229
Preliminary Technical Data
TABLE OF CONTENTS
AD9229—Specifications ........................................................................ 3
Analog Inputs ....................................................................................11
Voltage Reference..............................................................................11
Digital Outputs..................................................................................11
Timing ................................................................................................11
PLL ......................................................................................................11
Pin Function Descriptions ...................................................................12
Pin Configurations................................................................................13
Timing Diagram ....................................................................................14
Ordering Guide .................................................................................15
DIGITAL SPECIFICATIONS ........................................................... 4
AC SPECIFICATIONS....................................................................... 4
SWITCHING SPECIFICATIONS.................................................... 5
EXPLANATION OF TEST LEVELS................................................ 5
Absolute Maximum Ratings .................................................................. 6
EQuivalent circuits.................................................................................. 7
TYPICAL PERFORMANCE CHARACTERISTICS ......................... 8
Theory of Operation .............................................................................11
REVISION HISTORY
Revision PrA: Initial Version
Revision PrB: Added Definition and Theory of Operation sections, updated Pin Configurations
Revision PrC: Deleted demux outputs
Revision PrD: Added Pin Info, Package Info
Revision PrE: Ch. 3.3V to 3.0V for supply, Updated Sinad spec typo, Added analog typical Cin, Overange Recovery Time, Latency
Revision PrF: Added 50MSPS Grade, Removed Clk-, Updated Power, SNR,LVDS Rset, Tpd Estimates, Added Equiv Ckts, Added FFT, VREF
figure, Corrected FCO, DCO polarity timing
Rev. PrF | Page 2 of 15
Oct. 6, 2003
Preliminary Technical Data
AD9229
1
AD9229—SPECIFICATIONS
AVDD = 3.0V, DRVDD = 3.0V; INTERNAL REFERENCE; DIFFERENTIAL ANALOG INPUTS,MAXIMUM SAMPLE RATE,TMIN TO
TMAX, UNLESS OTHERWISE NOTED
Unit
Temp
Test
AD9229BCP-50
AD9229BCP-65
Parameter
Level
Min
Typ
Max
Min
Typ
Max
RESOLUTION
12
12
Bits
No Missing Codes
Full
VI
Guaran
teed
Guaran
teed
Offset Error
I
I
mV
%FS
mV
% FS
LSB
LSB
LSB
LSB
25°C
25°C
25°C
25°C
25°C
Full
± 0.5
± 0.5
± 0.5
± 0.5
Gain Error
Offset Matching
Gain Matching2
Differential Nonlinearity (DNL)
I
ACCURACY
I
I
± 0.3
± 0.6
± 0.3
± 0.6
VI
I
Integral Nonlinearity (INL)
25°C
Full
VI
V
V
V
I
Offset Error
Gain Error2
Full
ppm/°C
ppm/°C
ppm/°C
V
TEMPERATURE
DRIFT
Full
Reference
Full
Internal Reference Voltage
Output Current
0.5
0.5
25°C
Full
Full
Full
V
V
V
uA
REFERENCE
Input Current
uA
Input Resistance
Differential Input Voltage Range
Common Mode Voltage
Input Capacitance
Analog Bandwidth, Full Power
AVDD
kW
1 –2
1.5
7
1 –2
1.5
7
Vpp
V
Full
Full
Full
Full
V
V
ANALOG INPUTS
pF
V
500
3.0
500
3.0
MHz
V
IV
2.7
2.7
3.6
3.6
2.7
2.7
3.6
3.6
DRVDD
Full
IV
V
3.0
940
<3
3.0
1250
<3
Power Dissipation3
Power Down Dissipation
Power Supply Rejection Ratio (PSRR)
IAVDD3
IDRVDD3
IPLLVDD3
Full
Full
25°C
Full
Full
Full
VI
VI
I
mW
mW
mV/V
mA
POWER SUPPLY
VI
VI
VI
268
28
367
30
mA
18
19
Table 1: DC Specifications
1 Specifications subject to change without notice
2 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 0.5 V external reference and a 1 V p-p differential analog input).
3 Power dissipation measured with rated encode and a dc analog input (Outputs Static, IVDD = 0.). IVCC and IVDD measured with TBD MHz analog input @ 0.5dBFS.
Rev. PrF | Page 3 of 15
Oct. 6, 2003
AD9229
Preliminary Technical Data
DIGITAL SPECIFICATIONS
AVDD = 3.0V, DRVDD = 3.0V
Parameter
Unit
Temp
Test
Level
AD9229BCP-50
AD9229BCP-65
Min
Typ
Max
Min
Typ
Max
V
Full
Full
25°C
Full
Full
Full
Full
IV
IV
IV
2.0
2.0
V
IH
V
IL
0.8
0.8
0.8
V
CLOCK INPUT
PDWN INPUT
Input Capacitance
2
2
pF
Logic ‘1’ Voltage
IV
IV
IV
IV
2.0
2.0
V
Logic ‘0’ Voltage
0.8
V
Input Capacitance
2
2
PF
mV
Differential Output Voltage
247
454
247
454
(V )
OD
DIGITAL OUTPUTS
(LVDS Mode)*
Output Offset Voltage (V )
Full
Full
IV
IV
1.125
1.375
1.125
1.375
V
OS
Output Coding
Offset Binary
Offset Binary
Table 2: Digital Specifications
* LVDS Rset resistor = 3.6K, LVDS Output Termination Resistor= 100 Ohms.
AC SPECIFICATIONS1
AVDD = 3.0 V, DRVDD = 3.0V; INTERNAL REFERENCE; DIFFERENTIAL ANALOG INPUTS,MAXIMUM SAMPLE RATE,TMIN TO
TMAX, UNLESS OTHERWISE NOTED
Parameter
Temp
Test
AD9229BCP-50
AD9229BCP-65
Unit
Level
Min
Typ
Max
Min
Typ
Max
fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
V
V
I
70.5
70.5
dB
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
SIGNAL TO NOISE
RATIO (SNR) –
Without
dB
69.7
70.3
69.5
69.7
70.3
69.5
dB
Harmonics
V
V
V
I
dB
fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
dB
SIGNAL TO NOISE
RATIO (SINAD) –
With Harmonics
dB
dB
V
V
V
I
dB
fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
Bits
Bits
Bits
Bits
dB
EFFECTIVE
NUMBER OF BITS
(ENOB)
V
V
V
I
fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
SPURIOUS FREE
DYNAMIC RANGE
(SFDR)
85
85
dB
dB
V
V
V
I
dB
fIN= 10.3 MHz
fIN= 19.6 MHz
fIN= 32.5 MHz
fIN= 51 MHz
dBc
dBc
dBc
dBc
dBc
dBc
SECOND AND
THIRD
HARMONIC
DISTORTION
-85
-85
-85
-85
V
V
V
TWO TONE
INTERMOD
DISTORTION
(IMD)
fIN1= 19 MHz, fIN2= 20 MHz
fIN1= xx MHz, fIN2= xx MHz
1 SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1 Vpp full-scale input range.
Rev. PrF | Page 4 of 15
Oct. 6, 2003
Preliminary Technical Data
AD9229
Parameter
Temp
Test
AD9229BCP-50
AD9229BCP-65
Unit
Level
Min
Typ
Max
Min
Typ
Max
CROSSTALK
Full
V
-80
-80
dB
Table 3: AC Specifications
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V; DIFFERENTIAL ENCODE INPUT
Parameter
Temp
Test
AD9229BCP-50
AD9229BCP-65
Unit
Level
Min
10
Typ
Max
50
Min
10
Typ
Max
65
Clock Rate
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
VI
IV
IV
VI
VI
VI
V
MSPS
ns
CLOCK
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
Valid Time (tV)1
ns
ns
1
Propagation Delay (tPD
)
5
5
5
5
ns
1
MSB Propagation Delay (tMSB
)
ns
OUTPUT
PARAMETERS IN
LVDS MODE
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
ns
V
ns
DCO Propagation Delay (tCPD
)
VI
IV
VI
V
5
9
5
9
ns
Data to DCO Skew (tPD – tCPD
)
ns
Pipeline Latency
cycles
ps
Aperture Delay (tA)
APERTURE
Aperture Uncertainty (Jitter)
V
<1
<1
ps rms
cycles
Out of Range
Recovery Time
IV
2
2
Table 4: Switching Specifications
EXPLANATION OF TEST LEVELS
TEST LEVEL
I
100% production tested.
II
100% production tested at +25°C and guaranteed by design and characterization at specified temperatures.
Sample tested only.
III
IV
V
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
VI
100% production tested at +25°C and guaranteed by design and characterization for industrial temperature range.
1 tV and tPD are measured from the transition points of the CLK input to the 50%/50% levels of the digital outputs swing. The digital output load during test is
not to exceed an ac load of 5 pF or a dc current of ±40 µA. Rise and fall times measured from 20% to 80%.
Rev. PrF | Page 5 of 15
Oct. 6, 2003
AD9229
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
AVDD Voltage
3.9V
3.9V
DRVDD Voltage
Analog Input Voltage
Electrical
Analog Input Current
Digital Input Voltage
Digital Output Current
VREF Input Voltage
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Maximum Case Temperature
Storage Temperature Range (Ambient)
-40°C to +85°C
150°C
Environmental
Table 5: Absolute Maximum Ratings
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. PrF | Page 6 of 15
Oct. 6, 2003
Preliminary Technical Data
EQUIVALENT CIRCUITS
AD9229
DRVDD
AVDD
3.5MA
ANALOG IN
V-
V+
DATAOUT-,
DCO-,FCO-
DATAOUT+,
DCO+,FCO+
V+
V-
Figure 2 Analog Inputs
3.5MA
Figure 4 LVDS Outputs
AVDD
AVDD
AVDD
AVDD
PDWN
CLK
Figure 5 PDWN Input
Figure 3 Clock Input
Rev. PrF | Page 7 of 15
Oct. 6, 2003
TYPICAL PERFORMANCE CHARACTERISTICS
0
-20
-40
-60
SNR = 68.7 dB
SINAD = 68.5 dB
SFDR = 88.6 dB
-80
-100
-120
0
5
10
15
20
25
30
MHz
Measured FFT Performance 32MHz Ain at 65MSPS
Preliminary Technical Data
AD9229
Definitions
ANALOG BANDWIDTH
ENCODE PULSE WIDTH/DUTY CYCLE
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in logic“1” state to achieve rated
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing tENCH in text. At a give clock rate, these specs define an
acceptable Encode duty cycle.
APERTURE DELAY
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input is
sampled.
FULL SCALE INPUT POWER
Expressed in dBm. Computed using the following equation:
APERTURE UNCERTAINTY (JITTER)
2
æ
ö
÷
V
Fullscalerms
The sample-to-sample variation in aperture delay.
ç
ç
ç
ç
÷
÷
÷
ZInput
PowerFullscale =10log
CROSSTALK
.001
Coupling onto one channel being driven by a low level (-40 dBFS)
signal when the adjacent interfering channel is driven by a full-
scale signal.
ç
÷
è
ø
GAIN ERROR
DIFFERENTIAL ANALOG INPUT RESISTANCE,
DIFFERENTIAL ANALOG INPUT CAPACITANCE, AND
DIFFERENTIAL ANALOG INPUT IMPEDANCE
Gain error is the difference between the measured and ideal full
scale input voltage range of the worst ADC.
The real and complex impedances measured at each analog input
port. The resistance is measured statically and the capacitance and
differential input impedances are measured with a network
analyzer.
GAIN MATCHING
Expressed in %FSR. Computed using the following equation:
FSR max- FSR min
GainMatching =
*100%
DIFFERENTIAL ANALOG INPUT VOLTAGE RANGE
FSR max+ FSR min
æ
ö
÷
ç
The peak to peak differential voltage that must be applied to the
converter to generate a full scale response. Peak differential voltage
is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees out
of phase. Peak to peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement again.
Then the difference is computed between both peak measurements.
2
è
ø
where FSRmax is the most positive gain error of the ADCs and
FSRmin is the most negative gain error of the ADCs.
HARMONIC DISTORTION, SECOND
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
DIFFERENTIAL NONLINEARITY
HARMONIC DISTORTION, THIRD
The deviation of any code width from an ideal 1 LSB step.
The ratio of the rms signal amplitude to the rms value of the third
harmonic component, reported in dBc.
EFFECTIVE NUMBER OF BITS
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
INTEGRAL NONLINEARITY
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a“best straight line”
determined by a least square curve fit.
SNRMEASURED - 1.76dB
ENOB =
6.02
Rev. PrF | Page 9 of 15
Oct. 6, 2003
AD9229
Preliminary Technical Data
the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
MINIMUM CONVERSION RATE
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
SIGNAL-TO-NOISE RATIO (WITHOUT HARMONICS)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.
MAXIMUM CONVERSION RATE
The encode rate at which parametric testing is performed.
OFFSET ERROR
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
Offset error is the difference between the measured and ideal
voltage at the analog input that produces the midscale code at the
outputs. Offset error is given for the worst ADC.
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component may
or may not be a harmonic. It also may be reported in dBc (i.e.,
degrades as signal level is lowered) or dBFS (i.e., always related back
to converter full scale).
OFFSET MATCHING
Expressed in mV. Computed using the following equation:
TWO-TONE INTERMODULATION DISTORTION
REJECTION
OffsetMatching = OFF max- OFF min
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
where OFFmax is the most positive offset error and OFFmin is the
most negative offset error.
TWO-TONE SFDR
OUTPUT PROPAGATION DELAY
The ratio of the rms value of either input tone to the rms value of
the peak spurious component. The peak spurious component may
or may not be an IMD product. It also may be reported in dBc (i.e.,
degrades as signal level is lowered) or in dBFS (i.e., always relates
back to converter full scale).
The delay between a differential crossing of CLK+ and CLK- and
the time when all output data bits are within valid logic levels.
NOISE (FOR ANY RANGE WITHIN THE ADC)
WORST OTHER SPUR
FSdBm - SNRdBc - SignaldBFS
æ
ö
÷
ø
Vnoise = Z *.001*10èç
10
The ratio of the rms signal amplitude to the rms value of the worst
spurious component (excluding the second and third harmonic)
reported in dBc.
Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level and Signal is the signal level within the ADC reported in
dB below full scale. This value includes both thermal and
quantization noise.
TRANSIENT RESPONSE TIME
Transient response time is defined as the time it takes for the ADC
to reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.
POWER SUPPLY REJECTION RATIO
The ratio of a change in input offset voltage to a change in power
supply voltage.
OUT-OF-RANGE RECOVERY TIME
Out of range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above positive
full scale to 10% above negative full scale, or from 10% below
negative full scale to 10% below positive full scale.
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale) to
Rev. PrF | Page 10 of 15
Oct. 6, 2003
Preliminary Technical Data
AD9229
THEORY OF OPERATION
Analog Inputs
recommended to keep the trace length no longer than 1–2 inches
and to keep differential output trace lengths as equal as possible.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors will be reduced by the
common-mode rejection of the A/D.
The format of the output data is offset binary.
Timing
Data from each A/D is serialized and provided on a separate
channel.
Voltage Reference
The AD9229 has a stable and accurate reference voltage on chip,
which sets the full-scale voltage at the analog input channels.
Internal reference mode is established by grounding the SENSE pin.
(Recommended decoupling capacitors shown below) The internal
reference can be bypassed by setting SENSE to AVDD and driving
VREF with an external 1V reference.
Two output clocks are provided to assist in capturing data from the
AD9229. The data clock out (DCO) is used to clock the output
data and is equal to 6 times the sample clock frequency. ( 390MHz
for 65MHz input clock) Data is clocked out of the AD9229 on the
rising and falling edges of DCO. The FCO clock signals the start of
a new serial word, the rising edge of FCO occurs at the start of an
MSB.
VINA
VINB
REFT
PLL
0.1uF
10 uF
The AD9229 contains an internal PLL that is used to generate
internal clocking signals, if the PLL is unlocked, the data outputs
are static.
ADC
CORE
0.1
uF
REFB
0.1uF
VREF
10 uF
0.5V
0.1u F
SELECT
LOGIC
SENSE
AD9229
Internal Reference Mode Connection
Digital Outputs
The AD9229’s differential outputs conform to the ANSI-644 LVDS
standard. To set the LVDS bias current, place a resistor (RSET is
nominally equal to 3.6 kW) to ground at the LVDSBIAS pin. The
RSET resistor current (~ 1.2/RSET) is ratioed on-chip setting the
output current at each output equal to a nominal 3.5 mA. A 100 W
differential termination resistor placed at the LVDS receiver inputs
results in a nominal 350 mV swing at the receiver.
The AD9229’s LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments. Single
point-to-point net topologies are recommended with a 100 W
termination resistor as close to the receiver as possible. It is
Rev. PrF | Page 11 of 15
Oct. 6, 2003
AD9229
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
3.0 V Analog Supply
Pin No.
Name
Description
8,16,21,
29
AVDD
44
D+A
ADC A True Digital Output
9,12,15,
AGND
Analog Ground
43
D-A
ADC A Complement Digital Output
22,25,28,
31
2,35
DRVDD
42
D+B
ADC B True Digital Output
3.0 V Digital Output Supply
Digital Ground
1,36
32
DRGND
PLLVDD
41
40
D-B
ADC B Complement Digital Output
ADC C True Digital Output
D+C
PLL 3.0V Supply
33
30
18
17
20
19
10
11
14
13
23
24
27
26
PLLGND
CLK
PLL Ground
39
38
D-C
D+D
ADC C Complement Digital Output
ADC D True Digital Output
Input Clock
VREF
Voltage Reference Input/Output
Reference Mode Selection
Differential Reference (Positive)
Differential Reference (Negative)
ADC A Analog Input – True
ADC A Analog Input – Complement
ADC B Analog Input – True
ADC B Analog Input – Complement
ADC C Analog Input – True
ADC C Analog Input – Complement
ADC D Analog Input – True
ADC D Analog Input – Complement
37
D1-D
ADC D Complement Digital Output
Data Clock Output – True
SENSE
REFT
48
DCO+
DCO-
47
Data Clock Output – Complement
Frame Clock Indicator – True Output
Frame Clock Indicator – Complement Output
LVDS Output Current Set Resistor Pin
Power Down Selection ( Logic ‘1’ = Power Down )
Do Not Connect
REFB
46
FCO+
FCO-
VIN+A
VIN-A
VIN+B
VIN-B
VIN+C
VIN-C
VIN+D
VIN-D
45
34
LVDSBIAS
PDWN
DNC
7
3,4,5,6
Table 6: Pin Function Descriptions
Rev. PrF | Page 12 of 15
Oct. 6, 2003
Preliminary Technical Data
PIN CONFIGURATIONS
AD9229
48
1
37
36
DRGND
DRGND
DRVDD
LVDSBIAS
PLLGND
PLLVDD
AGND
DRVDD
DNC
DNC
DNC
DNC
AD9229
PDWN
AVDD
AGND
VIN+A
VIN-A
CLK
AVDD
AGND
VIN+D
VIN-D
AGND
AGND
12
13
25
24
Rev. PrF | Page 13 of 15
Oct. 6, 2003
AD9229
Preliminary Technical Data
TIMING DIAGRAM
N-1
AIN
tA
N
tEH
tEL
CLK
tPD
Data
Out
MSB
LSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB MSB
tCPD
DCO+
DCO-
tFPD
FCO-
FCO+
Figure 6: Serial LVDS Outputs
NOTE : Latency = 9 cycles
Rev. PrF | Page 14 of 15
Oct. 6, 2003
Preliminary Technical Data
AD9229
OUTLINE DIMENSIONS
Figure 7
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary
ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Ordering Guide
Model
Temperature Range
-40°C to +85°C (Ambient)
-40°C to +85°C (Ambient)
25°C (Ambient)
Description
AD9229BCP-50
AD9229BCP-65
AD9229/PCB
48-LFCSP
48-LFCSP
Evaluation Board ( Supplied with –65 Grade )
Table 7: Ordering Guide
© 2002 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
C02959-0-11/02(0)
Rev. PrF | Page 15 of 15
Oct. 6, 2003
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