AD9248BSTZRL-20 [ADI]
14-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter; 14位， 20 MSPS / 40 MSPS / 65 MSPS双通道A / D转换器
| 型号： | AD9248BSTZRL-20 |
| 厂家： | 
ADI |
| 描述： | 14-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter |
| 文件： | 总48页 (文件大小：1270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit, 20 MSPS/40 MSPS/65 MSPS
Dual A/D Converter
AD9248
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Integrated dual 14-bit ADC
AVDD
AGND
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 71.6 dB (to Nyquist, AD9248-65)
SFDR = 80.5 dBc (to Nyquist, AD9248-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
OTR_A
VIN+_A
VIN–_A
14
14
D13_A TO D0_A
OEB_A
SHA
ADC
OUTPUT
MUX/
BUFFERS
REFT_A
REFB_A
VREF
MUX_SELECT
CLK_A
CLOCK
DUTY CYCLE
STABILIZER
CLK_B
DCS
SENSE
AGND
SHARED_REF
PWDN_A
PWDN_B
DFS
0.5V
MODE
CONTROL
Output datamux option
REFT_B
REFB_B
VIN+_B
VIN–_B
APPLICATIONS
Ultrasound equipment
Direct conversion or IF sampling receivers
WB-CDMA, CDMA2000, WiMAX
Battery-powered instruments
Hand-held scopemeters
OTR_B
14
14
OUTPUT
MUX/
BUFFERS
SHA
ADC
D13_B TO D0_B
OEB_B
AD9248
DRVDD
DRGND
Figure 1.
Low cost digital oscilloscopes
Fabricated on an advanced CMOS process, the AD9248 is
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C).
GENERAL DESCRIPTION
The AD9248 is a dual, 3 V, 14-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and hold amplifiers (SHAs) and an
integrated voltage reference. The AD9248 uses a multistage
differential pipelined architecture with output error correction
logic to provide 14-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch full-
scale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9238, 12-bit 20 MSPS/
40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to suit
an application.
3. Low power consumption: AD9248-65: 65 MSPS = 600 mW,
AD9248-40: 40 MSPS = 330 mW, and AD9248-20: 20 MSPS =
180 mW.
4. Typical channel isolation of 85 dB @ fIN = 10 MHz.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
5. The clock duty cycle stabilizer (AD9248-20/AD9248-40/
AD9248-65) maintains performance over a wide range of
clock duty cycles.
6. Multiplexed data output option enables single-port operation
from either Data Port A or Data Port B.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
AD9248
TABLE OF CONTENTS
Specifications..................................................................................... 3
Clock Circuitry........................................................................... 22
Analog Inputs ............................................................................. 22
Reference Circuitry.................................................................... 22
Digital Control Logic................................................................. 22
Outputs ........................................................................................ 22
LQFP Evaluation Board Bill of Materials (BOM).................. 24
LQFP Evaluation Board Schematics........................................ 25
LQFP PCB Layers....................................................................... 29
Dual ADC LFCSP PCB.................................................................. 35
Power Connector........................................................................ 35
Analog Inputs ............................................................................. 35
Optional Operational Amplifier .............................................. 35
Clock ............................................................................................ 35
Voltage Reference ....................................................................... 35
Data Outputs............................................................................... 35
LFCSP Evaluation Board Bill of Materials (BOM) ................ 36
LFCSP PCB Schematics............................................................. 37
LFCSP PCB Layers..................................................................... 40
Thermal Considerations............................................................ 45
Outline Dimensions....................................................................... 46
Ordering Guide .......................................................................... 47
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Absolute Maximum Ratings............................................................ 8
Explanation of Test Levels........................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Equivalent Circuits......................................................................... 16
Theory of Operation ...................................................................... 17
Analog Input ............................................................................... 17
Clock Input and Considerations .............................................. 18
Power Dissipation and Standby Mode..................................... 19
Digital Outputs ........................................................................... 19
Timing.......................................................................................... 19
Data Format ................................................................................ 20
Voltage Reference....................................................................... 20
AD9248 LQFP Evaluation Board ................................................. 22
REVISION HISTORY
11/10—Rev. A to Rev. B
Changes to Terminology ............................................................... 11
Changes to Figure 22...................................................................... 15
Changes to Clock Input and Considerations Section................ 18
Changes to Timing Section........................................................... 19
Changes to Figure 33...................................................................... 19
Changes to Data Format Section.................................................. 20
Changes to Table 10 ....................................................................... 24
Changes to Figure 39...................................................................... 25
Changes to Table 13 ....................................................................... 36
Updated Outline Dimensions....................................................... 46
Changes to Ordering Guide.......................................................... 47
Changes to Absolute Maximum Ratings Section......................... 8
Changes to Figure 3.......................................................................... 9
Add Figure 4; Renumbered Sequentially....................................... 9
Changes to Theory of Operation Section and Analog Input
Section.............................................................................................. 17
Deleted Note 1 from Dual ADC LFCSP PCB Section............... 35
Updated Outline Dimensions....................................................... 46
3/05—Rev. 0 to Rev. A
Added LFCSP......................................................................Universal
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to General Description .................................................... 1
Changes to Product Highlights....................................................... 1
Changes to Table 6.......................................................................... 10
1/05—Revision 0: Initial Version
Rev. B | Page 2 of 48
AD9248
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
MIN to TMAX, DCS enabled, unless otherwise noted.
T
Table 1.
Test
AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65
Parameter
Temp Level Min Typ
Max
Min Typ
Max
Min Typ
Max
Unit
RESOLUTION
Full
VI
14
14
14
14
Bits
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Full
25°C
Full
Full
25°C
Full
VI
I
IV
V
IV
V
IV
14
14
Bits
±±.2
±±.25 ±2.2
±±.ꢀ5
±±.ꢀ
±2.ꢁ
±2.3
±1.3
±±.2
±±.3
±±.ꢀ5
±±.ꢀ
±2.ꢁ
±2.3
±1.3
±2.4
±±.2
±±.5
±±.ꢁ
±±.ꢀ5 ±1.±
±2.8
±1.3
±2.5
% FSR
% FSR
LSB
LSB
LSB
±1.±
±1.±
±4.5
Integral Nonlinearity (INL)2
25°C
±4.5
±2.4
±4.5
LSB
TEMPERATURE DRIFT
Offset Error
Gain Error1
Full
Full
V
V
±2
±12
±2
±12
±3
±12
ppm/°C
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.± mA
Output Voltage Error (±.5 V Mode)
Load Regulation @ ±.5 mA
INPUT REFERRED NOISE
Input Span = 1 V
Input Span = 2.± V
ANALOG INPUT
Full
Full
Full
Full
VI
V
V
±5
±35
±5
±35
±5
±35
mV
mV
mV
mV
±.8
±2.5
±.1
±.8
±2.5
±.1
±.8
±2.5
±.1
V
25°C
25°C
V
V
2.1
1.±5
2.1
1.±5
2.1
1.±5
LSB rms
LSB rms
Input Span = 1.± V
Input Span = 2.± V
Input Capacitance3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
Full
Full
Full
Full
IV
IV
V
1
2
ꢁ
ꢁ
1
2
ꢁ
ꢁ
1
2
ꢁ
ꢁ
V p-p
V p-p
pF
V
kΩ
AVDD
DRVDD
Full
Full
IV
IV
2.ꢁ
2.25 3.±
3.±
3.ꢀ
3.ꢀ
2.ꢁ
2.25 3.±
3.±
3.ꢀ
3.ꢀ
2.ꢁ
2.25 3.±
3.±
3.ꢀ
3.ꢀ
V
V
Supply Current
IAVDD2
Full
Full
Full
V
V
V
ꢀ±
5
±±.±1
11±
11
±±.±1
2±±
1ꢀ
±±.±1
mA
mA
% FSR
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input4
Sine Wave Input2
Standby Power5
Full
Full
Full
V
VI
V
18±
19±
2.±
33±
3ꢀ±
2.±
ꢀ±±
ꢀ4±
2.±
mW
mW
mW
21ꢁ
4±±
ꢁ±±
Rev. B | Page 3 of 48
AD9248
Test
AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65
Max Min Typ Max Min Typ Max
Parameter
Temp Level Min Typ
Unit
MATCHING CHARACTERISTICS
Offset Error
(Nonshared Reference Mode)
Offset Error
(Shared Reference Mode)
Gain Error
(Nonshared Reference Mode)
Gain Error
25°C
25°C
25°C
25°C
I
I
I
I
±±.19 ±1.5ꢀ
±±.19 ±1.5ꢀ
±±.±ꢁ ±1.43
±±.±1 ±±.±ꢀ
±±.19 ±1.5ꢀ
±±.19 ±1.5ꢀ
±±.±ꢁ ±1.43
±±.±1 ±±.±ꢀ
±±.25 ±1.ꢁ4 % FSR
±±.25 ±1.ꢁ4 % FSR
±±.±ꢁ ±1.4ꢁ % FSR
±±.±1 ±±.1± % FSR
(Shared Reference Mode)
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.± V external reference).
2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 29 for the equivalent analog input structure.
4 Measured with dc input at maximum clock rate.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
Rev. B | Page 4 of 48
AD9248
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V external reference,
MIN to TMAX, DCS Enabled, unless otherwise noted.
T
Table 2.
Test
AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65
Parameter
Temp Level Min Typ
Max Min Typ
Max Min Typ
Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz
Full
25°C
Full
25°C
Full
25°C
Full
V
IV
V
IV
V
IV
V
ꢁ3.4
ꢁ3.1 ꢁ3.ꢁ
ꢁ2.9
ꢁ3.1
ꢁ2.8 ꢁ3.4
ꢁ2.8
ꢁ2.3 ꢁ3.1
dB
dB
dB
dB
dB
dB
dB
dB
dB
fINPUT = 9.ꢁ MHz
fINPUT = 19.ꢀ MHz
fINPUT = 35 MHz
fINPUT = 1±± MHz
ꢁ2.4 ꢁ3.1
ꢁ2.ꢁ
ꢁ2.3 ꢁ2.9
ꢁ1.5
ꢁ1.2 ꢁ1.ꢀ
ꢀ9.±
25°C
25°C
IV
V
ꢁ±
ꢀ9.5
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD)
fINPUT = 2.4 MHz
fINPUT = 9.ꢁ MHz
fINPUT = 19.ꢀ MHz
fINPUT = 35 MHz
Full
25°C
Full
25°C
Full
25°C
Full
V
IV
V
IV
V
IV
V
ꢁ3.±
ꢁ2.2 ꢁ3.2
ꢁ2.±
ꢁ2.8
ꢁ2.± ꢁ3.±
ꢁ2.5
ꢁ1.ꢁ ꢁ2.ꢁ
dB
dB
dB
dB
dB
dB
dB
dB
dB
ꢁ±.9 ꢁ2.2
ꢁ2.1
ꢁ1.± ꢁ2.3
ꢁ±.9
ꢁ±.± ꢁ1.±
ꢀ8.5
25°C
25°C
IV
V
fINPUT = 1±± MHz
ꢀ9.5
ꢀ9.±
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 2.4 MHz
Full
25°C
Full
25°C
Full
25°C
Full
V
IV
V
IV
V
IV
V
11.8
11.ꢁ 11.8
11.ꢁ
11.8
11.ꢁ 11.8
11.8
11.ꢀ 11.8
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
fINPUT = 9.ꢁ MHz
fINPUT = 19.ꢀ MHz
fINPUT = 35 MHz
11.5 11.ꢁ
11.ꢁ
11.5 11.ꢁ
11.5
11.3 11.5
11.2
25°C
25°C
IV
V
fINPUT = 1±± MHz
11.3
11.2
WORST HARMONIC (SECOND or THIRD)
fINPUT = 2.4 MHz
Full
25°C
Full
25°C
Full
25°C
Full
V
IV
V
I
V
I
8ꢀ.±
ꢁꢁ.5 8ꢁ.5
83.±
85.±
ꢁꢁ.5 8ꢀ.±
84.±
ꢁꢁ.5 8ꢀ.±
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fINPUT = 9.ꢁ MHz
fINPUT = 19.ꢀ MHz
fINPUT = 35 MHz
ꢁꢀ.1 84.±
83.±
ꢁꢀ.± 84.±
V
I
8±.±
ꢁ3.± 8±.5
25°C
Rev. B | Page 5 of 48
AD9248
Test
AD9248BST/BCP-20 AD9248BST/BCP-40 AD9248BST/BCP-65
Parameter
Temp Level Min Typ
Max Min Typ
Max Min Typ
Max Unit
WORST OTHER SPUR
(NONSECOND or THIRD)
fINPUT = 2.4 MHz
fINPUT = 9.ꢁ MHz
fINPUT = 19.ꢀ MHz
fINPUT = 35 MHz
Full
25°C
Full
25°C
Full
25°C
Full
V
I
V
I
V
I
V
I
88.±
83.3 89.±
8ꢁ.±
88.±
83.5 89.±
85.5
81.± 8ꢀ.±
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
83.1 88.±
88.±
82.ꢀ 88.5
85.5
ꢁ9.8 8ꢀ.±
ꢁ5.±
25°C
25°C
fINPUT = 1±± MHz
V
ꢁ9.±
81.±
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fINPUT = 2.4 MHz
Full
25°C
Full
25°C
Full
25°C
Full
V
IV
V
I
V
I
8ꢀ.±
ꢁꢁ.5 8ꢁ.5
83.±
85.±
ꢁꢁ.5 8ꢀ.±
84.±
ꢁꢁ.5 8ꢀ.±
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
fINPUT = 9.ꢁ MHz
fINPUT = 19.ꢀ MHz
fINPUT = 35 MHz
CROSSTALK
ꢁꢀ.1
84.±
83.±
ꢁꢀ.± 84.±
V
I
8±.±
ꢁ3.± 8±.5
25°C
Full
V
−85.±
−85.±
−85.±
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
MIN to TMAX, DCS enabled, unless otherwise noted.
T
Table 3.
Test
AD9248BST/BCP-20
AD9248BST-40
Typ Max Min
AD9248BST-65
Typ Max Unit
Parameter
Temp Level Min
Typ Max Min
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
2.±
2.±
±.8
2.±
V
V
μA
μA
pF
±.8
+1±
+1±
±.8
+1±
+1±
−1±
−1±
+1±
+1±
−1±
−1±
−1±
−1±
2
2
2
LOGIC OUTPUTS1
High Level Output Voltage
Full
Full
IV
IV
DRVDD −
±.±5
DRVDD −
±.±5
DRVDD −
±.±5
V
V
Low Level Output Voltage
±.±5
±.±5
±.±5
1 Output voltage levels measured with capacitive load only on each output.
Rev. B | Page ꢀ of 48
AD9248
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
MIN to TMAX, DCS enabled, unless otherwise noted.
T
Table 4.
Test
AD9248BST/BCP-20
AD9248BST/BCP-40
AD9248BST/BCP-65
Parameter
Temp Level Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse-Width High1
CLK Pulse-Width Low1
DATA OUTPUT PARAMETER
Output Delay2 (tPD)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (tJ)
Wake-Up Time3
Full
Full
Full
Full
Full
VI
V
V
V
V
2±
4±
ꢀ5
MSPS
MSPS
ns
ns
ns
1
1
1
5±.±
15.±
15.±
25.±
8.8
8.8
15.4
ꢀ.2
ꢀ.2
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
2
3.5
ꢁ
1.±
±.5
2.5
2
ꢀ
2
3.5
ꢁ
1.±
±.5
2.5
2
ꢀ
2
3.5
ꢁ
1.±
±.5
2.5
2
ꢀ
ns
Cycles
ns
ps rms
ms
OUT-OF-RANGE RECOVERY TIME
Cycles
1 The AD9248-ꢀ5 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24).
2 Output delay is measured from clock 5±% transition to data 5±% transition, with a 5 pF load on each output.
3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with ±.1 μF and 1± μF capacitors on REFT and REFB.
N+1
N
N+8
N+2
N–1
N+3
ANALOG
INPUT
N+7
N+4
N+6
N+5
CLOCK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
tPD = MIN 2.0ns,
MAX 6.0ns
Figure 2. Timing Diagram
Rev. B | Page ꢁ of 48
AD9248
ABSOLUTE MAXIMUM RATINGS
EXPLANATION OF TEST LEVELS
Absolute maximum ratings are limiting values to be applied
individually, and beyond which the serviceability of the circuit
may be impaired. Functional operability is not necessarily implied.
Exposure to absolute maximum rating conditions for an extended
period may affect device reliability.
I
1±±% production tested.
II
1±±% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
Table 5.
Parameter
Rating
V
Parameter is a typical value only.
VI 1±±% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
1±±% production tested at temperature extremes for
military devices.
ELECTRICAL
AVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
Digital Outputs to DRGND
−±.3 V to +3.9 V
−±.3 V to +3.9 V
−±.3 V to +±.3 V
−3.9 V to +3.9 V
−±.3 V to DRVDD + ±.3 V
−±.3 V to AVDD + ±.3 V
ESD CAUTION
OEB, DFS, CLK, DCS, MUX_SELECT,
SHARED_REF to AGND
VINA, VINB to AGND
VREF to AGND
SENSE to AGND
REFB, REFT to AGND
PDWN to AGND
−±.3 V to AVDD + ±.3 V
−±.3 V to AVDD + ±.3 V
−±.3 V to AVDD + ±.3 V
−±.3 V to AVDD + ±.3 V
−±.3 V to AVDD + ±.3 V
ENVIRONMENTAL1
Operating Temperature
Junction Temperature
Lead Temperature (1± sec)
Storage Temperature
−4±°C to +85°C
15±°C
3±±°C
−ꢀ5°C to +15±°C
1 Typical thermal impedances: ꢀ4-lead LQFP, θJA = 54°C/W; ꢀ4-lead LFCSP, θJA
= 2ꢀ.4°C/W with heat slug soldered to ground plane. These measurements
were taken on a 4-layer board in still air, in accordance with EIA/JESD51-ꢁ.
Rev. B | Page 8 of 48
AD9248
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AGND
D6_A
PIN 1
2
VIN+_A
D5_A
3
4
VIN–_A
AGND
D4_A
D3_A
5
AVDD
D2_A
6
REFT_A
REFB_A
VREF
D1_A
7
D0_A (LSB)
DRVDD
DRGND
OTR_B
D13_B (MSB)
D12_B
D11_B
D10_B
D9_B
AD9248
64-LEAD LQFP
TOP VIEW
8
9
SENSE
REFB_B
REFT_B
AVDD
(Not to Scale)
10
11
12
13
14
15
16
AGND
VIN–_B
VIN+_B
AGND
D8_B
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. 64-Lead LQFP Pin Configuration
PIN 1
INDICATOR
AGND
VIN+_A
VIN–_A
AGND
1
2
3
4
5
6
7
8
9
48 D6_A
47 D5_A
46 D4_A
45 D3_A
44 D2_A
43 D1_A
42 D0_A (LSB)
41 DRVDD
40 DRGND
39 OTR_B
38 D13_B (MSB)
37 D12_B
36 D11_B
35 D10_B
34 D9_B
AVDD
REFT_A
REFB_A
VREF
AD9248
64-LEAD LFCSP
TOP VIEW
SENSE
REFB_B 10
REFT_B 11
AVDD 12
AGND 13
VIN–_B 14
VIN+_B 15
AGND 16
(Not to Scale)
33 D8_B
NOTES
1. THERE IS AN EXPOSED PAD THAT MUST CONNECT TO AGND.
Figure 4. 64-Lead LFCSP Pin Configuration
Rev. B | Page 9 of 48
AD9248
Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 4, 13, 1ꢀ
AGND
Analog Ground.
2
3
VIN+_A
VIN−_A
Analog Input Pin (+) for Channel A.
Analog Input Pin (−) for Channel A.
Analog Power Supply.
5, 12, 1ꢁ, ꢀ4 AVDD
ꢀ
ꢁ
8
9
1±
11
14
15
18
19
2±
21
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
VIN−_B
VIN+_B
CLK_B
DCS
Differential Reference (+) for Channel A.
Differential Reference (−) for Channel A.
Voltage Reference Input/Output.
Reference Mode Selection.
Differential Reference (−) for Channel B.
Differential Reference (+) for Channel B.
Analog Input Pin (−) for Channel B.
Analog Input Pin (+) for Channel B.
Clock Input Pin for Channel B.
Enable Duty Cycle Stabilizer (DCS) Mode.
Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement).
Power-Down Function Selection for Channel B.
DFS
PDWN_B
Logic ± enables Channel B. Logic 1 powers down Channel B (outputs static, not High-Z).
22
OEB_B
Output Enable Pin for Channel B.
Logic ± enables Data Bus B. Logic 1 sets outputs to High-Z.
23 to 2ꢁ,
3± to 38
D±_B (LSB) to
D13_B (MSB)
Channel B Data Output Bits.
28, 4±, 53
29, 41, 52
DRGND
DRVDD
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum ±.1 μF capacitor.
Recommended decoupling is ±.1 μF capacitor in parallel with 1± μF capacitor.
39
OTR_B
Out-of-Range Indicator for Channel B.
42 to 51,
54 to 5ꢁ
D±_A (LSB) to Channel A Data Output Bits.
D13_A (MSB)
58
59
OTR_A
OEB_A
Out-of-Range Indicator for Channel A.
Output Enable Pin for Channel A.
Logic ± enables Data Bus A. Logic 1 sets outputs to High-Z.
ꢀ±
ꢀ1
PDWN_A
Power-Down Function Selection for Channel A.
Logic ± enables Channel A. Logic 1 powers down Channel A (outputs static, not High-Z).
Data Multiplexed Mode.
MUX_SELECT
(See Data Format section for how to enable; high setting disables output data multiplexed mode.)
ꢀ2
ꢀ3
SHARED_REF
CLK_A
Shared Reference Control Pin (Low for Independent Reference Mode, High for Shared Reference Mode).
Clock Input Pin for Channel A.
EP
For the ꢀ4-Lead LFCSP only, there is an exposed pad that must connect to AGND.
Rev. B | Page 1± of 48
AD9248
TERMINOLOGY
Aperture Delay
Signal-to-Noise and Distortion (SINAD) Ratio
SHA performance measured from the rising edge of the clock
input to when the input signal is held for conversion.
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed dB.
Aperture Jitter
The variation in aperture delay for successive samples, which is
manifested as noise on the input to the ADC.
Effective Number of Bits (ENOB)
Using the following formula
Integral Nonlinearity (INL)
Deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
ENOB = (SINAD − 1.76)/6.02
ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in dB.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Spurious-Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as
Nyquist sampling.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1½ LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
IF Sampling
Due to the effects of aliasing, an ADC is not limited to Nyquist
sampling. Higher sampled frequencies are aliased down into the
first Nyquist zone (DC − fCLOCK/2) on the output of the ADC.
The bandwidth of the sampled signal should not overlap
Nyquist zones and alias onto itself. Nyquist sampling
performance is limited by the bandwidth of the input SHA and
clock jitter (jitter adds more noise at higher input frequencies).
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
Two-Tone SFDR
TMIN or TMAX.
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal (dBc).
Crosstalk
Coupling onto one channel being driven by a (−0.5 dBFS) signal
when the adjacent interfering channel is driven by a full-scale
signal. Measurement includes all spurs resulting from both
direct coupling and mixing components.
Rev. B | Page 11 of 48
AD9248
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V, unless otherwise noted.
0
100
95
90
85
80
75
70
65
SNR = 72.6dB
SINAD = 71.9dB
H2 = –81.5dBc
H3 = –86.8dBc
SFDR = 81.5dB
–20
SFDR
–40
–60
SNR
THIRD
HARMONIC
–80
SECOND
HARMONIC
CROSSTALK
60
55
50
–100
–120
0
5
10
15
20
25
30
40
45
50
55
60
65
FREQUENCY (MHz)
ADC SAMPLE RATE (MSPS)
Figure 5. Single-Tone FFT of Channel A Digitizing fIN = 12.5 MHz
While Channel B Is Digitizing fIN = 10 MHz
Figure 8. AD9248-65 Single-Tone SFDR/SNR vs. FS with fIN = 32.5 MHz
0
100
95
SNR = 70.5dB
SINAD = 69.4dB
H2 = –92.3dBc
H3 = –80.1dBc
SFDR = 80.1dBc
–20
90
SFDR
85
80
75
70
65
–40
–60
SNR
THIRD HARMONIC
SECOND
HARMONIC
–80
CROSSTALK
60
55
50
–100
–120
0
5
10
15
20
25
30
20
25
30
ADC SAMPLE RATE (MSPS)
35
40
FREQUENCY (MHz)
Figure 6. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz
While Channel B Is Digitizing fIN = 76 MHz
Figure 9. AD9248-40 Single-Tone SFDR/SNR vs. FS with fIN = 20 MHz
100
95
0
SNR = 68.1dB
SINAD = 68.0dB
H2 = –83.4dBc
H3 = –83.1dBc
SFDR = 75.1dBc
–20
90
SFDR
85
80
–40
–60
75
SNR
70
65
SECOND HARMONIC
CROSSTALK
–80
60
55
50
–100
–120
0
5
10
15
20
0
5
10
15
20
25
30
ADC SAMPLE RATE (MSPS)
FREQUENCY (MHz)
Figure 10. AD9248-20 Single-Tone SFDR/SNR vs. FS with fIN = 10 MHz
Figure 7. Single-Tone FFT of Channel A Digitizing fIN = 120 MHz
While Channel B Is Digitizing fIN = 126 MHz
Rev. B | Page 12 of 48
AD9248
100
90
95
90
SFDR
80
70
60
85
80
75
SFDR
SNR
SNR
50
40
70
65
–35
–30
–25
–20
–15
–10
–5
0
0
0
0
20
40
60
80
100
120
140
INPUT AMPLITUDE (dBFS)
INPUT FREQUENCY (MHz)
Figure 11. AD9248-65 Single-Tone SFDR/SNR vs. AIN with fIN = 32.5 MHz
Figure 14. AD9248-65 Single-Tone SFDR/SNR vs. fIN
95
90
100
90
SFDR
85
80
75
80
70
60
SFDR
SNR
SNR
60
70
65
50
40
20
40
80
100
120
140
–35
–30
–25
–20
–15
–10
–5
0
INPUT AMPLITUDE (dBFS)
INPUT FREQUENCY (MHz)
Figure 15. AD9248-40 Single-Tone SFDR/SNR vs. fIN
Figure 12. AD9248-40 Single-Tone SFDR/SNR vs. AIN with fIN = 20 MHz
95
90
85
100
90
SFDR
SFDR
80
70
60
80
75
SNR
SNR
70
65
50
40
20
40
60
80
100
120
140
–35
–30
–25
–20
–15
–10
–5
0
INPUT FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 16. AD9248-20 Single-Tone SFDR/SNR vs. fIN
Figure 13. AD9248-20 Single-Tone SFDR/SNR vs. AIN with fIN = 10 MHz
Rev. B | Page 13 of 48
AD9248
100
95
90
85
80
75
70
0
SFDR
–20
–40
–60
IMD = –85dBc
–80
SNR
–18
–100
65
60
–120
0
5
10
15
20
25
30
–24
–21
–15
–12
–9
–6
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 17. Dual-Tone FFT with fIN1 = 39 MHz and fIN2 = 40 MHz
Figure 20. Dual-Tone SFDR/SNR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz
0
100
SFDR
95
90
85
80
75
70
–20
–40
–60
IMD =
–83dBc
SNR
–80
–100
–120
65
60
0
5
10
15
20
25
30
–24
–21
–18
–15
–12
–9
–6
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 18. Dual-Tone FFT with fIN1 = 70 MHz and fIN2 = 71 MHz
Figure 21. Dual-Tone SFDR/SNR vs. AIN with fIN1 = 70 MHz and fIN2 = 71 MHz
0
100
95
90
–20
SFDR
–40
–60
85
80
75
70
–80
SNR
–100
–120
65
60
0
5
10
15
20
25
30
–24
–21
–18
–15
–12
–9
–6
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 19. Dual-Tone FFT with fIN1 = 200 MHz and fIN2 = 201 MHz
Figure 22. Dual-Tone SFDR/SNR vs.
IN with fIN1 = 200 MHz and fIN2 = 201 MHz
A
Rev. B | Page 14 of 48
AD9248
74
72
12.0
11.5
11.0
–65
600
SINAD –20
500
400
SINAD –65
SINAD –40
–40
300
70
68
200
100
–20
0
10
20
30
40
50
60
0
20
40
60
SAMPLE RATE (MSPS)
CLOCK FREQUENCY (MHz)
Figure 26. Analog Power Consumption vs. FS
Figure 23. SINAD vs. FS with Nyquist Input
95
90
85
80
75
70
65
60
55
50
2.5
2.0
DCS ON (SFDR)
1.5
DCS OFF (SFDR)
DCS ON (SINAD)
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
DCS OFF (SINAD)
30
35
40
45
50
55
60
65
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
DUTY CYCLE (%)
Figure 24. SINAD/SFDR vs. Clock Duty Cycle
Figure 27. AD9248-65 Typical INL
84
82
80
78
76
74
72
70
68
66
1.0
0.8
SFDR
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
SINAD
–50
0
50
100
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
TEMPERATURE (°C)
Figure 25. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz
Figure 28. AD9248-65 Typical DNL
Rev. B | Page 15 of 48
AD9248
EQUIVALENT CIRCUITS
AVDD
AVDD
CLK_A, CLK_B
DCS, DFS,
MUX_SELECT,
SHARED_REF
VIN+_A, VIN–_A,
VIN+_B, VIN–_B
Figure 31. Equivalent Digital Input Circuit
Figure 29. Equivalent Analog Input Circuit
DRVDD
Figure 30. Equivalent Digital Output Circuit
Rev. B | Page 1ꢀ of 48
AD9248
THEORY OF OPERATION
In IF under-sampling applications, any shunt capacitors
The AD9248 consists of two high performance ADCs that are
based on the AD9235 converter core. The dual ADC paths are
independent, except for a shared internal band gap reference
source, VREF. Each of the ADC paths consists of a proprietary
front end SHA followed by a pipelined switched-capacitor ADC.
The pipelined ADC is divided into three sections, consisting
of a 4-bit first stage, followed by eight 1.5-bit stages, and a final
3-bit flash. Each stage provides sufficient overlap to correct for
flash errors in the preceding stages. The quantized outputs from
each stage are combined through the digital correction logic
block into a final 14-bit result. The pipelined architecture
permits the first stage to operate on a new input sample, while
the remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the
should be removed. In combination with the driving source
impedance, they limit the input bandwidth. For best dynamic
performance, the source impedances driving VIN+ and VIN−
should be matched such that common-mode settling errors are
symmetrical. These errors are reduced by the common-mode
rejection of the ADC.
H
T
T
5pF
5pF
VIN+
C
PAR
respective clock.
T
VIN–
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the flash ADC
output to control a switched-capacitor digital-to-analog converter
(DAC) of the same resolution. The DAC output is subtracted from
the stage’s input signal and the residual is amplified (multiplied)
to drive the next pipeline stage. The residual multiplier stage is
also called a multiplying DAC (MDAC). One bit of redundancy
is used in each one of the stages to facilitate digital correction of
flash errors. The last stage simply consists of a flash ADC.
C
PAR
T
H
Figure 32. Switched-Capacitor Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
The input stage contains a differential SHA that can be
configured as ac- or dc-coupled in differential or single-ended
modes. The output-staging block aligns the data, carries out the
error correction, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
REFT = ½(AVDD + VREF
)
REFB = ½(AVDD −VREF
)
Span = 2 × (REFT − REFB) = 2 × VREF
The equations above show that the REFT and REFB voltages are
symmetrical about the midsupply voltage and, by definition, the
input span is twice the value of the VREF voltage.
ANALOG INPUT
The analog input to the AD9248 is a differential, switched-
capacitor SHA that has been designed for optimum perfor-
mance while processing a differential input signal. The SHA
input accepts inputs over a wide common-mode range. An
input common-mode voltage of midsupply is recommended
to maintain optimal performance.
The internal voltage reference can be pin-strapped to fixed values
of 0.5 V or 1.0 V or adjusted within the same range as discussed
in the Internal Reference Connection section. Maximum SNR
performance is achieved with the AD9248 set to the largest
input span of 2 V p-p. The relative SNR degradation is 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
The SHA input is a differential switched-capacitor circuit. In
Figure 32, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC input;
therefore, the precise values are dependent on the application.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as:
VCMMIN = VREF/2
VCMMAX = (AVDD + VREF)/2
Rev. B | Page 1ꢁ of 48
AD9248
The minimum common-mode input level allows the AD9248 to
accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a single-ended
source may be driven into VIN+ or VIN−. In this configuration,
one input accepts the signal, while the opposite input should be
set to midscale by connecting it to an appropriate reference. For
example, a 2 V p-p signal may be applied to VIN+, while a 1 V
reference is applied to VIN−. The AD9248 then accepts an
input signal varying between 2 V and 0 V. In the single-ended
configuration, distortion performance may degrade significantly
as compared to the differential case. However, the effect is less
noticeable at lower input frequencies and in the lower speed grade
models (AD9248-40 and AD9248-20).
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to the clock duty cycle. Commonly, a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance
characteristics.
The AD9248 provides separate clock inputs for each channel. The
optimum performance is achieved with the clocks operated at the
same frequency and phase. Clocking the channels asynchronously
may degrade performance significantly. In some applications, it
is desirable to skew the clock timing of adjacent channels. The
AD9248’s separate clock inputs allow for clock timing skew
(typically 1 ns) between the channels without significant
performance degradation.
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9248 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
The AD9248-65 contains two clock duty cycle stabilizers, one
for each converter, that retime the nonsampling edge, providing
an internal clock with a nominal 50% duty cycle. When proper
track-and-hold times for the converter are required to maintain
high performance, maintaining a 50% duty cycle clock is
particularly important in high speed applications. It may be
difficult to maintain a tightly controlled duty cycle on the input
clock on the PCB (see Figure 24). DCS can be enabled by tying
the DCS pin high.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9248. This is especially true in IF
under-sampling applications where frequencies in the 70 MHz
to 200 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 33.
The duty cycle stabilizer uses a delay-locked loop to create the
nonsampling edge. As a result, any changes to the sampling
frequency require approximately 2 μs to 3 μs to allow the DLL
to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated as
AVDD
50Ω
VINA
10pF
2V p-p
49.9Ω
AD9248
50Ω
VINB
AGND
⎡
⎢
⎣
⎤
⎥
⎦
1
SNR = 20 × log
10pF
(
2 × π × fINPUT ×t j
)
1kΩ
1kΩ
0.1μF
In the equation, the rms aperture jitter, tJ , represents the root-
sum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Under-sampling applications are particularly sensitive to jitter.
Figure 33. Differential Transformer Coupling
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
For optimal performance, especially in cases where aperture
jitter may affect the dynamic range of the AD9248, it is important
to minimize input clock jitter. The clock input circuitry should
use stable references; for example, use analog power and ground
planes to generate the valid high and low digital levels for the
AD9248 clock input. Power supplies for clock drivers should be
separated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods), it
should be retimed by the original clock at the last step.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
Rev. B | Page 18 of 48
AD9248
A single channel can be powered down for moderate power
POWER DISSIPATION AND STANDBY MODE
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered on. Because the buffer and voltage reference
remain powered on, the wake-up time is reduced to several
clock cycles.
The power dissipated by the AD9248 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
DIGITAL OUTPUTS
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
The AD9248 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
where N is the number of bits changing, and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases with clock frequency.
Either channel of the AD9248 can be placed into standby mode
independently by asserting the PDWN_A or PDWN_B pins.
The data format can be selected for either offset binary or twos
complement. See the Data Format section for more information.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
results in a typical power consumption of 1 mW for the ADC.
Note that if DCS is enabled, it is mandatory to disable the clock
of an independently powered-down channel. Otherwise,
significant distortion results on the active channel. If the clock
inputs remain active while in total standby mode, typical power
dissipation of 12 mW results.
TIMING
The AD9248 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propa-
gation delay (tPD) after the rising edge of the clock signal. Refer
to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the AD9248
using the DCS pin. This provides a stable 50% duty cycle to
internal circuits.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B =
HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time is directly related to the
recharging of the REFT and REFB decoupling capacitors and to
the duration of the power-down. Typically, it takes approximately
5 ms to restore full operation with fully discharged 0.1 μF and
10 μF decoupling capacitors on REFT and REFB.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9248.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9248
is 1 MSPS. At clock rates below 1 MSPS, dynamic performance
may degrade.
A
A
ANALOG INPUT
ADC A
A
1
0
8
A
2
A
–1
A
7
A
3
A
A
6
4
A
5
B
B
B
1
0
8
B
ANALOG INPUT
ADC B
2
B
–1
B
7
B
3
B
B
6
4
B
5
CLK_A = CLK_B =
MUX_SELECT
D0_A TO
D11_A
B
A
B
–7
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
1
–8
–7
–6
–6
–5
–5
–4
–4
–3
–3
–2
–2
–1
–1
0
0
tPD
tPD
Figure 34. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
Rev. B | Page 19 of 48
AD9248
DATA FORMAT
gain and offset matching performance. If the ADCs are to
function independently, the reference decoupling can be
treated independently and can provide superior isolation
between the dual channels. To enable shared reference mode,
the SHARED_REF pin must be tied high and the external
differential references must be externally shorted. (REFT_A
must be externally shorted to REFT_B, and REFB_A must be
shorted to REFB_B.)
The AD9248 data output format can be configured for either
twos complement or offset binary. This is controlled by the data
format select pin (DFS). Connecting DFS to AGND produces
offset binary output data. Conversely, connecting DFS to AVDD
formats the output data as twos complement.
The output data from the dual ADCs can be multiplexed onto a
single 14-bit output bus. The multiplexing is accomplished by
toggling the MUX_SELECT bit, which directs channel data to
the same or opposite channel data port. When MUX_SELECT
is logic high, the Channel A data is directed to the Channel A
output bus, and the Channel B data is directed to the Channel B
output bus. When MUX_SELECT is logic low, the channel data
is reversed, that is, the Channel A data is directed to the
Internal Reference Connection
A comparator within the AD9248 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 7. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 35), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected, as shown in Figure 36, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
Channel B output bus, and the Channel B data is directed to the
Channel A output bus. By toggling the MUX_SELECT bit,
multiplexed data is available on either of the output data ports.
If the ADCs run with synchronized timing, this same clock can
be applied to the MUX_SELECT pin. Any skew between
CLK_A, CLK_B, and MUX_SELECT can degrade AC
performance. It is recommended to keep the clock skew
<100 pS. After the MUX_SELECT rising edge, either data port
has the data for its respective channel; after the falling edge, the
alternate channel’s data is placed on the bus. Typically, the other
unused bus would be disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure 34 shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel’s power-
down pin must remain low.
VREF = 0.5 × (1 + R2/R1)
In all reference configurations, REFT and REFB drive the ADC
core and establish its input span. The input range of the ADC
always equals twice the voltage at the reference pin for either an
internal or an external reference.
VIN+
VIN–
REFT
0.1μF
ADC
CORE
0.1μF
10μF
VOLTAGE REFERENCE
REFB
0.1μF
A stable and accurate 0.5 V voltage reference is built into the
AD9248. The input range can be adjusted by varying the
reference voltage applied to the AD9248, using either the
internal reference with different external resistor configurations
or an externally applied reference voltage. The input span of the
ADC tracks reference voltage changes linearly. If the ADC is
being driven differentially through a transformer, the reference
voltage can be used to bias the center tap (common-mode
voltage).
VREF
10μF
SELECT
LOGIC
0.1μF
0.5V
SENSE
AD9248
The shared reference mode allows the user to connect the
references from the dual ADCs together externally for superior
Figure 35. Internal Reference Configuration
Table 7. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
AVDD
N/A
2 × External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
VREF
±.2 V to VREF
AGND to ±.2 V
±.5
1.±
±.5 × (1 + R2/R1)
1.±
2 × VREF (See Figure 3ꢀ)
2.±
Rev. B | Page 2± of 48
AD9248
1.2
1.0
External Reference Operation
The use of an external reference may be necessary to
enhance the gain accuracy of the ADC or to improve thermal
drift characteristics. When multiple ADCs track one another, a
single reference (internal or external) may be necessary to
reduce gain matching errors to an acceptable level. A high
precision external reference may also be selected to provide
lower gain and offset temperature drift. Figure 37 shows the
typical drift characteristics of the internal reference in both
1 V and 0.5 V modes. When the SENSE pin is tied to AVDD,
the internal reference is disabled, allowing the use of an
external reference. An internal reference buffer loads the
external reference with an equivalent 7 kΩ load. The internal
buffer still generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. The input span
is always twice the value of the reference voltage; therefore, the
external reference must be limited to a maximum of 1 V. If the
internal reference of the AD9248 is used to drive multiple
converters to improve gain matching, the loading of the
reference by the other converters must be considered. Figure 38
depicts how the internal reference voltage is affected by loading.
VREF = 1V
0.8
0.6
0.4
VREF = 0.5V
0.2
0
–30 –20 –10
0
20 30
TEMPERATURE (°C)
50 60 70 80
–40
10
40
Figure 37. Typical VREF Drift
0.05
0
–0.05
–0.10
–0.15
0.5V ERROR
VIN+
1V ERROR
VIN–
REFT
0.1μF
–0.20
–0.25
ADC
CORE
0.1μF
10μF
REFB
0.1μF
0.5
1.0
1.5
LOAD (mA)
2.0
3.0
0
2.5
VREF
R2
Figure 38. VREF Accuracy vs. Load
10μF
10μF
SENSE
SELECT
LOGIC
0.5V
R1
AD9248
Figure 36. Programmable Reference Configuration
Rev. B | Page 21 of 48
AD9248
AD9248 LQFP EVALUATION BOARD
The evaluation board supports both the AD9238 and AD9248
and has five main sections: clock circuitry, inputs, reference
circuitry, digital control logic, and outputs. A description of
each section follows. Table 8 shows the jumper settings and
notes assumptions in the comment column.
The common-mode level for both input options is set to
midsupply by a resistor divider off the AVDD supply but can
also be overdriven with an external supply using the (test
points) TP12, TP13 for the AD8138s, and TP14, TP15 for the
XFMRs. For low distortion of full-scale input signals when
using an AD8138, put Jumper JP17 and Jumper JP22 in
Position B and put an external negative supply on the TP10 and
TP11 testpoints.
Four supply connections to TB1 are necessary for the evaluation
board: the analog supply of the DUT, the on-board analog
circuitry supply, the digital driver DUT supply, and the on-
board digital circuitry supply. Separate analog and digital
supplies are recommended, and on each supply 3 V is nominal.
Each supply is decoupled on-board, and each IC, including the
DUT, is decoupled locally. All grounds should be tied together.
For best performance, use low jitter input sources and a high
performance band-pass filter after the signal source, before the
evaluation board (see Figure 39). For XFMR inputs, use solder
Jumper JP13 and Jumper JP14 for Channel A, and Jumper JP20
and Jumper JP21 for Channel B. For AD8138 inputs, use solder
Jumper JP15 and Jumper JP16 for Channel A, and Jumper JP18
and Jumper JP19 for Channel B. Remove all solder from the
jumpers not being used.
CLOCK CIRCUITRY
The clock circuitry is designed for a low jitter sine wave source
to be ac-coupled and level shifted before driving the 74VHC04
hex inverter chips (U8 and U9) whose output provides the clock
to the part. The POT (R32 and R31) on the level shifting
circuitry allows the user to vary the duty cycle if desired. The
amplitude of the sine wave must be large enough for the trip
points of the hex inverter and within the supplies to avoid noise
from clipping. To ensure a 50% duty cycle internal to the part,
the AD9248-65 has an on-chip duty cycle stabilizer circuit that
is enabled by putting in Jumper JP11. The duty cycle stabilizer
circuitry should only be used at clock rates above 40 MSPS.
REFERENCE CIRCUITRY
The evaluation board circuitry allows the user to select a
reference mode through a series of jumpers and provides an
external reference if necessary. Please refer to Table 9 to find the
jumper settings for each reference mode. The external reference
on the board is a simple resistor divider/zener diode circuit
buffered by an AD822 (U4). The POT (R4) can be used to
change the level of the external reference to fine adjust the ADC
full scale.
Each channel has its own clock circuitry, but normally both
clock pins are driven by a single 74VHC04, and the solder
Jumper JP24 is used to tie the clock pins together. When the
clock pins are tied together and only one 74VHC04 is being
used, the series termination resistor for the other channel must
be removed (either R54 or R55, depending on which inverter is
being used).
DIGITAL CONTROL LOGIC
The digital control logic on the evaluation board is a series of
jumpers and pull-down resistors used as digital inputs for the
following pins on the AD9248: the power-down and output
enable bar for each channel, the duty cycle restore circuitry, the
twos complement output mode, the shared reference mode, and
the MUX_SELECT pin. Refer to Table 8 for normal operating
jumper positions.
A data capture clock for each channel is created and sent to the
output buffers in order to be used in the data capture system if
needed. Jumper JP25 and Jumper JP26 are used to invert the
data clock, if necessary, and can be used to debug data capture
timing problems.
OUTPUTS
The outputs of the AD9248 (and the data clock discussed
earlier) are buffered by 74VHC541s (U2, U3, U7, U10) to
ensure the correct load on the outputs of the DUT, as well as the
extra drive capability to the next part of the system. The
74VHC541s are latches, but on this evaluation board, they are
wired and function as buffers. Jumper JP30 can be used to tie
the data clocks together if desired. If the data clocks are tied, the
R39 or R40 resistor must be removed, depending on which
clock circuitry is being used.
ANALOG INPUTS
The AD9248 achieves the best performance with a differential
input. The evaluation board has two input options for each
channel, a transformer (XFMR) and an AD8138, both of which
perform single-ended-to-differential conversions. The XFMR
allows for the best high frequency performance, and the
AD8138 is ideal for dc evaluation, low frequency inputs, and
driving an ADC differentially without loading the single-ended
signal.
Rev. B | Page 22 of 48
AD9248
Table 9. Reference Jumpers
Reference Mode
1 V Internal
±.5 V Internal
External
JP1
Out
Out
In
JP2
In
Out
Out
JP3
Out
In
JP4
JP5
Out
Out
In
Table 8. PCB Jumpers
Out
Out
Out
Normal
Setting Comment
JP Description
Out
1
2
3
4
5
ꢀ
ꢁ
8
9
Reference
Reference
Reference
Reference
Out
In
1 V Reference Mode
1 V Reference Mode
1 V Reference Mode
1 V Reference Mode
1 V Reference Mode
Out
Out
Out
Out
Out
Out
Out
Out
In
SINE SOURCE
LOW JITTER
(HP8644)
Reference
SINE SOURCE
LOW JITTER
(HP8644)
Shared Reference
Shared Reference
PDWN B
AD9248
EVALUATION BOARD
PDWN A
CLOCK
CIRCUITRY
1± Shared Reference
11 Duty Cycle
Duty Cycle Restore On
12 Twos Complement Out
OUTPUT
BUFFERS
INPUT
BAND-PASS
FILTERS
AD9248
CIRCUITRY
13 Input
In
Using XFMR Input
Using XFMR Input
Using XFMR Input
Using XFMR Input
Using XFMR Input
Using XFMR Input
14 Input
In
15 Input
1ꢀ Input
1ꢁ AD8138 Supply
18 Input
19 Input
Out
Out
A
Out
Out
In
REFERENCE MODE
SELECTION/EXTERNAL
REFERENCE/CONTROL
LOGIC
Figure 39. PCB Test Setup
2± Input
21 Input
In
22 AD8138 Supply
23 Mux Select
24 Tie Clocks
25 Data Clock
2ꢀ Data Clock
2ꢁ Mux Select
28 OEB_A
29 Mux Select
3± Data Clock
35 OEB_B
A
Out
In
A
Out
In
Out
Out
Out
Out
Using One Signal for Clock
Using One Signal for Clock
Rev. B | Page 23 of 48
AD9248
LQFP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 10.
No. Quantity Reference Designator
Device
Package
ACASE
±8±5
±ꢀ±3
±ꢀ±3
DCASE
12±ꢀ
ACASE
±2±1
±8±5
±ꢀ±3
Value
1± μF
±.1 μF
±.±±1 μF
±.1 μF
22 μF
±.1 μF
ꢀ.3 V
±.±1 μF
1
2
3
18
23
ꢁ
C1, C2, C11, C12, C2ꢁ, C28, C33, C34, C5±, C51, Cꢁ3 to Cꢁꢀ, C8ꢁ to C9±
C3 to C1±, C29 to C31, C5ꢀ, Cꢀ1 to Cꢀ5, Cꢁꢁ, Cꢁ9, C8±, C84 to C8ꢀ
C13, C15, C18, C19, C21, C23, C25
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
Capacitors
AD158±
4
5
15
4
Cꢀ, C14, C1ꢀ, C1ꢁ, C2±, C22, C24, C2ꢀ, C32, C35 to C4±
C41 to C44
ꢀ
4
C45 to C48
ꢁ
2
C49, C53
8
2
C52, C5ꢁ
9
4
C54, C55, Cꢀ8, Cꢀ9
1±
11
12
13
14
15
1ꢀ
1ꢁ
18
19
2±
21
22
23
24
25
2ꢀ
2ꢁ
28
29
3±
31
32
33
34
35
3ꢀ
3ꢁ
38
39
4±
41
42
43
44
4
2
1
1
14
13
4
4
ꢀ
1
1
ꢁ
ꢀ
8
ꢀ
2
4
2
4
2
2
2
1ꢀ
ꢀ
C58, C59 ,Cꢁ±, Cꢁ1
Cꢀ±, Cꢁ2
D1
J1
JP1 to JP5, JP8 to JP12, JP23, JP28, JP29, JP35
JPꢀ, JPꢁ, JP13, JP14 to JP1ꢀ, JP18 to JP21, JP24, JP2ꢁ, JP3±
JP1ꢁ, JP22, JP25, JP2ꢀ
L1 to L4
R1, R2, R13, R14, R23, R2ꢁ
R3
DNP
2± pF
±ꢀ±3
SOT-23CAN 1.2 V
SAM±8±UPM
JPRBLK±2
JPRSLD±2
JPRBLK±3
LC121±
12±ꢀ
12±ꢀ
RV3299UP
±8±5
12±ꢀ
±8±5
12±ꢀ
12±ꢀ
12±ꢀ
RV3299W
±8±5
12±ꢀ
±8±5
IND121±
Resistors
Resistor
1± μH
33 Ω
5.49 kΩ
1± kΩ
5 kΩ
49.9 Ω
1 kΩ
499 Ω
523 Ω
4± Ω
1± kΩ
5±± Ω
1± kΩ
22 Ω
± Ω
22 Ω
R4
Resistor
R5, Rꢀ, R38, R41, R43, R44, R51
Rꢁ, R8, R19, R2±, R52, R53
R9, R18, R29, R3±, R4ꢁ to R5±
R1±, R12, R15, R24, R25, R28
R11, R2ꢀ
R1ꢀ, R1ꢁ, R21, R22
R31, R32
R33 to R35, R42
R3ꢀ, R3ꢁ
R39, R4±
R54, R55
RP1 to RP1ꢀ
S1 to Sꢀ
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistors
Resistor Pack
12±ꢀ
RCAꢁ42±4
SMA2±±UP
DIP±ꢀRCUP
2
1
4
4
ꢁ
2
1
4
T1, T2
TB1
TP1, TP3, TP5, TPꢁ
TP2, TP4, TPꢀ, TP8
TP9, TP12 to TP1ꢁ
TP1±, TP11
T1-1T
TBLK±ꢀREM
RED
BLK
WHT
LOOPTP
LOOPTP
LOOPMINI
LOOPMINI
ꢀ4LQFPꢁXꢁ
SOL2±
SOIC-8
SO8NCꢁ
TSSOP-14
RED
U1
AD9248
ꢁ4VHC541
AD822
AD8138
ꢁ4VHC±4
U2, U3, Uꢁ, U1±
U4
U5, Uꢀ
1
2
2
U8, U9
Rev. B | Page 24 of 48
AD9248
LQFP EVALUATION BOARD SCHEMATICS
Figure 40. Evaluation Board Schematic
Rev. B | Page 25 of 48
AD9248
Figure 41. Evaluation Board Schematic (Continued)
Rev. B | Page 2ꢀ of 48
AD9248
Figure 42. Evaluation Board Schematic (Continued)
Rev. B | Page 2ꢁ of 48
AD9248
C28
10μF
6.3V
C75
10μF
6.3V
C8
0.1μF
C3
0.1μF
C10
0.1μF
C9
0.1μF
DVDD
1
19
20
10
R40
22Ω
G1
G2
VCC
GND
DATACLKA
U10
2
4
1
3
RP1 22Ω
1
8
74VHC541
1RP9 22Ω
8
2
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
RP9
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
2
3
4
1
2
3
4
7
6
5
8
7
6
5
RP1
RP1
RP1
RP2
RP2
RP2
RP2
RP3
RP3
RP3
RP3
RP4
RP4
RP4
RP4
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
3
6
5
OTRA
DA13
DA12
DA11
DA10
DA9
RP9
4
5
6
7
8
9
8
7
RP9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
9
RP10
RP10
RP10
RP10
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DA8
20
10
1
19
G1
G2
VCC
GND
U7
74VHC541
1
2
3
4
1
2
3
4
RP11
RP11
RP11
RP11
RP12
RP12
RP12
RP12
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
8
2
18
17
16
15
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
3
4
5
6
7
8
9
7
6
5
8
7
6
5
14
13
12
11
J1
SAM080UPM
JP30
C27
10μF
6.3V
C76
C7
0.1μF
C6
0.1μF
C4
0.1μF
C5
0.1μF
10μF
6.3V
DVDD
1
20
10
VCC
GND
G1
G2
19
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
41
U2
22Ω
8
1 RP13
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
74VHC541
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
RP5
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
8
7
2
3
4
1
2
3
4
1
18
RP13
RP13
RP13
RP14
RP14
RP14
RP14
RP15
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
2
3
4
5
6
7
8
9
7
6
5
A1
A2
A3
A4
A5
A6
A7
A8
Y1
OTRB
DA13
DA12
DA11
DA10
DA9
17
16
15
14
13
12
11
RP5
RP5
RP5
RP6
RP6
RP6
RP6
RP7
RP7
RP7
RP7
RP8
RP8
RP8
Y2
Y3
Y4
Y5
Y6
Y7
Y8
6
5
8
7
6
5
8
7
6
5
8
7
6
8
7
6
5
8
DA8
DA7
20
10
1
G1
G2
VCC
GND
19
U3
74VHC541
18
17
16
15
14
13
12
11
2
3
4
1
2
3
4
RP15
RP15
RP15
RP16
RP16
RP16
RP16
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
7
6
5
8
7
6
5
2
3
4
5
6
7
8
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
DA6
DA5
DA4
DA3
DA2
DA1
DA0
4
RP8 22Ω 5
J1
SAM080UPM
Y7
Y8
9
R39
22Ω
DATACLKB
Figure 43. Evaluation Board Schematic (Continued)
Rev. B | Page 28 of 48
AD9248
LQFP PCB LAYERS
Figure 44. PCB Top Layer
Rev. B | Page 29 of 48
AD9248
Figure 45. Bottom Layer
Rev. B | Page 3± of 48
AD9248
Figure 46. PCB Ground Plane
Rev. B | Page 31 of 48
AD9248
Figure 47. PCB Split Power Plane
Rev. B | Page 32 of 48
AD9248
Figure 48. PCB Top Silkscreen (Note that the PCB Supports Both the AD9238 and AD9248 LQFP)
Rev. B | Page 33 of 48
AD9248
Figure 49. PCB Bottom Silkscreen
Rev. B | Page 34 of 48
AD9248
DUAL ADC LFCSP PCB
CLOCK
The PCB requires a low jitter clock source, analog sources, and
power supplies. The PCB interfaces directly with Analog Devices
standard dual-channel data capture board (HSC-ADC-EVAL-DC),
which together with ADI’s ADC Analyzer™ software allows for
quick ADC evaluation.
The clock inputs are buffered on the board at U5 and U6. These
gates provide buffered clocks to the on-board latches, U2 and
U4, ADC input clocks, and DRA, DRB that are available at the
output Connector P3, P8. The clocks can be inverted at the
timing jumpers labeled with the respective clocks. The clock
paths also provide for various termination options. The ADC
input clocks can be set to bypass the buffers at solder bridges
P2, P9 and P10, P12. An optional clock buffer U3, U7 can also
be placed. The clock inputs can be bridged at TIEA, TIEB (R20,
R40) to allow one to clock both channels from one clock source;
however, optimal performance is obtained by driving J2 and J3.
POWER CONNECTOR
Power is supplied to the board via three detachable 4-lead
power strips.
Table 11. Power Connector
Terminal
VCC1 3.± V
VDD1 3.± V
VDL1 3.± V
VREF
Comments
Analog supply for ADC
Output supply for ADC
Supply circuitry
Optional external VREF
Optional op amp supply
Optional op amp supply
Table 12. Jumpers
Terminal
Comments
OEB A
PDWN A
MUX
Output Enable for A Side
Power-Down A
Mux Input
+5 V
−5 V
1VCC, VDD, and VDL are the minimum required power connections.
SHARED REF
DR A
LATA
ENC A
OEB B
PDWN B
DFS
SHARED REF
DR B
LATB
ENC B
Shared Reference Input
Invert DR A
Invert A Latch Clock
Invert Encode A
Output Enable for B Side
Power-Down B
Data Format Select
Shared Reference Input
Invert DR B
Invert B Latch Clock
Invert Encode B
ANALOG INPUTS
The evaluation board accepts a 2 V p-p analog input signal
centered at ground at two SMB connectors, Input A and
Input B. These signals are terminated at their respective
transformer primary side. T1 and T2 are wideband RF
transformers that provide the single-ended-to-differential
conversion, allowing the ADC to be driven differentially,
minimizing even-order harmonics. The analog signals can be
low-pass filtered at the transformer secondary to reduce high
frequency aliasing.
VOLTAGE REFERENCE
OPTIONAL OPERATIONAL AMPLIFIER
The ADC SENSE pin is brought out to E41, and the internal
reference mode is selected by placing a jumper from E41 to
ground (E27). External reference mode is selected by placing a
jumper from E41 to E25 and E30 to E2. R56 and R45 allow for
programmable reference mode selection.
The PCB has been designed to accommodate an optional
AD8139 op amp that can serve as a convenient solution for
dc-coupled applications. To use the AD8139 op amp, remove
C14, R4, R5, C13, R37, and R36. Place R22, R23, R30, and R24.
DATA OUTPUTS
The ADC outputs are latched on the PCB at U2, U4. The ADC
outputs have the recommended series resistors in line to limit
switching transient effects on ADC performance.
Rev. B | Page 35 of 48
AD9248
LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 13.
No.
Quantity
Reference Designator
C1, C3
C2, C5, Cꢁ, C9, C1±, C22, C3ꢀ
C4, Cꢀ, C8, C11 to C15, C2±, C21,
C24 to C2ꢁ, C29 to C35, C39 to Cꢀ1
Device
Package
±2±1
±8±5
Value
2± pF
1± μF
±.1 μF
1
2
3
2
ꢁ
44
Capacitors
Capacitors
Capacitors
±4±2
4
5
ꢀ
ꢁ
8
9
1±
11
12
13
14
15
1ꢀ
ꢀ
2
ꢀ
3
3
2
4
ꢀ
4
9
ꢀ
2
2ꢁ
C1ꢀ to C19, C3ꢁ, C38
C23, C28
J1 to Jꢀ
P1, P4, P11
P1, P4, P11
P31, P8
R1, R2, R32, R34
R3, Rꢀ, Rꢁ, R8, R11, R14, R33, R42, R51, Rꢀ1
R4, R5, R3ꢀ, R3ꢁ
Capacitors
Capacitors
SMBs
Power Connector Posts
Detachable Connectors
Connectors
Resistors
Resistors
Resistors
Resistors
Resistors
TAJD
±2±1
1± μF
±.1 μF
Z5.531.3425.±
25.ꢀ±2.5453.±
Wieland
Wieland
±4±2
±4±2
±4±2
±4±2
±4±2
±4±2
±4±2
3ꢀ Ω
5± Ω
33 Ω
± Ω
499 Ω
525 Ω
1 kΩ
R9, R1±, R12, R13, R2±, R35, R38, R4±, R43
R15, R1ꢀ, R18, R2ꢀ, R29, R31
R1ꢁ, R25
Resistors
Resistors
R19, R21, R2ꢁ, R28, R39, R41, R44,
R4ꢀ to R49, R52, R54, R55, R5ꢁ to Rꢀ±, Rꢀ2 to Rꢁ±
1ꢁ
18
19
2±
21
22
23
24
25
2ꢀ
2ꢁ
4
2
1
8
2
1
2
2
2
2
4
R22 to R24, R3±
R45, R5ꢀ
R5±
RZ1 to RZꢀ, RZ9, RZ1±
T1, T2
U1
U2, U425
U32, Uꢁ
U5, Uꢀ
U11, U12
Rꢀ, R8, R33, R42
Resistors
Resistors
Resistor
Resistor Pack
Transformers
AD9248
SNꢁ4LVTH1ꢀ23ꢁ4
SNꢁ4LVC1G±4
SNꢁ4VCX8ꢀ
AD8139
±4±2
±4±2
±4±2
4± Ω
1± kΩ
22 Ω
22± Ω
AWT-1WT
LFCSP-ꢀ4
TSSOP-48
SOT-ꢁ±
SO-14
Mini-Circuits®
SO-8/EP
±4±2
Resistors
1±± Ω
1 P3, P8 implemented as one 8±-pin connector SAMTEC TSW-14±-±8-L-D-RA.
2 U3, Uꢁ not placed.
Rev. B | Page 3ꢀ of 48
AD9248
LFCSP PCB SCHEMATICS
7 A D
A D 8
9 A D
7 _ D A
8 _ D A
9 _ D A
D D 2 D R V
B D 7
B D 6
B D 5
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
7 _ D B
6 _ D B
5 _ D B
3 2
3 1
3 0
D D D R V
2 9
D R G N D
2 8
D R G N D 2
1 0 D A
1 1 D A
1 2 D A
1 3 D A
T R O A
1 0 D _ A
1 1 D _ A
1 2 D _ A
1 3 D _ A
O T R _ A
O E B _ A
_ A N W P D
X _ U S M E L
E F _ R S H
B D 4
B D 3
B D 2
B D 1
B D 0
4 _ D B
2 7
2 6
2 5
2 4
2 3
3 _ D B
2 _ D B
1 _ D B
0 _ D B
O E B _ B
2 2
_ B N W P D
2 1
D F S
2 0
D C S
1 9
6 2
6 3
6 4
A
C L K _
D D A 5 V
E P A
N E C A
D V
N E C B
V D
B
C L K _
1 8
1 7
D D A 3 V
D
6 5
Figure 50. PCB Schematic (1 of 3)
Rev. B | Page 3ꢁ of 48
AD9248
Figure 51. PCB Schematic (2 of 3)
Rev. B | Page 38 of 48
AD9248
Figure 52. PCB Schematic (3 of 3)
Rev. B | Page 39 of 48
AD9248
LFCSP PCB LAYERS
Figure 53. PCB Top-Side Silkscreen
Rev. B | Page 4± of 48
AD9248
Figure 54. PCB Top-Side Copper Routing
Rev. B | Page 41 of 48
AD9248
Figure 55. PCB Ground Layer
Rev. B | Page 42 of 48
AD9248
Figure 56. PCB Split Power Plane
Rev. B | Page 43 of 48
AD9248
Figure 57. PCB Bottom-Side Copper Routing
Rev. B | Page 44 of 48
AD9248
Figure 58. PCB Bottom-Side Silkscreen
THERMAL CONSIDERATIONS
The AD9248 LFCSP has an integrated heat slug
that improves the thermal and electrical properties of the
package when locally attached to a ground plane at the PCB.
A thermal (filled) via array to a ground plane beneath the
part provides a path for heat to escape the package, lowering
junction temperature. Improved electrical performance
also results from the reduction in package parasitics due to
proximity of the ground plane. Recommended array is 0.3 mm
vias on 1.2 mm pitch. θJA = 26.4°C/W with this recommended
configuration. Soldering the slug to the PCB is a requirement
for this package.
Figure 59. Thermal Via Array
Rev. B | Page 45 of 48
AD9248
OUTLINE DIMENSIONS
9.20
0.75
0.60
0.45
9.00 SQ
8.80
1.60
MAX
64
49
1
48
PIN 1
7.20
7.00 SQ
6.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.15
0.05
16
33
SEATING
PLANE
17
32
0.08
COPLANARITY
VIEW A
0.23
0.18
0.13
0.40
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBD
Figure 60. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-1)
Dimensions shown in millimeters
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
64
49
48
1
PIN 1
INDICATOR
*
4.85
4.70 SQ
4.55
8.75
BSC SQ
TOP
VIEW
EXPOSED PAD
(BOTTOM VIEW)
0.50
33
32
16
0.40
0.30
17
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.50 BSC
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 61. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
Rev. B | Page 4ꢀ of 48
AD9248
ORDERING GUIDE
Model1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
AD9248BSTZ-20
AD9248BSTZ-40
AD9248BSTZ-65
AD9248BSTZRL-20
AD9248BSTZRL-40
AD9248BSTZRL-65
AD9248BCPZ-20
AD9248BCPZ-40
AD9248BCPZ-65
AD9248BCPZRL-20
AD9248BCPZRL-40
AD9248BCPZRL-65
AD9248BST-65EBZ
AD9248BCP-65EBZ
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Low Profile Quad Flat Package (LQFP)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board with AD9248BSTZ-65
ST-64-1
ST-64-1
ST-64-1
ST-64-1
ST-64-1
ST-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
Evaluation Board with AD9248BCPZ-65
1 Z = RoHS Compliant Part.
Rev. B | Page 47 of 48
AD9248
NOTES
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04446–0–11/10(B)
Rev. B | Page 48 of 48
相关型号：
©2020 ICPDF网 联系我们和版权申明