AD9389BBCPZ-165 [ADI]
High Performance HDMI/DVI Transmitter; 高性能HDMI / DVI发送器
| 型号： | AD9389BBCPZ-165 |
| 厂家： | 
ADI |
| 描述： | High Performance HDMI/DVI Transmitter |
| 文件： | 总12页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance
HDMI/DVI Transmitter
Preliminary Technical Data
AD9389B
FEATURES
FUNCTIONAL BLOCK DIAGRAM
INT
SCL SDA
MCL MDA
General
HDMI™/DVI transmitter compatible with HDMI v. 1.3,
DVI v. 1.0, and HDCP v. 1.2
INTERRUPT
HANDLER
HPD
2
I C
Internal key storage for HDCP
SLAVE
HDCP
CORE
Single 1.8 V power supply
Video/audio inputs accept logic levels from 1.8 V to 3.3 V
80-lead LQFP, Pb-free package
64-lead LFCSP, Pb-free package
HDCP-EDID
MICRO-
CONTROLLER
REGISTER
CONFIGURATION
LOGIC
Digital video
DDCSDA
DDCSCL
2
I C
MASTER
165 MHz operation supports all resolutions from 480i to
1080p and UXGA at 60 Hz
Programmable two-way color space converter
Supports RGB, YCbCr, and DDR
Supports ITU656-based embedded syncs
Automatic input video format timing detection (CEA-861B)
Digital audio
Supports standard S/PDIF for stereo LPCM or compressed
audio up to 192 kHz
CLK
VSYNC
HSYNC
DE
VIDEO
DATA
CAPTURE
Tx0–/Tx0+
Tx1–/Tx1+
Tx2–/Tx2+
TxC–/TxC+
COLOR
SPACE
CONVER-
SION
HDMI
Tx
CORE
4:2:2 TO
4:4:4
CONVER-
SION
D[23:0]
XOR
MASK
S/PDIF
MCLK
8-channel, uncompressed, LPCM I2S audio up to 192 kHz
Special features for easy system design
On-chip MPU with I2C® master to perform HDCP
operations and EDID reading operations
5 V tolerant I2C and HPD I/Os, no extra device needed
No audio master clock needed for supporting
S/PDIF and I2S
AUDIO
DATA
CAPTURE
2
I S[3:0]
LRCLK
SCLK
AD9389B
Figure 1.
On-chip MPU reports HDMI events through interrupts and
registers
The AD9389B supports both S/PDIF and 8-channel I2S audio.
Its high fidelity, 8-channel I2S can transmit either stereo or 7.1
surround audio at 192 kHz. The S/PDIF can carry stereo LPCM
audio or compressed audio, including DTS®, THX®, and Dolby®
Digital.
APPLICATIONS
DVD players and recorders
Digital set-top boxes
A/V receivers
Digital cameras and camcorders
HDMI repeater/splitter
The AD9389B helps reduce system design complexity and cost
by incorporating such features as an internal MPU for HDCP
operations, an I2C master for EDID reading, a single 1.8 V power
supply, and 5 V tolerance on the I2C and hot plug detect pins.
GENERAL DESCRIPTION
Fabricated in an advanced CMOS process, the AD9389B is
available in a space-saving, 64-lead LFCSP surface-mount
package, and an 80-lead LQFP surface-mount package. All
packages are available as Pb-free and are specified from −25°C
to +85°C.
The AD9389B is a 165 MHz, high definition multimedia inter-
face (HDMI) v. 1.3 transmitter. It supports HDTV formats up to
1080p, and computer graphic resolutions up to UXGA (1600 ×
1200 @ 60 Hz). With the inclusion of HDCP, the AD9389B allows
the secure transmission of protected content as specified by the
HDCP v. 1.2 protocol.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD9389B
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Design Resources ..........................................................................9
Document Conventions ...............................................................9
PCB Layout Recommendations.................................................... 10
Power Supply Bypassing............................................................ 10
Digital Inputs .............................................................................. 10
External Swing Resistor............................................................. 10
Output Signals ............................................................................ 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Explanation of Test Levels........................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Applications....................................................................................... 9
Rev. PrA | Page 2 of 12
Preliminary Technical Data
AD9389B
SPECIFICATIONS
Table 1.
Test
Parameter
Conditions
Temp Level1
Min
Typ
Max Unit
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH
Full
Full
25°C
VI
VI
V
1.4
3.5
0.7
V
V
pF
3
)
Full
Full
VI
VI
VDD − 0.1
V
V
Output Voltage, Low (VOL
)
0.4
THERMAL CHARACTERISTICS
Thermal Resistance
θJC Junction-to-Case
V
V
V
15.2
59
+25
°C/W
°C/W
°C
θJA Junction-to-Ambient
Ambient Temperature
DC SPECIFICATIONS
Input Leakage Current, IIL
Input Clamp Voltage
Full
−25
−10
+85
+10
25°C
25°C
25°C
VI
V
V
μA
V
V
−16 mA
+16 mA
−0.8
+0.8
AVCC
Differential High Level Output
Voltage
V
V
Differential Output Short-Circuit
Current
IV
10
μA
POWER SUPPLY
VDD (All) Supply Voltage
VDD Supply Voltage Noise
Power-Down Current
Full
Full
IV
V
IV
1.71
1.8
1.89
50
V
mV p-p
mA
With active video applied, 165 MHz, typical 25°C
random pattern
With active video applied, 165 MHz, typical 25°C
random pattern
With active video applied, 165 MHz, typical 25°C
random pattern
With active video applied, 165 MHz, typical 25°C
random pattern
9
2
IAVDD
IV
IV
IV
IV
VI
TBD
TBD
TBD
TBD
TBD
2
IPVDD
2
IDVDD
Transmitter Supply Current2
With active video applied, 165 MHz, typical 25°C
random pattern
mA
Transmitter Total Power
AC SPECIFICATIONS
Full
mW
CLK Frequency
25°C
25°C
Full
Full
Full
IV
IV
IV
IV
IV
VI
VI
13.5
48
80
52
2
MHz
%
ns
ns
ns
TMDS Output CLK Duty Cycle
Worst Case CLK Input Jitter
Input Data Setup Time
Input Data Hold Time
TMDS Differential Swing
1
1
800
1000 1200 mV
VSYNC and HSYNC Delay from DE
Falling Edge
1
UI3
VSYNC and HSYNC Delay to DE
Rising Edge
VI
1
UI
DE High Time
DE Low Time
25°C
25°C
VI
VI
8191 UI
138
UI
Differential Output Swing
Low-to-High Transition Time
High-to-Low Transition Time
25°C
25°C
VII
VII
75
75
490
490
ps
ps
Rev. PrA | Page 3 of 12
AD9389B
Preliminary Technical Data
Test
Temp Level1
Parameter
Conditions
Min
Typ
Max Unit
AUDIO AC TIMING
Sample Rate
I2S Cycle Time
I2S Setup Time
I2S Hold Time
I2S and S/PDIF
Full
IV
IV
IV
IV
IV
32
192
1
kHz
UI
ns
ns
μs
25°C
25°C
25°C
25°C
15
0
75
Audio Pipeline Delay
1 See Explanation of Test Levels section.
2 Using low output drive strength.
3 UI = unit interval.
Rev. PrA | Page 4 of 12
Preliminary Technical Data
AD9389B
ABSOLUTE MAXIMUM RATINGS
Table 2.
EXPLANATION OF TEST LEVELS
I.
100% production tested.
Parameter
Rating
Digital Inputs
5 V to 0.0 V
20 mA
−40°C to +85°C
−65°C to +150°C
150°C
II.
100% production tested at 25°C and sample tested at
specified temperatures.
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
III.
IV.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
V.
Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design
and characterization testing.
VII. Limits defined by HDMI specification; guaranteed by
design and characterization testing.
ESD CAUTION
Rev. PrA | Page 5 of 12
AD9389B
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
80 79 78
76 75 74 73 72
70 69 68 67 66 65 64 63 62 61
71
77
1
2
60
DVDD
D0
GND
PIN 1
INDICATOR
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GND
D15
3
DE
4
HSYNC
VSYNC
CLK
D16
5
D17
6
D18
7
S/PDIF
MCLK
D19
8
D20
2
9
I S0
D21
AD9389B
TOP VIEW
2
10
11
12
13
14
15
16
17
18
19
20
I S1
D22
(Not to Scale)
2
I S2
D23
2
I S3
MCL
MDA
SDA
SCL
SCLK
LRCLK
GND
PVDD
GND
DDCSDA
DDCSCL
GND
GND
AVDD
GND
PVDD
PVDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 2. 80-Lead LQFP Pin Configuration (Top View)
PIN 1
INDICATOR
DVDD
D0
DE
HSYNC
VSYNC
CLK
1
2
3
4
5
6
7
8
9
48 DVDD
47 D15
46 D16
45 D17
44 D18
43 D19
42 D20
41 D21
40 D22
39 D23
38 MCL
37 MDA
36 SDA
35 SCL
+
S/PDIF
MCLK
AD9389B
TOP VIEW
2
I S0
(Not to Scale)
2
I S1 10
2
I S2 11
2
I S3 12
SCLK 13
LRCLK 14
PVDD 15
PVDD 16
34 DDCSDA
33 DDCSCL
NOTES
1. GND PADDLE ON BOTTOM OF PACKAGE.
Figure 3. 64-Lead LFCSP Pin Configuration (Top View)
Rev. PrA | Page 6 of 12
Preliminary Technical Data
AD9389B
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Type1 Description
LFCSP
LQFP
2, 39 to 47,
50 to 63
2, 50 to 58,
65 to 78
D[23:0]
I
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic
levels from 1.8 V to 3.3 V.
6
3
6
3
CLK
DE
I
I
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to
3.3 V.
4
5
18
4
5
23
HSYNC
VSYNC
EXT_SWG
I
I
I
Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Sets internal reference currents. Place an 887 Ω resistor (1% tolerance)
between this pin and ground.
20
7
25
7
HPD
I
I
Hot Plug Detect Signal. This indicates to the interface whether the receiver is
connected. 1.8 V to 5.0 V CMOS logic level.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input
from a Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V
to 3.3 V.
S/PDIF
8
8
MCLK
I
I
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 ×
sampling frequency (fS), 256 × fS, 384 × fS, or 512 × fS. Supports 1.8 V to 3.3 V
CMOS logic level.
9 to 12
9 to 12
I2S[3:0]
I2S Audio Data Inputs. These represent the eight channels of audio (two per
input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V.
I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
Power-Down Control and I2C Address Selection. The I2C address and the PD
polarity are set by the PD/A0 pin state when the supplies are applied to the
AD9389B. Supports 1.8 V to 3.3 V CMOS logic level.
13
14
262
13
14
332
SCLK
LRCLK
PD/A0
I
I
I
21, 22
30, 31
27, 28
24, 25
32
27, 28
37, 38
34, 35
30, 31
40
TxC−/TxC+
Tx2−/Tx2+
Tx1−/Tx1+
Tx0−/Tx0+
INT
O
O
O
O
O
Differential Clock Output. Differential clock output at pixel clock rate; TMDS
logic level.
Differential Output Channel 2. Differential output of the red data at 10× the
pixel clock rate; TMDS logic level.
Differential Output Channel 1. Differential output of the green data at 10× the
pixel clock rate; TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10× the
pixel clock rate; TMDS logic level.
Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply
is recommended.
19, 23, 29
1, 48, 49
24, 29, 36, 41
1, 61 to 64
AVDD
DVDD
P
P
1.8 V Power Supply for TMDS Outputs.
1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power
to the digital logic and I/Os. They should be filtered and as quiet as possible.
15 to 17
16, 19 to 21
PVDD
GND
P
P
1.8 V PLL Power Supply. The most sensitive portion of the AD9389B is the
clock generation circuitry. These pins provide power to the clock PLL. The
designer should provide quiet, noise-free power to these pins.
Ground. The ground return for all circuitry on-chip. It is recommended that
the AD9389B be assembled on a single, solid ground plane with careful
attention given to ground current paths.
64, paddle
on bottom
side
15, 17, 18, 22,
26, 32, 39, 42,
43, 59, 60, 79, 80
36
35
37
38
47
46
48
49
SDA
SCL
C2
C2
C2
C2
Serial Port Data I/O. This pin serves as the serial port data I/O slave for register
access. Supports CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data Clock. This pin serves as the serial port data clock slave for
register access. Supports CMOS logic levels from 1.8 V to 3.3 V.
Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic
levels from 1.8 V to 3.3 V.
MDA
MCL
Rev. PrA | Page 7 of 12
AD9389B
Preliminary Technical Data
Pin No.
Mnemonic
Type1 Description
LFCSP
LQFP
34
45
DDCSDA
C2
Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus.
Supports a 5 V CMOS logic level.
33
44
DDCSCL
C2
Serial Port Data Clock to Receiver. This pin serves as the master clock for the
DDC bus. Supports a 5 V CMOS logic level.
1 I = input, O = output, P = power supply, C = control.
2 For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from flatpanel_apps@analog.com.
Rev. PrA | Page 8 of 12
Preliminary Technical Data
AD9389B
APPLICATIONS
DESIGN RESOURCES
DOCUMENT CONVENTIONS
Analog Devices, Inc. evaluation kits, reference design
schematics, and other support documentation are available
under the nondisclosure agreement (NDA) from
flatpanel_apps@analog.com.
In this data sheet, data is represented using the conventions
described in Table 4.
Table 4. Document Conventions
Data
Type Format
Other resources include:
0xNN Hexadecimal (Base-16) numbers are represented using
the C language notation, preceded by 0x.
0bNN Binary (Base-2) numbers are represented using the C
language notation, preceded by 0b.
EIA/CEA-861B which describes audio and video infoframes as
well as the E-EDID structure for HDMI. It is available from
Consumer Electronics Association (CEA).
NN
Decimal (Base-10) numbers are represented using no
additional prefixes or suffixes.
Bits are numbered in little endian format, that is, the
least significant bit of a byte or word is referred to as Bit 0.
The HDMI v. 1.3, a defining document for HDMI Version 1.3,
and the HDMI Compliance Test Specification Version 1.3 are
available from HDMI Licensing, LLC.
Bit
The HDCP v. 1.2 is the defining document for HDCP
Version 1.2 available from Digital Content Protection, LLC.
Rev. PrA | Page 9 of 12
AD9389B
Preliminary Technical Data
PCB LAYOUT RECOMMENDATIONS
Other Input Signals
The AD9389B is a high precision, high speed analog device. As
such, to obtain the maximum performance from the part, it is
important to have a well laid out board.
The HPD must be connected to the HDMI connector. A 10 kΩ
pull-down resistor to ground is also recommended.
POWER SUPPLY BYPASSING
The PD/A0 input pin can be connected to GND or supply
(through a resistor or a control signal). The device address and
power-down polarity are set by the state of the PD/A0 pin when
the AD9389B supplies are applied/enabled. For example, if the
PD/A0 pin is low (when the supplies are turned on), then the
device address is 0x72 and the power-down is active high. If the
PD/A0 pin is high (when the supplies are turned on), the device
address is 0x7A and the power-down is active low.
It is recommended to bypass each power supply pin with a
0.1 μF capacitor. The exception is when two or more supply
pins are adjacent to each other. For these groupings of
powers/grounds, it is necessary to have only one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the
AD9389B, as that interposes resistive vias in the path.
The SCL and SDA pins should be connected to the I2C master.
A pull-up resistor of 2 kꢀ to 1.8 V or 3.3 V is recommended.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make a
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
EXTERNAL SWING RESISTOR
The external swing resistor must be connected directly to the
EXT_SWG pin and ground. The external swing resistor must
have a value of 887 Ω ( 1% tolerance). Avoid running any high
speed ac or noisy signals next to, or close to, the EXT_SWG pin.
It is particularly important to maintain low noise and good
stability of PVDD (the PLL supply). Abrupt changes in PVDD
can result in similarly abrupt changes in sampling clock phase
and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is best practice to provide
separate regulated supplies for each of the analog circuitry
groups (AVDD and PVDD).
OUTPUT SIGNALS
TMDS Output Signals
The AD9389B has three TMDS data channels (0, 1, and 2) that
output signals up to 800 MHz as well as the TMDS output data
clock. To minimize the channel-to-channel skew, make the
trace length of these signals the same. Additionally, these traces
need to have a 50 ꢀ characteristic impedance and need to be
routed as 100 ꢀ differential pairs. Best practice recommends
routing these lines on the top PCB layer to avoid the use of vias.
It is also recommended to use a single ground plane for the
entire board. Experience has repeatedly shown that the noise
performance is the same or better with a single ground plane.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller, and long ground loops can result.
Other Output Signals (non TMDS)
DDCSCL and DDCSDA
DIGITAL INPUTS
Video and Audio Data Input Signals
The DDCSCL and DDCSDA outputs need to have a minimum
amount of capacitance loading to ensure the best signal integrity.
The DDCSCL and DDCSDA capacitance loading must be less
than 50 pF to meet the HDMI compliance specification. The
DDCSCL and DDCSDA must be connected to the HDMI
connector and a pull-up resistor to 5 V is required. The pull-up
resistor must have a value between 1.5 kΩ and 2 kΩ.
The digital inputs on the AD9389B are designed to work with
signals ranging from 1.8 V to 3.3 V logic level. Therefore, no
extra components need to be added when using 3.3 V logic.
Any noise that gets onto the clock input (labeled CLK) trace
adds jitter to the system. Therefore, minimize the video clock
input (Pin 6: CLK) trace length and do not run any digital or
other high frequency traces near it. Make sure to match the
length of the input data signals to optimize data capture,
especially for high frequency modes such as 1080p, UXGA, and
double data rate input formats.
INT Pin
The INT pin is an output that should be connected to the micro-
controller of the system. A pull-up resistor to 1.8 V or 3.3 V is
required for proper operation—the recommended value is 2 kΩ.
MCL and MDA
The MCL and MDA outputs should be connected to the
EEPROM containing the HDCP key (if HDCP is implemented).
Pull-up resistors of 2 kΩ are recommended.
Rev. PrA | Page 10 of 12
Preliminary Technical Data
OUTLINE DIMENSIONS
AD9389B
16.20
16.00 SQ
15.80
0.75
0.60
0.45
1.60
MAX
61
80
60
1
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.10 MAX
COPLANARITY
20
41
0.15
0.05
40
21
SEATING
PLANE
VIEW A
0.65
0.38
0.32
0.22
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 4. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
49
48
64
1
PIN 1
INDICATOR
+
4.85
4.70 SQ*
4.55
8.75
BSC SQ
EXPOSED PAD**
TOP
VIEW
(BOTTO M VIEW)
0.45
0.40
0.35
33
32
16
17
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
SEATING
PLANE
64 LFCSP (LEAD FRAME CHIP SCALE PACKAGE)
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
*
**Note: PAD is CONNECTED to GND
DIMENSIONS in Millimeters
Figure 5. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
Rev. PrA | Page 11 of 12
AD9389B
Preliminary Technical Data
ORDERING GUIDE
Model
Temperature Range
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
Package Description
Package Option
AD9389BBCPZ-801
AD9389BBCPZ-1651
AD9389BBSTZ-801
AD9389BBSTZ-1651
AD9389B/PCB
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
80-Lead Low Profile Quad Flat Package [LQFP]
80-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
CP-64-1
CP-64-1
ST-80-2
ST-80-2
1 Z = RoHS Compliant Part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06555-0-3/07(PrA)
Rev. PrA | Page 12 of 12
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